)]}'
{
  "commit": "3914fd62b6ded00fbea84171bb075ed0a2d72ed0",
  "tree": "cea8333f156f0e80f9a4cc23cb9c5a9823ae44a0",
  "parents": [
    "28f3f99e18bf001c254bcf184abb4d3b438497eb"
  ],
  "author": {
    "name": "roman3017",
    "email": "rbacik@hotmail.com",
    "time": "Sat Dec 24 01:46:21 2022 -0800"
  },
  "committer": {
    "name": "roman3017",
    "email": "rbacik@hotmail.com",
    "time": "Sat Dec 24 01:46:21 2022 -0800"
  },
  "message": "remove unnecessary code from fpga test\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "e3054f53c7a823b0960e5b723bc96132caca0369",
      "old_mode": 33188,
      "old_path": "verilog/rtl/fpga/fpga_pins.pcf",
      "new_id": "16d878e082cb3c8bbdb040fede45710179db1317",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga/fpga_pins.pcf"
    },
    {
      "type": "modify",
      "old_id": "08a615b013c047513fd2df982d52996dca0e442a",
      "old_mode": 33188,
      "old_path": "verilog/rtl/fpga/fpga_top.v",
      "new_id": "df4e9864a5744bbc0a81e83652d67f241f8ae9ca",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga/fpga_top.v"
    }
  ]
}