diff --git a/verilog/rtl/fpga/Makefile b/verilog/rtl/fpga/Makefile
index b29bd15..7946b02 100644
--- a/verilog/rtl/fpga/Makefile
+++ b/verilog/rtl/fpga/Makefile
@@ -69,6 +69,6 @@
 	icepack $< $@
 
 clean:
-	rm -f *.bin *.asc *.json *.out *.vcd *.rpt
+	rm -f *.bin *.asc *.json *.out *.vcd *.rpt pll.v
 
 .PHONY: all sim sint prog clean time
diff --git a/verilog/rtl/fpga/fpga_top.v b/verilog/rtl/fpga/fpga_top.v
index fa4093c..08a615b 100644
--- a/verilog/rtl/fpga/fpga_top.v
+++ b/verilog/rtl/fpga/fpga_top.v
@@ -13,7 +13,7 @@
    localparam c_UART_SPEED      = 115200;
    localparam c_CLKS_PER_BYTE   = (c_CLOCK_MHZ*1000000+c_UART_SPEED*8-1)/(c_UART_SPEED*8);
 
-   wire             clk_pll; //48MHz clock
+   wire             clk_pll;
    wire             lock;
 
    wire             dp_pu;
@@ -70,7 +70,7 @@
       .VENDORID(16'h1D50),
       .PRODUCTID(16'h6130)
    ) u_usb_cdc (
-      .clk_i(clk_pll), // 48MHz
+      .clk_i(clk_pll),
       .rstn_i(rstn),
       .app_clk_i(1'b0),