diff --git a/Makefile b/Makefile
index 491109f..a54eedb 100644
--- a/Makefile
+++ b/Makefile
@@ -15,22 +15,28 @@
 # SPDX-License-Identifier: Apache-2.0
 MAKEFLAGS+=--warn-undefined-variables
 
-CARAVEL_ROOT?=$(PWD)/caravel
+export CARAVEL_ROOT?=$(PWD)/caravel
 PRECHECK_ROOT?=${HOME}/mpw_precheck
-MCW_ROOT?=$(PWD)/mgmt_core_wrapper
+export MCW_ROOT?=$(PWD)/mgmt_core_wrapper
 SIM?=RTL
 DUMP?=OFF
 RISC_CORE ?=0
 
-export SKYWATER_COMMIT=c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
-export OPEN_PDKS_COMMIT=7519dfb04400f224f140749cda44ee7de6f5e095
-export PDK_MAGIC_COMMIT=7d601628e4e05fd17fcb80c3552dacb64e9f6e7b
-export OPENLANE_TAG=2022.02.23_02.50.41
-
 # Install lite version of caravel, (1): caravel-lite, (0): caravel
 CARAVEL_LITE?=1
 
-MPW_TAG ?= mpw-5c
+# PDK switch varient
+export PDK?=sky130A
+#export PDK?=gf180mcuC
+export PDKPATH?=$(PDK_ROOT)/$(PDK)
+
+
+
+ifeq ($(PDK),sky130A)
+	SKYWATER_COMMIT=f70d8ca46961ff92719d8870a18a076370b85f6c
+	export OPEN_PDKS_COMMIT?=0059588eebfc704681dc2368bd1d33d96281d10f
+	export OPENLANE_TAG?=2022.10.20
+	MPW_TAG ?= mpw-7g
 
 ifeq ($(CARAVEL_LITE),1)
 	CARAVEL_NAME := caravel-lite
@@ -42,8 +48,7 @@
 	CARAVEL_TAG := $(MPW_TAG)
 endif
 
-# Install caravel as submodule, (1): submodule, (0): clone
-SUBMODULE?=1
+endif
 
 #RISCV COMPLIANCE test Environment
 COREMARK_DIR   = verilog/dv/riscv_regress/dependencies/coremark
@@ -58,6 +63,36 @@
 RISCV_COMP_BRANCH =  d51259b2a949be3af02e776c39e135402675ac9b
 RISCV_TEST_BRANCH =  e30978a71921159aec38eeefd848fca4ed39a826
 
+ifeq ($(PDK),sky130B)
+	SKYWATER_COMMIT=f70d8ca46961ff92719d8870a18a076370b85f6c
+	export OPEN_PDKS_COMMIT?=0059588eebfc704681dc2368bd1d33d96281d10f
+	export OPENLANE_TAG?=2022.10.20
+	MPW_TAG ?= mpw-7g
+
+ifeq ($(CARAVEL_LITE),1)
+	CARAVEL_NAME := caravel-lite
+	CARAVEL_REPO := https://github.com/efabless/caravel-lite
+	CARAVEL_TAG := $(MPW_TAG)
+else
+	CARAVEL_NAME := caravel
+	CARAVEL_REPO := https://github.com/efabless/caravel
+	CARAVEL_TAG := $(MPW_TAG)
+endif
+
+endif
+
+ifeq ($(PDK),gf180mcuC)
+
+	MPW_TAG ?= gfmpw-0a
+	CARAVEL_NAME := caravel
+	CARAVEL_REPO := https://github.com/efabless/caravel-gf180mcu
+	CARAVEL_TAG := $(MPW_TAG)
+	#OPENLANE_TAG=ddfeab57e3e8769ea3d40dda12be0460e09bb6d9
+	export OPEN_PDKS_COMMIT?=0059588eebfc704681dc2368bd1d33d96281d10f
+	export OPENLANE_TAG?=2022.11.17
+
+endif
+
 # Include Caravel Makefile Targets
 .PHONY: % : check-caravel
 %:
@@ -78,13 +113,13 @@
 	docker pull riscduino/dv_setup:mpw6
 
 .PHONY: setup
-setup: install check-env install_mcw pdk openlane
+setup: install check-env install_mcw openlane pdk-with-volare setup-timing-scripts
 
 # Openlane
 blocks=$(shell cd openlane && find * -maxdepth 0 -type d)
 .PHONY: $(blocks)
 $(blocks): % :
-	export CARAVEL_ROOT=$(CARAVEL_ROOT) && cd openlane && $(MAKE) $*
+	$(MAKE) -C openlane $*
 
 
 PATTERNS=$(shell cd verilog/dv && find * -maxdepth 0 -type d)
@@ -111,6 +146,11 @@
 # Install Openlane
 .PHONY: openlane
 openlane:
+	@if [ "$$(realpath $${OPENLANE_ROOT})" = "$$(realpath $$(pwd)/openlane)" ]; then\
+		echo "OPENLANE_ROOT is set to '$$(pwd)/openlane' which contains openlane config files"; \
+		echo "Please set it to a different directory"; \
+		exit 1; \
+	fi
 	cd openlane && $(MAKE) openlane
 
 #### Not sure if the targets following are of any use
@@ -143,15 +183,22 @@
 # Default installs to the user home directory, override by "export PRECHECK_ROOT=<precheck-installation-path>"
 .PHONY: precheck
 precheck:
-	@git clone --depth=1 --branch mpw-5a https://github.com/efabless/mpw_precheck.git $(PRECHECK_ROOT)
+	@git clone --depth=1 --branch $(MPW_TAG) https://github.com/efabless/mpw_precheck.git $(PRECHECK_ROOT)
 	@docker pull efabless/mpw_precheck:latest
 
 .PHONY: run-precheck
 run-precheck: check-pdk check-precheck
 	$(eval INPUT_DIRECTORY := $(shell pwd))
 	cd $(PRECHECK_ROOT) && \
-	docker run -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) -v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) -v $(PDK_ROOT):$(PDK_ROOT) -e INPUT_DIRECTORY=$(INPUT_DIRECTORY) -e PDK_ROOT=$(PDK_ROOT) \
-	-u $(shell id -u $(USER)):$(shell id -g $(USER)) efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --input_directory $(INPUT_DIRECTORY) --pdk_path $(PDK_ROOT)"
+	docker run -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) \
+	-v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) \
+	-v $(PDK_ROOT):$(PDK_ROOT) \
+	-e INPUT_DIRECTORY=$(INPUT_DIRECTORY) \
+	-e PDK_PATH=$(PDK_ROOT)/$(PDK) \
+	-e PDK_ROOT=$(PDK_ROOT) \
+	-e PDKPATH=$(PDKPATH) \
+	-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
+	efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --input_directory $(INPUT_DIRECTORY) --pdk_path $(PDK_ROOT)/$(PDK)"
 
 
 
@@ -217,3 +264,66 @@
 help:
 	cd $(CARAVEL_ROOT) && $(MAKE) help
 	@$(MAKE) -pRrq -f $(lastword $(MAKEFILE_LIST)) : 2>/dev/null | awk -v RS= -F: '/^# File/,/^# Finished Make data base/ {if ($$1 !~ "^[#.]") {print $$1}}' | sort | egrep -v -e '^[^[:alnum:]]' -e '^$@$$'
+
+
+export CUP_ROOT=$(shell pwd)
+export TIMING_ROOT?=$(shell pwd)/deps/timing-scripts
+export PROJECT_ROOT=$(CUP_ROOT)
+timing-scripts-repo=https://github.com/efabless/timing-scripts.git
+
+$(TIMING_ROOT):
+	@mkdir -p $(CUP_ROOT)/deps
+	@git clone $(timing-scripts-repo) $(TIMING_ROOT)
+
+.PHONY: setup-timing-scripts
+setup-timing-scripts: $(TIMING_ROOT)
+	@( cd $(TIMING_ROOT) && git pull )
+	@#( cd $(TIMING_ROOT) && git fetch && git checkout $(MPW_TAG); )
+	@python3 -m venv ./venv 
+		. ./venv/bin/activate && \
+		python3 -m pip install --upgrade pip && \
+		python3 -m pip install -r $(TIMING_ROOT)/requirements.txt && \
+		deactivate
+
+./verilog/gl/user_project_wrapper.v:
+	$(error you don't have $@)
+
+./env/spef-mapping.tcl: 
+	@echo "run the following:"
+	@echo "make extract-parasitics"
+	@echo "make create-spef-mapping"
+	exit 1
+
+.PHONY: create-spef-mapping
+create-spef-mapping: ./verilog/gl/user_project_wrapper.v
+	@. ./venv/bin/activate && \
+		python3 $(TIMING_ROOT)/scripts/generate_spef_mapping.py \
+			-i ./verilog/gl/user_project_wrapper.v \
+			-o ./env/spef-mapping.tcl \
+			--pdk-path $(PDK_ROOT)/$(PDK) \
+			--macro-parent mprj \
+			--project-root "$(CUP_ROOT)" && \
+		deactivate
+
+.PHONY: extract-parasitics
+extract-parasitics: ./verilog/gl/user_project_wrapper.v
+	@. ./venv/bin/activate && \
+		python3 $(TIMING_ROOT)/scripts/get_macros.py \
+		-i ./verilog/gl/user_project_wrapper.v \
+		-o ./tmp-macros-list \
+		--project-root "$(CUP_ROOT)" \
+		--pdk-path $(PDK_ROOT)/$(PDK) && \
+		deactivate
+		@cat ./tmp-macros-list | cut -d " " -f2 \
+			| xargs -I % bash -c "$(MAKE) -C $(TIMING_ROOT) \
+				-f $(TIMING_ROOT)/timing.mk rcx-% || echo 'Cannot extract %. Probably no def for this macro'"
+	@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk rcx-user_project_wrapper
+	@cat ./tmp-macros-list
+	@rm ./tmp-macros-list
+	
+.PHONY: caravel-sta
+caravel-sta: ./env/spef-mapping.tcl
+	@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-typ
+	@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-fast
+	@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-slow
+	@echo "You can find results for all corners in $(CUP_ROOT)/signoff/caravel/openlane-signoff/timing/"
diff --git a/openlane/pinmux_top/base.sdc b/openlane/pinmux_top/base.sdc
index 9c22d9c..e642e15 100644
--- a/openlane/pinmux_top/base.sdc
+++ b/openlane/pinmux_top/base.sdc
@@ -7,7 +7,32 @@
 # Timing Constraints
 ###############################################################################
 create_clock -name mclk -period 10.0000 [get_ports {mclk}]
-set_propagated_clock [get_clocks {mclk}]
+create_clock -name user_clock1 -period 10.0000 [get_ports {user_clock1}]
+create_clock -name user_clock2 -period 10.0000 [get_ports {user_clock2}]
+create_clock -name int_pll_clock -period 5.0000  [get_pins {int_pll_clock}]
+create_clock -name rtc_ref_clk -period 50.0000  [get_pins {u_glbl_reg.u_rtc_ref_clkbuf.u_buf/X}]
+create_clock -name rtc_clk     -period 50.0000  [get_pins {u_glbl_reg.u_clkbuf_rtc.u_buf/X}]
+create_clock -name usb_ref_clk -period 5.0000   [get_pins {u_glbl_reg.u_usb_ref_clkbuf.u_buf/X}]
+create_clock -name dbg_ref_clk -period 10.0000 [get_pins {u_glbl_reg.u_clkbuf_dbg_ref.u_buf/X}]
+
+
+set_clock_groups \
+   -name clock_group \
+   -logically_exclusive \
+   -group [get_clocks {mclk}]\
+   -group [get_clocks {user_clock1}]\
+   -group [get_clocks {user_clock2}]\
+   -group [get_clocks {int_pll_clock}]\
+   -group [get_clocks {rtc_ref_clk}]\
+   -group [get_clocks {rtc_clk}]\
+   -group [get_clocks {usb_ref_clk}]\
+   -group [get_clocks {dbg_ref_clk}]\
+   -comment {Async Clock group}
+
+
+
+set_propagated_clock [all_clocks]
+
 
 set_clock_transition 0.1500 [all_clocks]
 set_clock_uncertainty -setup 0.5000 [all_clocks]
diff --git a/openlane/pinmux_top/config.tcl b/openlane/pinmux_top/config.tcl
index 9326c1a..960f746 100755
--- a/openlane/pinmux_top/config.tcl
+++ b/openlane/pinmux_top/config.tcl
@@ -64,6 +64,7 @@
      $::env(DESIGN_DIR)/../../verilog/rtl/ws281x/src/ws281x_reg.sv \
      $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/strap_ctrl.sv \
      $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/glbl_rst_reg.sv \
+     $::env(DESIGN_DIR)/../../verilog/rtl/dig2ana/src/dig2ana_reg.sv \
      $::env(DESIGN_DIR)/../../verilog/rtl/lib/pulse_gen_type1.sv   \
      $::env(DESIGN_DIR)/../../verilog/rtl/lib/pulse_gen_type2.sv   \
      $::env(DESIGN_DIR)/../../verilog/rtl/lib/registers.v          \
@@ -92,7 +93,7 @@
 set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
 
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 500 850"
+set ::env(DIE_AREA) "0 0 520 900"
 
 
 # If you're going to use multiple power domains, then keep this disabled.
@@ -102,7 +103,7 @@
 
 
 set ::env(PL_TIME_DRIVEN) 1
-set ::env(PL_TARGET_DENSITY) "0.37"
+set ::env(PL_TARGET_DENSITY) "0.35"
 set ::env(CELL_PAD) "8"
 #set ::env(GRT_ADJUSTMENT) {0.2}
 
@@ -131,7 +132,10 @@
 
 #set ::env(GLB_RT_MAXLAYER) 5
 set ::env(RT_MAX_LAYER) {met4}
-#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+
+#Lef 
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
 
 set ::env(DIODE_INSERTION_STRATEGY) 4
 
diff --git a/openlane/pinmux_top/pin_order.cfg b/openlane/pinmux_top/pin_order.cfg
index 116c747..a8e15ef 100644
--- a/openlane/pinmux_top/pin_order.cfg
+++ b/openlane/pinmux_top/pin_order.cfg
@@ -2,9 +2,9 @@
 #MANUAL_PLACE
 
 #S
-cpu_core_rst_n\[3\]    000 0 2
-cpu_core_rst_n\[2\]
-cpu_core_rst_n\[1\]
+cpu_core_rst_n\[3\]   000 0 2
+cpu_core_rst_n\[2\]   
+cpu_core_rst_n\[1\]   
 cpu_core_rst_n\[0\]
 cpu_intf_rst_n
 qspim_rst_n
@@ -64,82 +64,13 @@
 spis_miso
 spis_mosi
 
-cfg_strap_pad_ctrl   0100 0 4
-user_clock1
+user_clock1          0100 0 4
 user_clock2
 int_pll_clock
 xtal_clk
-e_reset_n
-p_reset_n
 s_reset_n
 rtc_clk
 usb_clk
-strap_uartm\[1\]
-strap_uartm\[0\]
-strap_sticky\[31\]
-strap_sticky\[30\]
-strap_sticky\[29\]
-strap_sticky\[28\]
-strap_sticky\[27\]
-strap_sticky\[26\]
-strap_sticky\[25\]
-strap_sticky\[24\]
-strap_sticky\[23\]
-strap_sticky\[22\]
-strap_sticky\[21\]
-strap_sticky\[20\]
-strap_sticky\[19\]
-strap_sticky\[18\]
-strap_sticky\[17\]
-strap_sticky\[16\]
-strap_sticky\[15\]
-strap_sticky\[14\]
-strap_sticky\[13\]
-strap_sticky\[12\]
-strap_sticky\[11\]
-strap_sticky\[10\]
-strap_sticky\[9\]
-strap_sticky\[8\]
-strap_sticky\[7\]
-strap_sticky\[6\]
-strap_sticky\[5\]
-strap_sticky\[4\]
-strap_sticky\[3\]
-strap_sticky\[2\]
-strap_sticky\[1\]
-strap_sticky\[0\]
-system_strap\[31\]
-system_strap\[30\]
-system_strap\[29\]
-system_strap\[28\]
-system_strap\[27\]
-system_strap\[26\]
-system_strap\[25\]
-system_strap\[24\]
-system_strap\[23\]
-system_strap\[22\]
-system_strap\[21\]
-system_strap\[20\]
-system_strap\[19\]
-system_strap\[18\]
-system_strap\[17\]
-system_strap\[16\]
-system_strap\[15\]
-system_strap\[14\]
-system_strap\[13\]
-system_strap\[12\]
-system_strap\[11\]
-system_strap\[10\]
-system_strap\[9\]
-system_strap\[8\]
-system_strap\[7\]
-system_strap\[6\]
-system_strap\[5\]
-system_strap\[4\]
-system_strap\[3\]
-system_strap\[2\]
-system_strap\[1\]
-system_strap\[0\]
 
 pinmux_debug\[0\] 0300 0  2
 pinmux_debug\[1\]
@@ -176,8 +107,80 @@
 cpu_clk
 
 #W
+strap_sticky\[31\]   000 0 2
+strap_sticky\[30\]
+strap_sticky\[29\]
+strap_sticky\[28\]
+strap_sticky\[27\]
+strap_sticky\[26\]
+strap_sticky\[25\]
+strap_sticky\[24\]
+strap_sticky\[23\]
+strap_sticky\[22\]
+strap_sticky\[21\]
+strap_sticky\[20\]
+strap_sticky\[19\]
+strap_sticky\[18\]
+strap_sticky\[17\]
+strap_sticky\[16\]
+strap_sticky\[15\]
+strap_sticky\[14\]
+strap_sticky\[13\]
+strap_sticky\[12\]
+strap_sticky\[11\]
+strap_sticky\[10\]
+strap_sticky\[9\]
+strap_sticky\[8\]
+strap_sticky\[7\]
+strap_sticky\[6\]
+strap_sticky\[5\]
+strap_sticky\[4\]
+strap_sticky\[3\]
+strap_sticky\[2\]
+strap_sticky\[1\]
+strap_sticky\[0\]
 
-soft_irq            
+strap_uartm\[1\]      
+strap_uartm\[0\]
+
+system_strap\[31\]
+system_strap\[30\]
+system_strap\[29\]
+system_strap\[28\]
+system_strap\[27\]
+system_strap\[26\]
+system_strap\[25\]
+system_strap\[24\]
+system_strap\[23\]
+system_strap\[22\]
+system_strap\[21\]
+system_strap\[20\]
+system_strap\[19\]
+system_strap\[18\]
+system_strap\[17\]
+system_strap\[16\]
+system_strap\[15\]
+system_strap\[14\]
+system_strap\[13\]
+system_strap\[12\]
+system_strap\[11\]
+system_strap\[10\]
+system_strap\[9\]
+system_strap\[8\]
+system_strap\[7\]
+system_strap\[6\]
+system_strap\[5\]
+system_strap\[4\]
+system_strap\[3\]
+system_strap\[2\]
+system_strap\[1\]
+system_strap\[0\]
+
+p_reset_n
+e_reset_n
+cfg_strap_pad_ctrl  
+
+soft_irq              200  0 2
 irq_lines\[31\]     
 irq_lines\[30\]     
 irq_lines\[29\]     
@@ -221,7 +224,7 @@
 
 
 
-reg_cs            200 0
+reg_cs            260 0  2
 reg_wr           
 reg_addr\[9\]    
 reg_addr\[8\]    
@@ -305,7 +308,44 @@
 
 
 #N
-digital_io_oen\[37\]  000 0 4
+
+cfg_dac3_mux_sel\[7\]
+cfg_dac3_mux_sel\[6\]
+cfg_dac3_mux_sel\[5\]
+cfg_dac3_mux_sel\[4\]
+cfg_dac3_mux_sel\[3\]
+cfg_dac3_mux_sel\[2\]
+cfg_dac3_mux_sel\[1\]
+cfg_dac3_mux_sel\[0\]
+
+cfg_dac2_mux_sel\[7\]
+cfg_dac2_mux_sel\[6\]
+cfg_dac2_mux_sel\[5\]
+cfg_dac2_mux_sel\[4\]
+cfg_dac2_mux_sel\[3\]
+cfg_dac2_mux_sel\[2\]
+cfg_dac2_mux_sel\[1\]
+cfg_dac2_mux_sel\[0\]
+
+cfg_dac1_mux_sel\[7\]
+cfg_dac1_mux_sel\[6\]
+cfg_dac1_mux_sel\[5\]
+cfg_dac1_mux_sel\[4\]
+cfg_dac1_mux_sel\[3\]
+cfg_dac1_mux_sel\[2\]
+cfg_dac1_mux_sel\[1\]
+cfg_dac1_mux_sel\[0\]
+
+cfg_dac0_mux_sel\[7\]
+cfg_dac0_mux_sel\[6\]
+cfg_dac0_mux_sel\[5\]
+cfg_dac0_mux_sel\[4\]
+cfg_dac0_mux_sel\[3\]
+cfg_dac0_mux_sel\[2\]
+cfg_dac0_mux_sel\[1\]
+cfg_dac0_mux_sel\[0\]
+
+digital_io_oen\[37\]  100 0 4
 digital_io_out\[37\]
 digital_io_in\[37\]
 digital_io_oen\[36\]
diff --git a/openlane/qspim_top/config.tcl b/openlane/qspim_top/config.tcl
index c376278..8e17a61 100755
--- a/openlane/qspim_top/config.tcl
+++ b/openlane/qspim_top/config.tcl
@@ -95,6 +95,11 @@
 
 #set ::env(GLB_RT_MAXLAYER) 5
 set ::env(RT_MAX_LAYER) {met4}
+
+#Lef 
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+
 #set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
 set ::env(DIODE_INSERTION_STRATEGY) 4
 
diff --git a/openlane/qspim_top/pin_order.cfg b/openlane/qspim_top/pin_order.cfg
index 9f93b81..c078759 100644
--- a/openlane/qspim_top/pin_order.cfg
+++ b/openlane/qspim_top/pin_order.cfg
@@ -55,7 +55,7 @@
 
 
 #W
-cfg_cska_sp_co\[3\]   0000 0 2
+cfg_cska_sp_co\[3\]   0200 0 2
 cfg_cska_sp_co\[2\]
 cfg_cska_sp_co\[1\]
 cfg_cska_sp_co\[0\]
@@ -67,7 +67,7 @@
 wbd_clk_spi
 mclk                   
 
-wbd_stb_i              0100 0 2
+wbd_stb_i              0300 0 2
 wbd_we_i               
 wbd_adr_i\[31\]        
 wbd_adr_i\[30\]        
diff --git a/openlane/uart_i2cm_usb_spi_top/config.tcl b/openlane/uart_i2cm_usb_spi_top/config.tcl
index 9870805..7576c81 100644
--- a/openlane/uart_i2cm_usb_spi_top/config.tcl
+++ b/openlane/uart_i2cm_usb_spi_top/config.tcl
@@ -118,6 +118,11 @@
 
 #set ::env(GLB_RT_MAXLAYER) 5
 set ::env(RT_MAX_LAYER) {met4}
+
+#Lef 
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+
 #set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
 set ::env(DIODE_INSERTION_STRATEGY) 4
 
diff --git a/openlane/uart_i2cm_usb_spi_top/pin_order.cfg b/openlane/uart_i2cm_usb_spi_top/pin_order.cfg
index aba1684..2801070 100644
--- a/openlane/uart_i2cm_usb_spi_top/pin_order.cfg
+++ b/openlane/uart_i2cm_usb_spi_top/pin_order.cfg
@@ -2,7 +2,7 @@
 #MANUAL_PLACE
 
 #W
-cfg_cska_uart\[3\]     0000 0  2
+cfg_cska_uart\[3\]     0200 0  2
 cfg_cska_uart\[2\]
 cfg_cska_uart\[1\]
 cfg_cska_uart\[0\]
@@ -10,7 +10,7 @@
 wbd_clk_uart
 app_clk                
 
-reg_cs                 0100 0  2
+reg_cs                 0300 0  2
 reg_wr                 
 reg_addr\[8\]          
 reg_addr\[7\]          
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 7e004cb..60d31ef 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -73,8 +73,9 @@
 	$::env(DESIGN_DIR)/../../verilog/gl/ycr_intf.v \
 	$::env(DESIGN_DIR)/../../verilog/gl/ycr_core_top.v \
 	$::env(DESIGN_DIR)/../../verilog/gl/ycr4_iconnect.v \
-	$::env(DESIGN_DIR)/../../verilog/gl/digital_pll.v \
-	$::env(PDK_ROOT)/sky130B/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \
+	$::env(DESIGN_DIR)/../../verilog/gl/dg_pll.v \
+	$::env(DESIGN_DIR)/../../verilog/gl/dac_top.v \
+	$::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \
 	"
 
 set ::env(EXTRA_LEFS) "\
@@ -86,8 +87,9 @@
 	$lef_root/ycr_intf.lef \
 	$lef_root/ycr_core_top.lef \
 	$lef_root/ycr4_iconnect.lef \
-	$lef_root/digital_pll.lef \
-	$::env(PDK_ROOT)/sky130B/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef \
+	$lef_root/dg_pll.lef \
+	$::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef \
+	$lef_root/dac_top.lef \
 	"
 
 set ::env(EXTRA_GDS_FILES) "\
@@ -99,8 +101,9 @@
 	$gds_root/ycr_intf.gds \
 	$gds_root/ycr_core_top.gds \
 	$gds_root/ycr4_iconnect.gds \
-	$gds_root/digital_pll.gds \
-	$::env(PDK_ROOT)/sky130B/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds \
+	$gds_root/dg_pll.gds \
+	$gds_root/dac_top.gds \
+	$::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds \
 	"
 
 set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
@@ -121,13 +124,13 @@
 set ::env(FP_PDN_HORIZONTAL_HALO) "10"
 set ::env(FP_PDN_VERTICAL_HALO) "10"
 set ::env(FP_PDN_VOFFSET) "5"
-set ::env(FP_PDN_VPITCH) "60"
+set ::env(FP_PDN_VPITCH) "80"
 set ::env(FP_PDN_HOFFSET) "5"
-set ::env(FP_PDN_HPITCH) "60"
+set ::env(FP_PDN_HPITCH) "80"
 set ::env(FP_PDN_HWIDTH) {6.2}
 set ::env(FP_PDN_VWIDTH) {6.2}
-set ::env(FP_PDN_HSPACING) {20}
-set ::env(FP_PDN_VSPACING) {20}
+set ::env(FP_PDN_HSPACING) {13.8}
+set ::env(FP_PDN_VSPACING) {13.8}
 
 set ::env(VDD_NETS) {vccd1 vccd2 vdda1 vdda2}
 set ::env(GND_NETS) {vssd1 vssd2 vssa1 vssa2}
@@ -136,6 +139,7 @@
 set ::env(VDD_PIN) {vccd1}
 set ::env(GND_PIN) {vssd1}
 
+set ::env(PDN_STRIPE) {vccd1 vdda1 vssd1 vssa1}
 set ::env(DRT_OPT_ITERS) {32}
 
 set ::env(GRT_OBS) "                              \
@@ -170,7 +174,8 @@
 	u_riscv_top.i_core_top_2    vccd1 vssd1 vccd1 vssd1, \
 	u_riscv_top.i_core_top_3    vccd1 vssd1 vccd1 vssd1, \
 	u_riscv_top.u_connect       vccd1 vssd1 VPWR  VGND, \
-	u_riscv_top.u_intf          vccd1 vssd1 vccd1 vssd1 \
+	u_riscv_top.u_intf          vccd1 vssd1 vccd1 vssd1, \
+	u_4x8bit_dac                vdda1 vssa1 vccd1 vssd1
       	"
 
 
@@ -183,8 +188,8 @@
 set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
 set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
 set ::env(DIODE_INSERTION_STRATEGY) 0
-set ::env(FILL_INSERTION) 0
-set ::env(TAP_DECAP_INSERTION) 0
+set ::env(RUN_FILL_INSERTION) 0
+set ::env(RUN_TAP_DECAP_INSERTION) 0
 set ::env(CLOCK_TREE_SYNTH) 0
 set ::env(QUIT_ON_LVS_ERROR) "1"
 set ::env(QUIT_ON_MAGIC_DRC) "0"
diff --git a/openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper.def b/openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper.def
index 7bf40c0..0647d54 100644
--- a/openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper.def
+++ b/openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper.def
@@ -1308,9 +1308,6 @@
     - via4_3100x3100 + VIARULE M4M5_PR + CUTSIZE 800 800  + LAYERS met4 via4 met5  + CUTSPACING 800 800  + ENCLOSURE 350 350 350 350  + ROWCOL 2 2  ;
     - via4_1600x3100 + VIARULE M4M5_PR + CUTSIZE 800 800  + LAYERS met4 via4 met5  + CUTSPACING 800 800  + ENCLOSURE 400 350 400 350  + ROWCOL 2 1  ;
 END VIAS
-COMPONENTS 1 ;
-    - mprj user_proj_example + FIXED ( 1175000 1690000 ) N ;
-END COMPONENTS
 PINS 645 ;
     - analog_io[0] + NET analog_io[0] + DIRECTION INOUT + USE SIGNAL
       + PORT
@@ -7656,6841 +7653,4 @@
       NEW met4 3100 + SHAPE STRIPE ( 1379120 -19070 ) ( 1379120 1680000 )
       NEW met4 3100 + SHAPE STRIPE ( 1199120 -19070 ) ( 1199120 1680000 ) ;
 END SPECIALNETS
-NETS 637 ;
-    - analog_io[0] ( PIN analog_io[0] ) + USE SIGNAL ;
-    - analog_io[10] ( PIN analog_io[10] ) + USE SIGNAL ;
-    - analog_io[11] ( PIN analog_io[11] ) + USE SIGNAL ;
-    - analog_io[12] ( PIN analog_io[12] ) + USE SIGNAL ;
-    - analog_io[13] ( PIN analog_io[13] ) + USE SIGNAL ;
-    - analog_io[14] ( PIN analog_io[14] ) + USE SIGNAL ;
-    - analog_io[15] ( PIN analog_io[15] ) + USE SIGNAL ;
-    - analog_io[16] ( PIN analog_io[16] ) + USE SIGNAL ;
-    - analog_io[17] ( PIN analog_io[17] ) + USE SIGNAL ;
-    - analog_io[18] ( PIN analog_io[18] ) + USE SIGNAL ;
-    - analog_io[19] ( PIN analog_io[19] ) + USE SIGNAL ;
-    - analog_io[1] ( PIN analog_io[1] ) + USE SIGNAL ;
-    - analog_io[20] ( PIN analog_io[20] ) + USE SIGNAL ;
-    - analog_io[21] ( PIN analog_io[21] ) + USE SIGNAL ;
-    - analog_io[22] ( PIN analog_io[22] ) + USE SIGNAL ;
-    - analog_io[23] ( PIN analog_io[23] ) + USE SIGNAL ;
-    - analog_io[24] ( PIN analog_io[24] ) + USE SIGNAL ;
-    - analog_io[25] ( PIN analog_io[25] ) + USE SIGNAL ;
-    - analog_io[26] ( PIN analog_io[26] ) + USE SIGNAL ;
-    - analog_io[27] ( PIN analog_io[27] ) + USE SIGNAL ;
-    - analog_io[28] ( PIN analog_io[28] ) + USE SIGNAL ;
-    - analog_io[2] ( PIN analog_io[2] ) + USE SIGNAL ;
-    - analog_io[3] ( PIN analog_io[3] ) + USE SIGNAL ;
-    - analog_io[4] ( PIN analog_io[4] ) + USE SIGNAL ;
-    - analog_io[5] ( PIN analog_io[5] ) + USE SIGNAL ;
-    - analog_io[6] ( PIN analog_io[6] ) + USE SIGNAL ;
-    - analog_io[7] ( PIN analog_io[7] ) + USE SIGNAL ;
-    - analog_io[8] ( PIN analog_io[8] ) + USE SIGNAL ;
-    - analog_io[9] ( PIN analog_io[9] ) + USE SIGNAL ;
-    - io_in[0] ( PIN io_in[0] ) ( mprj io_in[0] ) + USE SIGNAL
-      + ROUTED met2 ( 2900990 32980 ) ( * 34170 )
-      NEW met3 ( 2900990 32980 ) ( 2917780 * 0 )
-      NEW met2 ( 1178980 2289900 0 ) ( 1179670 * )
-      NEW met2 ( 1179670 2289900 ) ( * 2300100 )
-      NEW met1 ( 2080350 34170 ) ( 2900990 * )
-      NEW met2 ( 2080350 34170 ) ( * 2300100 )
-      NEW met3 ( 1179670 2300100 ) ( 2080350 * )
-      NEW met1 ( 2900990 34170 ) M1M2_PR
-      NEW met2 ( 2900990 32980 ) M2M3_PR
-      NEW met2 ( 1179670 2300100 ) M2M3_PR
-      NEW met1 ( 2080350 34170 ) M1M2_PR
-      NEW met2 ( 2080350 2300100 ) M2M3_PR ;
-    - io_in[10] ( PIN io_in[10] ) ( mprj io_in[10] ) + USE SIGNAL
-      + ROUTED met2 ( 2900990 2290580 ) ( * 2293810 )
-      NEW met3 ( 2900990 2290580 ) ( 2917780 * 0 )
-      NEW met2 ( 1415880 2289900 0 ) ( 1417490 * )
-      NEW met2 ( 1417490 2289900 ) ( * 2293810 )
-      NEW met1 ( 1417490 2293810 ) ( 2900990 * )
-      NEW met1 ( 2900990 2293810 ) M1M2_PR
-      NEW met2 ( 2900990 2290580 ) M2M3_PR
-      NEW met1 ( 1417490 2293810 ) M1M2_PR ;
-    - io_in[11] ( PIN io_in[11] ) ( mprj io_in[11] ) + USE SIGNAL
-      + ROUTED met2 ( 1437270 2289900 ) ( 1439340 * 0 )
-      NEW met2 ( 1435430 2401200 ) ( 1437270 * )
-      NEW met2 ( 1437270 2289900 ) ( * 2401200 )
-      NEW met2 ( 1435430 2401200 ) ( * 2553230 )
-      NEW met2 ( 2900990 2553230 ) ( * 2556460 )
-      NEW met3 ( 2900990 2556460 ) ( 2917780 * 0 )
-      NEW met1 ( 1435430 2553230 ) ( 2900990 * )
-      NEW met1 ( 1435430 2553230 ) M1M2_PR
-      NEW met1 ( 2900990 2553230 ) M1M2_PR
-      NEW met2 ( 2900990 2556460 ) M2M3_PR ;
-    - io_in[12] ( PIN io_in[12] ) ( mprj io_in[12] ) + USE SIGNAL
-      + ROUTED met2 ( 2899150 2815370 ) ( * 2821660 )
-      NEW met3 ( 2899150 2821660 ) ( 2917780 * 0 )
-      NEW met2 ( 1463030 2289900 ) ( 1463260 * 0 )
-      NEW met2 ( 1463030 2289900 ) ( * 2815370 )
-      NEW met1 ( 1463030 2815370 ) ( 2899150 * )
-      NEW met1 ( 1463030 2815370 ) M1M2_PR
-      NEW met1 ( 2899150 2815370 ) M1M2_PR
-      NEW met2 ( 2899150 2821660 ) M2M3_PR ;
-    - io_in[13] ( PIN io_in[13] ) ( mprj io_in[13] ) + USE SIGNAL
-      + ROUTED met2 ( 2900990 3084310 ) ( * 3087540 )
-      NEW met3 ( 2900990 3087540 ) ( 2917780 * 0 )
-      NEW met1 ( 1483730 3084310 ) ( 2900990 * )
-      NEW met2 ( 1484650 2289900 ) ( 1486720 * 0 )
-      NEW met2 ( 1483730 2401200 ) ( 1484650 * )
-      NEW met2 ( 1484650 2289900 ) ( * 2401200 )
-      NEW met2 ( 1483730 2401200 ) ( * 3084310 )
-      NEW met1 ( 2900990 3084310 ) M1M2_PR
-      NEW met2 ( 2900990 3087540 ) M2M3_PR
-      NEW met1 ( 1483730 3084310 ) M1M2_PR ;
-    - io_in[14] ( PIN io_in[14] ) ( mprj io_in[14] ) + USE SIGNAL
-      + ROUTED met2 ( 2900990 3353420 ) ( * 3353930 )
-      NEW met3 ( 2900990 3353420 ) ( 2917780 * 0 )
-      NEW met2 ( 1508570 2289900 ) ( 1510640 * 0 )
-      NEW met2 ( 1504430 2401200 ) ( 1508570 * )
-      NEW met2 ( 1508570 2289900 ) ( * 2401200 )
-      NEW met2 ( 1504430 2401200 ) ( * 3353930 )
-      NEW met1 ( 1504430 3353930 ) ( 2900990 * )
-      NEW met1 ( 2900990 3353930 ) M1M2_PR
-      NEW met2 ( 2900990 3353420 ) M2M3_PR
-      NEW met1 ( 1504430 3353930 ) M1M2_PR ;
-    - io_in[15] ( PIN io_in[15] ) ( mprj io_in[15] ) + USE SIGNAL
-      + ROUTED met2 ( 1534100 2289900 0 ) ( 1535710 * )
-      NEW met2 ( 1535710 2289900 ) ( * 2308430 )
-      NEW met2 ( 2794730 2308430 ) ( * 3512100 )
-      NEW met2 ( 2794730 3512100 ) ( 2798410 * )
-      NEW met2 ( 2798410 3512100 ) ( * 3517980 0 )
-      NEW met1 ( 1535710 2308430 ) ( 2794730 * )
-      NEW met1 ( 1535710 2308430 ) M1M2_PR
-      NEW met1 ( 2794730 2308430 ) M1M2_PR ;
-    - io_in[16] ( PIN io_in[16] ) ( mprj io_in[16] ) + USE SIGNAL
-      + ROUTED met2 ( 1558020 2289900 0 ) ( 1559170 * )
-      NEW met2 ( 1559170 2289900 ) ( * 2309450 )
-      NEW met2 ( 2470430 3517980 ) ( 2473190 * )
-      NEW met2 ( 2473190 3517300 ) ( * 3517980 )
-      NEW met2 ( 2473190 3517300 ) ( 2474110 * )
-      NEW met2 ( 2474110 3517300 ) ( * 3517980 0 )
-      NEW met2 ( 2470430 2309450 ) ( * 3517980 )
-      NEW met1 ( 1559170 2309450 ) ( 2470430 * )
-      NEW met1 ( 1559170 2309450 ) M1M2_PR
-      NEW met1 ( 2470430 2309450 ) M1M2_PR ;
-    - io_in[17] ( PIN io_in[17] ) ( mprj io_in[17] ) + USE SIGNAL
-      + ROUTED met2 ( 2146130 3517980 ) ( 2148430 * )
-      NEW met2 ( 2148430 3517300 ) ( * 3517980 )
-      NEW met2 ( 2148430 3517300 ) ( 2149350 * )
-      NEW met2 ( 2149350 3517300 ) ( * 3517980 0 )
-      NEW met2 ( 2146130 2310130 ) ( * 3517980 )
-      NEW met2 ( 1581480 2289900 0 ) ( 1583090 * )
-      NEW met2 ( 1583090 2289900 ) ( * 2310130 )
-      NEW met1 ( 1583090 2310130 ) ( 2146130 * )
-      NEW met1 ( 2146130 2310130 ) M1M2_PR
-      NEW met1 ( 1583090 2310130 ) M1M2_PR ;
-    - io_in[18] ( PIN io_in[18] ) ( mprj io_in[18] ) + USE SIGNAL
-      + ROUTED met2 ( 1821830 3512100 ) ( 1825050 * )
-      NEW met2 ( 1825050 3512100 ) ( * 3517980 0 )
-      NEW met2 ( 1605400 2289900 0 ) ( 1607010 * )
-      NEW met2 ( 1607010 2289900 ) ( * 2311150 )
-      NEW met1 ( 1607010 2311150 ) ( 1821830 * )
-      NEW met2 ( 1821830 2311150 ) ( * 3512100 )
-      NEW met1 ( 1607010 2311150 ) M1M2_PR
-      NEW met1 ( 1821830 2311150 ) M1M2_PR ;
-    - io_in[19] ( PIN io_in[19] ) ( mprj io_in[19] ) + USE SIGNAL
-      + ROUTED met2 ( 1628630 2289900 ) ( 1628860 * 0 )
-      NEW met2 ( 1628630 2289900 ) ( * 2311490 )
-      NEW met1 ( 1497530 2311490 ) ( 1628630 * )
-      NEW met2 ( 1497530 3517980 ) ( 1499830 * )
-      NEW met2 ( 1499830 3517300 ) ( * 3517980 )
-      NEW met2 ( 1499830 3517300 ) ( 1500750 * )
-      NEW met2 ( 1500750 3517300 ) ( * 3517980 0 )
-      NEW met2 ( 1497530 2311490 ) ( * 3517980 )
-      NEW met1 ( 1628630 2311490 ) M1M2_PR
-      NEW met1 ( 1497530 2311490 ) M1M2_PR ;
-    - io_in[1] ( PIN io_in[1] ) ( mprj io_in[1] ) + USE SIGNAL
-      + ROUTED met3 ( 2902140 231540 ) ( 2917780 * 0 )
-      NEW met4 ( 2902140 231540 ) ( * 2299420 )
-      NEW met2 ( 1202440 2289900 0 ) ( 1204050 * )
-      NEW met2 ( 1204050 2289900 ) ( * 2299420 )
-      NEW met3 ( 1204050 2299420 ) ( 2902140 * )
-      NEW met3 ( 2902140 231540 ) M3M4_PR
-      NEW met3 ( 2902140 2299420 ) M3M4_PR
-      NEW met2 ( 1204050 2299420 ) M2M3_PR ;
-    - io_in[20] ( PIN io_in[20] ) ( mprj io_in[20] ) + USE SIGNAL
-      + ROUTED met2 ( 1173230 3517980 ) ( 1175070 * )
-      NEW met2 ( 1175070 3517300 ) ( * 3517980 )
-      NEW met2 ( 1175070 3517300 ) ( 1175990 * )
-      NEW met2 ( 1175990 3517300 ) ( * 3517980 0 )
-      NEW met2 ( 1173230 2310470 ) ( * 3517980 )
-      NEW met2 ( 1651170 2289900 ) ( 1652780 * 0 )
-      NEW met2 ( 1651170 2289900 ) ( * 2310470 )
-      NEW met1 ( 1173230 2310470 ) ( 1651170 * )
-      NEW met1 ( 1173230 2310470 ) M1M2_PR
-      NEW met1 ( 1651170 2310470 ) M1M2_PR ;
-    - io_in[21] ( PIN io_in[21] ) ( mprj io_in[21] ) + USE SIGNAL
-      + ROUTED met2 ( 1674630 2289900 ) ( 1676240 * 0 )
-      NEW met2 ( 1674630 2289900 ) ( * 2309790 )
-      NEW met1 ( 848930 2309790 ) ( 1674630 * )
-      NEW met2 ( 848930 2309790 ) ( * 3512100 )
-      NEW met2 ( 848930 3512100 ) ( 851690 * )
-      NEW met2 ( 851690 3512100 ) ( * 3517980 0 )
-      NEW met1 ( 1674630 2309790 ) M1M2_PR
-      NEW met1 ( 848930 2309790 ) M1M2_PR ;
-    - io_in[22] ( PIN io_in[22] ) ( mprj io_in[22] ) + USE SIGNAL
-      + ROUTED met1 ( 524630 2308770 ) ( 1698550 * )
-      NEW met2 ( 524630 3517980 ) ( 526470 * )
-      NEW met2 ( 526470 3517300 ) ( * 3517980 )
-      NEW met2 ( 526470 3517300 ) ( 527390 * )
-      NEW met2 ( 527390 3517300 ) ( * 3517980 0 )
-      NEW met2 ( 524630 2308770 ) ( * 3517980 )
-      NEW met2 ( 1698550 2289900 ) ( 1700160 * 0 )
-      NEW met2 ( 1698550 2289900 ) ( * 2308770 )
-      NEW met1 ( 524630 2308770 ) M1M2_PR
-      NEW met1 ( 1698550 2308770 ) M1M2_PR ;
-    - io_in[23] ( PIN io_in[23] ) ( mprj io_in[23] ) + USE SIGNAL
-      + ROUTED met2 ( 200330 3517980 ) ( 201710 * )
-      NEW met2 ( 201710 3517300 ) ( * 3517980 )
-      NEW met2 ( 201710 3517300 ) ( 202630 * )
-      NEW met2 ( 202630 3517300 ) ( * 3517980 0 )
-      NEW met2 ( 200330 2308090 ) ( * 3517980 )
-      NEW met1 ( 200330 2308090 ) ( 1722010 * )
-      NEW met2 ( 1722010 2289900 ) ( 1723620 * 0 )
-      NEW met2 ( 1722010 2289900 ) ( * 2308090 )
-      NEW met1 ( 200330 2308090 ) M1M2_PR
-      NEW met1 ( 1722010 2308090 ) M1M2_PR ;
-    - io_in[24] ( PIN io_in[24] ) ( mprj io_in[24] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 3421420 0 ) ( 17250 * )
-      NEW met2 ( 17250 3415810 ) ( * 3421420 )
-      NEW met1 ( 17250 3415810 ) ( 1745930 * )
-      NEW met2 ( 1745930 2289900 ) ( 1747540 * 0 )
-      NEW met2 ( 1745930 2289900 ) ( * 3415810 )
-      NEW met2 ( 17250 3421420 ) M2M3_PR
-      NEW met1 ( 17250 3415810 ) M1M2_PR
-      NEW met1 ( 1745930 3415810 ) M1M2_PR ;
-    - io_in[25] ( PIN io_in[25] ) ( mprj io_in[25] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 3160300 0 ) ( 17250 * )
-      NEW met2 ( 17250 3160300 ) ( * 3160470 )
-      NEW met2 ( 1766630 2401200 ) ( 1768930 * )
-      NEW met2 ( 1766630 2401200 ) ( * 3160470 )
-      NEW met1 ( 17250 3160470 ) ( 1766630 * )
-      NEW met2 ( 1768930 2289900 ) ( 1771000 * 0 )
-      NEW met2 ( 1768930 2289900 ) ( * 2401200 )
-      NEW met2 ( 17250 3160300 ) M2M3_PR
-      NEW met1 ( 17250 3160470 ) M1M2_PR
-      NEW met1 ( 1766630 3160470 ) M1M2_PR ;
-    - io_in[26] ( PIN io_in[26] ) ( mprj io_in[26] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 2899860 0 ) ( 16790 * )
-      NEW met2 ( 16790 2898330 ) ( * 2899860 )
-      NEW met1 ( 16790 2898330 ) ( 1794230 * )
-      NEW met2 ( 1794230 2289900 ) ( 1794920 * 0 )
-      NEW met2 ( 1794230 2289900 ) ( * 2898330 )
-      NEW met2 ( 16790 2899860 ) M2M3_PR
-      NEW met1 ( 16790 2898330 ) M1M2_PR
-      NEW met1 ( 1794230 2898330 ) M1M2_PR ;
-    - io_in[27] ( PIN io_in[27] ) ( mprj io_in[27] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 2639420 0 ) ( 17250 * )
-      NEW met2 ( 17250 2635850 ) ( * 2639420 )
-      NEW met1 ( 17250 2635850 ) ( 1814930 * )
-      NEW met2 ( 1814930 2401200 ) ( 1816310 * )
-      NEW met2 ( 1814930 2401200 ) ( * 2635850 )
-      NEW met2 ( 1816310 2289900 ) ( 1818380 * 0 )
-      NEW met2 ( 1816310 2289900 ) ( * 2401200 )
-      NEW met2 ( 17250 2639420 ) M2M3_PR
-      NEW met1 ( 17250 2635850 ) M1M2_PR
-      NEW met1 ( 1814930 2635850 ) M1M2_PR ;
-    - io_in[28] ( PIN io_in[28] ) ( mprj io_in[28] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 2378300 0 ) ( 17250 * )
-      NEW met2 ( 17250 2373710 ) ( * 2378300 )
-      NEW met1 ( 17250 2373710 ) ( 1840230 * )
-      NEW met2 ( 1840230 2289900 ) ( 1842300 * 0 )
-      NEW met2 ( 1840230 2289900 ) ( * 2373710 )
-      NEW met2 ( 17250 2378300 ) M2M3_PR
-      NEW met1 ( 17250 2373710 ) M1M2_PR
-      NEW met1 ( 1840230 2373710 ) M1M2_PR ;
-    - io_in[29] ( PIN io_in[29] ) ( mprj io_in[29] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 2117860 0 ) ( 20010 * )
-      NEW met2 ( 20010 2117860 ) ( * 2291430 )
-      NEW met2 ( 1864150 2289900 ) ( 1865760 * 0 )
-      NEW met2 ( 1864150 2289900 ) ( * 2291430 )
-      NEW met1 ( 20010 2291430 ) ( 1864150 * )
-      NEW met2 ( 20010 2117860 ) M2M3_PR
-      NEW met1 ( 20010 2291430 ) M1M2_PR
-      NEW met1 ( 1864150 2291430 ) M1M2_PR ;
-    - io_in[2] ( PIN io_in[2] ) ( mprj io_in[2] ) + USE SIGNAL
-      + ROUTED met3 ( 2901910 430780 ) ( 2917780 * 0 )
-      NEW met2 ( 2901910 430780 ) ( * 2298910 )
-      NEW met2 ( 1226360 2289900 0 ) ( 1227970 * )
-      NEW met2 ( 1227970 2289900 ) ( * 2298910 )
-      NEW met1 ( 1227970 2298910 ) ( 2901910 * )
-      NEW met2 ( 2901910 430780 ) M2M3_PR
-      NEW met1 ( 2901910 2298910 ) M1M2_PR
-      NEW met1 ( 1227970 2298910 ) M1M2_PR ;
-    - io_in[30] ( PIN io_in[30] ) ( mprj io_in[30] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 1856740 0 ) ( 18630 * )
-      NEW met2 ( 18630 1856740 ) ( * 2291090 )
-      NEW met2 ( 1889680 2289900 0 ) ( * 2291090 )
-      NEW met1 ( 18630 2291090 ) ( 1889680 * )
-      NEW met2 ( 18630 1856740 ) M2M3_PR
-      NEW met1 ( 18630 2291090 ) M1M2_PR
-      NEW met1 ( 1889680 2291090 ) M1M2_PR ;
-    - io_in[31] ( PIN io_in[31] ) ( mprj io_in[31] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 1596300 0 ) ( 17710 * )
-      NEW met2 ( 17710 1596300 ) ( * 1600550 )
-      NEW met2 ( 1168630 1600550 ) ( * 2301290 )
-      NEW met1 ( 17710 1600550 ) ( 1168630 * )
-      NEW met2 ( 1911530 2289900 ) ( 1913140 * 0 )
-      NEW met2 ( 1911530 2289900 ) ( * 2301290 )
-      NEW met1 ( 1168630 2301290 ) ( 1911530 * )
-      NEW met2 ( 17710 1596300 ) M2M3_PR
-      NEW met1 ( 17710 1600550 ) M1M2_PR
-      NEW met1 ( 1168630 1600550 ) M1M2_PR
-      NEW met1 ( 1168630 2301290 ) M1M2_PR
-      NEW met1 ( 1911530 2301290 ) M1M2_PR ;
-    - io_in[32] ( PIN io_in[32] ) ( mprj io_in[32] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 1335860 0 ) ( 17710 * )
-      NEW met2 ( 17710 1335860 ) ( * 1338410 )
-      NEW met2 ( 1172770 1338410 ) ( * 2300610 )
-      NEW met2 ( 1935450 2289900 ) ( 1937060 * 0 )
-      NEW met2 ( 1935450 2289900 ) ( * 2300610 )
-      NEW met1 ( 17710 1338410 ) ( 1172770 * )
-      NEW met1 ( 1172770 2300610 ) ( 1935450 * )
-      NEW met2 ( 17710 1335860 ) M2M3_PR
-      NEW met1 ( 17710 1338410 ) M1M2_PR
-      NEW met1 ( 1172770 1338410 ) M1M2_PR
-      NEW met1 ( 1172770 2300610 ) M1M2_PR
-      NEW met1 ( 1935450 2300610 ) M1M2_PR ;
-    - io_in[33] ( PIN io_in[33] ) ( mprj io_in[33] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 1074740 0 ) ( 16790 * )
-      NEW met2 ( 16790 1074740 ) ( * 1076270 )
-      NEW met2 ( 1171850 1076270 ) ( * 2300270 )
-      NEW met2 ( 1959830 2289900 ) ( 1960520 * 0 )
-      NEW met2 ( 1959830 2289900 ) ( * 2300270 )
-      NEW met1 ( 16790 1076270 ) ( 1171850 * )
-      NEW met1 ( 1171850 2300270 ) ( 1959830 * )
-      NEW met2 ( 16790 1074740 ) M2M3_PR
-      NEW met1 ( 16790 1076270 ) M1M2_PR
-      NEW met1 ( 1171850 1076270 ) M1M2_PR
-      NEW met1 ( 1171850 2300270 ) M1M2_PR
-      NEW met1 ( 1959830 2300270 ) M1M2_PR ;
-    - io_in[34] ( PIN io_in[34] ) ( mprj io_in[34] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 814300 0 ) ( 16330 * )
-      NEW met2 ( 16330 814300 ) ( * 820930 )
-      NEW met2 ( 1170930 820930 ) ( * 2299590 )
-      NEW met1 ( 16330 820930 ) ( 1170930 * )
-      NEW met2 ( 1982830 2289900 ) ( 1984440 * 0 )
-      NEW met2 ( 1982830 2289900 ) ( * 2299590 )
-      NEW met1 ( 1170930 2299590 ) ( 1982830 * )
-      NEW met2 ( 16330 814300 ) M2M3_PR
-      NEW met1 ( 16330 820930 ) M1M2_PR
-      NEW met1 ( 1170930 820930 ) M1M2_PR
-      NEW met1 ( 1170930 2299590 ) M1M2_PR
-      NEW met1 ( 1982830 2299590 ) M1M2_PR ;
-    - io_in[35] ( PIN io_in[35] ) ( mprj io_in[35] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 553180 0 ) ( 15870 * )
-      NEW met2 ( 15870 553180 ) ( * 558790 )
-      NEW met2 ( 1170010 558790 ) ( * 2299250 )
-      NEW met1 ( 15870 558790 ) ( 1170010 * )
-      NEW met2 ( 2006290 2289900 ) ( 2007900 * 0 )
-      NEW met2 ( 2006290 2289900 ) ( * 2299250 )
-      NEW met1 ( 1170010 2299250 ) ( 2006290 * )
-      NEW met2 ( 15870 553180 ) M2M3_PR
-      NEW met1 ( 15870 558790 ) M1M2_PR
-      NEW met1 ( 1170010 558790 ) M1M2_PR
-      NEW met1 ( 1170010 2299250 ) M1M2_PR
-      NEW met1 ( 2006290 2299250 ) M1M2_PR ;
-    - io_in[36] ( PIN io_in[36] ) ( mprj io_in[36] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 358020 0 ) ( 3220 * )
-      NEW met3 ( 3220 357340 ) ( * 358020 )
-      NEW met3 ( 1380 357340 ) ( 3220 * )
-      NEW met3 ( 1380 354620 ) ( * 357340 )
-      NEW met4 ( 1169780 351900 ) ( * 2300780 )
-      NEW met2 ( 2030210 2289900 ) ( 2031820 * 0 )
-      NEW met2 ( 2030210 2289900 ) ( * 2300780 )
-      NEW met3 ( 1380 354620 ) ( 34500 * )
-      NEW met3 ( 34500 351900 ) ( * 354620 )
-      NEW met3 ( 34500 351900 ) ( 1169780 * )
-      NEW met3 ( 1169780 2300780 ) ( 2030210 * )
-      NEW met3 ( 1169780 351900 ) M3M4_PR
-      NEW met3 ( 1169780 2300780 ) M3M4_PR
-      NEW met2 ( 2030210 2300780 ) M2M3_PR ;
-    - io_in[37] ( PIN io_in[37] ) ( mprj io_in[37] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 162180 0 ) ( 3220 * )
-      NEW met3 ( 3220 161500 ) ( * 162180 )
-      NEW met3 ( 1380 161500 ) ( 3220 * )
-      NEW met3 ( 1380 158780 ) ( * 161500 )
-      NEW met3 ( 2049300 2287180 ) ( 2053670 * )
-      NEW met2 ( 2053670 2287180 ) ( 2055280 * 0 )
-      NEW met4 ( 2049300 158780 ) ( * 2287180 )
-      NEW met3 ( 1380 158780 ) ( 2049300 * )
-      NEW met3 ( 2049300 158780 ) M3M4_PR
-      NEW met3 ( 2049300 2287180 ) M3M4_PR
-      NEW met2 ( 2053670 2287180 ) M2M3_PR ;
-    - io_in[3] ( PIN io_in[3] ) ( mprj io_in[3] ) + USE SIGNAL
-      + ROUTED met3 ( 1270060 2285820 ) ( * 2287180 )
-      NEW met3 ( 1251430 2287180 ) ( 1270060 * )
-      NEW met2 ( 1249820 2287180 0 ) ( 1251430 * )
-      NEW met3 ( 2902370 630020 ) ( 2917780 * 0 )
-      NEW met2 ( 2902370 630020 ) ( * 2285820 )
-      NEW met3 ( 1270060 2285820 ) ( 2902370 * )
-      NEW met2 ( 1251430 2287180 ) M2M3_PR
-      NEW met2 ( 2902370 630020 ) M2M3_PR
-      NEW met2 ( 2902370 2285820 ) M2M3_PR ;
-    - io_in[4] ( PIN io_in[4] ) ( mprj io_in[4] ) + USE SIGNAL
-      + ROUTED met2 ( 1273740 2287180 0 ) ( 1275350 * )
-      NEW met3 ( 2903290 829260 ) ( 2917780 * 0 )
-      NEW met2 ( 2903290 829260 ) ( * 2286500 )
-      NEW met3 ( 1275350 2287180 ) ( 1290300 * )
-      NEW met3 ( 1290300 2286500 ) ( * 2287180 )
-      NEW met3 ( 1290300 2286500 ) ( 2903290 * )
-      NEW met2 ( 1275350 2287180 ) M2M3_PR
-      NEW met2 ( 2903290 829260 ) M2M3_PR
-      NEW met2 ( 2903290 2286500 ) M2M3_PR ;
-    - io_in[5] ( PIN io_in[5] ) ( mprj io_in[5] ) + USE SIGNAL
-      + ROUTED met3 ( 2904210 1028500 ) ( 2917780 * 0 )
-      NEW met2 ( 2904210 1028500 ) ( * 2287180 )
-      NEW met2 ( 1297200 2287180 0 ) ( 1297890 * )
-      NEW met3 ( 1966500 2287180 ) ( * 2287860 )
-      NEW met3 ( 1966500 2287860 ) ( 2063100 * )
-      NEW met3 ( 2063100 2287180 ) ( * 2287860 )
-      NEW met3 ( 2063100 2287180 ) ( 2904210 * )
-      NEW met3 ( 1297890 2287180 ) ( 1966500 * )
-      NEW met2 ( 2904210 1028500 ) M2M3_PR
-      NEW met2 ( 2904210 2287180 ) M2M3_PR
-      NEW met2 ( 1297890 2287180 ) M2M3_PR ;
-    - io_in[6] ( PIN io_in[6] ) ( mprj io_in[6] ) + USE SIGNAL
-      + ROUTED met3 ( 2902830 1227740 ) ( 2917780 * 0 )
-      NEW met2 ( 2902830 1227740 ) ( * 2284630 )
-      NEW met1 ( 1338600 2284630 ) ( * 2287350 )
-      NEW met1 ( 1322730 2287350 ) ( 1338600 * )
-      NEW met2 ( 1322730 2287180 ) ( * 2287350 )
-      NEW met2 ( 1321120 2287180 0 ) ( 1322730 * )
-      NEW met1 ( 1897500 2284630 ) ( 2902830 * )
-      NEW met1 ( 1897500 2283950 ) ( * 2284630 )
-      NEW met1 ( 1890600 2283950 ) ( 1897500 * )
-      NEW met1 ( 1890600 2282930 ) ( * 2283950 )
-      NEW met1 ( 1883700 2282930 ) ( 1890600 * )
-      NEW met1 ( 1883700 2282930 ) ( * 2283270 )
-      NEW met1 ( 1835400 2283270 ) ( 1883700 * )
-      NEW met1 ( 1835400 2282250 ) ( * 2283270 )
-      NEW met1 ( 1828500 2282250 ) ( 1835400 * )
-      NEW met1 ( 1828500 2281910 ) ( * 2282250 )
-      NEW met1 ( 1821600 2281910 ) ( 1828500 * )
-      NEW met1 ( 1821600 2281910 ) ( * 2282250 )
-      NEW met1 ( 1807800 2282250 ) ( 1821600 * )
-      NEW met1 ( 1807800 2281910 ) ( * 2282250 )
-      NEW met1 ( 1800900 2281910 ) ( 1807800 * )
-      NEW met1 ( 1800900 2280890 ) ( * 2281910 )
-      NEW met1 ( 1794000 2280890 ) ( 1800900 * )
-      NEW met1 ( 1794000 2280890 ) ( * 2283270 )
-      NEW met1 ( 1787100 2283270 ) ( 1794000 * )
-      NEW met1 ( 1787100 2282590 ) ( * 2283270 )
-      NEW met1 ( 1780200 2282590 ) ( 1787100 * )
-      NEW met1 ( 1780200 2281910 ) ( * 2282590 )
-      NEW met1 ( 1773300 2281910 ) ( 1780200 * )
-      NEW met1 ( 1773300 2281910 ) ( * 2282250 )
-      NEW met1 ( 1766400 2282250 ) ( 1773300 * )
-      NEW met1 ( 1764330 2281230 ) ( * 2281910 )
-      NEW met1 ( 1764330 2281230 ) ( 1766400 * )
-      NEW met1 ( 1766400 2281230 ) ( * 2282250 )
-      NEW met1 ( 1731900 2281910 ) ( 1764330 * )
-      NEW met1 ( 1731900 2280210 ) ( * 2281910 )
-      NEW met1 ( 1725000 2280210 ) ( 1731900 * )
-      NEW met1 ( 1725000 2280210 ) ( * 2280890 )
-      NEW met1 ( 1718100 2280890 ) ( 1725000 * )
-      NEW met1 ( 1718100 2280550 ) ( * 2280890 )
-      NEW met1 ( 1704300 2280550 ) ( 1718100 * )
-      NEW met1 ( 1704300 2280550 ) ( * 2281570 )
-      NEW met1 ( 1690500 2281570 ) ( 1704300 * )
-      NEW met1 ( 1690500 2279530 ) ( * 2281570 )
-      NEW met1 ( 1683600 2279530 ) ( 1690500 * )
-      NEW met1 ( 1683600 2279190 ) ( * 2279530 )
-      NEW met1 ( 1676700 2279190 ) ( 1683600 * )
-      NEW met1 ( 1676700 2279190 ) ( * 2280550 )
-      NEW met1 ( 1669800 2280550 ) ( 1676700 * )
-      NEW met1 ( 1669800 2280550 ) ( * 2281230 )
-      NEW met1 ( 1662900 2281230 ) ( 1669800 * )
-      NEW met1 ( 1662900 2278170 ) ( * 2281230 )
-      NEW met1 ( 1649100 2278170 ) ( 1662900 * )
-      NEW met1 ( 1610690 2284630 ) ( * 2287350 )
-      NEW met2 ( 1610690 2287350 ) ( * 2288710 )
-      NEW met1 ( 1610690 2288710 ) ( 1617590 * )
-      NEW met2 ( 1617590 2287350 ) ( * 2288710 )
-      NEW met1 ( 1617590 2281570 ) ( * 2287350 )
-      NEW met1 ( 1617590 2281570 ) ( 1618050 * )
-      NEW met1 ( 1618050 2281230 ) ( * 2281570 )
-      NEW met1 ( 1618050 2281230 ) ( 1649100 * )
-      NEW met1 ( 1649100 2278170 ) ( * 2281230 )
-      NEW met1 ( 1338600 2284630 ) ( 1610690 * )
-      NEW met2 ( 2902830 1227740 ) M2M3_PR
-      NEW met1 ( 2902830 2284630 ) M1M2_PR
-      NEW met1 ( 1322730 2287350 ) M1M2_PR
-      NEW met1 ( 1610690 2287350 ) M1M2_PR
-      NEW met1 ( 1610690 2288710 ) M1M2_PR
-      NEW met1 ( 1617590 2288710 ) M1M2_PR
-      NEW met1 ( 1617590 2287350 ) M1M2_PR ;
-    - io_in[7] ( PIN io_in[7] ) ( mprj io_in[7] ) + USE SIGNAL
-      + ROUTED met1 ( 1345270 2284970 ) ( * 2287350 )
-      NEW met2 ( 1345270 2287180 ) ( * 2287350 )
-      NEW met2 ( 1344580 2287180 0 ) ( 1345270 * )
-      NEW met3 ( 2903750 1493620 ) ( 2917780 * 0 )
-      NEW met2 ( 2903750 1493620 ) ( * 2284970 )
-      NEW met1 ( 1890600 2284970 ) ( 2903750 * )
-      NEW met1 ( 1890600 2284630 ) ( * 2284970 )
-      NEW met1 ( 1883700 2284630 ) ( 1890600 * )
-      NEW met1 ( 1883700 2284630 ) ( * 2284970 )
-      NEW met1 ( 1863000 2284970 ) ( 1883700 * )
-      NEW met2 ( 1838390 2287350 ) ( * 2288710 )
-      NEW met1 ( 1838390 2287350 ) ( 1838850 * )
-      NEW met1 ( 1838850 2286330 ) ( * 2287350 )
-      NEW met1 ( 1838850 2286330 ) ( 1863000 * )
-      NEW met1 ( 1863000 2284970 ) ( * 2286330 )
-      NEW met2 ( 1790550 2287350 ) ( * 2288710 )
-      NEW met1 ( 1790550 2288710 ) ( 1838390 * )
-      NEW met1 ( 1780200 2287350 ) ( 1790550 * )
-      NEW met1 ( 1780200 2284970 ) ( * 2287350 )
-      NEW met2 ( 1748230 2287350 ) ( * 2288370 )
-      NEW met1 ( 1748230 2287010 ) ( * 2287350 )
-      NEW met1 ( 1748230 2287010 ) ( 1748690 * )
-      NEW met1 ( 1748690 2284970 ) ( * 2287010 )
-      NEW met1 ( 1748690 2284970 ) ( 1780200 * )
-      NEW met1 ( 1708670 2284970 ) ( * 2287350 )
-      NEW met2 ( 1708670 2287350 ) ( * 2288370 )
-      NEW met1 ( 1708670 2288370 ) ( 1748230 * )
-      NEW met1 ( 1609310 2284970 ) ( * 2285310 )
-      NEW met1 ( 1609310 2285310 ) ( 1610230 * )
-      NEW met1 ( 1610230 2285310 ) ( * 2287350 )
-      NEW met2 ( 1610230 2287350 ) ( * 2288370 )
-      NEW met1 ( 1610230 2288370 ) ( 1620350 * )
-      NEW met2 ( 1620350 2287350 ) ( * 2288370 )
-      NEW met1 ( 1620350 2284970 ) ( * 2287350 )
-      NEW met1 ( 1345270 2284970 ) ( 1609310 * )
-      NEW met1 ( 1620350 2284970 ) ( 1708670 * )
-      NEW met1 ( 1345270 2287350 ) M1M2_PR
-      NEW met2 ( 2903750 1493620 ) M2M3_PR
-      NEW met1 ( 2903750 2284970 ) M1M2_PR
-      NEW met1 ( 1838390 2288710 ) M1M2_PR
-      NEW met1 ( 1838390 2287350 ) M1M2_PR
-      NEW met1 ( 1790550 2287350 ) M1M2_PR
-      NEW met1 ( 1790550 2288710 ) M1M2_PR
-      NEW met1 ( 1748230 2288370 ) M1M2_PR
-      NEW met1 ( 1748230 2287350 ) M1M2_PR
-      NEW met1 ( 1708670 2287350 ) M1M2_PR
-      NEW met1 ( 1708670 2288370 ) M1M2_PR
-      NEW met1 ( 1610230 2287350 ) M1M2_PR
-      NEW met1 ( 1610230 2288370 ) M1M2_PR
-      NEW met1 ( 1620350 2288370 ) M1M2_PR
-      NEW met1 ( 1620350 2287350 ) M1M2_PR ;
-    - io_in[8] ( PIN io_in[8] ) ( mprj io_in[8] ) + USE SIGNAL
-      + ROUTED met3 ( 2904670 1759500 ) ( 2917780 * 0 )
-      NEW met1 ( 1370110 2285310 ) ( * 2287350 )
-      NEW met2 ( 1370110 2287180 ) ( * 2287350 )
-      NEW met2 ( 1368500 2287180 0 ) ( 1370110 * )
-      NEW met2 ( 2904670 1759500 ) ( * 2285310 )
-      NEW met1 ( 1883700 2285310 ) ( 2904670 * )
-      NEW met1 ( 1883700 2285310 ) ( * 2287010 )
-      NEW met2 ( 1837470 2287690 ) ( * 2287860 )
-      NEW met3 ( 1837470 2287860 ) ( 1839310 * )
-      NEW met2 ( 1839310 2287350 ) ( * 2287860 )
-      NEW met1 ( 1839310 2287010 ) ( * 2287350 )
-      NEW met1 ( 1839310 2287010 ) ( 1883700 * )
-      NEW met1 ( 1763870 2285310 ) ( * 2287690 )
-      NEW met1 ( 1763870 2287690 ) ( 1837470 * )
-      NEW met1 ( 1752600 2285310 ) ( 1763870 * )
-      NEW met2 ( 1748690 2287350 ) ( * 2287860 )
-      NEW met1 ( 1748690 2287350 ) ( 1752600 * )
-      NEW met1 ( 1752600 2285310 ) ( * 2287350 )
-      NEW met1 ( 1707290 2285310 ) ( * 2287350 )
-      NEW met2 ( 1707290 2287350 ) ( * 2287860 )
-      NEW met3 ( 1707290 2287860 ) ( 1748690 * )
-      NEW met1 ( 1608850 2285310 ) ( * 2287690 )
-      NEW met1 ( 1608850 2287690 ) ( 1620810 * )
-      NEW met1 ( 1620810 2285310 ) ( * 2287690 )
-      NEW met1 ( 1370110 2285310 ) ( 1608850 * )
-      NEW met1 ( 1620810 2285310 ) ( 1707290 * )
-      NEW met2 ( 2904670 1759500 ) M2M3_PR
-      NEW met1 ( 1370110 2287350 ) M1M2_PR
-      NEW met1 ( 2904670 2285310 ) M1M2_PR
-      NEW met1 ( 1837470 2287690 ) M1M2_PR
-      NEW met2 ( 1837470 2287860 ) M2M3_PR
-      NEW met2 ( 1839310 2287860 ) M2M3_PR
-      NEW met1 ( 1839310 2287350 ) M1M2_PR
-      NEW met2 ( 1748690 2287860 ) M2M3_PR
-      NEW met1 ( 1748690 2287350 ) M1M2_PR
-      NEW met1 ( 1707290 2287350 ) M1M2_PR
-      NEW met2 ( 1707290 2287860 ) M2M3_PR ;
-    - io_in[9] ( PIN io_in[9] ) ( mprj io_in[9] ) + USE SIGNAL
-      + ROUTED met3 ( 2900530 2024700 ) ( 2917780 * 0 )
-      NEW met2 ( 2900530 2024700 ) ( * 2285990 )
-      NEW met1 ( 1435200 2285990 ) ( * 2287350 )
-      NEW met1 ( 1393570 2287350 ) ( 1435200 * )
-      NEW met2 ( 1393570 2287180 ) ( * 2287350 )
-      NEW met2 ( 1391960 2287180 0 ) ( 1393570 * )
-      NEW met1 ( 1897500 2285990 ) ( 2900530 * )
-      NEW met1 ( 1897500 2285990 ) ( * 2287690 )
-      NEW met1 ( 1890600 2287690 ) ( 1897500 * )
-      NEW met1 ( 1890600 2287690 ) ( * 2288030 )
-      NEW met1 ( 1704300 2285990 ) ( * 2288030 )
-      NEW met1 ( 1704300 2288030 ) ( 1890600 * )
-      NEW met1 ( 1649100 2285990 ) ( 1704300 * )
-      NEW met1 ( 1435200 2285990 ) ( 1600800 * )
-      NEW met1 ( 1600800 2285990 ) ( * 2289050 )
-      NEW met1 ( 1600800 2289050 ) ( 1649100 * )
-      NEW met1 ( 1649100 2285990 ) ( * 2289050 )
-      NEW met2 ( 2900530 2024700 ) M2M3_PR
-      NEW met1 ( 2900530 2285990 ) M1M2_PR
-      NEW met1 ( 1393570 2287350 ) M1M2_PR ;
-    - io_oeb[0] ( PIN io_oeb[0] ) ( mprj io_oeb[0] ) + USE SIGNAL
-      + ROUTED met2 ( 1186570 2289900 ) ( 1186800 * 0 )
-      NEW met2 ( 1186570 2289900 ) ( * 2298740 )
-      NEW met3 ( 2901220 165580 ) ( 2917780 * 0 )
-      NEW met4 ( 2901220 165580 ) ( * 2298740 )
-      NEW met3 ( 1186570 2298740 ) ( 2901220 * )
-      NEW met2 ( 1186570 2298740 ) M2M3_PR
-      NEW met3 ( 2901220 165580 ) M3M4_PR
-      NEW met3 ( 2901220 2298740 ) M3M4_PR ;
-    - io_oeb[10] ( PIN io_oeb[10] ) ( mprj io_oeb[10] ) + USE SIGNAL
-      + ROUTED met2 ( 2900990 2421990 ) ( * 2423180 )
-      NEW met3 ( 2900990 2423180 ) ( 2917780 * 0 )
-      NEW met1 ( 1421630 2421990 ) ( 2900990 * )
-      NEW met2 ( 1421630 2289900 ) ( 1423700 * 0 )
-      NEW met2 ( 1421630 2289900 ) ( * 2421990 )
-      NEW met1 ( 2900990 2421990 ) M1M2_PR
-      NEW met2 ( 2900990 2423180 ) M2M3_PR
-      NEW met1 ( 1421630 2421990 ) M1M2_PR ;
-    - io_oeb[11] ( PIN io_oeb[11] ) ( mprj io_oeb[11] ) + USE SIGNAL
-      + ROUTED met2 ( 1445090 2289900 ) ( 1447160 * 0 )
-      NEW met2 ( 1442330 2401200 ) ( 1445090 * )
-      NEW met2 ( 1445090 2289900 ) ( * 2401200 )
-      NEW met2 ( 1442330 2401200 ) ( * 2684130 )
-      NEW met2 ( 2900990 2684130 ) ( * 2689060 )
-      NEW met3 ( 2900990 2689060 ) ( 2917780 * 0 )
-      NEW met1 ( 1442330 2684130 ) ( 2900990 * )
-      NEW met1 ( 1442330 2684130 ) M1M2_PR
-      NEW met1 ( 2900990 2684130 ) M1M2_PR
-      NEW met2 ( 2900990 2689060 ) M2M3_PR ;
-    - io_oeb[12] ( PIN io_oeb[12] ) ( mprj io_oeb[12] ) + USE SIGNAL
-      + ROUTED met2 ( 1469930 2289900 ) ( 1471080 * 0 )
-      NEW met2 ( 1469930 2289900 ) ( * 2953410 )
-      NEW met2 ( 2899150 2953410 ) ( * 2954940 )
-      NEW met3 ( 2899150 2954940 ) ( 2917780 * 0 )
-      NEW met1 ( 1469930 2953410 ) ( 2899150 * )
-      NEW met1 ( 1469930 2953410 ) M1M2_PR
-      NEW met1 ( 2899150 2953410 ) M1M2_PR
-      NEW met2 ( 2899150 2954940 ) M2M3_PR ;
-    - io_oeb[13] ( PIN io_oeb[13] ) ( mprj io_oeb[13] ) + USE SIGNAL
-      + ROUTED met2 ( 2900990 3215550 ) ( * 3220140 )
-      NEW met3 ( 2900990 3220140 ) ( 2917780 * 0 )
-      NEW met1 ( 1490630 3215550 ) ( 2900990 * )
-      NEW met2 ( 1492470 2289900 ) ( 1494540 * 0 )
-      NEW met2 ( 1490630 2401200 ) ( 1492470 * )
-      NEW met2 ( 1492470 2289900 ) ( * 2401200 )
-      NEW met2 ( 1490630 2401200 ) ( * 3215550 )
-      NEW met1 ( 2900990 3215550 ) M1M2_PR
-      NEW met2 ( 2900990 3220140 ) M2M3_PR
-      NEW met1 ( 1490630 3215550 ) M1M2_PR ;
-    - io_oeb[14] ( PIN io_oeb[14] ) ( mprj io_oeb[14] ) + USE SIGNAL
-      + ROUTED met2 ( 2900990 3484830 ) ( * 3486020 )
-      NEW met3 ( 2900990 3486020 ) ( 2917780 * 0 )
-      NEW met1 ( 1518230 3484830 ) ( 2900990 * )
-      NEW met2 ( 1518230 2289900 ) ( 1518460 * 0 )
-      NEW met2 ( 1518230 2289900 ) ( * 3484830 )
-      NEW met1 ( 2900990 3484830 ) M1M2_PR
-      NEW met2 ( 2900990 3486020 ) M2M3_PR
-      NEW met1 ( 1518230 3484830 ) M1M2_PR ;
-    - io_oeb[15] ( PIN io_oeb[15] ) ( mprj io_oeb[15] ) + USE SIGNAL
-      + ROUTED met2 ( 1541920 2289900 0 ) ( 1543530 * )
-      NEW met2 ( 1543530 2289900 ) ( * 2309110 )
-      NEW met2 ( 2636030 2309110 ) ( * 3517980 0 )
-      NEW met1 ( 1543530 2309110 ) ( 2636030 * )
-      NEW met1 ( 1543530 2309110 ) M1M2_PR
-      NEW met1 ( 2636030 2309110 ) M1M2_PR ;
-    - io_oeb[16] ( PIN io_oeb[16] ) ( mprj io_oeb[16] ) + USE SIGNAL
-      + ROUTED met2 ( 1563770 2289900 ) ( 1565840 * 0 )
-      NEW met2 ( 1559630 2401200 ) ( 1563770 * )
-      NEW met2 ( 1563770 2289900 ) ( * 2401200 )
-      NEW met2 ( 1559630 2401200 ) ( * 3504210 )
-      NEW met2 ( 2311730 3504210 ) ( * 3517980 0 )
-      NEW met1 ( 1559630 3504210 ) ( 2311730 * )
-      NEW met1 ( 1559630 3504210 ) M1M2_PR
-      NEW met1 ( 2311730 3504210 ) M1M2_PR ;
-    - io_oeb[17] ( PIN io_oeb[17] ) ( mprj io_oeb[17] ) + USE SIGNAL
-      + ROUTED met2 ( 1589300 2289900 0 ) ( 1590910 * )
-      NEW met2 ( 1590910 2289900 ) ( * 2310810 )
-      NEW met2 ( 1987430 2310810 ) ( * 3517980 0 )
-      NEW met1 ( 1590910 2310810 ) ( 1987430 * )
-      NEW met1 ( 1590910 2310810 ) M1M2_PR
-      NEW met1 ( 1987430 2310810 ) M1M2_PR ;
-    - io_oeb[18] ( PIN io_oeb[18] ) ( mprj io_oeb[18] ) + USE SIGNAL
-      + ROUTED met2 ( 1656690 3517980 ) ( 1661750 * )
-      NEW met2 ( 1661750 3517300 ) ( * 3517980 )
-      NEW met2 ( 1661750 3517300 ) ( 1662670 * )
-      NEW met2 ( 1662670 3517300 ) ( * 3517980 0 )
-      NEW met2 ( 1656690 2307750 ) ( * 3517980 )
-      NEW met1 ( 1614370 2307750 ) ( 1656690 * )
-      NEW met2 ( 1613220 2289900 0 ) ( 1614370 * )
-      NEW met2 ( 1614370 2289900 ) ( * 2307750 )
-      NEW met1 ( 1656690 2307750 ) M1M2_PR
-      NEW met1 ( 1614370 2307750 ) M1M2_PR ;
-    - io_oeb[19] ( PIN io_oeb[19] ) ( mprj io_oeb[19] ) + USE SIGNAL
-      + ROUTED met2 ( 1635530 2289900 ) ( 1636680 * 0 )
-      NEW met2 ( 1635530 2289900 ) ( * 3500810 )
-      NEW met1 ( 1338370 3500810 ) ( 1635530 * )
-      NEW met2 ( 1338370 3500810 ) ( * 3517980 0 )
-      NEW met1 ( 1635530 3500810 ) M1M2_PR
-      NEW met1 ( 1338370 3500810 ) M1M2_PR ;
-    - io_oeb[1] ( PIN io_oeb[1] ) ( mprj io_oeb[1] ) + USE SIGNAL
-      + ROUTED met3 ( 2901450 364820 ) ( 2917780 * 0 )
-      NEW met2 ( 2901450 364820 ) ( * 2284460 )
-      NEW met3 ( 1225900 2284460 ) ( * 2287180 )
-      NEW met3 ( 1211870 2287180 ) ( 1225900 * )
-      NEW met2 ( 1210260 2287180 0 ) ( 1211870 * )
-      NEW met3 ( 1225900 2284460 ) ( 2901450 * )
-      NEW met2 ( 2901450 364820 ) M2M3_PR
-      NEW met2 ( 2901450 2284460 ) M2M3_PR
-      NEW met2 ( 1211870 2287180 ) M2M3_PR ;
-    - io_oeb[20] ( PIN io_oeb[20] ) ( mprj io_oeb[20] ) + USE SIGNAL
-      + ROUTED met2 ( 1658530 2289900 ) ( 1660600 * 0 )
-      NEW met2 ( 1658530 2289900 ) ( * 2304600 )
-      NEW met2 ( 1656230 2304600 ) ( 1658530 * )
-      NEW met2 ( 1656230 2304600 ) ( * 3504550 )
-      NEW met1 ( 1014070 3504550 ) ( 1656230 * )
-      NEW met2 ( 1014070 3504550 ) ( * 3517980 0 )
-      NEW met1 ( 1656230 3504550 ) M1M2_PR
-      NEW met1 ( 1014070 3504550 ) M1M2_PR ;
-    - io_oeb[21] ( PIN io_oeb[21] ) ( mprj io_oeb[21] ) + USE SIGNAL
-      + ROUTED met2 ( 689310 3503190 ) ( * 3517980 0 )
-      NEW met1 ( 689310 3503190 ) ( 1683830 * )
-      NEW met2 ( 1683830 2289900 ) ( 1684060 * 0 )
-      NEW met2 ( 1683830 2289900 ) ( * 3503190 )
-      NEW met1 ( 689310 3503190 ) M1M2_PR
-      NEW met1 ( 1683830 3503190 ) M1M2_PR ;
-    - io_oeb[22] ( PIN io_oeb[22] ) ( mprj io_oeb[22] ) + USE SIGNAL
-      + ROUTED met1 ( 365010 3502170 ) ( 1704530 * )
-      NEW met2 ( 365010 3502170 ) ( * 3517980 0 )
-      NEW met2 ( 1705910 2289900 ) ( 1707980 * 0 )
-      NEW met2 ( 1704530 2401200 ) ( 1705910 * )
-      NEW met2 ( 1705910 2289900 ) ( * 2401200 )
-      NEW met2 ( 1704530 2401200 ) ( * 3502170 )
-      NEW met1 ( 365010 3502170 ) M1M2_PR
-      NEW met1 ( 1704530 3502170 ) M1M2_PR ;
-    - io_oeb[23] ( PIN io_oeb[23] ) ( mprj io_oeb[23] ) + USE SIGNAL
-      + ROUTED met2 ( 1725230 2401200 ) ( 1729370 * )
-      NEW met2 ( 1725230 2401200 ) ( * 3501490 )
-      NEW met1 ( 40710 3501490 ) ( 1725230 * )
-      NEW met2 ( 40710 3501490 ) ( * 3517980 0 )
-      NEW met2 ( 1729370 2289900 ) ( 1731440 * 0 )
-      NEW met2 ( 1729370 2289900 ) ( * 2401200 )
-      NEW met1 ( 1725230 3501490 ) M1M2_PR
-      NEW met1 ( 40710 3501490 ) M1M2_PR ;
-    - io_oeb[24] ( PIN io_oeb[24] ) ( mprj io_oeb[24] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 3290860 0 ) ( 17250 * )
-      NEW met2 ( 17250 3284570 ) ( * 3290860 )
-      NEW met2 ( 1752830 2401200 ) ( 1753290 * )
-      NEW met2 ( 1752830 2401200 ) ( * 3284570 )
-      NEW met1 ( 17250 3284570 ) ( 1752830 * )
-      NEW met2 ( 1753290 2289900 ) ( 1755360 * 0 )
-      NEW met2 ( 1753290 2289900 ) ( * 2401200 )
-      NEW met2 ( 17250 3290860 ) M2M3_PR
-      NEW met1 ( 17250 3284570 ) M1M2_PR
-      NEW met1 ( 1752830 3284570 ) M1M2_PR ;
-    - io_oeb[25] ( PIN io_oeb[25] ) ( mprj io_oeb[25] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 3030420 0 ) ( 16330 * )
-      NEW met2 ( 16330 3029230 ) ( * 3030420 )
-      NEW met2 ( 1773530 2401200 ) ( 1776750 * )
-      NEW met1 ( 16330 3029230 ) ( 1773530 * )
-      NEW met2 ( 1773530 2401200 ) ( * 3029230 )
-      NEW met2 ( 1776750 2289900 ) ( 1778820 * 0 )
-      NEW met2 ( 1776750 2289900 ) ( * 2401200 )
-      NEW met2 ( 16330 3030420 ) M2M3_PR
-      NEW met1 ( 16330 3029230 ) M1M2_PR
-      NEW met1 ( 1773530 3029230 ) M1M2_PR ;
-    - io_oeb[26] ( PIN io_oeb[26] ) ( mprj io_oeb[26] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 2769300 0 ) ( 17250 * )
-      NEW met2 ( 17250 2767090 ) ( * 2769300 )
-      NEW met1 ( 17250 2767090 ) ( 1801130 * )
-      NEW met2 ( 1801130 2289900 ) ( 1802740 * 0 )
-      NEW met2 ( 1801130 2289900 ) ( * 2767090 )
-      NEW met2 ( 17250 2769300 ) M2M3_PR
-      NEW met1 ( 17250 2767090 ) M1M2_PR
-      NEW met1 ( 1801130 2767090 ) M1M2_PR ;
-    - io_oeb[27] ( PIN io_oeb[27] ) ( mprj io_oeb[27] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 2508860 0 ) ( 15410 * )
-      NEW met2 ( 15410 2504950 ) ( * 2508860 )
-      NEW met2 ( 1822290 2401200 ) ( 1824130 * )
-      NEW met2 ( 1822290 2401200 ) ( * 2504950 )
-      NEW met1 ( 15410 2504950 ) ( 1822290 * )
-      NEW met2 ( 1824130 2289900 ) ( 1826200 * 0 )
-      NEW met2 ( 1824130 2289900 ) ( * 2401200 )
-      NEW met2 ( 15410 2508860 ) M2M3_PR
-      NEW met1 ( 15410 2504950 ) M1M2_PR
-      NEW met1 ( 1822290 2504950 ) M1M2_PR ;
-    - io_oeb[28] ( PIN io_oeb[28] ) ( mprj io_oeb[28] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 2247740 0 ) ( 20470 * )
-      NEW met2 ( 20470 2247740 ) ( * 2284290 )
-      NEW met2 ( 1848510 2289050 ) ( * 2289220 )
-      NEW met2 ( 1848510 2289220 ) ( 1850120 * 0 )
-      NEW met1 ( 1791010 2284630 ) ( * 2287350 )
-      NEW met2 ( 1791010 2287350 ) ( * 2289050 )
-      NEW met1 ( 1791010 2289050 ) ( 1848510 * )
-      NEW met1 ( 1787100 2284630 ) ( 1791010 * )
-      NEW met1 ( 1787100 2283950 ) ( * 2284630 )
-      NEW met1 ( 1780200 2283950 ) ( 1787100 * )
-      NEW met1 ( 1780200 2283950 ) ( * 2284290 )
-      NEW met1 ( 1773300 2284290 ) ( 1780200 * )
-      NEW met1 ( 1773300 2283270 ) ( * 2284290 )
-      NEW met1 ( 1766400 2283270 ) ( 1773300 * )
-      NEW met1 ( 1766400 2283270 ) ( * 2284630 )
-      NEW met1 ( 1746850 2284630 ) ( * 2287690 )
-      NEW met1 ( 1746850 2284630 ) ( 1766400 * )
-      NEW met1 ( 1738800 2287690 ) ( 1746850 * )
-      NEW met1 ( 1738800 2284970 ) ( * 2287690 )
-      NEW met1 ( 1731900 2284970 ) ( 1738800 * )
-      NEW met1 ( 1731900 2283610 ) ( * 2284970 )
-      NEW met1 ( 1725000 2283610 ) ( 1731900 * )
-      NEW met1 ( 1725000 2283610 ) ( * 2284630 )
-      NEW met1 ( 1690500 2284630 ) ( 1725000 * )
-      NEW met1 ( 1690500 2283610 ) ( * 2284630 )
-      NEW met1 ( 1676700 2283610 ) ( 1690500 * )
-      NEW met1 ( 1676700 2283610 ) ( * 2284630 )
-      NEW met1 ( 1612070 2284290 ) ( * 2286670 )
-      NEW met1 ( 1612070 2286670 ) ( 1612530 * )
-      NEW met1 ( 1612530 2286670 ) ( * 2287350 )
-      NEW met2 ( 1612530 2287350 ) ( * 2287860 )
-      NEW met3 ( 1612530 2287860 ) ( 1618510 * )
-      NEW met2 ( 1618510 2287350 ) ( * 2287860 )
-      NEW met1 ( 1618510 2284630 ) ( * 2287350 )
-      NEW met1 ( 20470 2284290 ) ( 1612070 * )
-      NEW met1 ( 1618510 2284630 ) ( 1676700 * )
-      NEW met2 ( 20470 2247740 ) M2M3_PR
-      NEW met1 ( 20470 2284290 ) M1M2_PR
-      NEW met1 ( 1848510 2289050 ) M1M2_PR
-      NEW met1 ( 1791010 2287350 ) M1M2_PR
-      NEW met1 ( 1791010 2289050 ) M1M2_PR
-      NEW met1 ( 1612530 2287350 ) M1M2_PR
-      NEW met2 ( 1612530 2287860 ) M2M3_PR
-      NEW met2 ( 1618510 2287860 ) M2M3_PR
-      NEW met1 ( 1618510 2287350 ) M1M2_PR ;
-    - io_oeb[29] ( PIN io_oeb[29] ) ( mprj io_oeb[29] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 1987300 0 ) ( 19090 * )
-      NEW met2 ( 19090 1987300 ) ( * 2283950 )
-      NEW met2 ( 1871970 2288540 ) ( * 2288710 )
-      NEW met2 ( 1871970 2288540 ) ( 1873580 * 0 )
-      NEW met1 ( 1837470 2283950 ) ( * 2287350 )
-      NEW met1 ( 1837470 2287350 ) ( 1837930 * )
-      NEW met1 ( 1837930 2287350 ) ( * 2287690 )
-      NEW met1 ( 1837930 2287690 ) ( 1838850 * )
-      NEW met2 ( 1838850 2287690 ) ( * 2288710 )
-      NEW met1 ( 1838850 2288710 ) ( 1871970 * )
-      NEW met1 ( 1835400 2283950 ) ( 1837470 * )
-      NEW met1 ( 1835400 2283950 ) ( * 2284290 )
-      NEW met1 ( 1828500 2284290 ) ( 1835400 * )
-      NEW met1 ( 1828500 2284290 ) ( * 2284630 )
-      NEW met1 ( 1821600 2284630 ) ( 1828500 * )
-      NEW met1 ( 1821600 2282590 ) ( * 2284630 )
-      NEW met1 ( 1814700 2282590 ) ( 1821600 * )
-      NEW met1 ( 1814700 2282590 ) ( * 2282930 )
-      NEW met1 ( 1807800 2282930 ) ( 1814700 * )
-      NEW met1 ( 1807800 2282930 ) ( * 2283610 )
-      NEW met1 ( 1780200 2283610 ) ( 1807800 * )
-      NEW met1 ( 1780200 2282930 ) ( * 2283610 )
-      NEW met1 ( 1773300 2282930 ) ( 1780200 * )
-      NEW met1 ( 1773300 2282590 ) ( * 2282930 )
-      NEW met1 ( 1766400 2282590 ) ( 1773300 * )
-      NEW met1 ( 1763410 2282590 ) ( * 2282930 )
-      NEW met1 ( 1763410 2282590 ) ( 1764330 * )
-      NEW met1 ( 1764330 2282590 ) ( * 2282930 )
-      NEW met1 ( 1764330 2282930 ) ( 1764790 * )
-      NEW met1 ( 1764790 2282930 ) ( * 2283270 )
-      NEW met1 ( 1764790 2283270 ) ( 1765710 * )
-      NEW met1 ( 1765710 2282930 ) ( * 2283270 )
-      NEW met1 ( 1765710 2282930 ) ( 1766400 * )
-      NEW met1 ( 1766400 2282590 ) ( * 2282930 )
-      NEW met1 ( 1759500 2282930 ) ( 1763410 * )
-      NEW met1 ( 1759500 2282590 ) ( * 2282930 )
-      NEW met1 ( 1752600 2282590 ) ( 1759500 * )
-      NEW met1 ( 1752600 2282590 ) ( * 2282930 )
-      NEW met1 ( 1745700 2282930 ) ( 1752600 * )
-      NEW met1 ( 1745700 2282590 ) ( * 2282930 )
-      NEW met1 ( 1738800 2282590 ) ( 1745700 * )
-      NEW met1 ( 1738800 2282590 ) ( * 2282930 )
-      NEW met1 ( 1731900 2282930 ) ( 1738800 * )
-      NEW met1 ( 1731900 2282250 ) ( * 2282930 )
-      NEW met1 ( 1725000 2282250 ) ( 1731900 * )
-      NEW met1 ( 1725000 2281230 ) ( * 2282250 )
-      NEW met1 ( 1711200 2281230 ) ( 1725000 * )
-      NEW met1 ( 1711200 2281230 ) ( * 2283270 )
-      NEW met1 ( 1704300 2283270 ) ( 1711200 * )
-      NEW met1 ( 1704300 2283270 ) ( * 2283610 )
-      NEW met1 ( 1697400 2283610 ) ( 1704300 * )
-      NEW met1 ( 1697400 2283270 ) ( * 2283610 )
-      NEW met1 ( 1683600 2283270 ) ( 1697400 * )
-      NEW met1 ( 1683600 2282590 ) ( * 2283270 )
-      NEW met1 ( 1676700 2282590 ) ( 1683600 * )
-      NEW met1 ( 1676700 2282590 ) ( * 2282930 )
-      NEW met1 ( 1669800 2282930 ) ( 1676700 * )
-      NEW met1 ( 1669800 2282590 ) ( * 2282930 )
-      NEW met1 ( 1662900 2282590 ) ( 1669800 * )
-      NEW met1 ( 1662900 2282590 ) ( * 2283270 )
-      NEW met1 ( 1656000 2283270 ) ( 1662900 * )
-      NEW met1 ( 1656000 2282250 ) ( * 2283270 )
-      NEW met1 ( 1617130 2283950 ) ( * 2287350 )
-      NEW met2 ( 1617130 2287350 ) ( * 2289220 )
-      NEW met2 ( 1617130 2289220 ) ( 1618050 * )
-      NEW met2 ( 1618050 2287350 ) ( * 2289220 )
-      NEW met1 ( 1618050 2282250 ) ( * 2287350 )
-      NEW met1 ( 19090 2283950 ) ( 1617130 * )
-      NEW met1 ( 1618050 2282250 ) ( 1656000 * )
-      NEW met2 ( 19090 1987300 ) M2M3_PR
-      NEW met1 ( 19090 2283950 ) M1M2_PR
-      NEW met1 ( 1871970 2288710 ) M1M2_PR
-      NEW met1 ( 1838850 2287690 ) M1M2_PR
-      NEW met1 ( 1838850 2288710 ) M1M2_PR
-      NEW met1 ( 1617130 2287350 ) M1M2_PR
-      NEW met1 ( 1618050 2287350 ) M1M2_PR ;
-    - io_oeb[2] ( PIN io_oeb[2] ) ( mprj io_oeb[2] ) + USE SIGNAL
-      + ROUTED met1 ( 2888570 564910 ) ( 2902370 * )
-      NEW met2 ( 2902370 564060 ) ( * 564910 )
-      NEW met3 ( 2902370 564060 ) ( 2917780 * 0 )
-      NEW met2 ( 2888570 564910 ) ( * 2285140 )
-      NEW met3 ( 1242000 2285140 ) ( * 2287180 )
-      NEW met3 ( 1234870 2287180 ) ( 1242000 * )
-      NEW met2 ( 1234180 2287180 0 ) ( 1234870 * )
-      NEW met3 ( 1242000 2285140 ) ( 2888570 * )
-      NEW met1 ( 2888570 564910 ) M1M2_PR
-      NEW met1 ( 2902370 564910 ) M1M2_PR
-      NEW met2 ( 2902370 564060 ) M2M3_PR
-      NEW met2 ( 2888570 2285140 ) M2M3_PR
-      NEW met2 ( 1234870 2287180 ) M2M3_PR ;
-    - io_oeb[30] ( PIN io_oeb[30] ) ( mprj io_oeb[30] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 1726860 0 ) ( 17710 * )
-      NEW met2 ( 17710 1726860 ) ( * 2298230 )
-      NEW met2 ( 1895890 2289900 ) ( 1897500 * 0 )
-      NEW met2 ( 1895890 2289900 ) ( * 2298230 )
-      NEW met1 ( 17710 2298230 ) ( 1895890 * )
-      NEW met2 ( 17710 1726860 ) M2M3_PR
-      NEW met1 ( 17710 2298230 ) M1M2_PR
-      NEW met1 ( 1895890 2298230 ) M1M2_PR ;
-    - io_oeb[31] ( PIN io_oeb[31] ) ( mprj io_oeb[31] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 1465740 0 ) ( 15410 * )
-      NEW met2 ( 15410 1465740 ) ( * 1469650 )
-      NEW met2 ( 1169090 1469650 ) ( * 2281740 )
-      NEW met4 ( 1919580 2281740 ) ( * 2287860 )
-      NEW met3 ( 1919580 2287860 ) ( 1919810 * )
-      NEW met2 ( 1919810 2287860 ) ( 1920960 * 0 )
-      NEW met1 ( 15410 1469650 ) ( 1169090 * )
-      NEW met3 ( 1169090 2281740 ) ( 1919580 * )
-      NEW met2 ( 15410 1465740 ) M2M3_PR
-      NEW met1 ( 15410 1469650 ) M1M2_PR
-      NEW met1 ( 1169090 1469650 ) M1M2_PR
-      NEW met2 ( 1169090 2281740 ) M2M3_PR
-      NEW met3 ( 1919580 2281740 ) M3M4_PR
-      NEW met3 ( 1919580 2287860 ) M3M4_PR
-      NEW met2 ( 1919810 2287860 ) M2M3_PR
-      NEW met3 ( 1919580 2287860 ) RECT ( -390 -150 0 150 )  ;
-    - io_oeb[32] ( PIN io_oeb[32] ) ( mprj io_oeb[32] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 1205300 0 ) ( 17710 * )
-      NEW met2 ( 17710 1205300 ) ( * 1207170 )
-      NEW met2 ( 1172310 1207170 ) ( * 2281060 )
-      NEW met4 ( 1943500 2281060 ) ( * 2287860 )
-      NEW met3 ( 1943500 2287860 ) ( 1943730 * )
-      NEW met2 ( 1943730 2287860 ) ( 1944880 * 0 )
-      NEW met1 ( 17710 1207170 ) ( 1172310 * )
-      NEW met3 ( 1172310 2281060 ) ( 1943500 * )
-      NEW met2 ( 17710 1205300 ) M2M3_PR
-      NEW met1 ( 17710 1207170 ) M1M2_PR
-      NEW met1 ( 1172310 1207170 ) M1M2_PR
-      NEW met2 ( 1172310 2281060 ) M2M3_PR
-      NEW met3 ( 1943500 2281060 ) M3M4_PR
-      NEW met3 ( 1943500 2287860 ) M3M4_PR
-      NEW met2 ( 1943730 2287860 ) M2M3_PR
-      NEW met3 ( 1943500 2287860 ) RECT ( -390 -150 0 150 )  ;
-    - io_oeb[33] ( PIN io_oeb[33] ) ( mprj io_oeb[33] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 944180 0 ) ( 17710 * )
-      NEW met2 ( 17710 944180 ) ( * 945030 )
-      NEW met2 ( 1171390 945030 ) ( * 2280380 )
-      NEW met4 ( 1965580 2280380 ) ( * 2286500 )
-      NEW met1 ( 17710 945030 ) ( 1171390 * )
-      NEW met4 ( 1967420 2286500 ) ( * 2287180 )
-      NEW met3 ( 1967420 2287180 ) ( 1967650 * )
-      NEW met2 ( 1967650 2287180 ) ( 1968340 * 0 )
-      NEW met4 ( 1965580 2286500 ) ( 1967420 * )
-      NEW met3 ( 1171390 2280380 ) ( 1965580 * )
-      NEW met2 ( 17710 944180 ) M2M3_PR
-      NEW met1 ( 17710 945030 ) M1M2_PR
-      NEW met1 ( 1171390 945030 ) M1M2_PR
-      NEW met2 ( 1171390 2280380 ) M2M3_PR
-      NEW met3 ( 1965580 2280380 ) M3M4_PR
-      NEW met3 ( 1967420 2287180 ) M3M4_PR
-      NEW met2 ( 1967650 2287180 ) M2M3_PR
-      NEW met3 ( 1967650 2287180 ) RECT ( 0 -150 390 150 )  ;
-    - io_oeb[34] ( PIN io_oeb[34] ) ( mprj io_oeb[34] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 683740 0 ) ( 17710 * )
-      NEW met2 ( 17710 683740 ) ( * 689690 )
-      NEW met2 ( 1170470 689690 ) ( * 2294830 )
-      NEW met1 ( 17710 689690 ) ( 1170470 * )
-      NEW met2 ( 1990650 2289900 ) ( 1992260 * 0 )
-      NEW met2 ( 1990650 2289900 ) ( * 2294830 )
-      NEW met1 ( 1170470 2294830 ) ( 1990650 * )
-      NEW met2 ( 17710 683740 ) M2M3_PR
-      NEW met1 ( 17710 689690 ) M1M2_PR
-      NEW met1 ( 1170470 689690 ) M1M2_PR
-      NEW met1 ( 1170470 2294830 ) M1M2_PR
-      NEW met1 ( 1990650 2294830 ) M1M2_PR ;
-    - io_oeb[35] ( PIN io_oeb[35] ) ( mprj io_oeb[35] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 423300 0 ) ( 17710 * )
-      NEW met2 ( 17710 423300 ) ( * 427550 )
-      NEW met2 ( 1169550 427550 ) ( * 2293980 )
-      NEW met2 ( 2015490 2289900 ) ( 2015720 * 0 )
-      NEW met2 ( 2015490 2289900 ) ( * 2293980 )
-      NEW met1 ( 17710 427550 ) ( 1169550 * )
-      NEW met3 ( 1169550 2293980 ) ( 2015490 * )
-      NEW met2 ( 17710 423300 ) M2M3_PR
-      NEW met1 ( 17710 427550 ) M1M2_PR
-      NEW met1 ( 1169550 427550 ) M1M2_PR
-      NEW met2 ( 1169550 2293980 ) M2M3_PR
-      NEW met2 ( 2015490 2293980 ) M2M3_PR ;
-    - io_oeb[36] ( PIN io_oeb[36] ) ( mprj io_oeb[36] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 227460 0 ) ( 3220 * )
-      NEW met3 ( 3220 226780 ) ( * 227460 )
-      NEW met3 ( 1380 226780 ) ( 3220 * )
-      NEW met3 ( 1380 224060 ) ( * 226780 )
-      NEW met4 ( 1168860 221340 ) ( * 2292620 )
-      NEW met2 ( 2038030 2289900 ) ( 2039640 * 0 )
-      NEW met2 ( 2038030 2289900 ) ( * 2292620 )
-      NEW met3 ( 1380 224060 ) ( 34500 * )
-      NEW met3 ( 34500 221340 ) ( * 224060 )
-      NEW met3 ( 34500 221340 ) ( 1168860 * )
-      NEW met3 ( 1168860 2292620 ) ( 2038030 * )
-      NEW met3 ( 1168860 221340 ) M3M4_PR
-      NEW met3 ( 1168860 2292620 ) M3M4_PR
-      NEW met2 ( 2038030 2292620 ) M2M3_PR ;
-    - io_oeb[37] ( PIN io_oeb[37] ) ( mprj io_oeb[37] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 32300 0 ) ( 17250 * )
-      NEW met2 ( 17250 32300 ) ( * 2302140 )
-      NEW met2 ( 2061490 2289900 ) ( * 2302140 )
-      NEW met2 ( 2061490 2289900 ) ( 2063100 * 0 )
-      NEW met3 ( 17250 2302140 ) ( 2061490 * )
-      NEW met2 ( 17250 32300 ) M2M3_PR
-      NEW met2 ( 17250 2302140 ) M2M3_PR
-      NEW met2 ( 2061490 2302140 ) M2M3_PR ;
-    - io_oeb[3] ( PIN io_oeb[3] ) ( mprj io_oeb[3] ) + USE SIGNAL
-      + ROUTED met1 ( 2889490 765850 ) ( 2903750 * )
-      NEW met2 ( 2903750 763300 ) ( * 765850 )
-      NEW met3 ( 2903750 763300 ) ( 2917780 * 0 )
-      NEW met2 ( 1257640 2289900 0 ) ( 1259250 * )
-      NEW met2 ( 1259250 2289900 ) ( * 2292110 )
-      NEW met2 ( 2889490 765850 ) ( * 2292110 )
-      NEW met1 ( 1259250 2292110 ) ( 2889490 * )
-      NEW met1 ( 2889490 765850 ) M1M2_PR
-      NEW met1 ( 2903750 765850 ) M1M2_PR
-      NEW met2 ( 2903750 763300 ) M2M3_PR
-      NEW met1 ( 1259250 2292110 ) M1M2_PR
-      NEW met1 ( 2889490 2292110 ) M1M2_PR ;
-    - io_oeb[4] ( PIN io_oeb[4] ) ( mprj io_oeb[4] ) + USE SIGNAL
-      + ROUTED met1 ( 2890410 965770 ) ( 2898230 * )
-      NEW met2 ( 2898230 962540 ) ( * 965770 )
-      NEW met3 ( 2898230 962540 ) ( 2917780 * 0 )
-      NEW met2 ( 1281560 2289900 0 ) ( 1283170 * )
-      NEW met2 ( 1283170 2289900 ) ( * 2292450 )
-      NEW met2 ( 2890410 965770 ) ( * 2292450 )
-      NEW met1 ( 1283170 2292450 ) ( 2890410 * )
-      NEW met1 ( 2890410 965770 ) M1M2_PR
-      NEW met1 ( 2898230 965770 ) M1M2_PR
-      NEW met2 ( 2898230 962540 ) M2M3_PR
-      NEW met1 ( 1283170 2292450 ) M1M2_PR
-      NEW met1 ( 2890410 2292450 ) M1M2_PR ;
-    - io_oeb[5] ( PIN io_oeb[5] ) ( mprj io_oeb[5] ) + USE SIGNAL
-      + ROUTED met1 ( 2890870 1166030 ) ( 2898230 * )
-      NEW met2 ( 2898230 1161780 ) ( * 1166030 )
-      NEW met3 ( 2898230 1161780 ) ( 2917780 * 0 )
-      NEW met2 ( 2890870 1166030 ) ( * 2292790 )
-      NEW met2 ( 1305020 2289900 0 ) ( 1306630 * )
-      NEW met2 ( 1306630 2289900 ) ( * 2292790 )
-      NEW met1 ( 1306630 2292790 ) ( 2890870 * )
-      NEW met1 ( 2890870 1166030 ) M1M2_PR
-      NEW met1 ( 2898230 1166030 ) M1M2_PR
-      NEW met2 ( 2898230 1161780 ) M2M3_PR
-      NEW met1 ( 2890870 2292790 ) M1M2_PR
-      NEW met1 ( 1306630 2292790 ) M1M2_PR ;
-    - io_oeb[6] ( PIN io_oeb[6] ) ( mprj io_oeb[6] ) + USE SIGNAL
-      + ROUTED met1 ( 2887190 1365950 ) ( 2898230 * )
-      NEW met2 ( 2898230 1361020 ) ( * 1365950 )
-      NEW met3 ( 2898230 1361020 ) ( 2917780 * 0 )
-      NEW met2 ( 2887190 1365950 ) ( * 2293130 )
-      NEW met2 ( 1328940 2289900 0 ) ( 1330550 * )
-      NEW met2 ( 1330550 2289900 ) ( * 2293130 )
-      NEW met1 ( 1330550 2293130 ) ( 2887190 * )
-      NEW met1 ( 2887190 1365950 ) M1M2_PR
-      NEW met1 ( 2898230 1365950 ) M1M2_PR
-      NEW met2 ( 2898230 1361020 ) M2M3_PR
-      NEW met1 ( 2887190 2293130 ) M1M2_PR
-      NEW met1 ( 1330550 2293130 ) M1M2_PR ;
-    - io_oeb[7] ( PIN io_oeb[7] ) ( mprj io_oeb[7] ) + USE SIGNAL
-      + ROUTED met2 ( 1352170 2289900 ) ( 1352400 * 0 )
-      NEW met2 ( 1352170 2289900 ) ( * 2293470 )
-      NEW met1 ( 2886730 1627410 ) ( 2900530 * )
-      NEW met2 ( 2900530 1626220 ) ( * 1627410 )
-      NEW met3 ( 2900530 1626220 ) ( 2917780 * 0 )
-      NEW met2 ( 2886730 1627410 ) ( * 2293470 )
-      NEW met1 ( 1352170 2293470 ) ( 2886730 * )
-      NEW met1 ( 1352170 2293470 ) M1M2_PR
-      NEW met1 ( 2886730 1627410 ) M1M2_PR
-      NEW met1 ( 2900530 1627410 ) M1M2_PR
-      NEW met2 ( 2900530 1626220 ) M2M3_PR
-      NEW met1 ( 2886730 2293470 ) M1M2_PR ;
-    - io_oeb[8] ( PIN io_oeb[8] ) ( mprj io_oeb[8] ) + USE SIGNAL
-      + ROUTED met2 ( 1377930 2287180 ) ( * 2287350 )
-      NEW met2 ( 1376320 2287180 0 ) ( 1377930 * )
-      NEW met3 ( 2900990 1892100 ) ( 2917780 * 0 )
-      NEW met2 ( 2900990 1892100 ) ( * 2285650 )
-      NEW met1 ( 1377930 2287350 ) ( 1386900 * )
-      NEW met1 ( 1386900 2285650 ) ( * 2287350 )
-      NEW met1 ( 1890600 2285650 ) ( 2900990 * )
-      NEW met2 ( 1866450 2287350 ) ( * 2288370 )
-      NEW met1 ( 1866450 2287350 ) ( 1890600 * )
-      NEW met1 ( 1890600 2285650 ) ( * 2287350 )
-      NEW met1 ( 1780200 2288370 ) ( 1866450 * )
-      NEW met1 ( 1780200 2288370 ) ( * 2288710 )
-      NEW met1 ( 1704990 2285650 ) ( * 2287350 )
-      NEW met2 ( 1704990 2287350 ) ( * 2288710 )
-      NEW met1 ( 1704990 2288710 ) ( 1780200 * )
-      NEW met1 ( 1601490 2285650 ) ( * 2288030 )
-      NEW met1 ( 1601490 2288030 ) ( 1621270 * )
-      NEW met1 ( 1621270 2285650 ) ( * 2288030 )
-      NEW met1 ( 1386900 2285650 ) ( 1601490 * )
-      NEW met1 ( 1621270 2285650 ) ( 1704990 * )
-      NEW met1 ( 1377930 2287350 ) M1M2_PR
-      NEW met2 ( 2900990 1892100 ) M2M3_PR
-      NEW met1 ( 2900990 2285650 ) M1M2_PR
-      NEW met1 ( 1866450 2288370 ) M1M2_PR
-      NEW met1 ( 1866450 2287350 ) M1M2_PR
-      NEW met1 ( 1704990 2287350 ) M1M2_PR
-      NEW met1 ( 1704990 2288710 ) M1M2_PR ;
-    - io_oeb[9] ( PIN io_oeb[9] ) ( mprj io_oeb[9] ) + USE SIGNAL
-      + ROUTED met3 ( 2917780 2153220 ) ( * 2157300 )
-      NEW met3 ( 2916860 2157300 ) ( 2917780 * )
-      NEW met3 ( 2916860 2157300 ) ( * 2157980 )
-      NEW met3 ( 2916860 2157980 ) ( 2917780 * 0 )
-      NEW met4 ( 2049300 2296700 ) ( * 2301460 )
-      NEW met4 ( 2048380 2296700 ) ( 2049300 * )
-      NEW met4 ( 2048380 2153220 ) ( * 2296700 )
-      NEW met3 ( 2048380 2153220 ) ( 2917780 * )
-      NEW met2 ( 1399780 2289900 0 ) ( 1400470 * )
-      NEW met2 ( 1400470 2289900 ) ( * 2301460 )
-      NEW met3 ( 1400470 2301460 ) ( 2049300 * )
-      NEW met3 ( 2048380 2153220 ) M3M4_PR
-      NEW met3 ( 2049300 2301460 ) M3M4_PR
-      NEW met2 ( 1400470 2301460 ) M2M3_PR ;
-    - io_out[0] ( PIN io_out[0] ) ( mprj io_out[0] ) + USE SIGNAL
-      + ROUTED met3 ( 2887420 98940 ) ( 2917780 * 0 )
-      NEW met4 ( 2887420 98940 ) ( * 2291260 )
-      NEW met2 ( 1194620 2289900 0 ) ( * 2291260 )
-      NEW met3 ( 1194620 2291260 ) ( 2887420 * )
-      NEW met3 ( 2887420 98940 ) M3M4_PR
-      NEW met3 ( 2887420 2291260 ) M3M4_PR
-      NEW met2 ( 1194620 2291260 ) M2M3_PR ;
-    - io_out[10] ( PIN io_out[10] ) ( mprj io_out[10] ) + USE SIGNAL
-      + ROUTED met2 ( 2900070 2352970 ) ( * 2357220 )
-      NEW met3 ( 2900070 2357220 ) ( 2917780 * 0 )
-      NEW met2 ( 1429450 2289900 ) ( 1431520 * 0 )
-      NEW met2 ( 1429450 2289900 ) ( * 2352970 )
-      NEW met1 ( 1429450 2352970 ) ( 2900070 * )
-      NEW met1 ( 2900070 2352970 ) M1M2_PR
-      NEW met2 ( 2900070 2357220 ) M2M3_PR
-      NEW met1 ( 1429450 2352970 ) M1M2_PR ;
-    - io_out[11] ( PIN io_out[11] ) ( mprj io_out[11] ) + USE SIGNAL
-      + ROUTED met2 ( 2900990 2622250 ) ( * 2622420 )
-      NEW met3 ( 2900990 2622420 ) ( 2917780 * 0 )
-      NEW met2 ( 1452910 2289900 ) ( 1454980 * 0 )
-      NEW met2 ( 1449230 2401200 ) ( 1452910 * )
-      NEW met2 ( 1452910 2289900 ) ( * 2401200 )
-      NEW met2 ( 1449230 2401200 ) ( * 2622250 )
-      NEW met1 ( 1449230 2622250 ) ( 2900990 * )
-      NEW met1 ( 1449230 2622250 ) M1M2_PR
-      NEW met1 ( 2900990 2622250 ) M1M2_PR
-      NEW met2 ( 2900990 2622420 ) M2M3_PR ;
-    - io_out[12] ( PIN io_out[12] ) ( mprj io_out[12] ) + USE SIGNAL
-      + ROUTED met2 ( 2900990 2884390 ) ( * 2888300 )
-      NEW met3 ( 2900990 2888300 ) ( 2917780 * 0 )
-      NEW met2 ( 1476830 2289900 ) ( 1478900 * 0 )
-      NEW met2 ( 1476830 2289900 ) ( * 2884390 )
-      NEW met1 ( 1476830 2884390 ) ( 2900990 * )
-      NEW met1 ( 1476830 2884390 ) M1M2_PR
-      NEW met1 ( 2900990 2884390 ) M1M2_PR
-      NEW met2 ( 2900990 2888300 ) M2M3_PR ;
-    - io_out[13] ( PIN io_out[13] ) ( mprj io_out[13] ) + USE SIGNAL
-      + ROUTED met2 ( 2900990 3153330 ) ( * 3154180 )
-      NEW met3 ( 2900990 3154180 ) ( 2917780 * 0 )
-      NEW met2 ( 1500290 2289900 ) ( 1502360 * 0 )
-      NEW met2 ( 1497990 2401200 ) ( 1500290 * )
-      NEW met2 ( 1500290 2289900 ) ( * 2401200 )
-      NEW met2 ( 1497990 2401200 ) ( * 3153330 )
-      NEW met1 ( 1497990 3153330 ) ( 2900990 * )
-      NEW met1 ( 2900990 3153330 ) M1M2_PR
-      NEW met2 ( 2900990 3154180 ) M2M3_PR
-      NEW met1 ( 1497990 3153330 ) M1M2_PR ;
-    - io_out[14] ( PIN io_out[14] ) ( mprj io_out[14] ) + USE SIGNAL
-      + ROUTED met2 ( 2900990 3416150 ) ( * 3419380 )
-      NEW met3 ( 2900990 3419380 ) ( 2917780 * 0 )
-      NEW met2 ( 1525130 2289900 ) ( 1526280 * 0 )
-      NEW met2 ( 1525130 2289900 ) ( * 3416150 )
-      NEW met1 ( 1525130 3416150 ) ( 2900990 * )
-      NEW met1 ( 2900990 3416150 ) M1M2_PR
-      NEW met2 ( 2900990 3419380 ) M2M3_PR
-      NEW met1 ( 1525130 3416150 ) M1M2_PR ;
-    - io_out[15] ( PIN io_out[15] ) ( mprj io_out[15] ) + USE SIGNAL
-      + ROUTED met2 ( 1547670 2289900 ) ( 1549740 * 0 )
-      NEW met2 ( 1545830 2401200 ) ( 1547670 * )
-      NEW met2 ( 1547670 2289900 ) ( * 2401200 )
-      NEW met2 ( 1545830 2401200 ) ( * 3502850 )
-      NEW met2 ( 2717450 3502850 ) ( * 3517980 0 )
-      NEW met1 ( 1545830 3502850 ) ( 2717450 * )
-      NEW met1 ( 1545830 3502850 ) M1M2_PR
-      NEW met1 ( 2717450 3502850 ) M1M2_PR ;
-    - io_out[16] ( PIN io_out[16] ) ( mprj io_out[16] ) + USE SIGNAL
-      + ROUTED met2 ( 1573430 2289900 ) ( 1573660 * 0 )
-      NEW met2 ( 1573430 2289900 ) ( * 3503870 )
-      NEW met1 ( 1573430 3503870 ) ( 2392690 * )
-      NEW met2 ( 2392690 3503870 ) ( * 3517980 0 )
-      NEW met1 ( 1573430 3503870 ) M1M2_PR
-      NEW met1 ( 2392690 3503870 ) M1M2_PR ;
-    - io_out[17] ( PIN io_out[17] ) ( mprj io_out[17] ) + USE SIGNAL
-      + ROUTED met1 ( 1594130 3501150 ) ( 2068390 * )
-      NEW met2 ( 1595050 2289900 ) ( 1597120 * 0 )
-      NEW met2 ( 1594130 2401200 ) ( 1595050 * )
-      NEW met2 ( 1595050 2289900 ) ( * 2401200 )
-      NEW met2 ( 1594130 2401200 ) ( * 3501150 )
-      NEW met2 ( 2068390 3501150 ) ( * 3517980 0 )
-      NEW met1 ( 1594130 3501150 ) M1M2_PR
-      NEW met1 ( 2068390 3501150 ) M1M2_PR ;
-    - io_out[18] ( PIN io_out[18] ) ( mprj io_out[18] ) + USE SIGNAL
-      + ROUTED met2 ( 1739030 2302310 ) ( * 3512100 )
-      NEW met2 ( 1739030 3512100 ) ( 1744090 * )
-      NEW met2 ( 1744090 3512100 ) ( * 3517980 0 )
-      NEW met2 ( 1620810 2289220 ) ( 1621040 * 0 )
-      NEW met2 ( 1620810 2289220 ) ( * 2302310 )
-      NEW met1 ( 1620810 2302310 ) ( 1739030 * )
-      NEW met1 ( 1739030 2302310 ) M1M2_PR
-      NEW met1 ( 1620810 2302310 ) M1M2_PR ;
-    - io_out[19] ( PIN io_out[19] ) ( mprj io_out[19] ) + USE SIGNAL
-      + ROUTED met2 ( 1642890 2289900 ) ( 1644500 * 0 )
-      NEW met2 ( 1642890 2289900 ) ( * 2301970 )
-      NEW met2 ( 1414730 2301970 ) ( * 3512100 )
-      NEW met2 ( 1414730 3512100 ) ( 1419330 * )
-      NEW met2 ( 1419330 3512100 ) ( * 3517980 0 )
-      NEW met1 ( 1414730 2301970 ) ( 1642890 * )
-      NEW met1 ( 1642890 2301970 ) M1M2_PR
-      NEW met1 ( 1414730 2301970 ) M1M2_PR ;
-    - io_out[1] ( PIN io_out[1] ) ( mprj io_out[1] ) + USE SIGNAL
-      + ROUTED met1 ( 2888110 303450 ) ( 2899610 * )
-      NEW met2 ( 2899610 298180 ) ( * 303450 )
-      NEW met3 ( 2899610 298180 ) ( 2917780 * 0 )
-      NEW met2 ( 2888110 303450 ) ( * 2291940 )
-      NEW met2 ( 1218080 2289900 0 ) ( 1219690 * )
-      NEW met2 ( 1219690 2289900 ) ( * 2291940 )
-      NEW met3 ( 1219690 2291940 ) ( 2888110 * )
-      NEW met1 ( 2888110 303450 ) M1M2_PR
-      NEW met1 ( 2899610 303450 ) M1M2_PR
-      NEW met2 ( 2899610 298180 ) M2M3_PR
-      NEW met2 ( 2888110 2291940 ) M2M3_PR
-      NEW met2 ( 1219690 2291940 ) M2M3_PR ;
-    - io_out[20] ( PIN io_out[20] ) ( mprj io_out[20] ) + USE SIGNAL
-      + ROUTED met2 ( 1095030 3504890 ) ( * 3517980 0 )
-      NEW met2 ( 1666810 2289900 ) ( 1668420 * 0 )
-      NEW met2 ( 1666810 2289900 ) ( * 2302650 )
-      NEW met1 ( 1645650 2302650 ) ( 1666810 * )
-      NEW met2 ( 1645650 2302650 ) ( * 3504890 )
-      NEW met1 ( 1095030 3504890 ) ( 1645650 * )
-      NEW met1 ( 1095030 3504890 ) M1M2_PR
-      NEW met1 ( 1645650 3504890 ) M1M2_PR
-      NEW met1 ( 1666810 2302650 ) M1M2_PR
-      NEW met1 ( 1645650 2302650 ) M1M2_PR ;
-    - io_out[21] ( PIN io_out[21] ) ( mprj io_out[21] ) + USE SIGNAL
-      + ROUTED met2 ( 770730 3503530 ) ( * 3517980 0 )
-      NEW met2 ( 1666350 2301970 ) ( * 3503530 )
-      NEW met1 ( 770730 3503530 ) ( 1666350 * )
-      NEW met2 ( 1690730 2289900 ) ( 1691880 * 0 )
-      NEW met2 ( 1690730 2289900 ) ( * 2301970 )
-      NEW met1 ( 1666350 2301970 ) ( 1690730 * )
-      NEW met1 ( 770730 3503530 ) M1M2_PR
-      NEW met1 ( 1666350 3503530 ) M1M2_PR
-      NEW met1 ( 1666350 2301970 ) M1M2_PR
-      NEW met1 ( 1690730 2301970 ) M1M2_PR ;
-    - io_out[22] ( PIN io_out[22] ) ( mprj io_out[22] ) + USE SIGNAL
-      + ROUTED met1 ( 445970 3502510 ) ( 1693950 * )
-      NEW met2 ( 445970 3502510 ) ( * 3517980 0 )
-      NEW met1 ( 1693950 2301970 ) ( 1714190 * )
-      NEW met2 ( 1693950 2301970 ) ( * 3502510 )
-      NEW met2 ( 1714190 2289900 ) ( 1715800 * 0 )
-      NEW met2 ( 1714190 2289900 ) ( * 2301970 )
-      NEW met1 ( 445970 3502510 ) M1M2_PR
-      NEW met1 ( 1693950 3502510 ) M1M2_PR
-      NEW met1 ( 1714190 2301970 ) M1M2_PR
-      NEW met1 ( 1693950 2301970 ) M1M2_PR ;
-    - io_out[23] ( PIN io_out[23] ) ( mprj io_out[23] ) + USE SIGNAL
-      + ROUTED met2 ( 121670 3501830 ) ( * 3517980 0 )
-      NEW met2 ( 1739260 2289220 0 ) ( 1739950 * )
-      NEW met2 ( 1739950 2289220 ) ( * 2302990 )
-      NEW met1 ( 121670 3501830 ) ( 1714650 * )
-      NEW met1 ( 1714650 2302990 ) ( 1739950 * )
-      NEW met2 ( 1714650 2302990 ) ( * 3501830 )
-      NEW met1 ( 121670 3501830 ) M1M2_PR
-      NEW met1 ( 1739950 2302990 ) M1M2_PR
-      NEW met1 ( 1714650 3501830 ) M1M2_PR
-      NEW met1 ( 1714650 2302990 ) M1M2_PR ;
-    - io_out[24] ( PIN io_out[24] ) ( mprj io_out[24] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 3356140 0 ) ( 17710 * )
-      NEW met2 ( 17710 3353590 ) ( * 3356140 )
-      NEW met2 ( 1759730 2401200 ) ( 1761110 * )
-      NEW met2 ( 1759730 2401200 ) ( * 3353590 )
-      NEW met1 ( 17710 3353590 ) ( 1759730 * )
-      NEW met2 ( 1761110 2289900 ) ( 1763180 * 0 )
-      NEW met2 ( 1761110 2289900 ) ( * 2401200 )
-      NEW met2 ( 17710 3356140 ) M2M3_PR
-      NEW met1 ( 17710 3353590 ) M1M2_PR
-      NEW met1 ( 1759730 3353590 ) M1M2_PR ;
-    - io_out[25] ( PIN io_out[25] ) ( mprj io_out[25] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 3095700 0 ) ( 15870 * )
-      NEW met2 ( 15870 3091450 ) ( * 3095700 )
-      NEW met1 ( 15870 3091450 ) ( 1780430 * )
-      NEW met2 ( 1780430 2401200 ) ( 1784570 * )
-      NEW met2 ( 1780430 2401200 ) ( * 3091450 )
-      NEW met2 ( 1784570 2289900 ) ( 1786640 * 0 )
-      NEW met2 ( 1784570 2289900 ) ( * 2401200 )
-      NEW met2 ( 15870 3095700 ) M2M3_PR
-      NEW met1 ( 15870 3091450 ) M1M2_PR
-      NEW met1 ( 1780430 3091450 ) M1M2_PR ;
-    - io_out[26] ( PIN io_out[26] ) ( mprj io_out[26] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 2834580 0 ) ( 17250 * )
-      NEW met2 ( 17250 2829310 ) ( * 2834580 )
-      NEW met1 ( 17250 2829310 ) ( 1808030 * )
-      NEW met2 ( 1808030 2401200 ) ( 1808490 * )
-      NEW met2 ( 1808030 2401200 ) ( * 2829310 )
-      NEW met2 ( 1808490 2289900 ) ( 1810560 * 0 )
-      NEW met2 ( 1808490 2289900 ) ( * 2401200 )
-      NEW met2 ( 17250 2834580 ) M2M3_PR
-      NEW met1 ( 17250 2829310 ) M1M2_PR
-      NEW met1 ( 1808030 2829310 ) M1M2_PR ;
-    - io_out[27] ( PIN io_out[27] ) ( mprj io_out[27] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 2574140 0 ) ( 17250 * )
-      NEW met2 ( 17250 2573970 ) ( * 2574140 )
-      NEW met2 ( 1742250 2302310 ) ( * 2573970 )
-      NEW met1 ( 17250 2573970 ) ( 1742250 * )
-      NEW met1 ( 1742250 2302310 ) ( 1832410 * )
-      NEW met2 ( 1832410 2289900 ) ( 1834020 * 0 )
-      NEW met2 ( 1832410 2289900 ) ( * 2302310 )
-      NEW met2 ( 17250 2574140 ) M2M3_PR
-      NEW met1 ( 17250 2573970 ) M1M2_PR
-      NEW met1 ( 1742250 2302310 ) M1M2_PR
-      NEW met1 ( 1742250 2573970 ) M1M2_PR
-      NEW met1 ( 1832410 2302310 ) M1M2_PR ;
-    - io_out[28] ( PIN io_out[28] ) ( mprj io_out[28] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 2313020 0 ) ( 16330 * )
-      NEW met2 ( 16330 2311830 ) ( * 2313020 )
-      NEW met2 ( 1745470 2301970 ) ( * 2311830 )
-      NEW met1 ( 16330 2311830 ) ( 1745470 * )
-      NEW met1 ( 1745470 2301970 ) ( 1856330 * )
-      NEW met2 ( 1856330 2289900 ) ( 1857940 * 0 )
-      NEW met2 ( 1856330 2289900 ) ( * 2301970 )
-      NEW met2 ( 16330 2313020 ) M2M3_PR
-      NEW met1 ( 16330 2311830 ) M1M2_PR
-      NEW met1 ( 1745470 2311830 ) M1M2_PR
-      NEW met1 ( 1745470 2301970 ) M1M2_PR
-      NEW met1 ( 1856330 2301970 ) M1M2_PR ;
-    - io_out[29] ( PIN io_out[29] ) ( mprj io_out[29] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 2052580 0 ) ( 19550 * )
-      NEW met2 ( 19550 2052580 ) ( * 2298570 )
-      NEW met2 ( 1879790 2289900 ) ( 1881400 * 0 )
-      NEW met2 ( 1879790 2289900 ) ( * 2298570 )
-      NEW met1 ( 19550 2298570 ) ( 1879790 * )
-      NEW met2 ( 19550 2052580 ) M2M3_PR
-      NEW met1 ( 19550 2298570 ) M1M2_PR
-      NEW met1 ( 1879790 2298570 ) M1M2_PR ;
-    - io_out[2] ( PIN io_out[2] ) ( mprj io_out[2] ) + USE SIGNAL
-      + ROUTED met1 ( 2887650 503370 ) ( 2899150 * )
-      NEW met2 ( 2899150 497420 ) ( * 503370 )
-      NEW met3 ( 2899150 497420 ) ( 2917780 * 0 )
-      NEW met2 ( 2887650 503370 ) ( * 2291770 )
-      NEW met2 ( 1241770 2289900 ) ( 1242000 * 0 )
-      NEW met2 ( 1241770 2289900 ) ( * 2291770 )
-      NEW met1 ( 1241770 2291770 ) ( 2887650 * )
-      NEW met1 ( 2887650 503370 ) M1M2_PR
-      NEW met1 ( 2899150 503370 ) M1M2_PR
-      NEW met2 ( 2899150 497420 ) M2M3_PR
-      NEW met1 ( 2887650 2291770 ) M1M2_PR
-      NEW met1 ( 1241770 2291770 ) M1M2_PR ;
-    - io_out[30] ( PIN io_out[30] ) ( mprj io_out[30] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 1792140 0 ) ( 18170 * )
-      NEW met2 ( 18170 1792140 ) ( * 2297890 )
-      NEW met2 ( 1904630 2289900 ) ( 1905320 * 0 )
-      NEW met2 ( 1904630 2289900 ) ( * 2297890 )
-      NEW met1 ( 18170 2297890 ) ( 1904630 * )
-      NEW met2 ( 18170 1792140 ) M2M3_PR
-      NEW met1 ( 18170 2297890 ) M1M2_PR
-      NEW met1 ( 1904630 2297890 ) M1M2_PR ;
-    - io_out[31] ( PIN io_out[31] ) ( mprj io_out[31] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 1531020 0 ) ( 17710 * )
-      NEW met2 ( 17710 1531020 ) ( * 1531530 )
-      NEW met2 ( 1157590 1531530 ) ( * 2295510 )
-      NEW met2 ( 1927170 2289900 ) ( 1928780 * 0 )
-      NEW met2 ( 1927170 2289900 ) ( * 2295510 )
-      NEW met1 ( 17710 1531530 ) ( 1157590 * )
-      NEW met1 ( 1157590 2295510 ) ( 1927170 * )
-      NEW met2 ( 17710 1531020 ) M2M3_PR
-      NEW met1 ( 17710 1531530 ) M1M2_PR
-      NEW met1 ( 1157590 1531530 ) M1M2_PR
-      NEW met1 ( 1157590 2295510 ) M1M2_PR
-      NEW met1 ( 1927170 2295510 ) M1M2_PR ;
-    - io_out[32] ( PIN io_out[32] ) ( mprj io_out[32] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 1270580 0 ) ( 15870 * )
-      NEW met2 ( 15870 1270580 ) ( * 1276190 )
-      NEW met2 ( 1157130 1276190 ) ( * 2295170 )
-      NEW met2 ( 1951090 2289900 ) ( 1952700 * 0 )
-      NEW met2 ( 1951090 2289900 ) ( * 2295170 )
-      NEW met1 ( 15870 1276190 ) ( 1157130 * )
-      NEW met1 ( 1157130 2295170 ) ( 1951090 * )
-      NEW met2 ( 15870 1270580 ) M2M3_PR
-      NEW met1 ( 15870 1276190 ) M1M2_PR
-      NEW met1 ( 1157130 1276190 ) M1M2_PR
-      NEW met1 ( 1157130 2295170 ) M1M2_PR
-      NEW met1 ( 1951090 2295170 ) M1M2_PR ;
-    - io_out[33] ( PIN io_out[33] ) ( mprj io_out[33] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 1009460 0 ) ( 15410 * )
-      NEW met2 ( 15410 1009460 ) ( * 1014050 )
-      NEW met2 ( 1156670 1014050 ) ( * 2294490 )
-      NEW met1 ( 15410 1014050 ) ( 1156670 * )
-      NEW met2 ( 1974550 2289900 ) ( 1976160 * 0 )
-      NEW met2 ( 1974550 2289900 ) ( * 2294490 )
-      NEW met1 ( 1156670 2294490 ) ( 1974550 * )
-      NEW met2 ( 15410 1009460 ) M2M3_PR
-      NEW met1 ( 15410 1014050 ) M1M2_PR
-      NEW met1 ( 1156670 1014050 ) M1M2_PR
-      NEW met1 ( 1156670 2294490 ) M1M2_PR
-      NEW met1 ( 1974550 2294490 ) M1M2_PR ;
-    - io_out[34] ( PIN io_out[34] ) ( mprj io_out[34] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 749020 0 ) ( 17710 * )
-      NEW met2 ( 17710 749020 ) ( * 751910 )
-      NEW met2 ( 1156210 751910 ) ( * 2294150 )
-      NEW met1 ( 17710 751910 ) ( 1156210 * )
-      NEW met2 ( 1998470 2289900 ) ( 2000080 * 0 )
-      NEW met2 ( 1998470 2289900 ) ( * 2294150 )
-      NEW met1 ( 1156210 2294150 ) ( 1998470 * )
-      NEW met2 ( 17710 749020 ) M2M3_PR
-      NEW met1 ( 17710 751910 ) M1M2_PR
-      NEW met1 ( 1156210 751910 ) M1M2_PR
-      NEW met1 ( 1156210 2294150 ) M1M2_PR
-      NEW met1 ( 1998470 2294150 ) M1M2_PR ;
-    - io_out[35] ( PIN io_out[35] ) ( mprj io_out[35] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 487900 0 ) ( 17710 * )
-      NEW met2 ( 17710 487900 ) ( * 489770 )
-      NEW met2 ( 1155750 489770 ) ( * 2293300 )
-      NEW met2 ( 2021930 2289900 ) ( 2023540 * 0 )
-      NEW met2 ( 2021930 2289900 ) ( * 2293300 )
-      NEW met1 ( 17710 489770 ) ( 1155750 * )
-      NEW met3 ( 1155750 2293300 ) ( 2021930 * )
-      NEW met2 ( 17710 487900 ) M2M3_PR
-      NEW met1 ( 17710 489770 ) M1M2_PR
-      NEW met1 ( 1155750 489770 ) M1M2_PR
-      NEW met2 ( 1155750 2293300 ) M2M3_PR
-      NEW met2 ( 2021930 2293300 ) M2M3_PR ;
-    - io_out[36] ( PIN io_out[36] ) ( mprj io_out[36] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 292740 0 ) ( 3220 * )
-      NEW met3 ( 3220 292060 ) ( * 292740 )
-      NEW met3 ( 1380 292060 ) ( 3220 * )
-      NEW met3 ( 1380 290020 ) ( * 292060 )
-      NEW met3 ( 2043780 2287180 ) ( 2045850 * )
-      NEW met2 ( 2045850 2287180 ) ( 2047460 * 0 )
-      NEW met4 ( 2043780 290020 ) ( * 2287180 )
-      NEW met3 ( 1380 290020 ) ( 2043780 * )
-      NEW met3 ( 2043780 290020 ) M3M4_PR
-      NEW met3 ( 2043780 2287180 ) M3M4_PR
-      NEW met2 ( 2045850 2287180 ) M2M3_PR ;
-    - io_out[37] ( PIN io_out[37] ) ( mprj io_out[37] ) + USE SIGNAL
-      + ROUTED met3 ( 1380 96900 0 ) ( 17710 * )
-      NEW met2 ( 17710 96900 ) ( * 103190 )
-      NEW met1 ( 17710 103190 ) ( 2074830 * )
-      NEW met2 ( 2070920 2287180 0 ) ( 2074830 * )
-      NEW met2 ( 2074830 103190 ) ( * 2287180 )
-      NEW met2 ( 17710 96900 ) M2M3_PR
-      NEW met1 ( 17710 103190 ) M1M2_PR
-      NEW met1 ( 2074830 103190 ) M1M2_PR ;
-    - io_out[3] ( PIN io_out[3] ) ( mprj io_out[3] ) + USE SIGNAL
-      + ROUTED met1 ( 2889030 696830 ) ( 2898230 * )
-      NEW met2 ( 2898230 696660 ) ( * 696830 )
-      NEW met3 ( 2898230 696660 ) ( 2917780 * 0 )
-      NEW met2 ( 1265460 2289900 0 ) ( 1267070 * )
-      NEW met2 ( 1267070 2289900 ) ( * 2304690 )
-      NEW met2 ( 2889030 696830 ) ( * 2304690 )
-      NEW met1 ( 1267070 2304690 ) ( 2889030 * )
-      NEW met1 ( 1267070 2304690 ) M1M2_PR
-      NEW met1 ( 2889030 696830 ) M1M2_PR
-      NEW met1 ( 2898230 696830 ) M1M2_PR
-      NEW met2 ( 2898230 696660 ) M2M3_PR
-      NEW met1 ( 2889030 2304690 ) M1M2_PR ;
-    - io_out[4] ( PIN io_out[4] ) ( mprj io_out[4] ) + USE SIGNAL
-      + ROUTED met1 ( 2889950 896750 ) ( 2898690 * )
-      NEW met2 ( 2898690 895900 ) ( * 896750 )
-      NEW met3 ( 2898690 895900 ) ( 2917780 * 0 )
-      NEW met2 ( 1289380 2289900 0 ) ( 1290070 * )
-      NEW met2 ( 1290070 2289900 ) ( * 2305030 )
-      NEW met2 ( 2889950 896750 ) ( * 2305030 )
-      NEW met1 ( 1290070 2305030 ) ( 2889950 * )
-      NEW met1 ( 1290070 2305030 ) M1M2_PR
-      NEW met1 ( 2889950 896750 ) M1M2_PR
-      NEW met1 ( 2898690 896750 ) M1M2_PR
-      NEW met2 ( 2898690 895900 ) M2M3_PR
-      NEW met1 ( 2889950 2305030 ) M1M2_PR ;
-    - io_out[5] ( PIN io_out[5] ) ( mprj io_out[5] ) + USE SIGNAL
-      + ROUTED met3 ( 2894550 1095140 ) ( 2917780 * 0 )
-      NEW met2 ( 2894550 1095140 ) ( * 2312170 )
-      NEW met2 ( 1312840 2289900 0 ) ( 1314450 * )
-      NEW met2 ( 1314450 2289900 ) ( * 2312170 )
-      NEW met1 ( 1314450 2312170 ) ( 2894550 * )
-      NEW met2 ( 2894550 1095140 ) M2M3_PR
-      NEW met1 ( 2894550 2312170 ) M1M2_PR
-      NEW met1 ( 1314450 2312170 ) M1M2_PR ;
-    - io_out[6] ( PIN io_out[6] ) ( mprj io_out[6] ) + USE SIGNAL
-      + ROUTED met2 ( 2121750 1296930 ) ( * 2299930 )
-      NEW met2 ( 2899150 1294380 ) ( * 1296930 )
-      NEW met3 ( 2899150 1294380 ) ( 2917780 * 0 )
-      NEW met2 ( 1336760 2289900 0 ) ( 1337450 * )
-      NEW met2 ( 1337450 2289900 ) ( * 2299930 )
-      NEW met1 ( 2121750 1296930 ) ( 2899150 * )
-      NEW met1 ( 1337450 2299930 ) ( 2121750 * )
-      NEW met1 ( 2121750 1296930 ) M1M2_PR
-      NEW met1 ( 2121750 2299930 ) M1M2_PR
-      NEW met1 ( 2899150 1296930 ) M1M2_PR
-      NEW met2 ( 2899150 1294380 ) M2M3_PR
-      NEW met1 ( 1337450 2299930 ) M1M2_PR ;
-    - io_out[7] ( PIN io_out[7] ) ( mprj io_out[7] ) + USE SIGNAL
-      + ROUTED met3 ( 2895010 1560260 ) ( 2917780 * 0 )
-      NEW met2 ( 1360220 2289900 0 ) ( 1361830 * )
-      NEW met2 ( 1361830 2289900 ) ( * 2312510 )
-      NEW met2 ( 2895010 1560260 ) ( * 2312510 )
-      NEW met1 ( 1361830 2312510 ) ( 2895010 * )
-      NEW met1 ( 1361830 2312510 ) M1M2_PR
-      NEW met2 ( 2895010 1560260 ) M2M3_PR
-      NEW met1 ( 2895010 2312510 ) M1M2_PR ;
-    - io_out[8] ( PIN io_out[8] ) ( mprj io_out[8] ) + USE SIGNAL
-      + ROUTED met2 ( 2900990 1825460 ) ( * 1828350 )
-      NEW met3 ( 2900990 1825460 ) ( 2917780 * 0 )
-      NEW met2 ( 1384140 2289900 0 ) ( 1385290 * )
-      NEW met2 ( 1385290 2289900 ) ( * 2300950 )
-      NEW met2 ( 2128650 1828350 ) ( * 2300950 )
-      NEW met1 ( 2128650 1828350 ) ( 2900990 * )
-      NEW met1 ( 1385290 2300950 ) ( 2128650 * )
-      NEW met1 ( 2128650 1828350 ) M1M2_PR
-      NEW met1 ( 2900990 1828350 ) M1M2_PR
-      NEW met2 ( 2900990 1825460 ) M2M3_PR
-      NEW met1 ( 1385290 2300950 ) M1M2_PR
-      NEW met1 ( 2128650 2300950 ) M1M2_PR ;
-    - io_out[9] ( PIN io_out[9] ) ( mprj io_out[9] ) + USE SIGNAL
-      + ROUTED met2 ( 2142450 2097290 ) ( * 2301630 )
-      NEW met2 ( 2900070 2091340 ) ( * 2097290 )
-      NEW met3 ( 2900070 2091340 ) ( 2917780 * 0 )
-      NEW met2 ( 1407370 2289900 ) ( 1407600 * 0 )
-      NEW met2 ( 1407370 2289900 ) ( * 2301630 )
-      NEW met1 ( 2142450 2097290 ) ( 2900070 * )
-      NEW met1 ( 1407370 2301630 ) ( 2142450 * )
-      NEW met1 ( 2142450 2097290 ) M1M2_PR
-      NEW met1 ( 2142450 2301630 ) M1M2_PR
-      NEW met1 ( 2900070 2097290 ) M1M2_PR
-      NEW met2 ( 2900070 2091340 ) M2M3_PR
-      NEW met1 ( 1407370 2301630 ) M1M2_PR ;
-    - la_data_in[0] ( PIN la_data_in[0] ) ( mprj la_data_in[0] ) + USE SIGNAL
-      + ROUTED met2 ( 1367810 1688780 ) ( 1368890 * )
-      NEW met2 ( 1368890 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1367810 81090 ) ( * 1688780 )
-      NEW met2 ( 628130 1700 ) ( 629510 * 0 )
-      NEW met2 ( 628130 1700 ) ( * 81090 )
-      NEW met1 ( 628130 81090 ) ( 1367810 * )
-      NEW met1 ( 1367810 81090 ) M1M2_PR
-      NEW met1 ( 628130 81090 ) M1M2_PR ;
-    - la_data_in[100] ( PIN la_data_in[100] ) ( mprj la_data_in[100] ) + USE SIGNAL
-      + ROUTED met2 ( 2402810 1700 0 ) ( * 57630 )
-      NEW met2 ( 1912450 57630 ) ( * 1580100 )
-      NEW met2 ( 1912450 1580100 ) ( 1913370 * )
-      NEW met2 ( 1913370 1688780 ) ( 1916750 * )
-      NEW met2 ( 1916750 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1913370 1580100 ) ( * 1688780 )
-      NEW met1 ( 1912450 57630 ) ( 2402810 * )
-      NEW met1 ( 2402810 57630 ) M1M2_PR
-      NEW met1 ( 1912450 57630 ) M1M2_PR ;
-    - la_data_in[101] ( PIN la_data_in[101] ) ( mprj la_data_in[101] ) + USE SIGNAL
-      + ROUTED met2 ( 1919810 57970 ) ( * 1580100 )
-      NEW met2 ( 1919810 1580100 ) ( 1922110 * )
-      NEW met2 ( 1922110 1688780 ) ( 1922270 * )
-      NEW met2 ( 1922270 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1922110 1580100 ) ( * 1688780 )
-      NEW met2 ( 2420290 1700 0 ) ( * 57970 )
-      NEW met1 ( 1919810 57970 ) ( 2420290 * )
-      NEW met1 ( 1919810 57970 ) M1M2_PR
-      NEW met1 ( 2420290 57970 ) M1M2_PR ;
-    - la_data_in[102] ( PIN la_data_in[102] ) ( mprj la_data_in[102] ) + USE SIGNAL
-      + ROUTED met2 ( 2435930 1700 ) ( 2438230 * 0 )
-      NEW met2 ( 1926710 1688780 ) ( 1927790 * )
-      NEW met2 ( 1927790 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1926710 62050 ) ( * 1688780 )
-      NEW met2 ( 2435930 1700 ) ( * 62050 )
-      NEW met1 ( 1926710 62050 ) ( 2435930 * )
-      NEW met1 ( 1926710 62050 ) M1M2_PR
-      NEW met1 ( 2435930 62050 ) M1M2_PR ;
-    - la_data_in[103] ( PIN la_data_in[103] ) ( mprj la_data_in[103] ) + USE SIGNAL
-      + ROUTED met2 ( 1932690 1688780 ) ( 1933310 * )
-      NEW met2 ( 1933310 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1932690 61710 ) ( * 1688780 )
-      NEW met2 ( 2453870 1700 ) ( 2455710 * 0 )
-      NEW met2 ( 2453870 1700 ) ( * 16830 )
-      NEW met1 ( 2449730 16830 ) ( 2453870 * )
-      NEW met1 ( 1932690 61710 ) ( 2449730 * )
-      NEW met2 ( 2449730 16830 ) ( * 61710 )
-      NEW met1 ( 1932690 61710 ) M1M2_PR
-      NEW met1 ( 2453870 16830 ) M1M2_PR
-      NEW met1 ( 2449730 16830 ) M1M2_PR
-      NEW met1 ( 2449730 61710 ) M1M2_PR ;
-    - la_data_in[104] ( PIN la_data_in[104] ) ( mprj la_data_in[104] ) + USE SIGNAL
-      + ROUTED met1 ( 1933150 1652570 ) ( 1938670 * )
-      NEW met2 ( 1933150 60690 ) ( * 1652570 )
-      NEW met2 ( 1938670 1688780 ) ( 1938830 * )
-      NEW met2 ( 1938830 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1938670 1652570 ) ( * 1688780 )
-      NEW met1 ( 1933150 60690 ) ( 2473650 * )
-      NEW met2 ( 2473650 1700 0 ) ( * 60690 )
-      NEW met1 ( 1933150 1652570 ) M1M2_PR
-      NEW met1 ( 1938670 1652570 ) M1M2_PR
-      NEW met1 ( 1933150 60690 ) M1M2_PR
-      NEW met1 ( 2473650 60690 ) M1M2_PR ;
-    - la_data_in[105] ( PIN la_data_in[105] ) ( mprj la_data_in[105] ) + USE SIGNAL
-      + ROUTED met1 ( 1939130 1683510 ) ( 1944190 * )
-      NEW met2 ( 1944190 1683510 ) ( * 1688780 )
-      NEW met2 ( 1944190 1688780 ) ( 1944350 * )
-      NEW met2 ( 1944350 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1939130 23290 ) ( * 1683510 )
-      NEW met2 ( 2491130 1700 0 ) ( * 23290 )
-      NEW met1 ( 1939130 23290 ) ( 2491130 * )
-      NEW met1 ( 1939130 23290 ) M1M2_PR
-      NEW met1 ( 1939130 1683510 ) M1M2_PR
-      NEW met1 ( 1944190 1683510 ) M1M2_PR
-      NEW met1 ( 2491130 23290 ) M1M2_PR ;
-    - la_data_in[106] ( PIN la_data_in[106] ) ( mprj la_data_in[106] ) + USE SIGNAL
-      + ROUTED met1 ( 1946030 1652570 ) ( 1949710 * )
-      NEW met2 ( 2509070 1700 0 ) ( * 23630 )
-      NEW met2 ( 1946030 23630 ) ( * 1652570 )
-      NEW met2 ( 1949710 1688780 ) ( 1949870 * )
-      NEW met2 ( 1949870 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1949710 1652570 ) ( * 1688780 )
-      NEW met1 ( 1946030 23630 ) ( 2509070 * )
-      NEW met1 ( 1946030 23630 ) M1M2_PR
-      NEW met1 ( 1946030 1652570 ) M1M2_PR
-      NEW met1 ( 1949710 1652570 ) M1M2_PR
-      NEW met1 ( 2509070 23630 ) M1M2_PR ;
-    - la_data_in[107] ( PIN la_data_in[107] ) ( mprj la_data_in[107] ) + USE SIGNAL
-      + ROUTED met2 ( 2527010 1700 0 ) ( * 27370 )
-      NEW met1 ( 1952930 1689290 ) ( 1955390 * )
-      NEW met2 ( 1955390 1689290 ) ( * 1690140 0 )
-      NEW met2 ( 1952930 27370 ) ( * 1689290 )
-      NEW met1 ( 1952930 27370 ) ( 2527010 * )
-      NEW met1 ( 1952930 27370 ) M1M2_PR
-      NEW met1 ( 2527010 27370 ) M1M2_PR
-      NEW met1 ( 1952930 1689290 ) M1M2_PR
-      NEW met1 ( 1955390 1689290 ) M1M2_PR ;
-    - la_data_in[108] ( PIN la_data_in[108] ) ( mprj la_data_in[108] ) + USE SIGNAL
-      + ROUTED met2 ( 2544490 1700 0 ) ( * 27030 )
-      NEW met2 ( 1960290 1688780 ) ( 1960450 * )
-      NEW met2 ( 1960450 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1960290 27030 ) ( * 1688780 )
-      NEW met1 ( 1960290 27030 ) ( 2544490 * )
-      NEW met1 ( 1960290 27030 ) M1M2_PR
-      NEW met1 ( 2544490 27030 ) M1M2_PR ;
-    - la_data_in[109] ( PIN la_data_in[109] ) ( mprj la_data_in[109] ) + USE SIGNAL
-      + ROUTED met1 ( 1959830 1688950 ) ( 1965970 * )
-      NEW met2 ( 1965970 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1959830 26690 ) ( * 1688950 )
-      NEW met2 ( 2562430 1700 0 ) ( * 26690 )
-      NEW met1 ( 1959830 26690 ) ( 2562430 * )
-      NEW met1 ( 1959830 26690 ) M1M2_PR
-      NEW met1 ( 1959830 1688950 ) M1M2_PR
-      NEW met1 ( 1965970 1688950 ) M1M2_PR
-      NEW met1 ( 2562430 26690 ) M1M2_PR ;
-    - la_data_in[10] ( PIN la_data_in[10] ) ( mprj la_data_in[10] ) + USE SIGNAL
-      + ROUTED met2 ( 806610 1700 0 ) ( * 81770 )
-      NEW met1 ( 806610 81770 ) ( 1423010 * )
-      NEW met2 ( 1423010 1688780 ) ( 1423630 * )
-      NEW met2 ( 1423630 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1423010 81770 ) ( * 1688780 )
-      NEW met1 ( 806610 81770 ) M1M2_PR
-      NEW met1 ( 1423010 81770 ) M1M2_PR ;
-    - la_data_in[110] ( PIN la_data_in[110] ) ( mprj la_data_in[110] ) + USE SIGNAL
-      + ROUTED met2 ( 2579910 1700 0 ) ( * 26350 )
-      NEW met1 ( 1966730 26350 ) ( 2579910 * )
-      NEW met1 ( 1966730 1688950 ) ( 1971490 * )
-      NEW met2 ( 1971490 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1966730 26350 ) ( * 1688950 )
-      NEW met1 ( 1966730 26350 ) M1M2_PR
-      NEW met1 ( 2579910 26350 ) M1M2_PR
-      NEW met1 ( 1966730 1688950 ) M1M2_PR
-      NEW met1 ( 1971490 1688950 ) M1M2_PR ;
-    - la_data_in[111] ( PIN la_data_in[111] ) ( mprj la_data_in[111] ) + USE SIGNAL
-      + ROUTED met2 ( 2597850 1700 0 ) ( * 26010 )
-      NEW met1 ( 1973630 26010 ) ( 2597850 * )
-      NEW met1 ( 1973630 1683510 ) ( 1976850 * )
-      NEW met2 ( 1976850 1683510 ) ( * 1688780 )
-      NEW met2 ( 1976850 1688780 ) ( 1977010 * )
-      NEW met2 ( 1977010 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1973630 26010 ) ( * 1683510 )
-      NEW met1 ( 2597850 26010 ) M1M2_PR
-      NEW met1 ( 1973630 26010 ) M1M2_PR
-      NEW met1 ( 1973630 1683510 ) M1M2_PR
-      NEW met1 ( 1976850 1683510 ) M1M2_PR ;
-    - la_data_in[112] ( PIN la_data_in[112] ) ( mprj la_data_in[112] ) + USE SIGNAL
-      + ROUTED met2 ( 2615330 1700 0 ) ( * 25670 )
-      NEW met1 ( 1980530 1652910 ) ( 1982370 * )
-      NEW met1 ( 1980530 25670 ) ( 2615330 * )
-      NEW met2 ( 1980530 25670 ) ( * 1652910 )
-      NEW met2 ( 1982370 1688780 ) ( 1982530 * )
-      NEW met2 ( 1982530 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1982370 1652910 ) ( * 1688780 )
-      NEW met1 ( 2615330 25670 ) M1M2_PR
-      NEW met1 ( 1980530 25670 ) M1M2_PR
-      NEW met1 ( 1980530 1652910 ) M1M2_PR
-      NEW met1 ( 1982370 1652910 ) M1M2_PR ;
-    - la_data_in[113] ( PIN la_data_in[113] ) ( mprj la_data_in[113] ) + USE SIGNAL
-      + ROUTED met2 ( 2633270 1700 0 ) ( * 25330 )
-      NEW met1 ( 1987430 25330 ) ( 2633270 * )
-      NEW met2 ( 1987430 1688780 ) ( 1988050 * )
-      NEW met2 ( 1988050 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1987430 25330 ) ( * 1688780 )
-      NEW met1 ( 2633270 25330 ) M1M2_PR
-      NEW met1 ( 1987430 25330 ) M1M2_PR ;
-    - la_data_in[114] ( PIN la_data_in[114] ) ( mprj la_data_in[114] ) + USE SIGNAL
-      + ROUTED met1 ( 1987890 1652570 ) ( 1993410 * )
-      NEW met2 ( 2650750 1700 0 ) ( * 24140 )
-      NEW met3 ( 1987890 24140 ) ( 2650750 * )
-      NEW met2 ( 1987890 24140 ) ( * 1652570 )
-      NEW met2 ( 1993410 1688780 ) ( 1993570 * )
-      NEW met2 ( 1993570 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1993410 1652570 ) ( * 1688780 )
-      NEW met2 ( 1987890 24140 ) M2M3_PR
-      NEW met1 ( 1987890 1652570 ) M1M2_PR
-      NEW met1 ( 1993410 1652570 ) M1M2_PR
-      NEW met2 ( 2650750 24140 ) M2M3_PR ;
-    - la_data_in[115] ( PIN la_data_in[115] ) ( mprj la_data_in[115] ) + USE SIGNAL
-      + ROUTED met2 ( 2668690 1700 0 ) ( * 24990 )
-      NEW met1 ( 1994330 24990 ) ( 2668690 * )
-      NEW met1 ( 1994330 1688950 ) ( 1999090 * )
-      NEW met2 ( 1999090 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1994330 24990 ) ( * 1688950 )
-      NEW met1 ( 1994330 24990 ) M1M2_PR
-      NEW met1 ( 2668690 24990 ) M1M2_PR
-      NEW met1 ( 1994330 1688950 ) M1M2_PR
-      NEW met1 ( 1999090 1688950 ) M1M2_PR ;
-    - la_data_in[116] ( PIN la_data_in[116] ) ( mprj la_data_in[116] ) + USE SIGNAL
-      + ROUTED met2 ( 2686170 1700 0 ) ( * 24650 )
-      NEW met1 ( 2001230 24650 ) ( 2686170 * )
-      NEW met1 ( 2001230 1683510 ) ( 2004450 * )
-      NEW met2 ( 2004450 1683510 ) ( * 1688780 )
-      NEW met2 ( 2004450 1688780 ) ( 2004610 * )
-      NEW met2 ( 2004610 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 2001230 24650 ) ( * 1683510 )
-      NEW met1 ( 2001230 24650 ) M1M2_PR
-      NEW met1 ( 2686170 24650 ) M1M2_PR
-      NEW met1 ( 2001230 1683510 ) M1M2_PR
-      NEW met1 ( 2004450 1683510 ) M1M2_PR ;
-    - la_data_in[117] ( PIN la_data_in[117] ) ( mprj la_data_in[117] ) + USE SIGNAL
-      + ROUTED met2 ( 2704110 1700 0 ) ( * 24310 )
-      NEW met1 ( 2008130 24310 ) ( 2704110 * )
-      NEW met1 ( 2008130 1688270 ) ( * 1688610 )
-      NEW met1 ( 2008130 1688610 ) ( 2010130 * )
-      NEW met1 ( 2010130 1688610 ) ( * 1689290 )
-      NEW met2 ( 2010130 1689290 ) ( * 1690140 0 )
-      NEW met2 ( 2008130 24310 ) ( * 1688270 )
-      NEW met1 ( 2704110 24310 ) M1M2_PR
-      NEW met1 ( 2008130 24310 ) M1M2_PR
-      NEW met1 ( 2008130 1688270 ) M1M2_PR
-      NEW met1 ( 2010130 1689290 ) M1M2_PR ;
-    - la_data_in[118] ( PIN la_data_in[118] ) ( mprj la_data_in[118] ) + USE SIGNAL
-      + ROUTED met2 ( 2722050 1700 0 ) ( * 23970 )
-      NEW met2 ( 2015030 1688780 ) ( 2015650 * )
-      NEW met2 ( 2015650 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 2015030 23970 ) ( * 1688780 )
-      NEW met1 ( 2015030 23970 ) ( 2722050 * )
-      NEW met1 ( 2015030 23970 ) M1M2_PR
-      NEW met1 ( 2722050 23970 ) M1M2_PR ;
-    - la_data_in[119] ( PIN la_data_in[119] ) ( mprj la_data_in[119] ) + USE SIGNAL
-      + ROUTED met1 ( 2015950 1652570 ) ( 2020550 * )
-      NEW met2 ( 2015950 58990 ) ( * 1652570 )
-      NEW met2 ( 2020550 1688780 ) ( 2020710 * )
-      NEW met2 ( 2020710 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 2020550 1652570 ) ( * 1688780 )
-      NEW met1 ( 2015950 58990 ) ( 2739530 * )
-      NEW met2 ( 2739530 1700 0 ) ( * 58990 )
-      NEW met1 ( 2015950 1652570 ) M1M2_PR
-      NEW met1 ( 2020550 1652570 ) M1M2_PR
-      NEW met1 ( 2015950 58990 ) M1M2_PR
-      NEW met1 ( 2739530 58990 ) M1M2_PR ;
-    - la_data_in[11] ( PIN la_data_in[11] ) ( mprj la_data_in[11] ) + USE SIGNAL
-      + ROUTED met2 ( 822250 1700 ) ( 824550 * 0 )
-      NEW met2 ( 822250 1700 ) ( * 82110 )
-      NEW met1 ( 822250 82110 ) ( 1429450 * )
-      NEW met2 ( 1429220 1688780 ) ( 1429450 * )
-      NEW met2 ( 1429220 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1429450 82110 ) ( * 1688780 )
-      NEW met1 ( 822250 82110 ) M1M2_PR
-      NEW met1 ( 1429450 82110 ) M1M2_PR ;
-    - la_data_in[120] ( PIN la_data_in[120] ) ( mprj la_data_in[120] ) + USE SIGNAL
-      + ROUTED met2 ( 2023310 1688780 ) ( 2026230 * )
-      NEW met2 ( 2026230 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 2023310 58650 ) ( * 1688780 )
-      NEW met2 ( 2755170 1700 ) ( 2757470 * 0 )
-      NEW met1 ( 2023310 58650 ) ( 2755170 * )
-      NEW met2 ( 2755170 1700 ) ( * 58650 )
-      NEW met1 ( 2023310 58650 ) M1M2_PR
-      NEW met1 ( 2755170 58650 ) M1M2_PR ;
-    - la_data_in[121] ( PIN la_data_in[121] ) ( mprj la_data_in[121] ) + USE SIGNAL
-      + ROUTED met1 ( 2029750 1652570 ) ( 2031590 * )
-      NEW met2 ( 2029750 65450 ) ( * 1652570 )
-      NEW met2 ( 2031590 1688780 ) ( 2031750 * )
-      NEW met2 ( 2031750 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 2031590 1652570 ) ( * 1688780 )
-      NEW met2 ( 2774030 1700 ) ( 2774950 * 0 )
-      NEW met1 ( 2029750 65450 ) ( 2774030 * )
-      NEW met2 ( 2774030 1700 ) ( * 65450 )
-      NEW met1 ( 2029750 1652570 ) M1M2_PR
-      NEW met1 ( 2031590 1652570 ) M1M2_PR
-      NEW met1 ( 2029750 65450 ) M1M2_PR
-      NEW met1 ( 2774030 65450 ) M1M2_PR ;
-    - la_data_in[122] ( PIN la_data_in[122] ) ( mprj la_data_in[122] ) + USE SIGNAL
-      + ROUTED met2 ( 2792890 1700 0 ) ( * 32130 )
-      NEW met2 ( 2035730 1688780 ) ( 2037270 * )
-      NEW met2 ( 2037270 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 2035730 32130 ) ( * 1688780 )
-      NEW met1 ( 2035730 32130 ) ( 2792890 * )
-      NEW met1 ( 2035730 32130 ) M1M2_PR
-      NEW met1 ( 2792890 32130 ) M1M2_PR ;
-    - la_data_in[123] ( PIN la_data_in[123] ) ( mprj la_data_in[123] ) + USE SIGNAL
-      + ROUTED met2 ( 2810370 1700 0 ) ( * 31790 )
-      NEW met2 ( 2042630 1688780 ) ( 2042790 * )
-      NEW met2 ( 2042790 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 2042630 31790 ) ( * 1688780 )
-      NEW met1 ( 2042630 31790 ) ( 2810370 * )
-      NEW met1 ( 2042630 31790 ) M1M2_PR
-      NEW met1 ( 2810370 31790 ) M1M2_PR ;
-    - la_data_in[124] ( PIN la_data_in[124] ) ( mprj la_data_in[124] ) + USE SIGNAL
-      + ROUTED met1 ( 2043090 1652570 ) ( 2048150 * )
-      NEW met2 ( 2828310 1700 0 ) ( * 31450 )
-      NEW met2 ( 2043090 31450 ) ( * 1652570 )
-      NEW met2 ( 2048150 1688780 ) ( 2048310 * )
-      NEW met2 ( 2048310 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 2048150 1652570 ) ( * 1688780 )
-      NEW met1 ( 2043090 31450 ) ( 2828310 * )
-      NEW met1 ( 2043090 31450 ) M1M2_PR
-      NEW met1 ( 2043090 1652570 ) M1M2_PR
-      NEW met1 ( 2048150 1652570 ) M1M2_PR
-      NEW met1 ( 2828310 31450 ) M1M2_PR ;
-    - la_data_in[125] ( PIN la_data_in[125] ) ( mprj la_data_in[125] ) + USE SIGNAL
-      + ROUTED met1 ( 2049530 1689290 ) ( 2053830 * )
-      NEW met2 ( 2053830 1689290 ) ( * 1690140 0 )
-      NEW met2 ( 2049530 31110 ) ( * 1689290 )
-      NEW met2 ( 2845790 1700 0 ) ( * 31110 )
-      NEW met1 ( 2049530 31110 ) ( 2845790 * )
-      NEW met1 ( 2049530 31110 ) M1M2_PR
-      NEW met1 ( 2049530 1689290 ) M1M2_PR
-      NEW met1 ( 2053830 1689290 ) M1M2_PR
-      NEW met1 ( 2845790 31110 ) M1M2_PR ;
-    - la_data_in[126] ( PIN la_data_in[126] ) ( mprj la_data_in[126] ) + USE SIGNAL
-      + ROUTED met2 ( 2056890 30940 ) ( * 1676700 )
-      NEW met2 ( 2056890 1676700 ) ( 2058270 * )
-      NEW met2 ( 2058270 1676700 ) ( * 1688780 )
-      NEW met2 ( 2058270 1688780 ) ( 2059350 * )
-      NEW met2 ( 2059350 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 2863730 1700 0 ) ( * 30940 )
-      NEW met3 ( 2056890 30940 ) ( 2863730 * )
-      NEW met2 ( 2056890 30940 ) M2M3_PR
-      NEW met2 ( 2863730 30940 ) M2M3_PR ;
-    - la_data_in[127] ( PIN la_data_in[127] ) ( mprj la_data_in[127] ) + USE SIGNAL
-      + ROUTED met2 ( 2881670 1700 0 ) ( * 30770 )
-      NEW met1 ( 2063330 30770 ) ( 2881670 * )
-      NEW met2 ( 2063330 1688780 ) ( 2064870 * )
-      NEW met2 ( 2064870 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 2063330 30770 ) ( * 1688780 )
-      NEW met1 ( 2063330 30770 ) M1M2_PR
-      NEW met1 ( 2881670 30770 ) M1M2_PR ;
-    - la_data_in[12] ( PIN la_data_in[12] ) ( mprj la_data_in[12] ) + USE SIGNAL
-      + ROUTED met2 ( 842030 1700 0 ) ( * 82450 )
-      NEW met1 ( 842030 82450 ) ( 1429910 * )
-      NEW met2 ( 1429910 1688780 ) ( 1434670 * )
-      NEW met2 ( 1434670 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1429910 82450 ) ( * 1688780 )
-      NEW met1 ( 842030 82450 ) M1M2_PR
-      NEW met1 ( 1429910 82450 ) M1M2_PR ;
-    - la_data_in[13] ( PIN la_data_in[13] ) ( mprj la_data_in[13] ) + USE SIGNAL
-      + ROUTED met2 ( 859970 1700 0 ) ( * 82790 )
-      NEW met2 ( 1436810 1688780 ) ( 1440190 * )
-      NEW met2 ( 1440190 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1436810 82790 ) ( * 1688780 )
-      NEW met1 ( 859970 82790 ) ( 1436810 * )
-      NEW met1 ( 859970 82790 ) M1M2_PR
-      NEW met1 ( 1436810 82790 ) M1M2_PR ;
-    - la_data_in[14] ( PIN la_data_in[14] ) ( mprj la_data_in[14] ) + USE SIGNAL
-      + ROUTED met2 ( 877450 1700 0 ) ( * 23290 )
-      NEW met2 ( 1445550 1677730 ) ( * 1688780 )
-      NEW met2 ( 1445550 1688780 ) ( 1445710 * )
-      NEW met2 ( 1445710 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 877450 23290 ) ( 1294210 * )
-      NEW met2 ( 1294210 23290 ) ( * 1677730 )
-      NEW met1 ( 1294210 1677730 ) ( 1445550 * )
-      NEW met1 ( 877450 23290 ) M1M2_PR
-      NEW met1 ( 1445550 1677730 ) M1M2_PR
-      NEW met1 ( 1294210 23290 ) M1M2_PR
-      NEW met1 ( 1294210 1677730 ) M1M2_PR ;
-    - la_data_in[15] ( PIN la_data_in[15] ) ( mprj la_data_in[15] ) + USE SIGNAL
-      + ROUTED met2 ( 895390 1700 0 ) ( * 22950 )
-      NEW met2 ( 1451070 1678750 ) ( * 1688780 )
-      NEW met2 ( 1451070 1688780 ) ( 1451230 * )
-      NEW met2 ( 1451230 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 895390 22950 ) ( 1293750 * )
-      NEW met2 ( 1293750 22950 ) ( * 1678750 )
-      NEW met1 ( 1293750 1678750 ) ( 1451070 * )
-      NEW met1 ( 895390 22950 ) M1M2_PR
-      NEW met1 ( 1451070 1678750 ) M1M2_PR
-      NEW met1 ( 1293750 22950 ) M1M2_PR
-      NEW met1 ( 1293750 1678750 ) M1M2_PR ;
-    - la_data_in[16] ( PIN la_data_in[16] ) ( mprj la_data_in[16] ) + USE SIGNAL
-      + ROUTED met2 ( 1456590 1688780 ) ( 1456750 * )
-      NEW met2 ( 1456750 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 912870 1700 0 ) ( * 24650 )
-      NEW met1 ( 912870 24650 ) ( 1456590 * )
-      NEW met2 ( 1456590 24650 ) ( * 1688780 )
-      NEW met1 ( 912870 24650 ) M1M2_PR
-      NEW met1 ( 1456590 24650 ) M1M2_PR ;
-    - la_data_in[17] ( PIN la_data_in[17] ) ( mprj la_data_in[17] ) + USE SIGNAL
-      + ROUTED met1 ( 1457050 1649510 ) ( 1462110 * )
-      NEW met2 ( 1462110 1688780 ) ( 1462270 * )
-      NEW met2 ( 1462270 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1462110 1649510 ) ( * 1688780 )
-      NEW met2 ( 930810 1700 0 ) ( * 24990 )
-      NEW met1 ( 930810 24990 ) ( 1457050 * )
-      NEW met2 ( 1457050 24990 ) ( * 1649510 )
-      NEW met1 ( 1457050 1649510 ) M1M2_PR
-      NEW met1 ( 1462110 1649510 ) M1M2_PR
-      NEW met1 ( 930810 24990 ) M1M2_PR
-      NEW met1 ( 1457050 24990 ) M1M2_PR ;
-    - la_data_in[18] ( PIN la_data_in[18] ) ( mprj la_data_in[18] ) + USE SIGNAL
-      + ROUTED met1 ( 1463030 1688950 ) ( 1467790 * )
-      NEW met2 ( 1467790 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1463030 25330 ) ( * 1688950 )
-      NEW met2 ( 948750 1700 0 ) ( * 25330 )
-      NEW met1 ( 948750 25330 ) ( 1463030 * )
-      NEW met1 ( 1463030 25330 ) M1M2_PR
-      NEW met1 ( 1463030 1688950 ) M1M2_PR
-      NEW met1 ( 1467790 1688950 ) M1M2_PR
-      NEW met1 ( 948750 25330 ) M1M2_PR ;
-    - la_data_in[19] ( PIN la_data_in[19] ) ( mprj la_data_in[19] ) + USE SIGNAL
-      + ROUTED met2 ( 966230 1700 0 ) ( * 25670 )
-      NEW met1 ( 1469930 1683510 ) ( 1473150 * )
-      NEW met2 ( 1473150 1683510 ) ( * 1688780 )
-      NEW met2 ( 1473150 1688780 ) ( 1473310 * )
-      NEW met2 ( 1473310 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1469930 25670 ) ( * 1683510 )
-      NEW met1 ( 966230 25670 ) ( 1469930 * )
-      NEW met1 ( 966230 25670 ) M1M2_PR
-      NEW met1 ( 1469930 25670 ) M1M2_PR
-      NEW met1 ( 1469930 1683510 ) M1M2_PR
-      NEW met1 ( 1473150 1683510 ) M1M2_PR ;
-    - la_data_in[1] ( PIN la_data_in[1] ) ( mprj la_data_in[1] ) + USE SIGNAL
-      + ROUTED met2 ( 1373330 1688780 ) ( 1374410 * )
-      NEW met2 ( 1374410 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1373330 23970 ) ( * 1688780 )
-      NEW met2 ( 646990 1700 0 ) ( * 23970 )
-      NEW met1 ( 646990 23970 ) ( 1373330 * )
-      NEW met1 ( 1373330 23970 ) M1M2_PR
-      NEW met1 ( 646990 23970 ) M1M2_PR ;
-    - la_data_in[20] ( PIN la_data_in[20] ) ( mprj la_data_in[20] ) + USE SIGNAL
-      + ROUTED met2 ( 984170 1700 0 ) ( * 26010 )
-      NEW met2 ( 1476830 1688780 ) ( 1478370 * )
-      NEW met2 ( 1478370 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1476830 26010 ) ( * 1688780 )
-      NEW met1 ( 984170 26010 ) ( 1476830 * )
-      NEW met1 ( 984170 26010 ) M1M2_PR
-      NEW met1 ( 1476830 26010 ) M1M2_PR ;
-    - la_data_in[21] ( PIN la_data_in[21] ) ( mprj la_data_in[21] ) + USE SIGNAL
-      + ROUTED met2 ( 1001650 1700 0 ) ( * 26350 )
-      NEW met2 ( 1484190 82800 ) ( 1484650 * )
-      NEW met2 ( 1484650 26350 ) ( * 82800 )
-      NEW met2 ( 1483960 1688780 ) ( 1484190 * )
-      NEW met2 ( 1483960 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1484190 82800 ) ( * 1688780 )
-      NEW met1 ( 1001650 26350 ) ( 1484650 * )
-      NEW met1 ( 1001650 26350 ) M1M2_PR
-      NEW met1 ( 1484650 26350 ) M1M2_PR ;
-    - la_data_in[22] ( PIN la_data_in[22] ) ( mprj la_data_in[22] ) + USE SIGNAL
-      + ROUTED met2 ( 1483270 26690 ) ( * 27540 )
-      NEW met2 ( 1019590 1700 0 ) ( * 26690 )
-      NEW met2 ( 1483270 27540 ) ( 1483730 * )
-      NEW met1 ( 1483730 1645770 ) ( 1489250 * )
-      NEW met2 ( 1483730 27540 ) ( * 1645770 )
-      NEW met2 ( 1489250 1688780 ) ( 1489410 * )
-      NEW met2 ( 1489410 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1489250 1645770 ) ( * 1688780 )
-      NEW met1 ( 1019590 26690 ) ( 1483270 * )
-      NEW met1 ( 1483270 26690 ) M1M2_PR
-      NEW met1 ( 1019590 26690 ) M1M2_PR
-      NEW met1 ( 1483730 1645770 ) M1M2_PR
-      NEW met1 ( 1489250 1645770 ) M1M2_PR ;
-    - la_data_in[23] ( PIN la_data_in[23] ) ( mprj la_data_in[23] ) + USE SIGNAL
-      + ROUTED met2 ( 1037070 1700 0 ) ( * 24140 )
-      NEW met3 ( 1037070 24140 ) ( 1386900 * )
-      NEW met3 ( 1386900 24140 ) ( * 24820 )
-      NEW met2 ( 1490170 1652060 ) ( 1490630 * )
-      NEW met2 ( 1490170 1652060 ) ( * 1652740 )
-      NEW met2 ( 1490170 1652740 ) ( 1491090 * )
-      NEW met2 ( 1490630 24820 ) ( * 1652060 )
-      NEW met1 ( 1491090 1688270 ) ( 1494930 * )
-      NEW met1 ( 1494930 1688270 ) ( * 1689290 )
-      NEW met2 ( 1494930 1689290 ) ( * 1690140 0 )
-      NEW met2 ( 1491090 1652740 ) ( * 1688270 )
-      NEW met3 ( 1386900 24820 ) ( 1490630 * )
-      NEW met2 ( 1037070 24140 ) M2M3_PR
-      NEW met2 ( 1490630 24820 ) M2M3_PR
-      NEW met1 ( 1491090 1688270 ) M1M2_PR
-      NEW met1 ( 1494930 1689290 ) M1M2_PR ;
-    - la_data_in[24] ( PIN la_data_in[24] ) ( mprj la_data_in[24] ) + USE SIGNAL
-      + ROUTED met2 ( 1055010 1700 0 ) ( * 27030 )
-      NEW met1 ( 1497530 1689290 ) ( 1500450 * )
-      NEW met2 ( 1500450 1689290 ) ( * 1690140 0 )
-      NEW met2 ( 1497530 27030 ) ( * 1689290 )
-      NEW met1 ( 1055010 27030 ) ( 1497530 * )
-      NEW met1 ( 1055010 27030 ) M1M2_PR
-      NEW met1 ( 1497530 27030 ) M1M2_PR
-      NEW met1 ( 1497530 1689290 ) M1M2_PR
-      NEW met1 ( 1500450 1689290 ) M1M2_PR ;
-    - la_data_in[25] ( PIN la_data_in[25] ) ( mprj la_data_in[25] ) + USE SIGNAL
-      + ROUTED met2 ( 1072490 1700 0 ) ( * 27370 )
-      NEW met2 ( 1504430 1689460 ) ( 1505970 * )
-      NEW met2 ( 1505970 1689460 ) ( * 1690140 0 )
-      NEW met2 ( 1504430 27370 ) ( * 1689460 )
-      NEW met1 ( 1072490 27370 ) ( 1504430 * )
-      NEW met1 ( 1072490 27370 ) M1M2_PR
-      NEW met1 ( 1504430 27370 ) M1M2_PR ;
-    - la_data_in[26] ( PIN la_data_in[26] ) ( mprj la_data_in[26] ) + USE SIGNAL
-      + ROUTED met2 ( 1090430 1700 0 ) ( * 23630 )
-      NEW met2 ( 1511330 1688780 ) ( 1511490 * )
-      NEW met2 ( 1511490 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1511330 23630 ) ( * 1688780 )
-      NEW met1 ( 1090430 23630 ) ( 1511330 * )
-      NEW met1 ( 1090430 23630 ) M1M2_PR
-      NEW met1 ( 1511330 23630 ) M1M2_PR ;
-    - la_data_in[27] ( PIN la_data_in[27] ) ( mprj la_data_in[27] ) + USE SIGNAL
-      + ROUTED met2 ( 1105610 1700 ) ( 1107910 * 0 )
-      NEW met2 ( 1105610 1700 ) ( * 79050 )
-      NEW met1 ( 1105610 79050 ) ( 1512710 * )
-      NEW met2 ( 1512710 79050 ) ( * 1580100 )
-      NEW met2 ( 1512710 1580100 ) ( 1516850 * )
-      NEW met2 ( 1516850 1688780 ) ( 1517010 * )
-      NEW met2 ( 1517010 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1516850 1580100 ) ( * 1688780 )
-      NEW met1 ( 1105610 79050 ) M1M2_PR
-      NEW met1 ( 1512710 79050 ) M1M2_PR ;
-    - la_data_in[28] ( PIN la_data_in[28] ) ( mprj la_data_in[28] ) + USE SIGNAL
-      + ROUTED met2 ( 1125850 1700 0 ) ( * 78710 )
-      NEW met1 ( 1125850 78710 ) ( 1519610 * )
-      NEW met2 ( 1519610 78710 ) ( * 1580100 )
-      NEW met2 ( 1519610 1580100 ) ( 1522370 * )
-      NEW met2 ( 1522370 1688780 ) ( 1522530 * )
-      NEW met2 ( 1522530 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1522370 1580100 ) ( * 1688780 )
-      NEW met1 ( 1125850 78710 ) M1M2_PR
-      NEW met1 ( 1519610 78710 ) M1M2_PR ;
-    - la_data_in[29] ( PIN la_data_in[29] ) ( mprj la_data_in[29] ) + USE SIGNAL
-      + ROUTED met2 ( 1141490 1700 ) ( 1143790 * 0 )
-      NEW met2 ( 1141490 1700 ) ( * 78370 )
-      NEW met1 ( 1141490 78370 ) ( 1526510 * )
-      NEW met2 ( 1526510 1688780 ) ( 1528050 * )
-      NEW met2 ( 1528050 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1526510 78370 ) ( * 1688780 )
-      NEW met1 ( 1141490 78370 ) M1M2_PR
-      NEW met1 ( 1526510 78370 ) M1M2_PR ;
-    - la_data_in[2] ( PIN la_data_in[2] ) ( mprj la_data_in[2] ) + USE SIGNAL
-      + ROUTED met2 ( 664930 1700 0 ) ( * 24310 )
-      NEW met1 ( 1373790 1652570 ) ( 1379770 * )
-      NEW met2 ( 1373790 24310 ) ( * 1652570 )
-      NEW met2 ( 1379770 1688780 ) ( 1379930 * )
-      NEW met2 ( 1379930 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1379770 1652570 ) ( * 1688780 )
-      NEW met1 ( 664930 24310 ) ( 1373790 * )
-      NEW met1 ( 664930 24310 ) M1M2_PR
-      NEW met1 ( 1373790 24310 ) M1M2_PR
-      NEW met1 ( 1373790 1652570 ) M1M2_PR
-      NEW met1 ( 1379770 1652570 ) M1M2_PR ;
-    - la_data_in[30] ( PIN la_data_in[30] ) ( mprj la_data_in[30] ) + USE SIGNAL
-      + ROUTED met2 ( 1161270 1700 0 ) ( * 29750 )
-      NEW met2 ( 1532490 1688780 ) ( 1533570 * )
-      NEW met2 ( 1533570 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1532490 29750 ) ( * 1688780 )
-      NEW met1 ( 1161270 29750 ) ( 1290300 * )
-      NEW met1 ( 1290300 29070 ) ( * 29750 )
-      NEW met1 ( 1290300 29070 ) ( 1414500 * )
-      NEW met1 ( 1414500 29070 ) ( * 29750 )
-      NEW met1 ( 1414500 29750 ) ( 1532490 * )
-      NEW met1 ( 1161270 29750 ) M1M2_PR
-      NEW met1 ( 1532490 29750 ) M1M2_PR ;
-    - la_data_in[31] ( PIN la_data_in[31] ) ( mprj la_data_in[31] ) + USE SIGNAL
-      + ROUTED met2 ( 1179210 1700 0 ) ( * 31110 )
-      NEW met1 ( 1532030 1652230 ) ( 1538470 * )
-      NEW met2 ( 1532030 31110 ) ( * 1652230 )
-      NEW met2 ( 1538470 1688780 ) ( 1538630 * )
-      NEW met2 ( 1538630 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1538470 1652230 ) ( * 1688780 )
-      NEW met1 ( 1179210 31110 ) ( 1532030 * )
-      NEW met1 ( 1179210 31110 ) M1M2_PR
-      NEW met1 ( 1532030 31110 ) M1M2_PR
-      NEW met1 ( 1532030 1652230 ) M1M2_PR
-      NEW met1 ( 1538470 1652230 ) M1M2_PR ;
-    - la_data_in[32] ( PIN la_data_in[32] ) ( mprj la_data_in[32] ) + USE SIGNAL
-      + ROUTED met1 ( 1538930 1683850 ) ( 1543990 * )
-      NEW met2 ( 1543990 1683850 ) ( * 1688780 )
-      NEW met2 ( 1543990 1688780 ) ( 1544150 * )
-      NEW met2 ( 1544150 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1538930 31790 ) ( * 1683850 )
-      NEW met2 ( 1196690 1700 0 ) ( * 31790 )
-      NEW met1 ( 1196690 31790 ) ( 1538930 * )
-      NEW met1 ( 1538930 31790 ) M1M2_PR
-      NEW met1 ( 1538930 1683850 ) M1M2_PR
-      NEW met1 ( 1543990 1683850 ) M1M2_PR
-      NEW met1 ( 1196690 31790 ) M1M2_PR ;
-    - la_data_in[33] ( PIN la_data_in[33] ) ( mprj la_data_in[33] ) + USE SIGNAL
-      + ROUTED met1 ( 1546290 1652570 ) ( 1549510 * )
-      NEW met2 ( 1546290 17510 ) ( * 1652570 )
-      NEW met2 ( 1549510 1688780 ) ( 1549670 * )
-      NEW met2 ( 1549670 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1549510 1652570 ) ( * 1688780 )
-      NEW met2 ( 1214630 1700 0 ) ( * 17510 )
-      NEW met1 ( 1214630 17510 ) ( 1546290 * )
-      NEW met1 ( 1546290 17510 ) M1M2_PR
-      NEW met1 ( 1546290 1652570 ) M1M2_PR
-      NEW met1 ( 1549510 1652570 ) M1M2_PR
-      NEW met1 ( 1214630 17510 ) M1M2_PR ;
-    - la_data_in[34] ( PIN la_data_in[34] ) ( mprj la_data_in[34] ) + USE SIGNAL
-      + ROUTED met1 ( 1552730 1688950 ) ( 1555190 * )
-      NEW met2 ( 1555190 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1552730 17850 ) ( * 1688950 )
-      NEW met2 ( 1232110 1700 0 ) ( * 17850 )
-      NEW met1 ( 1232110 17850 ) ( 1552730 * )
-      NEW met1 ( 1552730 17850 ) M1M2_PR
-      NEW met1 ( 1552730 1688950 ) M1M2_PR
-      NEW met1 ( 1555190 1688950 ) M1M2_PR
-      NEW met1 ( 1232110 17850 ) M1M2_PR ;
-    - la_data_in[35] ( PIN la_data_in[35] ) ( mprj la_data_in[35] ) + USE SIGNAL
-      + ROUTED met2 ( 1250050 1700 0 ) ( * 20230 )
-      NEW met2 ( 1559630 1680110 ) ( * 1689460 )
-      NEW met2 ( 1559630 1689460 ) ( 1560710 * )
-      NEW met2 ( 1560710 1689460 ) ( * 1690140 0 )
-      NEW met1 ( 1250050 20230 ) ( 1300650 * )
-      NEW met2 ( 1300650 20230 ) ( * 1680110 )
-      NEW met1 ( 1300650 1680110 ) ( 1559630 * )
-      NEW met1 ( 1250050 20230 ) M1M2_PR
-      NEW met1 ( 1559630 1680110 ) M1M2_PR
-      NEW met1 ( 1300650 20230 ) M1M2_PR
-      NEW met1 ( 1300650 1680110 ) M1M2_PR ;
-    - la_data_in[36] ( PIN la_data_in[36] ) ( mprj la_data_in[36] ) + USE SIGNAL
-      + ROUTED met2 ( 1267530 1700 0 ) ( * 16490 )
-      NEW met2 ( 1555030 1680620 ) ( * 1680790 )
-      NEW met2 ( 1555030 1680620 ) ( 1555950 * )
-      NEW met2 ( 1555950 1680450 ) ( * 1680620 )
-      NEW met1 ( 1555950 1680450 ) ( 1566070 * )
-      NEW met2 ( 1566070 1680450 ) ( * 1688780 )
-      NEW met2 ( 1566070 1688780 ) ( 1566230 * )
-      NEW met2 ( 1566230 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1267530 16490 ) ( 1307550 * )
-      NEW met2 ( 1307550 16490 ) ( * 1680790 )
-      NEW met1 ( 1307550 1680790 ) ( 1555030 * )
-      NEW met1 ( 1267530 16490 ) M1M2_PR
-      NEW met1 ( 1555030 1680790 ) M1M2_PR
-      NEW met1 ( 1555950 1680450 ) M1M2_PR
-      NEW met1 ( 1566070 1680450 ) M1M2_PR
-      NEW met1 ( 1307550 16490 ) M1M2_PR
-      NEW met1 ( 1307550 1680790 ) M1M2_PR ;
-    - la_data_in[37] ( PIN la_data_in[37] ) ( mprj la_data_in[37] ) + USE SIGNAL
-      + ROUTED met2 ( 1285470 1700 0 ) ( * 15810 )
-      NEW met1 ( 1552270 1681130 ) ( * 1681470 )
-      NEW met1 ( 1552270 1681470 ) ( 1571590 * )
-      NEW met2 ( 1571590 1681470 ) ( * 1688780 )
-      NEW met2 ( 1571590 1688780 ) ( 1571750 * )
-      NEW met2 ( 1571750 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1285470 15810 ) ( 1321350 * )
-      NEW met2 ( 1321350 15810 ) ( * 1681130 )
-      NEW met1 ( 1321350 1681130 ) ( 1552270 * )
-      NEW met1 ( 1285470 15810 ) M1M2_PR
-      NEW met1 ( 1571590 1681470 ) M1M2_PR
-      NEW met1 ( 1321350 15810 ) M1M2_PR
-      NEW met1 ( 1321350 1681130 ) M1M2_PR ;
-    - la_data_in[38] ( PIN la_data_in[38] ) ( mprj la_data_in[38] ) + USE SIGNAL
-      + ROUTED met2 ( 1574810 21930 ) ( * 1580100 )
-      NEW met2 ( 1574810 1580100 ) ( 1576190 * )
-      NEW met2 ( 1576190 1688780 ) ( 1577270 * )
-      NEW met2 ( 1577270 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1576190 1580100 ) ( * 1688780 )
-      NEW met2 ( 1303410 1700 0 ) ( * 19890 )
-      NEW met2 ( 1456590 19890 ) ( * 21930 )
-      NEW met1 ( 1303410 19890 ) ( 1456590 * )
-      NEW met1 ( 1456590 21930 ) ( 1574810 * )
-      NEW met1 ( 1574810 21930 ) M1M2_PR
-      NEW met1 ( 1303410 19890 ) M1M2_PR
-      NEW met1 ( 1456590 19890 ) M1M2_PR
-      NEW met1 ( 1456590 21930 ) M1M2_PR ;
-    - la_data_in[39] ( PIN la_data_in[39] ) ( mprj la_data_in[39] ) + USE SIGNAL
-      + ROUTED met2 ( 1320890 1700 0 ) ( * 20230 )
-      NEW met1 ( 1580790 1688950 ) ( * 1689290 )
-      NEW met1 ( 1580790 1689290 ) ( 1582790 * )
-      NEW met2 ( 1582790 1689290 ) ( * 1690140 0 )
-      NEW met2 ( 1580790 22610 ) ( * 1688950 )
-      NEW met2 ( 1457050 20230 ) ( * 22610 )
-      NEW met1 ( 1320890 20230 ) ( 1457050 * )
-      NEW met1 ( 1457050 22610 ) ( 1580790 * )
-      NEW met1 ( 1320890 20230 ) M1M2_PR
-      NEW met1 ( 1580790 22610 ) M1M2_PR
-      NEW met1 ( 1580790 1688950 ) M1M2_PR
-      NEW met1 ( 1582790 1689290 ) M1M2_PR
-      NEW met1 ( 1457050 20230 ) M1M2_PR
-      NEW met1 ( 1457050 22610 ) M1M2_PR ;
-    - la_data_in[3] ( PIN la_data_in[3] ) ( mprj la_data_in[3] ) + USE SIGNAL
-      + ROUTED met2 ( 682410 1700 0 ) ( * 30430 )
-      NEW met1 ( 1380690 1688950 ) ( 1385450 * )
-      NEW met2 ( 1385450 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1380690 30430 ) ( * 1688950 )
-      NEW met1 ( 682410 30430 ) ( 1380690 * )
-      NEW met1 ( 682410 30430 ) M1M2_PR
-      NEW met1 ( 1380690 30430 ) M1M2_PR
-      NEW met1 ( 1380690 1688950 ) M1M2_PR
-      NEW met1 ( 1385450 1688950 ) M1M2_PR ;
-    - la_data_in[40] ( PIN la_data_in[40] ) ( mprj la_data_in[40] ) + USE SIGNAL
-      + ROUTED met2 ( 1338830 1700 0 ) ( * 16830 )
-      NEW met2 ( 1469930 16830 ) ( * 22270 )
-      NEW met1 ( 1469930 22270 ) ( 1588150 * )
-      NEW met2 ( 1588150 1688780 ) ( 1588310 * )
-      NEW met2 ( 1588310 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1588150 22270 ) ( * 1688780 )
-      NEW met1 ( 1338830 16830 ) ( 1469930 * )
-      NEW met1 ( 1338830 16830 ) M1M2_PR
-      NEW met1 ( 1469930 16830 ) M1M2_PR
-      NEW met1 ( 1469930 22270 ) M1M2_PR
-      NEW met1 ( 1588150 22270 ) M1M2_PR ;
-    - la_data_in[41] ( PIN la_data_in[41] ) ( mprj la_data_in[41] ) + USE SIGNAL
-      + ROUTED met2 ( 1356310 1700 0 ) ( * 20570 )
-      NEW met2 ( 1490170 20570 ) ( * 26690 )
-      NEW met1 ( 1490170 26690 ) ( 1587690 * )
-      NEW met1 ( 1587690 1688950 ) ( 1593830 * )
-      NEW met2 ( 1593830 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1587690 26690 ) ( * 1688950 )
-      NEW met1 ( 1356310 20570 ) ( 1490170 * )
-      NEW met1 ( 1356310 20570 ) M1M2_PR
-      NEW met1 ( 1490170 20570 ) M1M2_PR
-      NEW met1 ( 1490170 26690 ) M1M2_PR
-      NEW met1 ( 1587690 26690 ) M1M2_PR
-      NEW met1 ( 1587690 1688950 ) M1M2_PR
-      NEW met1 ( 1593830 1688950 ) M1M2_PR ;
-    - la_data_in[42] ( PIN la_data_in[42] ) ( mprj la_data_in[42] ) + USE SIGNAL
-      + ROUTED met2 ( 1374250 1700 0 ) ( * 23970 )
-      NEW met1 ( 1594590 1688950 ) ( 1598890 * )
-      NEW met2 ( 1598890 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1594590 23970 ) ( * 1688950 )
-      NEW met1 ( 1374250 23970 ) ( 1594590 * )
-      NEW met1 ( 1374250 23970 ) M1M2_PR
-      NEW met1 ( 1594590 23970 ) M1M2_PR
-      NEW met1 ( 1594590 1688950 ) M1M2_PR
-      NEW met1 ( 1598890 1688950 ) M1M2_PR ;
-    - la_data_in[43] ( PIN la_data_in[43] ) ( mprj la_data_in[43] ) + USE SIGNAL
-      + ROUTED met2 ( 1391730 1700 0 ) ( * 24310 )
-      NEW met2 ( 1601950 1688780 ) ( 1604410 * )
-      NEW met2 ( 1604410 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1601950 24310 ) ( * 1688780 )
-      NEW met1 ( 1391730 24310 ) ( 1601950 * )
-      NEW met1 ( 1391730 24310 ) M1M2_PR
-      NEW met1 ( 1601950 24310 ) M1M2_PR ;
-    - la_data_in[44] ( PIN la_data_in[44] ) ( mprj la_data_in[44] ) + USE SIGNAL
-      + ROUTED met2 ( 1409670 1700 0 ) ( * 15810 )
-      NEW met2 ( 1489710 15810 ) ( * 26010 )
-      NEW met1 ( 1489710 26010 ) ( 1608850 * )
-      NEW met2 ( 1608850 1688780 ) ( 1609930 * )
-      NEW met2 ( 1609930 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1608850 26010 ) ( * 1688780 )
-      NEW met1 ( 1409670 15810 ) ( 1489710 * )
-      NEW met1 ( 1409670 15810 ) M1M2_PR
-      NEW met1 ( 1489710 15810 ) M1M2_PR
-      NEW met1 ( 1489710 26010 ) M1M2_PR
-      NEW met1 ( 1608850 26010 ) M1M2_PR ;
-    - la_data_in[45] ( PIN la_data_in[45] ) ( mprj la_data_in[45] ) + USE SIGNAL
-      + ROUTED met2 ( 1615290 1688780 ) ( 1615450 * )
-      NEW met2 ( 1615450 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1615290 23290 ) ( * 1688780 )
-      NEW met2 ( 1427150 1700 0 ) ( * 23290 )
-      NEW met1 ( 1427150 23290 ) ( 1615290 * )
-      NEW met1 ( 1615290 23290 ) M1M2_PR
-      NEW met1 ( 1427150 23290 ) M1M2_PR ;
-    - la_data_in[46] ( PIN la_data_in[46] ) ( mprj la_data_in[46] ) + USE SIGNAL
-      + ROUTED met1 ( 1615750 1652570 ) ( 1620810 * )
-      NEW met2 ( 1615750 22950 ) ( * 1652570 )
-      NEW met2 ( 1620810 1688780 ) ( 1620970 * )
-      NEW met2 ( 1620970 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1620810 1652570 ) ( * 1688780 )
-      NEW met2 ( 1445090 1700 0 ) ( * 22950 )
-      NEW met1 ( 1445090 22950 ) ( 1615750 * )
-      NEW met1 ( 1615750 22950 ) M1M2_PR
-      NEW met1 ( 1615750 1652570 ) M1M2_PR
-      NEW met1 ( 1620810 1652570 ) M1M2_PR
-      NEW met1 ( 1445090 22950 ) M1M2_PR ;
-    - la_data_in[47] ( PIN la_data_in[47] ) ( mprj la_data_in[47] ) + USE SIGNAL
-      + ROUTED met2 ( 1463030 1700 0 ) ( * 24650 )
-      NEW met1 ( 1463030 24650 ) ( 1622190 * )
-      NEW met1 ( 1622190 1688950 ) ( 1626490 * )
-      NEW met2 ( 1626490 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1622190 24650 ) ( * 1688950 )
-      NEW met1 ( 1463030 24650 ) M1M2_PR
-      NEW met1 ( 1622190 24650 ) M1M2_PR
-      NEW met1 ( 1622190 1688950 ) M1M2_PR
-      NEW met1 ( 1626490 1688950 ) M1M2_PR ;
-    - la_data_in[48] ( PIN la_data_in[48] ) ( mprj la_data_in[48] ) + USE SIGNAL
-      + ROUTED met2 ( 1480510 1700 0 ) ( * 24990 )
-      NEW met2 ( 1629090 1688780 ) ( 1632010 * )
-      NEW met2 ( 1632010 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1629090 24990 ) ( * 1688780 )
-      NEW met1 ( 1480510 24990 ) ( 1629090 * )
-      NEW met1 ( 1480510 24990 ) M1M2_PR
-      NEW met1 ( 1629090 24990 ) M1M2_PR ;
-    - la_data_in[49] ( PIN la_data_in[49] ) ( mprj la_data_in[49] ) + USE SIGNAL
-      + ROUTED met2 ( 1636450 1688780 ) ( 1637530 * )
-      NEW met2 ( 1637530 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1636450 25330 ) ( * 1688780 )
-      NEW met2 ( 1498450 1700 0 ) ( * 25330 )
-      NEW met1 ( 1498450 25330 ) ( 1636450 * )
-      NEW met1 ( 1636450 25330 ) M1M2_PR
-      NEW met1 ( 1498450 25330 ) M1M2_PR ;
-    - la_data_in[4] ( PIN la_data_in[4] ) ( mprj la_data_in[4] ) + USE SIGNAL
-      + ROUTED met2 ( 700350 1700 0 ) ( * 30090 )
-      NEW met1 ( 1362290 29410 ) ( * 30090 )
-      NEW met1 ( 700350 30090 ) ( 1362290 * )
-      NEW met1 ( 1362290 29410 ) ( 1387130 * )
-      NEW met1 ( 1387130 1652570 ) ( 1390810 * )
-      NEW met2 ( 1387130 29410 ) ( * 1652570 )
-      NEW met2 ( 1390810 1688780 ) ( 1390970 * )
-      NEW met2 ( 1390970 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1390810 1652570 ) ( * 1688780 )
-      NEW met1 ( 700350 30090 ) M1M2_PR
-      NEW met1 ( 1387130 29410 ) M1M2_PR
-      NEW met1 ( 1387130 1652570 ) M1M2_PR
-      NEW met1 ( 1390810 1652570 ) M1M2_PR ;
-    - la_data_in[50] ( PIN la_data_in[50] ) ( mprj la_data_in[50] ) + USE SIGNAL
-      + ROUTED met2 ( 1643120 1688780 ) ( 1643350 * )
-      NEW met2 ( 1643120 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1643350 25670 ) ( * 1688780 )
-      NEW met2 ( 1515930 1700 0 ) ( * 25670 )
-      NEW met1 ( 1515930 25670 ) ( 1643350 * )
-      NEW met1 ( 1643350 25670 ) M1M2_PR
-      NEW met1 ( 1515930 25670 ) M1M2_PR ;
-    - la_data_in[51] ( PIN la_data_in[51] ) ( mprj la_data_in[51] ) + USE SIGNAL
-      + ROUTED met2 ( 1533870 1700 0 ) ( * 26350 )
-      NEW met2 ( 1643810 1688780 ) ( 1648570 * )
-      NEW met2 ( 1648570 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1643810 26350 ) ( * 1688780 )
-      NEW met1 ( 1533870 26350 ) ( 1643810 * )
-      NEW met1 ( 1533870 26350 ) M1M2_PR
-      NEW met1 ( 1643810 26350 ) M1M2_PR ;
-    - la_data_in[52] ( PIN la_data_in[52] ) ( mprj la_data_in[52] ) + USE SIGNAL
-      + ROUTED met2 ( 1549050 1700 ) ( 1551350 * 0 )
-      NEW met2 ( 1549050 1700 ) ( * 3060 )
-      NEW met2 ( 1545830 3060 ) ( 1549050 * )
-      NEW met2 ( 1545830 3060 ) ( * 1679770 )
-      NEW met2 ( 1653930 1679770 ) ( * 1688780 )
-      NEW met2 ( 1653930 1688780 ) ( 1654090 * )
-      NEW met2 ( 1654090 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1545830 1679770 ) ( 1653930 * )
-      NEW met1 ( 1545830 1679770 ) M1M2_PR
-      NEW met1 ( 1653930 1679770 ) M1M2_PR ;
-    - la_data_in[53] ( PIN la_data_in[53] ) ( mprj la_data_in[53] ) + USE SIGNAL
-      + ROUTED met2 ( 1569290 1700 0 ) ( * 17340 )
-      NEW met2 ( 1566530 17340 ) ( 1569290 * )
-      NEW met2 ( 1566530 17340 ) ( * 1680110 )
-      NEW met2 ( 1658990 1680110 ) ( * 1688780 )
-      NEW met2 ( 1658990 1688780 ) ( 1659150 * )
-      NEW met2 ( 1659150 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1566530 1680110 ) ( 1658990 * )
-      NEW met1 ( 1566530 1680110 ) M1M2_PR
-      NEW met1 ( 1658990 1680110 ) M1M2_PR ;
-    - la_data_in[54] ( PIN la_data_in[54] ) ( mprj la_data_in[54] ) + USE SIGNAL
-      + ROUTED met2 ( 1664510 1681130 ) ( * 1688780 )
-      NEW met2 ( 1664510 1688780 ) ( 1664670 * )
-      NEW met2 ( 1664670 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1582170 82800 ) ( 1586770 * )
-      NEW met2 ( 1586770 1700 0 ) ( * 82800 )
-      NEW met1 ( 1628400 1681130 ) ( 1664510 * )
-      NEW met1 ( 1582170 1681470 ) ( 1628400 * )
-      NEW met1 ( 1628400 1681130 ) ( * 1681470 )
-      NEW met2 ( 1582170 82800 ) ( * 1681470 )
-      NEW met1 ( 1664510 1681130 ) M1M2_PR
-      NEW met1 ( 1582170 1681470 ) M1M2_PR ;
-    - la_data_in[55] ( PIN la_data_in[55] ) ( mprj la_data_in[55] ) + USE SIGNAL
-      + ROUTED met2 ( 1670260 1688780 ) ( 1671410 * )
-      NEW met2 ( 1670260 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1671410 16490 ) ( * 1688780 )
-      NEW met2 ( 1604710 1700 0 ) ( * 16490 )
-      NEW met1 ( 1604710 16490 ) ( 1671410 * )
-      NEW met1 ( 1671410 16490 ) M1M2_PR
-      NEW met1 ( 1604710 16490 ) M1M2_PR ;
-    - la_data_in[56] ( PIN la_data_in[56] ) ( mprj la_data_in[56] ) + USE SIGNAL
-      + ROUTED met1 ( 1645190 15470 ) ( * 16150 )
-      NEW met1 ( 1645190 15470 ) ( 1670950 * )
-      NEW met1 ( 1670950 1652230 ) ( 1675550 * )
-      NEW met2 ( 1670950 15470 ) ( * 1652230 )
-      NEW met2 ( 1675550 1688780 ) ( 1675710 * )
-      NEW met2 ( 1675710 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1675550 1652230 ) ( * 1688780 )
-      NEW met2 ( 1622190 1700 0 ) ( * 16150 )
-      NEW met1 ( 1622190 16150 ) ( 1645190 * )
-      NEW met1 ( 1670950 15470 ) M1M2_PR
-      NEW met1 ( 1670950 1652230 ) M1M2_PR
-      NEW met1 ( 1675550 1652230 ) M1M2_PR
-      NEW met1 ( 1622190 16150 ) M1M2_PR ;
-    - la_data_in[57] ( PIN la_data_in[57] ) ( mprj la_data_in[57] ) + USE SIGNAL
-      + ROUTED met2 ( 1640130 1700 0 ) ( * 17340 )
-      NEW met2 ( 1635530 17340 ) ( 1640130 * )
-      NEW met2 ( 1635530 17340 ) ( * 1680790 )
-      NEW met2 ( 1679690 1680790 ) ( * 1689290 )
-      NEW met2 ( 1679690 1689290 ) ( 1681230 * )
-      NEW met2 ( 1681230 1689290 ) ( * 1690140 0 )
-      NEW met1 ( 1635530 1680790 ) ( 1679690 * )
-      NEW met1 ( 1635530 1680790 ) M1M2_PR
-      NEW met1 ( 1679690 1680790 ) M1M2_PR ;
-    - la_data_in[58] ( PIN la_data_in[58] ) ( mprj la_data_in[58] ) + USE SIGNAL
-      + ROUTED met2 ( 1658070 1700 0 ) ( * 19550 )
-      NEW met1 ( 1658070 19550 ) ( 1684290 * )
-      NEW met1 ( 1684290 1688950 ) ( 1686750 * )
-      NEW met2 ( 1686750 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1684290 19550 ) ( * 1688950 )
-      NEW met1 ( 1658070 19550 ) M1M2_PR
-      NEW met1 ( 1684290 19550 ) M1M2_PR
-      NEW met1 ( 1684290 1688950 ) M1M2_PR
-      NEW met1 ( 1686750 1688950 ) M1M2_PR ;
-    - la_data_in[59] ( PIN la_data_in[59] ) ( mprj la_data_in[59] ) + USE SIGNAL
-      + ROUTED met2 ( 1675550 1700 0 ) ( * 18530 )
-      NEW met1 ( 1675550 18530 ) ( 1691190 * )
-      NEW met2 ( 1691190 1688780 ) ( 1692270 * )
-      NEW met2 ( 1692270 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1691190 18530 ) ( * 1688780 )
-      NEW met1 ( 1675550 18530 ) M1M2_PR
-      NEW met1 ( 1691190 18530 ) M1M2_PR ;
-    - la_data_in[5] ( PIN la_data_in[5] ) ( mprj la_data_in[5] ) + USE SIGNAL
-      + ROUTED met2 ( 717830 1700 0 ) ( * 34500 )
-      NEW met2 ( 717830 34500 ) ( 718290 * )
-      NEW met2 ( 718290 34500 ) ( * 81430 )
-      NEW met1 ( 718290 81430 ) ( 1394030 * )
-      NEW met1 ( 1394030 1689290 ) ( 1396490 * )
-      NEW met2 ( 1396490 1689290 ) ( * 1690140 0 )
-      NEW met2 ( 1394030 81430 ) ( * 1689290 )
-      NEW met1 ( 718290 81430 ) M1M2_PR
-      NEW met1 ( 1394030 81430 ) M1M2_PR
-      NEW met1 ( 1394030 1689290 ) M1M2_PR
-      NEW met1 ( 1396490 1689290 ) M1M2_PR ;
-    - la_data_in[60] ( PIN la_data_in[60] ) ( mprj la_data_in[60] ) + USE SIGNAL
-      + ROUTED met2 ( 1693490 1700 0 ) ( * 17510 )
-      NEW met1 ( 1693490 17510 ) ( 1698090 * )
-      NEW met2 ( 1697860 1688780 ) ( 1698090 * )
-      NEW met2 ( 1697860 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1698090 17510 ) ( * 1688780 )
-      NEW met1 ( 1693490 17510 ) M1M2_PR
-      NEW met1 ( 1698090 17510 ) M1M2_PR ;
-    - la_data_in[61] ( PIN la_data_in[61] ) ( mprj la_data_in[61] ) + USE SIGNAL
-      + ROUTED met2 ( 1706830 82800 ) ( 1710970 * )
-      NEW met2 ( 1710970 1700 0 ) ( * 82800 )
-      NEW met1 ( 1703610 1679770 ) ( 1706830 * )
-      NEW met2 ( 1703610 1679770 ) ( * 1688780 )
-      NEW met2 ( 1703380 1688780 ) ( 1703610 * )
-      NEW met2 ( 1703380 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1706830 82800 ) ( * 1679770 )
-      NEW met1 ( 1706830 1679770 ) M1M2_PR
-      NEW met1 ( 1703610 1679770 ) M1M2_PR ;
-    - la_data_in[62] ( PIN la_data_in[62] ) ( mprj la_data_in[62] ) + USE SIGNAL
-      + ROUTED met2 ( 1728910 1700 0 ) ( * 19550 )
-      NEW met1 ( 1706370 19550 ) ( 1728910 * )
-      NEW met2 ( 1706370 1688780 ) ( 1708830 * )
-      NEW met2 ( 1708830 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1706370 19550 ) ( * 1688780 )
-      NEW met1 ( 1728910 19550 ) M1M2_PR
-      NEW met1 ( 1706370 19550 ) M1M2_PR ;
-    - la_data_in[63] ( PIN la_data_in[63] ) ( mprj la_data_in[63] ) + USE SIGNAL
-      + ROUTED met2 ( 1746390 1700 0 ) ( * 14790 )
-      NEW met1 ( 1711890 14790 ) ( 1746390 * )
-      NEW met1 ( 1711890 1689290 ) ( 1714350 * )
-      NEW met2 ( 1714350 1689290 ) ( * 1690140 0 )
-      NEW met2 ( 1711890 14790 ) ( * 1689290 )
-      NEW met1 ( 1746390 14790 ) M1M2_PR
-      NEW met1 ( 1711890 14790 ) M1M2_PR
-      NEW met1 ( 1711890 1689290 ) M1M2_PR
-      NEW met1 ( 1714350 1689290 ) M1M2_PR ;
-    - la_data_in[64] ( PIN la_data_in[64] ) ( mprj la_data_in[64] ) + USE SIGNAL
-      + ROUTED met2 ( 1764330 1700 0 ) ( * 16830 )
-      NEW met1 ( 1728450 16830 ) ( 1764330 * )
-      NEW met2 ( 1728450 16830 ) ( * 1676710 )
-      NEW met1 ( 1725000 1676710 ) ( 1728450 * )
-      NEW met1 ( 1725000 1676710 ) ( * 1677390 )
-      NEW met1 ( 1719710 1677390 ) ( 1725000 * )
-      NEW met2 ( 1719710 1677390 ) ( * 1689290 )
-      NEW met2 ( 1719480 1689290 ) ( 1719710 * )
-      NEW met2 ( 1719480 1689290 ) ( * 1690140 0 )
-      NEW met1 ( 1764330 16830 ) M1M2_PR
-      NEW met1 ( 1728450 16830 ) M1M2_PR
-      NEW met1 ( 1728450 1676710 ) M1M2_PR
-      NEW met1 ( 1719710 1677390 ) M1M2_PR ;
-    - la_data_in[65] ( PIN la_data_in[65] ) ( mprj la_data_in[65] ) + USE SIGNAL
-      + ROUTED met1 ( 1718790 1651890 ) ( 1724770 * )
-      NEW met2 ( 1781810 1700 0 ) ( * 19890 )
-      NEW met1 ( 1718790 19890 ) ( 1781810 * )
-      NEW met2 ( 1718790 19890 ) ( * 1651890 )
-      NEW met2 ( 1724770 1688780 ) ( 1724930 * )
-      NEW met2 ( 1724930 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1724770 1651890 ) ( * 1688780 )
-      NEW met1 ( 1718790 19890 ) M1M2_PR
-      NEW met1 ( 1718790 1651890 ) M1M2_PR
-      NEW met1 ( 1724770 1651890 ) M1M2_PR
-      NEW met1 ( 1781810 19890 ) M1M2_PR ;
-    - la_data_in[66] ( PIN la_data_in[66] ) ( mprj la_data_in[66] ) + USE SIGNAL
-      + ROUTED met2 ( 1725690 1683340 ) ( 1728910 * )
-      NEW met2 ( 1728910 1683340 ) ( * 1688780 )
-      NEW met2 ( 1728910 1688780 ) ( 1730450 * )
-      NEW met2 ( 1730450 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1725690 14450 ) ( * 1683340 )
-      NEW met2 ( 1799750 1700 0 ) ( * 14450 )
-      NEW met1 ( 1725690 14450 ) ( 1799750 * )
-      NEW met1 ( 1725690 14450 ) M1M2_PR
-      NEW met1 ( 1799750 14450 ) M1M2_PR ;
-    - la_data_in[67] ( PIN la_data_in[67] ) ( mprj la_data_in[67] ) + USE SIGNAL
-      + ROUTED met1 ( 1732590 1652570 ) ( 1735810 * )
-      NEW met2 ( 1732590 19550 ) ( * 1652570 )
-      NEW met2 ( 1735810 1688780 ) ( 1735970 * )
-      NEW met2 ( 1735970 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1735810 1652570 ) ( * 1688780 )
-      NEW met2 ( 1817690 1700 0 ) ( * 19550 )
-      NEW met1 ( 1732590 19550 ) ( 1817690 * )
-      NEW met1 ( 1732590 19550 ) M1M2_PR
-      NEW met1 ( 1732590 1652570 ) M1M2_PR
-      NEW met1 ( 1735810 1652570 ) M1M2_PR
-      NEW met1 ( 1817690 19550 ) M1M2_PR ;
-    - la_data_in[68] ( PIN la_data_in[68] ) ( mprj la_data_in[68] ) + USE SIGNAL
-      + ROUTED met2 ( 1835170 1700 0 ) ( * 19210 )
-      NEW met2 ( 1739030 19210 ) ( * 1676700 )
-      NEW met2 ( 1739030 1676700 ) ( 1740870 * )
-      NEW met2 ( 1740870 1676700 ) ( * 1688780 )
-      NEW met2 ( 1740870 1688780 ) ( 1741490 * )
-      NEW met2 ( 1741490 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1739030 19210 ) ( 1835170 * )
-      NEW met1 ( 1739030 19210 ) M1M2_PR
-      NEW met1 ( 1835170 19210 ) M1M2_PR ;
-    - la_data_in[69] ( PIN la_data_in[69] ) ( mprj la_data_in[69] ) + USE SIGNAL
-      + ROUTED met2 ( 1853110 1700 0 ) ( * 18190 )
-      NEW met2 ( 1745930 1688780 ) ( 1747010 * )
-      NEW met2 ( 1747010 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1745930 18190 ) ( * 1688780 )
-      NEW met1 ( 1745930 18190 ) ( 1853110 * )
-      NEW met1 ( 1745930 18190 ) M1M2_PR
-      NEW met1 ( 1853110 18190 ) M1M2_PR ;
-    - la_data_in[6] ( PIN la_data_in[6] ) ( mprj la_data_in[6] ) + USE SIGNAL
-      + ROUTED met1 ( 731630 86870 ) ( 1401850 * )
-      NEW met2 ( 731630 82800 ) ( * 86870 )
-      NEW met2 ( 731630 82800 ) ( 735770 * )
-      NEW met2 ( 735770 1700 0 ) ( * 82800 )
-      NEW met2 ( 1401850 1688780 ) ( 1402010 * )
-      NEW met2 ( 1402010 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1401850 86870 ) ( * 1688780 )
-      NEW met1 ( 731630 86870 ) M1M2_PR
-      NEW met1 ( 1401850 86870 ) M1M2_PR ;
-    - la_data_in[70] ( PIN la_data_in[70] ) ( mprj la_data_in[70] ) + USE SIGNAL
-      + ROUTED met2 ( 1752370 1676710 ) ( * 1688780 )
-      NEW met2 ( 1752370 1688780 ) ( 1752530 * )
-      NEW met2 ( 1752530 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1776750 16150 ) ( 1812630 * )
-      NEW met2 ( 1812630 16150 ) ( * 20230 )
-      NEW met2 ( 1870590 1700 0 ) ( * 20230 )
-      NEW met1 ( 1812630 20230 ) ( 1870590 * )
-      NEW met1 ( 1752370 1676710 ) ( 1776750 * )
-      NEW met2 ( 1776750 16150 ) ( * 1676710 )
-      NEW met1 ( 1752370 1676710 ) M1M2_PR
-      NEW met1 ( 1776750 16150 ) M1M2_PR
-      NEW met1 ( 1812630 16150 ) M1M2_PR
-      NEW met1 ( 1812630 20230 ) M1M2_PR
-      NEW met1 ( 1870590 20230 ) M1M2_PR
-      NEW met1 ( 1776750 1676710 ) M1M2_PR ;
-    - la_data_in[71] ( PIN la_data_in[71] ) ( mprj la_data_in[71] ) + USE SIGNAL
-      + ROUTED met2 ( 1758350 1677050 ) ( * 1688780 )
-      NEW met2 ( 1758120 1688780 ) ( 1758350 * )
-      NEW met2 ( 1758120 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1783650 20230 ) ( 1802050 * )
-      NEW met1 ( 1802050 19890 ) ( * 20230 )
-      NEW met2 ( 1888530 1700 0 ) ( * 19890 )
-      NEW met1 ( 1802050 19890 ) ( 1888530 * )
-      NEW met1 ( 1758350 1677050 ) ( 1783650 * )
-      NEW met2 ( 1783650 20230 ) ( * 1677050 )
-      NEW met1 ( 1758350 1677050 ) M1M2_PR
-      NEW met1 ( 1783650 20230 ) M1M2_PR
-      NEW met1 ( 1888530 19890 ) M1M2_PR
-      NEW met1 ( 1783650 1677050 ) M1M2_PR ;
-    - la_data_in[72] ( PIN la_data_in[72] ) ( mprj la_data_in[72] ) + USE SIGNAL
-      + ROUTED met2 ( 1763870 1678750 ) ( * 1688780 )
-      NEW met2 ( 1763640 1688780 ) ( 1763870 * )
-      NEW met2 ( 1763640 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1790550 19890 ) ( 1794230 * )
-      NEW met2 ( 1794230 18530 ) ( * 19890 )
-      NEW met2 ( 1906010 1700 0 ) ( * 18530 )
-      NEW met1 ( 1794230 18530 ) ( 1906010 * )
-      NEW met1 ( 1763870 1678750 ) ( 1790550 * )
-      NEW met2 ( 1790550 19890 ) ( * 1678750 )
-      NEW met1 ( 1763870 1678750 ) M1M2_PR
-      NEW met1 ( 1790550 19890 ) M1M2_PR
-      NEW met1 ( 1794230 19890 ) M1M2_PR
-      NEW met1 ( 1794230 18530 ) M1M2_PR
-      NEW met1 ( 1906010 18530 ) M1M2_PR
-      NEW met1 ( 1790550 1678750 ) M1M2_PR ;
-    - la_data_in[73] ( PIN la_data_in[73] ) ( mprj la_data_in[73] ) + USE SIGNAL
-      + ROUTED met2 ( 1923950 1700 0 ) ( * 20570 )
-      NEW met2 ( 1769390 1679430 ) ( * 1688780 )
-      NEW met2 ( 1769160 1688780 ) ( 1769390 * )
-      NEW met2 ( 1769160 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1811250 20230 ) ( 1812170 * )
-      NEW met1 ( 1812170 20230 ) ( * 20570 )
-      NEW met1 ( 1812170 20570 ) ( 1923950 * )
-      NEW met2 ( 1811250 20230 ) ( * 1676700 )
-      NEW met2 ( 1810790 1676700 ) ( * 1679430 )
-      NEW met2 ( 1810790 1676700 ) ( 1811250 * )
-      NEW met1 ( 1769390 1679430 ) ( 1810790 * )
-      NEW met1 ( 1923950 20570 ) M1M2_PR
-      NEW met1 ( 1769390 1679430 ) M1M2_PR
-      NEW met1 ( 1811250 20230 ) M1M2_PR
-      NEW met1 ( 1810790 1679430 ) M1M2_PR ;
-    - la_data_in[74] ( PIN la_data_in[74] ) ( mprj la_data_in[74] ) + USE SIGNAL
-      + ROUTED met2 ( 1941430 1700 0 ) ( * 16490 )
-      NEW met2 ( 1832410 16490 ) ( * 1683170 )
-      NEW met1 ( 1832410 16490 ) ( 1941430 * )
-      NEW met2 ( 1774910 1683170 ) ( * 1688780 )
-      NEW met2 ( 1774680 1688780 ) ( 1774910 * )
-      NEW met2 ( 1774680 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1774910 1683170 ) ( 1832410 * )
-      NEW met1 ( 1832410 16490 ) M1M2_PR
-      NEW met1 ( 1941430 16490 ) M1M2_PR
-      NEW met1 ( 1832410 1683170 ) M1M2_PR
-      NEW met1 ( 1774910 1683170 ) M1M2_PR ;
-    - la_data_in[75] ( PIN la_data_in[75] ) ( mprj la_data_in[75] ) + USE SIGNAL
-      + ROUTED met2 ( 1959370 1700 0 ) ( * 19550 )
-      NEW met2 ( 1832870 19550 ) ( * 1682830 )
-      NEW met1 ( 1832870 19550 ) ( 1959370 * )
-      NEW met2 ( 1779970 1682830 ) ( * 1688780 )
-      NEW met2 ( 1779740 1688780 ) ( 1779970 * )
-      NEW met2 ( 1779740 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1779970 1682830 ) ( 1832870 * )
-      NEW met1 ( 1832870 19550 ) M1M2_PR
-      NEW met1 ( 1959370 19550 ) M1M2_PR
-      NEW met1 ( 1832870 1682830 ) M1M2_PR
-      NEW met1 ( 1779970 1682830 ) M1M2_PR ;
-    - la_data_in[76] ( PIN la_data_in[76] ) ( mprj la_data_in[76] ) + USE SIGNAL
-      + ROUTED met2 ( 1845750 16830 ) ( * 1678410 )
-      NEW met2 ( 1976850 1700 0 ) ( * 16830 )
-      NEW met1 ( 1845750 16830 ) ( 1976850 * )
-      NEW met2 ( 1785490 1678410 ) ( * 1688780 )
-      NEW met2 ( 1785260 1688780 ) ( 1785490 * )
-      NEW met2 ( 1785260 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1785490 1678410 ) ( 1845750 * )
-      NEW met1 ( 1845750 16830 ) M1M2_PR
-      NEW met1 ( 1845750 1678410 ) M1M2_PR
-      NEW met1 ( 1976850 16830 ) M1M2_PR
-      NEW met1 ( 1785490 1678410 ) M1M2_PR ;
-    - la_data_in[77] ( PIN la_data_in[77] ) ( mprj la_data_in[77] ) + USE SIGNAL
-      + ROUTED met1 ( 1787790 1652230 ) ( * 1653250 )
-      NEW met2 ( 1994790 1700 0 ) ( * 23970 )
-      NEW met1 ( 1787790 23970 ) ( 1994790 * )
-      NEW met2 ( 1787790 23970 ) ( * 1652230 )
-      NEW met1 ( 1787790 1689290 ) ( 1790710 * )
-      NEW met2 ( 1790710 1689290 ) ( * 1690140 0 )
-      NEW met2 ( 1787790 1653250 ) ( * 1689290 )
-      NEW met1 ( 1787790 23970 ) M1M2_PR
-      NEW met1 ( 1787790 1652230 ) M1M2_PR
-      NEW met1 ( 1787790 1653250 ) M1M2_PR
-      NEW met1 ( 1994790 23970 ) M1M2_PR
-      NEW met1 ( 1787790 1689290 ) M1M2_PR
-      NEW met1 ( 1790710 1689290 ) M1M2_PR ;
-    - la_data_in[78] ( PIN la_data_in[78] ) ( mprj la_data_in[78] ) + USE SIGNAL
-      + ROUTED met2 ( 2012730 1700 0 ) ( * 22270 )
-      NEW met1 ( 1795150 22270 ) ( 2012730 * )
-      NEW met2 ( 1795150 22270 ) ( * 1580100 )
-      NEW met2 ( 1795150 1580100 ) ( 1796070 * )
-      NEW met2 ( 1796070 1688780 ) ( 1796230 * )
-      NEW met2 ( 1796230 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1796070 1580100 ) ( * 1688780 )
-      NEW met1 ( 1795150 22270 ) M1M2_PR
-      NEW met1 ( 2012730 22270 ) M1M2_PR ;
-    - la_data_in[79] ( PIN la_data_in[79] ) ( mprj la_data_in[79] ) + USE SIGNAL
-      + ROUTED met2 ( 2030210 1700 0 ) ( * 22950 )
-      NEW met1 ( 1801130 22950 ) ( 2030210 * )
-      NEW met2 ( 1801130 1688780 ) ( 1801750 * )
-      NEW met2 ( 1801750 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1801130 22950 ) ( * 1688780 )
-      NEW met1 ( 2030210 22950 ) M1M2_PR
-      NEW met1 ( 1801130 22950 ) M1M2_PR ;
-    - la_data_in[7] ( PIN la_data_in[7] ) ( mprj la_data_in[7] ) + USE SIGNAL
-      + ROUTED met1 ( 752330 87550 ) ( 1402310 * )
-      NEW met1 ( 1402310 1642370 ) ( 1407370 * )
-      NEW met2 ( 752330 82800 ) ( * 87550 )
-      NEW met2 ( 752330 82800 ) ( 753250 * )
-      NEW met2 ( 753250 1700 0 ) ( * 82800 )
-      NEW met2 ( 1402310 87550 ) ( * 1642370 )
-      NEW met2 ( 1407370 1688780 ) ( 1407530 * )
-      NEW met2 ( 1407530 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1407370 1642370 ) ( * 1688780 )
-      NEW met1 ( 752330 87550 ) M1M2_PR
-      NEW met1 ( 1402310 87550 ) M1M2_PR
-      NEW met1 ( 1402310 1642370 ) M1M2_PR
-      NEW met1 ( 1407370 1642370 ) M1M2_PR ;
-    - la_data_in[80] ( PIN la_data_in[80] ) ( mprj la_data_in[80] ) + USE SIGNAL
-      + ROUTED met2 ( 2048150 1700 0 ) ( * 30770 )
-      NEW met1 ( 1801590 1652570 ) ( 1807110 * )
-      NEW met1 ( 1801590 30770 ) ( 2048150 * )
-      NEW met2 ( 1801590 30770 ) ( * 1652570 )
-      NEW met2 ( 1807110 1688780 ) ( 1807270 * )
-      NEW met2 ( 1807270 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1807110 1652570 ) ( * 1688780 )
-      NEW met1 ( 2048150 30770 ) M1M2_PR
-      NEW met1 ( 1801590 30770 ) M1M2_PR
-      NEW met1 ( 1801590 1652570 ) M1M2_PR
-      NEW met1 ( 1807110 1652570 ) M1M2_PR ;
-    - la_data_in[81] ( PIN la_data_in[81] ) ( mprj la_data_in[81] ) + USE SIGNAL
-      + ROUTED met2 ( 2065630 1700 0 ) ( * 29410 )
-      NEW met1 ( 1808030 29410 ) ( 2065630 * )
-      NEW met1 ( 1808030 1688950 ) ( 1812790 * )
-      NEW met2 ( 1812790 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1808030 29410 ) ( * 1688950 )
-      NEW met1 ( 1808030 29410 ) M1M2_PR
-      NEW met1 ( 2065630 29410 ) M1M2_PR
-      NEW met1 ( 1808030 1688950 ) M1M2_PR
-      NEW met1 ( 1812790 1688950 ) M1M2_PR ;
-    - la_data_in[82] ( PIN la_data_in[82] ) ( mprj la_data_in[82] ) + USE SIGNAL
-      + ROUTED met2 ( 2083570 1700 0 ) ( * 27710 )
-      NEW met1 ( 2077590 27710 ) ( 2083570 * )
-      NEW met2 ( 2077590 27710 ) ( * 34170 )
-      NEW met1 ( 1815390 34170 ) ( 2077590 * )
-      NEW met2 ( 1815390 34170 ) ( * 1676700 )
-      NEW met2 ( 1815390 1676700 ) ( 1817230 * )
-      NEW met2 ( 1817230 1676700 ) ( * 1688780 )
-      NEW met2 ( 1817230 1688780 ) ( 1818310 * )
-      NEW met2 ( 1818310 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1815390 34170 ) M1M2_PR
-      NEW met1 ( 2083570 27710 ) M1M2_PR
-      NEW met1 ( 2077590 27710 ) M1M2_PR
-      NEW met1 ( 2077590 34170 ) M1M2_PR ;
-    - la_data_in[83] ( PIN la_data_in[83] ) ( mprj la_data_in[83] ) + USE SIGNAL
-      + ROUTED met2 ( 1821830 29750 ) ( * 1676700 )
-      NEW met2 ( 1821830 1676700 ) ( 1823670 * )
-      NEW met2 ( 1823670 1676700 ) ( * 1688780 )
-      NEW met2 ( 1823670 1688780 ) ( 1823830 * )
-      NEW met2 ( 1823830 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 2101050 1700 0 ) ( * 29750 )
-      NEW met1 ( 1821830 29750 ) ( 2101050 * )
-      NEW met1 ( 1821830 29750 ) M1M2_PR
-      NEW met1 ( 2101050 29750 ) M1M2_PR ;
-    - la_data_in[84] ( PIN la_data_in[84] ) ( mprj la_data_in[84] ) + USE SIGNAL
-      + ROUTED met2 ( 2118990 1700 0 ) ( * 30090 )
-      NEW met2 ( 1829420 1688780 ) ( 1829650 * )
-      NEW met2 ( 1829420 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1829650 30090 ) ( * 1688780 )
-      NEW met1 ( 1829650 30090 ) ( 2118990 * )
-      NEW met1 ( 1829650 30090 ) M1M2_PR
-      NEW met1 ( 2118990 30090 ) M1M2_PR ;
-    - la_data_in[85] ( PIN la_data_in[85] ) ( mprj la_data_in[85] ) + USE SIGNAL
-      + ROUTED met1 ( 1829190 1652570 ) ( 1834710 * )
-      NEW met2 ( 2136470 1700 0 ) ( * 30430 )
-      NEW met2 ( 1829190 30430 ) ( * 1652570 )
-      NEW met2 ( 1834710 1688780 ) ( 1834870 * )
-      NEW met2 ( 1834870 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1834710 1652570 ) ( * 1688780 )
-      NEW met1 ( 1829190 30430 ) ( 2136470 * )
-      NEW met1 ( 1829190 30430 ) M1M2_PR
-      NEW met1 ( 1829190 1652570 ) M1M2_PR
-      NEW met1 ( 1834710 1652570 ) M1M2_PR
-      NEW met1 ( 2136470 30430 ) M1M2_PR ;
-    - la_data_in[86] ( PIN la_data_in[86] ) ( mprj la_data_in[86] ) + USE SIGNAL
-      + ROUTED met2 ( 1836090 1652740 ) ( 1837010 * )
-      NEW met2 ( 2154410 1700 0 ) ( * 33830 )
-      NEW met2 ( 1836090 33830 ) ( * 1652740 )
-      NEW met1 ( 1837010 1689290 ) ( 1839930 * )
-      NEW met2 ( 1839930 1689290 ) ( * 1690140 0 )
-      NEW met2 ( 1837010 1652740 ) ( * 1689290 )
-      NEW met1 ( 1836090 33830 ) ( 2154410 * )
-      NEW met1 ( 1836090 33830 ) M1M2_PR
-      NEW met1 ( 2154410 33830 ) M1M2_PR
-      NEW met1 ( 1837010 1689290 ) M1M2_PR
-      NEW met1 ( 1839930 1689290 ) M1M2_PR ;
-    - la_data_in[87] ( PIN la_data_in[87] ) ( mprj la_data_in[87] ) + USE SIGNAL
-      + ROUTED met1 ( 1842530 1689290 ) ( 1845450 * )
-      NEW met2 ( 1845450 1689290 ) ( * 1690140 0 )
-      NEW met2 ( 1842530 33490 ) ( * 1689290 )
-      NEW met2 ( 2172350 1700 0 ) ( * 33490 )
-      NEW met1 ( 1842530 33490 ) ( 2172350 * )
-      NEW met1 ( 1842530 33490 ) M1M2_PR
-      NEW met1 ( 1842530 1689290 ) M1M2_PR
-      NEW met1 ( 1845450 1689290 ) M1M2_PR
-      NEW met1 ( 2172350 33490 ) M1M2_PR ;
-    - la_data_in[88] ( PIN la_data_in[88] ) ( mprj la_data_in[88] ) + USE SIGNAL
-      + ROUTED met2 ( 2189830 1700 0 ) ( * 33150 )
-      NEW met1 ( 1849430 33150 ) ( 2189830 * )
-      NEW met2 ( 1849430 1688780 ) ( 1850970 * )
-      NEW met2 ( 1850970 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1849430 33150 ) ( * 1688780 )
-      NEW met1 ( 1849430 33150 ) M1M2_PR
-      NEW met1 ( 2189830 33150 ) M1M2_PR ;
-    - la_data_in[89] ( PIN la_data_in[89] ) ( mprj la_data_in[89] ) + USE SIGNAL
-      + ROUTED met2 ( 2207770 1700 0 ) ( * 32810 )
-      NEW met1 ( 1856790 32810 ) ( 2207770 * )
-      NEW met2 ( 1856560 1688780 ) ( 1856790 * )
-      NEW met2 ( 1856560 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1856790 32810 ) ( * 1688780 )
-      NEW met1 ( 1856790 32810 ) M1M2_PR
-      NEW met1 ( 2207770 32810 ) M1M2_PR ;
-    - la_data_in[8] ( PIN la_data_in[8] ) ( mprj la_data_in[8] ) + USE SIGNAL
-      + ROUTED met2 ( 768890 1700 ) ( 771190 * 0 )
-      NEW met2 ( 766130 82800 ) ( * 88230 )
-      NEW met2 ( 766130 82800 ) ( 768890 * )
-      NEW met2 ( 768890 1700 ) ( * 82800 )
-      NEW met1 ( 766130 88230 ) ( 1407830 * )
-      NEW met1 ( 1407830 1652570 ) ( 1412890 * )
-      NEW met2 ( 1407830 88230 ) ( * 1652570 )
-      NEW met2 ( 1412890 1688780 ) ( 1413050 * )
-      NEW met2 ( 1413050 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1412890 1652570 ) ( * 1688780 )
-      NEW met1 ( 766130 88230 ) M1M2_PR
-      NEW met1 ( 1407830 88230 ) M1M2_PR
-      NEW met1 ( 1407830 1652570 ) M1M2_PR
-      NEW met1 ( 1412890 1652570 ) M1M2_PR ;
-    - la_data_in[90] ( PIN la_data_in[90] ) ( mprj la_data_in[90] ) + USE SIGNAL
-      + ROUTED met1 ( 1856330 1652570 ) ( 1861850 * )
-      NEW met2 ( 2225250 1700 0 ) ( * 32470 )
-      NEW met2 ( 1856330 32470 ) ( * 1652570 )
-      NEW met1 ( 1856330 32470 ) ( 2225250 * )
-      NEW met2 ( 1861850 1688780 ) ( 1862010 * )
-      NEW met2 ( 1862010 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1861850 1652570 ) ( * 1688780 )
-      NEW met1 ( 1856330 32470 ) M1M2_PR
-      NEW met1 ( 1856330 1652570 ) M1M2_PR
-      NEW met1 ( 1861850 1652570 ) M1M2_PR
-      NEW met1 ( 2225250 32470 ) M1M2_PR ;
-    - la_data_in[91] ( PIN la_data_in[91] ) ( mprj la_data_in[91] ) + USE SIGNAL
-      + ROUTED met2 ( 2243190 1700 0 ) ( * 15300 )
-      NEW met2 ( 2242730 15300 ) ( 2243190 * )
-      NEW met2 ( 2242730 15300 ) ( * 68510 )
-      NEW met1 ( 1864150 68510 ) ( 2242730 * )
-      NEW met2 ( 1864150 1681300 ) ( 1866450 * )
-      NEW met2 ( 1866450 1681300 ) ( * 1688780 )
-      NEW met2 ( 1866450 1688780 ) ( 1867530 * )
-      NEW met2 ( 1867530 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1864150 68510 ) ( * 1681300 )
-      NEW met1 ( 1864150 68510 ) M1M2_PR
-      NEW met1 ( 2242730 68510 ) M1M2_PR ;
-    - la_data_in[92] ( PIN la_data_in[92] ) ( mprj la_data_in[92] ) + USE SIGNAL
-      + ROUTED met2 ( 2258370 1700 ) ( 2260670 * 0 )
-      NEW met1 ( 1871050 68170 ) ( 2258370 * )
-      NEW met2 ( 2258370 1700 ) ( * 68170 )
-      NEW met2 ( 1871050 1688780 ) ( 1873050 * )
-      NEW met2 ( 1873050 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1871050 68170 ) ( * 1688780 )
-      NEW met1 ( 1871050 68170 ) M1M2_PR
-      NEW met1 ( 2258370 68170 ) M1M2_PR ;
-    - la_data_in[93] ( PIN la_data_in[93] ) ( mprj la_data_in[93] ) + USE SIGNAL
-      + ROUTED met1 ( 1877490 67830 ) ( 2278610 * )
-      NEW met2 ( 2278610 1700 0 ) ( * 67830 )
-      NEW met2 ( 1877490 1688780 ) ( 1878570 * )
-      NEW met2 ( 1878570 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1877490 67830 ) ( * 1688780 )
-      NEW met1 ( 1877490 67830 ) M1M2_PR
-      NEW met1 ( 2278610 67830 ) M1M2_PR ;
-    - la_data_in[94] ( PIN la_data_in[94] ) ( mprj la_data_in[94] ) + USE SIGNAL
-      + ROUTED met1 ( 1884850 67490 ) ( 2296090 * )
-      NEW met2 ( 2296090 1700 0 ) ( * 67490 )
-      NEW met2 ( 1884160 1688780 ) ( 1884850 * )
-      NEW met2 ( 1884160 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1884850 67490 ) ( * 1688780 )
-      NEW met1 ( 1884850 67490 ) M1M2_PR
-      NEW met1 ( 2296090 67490 ) M1M2_PR ;
-    - la_data_in[95] ( PIN la_data_in[95] ) ( mprj la_data_in[95] ) + USE SIGNAL
-      + ROUTED met2 ( 2311730 1700 ) ( 2314030 * 0 )
-      NEW met2 ( 2311730 1700 ) ( * 67150 )
-      NEW met1 ( 1884390 1652230 ) ( 1889450 * )
-      NEW met2 ( 1884390 67150 ) ( * 1652230 )
-      NEW met1 ( 1884390 67150 ) ( 2311730 * )
-      NEW met2 ( 1889450 1688780 ) ( 1889610 * )
-      NEW met2 ( 1889610 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1889450 1652230 ) ( * 1688780 )
-      NEW met1 ( 2311730 67150 ) M1M2_PR
-      NEW met1 ( 1884390 1652230 ) M1M2_PR
-      NEW met1 ( 1889450 1652230 ) M1M2_PR
-      NEW met1 ( 1884390 67150 ) M1M2_PR ;
-    - la_data_in[96] ( PIN la_data_in[96] ) ( mprj la_data_in[96] ) + USE SIGNAL
-      + ROUTED met2 ( 2331510 1700 0 ) ( * 36890 )
-      NEW met1 ( 1890830 36890 ) ( 2331510 * )
-      NEW met1 ( 1890830 1688950 ) ( 1895130 * )
-      NEW met2 ( 1895130 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1890830 36890 ) ( * 1688950 )
-      NEW met1 ( 2331510 36890 ) M1M2_PR
-      NEW met1 ( 1890830 36890 ) M1M2_PR
-      NEW met1 ( 1890830 1688950 ) M1M2_PR
-      NEW met1 ( 1895130 1688950 ) M1M2_PR ;
-    - la_data_in[97] ( PIN la_data_in[97] ) ( mprj la_data_in[97] ) + USE SIGNAL
-      + ROUTED met2 ( 2349450 1700 0 ) ( * 37230 )
-      NEW met2 ( 1898190 37230 ) ( * 1676700 )
-      NEW met2 ( 1898190 1676700 ) ( 1899110 * )
-      NEW met2 ( 1899110 1676700 ) ( * 1688780 )
-      NEW met2 ( 1899110 1688780 ) ( 1900190 * )
-      NEW met2 ( 1900190 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1898190 37230 ) ( 2349450 * )
-      NEW met1 ( 2349450 37230 ) M1M2_PR
-      NEW met1 ( 1898190 37230 ) M1M2_PR ;
-    - la_data_in[98] ( PIN la_data_in[98] ) ( mprj la_data_in[98] ) + USE SIGNAL
-      + ROUTED met2 ( 1905090 1688780 ) ( 1905710 * )
-      NEW met2 ( 1905710 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1905090 37570 ) ( * 1688780 )
-      NEW met1 ( 1905090 37570 ) ( 2367390 * )
-      NEW met2 ( 2367390 1700 0 ) ( * 37570 )
-      NEW met1 ( 1905090 37570 ) M1M2_PR
-      NEW met1 ( 2367390 37570 ) M1M2_PR ;
-    - la_data_in[99] ( PIN la_data_in[99] ) ( mprj la_data_in[99] ) + USE SIGNAL
-      + ROUTED met1 ( 1904630 1652570 ) ( 1911070 * )
-      NEW met2 ( 1904630 41310 ) ( * 1652570 )
-      NEW met2 ( 1911070 1688780 ) ( 1911230 * )
-      NEW met2 ( 1911230 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1911070 1652570 ) ( * 1688780 )
-      NEW met1 ( 1904630 41310 ) ( 2384870 * )
-      NEW met2 ( 2384870 1700 0 ) ( * 41310 )
-      NEW met1 ( 1904630 1652570 ) M1M2_PR
-      NEW met1 ( 1911070 1652570 ) M1M2_PR
-      NEW met1 ( 1904630 41310 ) M1M2_PR
-      NEW met1 ( 2384870 41310 ) M1M2_PR ;
-    - la_data_in[9] ( PIN la_data_in[9] ) ( mprj la_data_in[9] ) + USE SIGNAL
-      + ROUTED met2 ( 789130 1700 0 ) ( * 38930 )
-      NEW met1 ( 1414730 1652570 ) ( 1417950 * )
-      NEW met2 ( 1417950 1688780 ) ( 1418110 * )
-      NEW met2 ( 1418110 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1417950 1652570 ) ( * 1688780 )
-      NEW met1 ( 789130 38930 ) ( 1414730 * )
-      NEW met2 ( 1414730 38930 ) ( * 1652570 )
-      NEW met1 ( 789130 38930 ) M1M2_PR
-      NEW met1 ( 1414730 1652570 ) M1M2_PR
-      NEW met1 ( 1417950 1652570 ) M1M2_PR
-      NEW met1 ( 1414730 38930 ) M1M2_PR ;
-    - la_data_out[0] ( PIN la_data_out[0] ) ( mprj la_data_out[0] ) + USE SIGNAL
-      + ROUTED met1 ( 1366890 1652570 ) ( 1370570 * )
-      NEW met2 ( 1366890 37910 ) ( * 1652570 )
-      NEW met2 ( 1370570 1688780 ) ( 1370730 * )
-      NEW met2 ( 1370730 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1370570 1652570 ) ( * 1688780 )
-      NEW met2 ( 635030 1700 0 ) ( * 17340 )
-      NEW met2 ( 635030 17340 ) ( 635490 * )
-      NEW met2 ( 635490 17340 ) ( * 37910 )
-      NEW met1 ( 635490 37910 ) ( 1366890 * )
-      NEW met1 ( 1366890 1652570 ) M1M2_PR
-      NEW met1 ( 1370570 1652570 ) M1M2_PR
-      NEW met1 ( 1366890 37910 ) M1M2_PR
-      NEW met1 ( 635490 37910 ) M1M2_PR ;
-    - la_data_out[100] ( PIN la_data_out[100] ) ( mprj la_data_out[100] ) + USE SIGNAL
-      + ROUTED met2 ( 1918660 1688780 ) ( 1918890 * )
-      NEW met2 ( 1918660 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1918890 40970 ) ( * 1688780 )
-      NEW met2 ( 2408790 1700 0 ) ( * 40970 )
-      NEW met1 ( 1918890 40970 ) ( 2408790 * )
-      NEW met1 ( 1918890 40970 ) M1M2_PR
-      NEW met1 ( 2408790 40970 ) M1M2_PR ;
-    - la_data_out[101] ( PIN la_data_out[101] ) ( mprj la_data_out[101] ) + USE SIGNAL
-      + ROUTED met1 ( 1918430 1652570 ) ( 1923950 * )
-      NEW met2 ( 1918430 40630 ) ( * 1652570 )
-      NEW met2 ( 1923950 1688780 ) ( 1924110 * )
-      NEW met2 ( 1924110 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1923950 1652570 ) ( * 1688780 )
-      NEW met2 ( 2426270 1700 0 ) ( * 40630 )
-      NEW met1 ( 1918430 40630 ) ( 2426270 * )
-      NEW met1 ( 1918430 1652570 ) M1M2_PR
-      NEW met1 ( 1923950 1652570 ) M1M2_PR
-      NEW met1 ( 1918430 40630 ) M1M2_PR
-      NEW met1 ( 2426270 40630 ) M1M2_PR ;
-    - la_data_out[102] ( PIN la_data_out[102] ) ( mprj la_data_out[102] ) + USE SIGNAL
-      + ROUTED met1 ( 1925330 1688950 ) ( 1929630 * )
-      NEW met2 ( 1929630 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1925330 40290 ) ( * 1688950 )
-      NEW met2 ( 2444210 1700 0 ) ( * 40290 )
-      NEW met1 ( 1925330 40290 ) ( 2444210 * )
-      NEW met1 ( 1925330 40290 ) M1M2_PR
-      NEW met1 ( 1925330 1688950 ) M1M2_PR
-      NEW met1 ( 1929630 1688950 ) M1M2_PR
-      NEW met1 ( 2444210 40290 ) M1M2_PR ;
-    - la_data_out[103] ( PIN la_data_out[103] ) ( mprj la_data_out[103] ) + USE SIGNAL
-      + ROUTED met1 ( 1932230 1689290 ) ( 1935150 * )
-      NEW met2 ( 1935150 1689290 ) ( * 1690140 0 )
-      NEW met2 ( 1932230 39950 ) ( * 1689290 )
-      NEW met1 ( 1932230 39950 ) ( 2461690 * )
-      NEW met2 ( 2461690 1700 0 ) ( * 39950 )
-      NEW met1 ( 1932230 39950 ) M1M2_PR
-      NEW met1 ( 1932230 1689290 ) M1M2_PR
-      NEW met1 ( 1935150 1689290 ) M1M2_PR
-      NEW met1 ( 2461690 39950 ) M1M2_PR ;
-    - la_data_out[104] ( PIN la_data_out[104] ) ( mprj la_data_out[104] ) + USE SIGNAL
-      + ROUTED met2 ( 1939590 1688780 ) ( 1940670 * )
-      NEW met2 ( 1940670 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1939590 39610 ) ( * 1688780 )
-      NEW met1 ( 1939590 39610 ) ( 2479630 * )
-      NEW met2 ( 2479630 1700 0 ) ( * 39610 )
-      NEW met1 ( 1939590 39610 ) M1M2_PR
-      NEW met1 ( 2479630 39610 ) M1M2_PR ;
-    - la_data_out[105] ( PIN la_data_out[105] ) ( mprj la_data_out[105] ) + USE SIGNAL
-      + ROUTED met2 ( 1946260 1688780 ) ( 1946490 * )
-      NEW met2 ( 1946260 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1946490 39270 ) ( * 1688780 )
-      NEW met1 ( 1946490 39270 ) ( 2497110 * )
-      NEW met2 ( 2497110 1700 0 ) ( * 39270 )
-      NEW met1 ( 1946490 39270 ) M1M2_PR
-      NEW met1 ( 2497110 39270 ) M1M2_PR ;
-    - la_data_out[106] ( PIN la_data_out[106] ) ( mprj la_data_out[106] ) + USE SIGNAL
-      + ROUTED met1 ( 1946950 1688950 ) ( 1951710 * )
-      NEW met2 ( 1951710 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1946950 38930 ) ( * 1688950 )
-      NEW met2 ( 2515050 1700 0 ) ( * 38930 )
-      NEW met1 ( 1946950 38930 ) ( 2515050 * )
-      NEW met1 ( 1946950 38930 ) M1M2_PR
-      NEW met1 ( 1946950 1688950 ) M1M2_PR
-      NEW met1 ( 1951710 1688950 ) M1M2_PR
-      NEW met1 ( 2515050 38930 ) M1M2_PR ;
-    - la_data_out[107] ( PIN la_data_out[107] ) ( mprj la_data_out[107] ) + USE SIGNAL
-      + ROUTED met1 ( 1953390 1688270 ) ( 1956770 * )
-      NEW met1 ( 1956770 1688270 ) ( * 1689290 )
-      NEW met2 ( 1956770 1689290 ) ( * 1690140 0 )
-      NEW met2 ( 1953390 38590 ) ( * 1688270 )
-      NEW met2 ( 2532530 1700 0 ) ( * 38590 )
-      NEW met1 ( 1953390 38590 ) ( 2532530 * )
-      NEW met1 ( 1953390 38590 ) M1M2_PR
-      NEW met1 ( 1953390 1688270 ) M1M2_PR
-      NEW met1 ( 1956770 1689290 ) M1M2_PR
-      NEW met1 ( 2532530 38590 ) M1M2_PR ;
-    - la_data_out[108] ( PIN la_data_out[108] ) ( mprj la_data_out[108] ) + USE SIGNAL
-      + ROUTED met2 ( 1960750 1688780 ) ( 1962290 * )
-      NEW met2 ( 1962290 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1960750 38250 ) ( * 1688780 )
-      NEW met1 ( 1960750 38250 ) ( 2550470 * )
-      NEW met2 ( 2550470 1700 0 ) ( * 38250 )
-      NEW met1 ( 1960750 38250 ) M1M2_PR
-      NEW met1 ( 2550470 38250 ) M1M2_PR ;
-    - la_data_out[109] ( PIN la_data_out[109] ) ( mprj la_data_out[109] ) + USE SIGNAL
-      + ROUTED met2 ( 1967190 1688780 ) ( 1967810 * )
-      NEW met2 ( 1967810 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1967190 37910 ) ( * 1688780 )
-      NEW met1 ( 1967190 37910 ) ( 2567950 * )
-      NEW met2 ( 2567950 1700 0 ) ( * 37910 )
-      NEW met1 ( 1967190 37910 ) M1M2_PR
-      NEW met1 ( 2567950 37910 ) M1M2_PR ;
-    - la_data_out[10] ( PIN la_data_out[10] ) ( mprj la_data_out[10] ) + USE SIGNAL
-      + ROUTED met1 ( 1421630 1637610 ) ( 1425310 * )
-      NEW met2 ( 812590 1700 0 ) ( * 37740 )
-      NEW met2 ( 1425310 1688780 ) ( 1425470 * )
-      NEW met2 ( 1425470 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1425310 1637610 ) ( * 1688780 )
-      NEW met3 ( 812590 37740 ) ( 1421630 * )
-      NEW met2 ( 1421630 37740 ) ( * 1637610 )
-      NEW met1 ( 1421630 1637610 ) M1M2_PR
-      NEW met1 ( 1425310 1637610 ) M1M2_PR
-      NEW met2 ( 812590 37740 ) M2M3_PR
-      NEW met2 ( 1421630 37740 ) M2M3_PR ;
-    - la_data_out[110] ( PIN la_data_out[110] ) ( mprj la_data_out[110] ) + USE SIGNAL
-      + ROUTED met1 ( 1967650 1652570 ) ( 1973170 * )
-      NEW met2 ( 1967650 66810 ) ( * 1652570 )
-      NEW met2 ( 1973170 1688780 ) ( 1973330 * )
-      NEW met2 ( 1973330 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1973170 1652570 ) ( * 1688780 )
-      NEW met1 ( 1967650 66810 ) ( 2585890 * )
-      NEW met2 ( 2585890 1700 0 ) ( * 66810 )
-      NEW met1 ( 1967650 1652570 ) M1M2_PR
-      NEW met1 ( 1973170 1652570 ) M1M2_PR
-      NEW met1 ( 1967650 66810 ) M1M2_PR
-      NEW met1 ( 2585890 66810 ) M1M2_PR ;
-    - la_data_out[111] ( PIN la_data_out[111] ) ( mprj la_data_out[111] ) + USE SIGNAL
-      + ROUTED met2 ( 2601530 1700 ) ( 2603830 * 0 )
-      NEW met2 ( 2601530 1700 ) ( * 66470 )
-      NEW met1 ( 1974090 1688950 ) ( 1978850 * )
-      NEW met2 ( 1978850 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1974090 66470 ) ( * 1688950 )
-      NEW met1 ( 1974090 66470 ) ( 2601530 * )
-      NEW met1 ( 2601530 66470 ) M1M2_PR
-      NEW met1 ( 1974090 66470 ) M1M2_PR
-      NEW met1 ( 1974090 1688950 ) M1M2_PR
-      NEW met1 ( 1978850 1688950 ) M1M2_PR ;
-    - la_data_out[112] ( PIN la_data_out[112] ) ( mprj la_data_out[112] ) + USE SIGNAL
-      + ROUTED met2 ( 2619010 1700 ) ( 2621310 * 0 )
-      NEW met2 ( 2619010 1700 ) ( * 66130 )
-      NEW met1 ( 1980990 1652570 ) ( 1984210 * )
-      NEW met2 ( 1980990 66130 ) ( * 1652570 )
-      NEW met2 ( 1984210 1688780 ) ( 1984370 * )
-      NEW met2 ( 1984370 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1984210 1652570 ) ( * 1688780 )
-      NEW met1 ( 1980990 66130 ) ( 2619010 * )
-      NEW met1 ( 2619010 66130 ) M1M2_PR
-      NEW met1 ( 1980990 1652570 ) M1M2_PR
-      NEW met1 ( 1984210 1652570 ) M1M2_PR
-      NEW met1 ( 1980990 66130 ) M1M2_PR ;
-    - la_data_out[113] ( PIN la_data_out[113] ) ( mprj la_data_out[113] ) + USE SIGNAL
-      + ROUTED met2 ( 2639250 1700 0 ) ( * 65790 )
-      NEW met2 ( 1988350 1688780 ) ( 1989890 * )
-      NEW met2 ( 1989890 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1988350 65790 ) ( * 1688780 )
-      NEW met1 ( 1988350 65790 ) ( 2639250 * )
-      NEW met1 ( 2639250 65790 ) M1M2_PR
-      NEW met1 ( 1988350 65790 ) M1M2_PR ;
-    - la_data_out[114] ( PIN la_data_out[114] ) ( mprj la_data_out[114] ) + USE SIGNAL
-      + ROUTED met2 ( 1994790 1688780 ) ( 1995410 * )
-      NEW met2 ( 1995410 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1994790 44030 ) ( * 1688780 )
-      NEW met1 ( 1994790 44030 ) ( 2656730 * )
-      NEW met2 ( 2656730 1700 0 ) ( * 44030 )
-      NEW met1 ( 1994790 44030 ) M1M2_PR
-      NEW met1 ( 2656730 44030 ) M1M2_PR ;
-    - la_data_out[115] ( PIN la_data_out[115] ) ( mprj la_data_out[115] ) + USE SIGNAL
-      + ROUTED met1 ( 1995250 1652570 ) ( 2000770 * )
-      NEW met2 ( 1995250 44370 ) ( * 1652570 )
-      NEW met2 ( 2000770 1688780 ) ( 2000930 * )
-      NEW met2 ( 2000930 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 2000770 1652570 ) ( * 1688780 )
-      NEW met1 ( 1995250 44370 ) ( 2674670 * )
-      NEW met2 ( 2674670 1700 0 ) ( * 44370 )
-      NEW met1 ( 1995250 1652570 ) M1M2_PR
-      NEW met1 ( 2000770 1652570 ) M1M2_PR
-      NEW met1 ( 1995250 44370 ) M1M2_PR
-      NEW met1 ( 2674670 44370 ) M1M2_PR ;
-    - la_data_out[116] ( PIN la_data_out[116] ) ( mprj la_data_out[116] ) + USE SIGNAL
-      + ROUTED met2 ( 2692150 1700 0 ) ( * 48110 )
-      NEW met1 ( 2001690 1688950 ) ( 2006450 * )
-      NEW met2 ( 2006450 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 2001690 48110 ) ( * 1688950 )
-      NEW met1 ( 2001690 48110 ) ( 2692150 * )
-      NEW met1 ( 2692150 48110 ) M1M2_PR
-      NEW met1 ( 2001690 48110 ) M1M2_PR
-      NEW met1 ( 2001690 1688950 ) M1M2_PR
-      NEW met1 ( 2006450 1688950 ) M1M2_PR ;
-    - la_data_out[117] ( PIN la_data_out[117] ) ( mprj la_data_out[117] ) + USE SIGNAL
-      + ROUTED met2 ( 2710090 1700 0 ) ( * 47770 )
-      NEW met1 ( 2008590 1688270 ) ( 2011970 * )
-      NEW met1 ( 2011970 1688270 ) ( * 1689290 )
-      NEW met2 ( 2011970 1689290 ) ( * 1690140 0 )
-      NEW met2 ( 2008590 47770 ) ( * 1688270 )
-      NEW met1 ( 2008590 47770 ) ( 2710090 * )
-      NEW met1 ( 2710090 47770 ) M1M2_PR
-      NEW met1 ( 2008590 47770 ) M1M2_PR
-      NEW met1 ( 2008590 1688270 ) M1M2_PR
-      NEW met1 ( 2011970 1689290 ) M1M2_PR ;
-    - la_data_out[118] ( PIN la_data_out[118] ) ( mprj la_data_out[118] ) + USE SIGNAL
-      + ROUTED met2 ( 2015490 47430 ) ( * 1676700 )
-      NEW met2 ( 2015490 1676700 ) ( 2015950 * )
-      NEW met2 ( 2015950 1676700 ) ( * 1689460 )
-      NEW met2 ( 2015950 1689460 ) ( 2017030 * )
-      NEW met2 ( 2017030 1689460 ) ( * 1690140 0 )
-      NEW met2 ( 2727570 1700 0 ) ( * 47430 )
-      NEW met1 ( 2015490 47430 ) ( 2727570 * )
-      NEW met1 ( 2015490 47430 ) M1M2_PR
-      NEW met1 ( 2727570 47430 ) M1M2_PR ;
-    - la_data_out[119] ( PIN la_data_out[119] ) ( mprj la_data_out[119] ) + USE SIGNAL
-      + ROUTED met2 ( 2022390 1688780 ) ( 2022550 * )
-      NEW met2 ( 2022550 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 2022390 47090 ) ( * 1688780 )
-      NEW met1 ( 2022390 47090 ) ( 2745510 * )
-      NEW met2 ( 2745510 1700 0 ) ( * 47090 )
-      NEW met1 ( 2022390 47090 ) M1M2_PR
-      NEW met1 ( 2745510 47090 ) M1M2_PR ;
-    - la_data_out[11] ( PIN la_data_out[11] ) ( mprj la_data_out[11] ) + USE SIGNAL
-      + ROUTED met2 ( 830530 1700 0 ) ( * 39270 )
-      NEW met1 ( 1428530 1689290 ) ( 1430990 * )
-      NEW met2 ( 1430990 1689290 ) ( * 1690140 0 )
-      NEW met1 ( 830530 39270 ) ( 1428530 * )
-      NEW met2 ( 1428530 39270 ) ( * 1689290 )
-      NEW met1 ( 830530 39270 ) M1M2_PR
-      NEW met1 ( 1428530 1689290 ) M1M2_PR
-      NEW met1 ( 1430990 1689290 ) M1M2_PR
-      NEW met1 ( 1428530 39270 ) M1M2_PR ;
-    - la_data_out[120] ( PIN la_data_out[120] ) ( mprj la_data_out[120] ) + USE SIGNAL
-      + ROUTED met1 ( 2022850 1652570 ) ( 2027910 * )
-      NEW met2 ( 2022850 46750 ) ( * 1652570 )
-      NEW met2 ( 2027910 1688780 ) ( 2028070 * )
-      NEW met2 ( 2028070 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 2027910 1652570 ) ( * 1688780 )
-      NEW met1 ( 2022850 46750 ) ( 2763450 * )
-      NEW met2 ( 2763450 1700 0 ) ( * 46750 )
-      NEW met1 ( 2022850 1652570 ) M1M2_PR
-      NEW met1 ( 2027910 1652570 ) M1M2_PR
-      NEW met1 ( 2022850 46750 ) M1M2_PR
-      NEW met1 ( 2763450 46750 ) M1M2_PR ;
-    - la_data_out[121] ( PIN la_data_out[121] ) ( mprj la_data_out[121] ) + USE SIGNAL
-      + ROUTED met1 ( 2029290 1688950 ) ( 2033590 * )
-      NEW met2 ( 2033590 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 2029290 46410 ) ( * 1688950 )
-      NEW met1 ( 2029290 46410 ) ( 2780930 * )
-      NEW met2 ( 2780930 1700 0 ) ( * 46410 )
-      NEW met1 ( 2029290 46410 ) M1M2_PR
-      NEW met1 ( 2029290 1688950 ) M1M2_PR
-      NEW met1 ( 2033590 1688950 ) M1M2_PR
-      NEW met1 ( 2780930 46410 ) M1M2_PR ;
-    - la_data_out[122] ( PIN la_data_out[122] ) ( mprj la_data_out[122] ) + USE SIGNAL
-      + ROUTED met2 ( 2036190 46070 ) ( * 1580100 )
-      NEW met2 ( 2036190 1580100 ) ( 2038490 * )
-      NEW met2 ( 2038490 1688780 ) ( 2039110 * )
-      NEW met2 ( 2039110 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 2038490 1580100 ) ( * 1688780 )
-      NEW met2 ( 2798870 1700 0 ) ( * 46070 )
-      NEW met1 ( 2036190 46070 ) ( 2798870 * )
-      NEW met1 ( 2036190 46070 ) M1M2_PR
-      NEW met1 ( 2798870 46070 ) M1M2_PR ;
-    - la_data_out[123] ( PIN la_data_out[123] ) ( mprj la_data_out[123] ) + USE SIGNAL
-      + ROUTED met2 ( 2043550 1689460 ) ( 2044630 * )
-      NEW met2 ( 2044630 1689460 ) ( * 1690140 0 )
-      NEW met2 ( 2043550 45730 ) ( * 1689460 )
-      NEW met2 ( 2816350 1700 0 ) ( * 45730 )
-      NEW met1 ( 2043550 45730 ) ( 2816350 * )
-      NEW met1 ( 2043550 45730 ) M1M2_PR
-      NEW met1 ( 2816350 45730 ) M1M2_PR ;
-    - la_data_out[124] ( PIN la_data_out[124] ) ( mprj la_data_out[124] ) + USE SIGNAL
-      + ROUTED met2 ( 2049990 1688780 ) ( 2050150 * )
-      NEW met2 ( 2050150 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 2049990 45390 ) ( * 1688780 )
-      NEW met2 ( 2834290 1700 0 ) ( * 45390 )
-      NEW met1 ( 2049990 45390 ) ( 2834290 * )
-      NEW met1 ( 2049990 45390 ) M1M2_PR
-      NEW met1 ( 2834290 45390 ) M1M2_PR ;
-    - la_data_out[125] ( PIN la_data_out[125] ) ( mprj la_data_out[125] ) + USE SIGNAL
-      + ROUTED met2 ( 2050450 45050 ) ( * 1580100 )
-      NEW met2 ( 2050450 1580100 ) ( 2052750 * )
-      NEW met2 ( 2052750 1688780 ) ( 2055670 * )
-      NEW met2 ( 2055670 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 2052750 1580100 ) ( * 1688780 )
-      NEW met1 ( 2050450 45050 ) ( 2851770 * )
-      NEW met2 ( 2851770 1700 0 ) ( * 45050 )
-      NEW met1 ( 2050450 45050 ) M1M2_PR
-      NEW met1 ( 2851770 45050 ) M1M2_PR ;
-    - la_data_out[126] ( PIN la_data_out[126] ) ( mprj la_data_out[126] ) + USE SIGNAL
-      + ROUTED met2 ( 2057350 44710 ) ( * 1580100 )
-      NEW met2 ( 2057350 1580100 ) ( 2061030 * )
-      NEW met2 ( 2061030 1688780 ) ( 2061190 * )
-      NEW met2 ( 2061190 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 2061030 1580100 ) ( * 1688780 )
-      NEW met1 ( 2057350 44710 ) ( 2869710 * )
-      NEW met2 ( 2869710 1700 0 ) ( * 44710 )
-      NEW met1 ( 2057350 44710 ) M1M2_PR
-      NEW met1 ( 2869710 44710 ) M1M2_PR ;
-    - la_data_out[127] ( PIN la_data_out[127] ) ( mprj la_data_out[127] ) + USE SIGNAL
-      + ROUTED met2 ( 2887190 1700 0 ) ( * 44540 )
-      NEW met2 ( 2063790 44540 ) ( * 1676700 )
-      NEW met2 ( 2063790 1676700 ) ( 2065630 * )
-      NEW met2 ( 2065630 1676700 ) ( * 1688780 )
-      NEW met2 ( 2065630 1688780 ) ( 2066710 * )
-      NEW met2 ( 2066710 1688780 ) ( * 1690140 0 )
-      NEW met3 ( 2063790 44540 ) ( 2887190 * )
-      NEW met2 ( 2887190 44540 ) M2M3_PR
-      NEW met2 ( 2063790 44540 ) M2M3_PR ;
-    - la_data_out[12] ( PIN la_data_out[12] ) ( mprj la_data_out[12] ) + USE SIGNAL
-      + ROUTED met2 ( 1435430 1688780 ) ( 1436510 * )
-      NEW met2 ( 1436510 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 848010 1700 0 ) ( * 39610 )
-      NEW met1 ( 848010 39610 ) ( 1435430 * )
-      NEW met2 ( 1435430 39610 ) ( * 1688780 )
-      NEW met1 ( 848010 39610 ) M1M2_PR
-      NEW met1 ( 1435430 39610 ) M1M2_PR ;
-    - la_data_out[13] ( PIN la_data_out[13] ) ( mprj la_data_out[13] ) + USE SIGNAL
-      + ROUTED met1 ( 1435890 1652570 ) ( 1441870 * )
-      NEW met2 ( 865950 1700 0 ) ( * 39950 )
-      NEW met2 ( 1441870 1688780 ) ( 1442030 * )
-      NEW met2 ( 1442030 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1441870 1652570 ) ( * 1688780 )
-      NEW met1 ( 865950 39950 ) ( 1435890 * )
-      NEW met2 ( 1435890 39950 ) ( * 1652570 )
-      NEW met1 ( 1435890 1652570 ) M1M2_PR
-      NEW met1 ( 1441870 1652570 ) M1M2_PR
-      NEW met1 ( 865950 39950 ) M1M2_PR
-      NEW met1 ( 1435890 39950 ) M1M2_PR ;
-    - la_data_out[14] ( PIN la_data_out[14] ) ( mprj la_data_out[14] ) + USE SIGNAL
-      + ROUTED met2 ( 883430 1700 0 ) ( * 17340 )
-      NEW met2 ( 883430 17340 ) ( 883890 * )
-      NEW met2 ( 883890 17340 ) ( * 40290 )
-      NEW met2 ( 1443250 1580100 ) ( 1446930 * )
-      NEW met2 ( 1446930 1688780 ) ( 1447550 * )
-      NEW met2 ( 1447550 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1446930 1580100 ) ( * 1688780 )
-      NEW met1 ( 883890 40290 ) ( 1443250 * )
-      NEW met2 ( 1443250 40290 ) ( * 1580100 )
-      NEW met1 ( 883890 40290 ) M1M2_PR
-      NEW met1 ( 1443250 40290 ) M1M2_PR ;
-    - la_data_out[15] ( PIN la_data_out[15] ) ( mprj la_data_out[15] ) + USE SIGNAL
-      + ROUTED met2 ( 901370 1700 0 ) ( * 40630 )
-      NEW met2 ( 1450610 1580100 ) ( 1452450 * )
-      NEW met2 ( 1452450 1688780 ) ( 1453070 * )
-      NEW met2 ( 1453070 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1452450 1580100 ) ( * 1688780 )
-      NEW met1 ( 901370 40630 ) ( 1450610 * )
-      NEW met2 ( 1450610 40630 ) ( * 1580100 )
-      NEW met1 ( 901370 40630 ) M1M2_PR
-      NEW met1 ( 1450610 40630 ) M1M2_PR ;
-    - la_data_out[16] ( PIN la_data_out[16] ) ( mprj la_data_out[16] ) + USE SIGNAL
-      + ROUTED met2 ( 1457510 1688780 ) ( 1458590 * )
-      NEW met2 ( 1458590 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 918850 1700 0 ) ( * 40970 )
-      NEW met1 ( 918850 40970 ) ( 1457510 * )
-      NEW met2 ( 1457510 40970 ) ( * 1688780 )
-      NEW met1 ( 918850 40970 ) M1M2_PR
-      NEW met1 ( 1457510 40970 ) M1M2_PR ;
-    - la_data_out[17] ( PIN la_data_out[17] ) ( mprj la_data_out[17] ) + USE SIGNAL
-      + ROUTED met2 ( 1463490 1688780 ) ( 1464110 * )
-      NEW met2 ( 1464110 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1463490 41310 ) ( * 1688780 )
-      NEW met2 ( 936790 1700 0 ) ( * 41310 )
-      NEW met1 ( 936790 41310 ) ( 1463490 * )
-      NEW met1 ( 1463490 41310 ) M1M2_PR
-      NEW met1 ( 936790 41310 ) M1M2_PR ;
-    - la_data_out[18] ( PIN la_data_out[18] ) ( mprj la_data_out[18] ) + USE SIGNAL
-      + ROUTED met1 ( 1463950 1643730 ) ( 1469470 * )
-      NEW met2 ( 954270 1700 0 ) ( * 37570 )
-      NEW met2 ( 1463950 37570 ) ( * 1643730 )
-      NEW met2 ( 1469470 1688780 ) ( 1469630 * )
-      NEW met2 ( 1469630 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1469470 1643730 ) ( * 1688780 )
-      NEW met1 ( 954270 37570 ) ( 1463950 * )
-      NEW met1 ( 1463950 1643730 ) M1M2_PR
-      NEW met1 ( 1469470 1643730 ) M1M2_PR
-      NEW met1 ( 954270 37570 ) M1M2_PR
-      NEW met1 ( 1463950 37570 ) M1M2_PR ;
-    - la_data_out[19] ( PIN la_data_out[19] ) ( mprj la_data_out[19] ) + USE SIGNAL
-      + ROUTED met2 ( 972210 1700 0 ) ( * 37230 )
-      NEW met1 ( 1470390 1688950 ) ( 1475150 * )
-      NEW met2 ( 1475150 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1470390 37230 ) ( * 1688950 )
-      NEW met1 ( 972210 37230 ) ( 1470390 * )
-      NEW met1 ( 972210 37230 ) M1M2_PR
-      NEW met1 ( 1470390 37230 ) M1M2_PR
-      NEW met1 ( 1470390 1688950 ) M1M2_PR
-      NEW met1 ( 1475150 1688950 ) M1M2_PR ;
-    - la_data_out[1] ( PIN la_data_out[1] ) ( mprj la_data_out[1] ) + USE SIGNAL
-      + ROUTED met1 ( 1374250 1688270 ) ( 1376250 * )
-      NEW met1 ( 1376250 1688270 ) ( * 1689290 )
-      NEW met2 ( 1376250 1689290 ) ( * 1690140 0 )
-      NEW met2 ( 1374250 38250 ) ( * 1688270 )
-      NEW met2 ( 652970 1700 0 ) ( * 38250 )
-      NEW met1 ( 652970 38250 ) ( 1374250 * )
-      NEW met1 ( 1374250 38250 ) M1M2_PR
-      NEW met1 ( 1374250 1688270 ) M1M2_PR
-      NEW met1 ( 1376250 1689290 ) M1M2_PR
-      NEW met1 ( 652970 38250 ) M1M2_PR ;
-    - la_data_out[20] ( PIN la_data_out[20] ) ( mprj la_data_out[20] ) + USE SIGNAL
-      + ROUTED met2 ( 989690 1700 0 ) ( * 36890 )
-      NEW met2 ( 1477290 36890 ) ( * 1676700 )
-      NEW met2 ( 1477290 1676700 ) ( 1480050 * )
-      NEW met2 ( 1480050 1676700 ) ( * 1688780 )
-      NEW met2 ( 1480050 1688780 ) ( 1480210 * )
-      NEW met2 ( 1480210 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 989690 36890 ) ( 1477290 * )
-      NEW met1 ( 989690 36890 ) M1M2_PR
-      NEW met1 ( 1477290 36890 ) M1M2_PR ;
-    - la_data_out[21] ( PIN la_data_out[21] ) ( mprj la_data_out[21] ) + USE SIGNAL
-      + ROUTED met1 ( 1008090 89250 ) ( 1484650 * )
-      NEW met2 ( 1007630 1700 0 ) ( * 34500 )
-      NEW met2 ( 1007630 34500 ) ( 1008090 * )
-      NEW met2 ( 1008090 34500 ) ( * 89250 )
-      NEW met2 ( 1484650 1688780 ) ( 1485730 * )
-      NEW met2 ( 1485730 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1484650 89250 ) ( * 1688780 )
-      NEW met1 ( 1008090 89250 ) M1M2_PR
-      NEW met1 ( 1484650 89250 ) M1M2_PR ;
-    - la_data_out[22] ( PIN la_data_out[22] ) ( mprj la_data_out[22] ) + USE SIGNAL
-      + ROUTED met1 ( 1021430 89590 ) ( 1491550 * )
-      NEW met2 ( 1021430 82800 ) ( * 89590 )
-      NEW met2 ( 1021430 82800 ) ( 1025570 * )
-      NEW met2 ( 1025570 1700 0 ) ( * 82800 )
-      NEW met2 ( 1491320 1688780 ) ( 1491550 * )
-      NEW met2 ( 1491320 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1491550 89590 ) ( * 1688780 )
-      NEW met1 ( 1021430 89590 ) M1M2_PR
-      NEW met1 ( 1491550 89590 ) M1M2_PR ;
-    - la_data_out[23] ( PIN la_data_out[23] ) ( mprj la_data_out[23] ) + USE SIGNAL
-      + ROUTED met1 ( 1042130 85850 ) ( 1492010 * )
-      NEW met2 ( 1042130 82800 ) ( * 85850 )
-      NEW met2 ( 1042130 82800 ) ( 1043050 * )
-      NEW met2 ( 1043050 1700 0 ) ( * 82800 )
-      NEW met2 ( 1492010 1688780 ) ( 1496770 * )
-      NEW met2 ( 1496770 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1492010 85850 ) ( * 1688780 )
-      NEW met1 ( 1042130 85850 ) M1M2_PR
-      NEW met1 ( 1492010 85850 ) M1M2_PR ;
-    - la_data_out[24] ( PIN la_data_out[24] ) ( mprj la_data_out[24] ) + USE SIGNAL
-      + ROUTED met2 ( 1058690 1700 ) ( 1060990 * 0 )
-      NEW met2 ( 1055930 82800 ) ( * 85510 )
-      NEW met2 ( 1055930 82800 ) ( 1058690 * )
-      NEW met2 ( 1058690 1700 ) ( * 82800 )
-      NEW met1 ( 1055930 85510 ) ( 1498910 * )
-      NEW met2 ( 1498910 1688780 ) ( 1502290 * )
-      NEW met2 ( 1502290 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1498910 85510 ) ( * 1688780 )
-      NEW met1 ( 1055930 85510 ) M1M2_PR
-      NEW met1 ( 1498910 85510 ) M1M2_PR ;
-    - la_data_out[25] ( PIN la_data_out[25] ) ( mprj la_data_out[25] ) + USE SIGNAL
-      + ROUTED met2 ( 1076630 1700 ) ( 1078470 * 0 )
-      NEW met2 ( 1076630 1700 ) ( * 85170 )
-      NEW met1 ( 1076630 85170 ) ( 1505350 * )
-      NEW met2 ( 1505350 1688780 ) ( 1507810 * )
-      NEW met2 ( 1507810 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1505350 85170 ) ( * 1688780 )
-      NEW met1 ( 1076630 85170 ) M1M2_PR
-      NEW met1 ( 1505350 85170 ) M1M2_PR ;
-    - la_data_out[26] ( PIN la_data_out[26] ) ( mprj la_data_out[26] ) + USE SIGNAL
-      + ROUTED met2 ( 1096410 1700 0 ) ( * 47770 )
-      NEW met2 ( 1511790 1688780 ) ( 1513330 * )
-      NEW met2 ( 1513330 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1511790 47770 ) ( * 1688780 )
-      NEW met1 ( 1096410 47770 ) ( 1511790 * )
-      NEW met1 ( 1096410 47770 ) M1M2_PR
-      NEW met1 ( 1511790 47770 ) M1M2_PR ;
-    - la_data_out[27] ( PIN la_data_out[27] ) ( mprj la_data_out[27] ) + USE SIGNAL
-      + ROUTED met2 ( 1113890 1700 0 ) ( * 48110 )
-      NEW met2 ( 1518690 1688780 ) ( 1518850 * )
-      NEW met2 ( 1518850 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1518690 48110 ) ( * 1688780 )
-      NEW met1 ( 1113890 48110 ) ( 1518690 * )
-      NEW met1 ( 1113890 48110 ) M1M2_PR
-      NEW met1 ( 1518690 48110 ) M1M2_PR ;
-    - la_data_out[28] ( PIN la_data_out[28] ) ( mprj la_data_out[28] ) + USE SIGNAL
-      + ROUTED met2 ( 1131830 1700 0 ) ( * 17340 )
-      NEW met2 ( 1131830 17340 ) ( 1132290 * )
-      NEW met2 ( 1132290 17340 ) ( * 44370 )
-      NEW met1 ( 1518230 1688950 ) ( 1524370 * )
-      NEW met2 ( 1524370 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1518230 44370 ) ( * 1688950 )
-      NEW met1 ( 1132290 44370 ) ( 1518230 * )
-      NEW met1 ( 1132290 44370 ) M1M2_PR
-      NEW met1 ( 1518230 44370 ) M1M2_PR
-      NEW met1 ( 1518230 1688950 ) M1M2_PR
-      NEW met1 ( 1524370 1688950 ) M1M2_PR ;
-    - la_data_out[29] ( PIN la_data_out[29] ) ( mprj la_data_out[29] ) + USE SIGNAL
-      + ROUTED met2 ( 1149310 1700 0 ) ( * 44030 )
-      NEW met1 ( 1525130 1688950 ) ( 1529890 * )
-      NEW met2 ( 1529890 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1525130 44030 ) ( * 1688950 )
-      NEW met1 ( 1149310 44030 ) ( 1525130 * )
-      NEW met1 ( 1149310 44030 ) M1M2_PR
-      NEW met1 ( 1525130 44030 ) M1M2_PR
-      NEW met1 ( 1525130 1688950 ) M1M2_PR
-      NEW met1 ( 1529890 1688950 ) M1M2_PR ;
-    - la_data_out[2] ( PIN la_data_out[2] ) ( mprj la_data_out[2] ) + USE SIGNAL
-      + ROUTED met2 ( 670910 1700 0 ) ( * 38590 )
-      NEW met2 ( 1381150 1688780 ) ( 1381770 * )
-      NEW met2 ( 1381770 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1381150 38590 ) ( * 1688780 )
-      NEW met1 ( 670910 38590 ) ( 1381150 * )
-      NEW met1 ( 670910 38590 ) M1M2_PR
-      NEW met1 ( 1381150 38590 ) M1M2_PR ;
-    - la_data_out[30] ( PIN la_data_out[30] ) ( mprj la_data_out[30] ) + USE SIGNAL
-      + ROUTED met2 ( 1167250 1700 0 ) ( * 43690 )
-      NEW met2 ( 1532950 43690 ) ( * 1676700 )
-      NEW met2 ( 1532950 1676700 ) ( 1534790 * )
-      NEW met2 ( 1534790 1676700 ) ( * 1688780 )
-      NEW met2 ( 1534790 1688780 ) ( 1535410 * )
-      NEW met2 ( 1535410 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1167250 43690 ) ( 1532950 * )
-      NEW met1 ( 1167250 43690 ) M1M2_PR
-      NEW met1 ( 1532950 43690 ) M1M2_PR ;
-    - la_data_out[31] ( PIN la_data_out[31] ) ( mprj la_data_out[31] ) + USE SIGNAL
-      + ROUTED met2 ( 1185190 1700 0 ) ( * 30770 )
-      NEW met2 ( 1539390 1688780 ) ( 1540470 * )
-      NEW met2 ( 1540470 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1539390 30770 ) ( * 1688780 )
-      NEW met1 ( 1185190 30770 ) ( 1539390 * )
-      NEW met1 ( 1185190 30770 ) M1M2_PR
-      NEW met1 ( 1539390 30770 ) M1M2_PR ;
-    - la_data_out[32] ( PIN la_data_out[32] ) ( mprj la_data_out[32] ) + USE SIGNAL
-      + ROUTED met2 ( 1546290 1653420 ) ( 1547210 * )
-      NEW met2 ( 1547210 31450 ) ( * 1653420 )
-      NEW met2 ( 1546060 1688780 ) ( 1546290 * )
-      NEW met2 ( 1546060 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1546290 1653420 ) ( * 1688780 )
-      NEW met2 ( 1202670 1700 0 ) ( * 31450 )
-      NEW met1 ( 1202670 31450 ) ( 1547210 * )
-      NEW met1 ( 1547210 31450 ) M1M2_PR
-      NEW met1 ( 1202670 31450 ) M1M2_PR ;
-    - la_data_out[33] ( PIN la_data_out[33] ) ( mprj la_data_out[33] ) + USE SIGNAL
-      + ROUTED met2 ( 1551350 1682830 ) ( * 1688780 )
-      NEW met2 ( 1551350 1688780 ) ( 1551510 * )
-      NEW met2 ( 1551510 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1220610 1700 0 ) ( * 16830 )
-      NEW met1 ( 1220610 16830 ) ( 1328250 * )
-      NEW met2 ( 1328250 16830 ) ( * 1682830 )
-      NEW met1 ( 1328250 1682830 ) ( 1551350 * )
-      NEW met1 ( 1551350 1682830 ) M1M2_PR
-      NEW met1 ( 1220610 16830 ) M1M2_PR
-      NEW met1 ( 1328250 16830 ) M1M2_PR
-      NEW met1 ( 1328250 1682830 ) M1M2_PR ;
-    - la_data_out[34] ( PIN la_data_out[34] ) ( mprj la_data_out[34] ) + USE SIGNAL
-      + ROUTED met1 ( 1553190 1639650 ) ( 1556870 * )
-      NEW met2 ( 1553190 24140 ) ( * 1639650 )
-      NEW met2 ( 1556870 1688780 ) ( 1557030 * )
-      NEW met2 ( 1557030 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1556870 1639650 ) ( * 1688780 )
-      NEW met2 ( 1238090 1700 0 ) ( * 18190 )
-      NEW met2 ( 1495230 18190 ) ( * 24140 )
-      NEW met3 ( 1495230 24140 ) ( 1553190 * )
-      NEW met1 ( 1238090 18190 ) ( 1495230 * )
-      NEW met2 ( 1553190 24140 ) M2M3_PR
-      NEW met1 ( 1553190 1639650 ) M1M2_PR
-      NEW met1 ( 1556870 1639650 ) M1M2_PR
-      NEW met1 ( 1238090 18190 ) M1M2_PR
-      NEW met1 ( 1495230 18190 ) M1M2_PR
-      NEW met2 ( 1495230 24140 ) M2M3_PR ;
-    - la_data_out[35] ( PIN la_data_out[35] ) ( mprj la_data_out[35] ) + USE SIGNAL
-      + ROUTED met2 ( 1256030 1700 0 ) ( * 32130 )
-      NEW met2 ( 1560550 1688780 ) ( 1562550 * )
-      NEW met2 ( 1562550 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1560550 32130 ) ( * 1688780 )
-      NEW met1 ( 1256030 32130 ) ( 1560550 * )
-      NEW met1 ( 1256030 32130 ) M1M2_PR
-      NEW met1 ( 1560550 32130 ) M1M2_PR ;
-    - la_data_out[36] ( PIN la_data_out[36] ) ( mprj la_data_out[36] ) + USE SIGNAL
-      + ROUTED met2 ( 1273510 1700 0 ) ( * 32470 )
-      NEW met2 ( 1566990 1688780 ) ( 1568070 * )
-      NEW met2 ( 1568070 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1566990 32470 ) ( * 1688780 )
-      NEW met1 ( 1273510 32470 ) ( 1566990 * )
-      NEW met1 ( 1273510 32470 ) M1M2_PR
-      NEW met1 ( 1566990 32470 ) M1M2_PR ;
-    - la_data_out[37] ( PIN la_data_out[37] ) ( mprj la_data_out[37] ) + USE SIGNAL
-      + ROUTED met2 ( 1573660 1688780 ) ( 1573890 * )
-      NEW met2 ( 1573660 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1573890 32810 ) ( * 1688780 )
-      NEW met2 ( 1291450 1700 0 ) ( * 32810 )
-      NEW met1 ( 1291450 32810 ) ( 1573890 * )
-      NEW met1 ( 1573890 32810 ) M1M2_PR
-      NEW met1 ( 1291450 32810 ) M1M2_PR ;
-    - la_data_out[38] ( PIN la_data_out[38] ) ( mprj la_data_out[38] ) + USE SIGNAL
-      + ROUTED met1 ( 1574350 1688950 ) ( 1579110 * )
-      NEW met2 ( 1579110 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1574350 33150 ) ( * 1688950 )
-      NEW met2 ( 1308930 1700 0 ) ( * 33150 )
-      NEW met1 ( 1308930 33150 ) ( 1574350 * )
-      NEW met1 ( 1574350 33150 ) M1M2_PR
-      NEW met1 ( 1574350 1688950 ) M1M2_PR
-      NEW met1 ( 1579110 1688950 ) M1M2_PR
-      NEW met1 ( 1308930 33150 ) M1M2_PR ;
-    - la_data_out[39] ( PIN la_data_out[39] ) ( mprj la_data_out[39] ) + USE SIGNAL
-      + ROUTED met2 ( 1326870 1700 0 ) ( * 33490 )
-      NEW met2 ( 1581250 1688780 ) ( 1584630 * )
-      NEW met2 ( 1584630 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1581250 33490 ) ( * 1688780 )
-      NEW met1 ( 1326870 33490 ) ( 1581250 * )
-      NEW met1 ( 1326870 33490 ) M1M2_PR
-      NEW met1 ( 1581250 33490 ) M1M2_PR ;
-    - la_data_out[3] ( PIN la_data_out[3] ) ( mprj la_data_out[3] ) + USE SIGNAL
-      + ROUTED met2 ( 688390 1700 0 ) ( * 47090 )
-      NEW met1 ( 688390 47090 ) ( 1387590 * )
-      NEW met2 ( 1387360 1688780 ) ( 1387590 * )
-      NEW met2 ( 1387360 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1387590 47090 ) ( * 1688780 )
-      NEW met1 ( 688390 47090 ) M1M2_PR
-      NEW met1 ( 1387590 47090 ) M1M2_PR ;
-    - la_data_out[40] ( PIN la_data_out[40] ) ( mprj la_data_out[40] ) + USE SIGNAL
-      + ROUTED met2 ( 1344350 1700 0 ) ( * 33830 )
-      NEW met2 ( 1588610 1688780 ) ( 1590150 * )
-      NEW met2 ( 1590150 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1588610 33830 ) ( * 1688780 )
-      NEW met1 ( 1344350 33830 ) ( 1588610 * )
-      NEW met1 ( 1344350 33830 ) M1M2_PR
-      NEW met1 ( 1588610 33830 ) M1M2_PR ;
-    - la_data_out[41] ( PIN la_data_out[41] ) ( mprj la_data_out[41] ) + USE SIGNAL
-      + ROUTED met2 ( 1362290 1700 0 ) ( * 34170 )
-      NEW met2 ( 1595050 1688780 ) ( 1595670 * )
-      NEW met2 ( 1595670 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1595050 34170 ) ( * 1688780 )
-      NEW met1 ( 1362290 34170 ) ( 1595050 * )
-      NEW met1 ( 1362290 34170 ) M1M2_PR
-      NEW met1 ( 1595050 34170 ) M1M2_PR ;
-    - la_data_out[42] ( PIN la_data_out[42] ) ( mprj la_data_out[42] ) + USE SIGNAL
-      + ROUTED met2 ( 1380230 1700 0 ) ( * 30090 )
-      NEW met1 ( 1380230 30090 ) ( 1386900 * )
-      NEW met1 ( 1386900 30090 ) ( * 30430 )
-      NEW met1 ( 1595510 1652570 ) ( 1600570 * )
-      NEW met2 ( 1595510 30430 ) ( * 1652570 )
-      NEW met2 ( 1600570 1688780 ) ( 1600730 * )
-      NEW met2 ( 1600730 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1600570 1652570 ) ( * 1688780 )
-      NEW met1 ( 1386900 30430 ) ( 1595510 * )
-      NEW met1 ( 1380230 30090 ) M1M2_PR
-      NEW met1 ( 1595510 30430 ) M1M2_PR
-      NEW met1 ( 1595510 1652570 ) M1M2_PR
-      NEW met1 ( 1600570 1652570 ) M1M2_PR ;
-    - la_data_out[43] ( PIN la_data_out[43] ) ( mprj la_data_out[43] ) + USE SIGNAL
-      + ROUTED met2 ( 1397710 1700 0 ) ( * 30090 )
-      NEW met1 ( 1601490 1688950 ) ( 1606250 * )
-      NEW met2 ( 1606250 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1601490 30090 ) ( * 1688950 )
-      NEW met1 ( 1397710 30090 ) ( 1601490 * )
-      NEW met1 ( 1397710 30090 ) M1M2_PR
-      NEW met1 ( 1601490 30090 ) M1M2_PR
-      NEW met1 ( 1601490 1688950 ) M1M2_PR
-      NEW met1 ( 1606250 1688950 ) M1M2_PR ;
-    - la_data_out[44] ( PIN la_data_out[44] ) ( mprj la_data_out[44] ) + USE SIGNAL
-      + ROUTED met2 ( 1609310 18530 ) ( * 1580100 )
-      NEW met2 ( 1609310 1580100 ) ( 1610230 * )
-      NEW met2 ( 1610230 1688780 ) ( 1611770 * )
-      NEW met2 ( 1611770 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1610230 1580100 ) ( * 1688780 )
-      NEW met2 ( 1415650 1700 0 ) ( * 18530 )
-      NEW met1 ( 1415650 18530 ) ( 1609310 * )
-      NEW met1 ( 1609310 18530 ) M1M2_PR
-      NEW met1 ( 1415650 18530 ) M1M2_PR ;
-    - la_data_out[45] ( PIN la_data_out[45] ) ( mprj la_data_out[45] ) + USE SIGNAL
-      + ROUTED met2 ( 1528810 16490 ) ( * 1678750 )
-      NEW met2 ( 1615750 1678750 ) ( * 1689460 )
-      NEW met2 ( 1615750 1689460 ) ( 1617290 * )
-      NEW met2 ( 1617290 1689460 ) ( * 1690140 0 )
-      NEW met1 ( 1528810 1678750 ) ( 1615750 * )
-      NEW met2 ( 1433130 1700 0 ) ( * 16490 )
-      NEW met1 ( 1433130 16490 ) ( 1528810 * )
-      NEW met1 ( 1528810 16490 ) M1M2_PR
-      NEW met1 ( 1528810 1678750 ) M1M2_PR
-      NEW met1 ( 1615750 1678750 ) M1M2_PR
-      NEW met1 ( 1433130 16490 ) M1M2_PR ;
-    - la_data_out[46] ( PIN la_data_out[46] ) ( mprj la_data_out[46] ) + USE SIGNAL
-      + ROUTED met2 ( 1622650 1688780 ) ( 1622810 * )
-      NEW met2 ( 1622810 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1622650 19550 ) ( * 1688780 )
-      NEW met2 ( 1451070 1700 0 ) ( * 19550 )
-      NEW met1 ( 1451070 19550 ) ( 1622650 * )
-      NEW met1 ( 1622650 19550 ) M1M2_PR
-      NEW met1 ( 1451070 19550 ) M1M2_PR ;
-    - la_data_out[47] ( PIN la_data_out[47] ) ( mprj la_data_out[47] ) + USE SIGNAL
-      + ROUTED met2 ( 1468550 1700 0 ) ( * 20230 )
-      NEW met1 ( 1468550 20230 ) ( 1528350 * )
-      NEW met2 ( 1528350 20230 ) ( * 1679090 )
-      NEW met2 ( 1628170 1679090 ) ( * 1688780 )
-      NEW met2 ( 1628170 1688780 ) ( 1628330 * )
-      NEW met2 ( 1628330 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1528350 1679090 ) ( 1628170 * )
-      NEW met1 ( 1468550 20230 ) M1M2_PR
-      NEW met1 ( 1528350 20230 ) M1M2_PR
-      NEW met1 ( 1528350 1679090 ) M1M2_PR
-      NEW met1 ( 1628170 1679090 ) M1M2_PR ;
-    - la_data_out[48] ( PIN la_data_out[48] ) ( mprj la_data_out[48] ) + USE SIGNAL
-      + ROUTED met2 ( 1562850 15470 ) ( * 1680790 )
-      NEW met2 ( 1633690 1680790 ) ( * 1688780 )
-      NEW met2 ( 1633690 1688780 ) ( 1633850 * )
-      NEW met2 ( 1633850 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1486490 1700 0 ) ( * 15470 )
-      NEW met1 ( 1486490 15470 ) ( 1562850 * )
-      NEW met1 ( 1562850 1680790 ) ( 1633690 * )
-      NEW met1 ( 1562850 15470 ) M1M2_PR
-      NEW met1 ( 1562850 1680790 ) M1M2_PR
-      NEW met1 ( 1633690 1680790 ) M1M2_PR
-      NEW met1 ( 1486490 15470 ) M1M2_PR ;
-    - la_data_out[49] ( PIN la_data_out[49] ) ( mprj la_data_out[49] ) + USE SIGNAL
-      + ROUTED met2 ( 1535250 20570 ) ( * 1580100 )
-      NEW met2 ( 1535250 1580100 ) ( 1535710 * )
-      NEW met2 ( 1535710 1580100 ) ( * 1679430 )
-      NEW met2 ( 1639210 1679430 ) ( * 1688780 )
-      NEW met2 ( 1639210 1688780 ) ( 1639370 * )
-      NEW met2 ( 1639370 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1503970 1700 0 ) ( * 20570 )
-      NEW met1 ( 1503970 20570 ) ( 1535250 * )
-      NEW met1 ( 1535710 1679430 ) ( 1639210 * )
-      NEW met1 ( 1535250 20570 ) M1M2_PR
-      NEW met1 ( 1535710 1679430 ) M1M2_PR
-      NEW met1 ( 1639210 1679430 ) M1M2_PR
-      NEW met1 ( 1503970 20570 ) M1M2_PR ;
-    - la_data_out[4] ( PIN la_data_out[4] ) ( mprj la_data_out[4] ) + USE SIGNAL
-      + ROUTED met2 ( 706330 1700 0 ) ( * 47430 )
-      NEW met1 ( 706330 47430 ) ( 1388050 * )
-      NEW met1 ( 1388050 1688950 ) ( 1392810 * )
-      NEW met2 ( 1392810 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1388050 47430 ) ( * 1688950 )
-      NEW met1 ( 706330 47430 ) M1M2_PR
-      NEW met1 ( 1388050 47430 ) M1M2_PR
-      NEW met1 ( 1388050 1688950 ) M1M2_PR
-      NEW met1 ( 1392810 1688950 ) M1M2_PR ;
-    - la_data_out[50] ( PIN la_data_out[50] ) ( mprj la_data_out[50] ) + USE SIGNAL
-      + ROUTED met2 ( 1642430 1652740 ) ( 1642890 * )
-      NEW met2 ( 1642890 18190 ) ( * 1652740 )
-      NEW met1 ( 1642430 1689290 ) ( 1644890 * )
-      NEW met2 ( 1644890 1689290 ) ( * 1690140 0 )
-      NEW met2 ( 1642430 1652740 ) ( * 1689290 )
-      NEW met2 ( 1521910 1700 0 ) ( * 18190 )
-      NEW met1 ( 1521910 18190 ) ( 1642890 * )
-      NEW met1 ( 1642890 18190 ) M1M2_PR
-      NEW met1 ( 1642430 1689290 ) M1M2_PR
-      NEW met1 ( 1644890 1689290 ) M1M2_PR
-      NEW met1 ( 1521910 18190 ) M1M2_PR ;
-    - la_data_out[51] ( PIN la_data_out[51] ) ( mprj la_data_out[51] ) + USE SIGNAL
-      + ROUTED met2 ( 1539850 1700 0 ) ( * 20230 )
-      NEW met2 ( 1649790 1688780 ) ( 1650410 * )
-      NEW met2 ( 1650410 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1649790 20230 ) ( * 1688780 )
-      NEW met1 ( 1539850 20230 ) ( 1649790 * )
-      NEW met1 ( 1539850 20230 ) M1M2_PR
-      NEW met1 ( 1649790 20230 ) M1M2_PR ;
-    - la_data_out[52] ( PIN la_data_out[52] ) ( mprj la_data_out[52] ) + USE SIGNAL
-      + ROUTED met2 ( 1557330 1700 0 ) ( * 17170 )
-      NEW met1 ( 1650250 1652570 ) ( 1655310 * )
-      NEW met2 ( 1650250 17170 ) ( * 1652570 )
-      NEW met2 ( 1655310 1688780 ) ( 1655470 * )
-      NEW met2 ( 1655470 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1655310 1652570 ) ( * 1688780 )
-      NEW met1 ( 1557330 17170 ) ( 1650250 * )
-      NEW met1 ( 1557330 17170 ) M1M2_PR
-      NEW met1 ( 1650250 17170 ) M1M2_PR
-      NEW met1 ( 1650250 1652570 ) M1M2_PR
-      NEW met1 ( 1655310 1652570 ) M1M2_PR ;
-    - la_data_out[53] ( PIN la_data_out[53] ) ( mprj la_data_out[53] ) + USE SIGNAL
-      + ROUTED met2 ( 1575270 1700 0 ) ( * 17850 )
-      NEW met1 ( 1656690 1688950 ) ( 1660990 * )
-      NEW met2 ( 1660990 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1656690 17850 ) ( * 1688950 )
-      NEW met1 ( 1575270 17850 ) ( 1656690 * )
-      NEW met1 ( 1575270 17850 ) M1M2_PR
-      NEW met1 ( 1656690 17850 ) M1M2_PR
-      NEW met1 ( 1656690 1688950 ) M1M2_PR
-      NEW met1 ( 1660990 1688950 ) M1M2_PR ;
-    - la_data_out[54] ( PIN la_data_out[54] ) ( mprj la_data_out[54] ) + USE SIGNAL
-      + ROUTED met2 ( 1666350 1680450 ) ( * 1688780 )
-      NEW met2 ( 1666350 1688780 ) ( 1666510 * )
-      NEW met2 ( 1666510 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1590450 1700 ) ( 1592750 * 0 )
-      NEW met2 ( 1590450 1700 ) ( * 5780 )
-      NEW met2 ( 1587230 5780 ) ( 1590450 * )
-      NEW met2 ( 1587230 5780 ) ( * 1680450 )
-      NEW met1 ( 1587230 1680450 ) ( 1666350 * )
-      NEW met1 ( 1666350 1680450 ) M1M2_PR
-      NEW met1 ( 1587230 1680450 ) M1M2_PR ;
-    - la_data_out[55] ( PIN la_data_out[55] ) ( mprj la_data_out[55] ) + USE SIGNAL
-      + ROUTED met1 ( 1670490 1652570 ) ( 1671870 * )
-      NEW met2 ( 1670490 15130 ) ( * 1652570 )
-      NEW met2 ( 1671870 1688780 ) ( 1672030 * )
-      NEW met2 ( 1672030 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1671870 1652570 ) ( * 1688780 )
-      NEW met2 ( 1610690 1700 0 ) ( * 15130 )
-      NEW met1 ( 1610690 15130 ) ( 1670490 * )
-      NEW met1 ( 1670490 15130 ) M1M2_PR
-      NEW met1 ( 1670490 1652570 ) M1M2_PR
-      NEW met1 ( 1671870 1652570 ) M1M2_PR
-      NEW met1 ( 1610690 15130 ) M1M2_PR ;
-    - la_data_out[56] ( PIN la_data_out[56] ) ( mprj la_data_out[56] ) + USE SIGNAL
-      + ROUTED met2 ( 1628170 1700 0 ) ( * 18870 )
-      NEW met1 ( 1628170 18870 ) ( 1677390 * )
-      NEW met2 ( 1677390 1688780 ) ( 1677550 * )
-      NEW met2 ( 1677550 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1677390 18870 ) ( * 1688780 )
-      NEW met1 ( 1628170 18870 ) M1M2_PR
-      NEW met1 ( 1677390 18870 ) M1M2_PR ;
-    - la_data_out[57] ( PIN la_data_out[57] ) ( mprj la_data_out[57] ) + USE SIGNAL
-      + ROUTED met2 ( 1646110 1700 0 ) ( * 15810 )
-      NEW met1 ( 1646110 15810 ) ( 1678770 * )
-      NEW met2 ( 1678770 15810 ) ( * 1580100 )
-      NEW met2 ( 1678770 1580100 ) ( 1680150 * )
-      NEW met2 ( 1680150 1688780 ) ( 1683070 * )
-      NEW met2 ( 1683070 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1680150 1580100 ) ( * 1688780 )
-      NEW met1 ( 1646110 15810 ) M1M2_PR
-      NEW met1 ( 1678770 15810 ) M1M2_PR ;
-    - la_data_out[58] ( PIN la_data_out[58] ) ( mprj la_data_out[58] ) + USE SIGNAL
-      + ROUTED met2 ( 1663130 82800 ) ( 1663590 * )
-      NEW met2 ( 1663590 1700 0 ) ( * 82800 )
-      NEW met2 ( 1663130 82800 ) ( * 1676710 )
-      NEW met2 ( 1688430 1676710 ) ( * 1688780 )
-      NEW met2 ( 1688430 1688780 ) ( 1688590 * )
-      NEW met2 ( 1688590 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1663130 1676710 ) ( 1688430 * )
-      NEW met1 ( 1663130 1676710 ) M1M2_PR
-      NEW met1 ( 1688430 1676710 ) M1M2_PR ;
-    - la_data_out[59] ( PIN la_data_out[59] ) ( mprj la_data_out[59] ) + USE SIGNAL
-      + ROUTED met2 ( 1681530 1700 0 ) ( * 14450 )
-      NEW met1 ( 1681530 14450 ) ( 1690730 * )
-      NEW met2 ( 1690730 1689290 ) ( 1691190 * )
-      NEW met1 ( 1691190 1689290 ) ( 1694110 * )
-      NEW met2 ( 1694110 1689290 ) ( * 1690140 0 )
-      NEW met2 ( 1690730 14450 ) ( * 1689290 )
-      NEW met1 ( 1681530 14450 ) M1M2_PR
-      NEW met1 ( 1690730 14450 ) M1M2_PR
-      NEW met1 ( 1691190 1689290 ) M1M2_PR
-      NEW met1 ( 1694110 1689290 ) M1M2_PR ;
-    - la_data_out[5] ( PIN la_data_out[5] ) ( mprj la_data_out[5] ) + USE SIGNAL
-      + ROUTED met1 ( 717830 86530 ) ( 1394950 * )
-      NEW met1 ( 717830 58310 ) ( 723810 * )
-      NEW met2 ( 717830 58310 ) ( * 86530 )
-      NEW met2 ( 723810 1700 0 ) ( * 58310 )
-      NEW met2 ( 1394950 1688780 ) ( 1398330 * )
-      NEW met2 ( 1398330 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1394950 86530 ) ( * 1688780 )
-      NEW met1 ( 717830 86530 ) M1M2_PR
-      NEW met1 ( 1394950 86530 ) M1M2_PR
-      NEW met1 ( 717830 58310 ) M1M2_PR
-      NEW met1 ( 723810 58310 ) M1M2_PR ;
-    - la_data_out[60] ( PIN la_data_out[60] ) ( mprj la_data_out[60] ) + USE SIGNAL
-      + ROUTED met2 ( 1697630 1700 ) ( 1699470 * 0 )
-      NEW met1 ( 1697630 1688270 ) ( * 1689290 )
-      NEW met1 ( 1697630 1689290 ) ( 1699630 * )
-      NEW met2 ( 1699630 1689290 ) ( * 1690140 0 )
-      NEW met2 ( 1697630 1700 ) ( * 1688270 )
-      NEW met1 ( 1697630 1688270 ) M1M2_PR
-      NEW met1 ( 1699630 1689290 ) M1M2_PR ;
-    - la_data_out[61] ( PIN la_data_out[61] ) ( mprj la_data_out[61] ) + USE SIGNAL
-      + ROUTED met2 ( 1716950 1700 0 ) ( * 15810 )
-      NEW met1 ( 1705450 15810 ) ( 1716950 * )
-      NEW met2 ( 1705220 1688780 ) ( 1705450 * )
-      NEW met2 ( 1705220 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1705450 15810 ) ( * 1688780 )
-      NEW met1 ( 1716950 15810 ) M1M2_PR
-      NEW met1 ( 1705450 15810 ) M1M2_PR ;
-    - la_data_out[62] ( PIN la_data_out[62] ) ( mprj la_data_out[62] ) + USE SIGNAL
-      + ROUTED met2 ( 1734890 1700 0 ) ( * 15130 )
-      NEW met1 ( 1705910 15130 ) ( 1734890 * )
-      NEW met1 ( 1705910 1688950 ) ( 1710670 * )
-      NEW met2 ( 1710670 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1705910 15130 ) ( * 1688950 )
-      NEW met1 ( 1734890 15130 ) M1M2_PR
-      NEW met1 ( 1705910 15130 ) M1M2_PR
-      NEW met1 ( 1705910 1688950 ) M1M2_PR
-      NEW met1 ( 1710670 1688950 ) M1M2_PR ;
-    - la_data_out[63] ( PIN la_data_out[63] ) ( mprj la_data_out[63] ) + USE SIGNAL
-      + ROUTED met2 ( 1752370 1700 0 ) ( * 15470 )
-      NEW met1 ( 1712810 15470 ) ( 1752370 * )
-      NEW met2 ( 1712810 1688780 ) ( 1715730 * )
-      NEW met2 ( 1715730 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1712810 15470 ) ( * 1688780 )
-      NEW met1 ( 1752370 15470 ) M1M2_PR
-      NEW met1 ( 1712810 15470 ) M1M2_PR ;
-    - la_data_out[64] ( PIN la_data_out[64] ) ( mprj la_data_out[64] ) + USE SIGNAL
-      + ROUTED met2 ( 1770310 1700 0 ) ( * 16490 )
-      NEW met1 ( 1718330 16490 ) ( 1770310 * )
-      NEW met1 ( 1718330 1688950 ) ( 1721250 * )
-      NEW met2 ( 1721250 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1718330 16490 ) ( * 1688950 )
-      NEW met1 ( 1770310 16490 ) M1M2_PR
-      NEW met1 ( 1718330 16490 ) M1M2_PR
-      NEW met1 ( 1718330 1688950 ) M1M2_PR
-      NEW met1 ( 1721250 1688950 ) M1M2_PR ;
-    - la_data_out[65] ( PIN la_data_out[65] ) ( mprj la_data_out[65] ) + USE SIGNAL
-      + ROUTED met2 ( 1731210 1681810 ) ( * 1689290 )
-      NEW met1 ( 1726840 1689290 ) ( 1731210 * )
-      NEW met2 ( 1726840 1689290 ) ( * 1690140 0 )
-      NEW met2 ( 1787790 1700 0 ) ( * 16830 )
-      NEW met1 ( 1777210 16830 ) ( 1787790 * )
-      NEW met1 ( 1731210 1681810 ) ( 1777210 * )
-      NEW met2 ( 1777210 16830 ) ( * 1681810 )
-      NEW met1 ( 1731210 1681810 ) M1M2_PR
-      NEW met1 ( 1731210 1689290 ) M1M2_PR
-      NEW met1 ( 1726840 1689290 ) M1M2_PR
-      NEW met1 ( 1787790 16830 ) M1M2_PR
-      NEW met1 ( 1777210 16830 ) M1M2_PR
-      NEW met1 ( 1777210 1681810 ) M1M2_PR ;
-    - la_data_out[66] ( PIN la_data_out[66] ) ( mprj la_data_out[66] ) + USE SIGNAL
-      + ROUTED met1 ( 1732130 16150 ) ( 1770770 * )
-      NEW met1 ( 1770770 16150 ) ( * 16830 )
-      NEW met2 ( 1732130 1688780 ) ( 1732290 * )
-      NEW met2 ( 1732290 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1732130 16150 ) ( * 1688780 )
-      NEW met1 ( 1770770 16830 ) ( 1773300 * )
-      NEW met2 ( 1805730 1700 0 ) ( * 16490 )
-      NEW met1 ( 1773300 16490 ) ( 1805730 * )
-      NEW met1 ( 1773300 16490 ) ( * 16830 )
-      NEW met1 ( 1732130 16150 ) M1M2_PR
-      NEW met1 ( 1805730 16490 ) M1M2_PR ;
-    - la_data_out[67] ( PIN la_data_out[67] ) ( mprj la_data_out[67] ) + USE SIGNAL
-      + ROUTED met2 ( 1823210 1700 0 ) ( * 16830 )
-      NEW met2 ( 1738110 1682150 ) ( * 1688780 )
-      NEW met2 ( 1737880 1688780 ) ( 1738110 * )
-      NEW met2 ( 1737880 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1812170 16830 ) ( 1823210 * )
-      NEW met2 ( 1811710 82800 ) ( 1812170 * )
-      NEW met2 ( 1812170 16830 ) ( * 82800 )
-      NEW met1 ( 1738110 1682150 ) ( 1811710 * )
-      NEW met2 ( 1811710 82800 ) ( * 1682150 )
-      NEW met1 ( 1823210 16830 ) M1M2_PR
-      NEW met1 ( 1738110 1682150 ) M1M2_PR
-      NEW met1 ( 1812170 16830 ) M1M2_PR
-      NEW met1 ( 1811710 1682150 ) M1M2_PR ;
-    - la_data_out[68] ( PIN la_data_out[68] ) ( mprj la_data_out[68] ) + USE SIGNAL
-      + ROUTED met2 ( 1838850 1700 ) ( 1841150 * 0 )
-      NEW met2 ( 1838850 1700 ) ( * 3060 )
-      NEW met2 ( 1835630 3060 ) ( 1838850 * )
-      NEW met2 ( 1743630 1680110 ) ( * 1688780 )
-      NEW met2 ( 1743400 1688780 ) ( 1743630 * )
-      NEW met2 ( 1743400 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1835630 3060 ) ( * 1680110 )
-      NEW met1 ( 1743630 1680110 ) ( 1835630 * )
-      NEW met1 ( 1743630 1680110 ) M1M2_PR
-      NEW met1 ( 1835630 1680110 ) M1M2_PR ;
-    - la_data_out[69] ( PIN la_data_out[69] ) ( mprj la_data_out[69] ) + USE SIGNAL
-      + ROUTED met2 ( 1858630 1700 0 ) ( * 15810 )
-      NEW met1 ( 1831950 15810 ) ( 1858630 * )
-      NEW met2 ( 1749150 1680790 ) ( * 1688780 )
-      NEW met2 ( 1748920 1688780 ) ( 1749150 * )
-      NEW met2 ( 1748920 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1831950 15810 ) ( * 1680790 )
-      NEW met1 ( 1749150 1680790 ) ( 1831950 * )
-      NEW met1 ( 1858630 15810 ) M1M2_PR
-      NEW met1 ( 1831950 15810 ) M1M2_PR
-      NEW met1 ( 1749150 1680790 ) M1M2_PR
-      NEW met1 ( 1831950 1680790 ) M1M2_PR ;
-    - la_data_out[6] ( PIN la_data_out[6] ) ( mprj la_data_out[6] ) + USE SIGNAL
-      + ROUTED met2 ( 739450 1700 ) ( 741750 * 0 )
-      NEW met1 ( 738530 87210 ) ( 1401390 * )
-      NEW met2 ( 738530 82800 ) ( * 87210 )
-      NEW met2 ( 738530 82800 ) ( 739450 * )
-      NEW met2 ( 739450 1700 ) ( * 82800 )
-      NEW met1 ( 1401390 1689290 ) ( 1403850 * )
-      NEW met2 ( 1403850 1689290 ) ( * 1690140 0 )
-      NEW met2 ( 1401390 87210 ) ( * 1689290 )
-      NEW met1 ( 738530 87210 ) M1M2_PR
-      NEW met1 ( 1401390 87210 ) M1M2_PR
-      NEW met1 ( 1401390 1689290 ) M1M2_PR
-      NEW met1 ( 1403850 1689290 ) M1M2_PR ;
-    - la_data_out[70] ( PIN la_data_out[70] ) ( mprj la_data_out[70] ) + USE SIGNAL
-      + ROUTED met2 ( 1754670 1682490 ) ( * 1688780 )
-      NEW met2 ( 1754440 1688780 ) ( 1754670 * )
-      NEW met2 ( 1754440 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1825050 16150 ) ( * 1580100 )
-      NEW met2 ( 1825050 1580100 ) ( 1825510 * )
-      NEW met2 ( 1825510 1580100 ) ( * 1682490 )
-      NEW met2 ( 1876570 1700 0 ) ( * 16150 )
-      NEW met1 ( 1825050 16150 ) ( 1876570 * )
-      NEW met1 ( 1754670 1682490 ) ( 1825510 * )
-      NEW met1 ( 1825050 16150 ) M1M2_PR
-      NEW met1 ( 1754670 1682490 ) M1M2_PR
-      NEW met1 ( 1825510 1682490 ) M1M2_PR
-      NEW met1 ( 1876570 16150 ) M1M2_PR ;
-    - la_data_out[71] ( PIN la_data_out[71] ) ( mprj la_data_out[71] ) + USE SIGNAL
-      + ROUTED met2 ( 1759730 1688780 ) ( 1759890 * )
-      NEW met2 ( 1759890 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1759730 26350 ) ( * 1688780 )
-      NEW met2 ( 1894510 1700 0 ) ( * 26350 )
-      NEW met1 ( 1759730 26350 ) ( 1894510 * )
-      NEW met1 ( 1759730 26350 ) M1M2_PR
-      NEW met1 ( 1894510 26350 ) M1M2_PR ;
-    - la_data_out[72] ( PIN la_data_out[72] ) ( mprj la_data_out[72] ) + USE SIGNAL
-      + ROUTED met2 ( 1760190 26010 ) ( * 1580100 )
-      NEW met2 ( 1760190 1580100 ) ( 1764790 * )
-      NEW met2 ( 1764790 1688780 ) ( 1765410 * )
-      NEW met2 ( 1765410 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1764790 1580100 ) ( * 1688780 )
-      NEW met2 ( 1911990 1700 0 ) ( * 26010 )
-      NEW met1 ( 1760190 26010 ) ( 1911990 * )
-      NEW met1 ( 1760190 26010 ) M1M2_PR
-      NEW met1 ( 1911990 26010 ) M1M2_PR ;
-    - la_data_out[73] ( PIN la_data_out[73] ) ( mprj la_data_out[73] ) + USE SIGNAL
-      + ROUTED met2 ( 1929930 1700 0 ) ( * 25670 )
-      NEW met2 ( 1767090 25670 ) ( * 1580100 )
-      NEW met2 ( 1767090 1580100 ) ( 1770310 * )
-      NEW met2 ( 1770310 1688780 ) ( 1770930 * )
-      NEW met2 ( 1770930 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1770310 1580100 ) ( * 1688780 )
-      NEW met1 ( 1767090 25670 ) ( 1929930 * )
-      NEW met1 ( 1767090 25670 ) M1M2_PR
-      NEW met1 ( 1929930 25670 ) M1M2_PR ;
-    - la_data_out[74] ( PIN la_data_out[74] ) ( mprj la_data_out[74] ) + USE SIGNAL
-      + ROUTED met2 ( 1947410 1700 0 ) ( * 25330 )
-      NEW met1 ( 1773530 25330 ) ( 1947410 * )
-      NEW met2 ( 1773530 25330 ) ( * 1580100 )
-      NEW met2 ( 1773530 1580100 ) ( 1775370 * )
-      NEW met2 ( 1775370 1688780 ) ( 1775990 * )
-      NEW met2 ( 1775990 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1775370 1580100 ) ( * 1688780 )
-      NEW met1 ( 1947410 25330 ) M1M2_PR
-      NEW met1 ( 1773530 25330 ) M1M2_PR ;
-    - la_data_out[75] ( PIN la_data_out[75] ) ( mprj la_data_out[75] ) + USE SIGNAL
-      + ROUTED met2 ( 1965350 1700 0 ) ( * 24990 )
-      NEW met1 ( 1780890 24990 ) ( 1965350 * )
-      NEW met2 ( 1780890 1688780 ) ( 1781510 * )
-      NEW met2 ( 1781510 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1780890 24990 ) ( * 1688780 )
-      NEW met1 ( 1965350 24990 ) M1M2_PR
-      NEW met1 ( 1780890 24990 ) M1M2_PR ;
-    - la_data_out[76] ( PIN la_data_out[76] ) ( mprj la_data_out[76] ) + USE SIGNAL
-      + ROUTED met2 ( 1982830 1700 0 ) ( * 24650 )
-      NEW met1 ( 1780430 24650 ) ( 1982830 * )
-      NEW met1 ( 1780430 1688950 ) ( 1787030 * )
-      NEW met2 ( 1787030 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1780430 24650 ) ( * 1688950 )
-      NEW met1 ( 1780430 24650 ) M1M2_PR
-      NEW met1 ( 1982830 24650 ) M1M2_PR
-      NEW met1 ( 1780430 1688950 ) M1M2_PR
-      NEW met1 ( 1787030 1688950 ) M1M2_PR ;
-    - la_data_out[77] ( PIN la_data_out[77] ) ( mprj la_data_out[77] ) + USE SIGNAL
-      + ROUTED met2 ( 2000770 1700 0 ) ( * 24310 )
-      NEW met1 ( 1788250 24310 ) ( 2000770 * )
-      NEW met2 ( 1788250 24310 ) ( * 1580100 )
-      NEW met2 ( 1788250 1580100 ) ( 1788710 * )
-      NEW met2 ( 1788710 1580100 ) ( * 1676700 )
-      NEW met2 ( 1788710 1676700 ) ( 1789170 * )
-      NEW met2 ( 1789170 1676700 ) ( * 1688780 )
-      NEW met2 ( 1789170 1688780 ) ( 1792550 * )
-      NEW met2 ( 1792550 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1788250 24310 ) M1M2_PR
-      NEW met1 ( 2000770 24310 ) M1M2_PR ;
-    - la_data_out[78] ( PIN la_data_out[78] ) ( mprj la_data_out[78] ) + USE SIGNAL
-      + ROUTED met2 ( 2018250 1700 0 ) ( * 22610 )
-      NEW met1 ( 1794690 22610 ) ( 2018250 * )
-      NEW met1 ( 1794690 1688950 ) ( 1798070 * )
-      NEW met2 ( 1798070 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1794690 22610 ) ( * 1688950 )
-      NEW met1 ( 2018250 22610 ) M1M2_PR
-      NEW met1 ( 1794690 22610 ) M1M2_PR
-      NEW met1 ( 1794690 1688950 ) M1M2_PR
-      NEW met1 ( 1798070 1688950 ) M1M2_PR ;
-    - la_data_out[79] ( PIN la_data_out[79] ) ( mprj la_data_out[79] ) + USE SIGNAL
-      + ROUTED met2 ( 2036190 1700 0 ) ( * 31110 )
-      NEW met1 ( 1802050 31110 ) ( 2036190 * )
-      NEW met2 ( 1802050 1688780 ) ( 1803590 * )
-      NEW met2 ( 1803590 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1802050 31110 ) ( * 1688780 )
-      NEW met1 ( 2036190 31110 ) M1M2_PR
-      NEW met1 ( 1802050 31110 ) M1M2_PR ;
-    - la_data_out[7] ( PIN la_data_out[7] ) ( mprj la_data_out[7] ) + USE SIGNAL
-      + ROUTED met2 ( 759230 1700 0 ) ( * 34500 )
-      NEW met2 ( 759230 34500 ) ( 759690 * )
-      NEW met2 ( 759690 34500 ) ( * 87890 )
-      NEW met1 ( 759690 87890 ) ( 1408290 * )
-      NEW met2 ( 1408290 1688780 ) ( 1409370 * )
-      NEW met2 ( 1409370 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1408290 87890 ) ( * 1688780 )
-      NEW met1 ( 759690 87890 ) M1M2_PR
-      NEW met1 ( 1408290 87890 ) M1M2_PR ;
-    - la_data_out[80] ( PIN la_data_out[80] ) ( mprj la_data_out[80] ) + USE SIGNAL
-      + ROUTED met2 ( 2054130 1700 0 ) ( * 29070 )
-      NEW met1 ( 1808490 29070 ) ( 2054130 * )
-      NEW met2 ( 1808490 1688780 ) ( 1809110 * )
-      NEW met2 ( 1809110 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1808490 29070 ) ( * 1688780 )
-      NEW met1 ( 2054130 29070 ) M1M2_PR
-      NEW met1 ( 1808490 29070 ) M1M2_PR ;
-    - la_data_out[81] ( PIN la_data_out[81] ) ( mprj la_data_out[81] ) + USE SIGNAL
-      + ROUTED met1 ( 1808950 1652570 ) ( 1814470 * )
-      NEW met2 ( 1808950 43690 ) ( * 1652570 )
-      NEW met2 ( 1814470 1688780 ) ( 1814630 * )
-      NEW met2 ( 1814630 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1814470 1652570 ) ( * 1688780 )
-      NEW met1 ( 1808950 43690 ) ( 2071610 * )
-      NEW met2 ( 2071610 1700 0 ) ( * 43690 )
-      NEW met1 ( 1808950 1652570 ) M1M2_PR
-      NEW met1 ( 1814470 1652570 ) M1M2_PR
-      NEW met1 ( 1808950 43690 ) M1M2_PR
-      NEW met1 ( 2071610 43690 ) M1M2_PR ;
-    - la_data_out[82] ( PIN la_data_out[82] ) ( mprj la_data_out[82] ) + USE SIGNAL
-      + ROUTED met2 ( 2087250 1700 ) ( 2089550 * 0 )
-      NEW met2 ( 1815850 64430 ) ( * 1580100 )
-      NEW met2 ( 1815850 1580100 ) ( 1819990 * )
-      NEW met2 ( 1819990 1688780 ) ( 1820150 * )
-      NEW met2 ( 1820150 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1819990 1580100 ) ( * 1688780 )
-      NEW met1 ( 1815850 64430 ) ( 2087250 * )
-      NEW met2 ( 2087250 1700 ) ( * 64430 )
-      NEW met1 ( 1815850 64430 ) M1M2_PR
-      NEW met1 ( 2087250 64430 ) M1M2_PR ;
-    - la_data_out[83] ( PIN la_data_out[83] ) ( mprj la_data_out[83] ) + USE SIGNAL
-      + ROUTED met2 ( 1822290 64770 ) ( * 1580100 )
-      NEW met2 ( 1822290 1580100 ) ( 1824590 * )
-      NEW met2 ( 1824590 1688780 ) ( 1825670 * )
-      NEW met2 ( 1825670 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1824590 1580100 ) ( * 1688780 )
-      NEW met2 ( 2104730 1700 ) ( 2107030 * 0 )
-      NEW met1 ( 1822290 64770 ) ( 2104730 * )
-      NEW met2 ( 2104730 1700 ) ( * 64770 )
-      NEW met1 ( 1822290 64770 ) M1M2_PR
-      NEW met1 ( 2104730 64770 ) M1M2_PR ;
-    - la_data_out[84] ( PIN la_data_out[84] ) ( mprj la_data_out[84] ) + USE SIGNAL
-      + ROUTED met2 ( 2124970 1700 0 ) ( * 16830 )
-      NEW met1 ( 2118530 16830 ) ( 2124970 * )
-      NEW met2 ( 1830110 1688780 ) ( 1831190 * )
-      NEW met2 ( 1831190 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1830110 65110 ) ( * 1688780 )
-      NEW met2 ( 2118530 16830 ) ( * 65110 )
-      NEW met1 ( 1830110 65110 ) ( 2118530 * )
-      NEW met1 ( 2124970 16830 ) M1M2_PR
-      NEW met1 ( 2118530 16830 ) M1M2_PR
-      NEW met1 ( 1830110 65110 ) M1M2_PR
-      NEW met1 ( 2118530 65110 ) M1M2_PR ;
-    - la_data_out[85] ( PIN la_data_out[85] ) ( mprj la_data_out[85] ) + USE SIGNAL
-      + ROUTED met1 ( 1836550 1652230 ) ( * 1653250 )
-      NEW met2 ( 1836550 68850 ) ( * 1652230 )
-      NEW met2 ( 1836320 1688780 ) ( 1836550 * )
-      NEW met2 ( 1836320 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1836550 1653250 ) ( * 1688780 )
-      NEW met2 ( 2142450 1700 0 ) ( * 68850 )
-      NEW met1 ( 1836550 68850 ) ( 2142450 * )
-      NEW met1 ( 1836550 1652230 ) M1M2_PR
-      NEW met1 ( 1836550 1653250 ) M1M2_PR
-      NEW met1 ( 1836550 68850 ) M1M2_PR
-      NEW met1 ( 2142450 68850 ) M1M2_PR ;
-    - la_data_out[86] ( PIN la_data_out[86] ) ( mprj la_data_out[86] ) + USE SIGNAL
-      + ROUTED met2 ( 1837010 71230 ) ( * 1580100 )
-      NEW met2 ( 1837010 1580100 ) ( 1838850 * )
-      NEW met2 ( 1838850 1688780 ) ( 1841770 * )
-      NEW met2 ( 1841770 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1838850 1580100 ) ( * 1688780 )
-      NEW met1 ( 1837010 71230 ) ( 2160390 * )
-      NEW met2 ( 2160390 1700 0 ) ( * 71230 )
-      NEW met1 ( 1837010 71230 ) M1M2_PR
-      NEW met1 ( 2160390 71230 ) M1M2_PR ;
-    - la_data_out[87] ( PIN la_data_out[87] ) ( mprj la_data_out[87] ) + USE SIGNAL
-      + ROUTED met2 ( 1842990 50490 ) ( * 1676700 )
-      NEW met2 ( 1842990 1676700 ) ( 1845290 * )
-      NEW met2 ( 1845290 1676700 ) ( * 1688780 )
-      NEW met2 ( 1845290 1688780 ) ( 1847290 * )
-      NEW met2 ( 1847290 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 2175570 1700 ) ( 2177870 * 0 )
-      NEW met1 ( 1842990 50490 ) ( 2175570 * )
-      NEW met2 ( 2175570 1700 ) ( * 50490 )
-      NEW met1 ( 1842990 50490 ) M1M2_PR
-      NEW met1 ( 2175570 50490 ) M1M2_PR ;
-    - la_data_out[88] ( PIN la_data_out[88] ) ( mprj la_data_out[88] ) + USE SIGNAL
-      + ROUTED met2 ( 1849890 50830 ) ( * 1580100 )
-      NEW met2 ( 1849890 1580100 ) ( 1852190 * )
-      NEW met1 ( 1849890 50830 ) ( 2195810 * )
-      NEW met2 ( 2195810 1700 0 ) ( * 50830 )
-      NEW met2 ( 1852190 1688780 ) ( 1852810 * )
-      NEW met2 ( 1852810 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1852190 1580100 ) ( * 1688780 )
-      NEW met1 ( 1849890 50830 ) M1M2_PR
-      NEW met1 ( 2195810 50830 ) M1M2_PR ;
-    - la_data_out[89] ( PIN la_data_out[89] ) ( mprj la_data_out[89] ) + USE SIGNAL
-      + ROUTED met2 ( 2213290 1700 0 ) ( * 17340 )
-      NEW met2 ( 2210990 17340 ) ( 2213290 * )
-      NEW met2 ( 2210990 17340 ) ( * 51170 )
-      NEW met1 ( 1857250 51170 ) ( 2210990 * )
-      NEW met2 ( 1857250 1688780 ) ( 1858330 * )
-      NEW met2 ( 1858330 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1857250 51170 ) ( * 1688780 )
-      NEW met1 ( 1857250 51170 ) M1M2_PR
-      NEW met1 ( 2210990 51170 ) M1M2_PR ;
-    - la_data_out[8] ( PIN la_data_out[8] ) ( mprj la_data_out[8] ) + USE SIGNAL
-      + ROUTED met2 ( 777170 1700 0 ) ( * 52870 )
-      NEW met2 ( 1414960 1688780 ) ( 1415650 * )
-      NEW met2 ( 1414960 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 777170 52870 ) ( 1415650 * )
-      NEW met2 ( 1415650 52870 ) ( * 1688780 )
-      NEW met1 ( 777170 52870 ) M1M2_PR
-      NEW met1 ( 1415650 52870 ) M1M2_PR ;
-    - la_data_out[90] ( PIN la_data_out[90] ) ( mprj la_data_out[90] ) + USE SIGNAL
-      + ROUTED met2 ( 2228930 1700 ) ( 2231230 * 0 )
-      NEW met2 ( 2228930 1700 ) ( * 54910 )
-      NEW met1 ( 1863230 54910 ) ( 2228930 * )
-      NEW met2 ( 1863230 1688780 ) ( 1863850 * )
-      NEW met2 ( 1863850 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1863230 54910 ) ( * 1688780 )
-      NEW met1 ( 1863230 54910 ) M1M2_PR
-      NEW met1 ( 2228930 54910 ) M1M2_PR ;
-    - la_data_out[91] ( PIN la_data_out[91] ) ( mprj la_data_out[91] ) + USE SIGNAL
-      + ROUTED met1 ( 1863690 1652570 ) ( 1869210 * )
-      NEW met2 ( 2249170 1700 0 ) ( * 16150 )
-      NEW met1 ( 2243190 16150 ) ( 2249170 * )
-      NEW met2 ( 1863690 54570 ) ( * 1652570 )
-      NEW met2 ( 2243190 16150 ) ( * 54570 )
-      NEW met1 ( 1863690 54570 ) ( 2243190 * )
-      NEW met2 ( 1869210 1688780 ) ( 1869370 * )
-      NEW met2 ( 1869370 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1869210 1652570 ) ( * 1688780 )
-      NEW met1 ( 1863690 1652570 ) M1M2_PR
-      NEW met1 ( 1869210 1652570 ) M1M2_PR
-      NEW met1 ( 2249170 16150 ) M1M2_PR
-      NEW met1 ( 2243190 16150 ) M1M2_PR
-      NEW met1 ( 1863690 54570 ) M1M2_PR
-      NEW met1 ( 2243190 54570 ) M1M2_PR ;
-    - la_data_out[92] ( PIN la_data_out[92] ) ( mprj la_data_out[92] ) + USE SIGNAL
-      + ROUTED met1 ( 1870590 54230 ) ( 2266650 * )
-      NEW met2 ( 2266650 1700 0 ) ( * 54230 )
-      NEW met1 ( 1870590 1688950 ) ( 1874890 * )
-      NEW met2 ( 1874890 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1870590 54230 ) ( * 1688950 )
-      NEW met1 ( 1870590 54230 ) M1M2_PR
-      NEW met1 ( 2266650 54230 ) M1M2_PR
-      NEW met1 ( 1870590 1688950 ) M1M2_PR
-      NEW met1 ( 1874890 1688950 ) M1M2_PR ;
-    - la_data_out[93] ( PIN la_data_out[93] ) ( mprj la_data_out[93] ) + USE SIGNAL
-      + ROUTED met1 ( 1877030 53890 ) ( 2284590 * )
-      NEW met2 ( 2284590 1700 0 ) ( * 53890 )
-      NEW met1 ( 1877030 1688950 ) ( 1880410 * )
-      NEW met2 ( 1880410 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1877030 53890 ) ( * 1688950 )
-      NEW met1 ( 1877030 53890 ) M1M2_PR
-      NEW met1 ( 2284590 53890 ) M1M2_PR
-      NEW met1 ( 1877030 1688950 ) M1M2_PR
-      NEW met1 ( 1880410 1688950 ) M1M2_PR ;
-    - la_data_out[94] ( PIN la_data_out[94] ) ( mprj la_data_out[94] ) + USE SIGNAL
-      + ROUTED met1 ( 1883930 1652570 ) ( 1885770 * )
-      NEW met2 ( 2299770 1700 ) ( 2302070 * 0 )
-      NEW met2 ( 1883930 53550 ) ( * 1652570 )
-      NEW met1 ( 1883930 53550 ) ( 2299770 * )
-      NEW met2 ( 2299770 1700 ) ( * 53550 )
-      NEW met2 ( 1885770 1688780 ) ( 1885930 * )
-      NEW met2 ( 1885930 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1885770 1652570 ) ( * 1688780 )
-      NEW met1 ( 1883930 1652570 ) M1M2_PR
-      NEW met1 ( 1885770 1652570 ) M1M2_PR
-      NEW met1 ( 1883930 53550 ) M1M2_PR
-      NEW met1 ( 2299770 53550 ) M1M2_PR ;
-    - la_data_out[95] ( PIN la_data_out[95] ) ( mprj la_data_out[95] ) + USE SIGNAL
-      + ROUTED met2 ( 2320010 1700 0 ) ( * 53210 )
-      NEW met1 ( 1891290 53210 ) ( 2320010 * )
-      NEW met2 ( 1891290 1688780 ) ( 1891450 * )
-      NEW met2 ( 1891450 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1891290 53210 ) ( * 1688780 )
-      NEW met1 ( 2320010 53210 ) M1M2_PR
-      NEW met1 ( 1891290 53210 ) M1M2_PR ;
-    - la_data_out[96] ( PIN la_data_out[96] ) ( mprj la_data_out[96] ) + USE SIGNAL
-      + ROUTED met2 ( 2337490 1700 0 ) ( * 52870 )
-      NEW met1 ( 1891750 1652570 ) ( 1896350 * )
-      NEW met2 ( 1891750 52870 ) ( * 1652570 )
-      NEW met1 ( 1891750 52870 ) ( 2337490 * )
-      NEW met2 ( 1896350 1688780 ) ( 1896510 * )
-      NEW met2 ( 1896510 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1896350 1652570 ) ( * 1688780 )
-      NEW met1 ( 2337490 52870 ) M1M2_PR
-      NEW met1 ( 1891750 1652570 ) M1M2_PR
-      NEW met1 ( 1896350 1652570 ) M1M2_PR
-      NEW met1 ( 1891750 52870 ) M1M2_PR ;
-    - la_data_out[97] ( PIN la_data_out[97] ) ( mprj la_data_out[97] ) + USE SIGNAL
-      + ROUTED met2 ( 2353130 1700 ) ( 2355430 * 0 )
-      NEW met2 ( 1898650 52530 ) ( * 1580100 )
-      NEW met2 ( 1898650 1580100 ) ( 1901870 * )
-      NEW met2 ( 1901870 1688780 ) ( 1902030 * )
-      NEW met2 ( 1902030 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1901870 1580100 ) ( * 1688780 )
-      NEW met1 ( 1898650 52530 ) ( 2353130 * )
-      NEW met2 ( 2353130 1700 ) ( * 52530 )
-      NEW met1 ( 1898650 52530 ) M1M2_PR
-      NEW met1 ( 2353130 52530 ) M1M2_PR ;
-    - la_data_out[98] ( PIN la_data_out[98] ) ( mprj la_data_out[98] ) + USE SIGNAL
-      + ROUTED met2 ( 2370610 1700 ) ( 2372910 * 0 )
-      NEW met2 ( 1905550 52190 ) ( * 1580100 )
-      NEW met2 ( 1905550 1580100 ) ( 1907390 * )
-      NEW met2 ( 1907390 1688780 ) ( 1907550 * )
-      NEW met2 ( 1907550 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1907390 1580100 ) ( * 1688780 )
-      NEW met1 ( 1905550 52190 ) ( 2370610 * )
-      NEW met2 ( 2370610 1700 ) ( * 52190 )
-      NEW met1 ( 1905550 52190 ) M1M2_PR
-      NEW met1 ( 2370610 52190 ) M1M2_PR ;
-    - la_data_out[99] ( PIN la_data_out[99] ) ( mprj la_data_out[99] ) + USE SIGNAL
-      + ROUTED met2 ( 1911990 1688780 ) ( 1913070 * )
-      NEW met2 ( 1913070 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1911990 51850 ) ( * 1688780 )
-      NEW met1 ( 1911990 51850 ) ( 2390850 * )
-      NEW met2 ( 2390850 1700 0 ) ( * 51850 )
-      NEW met1 ( 1911990 51850 ) M1M2_PR
-      NEW met1 ( 2390850 51850 ) M1M2_PR ;
-    - la_data_out[9] ( PIN la_data_out[9] ) ( mprj la_data_out[9] ) + USE SIGNAL
-      + ROUTED met2 ( 794650 1700 0 ) ( * 53210 )
-      NEW met1 ( 1415190 1652230 ) ( 1419790 * )
-      NEW met2 ( 1419790 1688780 ) ( 1419950 * )
-      NEW met2 ( 1419950 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1419790 1652230 ) ( * 1688780 )
-      NEW met1 ( 794650 53210 ) ( 1415190 * )
-      NEW met2 ( 1415190 53210 ) ( * 1652230 )
-      NEW met1 ( 794650 53210 ) M1M2_PR
-      NEW met1 ( 1415190 1652230 ) M1M2_PR
-      NEW met1 ( 1419790 1652230 ) M1M2_PR
-      NEW met1 ( 1415190 53210 ) M1M2_PR ;
-    - la_oenb[0] ( PIN la_oenb[0] ) ( mprj la_oenb[0] ) + USE SIGNAL
-      + ROUTED met1 ( 1367350 1688950 ) ( 1372570 * )
-      NEW met2 ( 1372570 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1367350 52530 ) ( * 1688950 )
-      NEW met2 ( 641010 1700 0 ) ( * 20910 )
-      NEW met1 ( 635030 20910 ) ( 641010 * )
-      NEW met2 ( 635030 20910 ) ( * 52530 )
-      NEW met1 ( 635030 52530 ) ( 1367350 * )
-      NEW met1 ( 1367350 52530 ) M1M2_PR
-      NEW met1 ( 1367350 1688950 ) M1M2_PR
-      NEW met1 ( 1372570 1688950 ) M1M2_PR
-      NEW met1 ( 641010 20910 ) M1M2_PR
-      NEW met1 ( 635030 20910 ) M1M2_PR
-      NEW met1 ( 635030 52530 ) M1M2_PR ;
-    - la_oenb[100] ( PIN la_oenb[100] ) ( mprj la_oenb[100] ) + USE SIGNAL
-      + ROUTED met2 ( 2412010 1700 ) ( 2414310 * 0 )
-      NEW met2 ( 1919350 1688780 ) ( 1920430 * )
-      NEW met2 ( 1920430 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1919350 51510 ) ( * 1688780 )
-      NEW met2 ( 2412010 1700 ) ( * 51510 )
-      NEW met1 ( 1919350 51510 ) ( 2412010 * )
-      NEW met1 ( 1919350 51510 ) M1M2_PR
-      NEW met1 ( 2412010 51510 ) M1M2_PR ;
-    - la_oenb[101] ( PIN la_oenb[101] ) ( mprj la_oenb[101] ) + USE SIGNAL
-      + ROUTED met2 ( 1926020 1688780 ) ( 1926250 * )
-      NEW met2 ( 1926020 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1926250 58310 ) ( * 1688780 )
-      NEW met2 ( 2432250 1700 0 ) ( * 58310 )
-      NEW met1 ( 1926250 58310 ) ( 2432250 * )
-      NEW met1 ( 1926250 58310 ) M1M2_PR
-      NEW met1 ( 2432250 58310 ) M1M2_PR ;
-    - la_oenb[102] ( PIN la_oenb[102] ) ( mprj la_oenb[102] ) + USE SIGNAL
-      + ROUTED met1 ( 1925790 1652570 ) ( 1931310 * )
-      NEW met2 ( 1925790 61370 ) ( * 1652570 )
-      NEW met2 ( 1931310 1688780 ) ( 1931470 * )
-      NEW met2 ( 1931470 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1931310 1652570 ) ( * 1688780 )
-      NEW met2 ( 2449730 1700 0 ) ( * 15980 )
-      NEW met2 ( 2449730 15980 ) ( 2450190 * )
-      NEW met1 ( 1925790 61370 ) ( 2450190 * )
-      NEW met2 ( 2450190 15980 ) ( * 61370 )
-      NEW met1 ( 1925790 1652570 ) M1M2_PR
-      NEW met1 ( 1931310 1652570 ) M1M2_PR
-      NEW met1 ( 1925790 61370 ) M1M2_PR
-      NEW met1 ( 2450190 61370 ) M1M2_PR ;
-    - la_oenb[103] ( PIN la_oenb[103] ) ( mprj la_oenb[103] ) + USE SIGNAL
-      + ROUTED met2 ( 1933610 1688780 ) ( 1936990 * )
-      NEW met2 ( 1936990 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1933610 61030 ) ( * 1688780 )
-      NEW met2 ( 2465370 1700 ) ( 2467670 * 0 )
-      NEW met1 ( 1933610 61030 ) ( 2465370 * )
-      NEW met2 ( 2465370 1700 ) ( * 61030 )
-      NEW met1 ( 1933610 61030 ) M1M2_PR
-      NEW met1 ( 2465370 61030 ) M1M2_PR ;
-    - la_oenb[104] ( PIN la_oenb[104] ) ( mprj la_oenb[104] ) + USE SIGNAL
-      + ROUTED met2 ( 1940050 60350 ) ( * 1580100 )
-      NEW met2 ( 1940050 1580100 ) ( 1941890 * )
-      NEW met2 ( 1941890 1688780 ) ( 1942510 * )
-      NEW met2 ( 1942510 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1941890 1580100 ) ( * 1688780 )
-      NEW met1 ( 1940050 60350 ) ( 2485610 * )
-      NEW met2 ( 2485610 1700 0 ) ( * 60350 )
-      NEW met1 ( 1940050 60350 ) M1M2_PR
-      NEW met1 ( 2485610 60350 ) M1M2_PR ;
-    - la_oenb[105] ( PIN la_oenb[105] ) ( mprj la_oenb[105] ) + USE SIGNAL
-      + ROUTED met2 ( 1947410 1688780 ) ( 1948030 * )
-      NEW met2 ( 1948030 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1947410 60010 ) ( * 1688780 )
-      NEW met2 ( 2503090 1700 0 ) ( * 60010 )
-      NEW met1 ( 1947410 60010 ) ( 2503090 * )
-      NEW met1 ( 1947410 60010 ) M1M2_PR
-      NEW met1 ( 2503090 60010 ) M1M2_PR ;
-    - la_oenb[106] ( PIN la_oenb[106] ) ( mprj la_oenb[106] ) + USE SIGNAL
-      + ROUTED met2 ( 2518730 1700 ) ( 2521030 * 0 )
-      NEW met2 ( 1953620 1688780 ) ( 1953850 * )
-      NEW met2 ( 1953620 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1953850 59670 ) ( * 1688780 )
-      NEW met2 ( 2518730 1700 ) ( * 59670 )
-      NEW met1 ( 1953850 59670 ) ( 2518730 * )
-      NEW met1 ( 1953850 59670 ) M1M2_PR
-      NEW met1 ( 2518730 59670 ) M1M2_PR ;
-    - la_oenb[107] ( PIN la_oenb[107] ) ( mprj la_oenb[107] ) + USE SIGNAL
-      + ROUTED met2 ( 2536210 1700 ) ( 2538510 * 0 )
-      NEW met2 ( 1954310 1688780 ) ( 1958610 * )
-      NEW met2 ( 1958610 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1954310 71570 ) ( * 1688780 )
-      NEW met2 ( 2536210 1700 ) ( * 71570 )
-      NEW met1 ( 1954310 71570 ) ( 2536210 * )
-      NEW met1 ( 1954310 71570 ) M1M2_PR
-      NEW met1 ( 2536210 71570 ) M1M2_PR ;
-    - la_oenb[108] ( PIN la_oenb[108] ) ( mprj la_oenb[108] ) + USE SIGNAL
-      + ROUTED met2 ( 1961210 59330 ) ( * 1580100 )
-      NEW met2 ( 1961210 1580100 ) ( 1963510 * )
-      NEW met2 ( 1963510 1688780 ) ( 1964130 * )
-      NEW met2 ( 1964130 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1963510 1580100 ) ( * 1688780 )
-      NEW met1 ( 1961210 59330 ) ( 2556450 * )
-      NEW met2 ( 2556450 1700 0 ) ( * 59330 )
-      NEW met1 ( 1961210 59330 ) M1M2_PR
-      NEW met1 ( 2556450 59330 ) M1M2_PR ;
-    - la_oenb[109] ( PIN la_oenb[109] ) ( mprj la_oenb[109] ) + USE SIGNAL
-      + ROUTED met2 ( 1968110 1688780 ) ( 1969650 * )
-      NEW met2 ( 1969650 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1968110 71910 ) ( * 1688780 )
-      NEW met1 ( 1968110 71910 ) ( 2573930 * )
-      NEW met2 ( 2573930 1700 0 ) ( * 71910 )
-      NEW met1 ( 1968110 71910 ) M1M2_PR
-      NEW met1 ( 2573930 71910 ) M1M2_PR ;
-    - la_oenb[10] ( PIN la_oenb[10] ) ( mprj la_oenb[10] ) + USE SIGNAL
-      + ROUTED met2 ( 818570 1700 0 ) ( * 17340 )
-      NEW met2 ( 817190 17340 ) ( 818570 * )
-      NEW met1 ( 1422090 1652570 ) ( 1427150 * )
-      NEW met2 ( 817190 17340 ) ( * 53550 )
-      NEW met2 ( 1427150 1688780 ) ( 1427310 * )
-      NEW met2 ( 1427310 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1427150 1652570 ) ( * 1688780 )
-      NEW met1 ( 817190 53550 ) ( 1422090 * )
-      NEW met2 ( 1422090 53550 ) ( * 1652570 )
-      NEW met1 ( 1422090 1652570 ) M1M2_PR
-      NEW met1 ( 1427150 1652570 ) M1M2_PR
-      NEW met1 ( 817190 53550 ) M1M2_PR
-      NEW met1 ( 1422090 53550 ) M1M2_PR ;
-    - la_oenb[110] ( PIN la_oenb[110] ) ( mprj la_oenb[110] ) + USE SIGNAL
-      + ROUTED met2 ( 2589570 1700 ) ( 2591870 * 0 )
-      NEW met2 ( 1974550 1688780 ) ( 1975170 * )
-      NEW met2 ( 1975170 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1974550 75650 ) ( * 1688780 )
-      NEW met1 ( 1974550 75650 ) ( 2589570 * )
-      NEW met2 ( 2589570 1700 ) ( * 75650 )
-      NEW met1 ( 1974550 75650 ) M1M2_PR
-      NEW met1 ( 2589570 75650 ) M1M2_PR ;
-    - la_oenb[111] ( PIN la_oenb[111] ) ( mprj la_oenb[111] ) + USE SIGNAL
-      + ROUTED met2 ( 2608430 1700 ) ( 2609350 * 0 )
-      NEW met2 ( 2608430 1700 ) ( * 75310 )
-      NEW met2 ( 1981450 1652740 ) ( 1981910 * )
-      NEW met2 ( 1981910 75310 ) ( * 1652740 )
-      NEW met2 ( 1980760 1688780 ) ( 1981450 * )
-      NEW met2 ( 1980760 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1981450 1652740 ) ( * 1688780 )
-      NEW met1 ( 1981910 75310 ) ( 2608430 * )
-      NEW met1 ( 2608430 75310 ) M1M2_PR
-      NEW met1 ( 1981910 75310 ) M1M2_PR ;
-    - la_oenb[112] ( PIN la_oenb[112] ) ( mprj la_oenb[112] ) + USE SIGNAL
-      + ROUTED met2 ( 2627290 1700 0 ) ( * 74970 )
-      NEW met1 ( 1981450 1652230 ) ( 1986050 * )
-      NEW met2 ( 1981450 74970 ) ( * 1652230 )
-      NEW met2 ( 1986050 1688780 ) ( 1986210 * )
-      NEW met2 ( 1986210 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1986050 1652230 ) ( * 1688780 )
-      NEW met1 ( 1981450 74970 ) ( 2627290 * )
-      NEW met1 ( 2627290 74970 ) M1M2_PR
-      NEW met1 ( 1981450 1652230 ) M1M2_PR
-      NEW met1 ( 1986050 1652230 ) M1M2_PR
-      NEW met1 ( 1981450 74970 ) M1M2_PR ;
-    - la_oenb[113] ( PIN la_oenb[113] ) ( mprj la_oenb[113] ) + USE SIGNAL
-      + ROUTED met2 ( 2642930 1700 ) ( 2645230 * 0 )
-      NEW met2 ( 1988810 74630 ) ( * 1580100 )
-      NEW met2 ( 1988810 1580100 ) ( 1990190 * )
-      NEW met2 ( 1990190 1688780 ) ( 1991730 * )
-      NEW met2 ( 1991730 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1990190 1580100 ) ( * 1688780 )
-      NEW met1 ( 1988810 74630 ) ( 2642930 * )
-      NEW met2 ( 2642930 1700 ) ( * 74630 )
-      NEW met1 ( 1988810 74630 ) M1M2_PR
-      NEW met1 ( 2642930 74630 ) M1M2_PR ;
-    - la_oenb[114] ( PIN la_oenb[114] ) ( mprj la_oenb[114] ) + USE SIGNAL
-      + ROUTED met2 ( 2660410 1700 ) ( 2662710 * 0 )
-      NEW met2 ( 1995710 1688780 ) ( 1997250 * )
-      NEW met2 ( 1997250 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1995710 74290 ) ( * 1688780 )
-      NEW met1 ( 1995710 74290 ) ( 2660410 * )
-      NEW met2 ( 2660410 1700 ) ( * 74290 )
-      NEW met1 ( 1995710 74290 ) M1M2_PR
-      NEW met1 ( 2660410 74290 ) M1M2_PR ;
-    - la_oenb[115] ( PIN la_oenb[115] ) ( mprj la_oenb[115] ) + USE SIGNAL
-      + ROUTED met2 ( 2002150 1688780 ) ( 2002770 * )
-      NEW met2 ( 2002770 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 2002150 73950 ) ( * 1688780 )
-      NEW met1 ( 2002150 73950 ) ( 2680650 * )
-      NEW met2 ( 2680650 1700 0 ) ( * 73950 )
-      NEW met1 ( 2002150 73950 ) M1M2_PR
-      NEW met1 ( 2680650 73950 ) M1M2_PR ;
-    - la_oenb[116] ( PIN la_oenb[116] ) ( mprj la_oenb[116] ) + USE SIGNAL
-      + ROUTED met2 ( 2698130 1700 0 ) ( * 73610 )
-      NEW met2 ( 2008360 1688780 ) ( 2009050 * )
-      NEW met2 ( 2008360 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 2009050 73610 ) ( * 1688780 )
-      NEW met1 ( 2009050 73610 ) ( 2698130 * )
-      NEW met1 ( 2698130 73610 ) M1M2_PR
-      NEW met1 ( 2009050 73610 ) M1M2_PR ;
-    - la_oenb[117] ( PIN la_oenb[117] ) ( mprj la_oenb[117] ) + USE SIGNAL
-      + ROUTED met2 ( 2713770 1700 ) ( 2716070 * 0 )
-      NEW met2 ( 2713770 1700 ) ( * 73270 )
-      NEW met2 ( 2009510 1688780 ) ( 2013810 * )
-      NEW met2 ( 2013810 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 2009510 73270 ) ( * 1688780 )
-      NEW met1 ( 2009510 73270 ) ( 2713770 * )
-      NEW met1 ( 2713770 73270 ) M1M2_PR
-      NEW met1 ( 2009510 73270 ) M1M2_PR ;
-    - la_oenb[118] ( PIN la_oenb[118] ) ( mprj la_oenb[118] ) + USE SIGNAL
-      + ROUTED met2 ( 2732630 1700 ) ( 2733550 * 0 )
-      NEW met2 ( 2016410 1688780 ) ( 2018870 * )
-      NEW met2 ( 2018870 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 2016410 72930 ) ( * 1688780 )
-      NEW met2 ( 2732630 1700 ) ( * 72930 )
-      NEW met1 ( 2016410 72930 ) ( 2732630 * )
-      NEW met1 ( 2016410 72930 ) M1M2_PR
-      NEW met1 ( 2732630 72930 ) M1M2_PR ;
-    - la_oenb[119] ( PIN la_oenb[119] ) ( mprj la_oenb[119] ) + USE SIGNAL
-      + ROUTED met1 ( 2021930 1689290 ) ( 2024390 * )
-      NEW met2 ( 2024390 1689290 ) ( * 1690140 0 )
-      NEW met2 ( 2021930 18190 ) ( * 1689290 )
-      NEW met2 ( 2751490 1700 0 ) ( * 18190 )
-      NEW met1 ( 2021930 18190 ) ( 2751490 * )
-      NEW met1 ( 2021930 18190 ) M1M2_PR
-      NEW met1 ( 2021930 1689290 ) M1M2_PR
-      NEW met1 ( 2024390 1689290 ) M1M2_PR
-      NEW met1 ( 2751490 18190 ) M1M2_PR ;
-    - la_oenb[11] ( PIN la_oenb[11] ) ( mprj la_oenb[11] ) + USE SIGNAL
-      + ROUTED met2 ( 836050 1700 0 ) ( * 53890 )
-      NEW met1 ( 1428990 1688270 ) ( 1432830 * )
-      NEW met1 ( 1432830 1688270 ) ( * 1689290 )
-      NEW met2 ( 1432830 1689290 ) ( * 1690140 0 )
-      NEW met1 ( 836050 53890 ) ( 1428990 * )
-      NEW met2 ( 1428990 53890 ) ( * 1688270 )
-      NEW met1 ( 836050 53890 ) M1M2_PR
-      NEW met1 ( 1428990 1688270 ) M1M2_PR
-      NEW met1 ( 1432830 1689290 ) M1M2_PR
-      NEW met1 ( 1428990 53890 ) M1M2_PR ;
-    - la_oenb[120] ( PIN la_oenb[120] ) ( mprj la_oenb[120] ) + USE SIGNAL
-      + ROUTED met2 ( 2029980 1688780 ) ( 2030210 * )
-      NEW met2 ( 2029980 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 2030210 72590 ) ( * 1688780 )
-      NEW met1 ( 2030210 72590 ) ( 2768970 * )
-      NEW met2 ( 2768970 1700 0 ) ( * 72590 )
-      NEW met1 ( 2030210 72590 ) M1M2_PR
-      NEW met1 ( 2768970 72590 ) M1M2_PR ;
-    - la_oenb[121] ( PIN la_oenb[121] ) ( mprj la_oenb[121] ) + USE SIGNAL
-      + ROUTED met1 ( 2028830 1689290 ) ( 2035430 * )
-      NEW met2 ( 2035430 1689290 ) ( * 1690140 0 )
-      NEW met2 ( 2028830 17510 ) ( * 1689290 )
-      NEW met2 ( 2786910 1700 0 ) ( * 17510 )
-      NEW met1 ( 2028830 17510 ) ( 2786910 * )
-      NEW met1 ( 2028830 17510 ) M1M2_PR
-      NEW met1 ( 2028830 1689290 ) M1M2_PR
-      NEW met1 ( 2035430 1689290 ) M1M2_PR
-      NEW met1 ( 2786910 17510 ) M1M2_PR ;
-    - la_oenb[122] ( PIN la_oenb[122] ) ( mprj la_oenb[122] ) + USE SIGNAL
-      + ROUTED met2 ( 2804390 1700 0 ) ( * 18870 )
-      NEW met2 ( 2041250 1679430 ) ( * 1688780 )
-      NEW met2 ( 2041020 1688780 ) ( 2041250 * )
-      NEW met2 ( 2041020 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 2094610 18870 ) ( 2804390 * )
-      NEW met1 ( 2041250 1679430 ) ( 2094610 * )
-      NEW met2 ( 2094610 18870 ) ( * 1679430 )
-      NEW met1 ( 2804390 18870 ) M1M2_PR
-      NEW met1 ( 2041250 1679430 ) M1M2_PR
-      NEW met1 ( 2094610 18870 ) M1M2_PR
-      NEW met1 ( 2094610 1679430 ) M1M2_PR ;
-    - la_oenb[123] ( PIN la_oenb[123] ) ( mprj la_oenb[123] ) + USE SIGNAL
-      + ROUTED met2 ( 2044010 1688780 ) ( 2046470 * )
-      NEW met2 ( 2046470 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 2044010 72250 ) ( * 1688780 )
-      NEW met2 ( 2822330 1700 0 ) ( * 72250 )
-      NEW met1 ( 2044010 72250 ) ( 2822330 * )
-      NEW met1 ( 2044010 72250 ) M1M2_PR
-      NEW met1 ( 2822330 72250 ) M1M2_PR ;
-    - la_oenb[124] ( PIN la_oenb[124] ) ( mprj la_oenb[124] ) + USE SIGNAL
-      + ROUTED met2 ( 2052290 1679090 ) ( * 1688780 )
-      NEW met2 ( 2052060 1688780 ) ( 2052290 * )
-      NEW met2 ( 2052060 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 2094150 20570 ) ( 2095530 * )
-      NEW met2 ( 2095530 17850 ) ( * 20570 )
-      NEW met2 ( 2840270 1700 0 ) ( * 17850 )
-      NEW met1 ( 2095530 17850 ) ( 2840270 * )
-      NEW met1 ( 2052290 1679090 ) ( 2094150 * )
-      NEW met2 ( 2094150 20570 ) ( * 1679090 )
-      NEW met1 ( 2052290 1679090 ) M1M2_PR
-      NEW met1 ( 2094150 20570 ) M1M2_PR
-      NEW met1 ( 2095530 20570 ) M1M2_PR
-      NEW met1 ( 2095530 17850 ) M1M2_PR
-      NEW met1 ( 2840270 17850 ) M1M2_PR
-      NEW met1 ( 2094150 1679090 ) M1M2_PR ;
-    - la_oenb[125] ( PIN la_oenb[125] ) ( mprj la_oenb[125] ) + USE SIGNAL
-      + ROUTED met2 ( 2056430 1688780 ) ( 2057510 * )
-      NEW met2 ( 2057510 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 2056430 17170 ) ( * 1688780 )
-      NEW met2 ( 2857750 1700 0 ) ( * 17170 )
-      NEW met1 ( 2056430 17170 ) ( 2857750 * )
-      NEW met1 ( 2056430 17170 ) M1M2_PR
-      NEW met1 ( 2857750 17170 ) M1M2_PR ;
-    - la_oenb[126] ( PIN la_oenb[126] ) ( mprj la_oenb[126] ) + USE SIGNAL
-      + ROUTED met2 ( 2062870 1679770 ) ( * 1688780 )
-      NEW met2 ( 2062870 1688780 ) ( 2063030 * )
-      NEW met2 ( 2063030 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 2156250 18530 ) ( * 1679770 )
-      NEW met2 ( 2875690 1700 0 ) ( * 18530 )
-      NEW met1 ( 2156250 18530 ) ( 2875690 * )
-      NEW met1 ( 2062870 1679770 ) ( 2156250 * )
-      NEW met1 ( 2156250 18530 ) M1M2_PR
-      NEW met1 ( 2062870 1679770 ) M1M2_PR
-      NEW met1 ( 2156250 1679770 ) M1M2_PR
-      NEW met1 ( 2875690 18530 ) M1M2_PR ;
-    - la_oenb[127] ( PIN la_oenb[127] ) ( mprj la_oenb[127] ) + USE SIGNAL
-      + ROUTED met2 ( 2893170 1700 0 ) ( * 79390 )
-      NEW met2 ( 2064250 79390 ) ( * 1580100 )
-      NEW met2 ( 2064250 1580100 ) ( 2068390 * )
-      NEW met2 ( 2068390 1688780 ) ( 2068550 * )
-      NEW met2 ( 2068550 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 2068390 1580100 ) ( * 1688780 )
-      NEW met1 ( 2064250 79390 ) ( 2893170 * )
-      NEW met1 ( 2893170 79390 ) M1M2_PR
-      NEW met1 ( 2064250 79390 ) M1M2_PR ;
-    - la_oenb[12] ( PIN la_oenb[12] ) ( mprj la_oenb[12] ) + USE SIGNAL
-      + ROUTED met1 ( 1436350 1688270 ) ( * 1689290 )
-      NEW met1 ( 1436350 1689290 ) ( 1438350 * )
-      NEW met2 ( 1438350 1689290 ) ( * 1690140 0 )
-      NEW met2 ( 851690 1700 ) ( 853990 * 0 )
-      NEW met2 ( 851690 1700 ) ( * 54230 )
-      NEW met1 ( 851690 54230 ) ( 1436350 * )
-      NEW met2 ( 1436350 54230 ) ( * 1688270 )
-      NEW met1 ( 1436350 1688270 ) M1M2_PR
-      NEW met1 ( 1438350 1689290 ) M1M2_PR
-      NEW met1 ( 851690 54230 ) M1M2_PR
-      NEW met1 ( 1436350 54230 ) M1M2_PR ;
-    - la_oenb[13] ( PIN la_oenb[13] ) ( mprj la_oenb[13] ) + USE SIGNAL
-      + ROUTED met2 ( 869630 1700 ) ( 871470 * 0 )
-      NEW met2 ( 869630 1700 ) ( * 54570 )
-      NEW met2 ( 1442790 1688780 ) ( 1443870 * )
-      NEW met2 ( 1443870 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 869630 54570 ) ( 1442790 * )
-      NEW met2 ( 1442790 54570 ) ( * 1688780 )
-      NEW met1 ( 869630 54570 ) M1M2_PR
-      NEW met1 ( 1442790 54570 ) M1M2_PR ;
-    - la_oenb[14] ( PIN la_oenb[14] ) ( mprj la_oenb[14] ) + USE SIGNAL
-      + ROUTED met2 ( 889410 1700 0 ) ( * 20910 )
-      NEW met1 ( 883430 20910 ) ( 889410 * )
-      NEW met2 ( 883430 20910 ) ( * 54910 )
-      NEW met2 ( 1449460 1688780 ) ( 1449690 * )
-      NEW met2 ( 1449460 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 883430 54910 ) ( 1449690 * )
-      NEW met2 ( 1449690 54910 ) ( * 1688780 )
-      NEW met1 ( 889410 20910 ) M1M2_PR
-      NEW met1 ( 883430 20910 ) M1M2_PR
-      NEW met1 ( 883430 54910 ) M1M2_PR
-      NEW met1 ( 1449690 54910 ) M1M2_PR ;
-    - la_oenb[15] ( PIN la_oenb[15] ) ( mprj la_oenb[15] ) + USE SIGNAL
-      + ROUTED met1 ( 1450150 1688950 ) ( 1454910 * )
-      NEW met2 ( 1454910 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 905050 1700 ) ( 907350 * 0 )
-      NEW met2 ( 905050 1700 ) ( * 51170 )
-      NEW met1 ( 905050 51170 ) ( 1450150 * )
-      NEW met2 ( 1450150 51170 ) ( * 1688950 )
-      NEW met1 ( 1450150 1688950 ) M1M2_PR
-      NEW met1 ( 1454910 1688950 ) M1M2_PR
-      NEW met1 ( 905050 51170 ) M1M2_PR
-      NEW met1 ( 1450150 51170 ) M1M2_PR ;
-    - la_oenb[16] ( PIN la_oenb[16] ) ( mprj la_oenb[16] ) + USE SIGNAL
-      + ROUTED met2 ( 1457970 82800 ) ( 1458890 * )
-      NEW met2 ( 1457970 82800 ) ( * 1580100 )
-      NEW met2 ( 1457970 1580100 ) ( 1459810 * )
-      NEW met2 ( 1459810 1688780 ) ( 1460430 * )
-      NEW met2 ( 1460430 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1459810 1580100 ) ( * 1688780 )
-      NEW met2 ( 924830 1700 0 ) ( * 50830 )
-      NEW met1 ( 924830 50830 ) ( 1458890 * )
-      NEW met2 ( 1458890 50830 ) ( * 82800 )
-      NEW met1 ( 924830 50830 ) M1M2_PR
-      NEW met1 ( 1458890 50830 ) M1M2_PR ;
-    - la_oenb[17] ( PIN la_oenb[17] ) ( mprj la_oenb[17] ) + USE SIGNAL
-      + ROUTED met2 ( 1464410 1688780 ) ( 1465950 * )
-      NEW met2 ( 1465950 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1464410 50490 ) ( * 1688780 )
-      NEW met2 ( 942770 1700 0 ) ( * 17340 )
-      NEW met2 ( 941390 17340 ) ( 942770 * )
-      NEW met2 ( 941390 17340 ) ( * 50490 )
-      NEW met1 ( 941390 50490 ) ( 1464410 * )
-      NEW met1 ( 1464410 50490 ) M1M2_PR
-      NEW met1 ( 941390 50490 ) M1M2_PR ;
-    - la_oenb[18] ( PIN la_oenb[18] ) ( mprj la_oenb[18] ) + USE SIGNAL
-      + ROUTED met2 ( 959330 82800 ) ( * 88570 )
-      NEW met2 ( 959330 82800 ) ( 960250 * )
-      NEW met2 ( 960250 1700 0 ) ( * 82800 )
-      NEW met2 ( 1471310 1688780 ) ( 1471470 * )
-      NEW met2 ( 1471470 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1471310 88570 ) ( * 1688780 )
-      NEW met1 ( 959330 88570 ) ( 1471310 * )
-      NEW met1 ( 959330 88570 ) M1M2_PR
-      NEW met1 ( 1471310 88570 ) M1M2_PR ;
-    - la_oenb[19] ( PIN la_oenb[19] ) ( mprj la_oenb[19] ) + USE SIGNAL
-      + ROUTED met2 ( 975890 1700 ) ( 978190 * 0 )
-      NEW met2 ( 973130 82800 ) ( * 88910 )
-      NEW met2 ( 973130 82800 ) ( 975890 * )
-      NEW met2 ( 975890 1700 ) ( * 82800 )
-      NEW met1 ( 1470850 1689290 ) ( 1476530 * )
-      NEW met2 ( 1476530 1689290 ) ( * 1690140 0 )
-      NEW met2 ( 1470850 88910 ) ( * 1689290 )
-      NEW met1 ( 973130 88910 ) ( 1470850 * )
-      NEW met1 ( 973130 88910 ) M1M2_PR
-      NEW met1 ( 1470850 88910 ) M1M2_PR
-      NEW met1 ( 1470850 1689290 ) M1M2_PR
-      NEW met1 ( 1476530 1689290 ) M1M2_PR ;
-    - la_oenb[1] ( PIN la_oenb[1] ) ( mprj la_oenb[1] ) + USE SIGNAL
-      + ROUTED met2 ( 1374710 1688780 ) ( 1378090 * )
-      NEW met2 ( 1378090 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1374710 86020 ) ( * 1688780 )
-      NEW met2 ( 656650 1700 ) ( 658950 * 0 )
-      NEW met3 ( 655730 86020 ) ( 1374710 * )
-      NEW met2 ( 655730 82800 ) ( * 86020 )
-      NEW met2 ( 655730 82800 ) ( 656650 * )
-      NEW met2 ( 656650 1700 ) ( * 82800 )
-      NEW met2 ( 1374710 86020 ) M2M3_PR
-      NEW met2 ( 655730 86020 ) M2M3_PR ;
-    - la_oenb[20] ( PIN la_oenb[20] ) ( mprj la_oenb[20] ) + USE SIGNAL
-      + ROUTED met2 ( 993830 1700 ) ( 995670 * 0 )
-      NEW met2 ( 993830 1700 ) ( * 92310 )
-      NEW met2 ( 1477750 92310 ) ( * 1580100 )
-      NEW met2 ( 1477750 1580100 ) ( 1481890 * )
-      NEW met2 ( 1481890 1688780 ) ( 1482050 * )
-      NEW met2 ( 1482050 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1481890 1580100 ) ( * 1688780 )
-      NEW met1 ( 993830 92310 ) ( 1477750 * )
-      NEW met1 ( 993830 92310 ) M1M2_PR
-      NEW met1 ( 1477750 92310 ) M1M2_PR ;
-    - la_oenb[21] ( PIN la_oenb[21] ) ( mprj la_oenb[21] ) + USE SIGNAL
-      + ROUTED met1 ( 1007630 91970 ) ( 1485110 * )
-      NEW met1 ( 1007630 58310 ) ( 1013610 * )
-      NEW met2 ( 1007630 58310 ) ( * 91970 )
-      NEW met2 ( 1013610 1700 0 ) ( * 58310 )
-      NEW met2 ( 1485110 91970 ) ( * 1580100 )
-      NEW met2 ( 1485110 1580100 ) ( 1486950 * )
-      NEW met2 ( 1486950 1688780 ) ( 1487570 * )
-      NEW met2 ( 1487570 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1486950 1580100 ) ( * 1688780 )
-      NEW met1 ( 1007630 91970 ) M1M2_PR
-      NEW met1 ( 1485110 91970 ) M1M2_PR
-      NEW met1 ( 1007630 58310 ) M1M2_PR
-      NEW met1 ( 1013610 58310 ) M1M2_PR ;
-    - la_oenb[22] ( PIN la_oenb[22] ) ( mprj la_oenb[22] ) + USE SIGNAL
-      + ROUTED met1 ( 1490630 1651890 ) ( * 1653930 )
-      NEW met1 ( 1490630 1651890 ) ( 1491090 * )
-      NEW met2 ( 1031090 1700 0 ) ( * 60350 )
-      NEW met2 ( 1491090 60350 ) ( * 1651890 )
-      NEW met1 ( 1490630 1689290 ) ( 1493090 * )
-      NEW met2 ( 1493090 1689290 ) ( * 1690140 0 )
-      NEW met2 ( 1490630 1653930 ) ( * 1689290 )
-      NEW met1 ( 1031090 60350 ) ( 1491090 * )
-      NEW met1 ( 1490630 1653930 ) M1M2_PR
-      NEW met1 ( 1491090 1651890 ) M1M2_PR
-      NEW met1 ( 1031090 60350 ) M1M2_PR
-      NEW met1 ( 1491090 60350 ) M1M2_PR
-      NEW met1 ( 1490630 1689290 ) M1M2_PR
-      NEW met1 ( 1493090 1689290 ) M1M2_PR ;
-    - la_oenb[23] ( PIN la_oenb[23] ) ( mprj la_oenb[23] ) + USE SIGNAL
-      + ROUTED met2 ( 1049030 1700 0 ) ( * 60690 )
-      NEW met2 ( 1498450 1688780 ) ( 1498610 * )
-      NEW met2 ( 1498610 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1498450 60690 ) ( * 1688780 )
-      NEW met1 ( 1049030 60690 ) ( 1498450 * )
-      NEW met1 ( 1049030 60690 ) M1M2_PR
-      NEW met1 ( 1498450 60690 ) M1M2_PR ;
-    - la_oenb[24] ( PIN la_oenb[24] ) ( mprj la_oenb[24] ) + USE SIGNAL
-      + ROUTED met2 ( 1066970 1700 0 ) ( * 61030 )
-      NEW met1 ( 1497990 1652570 ) ( 1503970 * )
-      NEW met2 ( 1497990 61030 ) ( * 1652570 )
-      NEW met2 ( 1503970 1688780 ) ( 1504130 * )
-      NEW met2 ( 1504130 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1503970 1652570 ) ( * 1688780 )
-      NEW met1 ( 1066970 61030 ) ( 1497990 * )
-      NEW met1 ( 1066970 61030 ) M1M2_PR
-      NEW met1 ( 1497990 1652570 ) M1M2_PR
-      NEW met1 ( 1503970 1652570 ) M1M2_PR
-      NEW met1 ( 1497990 61030 ) M1M2_PR ;
-    - la_oenb[25] ( PIN la_oenb[25] ) ( mprj la_oenb[25] ) + USE SIGNAL
-      + ROUTED met2 ( 1084450 1700 0 ) ( * 61370 )
-      NEW met1 ( 1504890 1688950 ) ( 1509650 * )
-      NEW met2 ( 1509650 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1504890 61370 ) ( * 1688950 )
-      NEW met1 ( 1084450 61370 ) ( 1504890 * )
-      NEW met1 ( 1084450 61370 ) M1M2_PR
-      NEW met1 ( 1504890 61370 ) M1M2_PR
-      NEW met1 ( 1504890 1688950 ) M1M2_PR
-      NEW met1 ( 1509650 1688950 ) M1M2_PR ;
-    - la_oenb[26] ( PIN la_oenb[26] ) ( mprj la_oenb[26] ) + USE SIGNAL
-      + ROUTED met2 ( 1100090 1700 ) ( 1102390 * 0 )
-      NEW met2 ( 1100090 1700 ) ( * 61710 )
-      NEW met2 ( 1512250 61710 ) ( * 1676700 )
-      NEW met2 ( 1512250 1676700 ) ( 1515010 * )
-      NEW met2 ( 1515010 1676700 ) ( * 1688780 )
-      NEW met2 ( 1515010 1688780 ) ( 1515170 * )
-      NEW met2 ( 1515170 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1100090 61710 ) ( 1512250 * )
-      NEW met1 ( 1100090 61710 ) M1M2_PR
-      NEW met1 ( 1512250 61710 ) M1M2_PR ;
-    - la_oenb[27] ( PIN la_oenb[27] ) ( mprj la_oenb[27] ) + USE SIGNAL
-      + ROUTED met2 ( 1118030 1700 ) ( 1119870 * 0 )
-      NEW met2 ( 1118030 1700 ) ( * 62050 )
-      NEW met2 ( 1519150 1688780 ) ( 1520690 * )
-      NEW met2 ( 1520690 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1519150 62050 ) ( * 1688780 )
-      NEW met1 ( 1118030 62050 ) ( 1519150 * )
-      NEW met1 ( 1118030 62050 ) M1M2_PR
-      NEW met1 ( 1519150 62050 ) M1M2_PR ;
-    - la_oenb[28] ( PIN la_oenb[28] ) ( mprj la_oenb[28] ) + USE SIGNAL
-      + ROUTED met2 ( 1137810 1700 0 ) ( * 20910 )
-      NEW met1 ( 1131830 20910 ) ( 1137810 * )
-      NEW met2 ( 1131830 20910 ) ( * 58310 )
-      NEW met2 ( 1525590 1688780 ) ( 1526210 * )
-      NEW met2 ( 1526210 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1525590 58310 ) ( * 1688780 )
-      NEW met1 ( 1131830 58310 ) ( 1525590 * )
-      NEW met1 ( 1137810 20910 ) M1M2_PR
-      NEW met1 ( 1131830 20910 ) M1M2_PR
-      NEW met1 ( 1131830 58310 ) M1M2_PR
-      NEW met1 ( 1525590 58310 ) M1M2_PR ;
-    - la_oenb[29] ( PIN la_oenb[29] ) ( mprj la_oenb[29] ) + USE SIGNAL
-      + ROUTED met2 ( 1155290 1700 0 ) ( * 57970 )
-      NEW met1 ( 1526050 1652570 ) ( 1531570 * )
-      NEW met2 ( 1526050 57970 ) ( * 1652570 )
-      NEW met2 ( 1531570 1688780 ) ( 1531730 * )
-      NEW met2 ( 1531730 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1531570 1652570 ) ( * 1688780 )
-      NEW met1 ( 1155290 57970 ) ( 1526050 * )
-      NEW met1 ( 1155290 57970 ) M1M2_PR
-      NEW met1 ( 1526050 1652570 ) M1M2_PR
-      NEW met1 ( 1531570 1652570 ) M1M2_PR
-      NEW met1 ( 1526050 57970 ) M1M2_PR ;
-    - la_oenb[2] ( PIN la_oenb[2] ) ( mprj la_oenb[2] ) + USE SIGNAL
-      + ROUTED met2 ( 676430 1700 0 ) ( * 59670 )
-      NEW met2 ( 1381610 59670 ) ( * 1580100 )
-      NEW met2 ( 1381610 1580100 ) ( 1382990 * )
-      NEW met2 ( 1382990 1688780 ) ( 1383610 * )
-      NEW met2 ( 1383610 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1382990 1580100 ) ( * 1688780 )
-      NEW met1 ( 676430 59670 ) ( 1381610 * )
-      NEW met1 ( 676430 59670 ) M1M2_PR
-      NEW met1 ( 1381610 59670 ) M1M2_PR ;
-    - la_oenb[30] ( PIN la_oenb[30] ) ( mprj la_oenb[30] ) + USE SIGNAL
-      + ROUTED met2 ( 1173230 1700 0 ) ( * 17340 )
-      NEW met2 ( 1173230 17340 ) ( 1174610 * )
-      NEW met1 ( 1533410 1652570 ) ( 1536630 * )
-      NEW met2 ( 1174610 17340 ) ( * 57630 )
-      NEW met2 ( 1533410 57630 ) ( * 1652570 )
-      NEW met2 ( 1536630 1688780 ) ( 1536790 * )
-      NEW met2 ( 1536790 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1536630 1652570 ) ( * 1688780 )
-      NEW met1 ( 1174610 57630 ) ( 1533410 * )
-      NEW met1 ( 1533410 1652570 ) M1M2_PR
-      NEW met1 ( 1536630 1652570 ) M1M2_PR
-      NEW met1 ( 1174610 57630 ) M1M2_PR
-      NEW met1 ( 1533410 57630 ) M1M2_PR ;
-    - la_oenb[31] ( PIN la_oenb[31] ) ( mprj la_oenb[31] ) + USE SIGNAL
-      + ROUTED met2 ( 1190710 1700 0 ) ( * 44710 )
-      NEW met2 ( 1539850 44710 ) ( * 1580100 )
-      NEW met2 ( 1539850 1580100 ) ( 1541230 * )
-      NEW met2 ( 1541230 1688780 ) ( 1542310 * )
-      NEW met2 ( 1542310 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1541230 1580100 ) ( * 1688780 )
-      NEW met1 ( 1190710 44710 ) ( 1539850 * )
-      NEW met1 ( 1190710 44710 ) M1M2_PR
-      NEW met1 ( 1539850 44710 ) M1M2_PR ;
-    - la_oenb[32] ( PIN la_oenb[32] ) ( mprj la_oenb[32] ) + USE SIGNAL
-      + ROUTED met1 ( 1546750 1652910 ) ( * 1653930 )
-      NEW met2 ( 1546750 17170 ) ( * 1652910 )
-      NEW met2 ( 1546750 1688780 ) ( 1547830 * )
-      NEW met2 ( 1547830 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1546750 1653930 ) ( * 1688780 )
-      NEW met2 ( 1208650 1700 0 ) ( * 17170 )
-      NEW met1 ( 1208650 17170 ) ( 1546750 * )
-      NEW met1 ( 1546750 17170 ) M1M2_PR
-      NEW met1 ( 1546750 1652910 ) M1M2_PR
-      NEW met1 ( 1546750 1653930 ) M1M2_PR
-      NEW met1 ( 1208650 17170 ) M1M2_PR ;
-    - la_oenb[33] ( PIN la_oenb[33] ) ( mprj la_oenb[33] ) + USE SIGNAL
-      + ROUTED met2 ( 1372870 18530 ) ( * 37910 )
-      NEW met2 ( 1553420 1688780 ) ( 1554110 * )
-      NEW met2 ( 1553420 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1554110 37910 ) ( * 1688780 )
-      NEW met2 ( 1226130 1700 0 ) ( * 18530 )
-      NEW met1 ( 1226130 18530 ) ( 1372870 * )
-      NEW met1 ( 1372870 37910 ) ( 1554110 * )
-      NEW met1 ( 1372870 18530 ) M1M2_PR
-      NEW met1 ( 1372870 37910 ) M1M2_PR
-      NEW met1 ( 1554110 37910 ) M1M2_PR
-      NEW met1 ( 1226130 18530 ) M1M2_PR ;
-    - la_oenb[34] ( PIN la_oenb[34] ) ( mprj la_oenb[34] ) + USE SIGNAL
-      + ROUTED met2 ( 1244070 1700 0 ) ( * 19550 )
-      NEW met1 ( 1553650 1652570 ) ( 1558710 * )
-      NEW met2 ( 1376550 19550 ) ( * 38250 )
-      NEW met2 ( 1553650 38250 ) ( * 1652570 )
-      NEW met2 ( 1558710 1688780 ) ( 1558870 * )
-      NEW met2 ( 1558870 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1558710 1652570 ) ( * 1688780 )
-      NEW met1 ( 1244070 19550 ) ( 1376550 * )
-      NEW met1 ( 1376550 38250 ) ( 1553650 * )
-      NEW met1 ( 1244070 19550 ) M1M2_PR
-      NEW met1 ( 1376550 19550 ) M1M2_PR
-      NEW met1 ( 1553650 1652570 ) M1M2_PR
-      NEW met1 ( 1558710 1652570 ) M1M2_PR
-      NEW met1 ( 1376550 38250 ) M1M2_PR
-      NEW met1 ( 1553650 38250 ) M1M2_PR ;
-    - la_oenb[35] ( PIN la_oenb[35] ) ( mprj la_oenb[35] ) + USE SIGNAL
-      + ROUTED met2 ( 1262010 1700 0 ) ( * 19210 )
-      NEW met1 ( 1560090 1688950 ) ( 1564390 * )
-      NEW met2 ( 1564390 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1560090 38590 ) ( * 1688950 )
-      NEW met1 ( 1262010 19210 ) ( 1387590 * )
-      NEW met2 ( 1387590 19210 ) ( * 38590 )
-      NEW met1 ( 1387590 38590 ) ( 1560090 * )
-      NEW met1 ( 1262010 19210 ) M1M2_PR
-      NEW met1 ( 1560090 38590 ) M1M2_PR
-      NEW met1 ( 1560090 1688950 ) M1M2_PR
-      NEW met1 ( 1564390 1688950 ) M1M2_PR
-      NEW met1 ( 1387590 19210 ) M1M2_PR
-      NEW met1 ( 1387590 38590 ) M1M2_PR ;
-    - la_oenb[36] ( PIN la_oenb[36] ) ( mprj la_oenb[36] ) + USE SIGNAL
-      + ROUTED met2 ( 1279490 1700 0 ) ( * 18870 )
-      NEW met2 ( 1567450 38930 ) ( * 1580100 )
-      NEW met2 ( 1567450 1580100 ) ( 1569290 * )
-      NEW met2 ( 1569290 1688780 ) ( 1569910 * )
-      NEW met2 ( 1569910 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1569290 1580100 ) ( * 1688780 )
-      NEW met2 ( 1419330 18870 ) ( * 38930 )
-      NEW met1 ( 1279490 18870 ) ( 1419330 * )
-      NEW met1 ( 1419330 38930 ) ( 1567450 * )
-      NEW met1 ( 1279490 18870 ) M1M2_PR
-      NEW met1 ( 1567450 38930 ) M1M2_PR
-      NEW met1 ( 1419330 18870 ) M1M2_PR
-      NEW met1 ( 1419330 38930 ) M1M2_PR ;
-    - la_oenb[37] ( PIN la_oenb[37] ) ( mprj la_oenb[37] ) + USE SIGNAL
-      + ROUTED met2 ( 1342050 16150 ) ( * 1681810 )
-      NEW met2 ( 1532030 1678070 ) ( * 1681810 )
-      NEW met1 ( 1532030 1678070 ) ( 1575270 * )
-      NEW met2 ( 1575270 1678070 ) ( * 1688780 )
-      NEW met2 ( 1575270 1688780 ) ( 1575430 * )
-      NEW met2 ( 1575430 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1297430 1700 0 ) ( * 16150 )
-      NEW met1 ( 1297430 16150 ) ( 1342050 * )
-      NEW met1 ( 1342050 1681810 ) ( 1532030 * )
-      NEW met1 ( 1342050 16150 ) M1M2_PR
-      NEW met1 ( 1342050 1681810 ) M1M2_PR
-      NEW met1 ( 1532030 1681810 ) M1M2_PR
-      NEW met1 ( 1532030 1678070 ) M1M2_PR
-      NEW met1 ( 1575270 1678070 ) M1M2_PR
-      NEW met1 ( 1297430 16150 ) M1M2_PR ;
-    - la_oenb[38] ( PIN la_oenb[38] ) ( mprj la_oenb[38] ) + USE SIGNAL
-      + ROUTED met2 ( 1312610 1700 ) ( 1314910 * 0 )
-      NEW met2 ( 1312610 1700 ) ( * 2380 )
-      NEW met2 ( 1311230 2380 ) ( 1312610 * )
-      NEW met2 ( 1311230 2380 ) ( * 1679940 )
-      NEW met2 ( 1580330 1679940 ) ( * 1689460 )
-      NEW met2 ( 1580330 1689460 ) ( 1580950 * )
-      NEW met2 ( 1580950 1689460 ) ( * 1690140 0 )
-      NEW met3 ( 1311230 1679940 ) ( 1580330 * )
-      NEW met2 ( 1311230 1679940 ) M2M3_PR
-      NEW met2 ( 1580330 1679940 ) M2M3_PR ;
-    - la_oenb[39] ( PIN la_oenb[39] ) ( mprj la_oenb[39] ) + USE SIGNAL
-      + ROUTED met1 ( 1555490 1680450 ) ( * 1681130 )
-      NEW met2 ( 1332850 1700 0 ) ( 1333770 * )
-      NEW met2 ( 1333770 1700 ) ( * 1680450 )
-      NEW met1 ( 1333770 1680450 ) ( 1555490 * )
-      NEW met2 ( 1586310 1681130 ) ( * 1688780 )
-      NEW met2 ( 1586310 1688780 ) ( 1586470 * )
-      NEW met2 ( 1586470 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1555490 1681130 ) ( 1586310 * )
-      NEW met1 ( 1333770 1680450 ) M1M2_PR
-      NEW met1 ( 1586310 1681130 ) M1M2_PR ;
-    - la_oenb[3] ( PIN la_oenb[3] ) ( mprj la_oenb[3] ) + USE SIGNAL
-      + ROUTED met2 ( 694370 1700 0 ) ( * 60010 )
-      NEW met1 ( 694370 60010 ) ( 1388510 * )
-      NEW met2 ( 1388510 1688780 ) ( 1389130 * )
-      NEW met2 ( 1389130 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1388510 60010 ) ( * 1688780 )
-      NEW met1 ( 694370 60010 ) M1M2_PR
-      NEW met1 ( 1388510 60010 ) M1M2_PR ;
-    - la_oenb[40] ( PIN la_oenb[40] ) ( mprj la_oenb[40] ) + USE SIGNAL
-      + ROUTED met2 ( 1347110 82800 ) ( 1350330 * )
-      NEW met2 ( 1350330 1700 0 ) ( * 82800 )
-      NEW met2 ( 1347110 82800 ) ( * 1681470 )
-      NEW met1 ( 1532490 1681470 ) ( * 1681810 )
-      NEW met1 ( 1532490 1681810 ) ( 1551350 * )
-      NEW met2 ( 1551350 1681810 ) ( * 1681980 )
-      NEW met2 ( 1551350 1681980 ) ( 1551810 * )
-      NEW met2 ( 1551810 1681980 ) ( * 1682830 )
-      NEW met1 ( 1347110 1681470 ) ( 1532490 * )
-      NEW met2 ( 1591830 1682830 ) ( * 1688780 )
-      NEW met2 ( 1591830 1688780 ) ( 1591990 * )
-      NEW met2 ( 1591990 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1551810 1682830 ) ( 1591830 * )
-      NEW met1 ( 1347110 1681470 ) M1M2_PR
-      NEW met1 ( 1551350 1681810 ) M1M2_PR
-      NEW met1 ( 1551810 1682830 ) M1M2_PR
-      NEW met1 ( 1591830 1682830 ) M1M2_PR ;
-    - la_oenb[41] ( PIN la_oenb[41] ) ( mprj la_oenb[41] ) + USE SIGNAL
-      + ROUTED met2 ( 1368270 1700 0 ) ( * 1682150 )
-      NEW met2 ( 1596890 1682150 ) ( * 1688780 )
-      NEW met2 ( 1596890 1688780 ) ( 1597050 * )
-      NEW met2 ( 1597050 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1368270 1682150 ) ( 1596890 * )
-      NEW met1 ( 1368270 1682150 ) M1M2_PR
-      NEW met1 ( 1596890 1682150 ) M1M2_PR ;
-    - la_oenb[42] ( PIN la_oenb[42] ) ( mprj la_oenb[42] ) + USE SIGNAL
-      + ROUTED met2 ( 1383910 1700 ) ( 1385750 * 0 )
-      NEW met1 ( 1380230 58650 ) ( 1383910 * )
-      NEW met2 ( 1383910 1700 ) ( * 58650 )
-      NEW met2 ( 1380230 58650 ) ( * 1682490 )
-      NEW met2 ( 1601030 1682490 ) ( * 1689460 )
-      NEW met2 ( 1601030 1689460 ) ( 1602570 * )
-      NEW met2 ( 1602570 1689460 ) ( * 1690140 0 )
-      NEW met1 ( 1380230 1682490 ) ( 1601030 * )
-      NEW met1 ( 1380230 58650 ) M1M2_PR
-      NEW met1 ( 1383910 58650 ) M1M2_PR
-      NEW met1 ( 1380230 1682490 ) M1M2_PR
-      NEW met1 ( 1601030 1682490 ) M1M2_PR ;
-    - la_oenb[43] ( PIN la_oenb[43] ) ( mprj la_oenb[43] ) + USE SIGNAL
-      + ROUTED met2 ( 1400930 82800 ) ( 1403690 * )
-      NEW met2 ( 1403690 1700 0 ) ( * 82800 )
-      NEW met2 ( 1400930 82800 ) ( * 1683170 )
-      NEW met2 ( 1607930 1683170 ) ( * 1689460 )
-      NEW met2 ( 1607930 1689460 ) ( 1608090 * )
-      NEW met2 ( 1608090 1689460 ) ( * 1690140 0 )
-      NEW met1 ( 1400930 1683170 ) ( 1607930 * )
-      NEW met1 ( 1400930 1683170 ) M1M2_PR
-      NEW met1 ( 1607930 1683170 ) M1M2_PR ;
-    - la_oenb[44] ( PIN la_oenb[44] ) ( mprj la_oenb[44] ) + USE SIGNAL
-      + ROUTED met1 ( 1608390 1688950 ) ( 1613610 * )
-      NEW met2 ( 1613610 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1608390 18870 ) ( * 1688950 )
-      NEW met2 ( 1421630 1700 0 ) ( * 18870 )
-      NEW met1 ( 1421630 18870 ) ( 1608390 * )
-      NEW met1 ( 1608390 18870 ) M1M2_PR
-      NEW met1 ( 1608390 1688950 ) M1M2_PR
-      NEW met1 ( 1613610 1688950 ) M1M2_PR
-      NEW met1 ( 1421630 18870 ) M1M2_PR ;
-    - la_oenb[45] ( PIN la_oenb[45] ) ( mprj la_oenb[45] ) + USE SIGNAL
-      + ROUTED met2 ( 1616210 1688780 ) ( 1619130 * )
-      NEW met2 ( 1619130 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1616210 19210 ) ( * 1688780 )
-      NEW met2 ( 1439110 1700 0 ) ( * 19210 )
-      NEW met1 ( 1439110 19210 ) ( 1616210 * )
-      NEW met1 ( 1616210 19210 ) M1M2_PR
-      NEW met1 ( 1439110 19210 ) M1M2_PR ;
-    - la_oenb[46] ( PIN la_oenb[46] ) ( mprj la_oenb[46] ) + USE SIGNAL
-      + ROUTED met1 ( 1456130 1683510 ) ( 1469470 * )
-      NEW met1 ( 1469470 1683510 ) ( * 1683850 )
-      NEW met1 ( 1469470 1683850 ) ( 1473610 * )
-      NEW met1 ( 1473610 1683510 ) ( * 1683850 )
-      NEW met2 ( 1624490 1683510 ) ( * 1688780 )
-      NEW met2 ( 1624490 1688780 ) ( 1624650 * )
-      NEW met2 ( 1624650 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1473610 1683510 ) ( 1624490 * )
-      NEW met2 ( 1457050 1700 0 ) ( * 13800 )
-      NEW met2 ( 1456130 13800 ) ( 1457050 * )
-      NEW met2 ( 1456130 13800 ) ( * 1683510 )
-      NEW met1 ( 1456130 1683510 ) M1M2_PR
-      NEW met1 ( 1624490 1683510 ) M1M2_PR ;
-    - la_oenb[47] ( PIN la_oenb[47] ) ( mprj la_oenb[47] ) + USE SIGNAL
-      + ROUTED met2 ( 1474530 1700 0 ) ( * 16150 )
-      NEW met2 ( 1563310 82800 ) ( 1563770 * )
-      NEW met2 ( 1563770 16150 ) ( * 82800 )
-      NEW met2 ( 1563310 82800 ) ( * 1678410 )
-      NEW met2 ( 1628630 1678410 ) ( * 1689460 )
-      NEW met2 ( 1628630 1689460 ) ( 1630170 * )
-      NEW met2 ( 1630170 1689460 ) ( * 1690140 0 )
-      NEW met1 ( 1474530 16150 ) ( 1563770 * )
-      NEW met1 ( 1563310 1678410 ) ( 1628630 * )
-      NEW met1 ( 1474530 16150 ) M1M2_PR
-      NEW met1 ( 1563770 16150 ) M1M2_PR
-      NEW met1 ( 1563310 1678410 ) M1M2_PR
-      NEW met1 ( 1628630 1678410 ) M1M2_PR ;
-    - la_oenb[48] ( PIN la_oenb[48] ) ( mprj la_oenb[48] ) + USE SIGNAL
-      + ROUTED met2 ( 1576650 16830 ) ( * 1681810 )
-      NEW met2 ( 1635530 1681810 ) ( * 1689460 )
-      NEW met2 ( 1635530 1689460 ) ( 1635690 * )
-      NEW met2 ( 1635690 1689460 ) ( * 1690140 0 )
-      NEW met2 ( 1492470 1700 0 ) ( * 16830 )
-      NEW met1 ( 1492470 16830 ) ( 1576650 * )
-      NEW met1 ( 1576650 1681810 ) ( 1635530 * )
-      NEW met1 ( 1576650 16830 ) M1M2_PR
-      NEW met1 ( 1576650 1681810 ) M1M2_PR
-      NEW met1 ( 1635530 1681810 ) M1M2_PR
-      NEW met1 ( 1492470 16830 ) M1M2_PR ;
-    - la_oenb[49] ( PIN la_oenb[49] ) ( mprj la_oenb[49] ) + USE SIGNAL
-      + ROUTED met1 ( 1635990 1688950 ) ( 1641210 * )
-      NEW met2 ( 1641210 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1635990 18020 ) ( * 1688950 )
-      NEW met2 ( 1509950 1700 0 ) ( * 16660 )
-      NEW met3 ( 1509950 16660 ) ( 1580100 * )
-      NEW met3 ( 1580100 16660 ) ( * 18020 )
-      NEW met3 ( 1580100 18020 ) ( 1635990 * )
-      NEW met2 ( 1635990 18020 ) M2M3_PR
-      NEW met1 ( 1635990 1688950 ) M1M2_PR
-      NEW met1 ( 1641210 1688950 ) M1M2_PR
-      NEW met2 ( 1509950 16660 ) M2M3_PR ;
-    - la_oenb[4] ( PIN la_oenb[4] ) ( mprj la_oenb[4] ) + USE SIGNAL
-      + ROUTED met2 ( 710930 1700 ) ( 712310 * 0 )
-      NEW met1 ( 710930 86190 ) ( 1394490 * )
-      NEW met2 ( 710930 1700 ) ( * 86190 )
-      NEW met2 ( 1394490 1688780 ) ( 1394650 * )
-      NEW met2 ( 1394650 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1394490 86190 ) ( * 1688780 )
-      NEW met1 ( 710930 86190 ) M1M2_PR
-      NEW met1 ( 1394490 86190 ) M1M2_PR ;
-    - la_oenb[50] ( PIN la_oenb[50] ) ( mprj la_oenb[50] ) + USE SIGNAL
-      + ROUTED met1 ( 1642430 1652230 ) ( * 1653250 )
-      NEW met1 ( 1642430 1653250 ) ( 1642890 * )
-      NEW met2 ( 1642430 19890 ) ( * 1652230 )
-      NEW met1 ( 1642890 1688270 ) ( 1646730 * )
-      NEW met1 ( 1646730 1688270 ) ( * 1689290 )
-      NEW met2 ( 1646730 1689290 ) ( * 1690140 0 )
-      NEW met2 ( 1642890 1653250 ) ( * 1688270 )
-      NEW met2 ( 1527890 1700 0 ) ( * 19890 )
-      NEW met1 ( 1527890 19890 ) ( 1642430 * )
-      NEW met1 ( 1642430 19890 ) M1M2_PR
-      NEW met1 ( 1642430 1652230 ) M1M2_PR
-      NEW met1 ( 1642890 1653250 ) M1M2_PR
-      NEW met1 ( 1642890 1688270 ) M1M2_PR
-      NEW met1 ( 1646730 1689290 ) M1M2_PR
-      NEW met1 ( 1527890 19890 ) M1M2_PR ;
-    - la_oenb[51] ( PIN la_oenb[51] ) ( mprj la_oenb[51] ) + USE SIGNAL
-      + ROUTED met2 ( 1545370 1700 0 ) ( * 20570 )
-      NEW met2 ( 1650710 1688780 ) ( 1652250 * )
-      NEW met2 ( 1652250 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1650710 20570 ) ( * 1688780 )
-      NEW met1 ( 1545370 20570 ) ( 1650710 * )
-      NEW met1 ( 1545370 20570 ) M1M2_PR
-      NEW met1 ( 1650710 20570 ) M1M2_PR ;
-    - la_oenb[52] ( PIN la_oenb[52] ) ( mprj la_oenb[52] ) + USE SIGNAL
-      + ROUTED met2 ( 1563310 1700 0 ) ( * 17510 )
-      NEW met2 ( 1657610 17510 ) ( * 34500 )
-      NEW met2 ( 1657610 34500 ) ( 1658070 * )
-      NEW met2 ( 1657380 1688780 ) ( 1658070 * )
-      NEW met2 ( 1657380 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1658070 34500 ) ( * 1688780 )
-      NEW met1 ( 1563310 17510 ) ( 1657610 * )
-      NEW met1 ( 1563310 17510 ) M1M2_PR
-      NEW met1 ( 1657610 17510 ) M1M2_PR ;
-    - la_oenb[53] ( PIN la_oenb[53] ) ( mprj la_oenb[53] ) + USE SIGNAL
-      + ROUTED met1 ( 1657150 1652570 ) ( 1662670 * )
-      NEW met2 ( 1657150 16830 ) ( * 1652570 )
-      NEW met2 ( 1662670 1688780 ) ( 1662830 * )
-      NEW met2 ( 1662830 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1662670 1652570 ) ( * 1688780 )
-      NEW met2 ( 1581250 1700 0 ) ( * 16830 )
-      NEW met1 ( 1581250 16830 ) ( 1657150 * )
-      NEW met1 ( 1657150 16830 ) M1M2_PR
-      NEW met1 ( 1657150 1652570 ) M1M2_PR
-      NEW met1 ( 1662670 1652570 ) M1M2_PR
-      NEW met1 ( 1581250 16830 ) M1M2_PR ;
-    - la_oenb[54] ( PIN la_oenb[54] ) ( mprj la_oenb[54] ) + USE SIGNAL
-      + ROUTED met2 ( 1668190 1682830 ) ( * 1688780 )
-      NEW met2 ( 1668190 1688780 ) ( 1668350 * )
-      NEW met2 ( 1668350 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1595970 82800 ) ( 1598730 * )
-      NEW met2 ( 1598730 1700 0 ) ( * 82800 )
-      NEW met2 ( 1595970 82800 ) ( * 1682830 )
-      NEW met1 ( 1595970 1682830 ) ( 1668190 * )
-      NEW met1 ( 1668190 1682830 ) M1M2_PR
-      NEW met1 ( 1595970 1682830 ) M1M2_PR ;
-    - la_oenb[55] ( PIN la_oenb[55] ) ( mprj la_oenb[55] ) + USE SIGNAL
-      + ROUTED met2 ( 1644730 15810 ) ( * 18190 )
-      NEW met1 ( 1644730 18190 ) ( 1670030 * )
-      NEW met1 ( 1670030 1652910 ) ( 1673710 * )
-      NEW met2 ( 1670030 18190 ) ( * 1652910 )
-      NEW met2 ( 1673710 1688780 ) ( 1673870 * )
-      NEW met2 ( 1673870 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1673710 1652910 ) ( * 1688780 )
-      NEW met2 ( 1616670 1700 0 ) ( * 15810 )
-      NEW met1 ( 1616670 15810 ) ( 1644730 * )
-      NEW met1 ( 1644730 15810 ) M1M2_PR
-      NEW met1 ( 1644730 18190 ) M1M2_PR
-      NEW met1 ( 1670030 18190 ) M1M2_PR
-      NEW met1 ( 1670030 1652910 ) M1M2_PR
-      NEW met1 ( 1673710 1652910 ) M1M2_PR
-      NEW met1 ( 1616670 15810 ) M1M2_PR ;
-    - la_oenb[56] ( PIN la_oenb[56] ) ( mprj la_oenb[56] ) + USE SIGNAL
-      + ROUTED met2 ( 1634150 1700 0 ) ( * 19550 )
-      NEW met1 ( 1634150 19550 ) ( 1642890 * )
-      NEW met1 ( 1642890 19550 ) ( * 19890 )
-      NEW met1 ( 1642890 19890 ) ( 1677850 * )
-      NEW met2 ( 1677850 1688780 ) ( 1679390 * )
-      NEW met2 ( 1679390 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1677850 19890 ) ( * 1688780 )
-      NEW met1 ( 1634150 19550 ) M1M2_PR
-      NEW met1 ( 1677850 19890 ) M1M2_PR ;
-    - la_oenb[57] ( PIN la_oenb[57] ) ( mprj la_oenb[57] ) + USE SIGNAL
-      + ROUTED met2 ( 1652090 1700 0 ) ( * 20230 )
-      NEW met1 ( 1652090 20230 ) ( 1684750 * )
-      NEW met2 ( 1684750 1688780 ) ( 1684910 * )
-      NEW met2 ( 1684910 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1684750 20230 ) ( * 1688780 )
-      NEW met1 ( 1652090 20230 ) M1M2_PR
-      NEW met1 ( 1684750 20230 ) M1M2_PR ;
-    - la_oenb[58] ( PIN la_oenb[58] ) ( mprj la_oenb[58] ) + USE SIGNAL
-      + ROUTED met2 ( 1669570 1700 0 ) ( * 20570 )
-      NEW met1 ( 1669570 20570 ) ( 1685210 * )
-      NEW met2 ( 1685210 20570 ) ( * 1580100 )
-      NEW met2 ( 1685210 1580100 ) ( 1690270 * )
-      NEW met2 ( 1690270 1688780 ) ( 1690430 * )
-      NEW met2 ( 1690430 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1690270 1580100 ) ( * 1688780 )
-      NEW met1 ( 1669570 20570 ) M1M2_PR
-      NEW met1 ( 1685210 20570 ) M1M2_PR ;
-    - la_oenb[59] ( PIN la_oenb[59] ) ( mprj la_oenb[59] ) + USE SIGNAL
-      + ROUTED met2 ( 1687510 1700 0 ) ( * 17510 )
-      NEW met1 ( 1687510 17510 ) ( 1691650 * )
-      NEW met2 ( 1691650 17510 ) ( * 1580100 )
-      NEW met2 ( 1691650 1580100 ) ( 1693950 * )
-      NEW met2 ( 1693950 1688780 ) ( 1695950 * )
-      NEW met2 ( 1695950 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1693950 1580100 ) ( * 1688780 )
-      NEW met1 ( 1687510 17510 ) M1M2_PR
-      NEW met1 ( 1691650 17510 ) M1M2_PR ;
-    - la_oenb[5] ( PIN la_oenb[5] ) ( mprj la_oenb[5] ) + USE SIGNAL
-      + ROUTED met2 ( 727490 1700 ) ( 729790 * 0 )
-      NEW met1 ( 724730 96050 ) ( 1395410 * )
-      NEW met2 ( 724730 82800 ) ( * 96050 )
-      NEW met2 ( 724730 82800 ) ( 727490 * )
-      NEW met2 ( 727490 1700 ) ( * 82800 )
-      NEW met2 ( 1395410 96050 ) ( * 1580100 )
-      NEW met2 ( 1395410 1580100 ) ( 1399550 * )
-      NEW met2 ( 1399550 1688780 ) ( 1400170 * )
-      NEW met2 ( 1400170 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1399550 1580100 ) ( * 1688780 )
-      NEW met1 ( 724730 96050 ) M1M2_PR
-      NEW met1 ( 1395410 96050 ) M1M2_PR ;
-    - la_oenb[60] ( PIN la_oenb[60] ) ( mprj la_oenb[60] ) + USE SIGNAL
-      + ROUTED met2 ( 1704990 1700 0 ) ( * 16830 )
-      NEW met1 ( 1698550 16830 ) ( 1704990 * )
-      NEW met2 ( 1698550 1688780 ) ( 1701470 * )
-      NEW met2 ( 1701470 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1698550 16830 ) ( * 1688780 )
-      NEW met1 ( 1704990 16830 ) M1M2_PR
-      NEW met1 ( 1698550 16830 ) M1M2_PR ;
-    - la_oenb[61] ( PIN la_oenb[61] ) ( mprj la_oenb[61] ) + USE SIGNAL
-      + ROUTED met2 ( 1722930 1700 0 ) ( * 17510 )
-      NEW met1 ( 1704990 17510 ) ( 1722930 * )
-      NEW met2 ( 1704990 17510 ) ( * 1676700 )
-      NEW met2 ( 1704530 1676700 ) ( 1704990 * )
-      NEW met2 ( 1704530 1676700 ) ( * 1689290 )
-      NEW met1 ( 1704530 1689290 ) ( 1706990 * )
-      NEW met2 ( 1706990 1689290 ) ( * 1690140 0 )
-      NEW met1 ( 1722930 17510 ) M1M2_PR
-      NEW met1 ( 1704990 17510 ) M1M2_PR
-      NEW met1 ( 1704530 1689290 ) M1M2_PR
-      NEW met1 ( 1706990 1689290 ) M1M2_PR ;
-    - la_oenb[62] ( PIN la_oenb[62] ) ( mprj la_oenb[62] ) + USE SIGNAL
-      + ROUTED met2 ( 1740410 1700 0 ) ( * 17850 )
-      NEW met1 ( 1712350 17850 ) ( 1740410 * )
-      NEW met2 ( 1712350 1688780 ) ( 1712510 * )
-      NEW met2 ( 1712510 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1712350 17850 ) ( * 1688780 )
-      NEW met1 ( 1740410 17850 ) M1M2_PR
-      NEW met1 ( 1712350 17850 ) M1M2_PR ;
-    - la_oenb[63] ( PIN la_oenb[63] ) ( mprj la_oenb[63] ) + USE SIGNAL
-      + ROUTED met2 ( 1758350 1700 0 ) ( * 15810 )
-      NEW met1 ( 1725000 15810 ) ( 1758350 * )
-      NEW met1 ( 1711430 16150 ) ( 1725000 * )
-      NEW met1 ( 1725000 15810 ) ( * 16150 )
-      NEW met1 ( 1711430 1688950 ) ( 1717570 * )
-      NEW met2 ( 1717570 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1711430 16150 ) ( * 1688950 )
-      NEW met1 ( 1758350 15810 ) M1M2_PR
-      NEW met1 ( 1711430 16150 ) M1M2_PR
-      NEW met1 ( 1711430 1688950 ) M1M2_PR
-      NEW met1 ( 1717570 1688950 ) M1M2_PR ;
-    - la_oenb[64] ( PIN la_oenb[64] ) ( mprj la_oenb[64] ) + USE SIGNAL
-      + ROUTED met2 ( 1776290 1700 0 ) ( * 20230 )
-      NEW met1 ( 1719250 20230 ) ( 1776290 * )
-      NEW met2 ( 1719250 20230 ) ( * 1676700 )
-      NEW met2 ( 1719250 1676700 ) ( 1722930 * )
-      NEW met2 ( 1722930 1676700 ) ( * 1688780 )
-      NEW met2 ( 1722930 1688780 ) ( 1723090 * )
-      NEW met2 ( 1723090 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1719250 20230 ) M1M2_PR
-      NEW met1 ( 1776290 20230 ) M1M2_PR ;
-    - la_oenb[65] ( PIN la_oenb[65] ) ( mprj la_oenb[65] ) + USE SIGNAL
-      + ROUTED met2 ( 1725230 1688780 ) ( 1728610 * )
-      NEW met2 ( 1728610 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1725230 18530 ) ( * 1688780 )
-      NEW met2 ( 1793770 1700 0 ) ( * 18530 )
-      NEW met1 ( 1725230 18530 ) ( 1793770 * )
-      NEW met1 ( 1725230 18530 ) M1M2_PR
-      NEW met1 ( 1793770 18530 ) M1M2_PR ;
-    - la_oenb[66] ( PIN la_oenb[66] ) ( mprj la_oenb[66] ) + USE SIGNAL
-      + ROUTED met2 ( 1733050 1688780 ) ( 1734130 * )
-      NEW met2 ( 1734130 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1733050 20570 ) ( * 1688780 )
-      NEW met2 ( 1811710 1700 0 ) ( * 20570 )
-      NEW met1 ( 1733050 20570 ) ( 1811710 * )
-      NEW met1 ( 1733050 20570 ) M1M2_PR
-      NEW met1 ( 1811710 20570 ) M1M2_PR ;
-    - la_oenb[67] ( PIN la_oenb[67] ) ( mprj la_oenb[67] ) + USE SIGNAL
-      + ROUTED met2 ( 1829190 1700 0 ) ( * 16490 )
-      NEW met2 ( 1739950 1683510 ) ( * 1689460 )
-      NEW met2 ( 1739720 1689460 ) ( 1739950 * )
-      NEW met2 ( 1739720 1689460 ) ( * 1690140 0 )
-      NEW met1 ( 1797450 16830 ) ( 1806190 * )
-      NEW met1 ( 1806190 16490 ) ( * 16830 )
-      NEW met1 ( 1806190 16490 ) ( 1829190 * )
-      NEW met1 ( 1739950 1683510 ) ( 1797450 * )
-      NEW met2 ( 1797450 16830 ) ( * 1683510 )
-      NEW met1 ( 1829190 16490 ) M1M2_PR
-      NEW met1 ( 1739950 1683510 ) M1M2_PR
-      NEW met1 ( 1797450 16830 ) M1M2_PR
-      NEW met1 ( 1797450 1683510 ) M1M2_PR ;
-    - la_oenb[68] ( PIN la_oenb[68] ) ( mprj la_oenb[68] ) + USE SIGNAL
-      + ROUTED met2 ( 1847130 1700 0 ) ( * 18870 )
-      NEW met2 ( 1739490 18870 ) ( * 1580100 )
-      NEW met2 ( 1739490 1580100 ) ( 1744550 * )
-      NEW met2 ( 1744550 1688780 ) ( 1745170 * )
-      NEW met2 ( 1745170 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1744550 1580100 ) ( * 1688780 )
-      NEW met1 ( 1739490 18870 ) ( 1847130 * )
-      NEW met1 ( 1739490 18870 ) M1M2_PR
-      NEW met1 ( 1847130 18870 ) M1M2_PR ;
-    - la_oenb[69] ( PIN la_oenb[69] ) ( mprj la_oenb[69] ) + USE SIGNAL
-      + ROUTED met2 ( 1864610 1700 0 ) ( * 17850 )
-      NEW met2 ( 1746390 17850 ) ( * 1580100 )
-      NEW met2 ( 1746390 1580100 ) ( 1750070 * )
-      NEW met2 ( 1750070 1688780 ) ( 1750690 * )
-      NEW met2 ( 1750690 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1750070 1580100 ) ( * 1688780 )
-      NEW met1 ( 1746390 17850 ) ( 1864610 * )
-      NEW met1 ( 1746390 17850 ) M1M2_PR
-      NEW met1 ( 1864610 17850 ) M1M2_PR ;
-    - la_oenb[6] ( PIN la_oenb[6] ) ( mprj la_oenb[6] ) + USE SIGNAL
-      + ROUTED met1 ( 745430 96390 ) ( 1402770 * )
-      NEW met2 ( 745430 82800 ) ( * 96390 )
-      NEW met2 ( 745430 82800 ) ( 747730 * )
-      NEW met2 ( 747730 1700 0 ) ( * 82800 )
-      NEW met2 ( 1402770 1688780 ) ( 1405690 * )
-      NEW met2 ( 1405690 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1402770 96390 ) ( * 1688780 )
-      NEW met1 ( 745430 96390 ) M1M2_PR
-      NEW met1 ( 1402770 96390 ) M1M2_PR ;
-    - la_oenb[70] ( PIN la_oenb[70] ) ( mprj la_oenb[70] ) + USE SIGNAL
-      + ROUTED met2 ( 1752830 17170 ) ( * 1580100 )
-      NEW met2 ( 1752830 1580100 ) ( 1755590 * )
-      NEW met2 ( 1755590 1688780 ) ( 1756210 * )
-      NEW met2 ( 1756210 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1755590 1580100 ) ( * 1688780 )
-      NEW met2 ( 1882550 1700 0 ) ( * 17170 )
-      NEW met1 ( 1752830 17170 ) ( 1882550 * )
-      NEW met1 ( 1752830 17170 ) M1M2_PR
-      NEW met1 ( 1882550 17170 ) M1M2_PR ;
-    - la_oenb[71] ( PIN la_oenb[71] ) ( mprj la_oenb[71] ) + USE SIGNAL
-      + ROUTED met2 ( 1762030 1681470 ) ( * 1688780 )
-      NEW met2 ( 1761800 1688780 ) ( 1762030 * )
-      NEW met2 ( 1761800 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1900030 1700 0 ) ( * 18870 )
-      NEW met1 ( 1852650 18870 ) ( 1900030 * )
-      NEW met1 ( 1762030 1681470 ) ( 1852650 * )
-      NEW met2 ( 1852650 18870 ) ( * 1681470 )
-      NEW met1 ( 1852650 18870 ) M1M2_PR
-      NEW met1 ( 1762030 1681470 ) M1M2_PR
-      NEW met1 ( 1900030 18870 ) M1M2_PR
-      NEW met1 ( 1852650 1681470 ) M1M2_PR ;
-    - la_oenb[72] ( PIN la_oenb[72] ) ( mprj la_oenb[72] ) + USE SIGNAL
-      + ROUTED met2 ( 1766630 1688780 ) ( 1767250 * )
-      NEW met2 ( 1767250 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1766630 17510 ) ( * 1688780 )
-      NEW met2 ( 1917970 1700 0 ) ( * 17510 )
-      NEW met1 ( 1766630 17510 ) ( 1917970 * )
-      NEW met1 ( 1766630 17510 ) M1M2_PR
-      NEW met1 ( 1917970 17510 ) M1M2_PR ;
-    - la_oenb[73] ( PIN la_oenb[73] ) ( mprj la_oenb[73] ) + USE SIGNAL
-      + ROUTED met2 ( 1935910 1700 0 ) ( * 15470 )
-      NEW met2 ( 1773070 1681130 ) ( * 1688780 )
-      NEW met2 ( 1772840 1688780 ) ( 1773070 * )
-      NEW met2 ( 1772840 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1918200 15470 ) ( 1935910 * )
-      NEW met1 ( 1918200 15130 ) ( * 15470 )
-      NEW met1 ( 1859550 15130 ) ( 1918200 * )
-      NEW met1 ( 1773070 1681130 ) ( 1859550 * )
-      NEW met2 ( 1859550 15130 ) ( * 1681130 )
-      NEW met1 ( 1859550 15130 ) M1M2_PR
-      NEW met1 ( 1935910 15470 ) M1M2_PR
-      NEW met1 ( 1773070 1681130 ) M1M2_PR
-      NEW met1 ( 1859550 1681130 ) M1M2_PR ;
-    - la_oenb[74] ( PIN la_oenb[74] ) ( mprj la_oenb[74] ) + USE SIGNAL
-      + ROUTED met2 ( 1953390 1700 0 ) ( * 15810 )
-      NEW met1 ( 1866450 15470 ) ( 1869900 * )
-      NEW met1 ( 1869900 15470 ) ( * 15810 )
-      NEW met1 ( 1869900 15810 ) ( 1877030 * )
-      NEW met2 ( 1877030 15810 ) ( * 15980 )
-      NEW met2 ( 1877030 15980 ) ( 1878410 * )
-      NEW met2 ( 1878410 15810 ) ( * 15980 )
-      NEW met1 ( 1878410 15810 ) ( 1953390 * )
-      NEW met2 ( 1778130 1680450 ) ( * 1688780 )
-      NEW met2 ( 1777900 1688780 ) ( 1778130 * )
-      NEW met2 ( 1777900 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1778130 1680450 ) ( 1866450 * )
-      NEW met2 ( 1866450 15470 ) ( * 1680450 )
-      NEW met1 ( 1866450 15470 ) M1M2_PR
-      NEW met1 ( 1953390 15810 ) M1M2_PR
-      NEW met1 ( 1877030 15810 ) M1M2_PR
-      NEW met1 ( 1878410 15810 ) M1M2_PR
-      NEW met1 ( 1778130 1680450 ) M1M2_PR
-      NEW met1 ( 1866450 1680450 ) M1M2_PR ;
-    - la_oenb[75] ( PIN la_oenb[75] ) ( mprj la_oenb[75] ) + USE SIGNAL
-      + ROUTED met1 ( 1873350 15470 ) ( 1877490 * )
-      NEW met1 ( 1877490 15470 ) ( * 16150 )
-      NEW met2 ( 1971330 1700 0 ) ( * 16150 )
-      NEW met1 ( 1877490 16150 ) ( 1971330 * )
-      NEW met2 ( 1783650 1681810 ) ( * 1688780 )
-      NEW met2 ( 1783420 1688780 ) ( 1783650 * )
-      NEW met2 ( 1783420 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1783650 1681810 ) ( 1873350 * )
-      NEW met2 ( 1873350 15470 ) ( * 1681810 )
-      NEW met1 ( 1873350 15470 ) M1M2_PR
-      NEW met1 ( 1971330 16150 ) M1M2_PR
-      NEW met1 ( 1783650 1681810 ) M1M2_PR
-      NEW met1 ( 1873350 1681810 ) M1M2_PR ;
-    - la_oenb[76] ( PIN la_oenb[76] ) ( mprj la_oenb[76] ) + USE SIGNAL
-      + ROUTED met2 ( 1787330 1652740 ) ( 1788250 * )
-      NEW met2 ( 1988810 1700 0 ) ( * 21930 )
-      NEW met1 ( 1787330 21930 ) ( 1988810 * )
-      NEW met2 ( 1787330 21930 ) ( * 1652740 )
-      NEW met2 ( 1788250 1688780 ) ( 1788870 * )
-      NEW met2 ( 1788870 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1788250 1652740 ) ( * 1688780 )
-      NEW met1 ( 1787330 21930 ) M1M2_PR
-      NEW met1 ( 1988810 21930 ) M1M2_PR ;
-    - la_oenb[77] ( PIN la_oenb[77] ) ( mprj la_oenb[77] ) + USE SIGNAL
-      + ROUTED met2 ( 2006750 1700 0 ) ( * 18190 )
-      NEW met1 ( 1860010 18190 ) ( 2006750 * )
-      NEW met2 ( 1794230 1678750 ) ( * 1689460 )
-      NEW met2 ( 1794230 1689460 ) ( 1794390 * )
-      NEW met2 ( 1794390 1689460 ) ( * 1690140 0 )
-      NEW met1 ( 1794230 1678750 ) ( 1860010 * )
-      NEW met2 ( 1860010 18190 ) ( * 1678750 )
-      NEW met1 ( 1860010 18190 ) M1M2_PR
-      NEW met1 ( 2006750 18190 ) M1M2_PR
-      NEW met1 ( 1794230 1678750 ) M1M2_PR
-      NEW met1 ( 1860010 1678750 ) M1M2_PR ;
-    - la_oenb[78] ( PIN la_oenb[78] ) ( mprj la_oenb[78] ) + USE SIGNAL
-      + ROUTED met2 ( 2024230 1700 0 ) ( * 16660 )
-      NEW met2 ( 1794230 22100 ) ( 1794690 * )
-      NEW met2 ( 1794690 16660 ) ( * 22100 )
-      NEW met1 ( 1794230 1652570 ) ( 1799750 * )
-      NEW met3 ( 1794690 16660 ) ( 2024230 * )
-      NEW met2 ( 1794230 22100 ) ( * 1652570 )
-      NEW met2 ( 1799750 1688780 ) ( 1799910 * )
-      NEW met2 ( 1799910 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1799750 1652570 ) ( * 1688780 )
-      NEW met2 ( 2024230 16660 ) M2M3_PR
-      NEW met2 ( 1794690 16660 ) M2M3_PR
-      NEW met1 ( 1794230 1652570 ) M1M2_PR
-      NEW met1 ( 1799750 1652570 ) M1M2_PR ;
-    - la_oenb[79] ( PIN la_oenb[79] ) ( mprj la_oenb[79] ) + USE SIGNAL
-      + ROUTED met2 ( 2042170 1700 0 ) ( * 17170 )
-      NEW met1 ( 1887150 17170 ) ( 2042170 * )
-      NEW met2 ( 1805730 1679090 ) ( * 1688780 )
-      NEW met2 ( 1805500 1688780 ) ( 1805730 * )
-      NEW met2 ( 1805500 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1805730 1679090 ) ( 1887150 * )
-      NEW met2 ( 1887150 17170 ) ( * 1679090 )
-      NEW met1 ( 2042170 17170 ) M1M2_PR
-      NEW met1 ( 1887150 17170 ) M1M2_PR
-      NEW met1 ( 1805730 1679090 ) M1M2_PR
-      NEW met1 ( 1887150 1679090 ) M1M2_PR ;
-    - la_oenb[7] ( PIN la_oenb[7] ) ( mprj la_oenb[7] ) + USE SIGNAL
-      + ROUTED met2 ( 759230 48300 ) ( * 92650 )
-      NEW met2 ( 765210 1700 0 ) ( * 48110 )
-      NEW met1 ( 759230 92650 ) ( 1408750 * )
-      NEW met2 ( 758770 48110 ) ( * 48300 )
-      NEW met1 ( 758770 48110 ) ( 765210 * )
-      NEW met2 ( 758770 48300 ) ( 759230 * )
-      NEW met2 ( 1408750 92650 ) ( * 1580100 )
-      NEW met2 ( 1408750 1580100 ) ( 1410590 * )
-      NEW met2 ( 1410590 1688780 ) ( 1411210 * )
-      NEW met2 ( 1411210 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1410590 1580100 ) ( * 1688780 )
-      NEW met1 ( 759230 92650 ) M1M2_PR
-      NEW met1 ( 765210 48110 ) M1M2_PR
-      NEW met1 ( 1408750 92650 ) M1M2_PR
-      NEW met1 ( 758770 48110 ) M1M2_PR ;
-    - la_oenb[80] ( PIN la_oenb[80] ) ( mprj la_oenb[80] ) + USE SIGNAL
-      + ROUTED met2 ( 2059650 1700 0 ) ( * 18870 )
-      NEW met1 ( 1908310 18870 ) ( 2059650 * )
-      NEW met2 ( 1811250 1679770 ) ( * 1688780 )
-      NEW met2 ( 1811020 1688780 ) ( 1811250 * )
-      NEW met2 ( 1811020 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1908310 18870 ) ( * 1679770 )
-      NEW met1 ( 1811250 1679770 ) ( 1908310 * )
-      NEW met1 ( 2059650 18870 ) M1M2_PR
-      NEW met1 ( 1908310 18870 ) M1M2_PR
-      NEW met1 ( 1811250 1679770 ) M1M2_PR
-      NEW met1 ( 1908310 1679770 ) M1M2_PR ;
-    - la_oenb[81] ( PIN la_oenb[81] ) ( mprj la_oenb[81] ) + USE SIGNAL
-      + ROUTED met2 ( 1938670 20570 ) ( * 26690 )
-      NEW met1 ( 1814930 26690 ) ( 1938670 * )
-      NEW met2 ( 2077590 1700 0 ) ( * 20570 )
-      NEW met1 ( 1938670 20570 ) ( 2077590 * )
-      NEW met2 ( 1814930 1688780 ) ( 1816470 * )
-      NEW met2 ( 1816470 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1814930 26690 ) ( * 1688780 )
-      NEW met1 ( 1938670 26690 ) M1M2_PR
-      NEW met1 ( 1938670 20570 ) M1M2_PR
-      NEW met1 ( 1814930 26690 ) M1M2_PR
-      NEW met1 ( 2077590 20570 ) M1M2_PR ;
-    - la_oenb[82] ( PIN la_oenb[82] ) ( mprj la_oenb[82] ) + USE SIGNAL
-      + ROUTED met2 ( 1822290 1679430 ) ( * 1689460 )
-      NEW met2 ( 1822060 1689460 ) ( 1822290 * )
-      NEW met2 ( 1822060 1689460 ) ( * 1690140 0 )
-      NEW met2 ( 2095070 1700 0 ) ( * 17850 )
-      NEW met1 ( 1907850 17850 ) ( 2095070 * )
-      NEW met2 ( 1907850 17850 ) ( * 1679430 )
-      NEW met1 ( 1822290 1679430 ) ( 1907850 * )
-      NEW met1 ( 1822290 1679430 ) M1M2_PR
-      NEW met1 ( 1907850 17850 ) M1M2_PR
-      NEW met1 ( 2095070 17850 ) M1M2_PR
-      NEW met1 ( 1907850 1679430 ) M1M2_PR ;
-    - la_oenb[83] ( PIN la_oenb[83] ) ( mprj la_oenb[83] ) + USE SIGNAL
-      + ROUTED met1 ( 1956150 18530 ) ( 1959830 * )
-      NEW met2 ( 1959830 18530 ) ( * 19550 )
-      NEW met2 ( 2113010 1700 0 ) ( * 19550 )
-      NEW met1 ( 1844370 1683510 ) ( * 1683850 )
-      NEW met1 ( 1843450 1683850 ) ( 1844370 * )
-      NEW met1 ( 1843450 1683510 ) ( * 1683850 )
-      NEW met1 ( 1827810 1683510 ) ( 1843450 * )
-      NEW met2 ( 1827810 1683510 ) ( * 1688780 )
-      NEW met2 ( 1827580 1688780 ) ( 1827810 * )
-      NEW met2 ( 1827580 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1938670 1683510 ) ( * 1683850 )
-      NEW met1 ( 1938670 1683850 ) ( 1944650 * )
-      NEW met1 ( 1944650 1683510 ) ( * 1683850 )
-      NEW met1 ( 1944650 1683510 ) ( 1956150 * )
-      NEW met2 ( 1956150 18530 ) ( * 1683510 )
-      NEW met1 ( 1959830 19550 ) ( 2113010 * )
-      NEW met1 ( 1844370 1683510 ) ( 1938670 * )
-      NEW met1 ( 1956150 18530 ) M1M2_PR
-      NEW met1 ( 1959830 18530 ) M1M2_PR
-      NEW met1 ( 1959830 19550 ) M1M2_PR
-      NEW met1 ( 2113010 19550 ) M1M2_PR
-      NEW met1 ( 1827810 1683510 ) M1M2_PR
-      NEW met1 ( 1956150 1683510 ) M1M2_PR ;
-    - la_oenb[84] ( PIN la_oenb[84] ) ( mprj la_oenb[84] ) + USE SIGNAL
-      + ROUTED met2 ( 1942350 17510 ) ( * 27030 )
-      NEW met1 ( 1942350 17510 ) ( 1960290 * )
-      NEW met2 ( 1960290 17510 ) ( * 18530 )
-      NEW met2 ( 2130950 1700 0 ) ( * 18530 )
-      NEW met1 ( 1828730 1688950 ) ( 1833030 * )
-      NEW met2 ( 1833030 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1828730 27030 ) ( * 1688950 )
-      NEW met1 ( 1828730 27030 ) ( 1942350 * )
-      NEW met1 ( 1960290 18530 ) ( 2130950 * )
-      NEW met1 ( 1828730 27030 ) M1M2_PR
-      NEW met1 ( 1942350 27030 ) M1M2_PR
-      NEW met1 ( 1942350 17510 ) M1M2_PR
-      NEW met1 ( 1960290 17510 ) M1M2_PR
-      NEW met1 ( 1960290 18530 ) M1M2_PR
-      NEW met1 ( 2130950 18530 ) M1M2_PR
-      NEW met1 ( 1828730 1688950 ) M1M2_PR
-      NEW met1 ( 1833030 1688950 ) M1M2_PR ;
-    - la_oenb[85] ( PIN la_oenb[85] ) ( mprj la_oenb[85] ) + USE SIGNAL
-      + ROUTED met2 ( 2148430 1700 0 ) ( * 15810 )
-      NEW met1 ( 2114850 15810 ) ( 2148430 * )
-      NEW met1 ( 1848050 1682830 ) ( * 1683170 )
-      NEW met1 ( 1838390 1682830 ) ( 1848050 * )
-      NEW met2 ( 1838390 1682830 ) ( * 1688780 )
-      NEW met2 ( 1838160 1688780 ) ( 1838390 * )
-      NEW met2 ( 1838160 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 2114850 15810 ) ( * 1683170 )
-      NEW met1 ( 1848050 1683170 ) ( 2114850 * )
-      NEW met1 ( 2148430 15810 ) M1M2_PR
-      NEW met1 ( 2114850 15810 ) M1M2_PR
-      NEW met1 ( 1838390 1682830 ) M1M2_PR
-      NEW met1 ( 2114850 1683170 ) M1M2_PR ;
-    - la_oenb[86] ( PIN la_oenb[86] ) ( mprj la_oenb[86] ) + USE SIGNAL
-      + ROUTED met2 ( 2128650 15130 ) ( * 1682830 )
-      NEW met2 ( 2166370 1700 0 ) ( * 15130 )
-      NEW met1 ( 2128650 15130 ) ( 2166370 * )
-      NEW met1 ( 1848510 1682490 ) ( * 1682830 )
-      NEW met1 ( 1843910 1682490 ) ( 1848510 * )
-      NEW met2 ( 1843910 1682490 ) ( * 1688780 )
-      NEW met2 ( 1843680 1688780 ) ( 1843910 * )
-      NEW met2 ( 1843680 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1848510 1682830 ) ( 2128650 * )
-      NEW met1 ( 2128650 15130 ) M1M2_PR
-      NEW met1 ( 2128650 1682830 ) M1M2_PR
-      NEW met1 ( 2166370 15130 ) M1M2_PR
-      NEW met1 ( 1843910 1682490 ) M1M2_PR ;
-    - la_oenb[87] ( PIN la_oenb[87] ) ( mprj la_oenb[87] ) + USE SIGNAL
-      + ROUTED met2 ( 2129110 19550 ) ( * 1682490 )
-      NEW met2 ( 2183850 1700 0 ) ( * 19550 )
-      NEW met1 ( 2129110 19550 ) ( 2183850 * )
-      NEW met1 ( 1865530 1682150 ) ( * 1682490 )
-      NEW met1 ( 1848970 1682150 ) ( 1865530 * )
-      NEW met2 ( 1848970 1682150 ) ( * 1688780 )
-      NEW met2 ( 1848970 1688780 ) ( 1849130 * )
-      NEW met2 ( 1849130 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1865530 1682490 ) ( 2129110 * )
-      NEW met1 ( 2129110 19550 ) M1M2_PR
-      NEW met1 ( 2129110 1682490 ) M1M2_PR
-      NEW met1 ( 2183850 19550 ) M1M2_PR
-      NEW met1 ( 1848970 1682150 ) M1M2_PR ;
-    - la_oenb[88] ( PIN la_oenb[88] ) ( mprj la_oenb[88] ) + USE SIGNAL
-      + ROUTED met2 ( 2201790 1700 0 ) ( * 16490 )
-      NEW met1 ( 2163610 16490 ) ( 2201790 * )
-      NEW met2 ( 2163610 16490 ) ( * 1680790 )
-      NEW met2 ( 1854950 1680790 ) ( * 1688780 )
-      NEW met2 ( 1854720 1688780 ) ( 1854950 * )
-      NEW met2 ( 1854720 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1854950 1680790 ) ( 2163610 * )
-      NEW met1 ( 2201790 16490 ) M1M2_PR
-      NEW met1 ( 2163610 16490 ) M1M2_PR
-      NEW met1 ( 2163610 1680790 ) M1M2_PR
-      NEW met1 ( 1854950 1680790 ) M1M2_PR ;
-    - la_oenb[89] ( PIN la_oenb[89] ) ( mprj la_oenb[89] ) + USE SIGNAL
-      + ROUTED met2 ( 2216970 1700 ) ( 2219270 * 0 )
-      NEW met2 ( 1857710 80070 ) ( * 1580100 )
-      NEW met2 ( 1857710 1580100 ) ( 1858630 * )
-      NEW met2 ( 2216970 1700 ) ( * 80070 )
-      NEW met1 ( 1857710 80070 ) ( 2216970 * )
-      NEW met2 ( 1858630 1688780 ) ( 1860170 * )
-      NEW met2 ( 1860170 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1858630 1580100 ) ( * 1688780 )
-      NEW met1 ( 1857710 80070 ) M1M2_PR
-      NEW met1 ( 2216970 80070 ) M1M2_PR ;
-    - la_oenb[8] ( PIN la_oenb[8] ) ( mprj la_oenb[8] ) + USE SIGNAL
-      + ROUTED met2 ( 780850 1700 ) ( 783150 * 0 )
-      NEW met2 ( 780850 1700 ) ( * 64770 )
-      NEW met1 ( 780850 64770 ) ( 1416110 * )
-      NEW met2 ( 1416110 1688780 ) ( 1416270 * )
-      NEW met2 ( 1416270 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1416110 64770 ) ( * 1688780 )
-      NEW met1 ( 780850 64770 ) M1M2_PR
-      NEW met1 ( 1416110 64770 ) M1M2_PR ;
-    - la_oenb[90] ( PIN la_oenb[90] ) ( mprj la_oenb[90] ) + USE SIGNAL
-      + ROUTED met2 ( 2237210 1700 0 ) ( * 20570 )
-      NEW met1 ( 2163150 20570 ) ( 2237210 * )
-      NEW met2 ( 2163150 20570 ) ( * 1682150 )
-      NEW met2 ( 1865990 1682150 ) ( * 1689460 )
-      NEW met2 ( 1865760 1689460 ) ( 1865990 * )
-      NEW met2 ( 1865760 1689460 ) ( * 1690140 0 )
-      NEW met1 ( 1865990 1682150 ) ( 2163150 * )
-      NEW met1 ( 2237210 20570 ) M1M2_PR
-      NEW met1 ( 2163150 20570 ) M1M2_PR
-      NEW met1 ( 2163150 1682150 ) M1M2_PR
-      NEW met1 ( 1865990 1682150 ) M1M2_PR ;
-    - la_oenb[91] ( PIN la_oenb[91] ) ( mprj la_oenb[91] ) + USE SIGNAL
-      + ROUTED met2 ( 2254690 1700 0 ) ( * 19210 )
-      NEW met1 ( 1870130 19210 ) ( 2254690 * )
-      NEW met2 ( 1870130 1689460 ) ( 1871210 * )
-      NEW met2 ( 1871210 1689460 ) ( * 1690140 0 )
-      NEW met2 ( 1870130 19210 ) ( * 1689460 )
-      NEW met1 ( 2254690 19210 ) M1M2_PR
-      NEW met1 ( 1870130 19210 ) M1M2_PR ;
-    - la_oenb[92] ( PIN la_oenb[92] ) ( mprj la_oenb[92] ) + USE SIGNAL
-      + ROUTED met2 ( 2272630 1700 0 ) ( * 19550 )
-      NEW met1 ( 2184310 19550 ) ( 2272630 * )
-      NEW met2 ( 2183850 82800 ) ( 2184310 * )
-      NEW met2 ( 2184310 19550 ) ( * 82800 )
-      NEW met2 ( 2183850 82800 ) ( * 1681130 )
-      NEW met2 ( 1876570 1681130 ) ( * 1689460 )
-      NEW met2 ( 1876570 1689460 ) ( 1876730 * )
-      NEW met2 ( 1876730 1689460 ) ( * 1690140 0 )
-      NEW met1 ( 1876570 1681130 ) ( 2183850 * )
-      NEW met1 ( 2184310 19550 ) M1M2_PR
-      NEW met1 ( 2272630 19550 ) M1M2_PR
-      NEW met1 ( 2183850 1681130 ) M1M2_PR
-      NEW met1 ( 1876570 1681130 ) M1M2_PR ;
-    - la_oenb[93] ( PIN la_oenb[93] ) ( mprj la_oenb[93] ) + USE SIGNAL
-      + ROUTED met1 ( 2176950 16830 ) ( 2202250 * )
-      NEW met1 ( 2202250 16490 ) ( * 16830 )
-      NEW met2 ( 2290570 1700 0 ) ( * 16490 )
-      NEW met1 ( 2202250 16490 ) ( 2290570 * )
-      NEW met2 ( 2176950 16830 ) ( * 1681810 )
-      NEW met2 ( 1882550 1681810 ) ( * 1688780 )
-      NEW met2 ( 1882320 1688780 ) ( 1882550 * )
-      NEW met2 ( 1882320 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1882550 1681810 ) ( 2176950 * )
-      NEW met1 ( 2176950 16830 ) M1M2_PR
-      NEW met1 ( 2290570 16490 ) M1M2_PR
-      NEW met1 ( 2176950 1681810 ) M1M2_PR
-      NEW met1 ( 1882550 1681810 ) M1M2_PR ;
-    - la_oenb[94] ( PIN la_oenb[94] ) ( mprj la_oenb[94] ) + USE SIGNAL
-      + ROUTED met2 ( 2308050 1700 0 ) ( * 16150 )
-      NEW met2 ( 2211450 82800 ) ( 2213750 * )
-      NEW met2 ( 2213750 15810 ) ( * 82800 )
-      NEW met2 ( 2211450 82800 ) ( * 1680450 )
-      NEW met1 ( 2213750 15810 ) ( 2256300 * )
-      NEW met1 ( 2256300 15810 ) ( * 16150 )
-      NEW met1 ( 2256300 16150 ) ( 2308050 * )
-      NEW met2 ( 1888070 1680450 ) ( * 1688780 )
-      NEW met2 ( 1887840 1688780 ) ( 1888070 * )
-      NEW met2 ( 1887840 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1888070 1680450 ) ( 2211450 * )
-      NEW met1 ( 2213750 15810 ) M1M2_PR
-      NEW met1 ( 2308050 16150 ) M1M2_PR
-      NEW met1 ( 2211450 1680450 ) M1M2_PR
-      NEW met1 ( 1888070 1680450 ) M1M2_PR ;
-    - la_oenb[95] ( PIN la_oenb[95] ) ( mprj la_oenb[95] ) + USE SIGNAL
-      + ROUTED met2 ( 2325990 1700 0 ) ( * 79730 )
-      NEW met1 ( 1892210 79730 ) ( 2325990 * )
-      NEW met2 ( 1892210 1688780 ) ( 1893290 * )
-      NEW met2 ( 1893290 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1892210 79730 ) ( * 1688780 )
-      NEW met1 ( 2325990 79730 ) M1M2_PR
-      NEW met1 ( 1892210 79730 ) M1M2_PR ;
-    - la_oenb[96] ( PIN la_oenb[96] ) ( mprj la_oenb[96] ) + USE SIGNAL
-      + ROUTED met2 ( 2343470 1700 0 ) ( * 16830 )
-      NEW met1 ( 2204550 16830 ) ( 2343470 * )
-      NEW met2 ( 1898650 1681470 ) ( * 1689460 )
-      NEW met2 ( 1898420 1689460 ) ( 1898650 * )
-      NEW met2 ( 1898420 1689460 ) ( * 1690140 0 )
-      NEW met1 ( 1898650 1681470 ) ( 2204550 * )
-      NEW met2 ( 2204550 16830 ) ( * 1681470 )
-      NEW met1 ( 2343470 16830 ) M1M2_PR
-      NEW met1 ( 2204550 16830 ) M1M2_PR
-      NEW met1 ( 1898650 1681470 ) M1M2_PR
-      NEW met1 ( 2204550 1681470 ) M1M2_PR ;
-    - la_oenb[97] ( PIN la_oenb[97] ) ( mprj la_oenb[97] ) + USE SIGNAL
-      + ROUTED met2 ( 2361410 1700 0 ) ( * 20230 )
-      NEW met1 ( 1897730 20230 ) ( 2361410 * )
-      NEW met1 ( 1897730 1688950 ) ( 1903870 * )
-      NEW met2 ( 1903870 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1897730 20230 ) ( * 1688950 )
-      NEW met1 ( 1897730 20230 ) M1M2_PR
-      NEW met1 ( 2361410 20230 ) M1M2_PR
-      NEW met1 ( 1897730 1688950 ) M1M2_PR
-      NEW met1 ( 1903870 1688950 ) M1M2_PR ;
-    - la_oenb[98] ( PIN la_oenb[98] ) ( mprj la_oenb[98] ) + USE SIGNAL
-      + ROUTED met2 ( 2239050 20570 ) ( * 1680110 )
-      NEW met2 ( 2378890 1700 0 ) ( * 20570 )
-      NEW met1 ( 2239050 20570 ) ( 2378890 * )
-      NEW met2 ( 1909690 1680110 ) ( * 1688780 )
-      NEW met2 ( 1909460 1688780 ) ( 1909690 * )
-      NEW met2 ( 1909460 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1909690 1680110 ) ( 2239050 * )
-      NEW met1 ( 2239050 20570 ) M1M2_PR
-      NEW met1 ( 2239050 1680110 ) M1M2_PR
-      NEW met1 ( 2378890 20570 ) M1M2_PR
-      NEW met1 ( 1909690 1680110 ) M1M2_PR ;
-    - la_oenb[99] ( PIN la_oenb[99] ) ( mprj la_oenb[99] ) + USE SIGNAL
-      + ROUTED met2 ( 2396830 1700 0 ) ( * 19890 )
-      NEW met1 ( 1911530 19890 ) ( 2396830 * )
-      NEW met2 ( 1911530 1689460 ) ( 1911990 * )
-      NEW met2 ( 1911990 1689460 ) ( * 1689630 )
-      NEW met1 ( 1911990 1689630 ) ( 1914910 * )
-      NEW met2 ( 1914910 1689630 ) ( * 1690140 0 )
-      NEW met2 ( 1911530 19890 ) ( * 1689460 )
-      NEW met1 ( 1911530 19890 ) M1M2_PR
-      NEW met1 ( 2396830 19890 ) M1M2_PR
-      NEW met1 ( 1911990 1689630 ) M1M2_PR
-      NEW met1 ( 1914910 1689630 ) M1M2_PR ;
-    - la_oenb[9] ( PIN la_oenb[9] ) ( mprj la_oenb[9] ) + USE SIGNAL
-      + ROUTED met2 ( 800630 1700 0 ) ( * 64430 )
-      NEW met1 ( 800630 64430 ) ( 1422550 * )
-      NEW met2 ( 1421860 1688780 ) ( 1422550 * )
-      NEW met2 ( 1421860 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1422550 64430 ) ( * 1688780 )
-      NEW met1 ( 800630 64430 ) M1M2_PR
-      NEW met1 ( 1422550 64430 ) M1M2_PR ;
-    - user_clock2 ( PIN user_clock2 ) + USE SIGNAL ;
-    - user_irq[0] ( PIN user_irq[0] ) ( mprj irq[0] ) + USE SIGNAL
-      + ROUTED met2 ( 2905130 1700 0 ) ( * 19210 )
-      NEW met2 ( 2252850 82800 ) ( 2255150 * )
-      NEW met2 ( 2255150 19210 ) ( * 82800 )
-      NEW met2 ( 2252850 82800 ) ( * 1683510 )
-      NEW met1 ( 2255150 19210 ) ( 2905130 * )
-      NEW met2 ( 2070690 1683510 ) ( * 1688780 )
-      NEW met2 ( 2070460 1688780 ) ( 2070690 * )
-      NEW met2 ( 2070460 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 2070690 1683510 ) ( 2252850 * )
-      NEW met1 ( 2255150 19210 ) M1M2_PR
-      NEW met1 ( 2905130 19210 ) M1M2_PR
-      NEW met1 ( 2252850 1683510 ) M1M2_PR
-      NEW met1 ( 2070690 1683510 ) M1M2_PR ;
-    - user_irq[1] ( PIN user_irq[1] ) ( mprj irq[1] ) + USE SIGNAL
-      + ROUTED met2 ( 2911110 1700 0 ) ( * 16660 )
-      NEW met3 ( 2070230 16660 ) ( 2911110 * )
-      NEW met2 ( 2070230 16660 ) ( * 1580100 )
-      NEW met2 ( 2070230 1580100 ) ( 2071150 * )
-      NEW met2 ( 2071150 1688780 ) ( 2072230 * )
-      NEW met2 ( 2072230 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 2071150 1580100 ) ( * 1688780 )
-      NEW met2 ( 2911110 16660 ) M2M3_PR
-      NEW met2 ( 2070230 16660 ) M2M3_PR ;
-    - user_irq[2] ( PIN user_irq[2] ) ( mprj irq[2] ) + USE SIGNAL
-      + ROUTED met2 ( 2917090 1700 0 ) ( * 19550 )
-      NEW met1 ( 2273550 19550 ) ( 2917090 * )
-      NEW met2 ( 2074370 1679940 ) ( * 1688780 )
-      NEW met2 ( 2074140 1688780 ) ( 2074370 * )
-      NEW met2 ( 2074140 1688780 ) ( * 1690140 0 )
-      NEW met3 ( 2074370 1679940 ) ( 2273550 * )
-      NEW met2 ( 2273550 19550 ) ( * 1679940 )
-      NEW met1 ( 2917090 19550 ) M1M2_PR
-      NEW met1 ( 2273550 19550 ) M1M2_PR
-      NEW met2 ( 2074370 1679940 ) M2M3_PR
-      NEW met2 ( 2273550 1679940 ) M2M3_PR ;
-    - wb_clk_i ( PIN wb_clk_i ) ( mprj wb_clk_i ) + USE SIGNAL
-      + ROUTED met2 ( 2990 1700 0 ) ( * 30940 )
-      NEW met2 ( 1174150 1688780 ) ( 1175690 * )
-      NEW met2 ( 1175690 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1174150 30940 ) ( * 1688780 )
-      NEW met3 ( 2990 30940 ) ( 1174150 * )
-      NEW met2 ( 2990 30940 ) M2M3_PR
-      NEW met2 ( 1174150 30940 ) M2M3_PR ;
-    - wb_rst_i ( PIN wb_rst_i ) ( mprj wb_rst_i ) + USE SIGNAL
-      + ROUTED met2 ( 8510 1700 0 ) ( * 30770 )
-      NEW met1 ( 1173690 1688950 ) ( 1177070 * )
-      NEW met2 ( 1177070 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1173690 30770 ) ( * 1688950 )
-      NEW met1 ( 8510 30770 ) ( 1173690 * )
-      NEW met1 ( 8510 30770 ) M1M2_PR
-      NEW met1 ( 1173690 30770 ) M1M2_PR
-      NEW met1 ( 1173690 1688950 ) M1M2_PR
-      NEW met1 ( 1177070 1688950 ) M1M2_PR ;
-    - wbs_ack_o ( PIN wbs_ack_o ) ( mprj wbs_ack_o ) + USE SIGNAL
-      + ROUTED met2 ( 14490 1700 0 ) ( * 31110 )
-      NEW met1 ( 1173230 1689290 ) ( 1178910 * )
-      NEW met2 ( 1178910 1689290 ) ( * 1690140 0 )
-      NEW met2 ( 1173230 31110 ) ( * 1689290 )
-      NEW met1 ( 14490 31110 ) ( 1173230 * )
-      NEW met1 ( 14490 31110 ) M1M2_PR
-      NEW met1 ( 1173230 31110 ) M1M2_PR
-      NEW met1 ( 1173230 1689290 ) M1M2_PR
-      NEW met1 ( 1178910 1689290 ) M1M2_PR ;
-    - wbs_adr_i[0] ( PIN wbs_adr_i[0] ) ( mprj wbs_adr_i[0] ) + USE SIGNAL
-      + ROUTED met1 ( 1180590 1652570 ) ( 1186110 * )
-      NEW met2 ( 1180590 31450 ) ( * 1652570 )
-      NEW met2 ( 1186110 1688780 ) ( 1186270 * )
-      NEW met2 ( 1186270 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1186110 1652570 ) ( * 1688780 )
-      NEW met2 ( 38410 1700 0 ) ( * 31450 )
-      NEW met1 ( 38410 31450 ) ( 1180590 * )
-      NEW met1 ( 1180590 31450 ) M1M2_PR
-      NEW met1 ( 1180590 1652570 ) M1M2_PR
-      NEW met1 ( 1186110 1652570 ) M1M2_PR
-      NEW met1 ( 38410 31450 ) M1M2_PR ;
-    - wbs_adr_i[10] ( PIN wbs_adr_i[10] ) ( mprj wbs_adr_i[10] ) + USE SIGNAL
-      + ROUTED met1 ( 1242690 1652570 ) ( 1248210 * )
-      NEW met2 ( 1242690 32130 ) ( * 1652570 )
-      NEW met2 ( 1248210 1688780 ) ( 1248370 * )
-      NEW met2 ( 1248370 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1248210 1652570 ) ( * 1688780 )
-      NEW met2 ( 239430 1700 0 ) ( * 32130 )
-      NEW met1 ( 239430 32130 ) ( 1242690 * )
-      NEW met1 ( 1242690 32130 ) M1M2_PR
-      NEW met1 ( 1242690 1652570 ) M1M2_PR
-      NEW met1 ( 1248210 1652570 ) M1M2_PR
-      NEW met1 ( 239430 32130 ) M1M2_PR ;
-    - wbs_adr_i[11] ( PIN wbs_adr_i[11] ) ( mprj wbs_adr_i[11] ) + USE SIGNAL
-      + ROUTED met1 ( 1249130 1688950 ) ( 1253890 * )
-      NEW met2 ( 1253890 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1249130 32470 ) ( * 1688950 )
-      NEW met2 ( 256910 1700 0 ) ( * 32470 )
-      NEW met1 ( 256910 32470 ) ( 1249130 * )
-      NEW met1 ( 1249130 32470 ) M1M2_PR
-      NEW met1 ( 1249130 1688950 ) M1M2_PR
-      NEW met1 ( 1253890 1688950 ) M1M2_PR
-      NEW met1 ( 256910 32470 ) M1M2_PR ;
-    - wbs_adr_i[12] ( PIN wbs_adr_i[12] ) ( mprj wbs_adr_i[12] ) + USE SIGNAL
-      + ROUTED met2 ( 1256030 1689290 ) ( 1256490 * )
-      NEW met1 ( 1256490 1689290 ) ( 1259410 * )
-      NEW met2 ( 1259410 1689290 ) ( * 1690140 0 )
-      NEW met2 ( 1256030 32810 ) ( * 1689290 )
-      NEW met2 ( 274850 1700 0 ) ( * 32810 )
-      NEW met1 ( 274850 32810 ) ( 1256030 * )
-      NEW met1 ( 1256030 32810 ) M1M2_PR
-      NEW met1 ( 1256490 1689290 ) M1M2_PR
-      NEW met1 ( 1259410 1689290 ) M1M2_PR
-      NEW met1 ( 274850 32810 ) M1M2_PR ;
-    - wbs_adr_i[13] ( PIN wbs_adr_i[13] ) ( mprj wbs_adr_i[13] ) + USE SIGNAL
-      + ROUTED met2 ( 292330 1700 0 ) ( * 33150 )
-      NEW met1 ( 1262930 1688270 ) ( 1264930 * )
-      NEW met1 ( 1264930 1688270 ) ( * 1689290 )
-      NEW met2 ( 1264930 1689290 ) ( * 1690140 0 )
-      NEW met2 ( 1262930 33150 ) ( * 1688270 )
-      NEW met1 ( 292330 33150 ) ( 1262930 * )
-      NEW met1 ( 292330 33150 ) M1M2_PR
-      NEW met1 ( 1262930 33150 ) M1M2_PR
-      NEW met1 ( 1262930 1688270 ) M1M2_PR
-      NEW met1 ( 1264930 1689290 ) M1M2_PR ;
-    - wbs_adr_i[14] ( PIN wbs_adr_i[14] ) ( mprj wbs_adr_i[14] ) + USE SIGNAL
-      + ROUTED met2 ( 310270 1700 0 ) ( * 33490 )
-      NEW met2 ( 1269830 1688780 ) ( 1270450 * )
-      NEW met2 ( 1270450 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1269830 33490 ) ( * 1688780 )
-      NEW met1 ( 310270 33490 ) ( 1269830 * )
-      NEW met1 ( 310270 33490 ) M1M2_PR
-      NEW met1 ( 1269830 33490 ) M1M2_PR ;
-    - wbs_adr_i[15] ( PIN wbs_adr_i[15] ) ( mprj wbs_adr_i[15] ) + USE SIGNAL
-      + ROUTED met1 ( 1270290 1652570 ) ( 1275810 * )
-      NEW met2 ( 1270290 33830 ) ( * 1652570 )
-      NEW met2 ( 1275810 1688780 ) ( 1275970 * )
-      NEW met2 ( 1275970 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1275810 1652570 ) ( * 1688780 )
-      NEW met2 ( 327750 1700 0 ) ( * 33830 )
-      NEW met1 ( 327750 33830 ) ( 1270290 * )
-      NEW met1 ( 1270290 33830 ) M1M2_PR
-      NEW met1 ( 1270290 1652570 ) M1M2_PR
-      NEW met1 ( 1275810 1652570 ) M1M2_PR
-      NEW met1 ( 327750 33830 ) M1M2_PR ;
-    - wbs_adr_i[16] ( PIN wbs_adr_i[16] ) ( mprj wbs_adr_i[16] ) + USE SIGNAL
-      + ROUTED met1 ( 1276730 1688950 ) ( 1281490 * )
-      NEW met2 ( 1281490 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1276730 34170 ) ( * 1688950 )
-      NEW met2 ( 345690 1700 0 ) ( * 34170 )
-      NEW met1 ( 345690 34170 ) ( 1276730 * )
-      NEW met1 ( 1276730 34170 ) M1M2_PR
-      NEW met1 ( 1276730 1688950 ) M1M2_PR
-      NEW met1 ( 1281490 1688950 ) M1M2_PR
-      NEW met1 ( 345690 34170 ) M1M2_PR ;
-    - wbs_adr_i[17] ( PIN wbs_adr_i[17] ) ( mprj wbs_adr_i[17] ) + USE SIGNAL
-      + ROUTED met1 ( 1283630 1688950 ) ( 1287010 * )
-      NEW met2 ( 1287010 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1283630 46410 ) ( * 1688950 )
-      NEW met2 ( 363170 1700 0 ) ( * 46410 )
-      NEW met1 ( 363170 46410 ) ( 1283630 * )
-      NEW met1 ( 1283630 46410 ) M1M2_PR
-      NEW met1 ( 1283630 1688950 ) M1M2_PR
-      NEW met1 ( 1287010 1688950 ) M1M2_PR
-      NEW met1 ( 363170 46410 ) M1M2_PR ;
-    - wbs_adr_i[18] ( PIN wbs_adr_i[18] ) ( mprj wbs_adr_i[18] ) + USE SIGNAL
-      + ROUTED met2 ( 381110 1700 0 ) ( * 46750 )
-      NEW met1 ( 381110 46750 ) ( 1291910 * )
-      NEW met2 ( 1291910 1688780 ) ( 1292530 * )
-      NEW met2 ( 1292530 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1291910 46750 ) ( * 1688780 )
-      NEW met1 ( 381110 46750 ) M1M2_PR
-      NEW met1 ( 1291910 46750 ) M1M2_PR ;
-    - wbs_adr_i[19] ( PIN wbs_adr_i[19] ) ( mprj wbs_adr_i[19] ) + USE SIGNAL
-      + ROUTED met2 ( 396290 1700 ) ( 398590 * 0 )
-      NEW met2 ( 396290 1700 ) ( * 51340 )
-      NEW met3 ( 396290 51340 ) ( 1297890 * )
-      NEW met2 ( 1297660 1688780 ) ( 1297890 * )
-      NEW met2 ( 1297660 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1297890 51340 ) ( * 1688780 )
-      NEW met2 ( 396290 51340 ) M2M3_PR
-      NEW met2 ( 1297890 51340 ) M2M3_PR ;
-    - wbs_adr_i[1] ( PIN wbs_adr_i[1] ) ( mprj wbs_adr_i[1] ) + USE SIGNAL
-      + ROUTED met1 ( 1188410 1652570 ) ( 1193470 * )
-      NEW met2 ( 1188410 31790 ) ( * 1652570 )
-      NEW met2 ( 1193470 1689290 ) ( 1193630 * )
-      NEW met2 ( 1193630 1689290 ) ( * 1690140 0 )
-      NEW met2 ( 1193470 1652570 ) ( * 1689290 )
-      NEW met2 ( 61870 1700 0 ) ( * 31790 )
-      NEW met1 ( 61870 31790 ) ( 1188410 * )
-      NEW met1 ( 1188410 31790 ) M1M2_PR
-      NEW met1 ( 1188410 1652570 ) M1M2_PR
-      NEW met1 ( 1193470 1652570 ) M1M2_PR
-      NEW met1 ( 61870 31790 ) M1M2_PR ;
-    - wbs_adr_i[20] ( PIN wbs_adr_i[20] ) ( mprj wbs_adr_i[20] ) + USE SIGNAL
-      + ROUTED met2 ( 416530 1700 0 ) ( * 51510 )
-      NEW met1 ( 416530 51510 ) ( 1298810 * )
-      NEW met2 ( 1298810 51510 ) ( * 1676700 )
-      NEW met2 ( 1298810 1676700 ) ( 1300190 * )
-      NEW met2 ( 1300190 1676700 ) ( * 1688780 )
-      NEW met2 ( 1300190 1688780 ) ( 1303110 * )
-      NEW met2 ( 1303110 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 416530 51510 ) M1M2_PR
-      NEW met1 ( 1298810 51510 ) M1M2_PR ;
-    - wbs_adr_i[21] ( PIN wbs_adr_i[21] ) ( mprj wbs_adr_i[21] ) + USE SIGNAL
-      + ROUTED met2 ( 432170 1700 ) ( 434470 * 0 )
-      NEW met2 ( 432170 1700 ) ( * 51850 )
-      NEW met1 ( 432170 51850 ) ( 1305710 * )
-      NEW met2 ( 1305710 51850 ) ( * 1580100 )
-      NEW met2 ( 1305710 1580100 ) ( 1307090 * )
-      NEW met2 ( 1307090 1688780 ) ( 1308630 * )
-      NEW met2 ( 1308630 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1307090 1580100 ) ( * 1688780 )
-      NEW met1 ( 432170 51850 ) M1M2_PR
-      NEW met1 ( 1305710 51850 ) M1M2_PR ;
-    - wbs_adr_i[22] ( PIN wbs_adr_i[22] ) ( mprj wbs_adr_i[22] ) + USE SIGNAL
-      + ROUTED met2 ( 449650 1700 ) ( 451950 * 0 )
-      NEW met2 ( 449650 1700 ) ( * 52190 )
-      NEW met1 ( 449650 52190 ) ( 1312150 * )
-      NEW met1 ( 1312150 1688270 ) ( * 1689290 )
-      NEW met1 ( 1312150 1689290 ) ( 1314150 * )
-      NEW met2 ( 1314150 1689290 ) ( * 1690140 0 )
-      NEW met2 ( 1312150 52190 ) ( * 1688270 )
-      NEW met1 ( 449650 52190 ) M1M2_PR
-      NEW met1 ( 1312150 52190 ) M1M2_PR
-      NEW met1 ( 1312150 1688270 ) M1M2_PR
-      NEW met1 ( 1314150 1689290 ) M1M2_PR ;
-    - wbs_adr_i[23] ( PIN wbs_adr_i[23] ) ( mprj wbs_adr_i[23] ) + USE SIGNAL
-      + ROUTED met2 ( 469890 1700 0 ) ( * 66470 )
-      NEW met1 ( 469890 66470 ) ( 1318590 * )
-      NEW met2 ( 1318590 1688780 ) ( 1319670 * )
-      NEW met2 ( 1319670 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1318590 66470 ) ( * 1688780 )
-      NEW met1 ( 469890 66470 ) M1M2_PR
-      NEW met1 ( 1318590 66470 ) M1M2_PR ;
-    - wbs_adr_i[24] ( PIN wbs_adr_i[24] ) ( mprj wbs_adr_i[24] ) + USE SIGNAL
-      + ROUTED met2 ( 487370 1700 0 ) ( * 66810 )
-      NEW met1 ( 487370 66810 ) ( 1325490 * )
-      NEW met2 ( 1325260 1688780 ) ( 1325490 * )
-      NEW met2 ( 1325260 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1325490 66810 ) ( * 1688780 )
-      NEW met1 ( 487370 66810 ) M1M2_PR
-      NEW met1 ( 1325490 66810 ) M1M2_PR ;
-    - wbs_adr_i[25] ( PIN wbs_adr_i[25] ) ( mprj wbs_adr_i[25] ) + USE SIGNAL
-      + ROUTED met2 ( 503930 1700 ) ( 505310 * 0 )
-      NEW met2 ( 503930 1700 ) ( * 67150 )
-      NEW met1 ( 1326410 1636250 ) ( 1330550 * )
-      NEW met1 ( 503930 67150 ) ( 1326410 * )
-      NEW met2 ( 1326410 67150 ) ( * 1636250 )
-      NEW met2 ( 1330550 1688780 ) ( 1330710 * )
-      NEW met2 ( 1330710 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1330550 1636250 ) ( * 1688780 )
-      NEW met1 ( 503930 67150 ) M1M2_PR
-      NEW met1 ( 1326410 1636250 ) M1M2_PR
-      NEW met1 ( 1330550 1636250 ) M1M2_PR
-      NEW met1 ( 1326410 67150 ) M1M2_PR ;
-    - wbs_adr_i[26] ( PIN wbs_adr_i[26] ) ( mprj wbs_adr_i[26] ) + USE SIGNAL
-      + ROUTED met2 ( 520490 1700 ) ( 522790 * 0 )
-      NEW met2 ( 520490 1700 ) ( * 67490 )
-      NEW met1 ( 520490 67490 ) ( 1332390 * )
-      NEW met2 ( 1332390 67490 ) ( * 1676700 )
-      NEW met2 ( 1331930 1676700 ) ( 1332390 * )
-      NEW met2 ( 1331930 1676700 ) ( * 1689290 )
-      NEW met1 ( 1331930 1689290 ) ( 1336230 * )
-      NEW met2 ( 1336230 1689290 ) ( * 1690140 0 )
-      NEW met1 ( 520490 67490 ) M1M2_PR
-      NEW met1 ( 1332390 67490 ) M1M2_PR
-      NEW met1 ( 1331930 1689290 ) M1M2_PR
-      NEW met1 ( 1336230 1689290 ) M1M2_PR ;
-    - wbs_adr_i[27] ( PIN wbs_adr_i[27] ) ( mprj wbs_adr_i[27] ) + USE SIGNAL
-      + ROUTED met2 ( 1339750 1688780 ) ( 1341750 * )
-      NEW met2 ( 1341750 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1339750 67830 ) ( * 1688780 )
-      NEW met2 ( 540730 1700 0 ) ( * 67830 )
-      NEW met1 ( 540730 67830 ) ( 1339750 * )
-      NEW met1 ( 1339750 67830 ) M1M2_PR
-      NEW met1 ( 540730 67830 ) M1M2_PR ;
-    - wbs_adr_i[28] ( PIN wbs_adr_i[28] ) ( mprj wbs_adr_i[28] ) + USE SIGNAL
-      + ROUTED met2 ( 1346190 1688780 ) ( 1347270 * )
-      NEW met2 ( 1347270 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1346190 68170 ) ( * 1688780 )
-      NEW met2 ( 558210 1700 0 ) ( * 16490 )
-      NEW met1 ( 552230 16490 ) ( 558210 * )
-      NEW met2 ( 552230 16490 ) ( * 68170 )
-      NEW met1 ( 552230 68170 ) ( 1346190 * )
-      NEW met1 ( 1346190 68170 ) M1M2_PR
-      NEW met1 ( 558210 16490 ) M1M2_PR
-      NEW met1 ( 552230 16490 ) M1M2_PR
-      NEW met1 ( 552230 68170 ) M1M2_PR ;
-    - wbs_adr_i[29] ( PIN wbs_adr_i[29] ) ( mprj wbs_adr_i[29] ) + USE SIGNAL
-      + ROUTED met2 ( 573850 1700 ) ( 576150 * 0 )
-      NEW met2 ( 573850 1700 ) ( * 68510 )
-      NEW met2 ( 1352860 1688780 ) ( 1353090 * )
-      NEW met2 ( 1352860 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1353090 68510 ) ( * 1688780 )
-      NEW met1 ( 573850 68510 ) ( 1353090 * )
-      NEW met1 ( 573850 68510 ) M1M2_PR
-      NEW met1 ( 1353090 68510 ) M1M2_PR ;
-    - wbs_adr_i[2] ( PIN wbs_adr_i[2] ) ( mprj wbs_adr_i[2] ) + USE SIGNAL
-      + ROUTED met2 ( 85330 1700 0 ) ( * 44540 )
-      NEW met3 ( 85330 44540 ) ( 1201290 * )
-      NEW met2 ( 1201060 1688780 ) ( 1201290 * )
-      NEW met2 ( 1201060 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1201290 44540 ) ( * 1688780 )
-      NEW met2 ( 85330 44540 ) M2M3_PR
-      NEW met2 ( 1201290 44540 ) M2M3_PR ;
-    - wbs_adr_i[30] ( PIN wbs_adr_i[30] ) ( mprj wbs_adr_i[30] ) + USE SIGNAL
-      + ROUTED met2 ( 594090 1700 0 ) ( * 68850 )
-      NEW met2 ( 1354010 68850 ) ( * 1580100 )
-      NEW met2 ( 1354010 1580100 ) ( 1357230 * )
-      NEW met2 ( 1357230 1688780 ) ( 1357850 * )
-      NEW met2 ( 1357850 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1357230 1580100 ) ( * 1688780 )
-      NEW met1 ( 594090 68850 ) ( 1354010 * )
-      NEW met1 ( 594090 68850 ) M1M2_PR
-      NEW met1 ( 1354010 68850 ) M1M2_PR ;
-    - wbs_adr_i[31] ( PIN wbs_adr_i[31] ) ( mprj wbs_adr_i[31] ) + USE SIGNAL
-      + ROUTED met2 ( 611570 1700 0 ) ( * 65110 )
-      NEW met2 ( 1360910 65110 ) ( * 1580100 )
-      NEW met2 ( 1360910 1580100 ) ( 1362750 * )
-      NEW met2 ( 1362750 1688780 ) ( 1363370 * )
-      NEW met2 ( 1363370 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1362750 1580100 ) ( * 1688780 )
-      NEW met1 ( 611570 65110 ) ( 1360910 * )
-      NEW met1 ( 611570 65110 ) M1M2_PR
-      NEW met1 ( 1360910 65110 ) M1M2_PR ;
-    - wbs_adr_i[3] ( PIN wbs_adr_i[3] ) ( mprj wbs_adr_i[3] ) + USE SIGNAL
-      + ROUTED met2 ( 109250 1700 0 ) ( * 45050 )
-      NEW met1 ( 109250 45050 ) ( 1208650 * )
-      NEW met2 ( 1208420 1688780 ) ( 1208650 * )
-      NEW met2 ( 1208420 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1208650 45050 ) ( * 1688780 )
-      NEW met1 ( 109250 45050 ) M1M2_PR
-      NEW met1 ( 1208650 45050 ) M1M2_PR ;
-    - wbs_adr_i[4] ( PIN wbs_adr_i[4] ) ( mprj wbs_adr_i[4] ) + USE SIGNAL
-      + ROUTED met2 ( 132710 1700 0 ) ( * 45390 )
-      NEW met1 ( 132710 45390 ) ( 1215550 * )
-      NEW met2 ( 1215550 1688780 ) ( 1215710 * )
-      NEW met2 ( 1215710 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1215550 45390 ) ( * 1688780 )
-      NEW met1 ( 132710 45390 ) M1M2_PR
-      NEW met1 ( 1215550 45390 ) M1M2_PR ;
-    - wbs_adr_i[5] ( PIN wbs_adr_i[5] ) ( mprj wbs_adr_i[5] ) + USE SIGNAL
-      + ROUTED met2 ( 150650 1700 0 ) ( * 45730 )
-      NEW met1 ( 150650 45730 ) ( 1215090 * )
-      NEW met1 ( 1215090 1689630 ) ( 1221230 * )
-      NEW met2 ( 1221230 1689630 ) ( * 1690140 0 )
-      NEW met2 ( 1215090 45730 ) ( * 1689630 )
-      NEW met1 ( 150650 45730 ) M1M2_PR
-      NEW met1 ( 1215090 45730 ) M1M2_PR
-      NEW met1 ( 1215090 1689630 ) M1M2_PR
-      NEW met1 ( 1221230 1689630 ) M1M2_PR ;
-    - wbs_adr_i[6] ( PIN wbs_adr_i[6] ) ( mprj wbs_adr_i[6] ) + USE SIGNAL
-      + ROUTED met2 ( 168130 1700 0 ) ( * 46070 )
-      NEW met1 ( 168130 46070 ) ( 1221990 * )
-      NEW met1 ( 1221990 1689290 ) ( 1226750 * )
-      NEW met2 ( 1226750 1689290 ) ( * 1690140 0 )
-      NEW met2 ( 1221990 46070 ) ( * 1689290 )
-      NEW met1 ( 168130 46070 ) M1M2_PR
-      NEW met1 ( 1221990 46070 ) M1M2_PR
-      NEW met1 ( 1221990 1689290 ) M1M2_PR
-      NEW met1 ( 1226750 1689290 ) M1M2_PR ;
-    - wbs_adr_i[7] ( PIN wbs_adr_i[7] ) ( mprj wbs_adr_i[7] ) + USE SIGNAL
-      + ROUTED met2 ( 183770 1700 ) ( 186070 * 0 )
-      NEW met2 ( 183770 1700 ) ( * 59330 )
-      NEW met1 ( 183770 59330 ) ( 1229810 * )
-      NEW met2 ( 1229810 59330 ) ( * 1580100 )
-      NEW met2 ( 1229810 1580100 ) ( 1231190 * )
-      NEW met2 ( 1231190 1688780 ) ( 1232270 * )
-      NEW met2 ( 1232270 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1231190 1580100 ) ( * 1688780 )
-      NEW met1 ( 183770 59330 ) M1M2_PR
-      NEW met1 ( 1229810 59330 ) M1M2_PR ;
-    - wbs_adr_i[8] ( PIN wbs_adr_i[8] ) ( mprj wbs_adr_i[8] ) + USE SIGNAL
-      + ROUTED met2 ( 201250 1700 ) ( 203550 * 0 )
-      NEW met2 ( 201250 1700 ) ( * 64940 )
-      NEW met3 ( 201250 64940 ) ( 1235790 * )
-      NEW met2 ( 1235790 1688780 ) ( 1237330 * )
-      NEW met2 ( 1237330 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1235790 64940 ) ( * 1688780 )
-      NEW met2 ( 201250 64940 ) M2M3_PR
-      NEW met2 ( 1235790 64940 ) M2M3_PR ;
-    - wbs_adr_i[9] ( PIN wbs_adr_i[9] ) ( mprj wbs_adr_i[9] ) + USE SIGNAL
-      + ROUTED met2 ( 221490 1700 0 ) ( * 65450 )
-      NEW met2 ( 1242920 1688780 ) ( 1243150 * )
-      NEW met2 ( 1242920 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1243150 65450 ) ( * 1688780 )
-      NEW met1 ( 221490 65450 ) ( 1243150 * )
-      NEW met1 ( 221490 65450 ) M1M2_PR
-      NEW met1 ( 1243150 65450 ) M1M2_PR ;
-    - wbs_cyc_i ( PIN wbs_cyc_i ) ( mprj wbs_cyc_i ) + USE SIGNAL
-      + ROUTED met2 ( 20470 1700 0 ) ( * 44710 )
-      NEW met2 ( 1180820 1688780 ) ( 1181050 * )
-      NEW met2 ( 1180820 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1181050 44710 ) ( * 1688780 )
-      NEW met1 ( 20470 44710 ) ( 1181050 * )
-      NEW met1 ( 20470 44710 ) M1M2_PR
-      NEW met1 ( 1181050 44710 ) M1M2_PR ;
-    - wbs_dat_i[0] ( PIN wbs_dat_i[0] ) ( mprj wbs_dat_i[0] ) + USE SIGNAL
-      + ROUTED met2 ( 1187490 1688780 ) ( 1188110 * )
-      NEW met2 ( 1188110 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1187490 58140 ) ( * 1688780 )
-      NEW met2 ( 43930 1700 0 ) ( * 58140 )
-      NEW met3 ( 43930 58140 ) ( 1187490 * )
-      NEW met2 ( 1187490 58140 ) M2M3_PR
-      NEW met2 ( 43930 58140 ) M2M3_PR ;
-    - wbs_dat_i[10] ( PIN wbs_dat_i[10] ) ( mprj wbs_dat_i[10] ) + USE SIGNAL
-      + ROUTED met2 ( 1250050 1688780 ) ( 1250210 * )
-      NEW met2 ( 1250210 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1250050 65790 ) ( * 1688780 )
-      NEW met2 ( 242650 1700 ) ( 244950 * 0 )
-      NEW met2 ( 242650 1700 ) ( * 65790 )
-      NEW met1 ( 242650 65790 ) ( 1250050 * )
-      NEW met1 ( 1250050 65790 ) M1M2_PR
-      NEW met1 ( 242650 65790 ) M1M2_PR ;
-    - wbs_dat_i[11] ( PIN wbs_dat_i[11] ) ( mprj wbs_dat_i[11] ) + USE SIGNAL
-      + ROUTED met1 ( 1249590 1652570 ) ( 1255570 * )
-      NEW met2 ( 1249590 66130 ) ( * 1652570 )
-      NEW met2 ( 1255570 1688780 ) ( 1255730 * )
-      NEW met2 ( 1255730 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1255570 1652570 ) ( * 1688780 )
-      NEW met2 ( 262890 1700 0 ) ( * 66130 )
-      NEW met1 ( 262890 66130 ) ( 1249590 * )
-      NEW met1 ( 1249590 1652570 ) M1M2_PR
-      NEW met1 ( 1255570 1652570 ) M1M2_PR
-      NEW met1 ( 1249590 66130 ) M1M2_PR
-      NEW met1 ( 262890 66130 ) M1M2_PR ;
-    - wbs_dat_i[12] ( PIN wbs_dat_i[12] ) ( mprj wbs_dat_i[12] ) + USE SIGNAL
-      + ROUTED met2 ( 276230 82800 ) ( * 94690 )
-      NEW met2 ( 276230 82800 ) ( 280370 * )
-      NEW met2 ( 280370 1700 0 ) ( * 82800 )
-      NEW met2 ( 1256950 94690 ) ( * 1580100 )
-      NEW met2 ( 1256950 1580100 ) ( 1258330 * )
-      NEW met2 ( 1258330 1688780 ) ( 1261250 * )
-      NEW met2 ( 1261250 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1258330 1580100 ) ( * 1688780 )
-      NEW met1 ( 276230 94690 ) ( 1256950 * )
-      NEW met1 ( 276230 94690 ) M1M2_PR
-      NEW met1 ( 1256950 94690 ) M1M2_PR ;
-    - wbs_dat_i[13] ( PIN wbs_dat_i[13] ) ( mprj wbs_dat_i[13] ) + USE SIGNAL
-      + ROUTED met2 ( 296930 1700 ) ( 298310 * 0 )
-      NEW met2 ( 296930 1700 ) ( * 95370 )
-      NEW met2 ( 1263850 1688780 ) ( 1266770 * )
-      NEW met2 ( 1266770 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1263850 95370 ) ( * 1688780 )
-      NEW met1 ( 296930 95370 ) ( 1263850 * )
-      NEW met1 ( 296930 95370 ) M1M2_PR
-      NEW met1 ( 1263850 95370 ) M1M2_PR ;
-    - wbs_dat_i[14] ( PIN wbs_dat_i[14] ) ( mprj wbs_dat_i[14] ) + USE SIGNAL
-      + ROUTED met2 ( 310730 82800 ) ( * 95710 )
-      NEW met2 ( 310730 82800 ) ( 316250 * )
-      NEW met2 ( 316250 1700 0 ) ( * 82800 )
-      NEW met2 ( 1270750 1688780 ) ( 1272290 * )
-      NEW met2 ( 1272290 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1270750 95710 ) ( * 1688780 )
-      NEW met1 ( 310730 95710 ) ( 1270750 * )
-      NEW met1 ( 310730 95710 ) M1M2_PR
-      NEW met1 ( 1270750 95710 ) M1M2_PR ;
-    - wbs_dat_i[15] ( PIN wbs_dat_i[15] ) ( mprj wbs_dat_i[15] ) + USE SIGNAL
-      + ROUTED met2 ( 1277650 1688780 ) ( 1277810 * )
-      NEW met2 ( 1277810 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1277650 72250 ) ( * 1688780 )
-      NEW met2 ( 333730 1700 0 ) ( * 72250 )
-      NEW met1 ( 333730 72250 ) ( 1277650 * )
-      NEW met1 ( 1277650 72250 ) M1M2_PR
-      NEW met1 ( 333730 72250 ) M1M2_PR ;
-    - wbs_dat_i[16] ( PIN wbs_dat_i[16] ) ( mprj wbs_dat_i[16] ) + USE SIGNAL
-      + ROUTED met1 ( 1277190 1689630 ) ( 1283330 * )
-      NEW met2 ( 1283330 1689630 ) ( * 1690140 0 )
-      NEW met2 ( 1277190 72590 ) ( * 1689630 )
-      NEW met2 ( 349370 1700 ) ( 351670 * 0 )
-      NEW met2 ( 349370 1700 ) ( * 72590 )
-      NEW met1 ( 349370 72590 ) ( 1277190 * )
-      NEW met1 ( 1277190 72590 ) M1M2_PR
-      NEW met1 ( 1277190 1689630 ) M1M2_PR
-      NEW met1 ( 1283330 1689630 ) M1M2_PR
-      NEW met1 ( 349370 72590 ) M1M2_PR ;
-    - wbs_dat_i[17] ( PIN wbs_dat_i[17] ) ( mprj wbs_dat_i[17] ) + USE SIGNAL
-      + ROUTED met1 ( 1284090 1689290 ) ( 1288850 * )
-      NEW met2 ( 1288850 1689290 ) ( * 1690140 0 )
-      NEW met2 ( 1284090 72930 ) ( * 1689290 )
-      NEW met2 ( 366850 1700 ) ( 369150 * 0 )
-      NEW met2 ( 366850 1700 ) ( * 72930 )
-      NEW met1 ( 366850 72930 ) ( 1284090 * )
-      NEW met1 ( 1284090 72930 ) M1M2_PR
-      NEW met1 ( 1284090 1689290 ) M1M2_PR
-      NEW met1 ( 1288850 1689290 ) M1M2_PR
-      NEW met1 ( 366850 72930 ) M1M2_PR ;
-    - wbs_dat_i[18] ( PIN wbs_dat_i[18] ) ( mprj wbs_dat_i[18] ) + USE SIGNAL
-      + ROUTED met2 ( 387090 1700 0 ) ( * 73270 )
-      NEW met1 ( 387090 73270 ) ( 1290990 * )
-      NEW met1 ( 1290990 1684190 ) ( 1294210 * )
-      NEW met2 ( 1294210 1684190 ) ( * 1688780 )
-      NEW met2 ( 1294210 1688780 ) ( 1294370 * )
-      NEW met2 ( 1294370 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1290990 73270 ) ( * 1684190 )
-      NEW met1 ( 387090 73270 ) M1M2_PR
-      NEW met1 ( 1290990 73270 ) M1M2_PR
-      NEW met1 ( 1290990 1684190 ) M1M2_PR
-      NEW met1 ( 1294210 1684190 ) M1M2_PR ;
-    - wbs_dat_i[19] ( PIN wbs_dat_i[19] ) ( mprj wbs_dat_i[19] ) + USE SIGNAL
-      + ROUTED met2 ( 404570 1700 0 ) ( * 73610 )
-      NEW met1 ( 404570 73610 ) ( 1298350 * )
-      NEW met2 ( 1298350 1688780 ) ( 1299430 * )
-      NEW met2 ( 1299430 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1298350 73610 ) ( * 1688780 )
-      NEW met1 ( 404570 73610 ) M1M2_PR
-      NEW met1 ( 1298350 73610 ) M1M2_PR ;
-    - wbs_dat_i[1] ( PIN wbs_dat_i[1] ) ( mprj wbs_dat_i[1] ) + USE SIGNAL
-      + ROUTED met2 ( 67850 1700 0 ) ( * 58650 )
-      NEW met1 ( 67850 58650 ) ( 1194850 * )
-      NEW met2 ( 1194850 1688780 ) ( 1195470 * )
-      NEW met2 ( 1195470 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1194850 58650 ) ( * 1688780 )
-      NEW met1 ( 67850 58650 ) M1M2_PR
-      NEW met1 ( 1194850 58650 ) M1M2_PR ;
-    - wbs_dat_i[20] ( PIN wbs_dat_i[20] ) ( mprj wbs_dat_i[20] ) + USE SIGNAL
-      + ROUTED met2 ( 421130 1700 ) ( 422510 * 0 )
-      NEW met2 ( 421130 1700 ) ( * 73950 )
-      NEW met1 ( 421130 73950 ) ( 1305250 * )
-      NEW met2 ( 1305020 1688780 ) ( 1305250 * )
-      NEW met2 ( 1305020 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1305250 73950 ) ( * 1688780 )
-      NEW met1 ( 421130 73950 ) M1M2_PR
-      NEW met1 ( 1305250 73950 ) M1M2_PR ;
-    - wbs_dat_i[21] ( PIN wbs_dat_i[21] ) ( mprj wbs_dat_i[21] ) + USE SIGNAL
-      + ROUTED met2 ( 437690 1700 ) ( 439990 * 0 )
-      NEW met1 ( 1304790 1652570 ) ( 1310310 * )
-      NEW met2 ( 437690 1700 ) ( * 74290 )
-      NEW met1 ( 437690 74290 ) ( 1304790 * )
-      NEW met2 ( 1304790 74290 ) ( * 1652570 )
-      NEW met2 ( 1310310 1688780 ) ( 1310470 * )
-      NEW met2 ( 1310470 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1310310 1652570 ) ( * 1688780 )
-      NEW met1 ( 1304790 1652570 ) M1M2_PR
-      NEW met1 ( 1310310 1652570 ) M1M2_PR
-      NEW met1 ( 437690 74290 ) M1M2_PR
-      NEW met1 ( 1304790 74290 ) M1M2_PR ;
-    - wbs_dat_i[22] ( PIN wbs_dat_i[22] ) ( mprj wbs_dat_i[22] ) + USE SIGNAL
-      + ROUTED met2 ( 457930 1700 0 ) ( * 74630 )
-      NEW met1 ( 457930 74630 ) ( 1312610 * )
-      NEW met2 ( 1312610 1688780 ) ( 1315990 * )
-      NEW met2 ( 1315990 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1312610 74630 ) ( * 1688780 )
-      NEW met1 ( 457930 74630 ) M1M2_PR
-      NEW met1 ( 1312610 74630 ) M1M2_PR ;
-    - wbs_dat_i[23] ( PIN wbs_dat_i[23] ) ( mprj wbs_dat_i[23] ) + USE SIGNAL
-      + ROUTED met2 ( 474030 1700 ) ( 475870 * 0 )
-      NEW met2 ( 474030 1700 ) ( * 16830 )
-      NEW met1 ( 469430 16830 ) ( 474030 * )
-      NEW met2 ( 469430 16830 ) ( * 74970 )
-      NEW met1 ( 469430 74970 ) ( 1319050 * )
-      NEW met2 ( 1319050 74970 ) ( * 1580100 )
-      NEW met2 ( 1319050 1580100 ) ( 1320890 * )
-      NEW met2 ( 1320890 1688780 ) ( 1321510 * )
-      NEW met2 ( 1321510 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1320890 1580100 ) ( * 1688780 )
-      NEW met1 ( 474030 16830 ) M1M2_PR
-      NEW met1 ( 469430 16830 ) M1M2_PR
-      NEW met1 ( 469430 74970 ) M1M2_PR
-      NEW met1 ( 1319050 74970 ) M1M2_PR ;
-    - wbs_dat_i[24] ( PIN wbs_dat_i[24] ) ( mprj wbs_dat_i[24] ) + USE SIGNAL
-      + ROUTED met2 ( 491050 1700 ) ( 493350 * 0 )
-      NEW met2 ( 491050 1700 ) ( * 75310 )
-      NEW met1 ( 491050 75310 ) ( 1325950 * )
-      NEW met2 ( 1325950 1688780 ) ( 1327030 * )
-      NEW met2 ( 1327030 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1325950 75310 ) ( * 1688780 )
-      NEW met1 ( 491050 75310 ) M1M2_PR
-      NEW met1 ( 1325950 75310 ) M1M2_PR ;
-    - wbs_dat_i[25] ( PIN wbs_dat_i[25] ) ( mprj wbs_dat_i[25] ) + USE SIGNAL
-      + ROUTED met2 ( 511290 1700 0 ) ( * 75650 )
-      NEW met1 ( 511290 75650 ) ( 1332850 * )
-      NEW met2 ( 1332620 1688780 ) ( 1332850 * )
-      NEW met2 ( 1332620 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1332850 75650 ) ( * 1688780 )
-      NEW met1 ( 511290 75650 ) M1M2_PR
-      NEW met1 ( 1332850 75650 ) M1M2_PR ;
-    - wbs_dat_i[26] ( PIN wbs_dat_i[26] ) ( mprj wbs_dat_i[26] ) + USE SIGNAL
-      + ROUTED met2 ( 528770 1700 0 ) ( * 71910 )
-      NEW met1 ( 528770 71910 ) ( 1333310 * )
-      NEW met1 ( 1333310 1688950 ) ( 1338070 * )
-      NEW met2 ( 1338070 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1333310 71910 ) ( * 1688950 )
-      NEW met1 ( 528770 71910 ) M1M2_PR
-      NEW met1 ( 1333310 71910 ) M1M2_PR
-      NEW met1 ( 1333310 1688950 ) M1M2_PR
-      NEW met1 ( 1338070 1688950 ) M1M2_PR ;
-    - wbs_dat_i[27] ( PIN wbs_dat_i[27] ) ( mprj wbs_dat_i[27] ) + USE SIGNAL
-      + ROUTED met1 ( 1339290 1688950 ) ( 1343590 * )
-      NEW met2 ( 1343590 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1339290 71570 ) ( * 1688950 )
-      NEW met2 ( 545330 1700 ) ( 546710 * 0 )
-      NEW met2 ( 545330 1700 ) ( * 71570 )
-      NEW met1 ( 545330 71570 ) ( 1339290 * )
-      NEW met1 ( 1339290 71570 ) M1M2_PR
-      NEW met1 ( 1339290 1688950 ) M1M2_PR
-      NEW met1 ( 1343590 1688950 ) M1M2_PR
-      NEW met1 ( 545330 71570 ) M1M2_PR ;
-    - wbs_dat_i[28] ( PIN wbs_dat_i[28] ) ( mprj wbs_dat_i[28] ) + USE SIGNAL
-      + ROUTED met2 ( 1346650 1683340 ) ( 1347570 * )
-      NEW met2 ( 1347570 1683340 ) ( * 1688780 )
-      NEW met2 ( 1347570 1688780 ) ( 1349110 * )
-      NEW met2 ( 1349110 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1346650 71230 ) ( * 1683340 )
-      NEW met2 ( 561890 1700 ) ( 564190 * 0 )
-      NEW met2 ( 561890 1700 ) ( * 71230 )
-      NEW met1 ( 561890 71230 ) ( 1346650 * )
-      NEW met1 ( 1346650 71230 ) M1M2_PR
-      NEW met1 ( 561890 71230 ) M1M2_PR ;
-    - wbs_dat_i[29] ( PIN wbs_dat_i[29] ) ( mprj wbs_dat_i[29] ) + USE SIGNAL
-      + ROUTED met2 ( 582130 1700 0 ) ( * 80070 )
-      NEW met2 ( 1353550 1688780 ) ( 1354630 * )
-      NEW met2 ( 1354630 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1353550 80070 ) ( * 1688780 )
-      NEW met1 ( 582130 80070 ) ( 1353550 * )
-      NEW met1 ( 582130 80070 ) M1M2_PR
-      NEW met1 ( 1353550 80070 ) M1M2_PR ;
-    - wbs_dat_i[2] ( PIN wbs_dat_i[2] ) ( mprj wbs_dat_i[2] ) + USE SIGNAL
-      + ROUTED met2 ( 89930 1700 ) ( 91310 * 0 )
-      NEW met2 ( 89930 1700 ) ( * 58990 )
-      NEW met1 ( 89930 58990 ) ( 1201750 * )
-      NEW met2 ( 1201750 1688780 ) ( 1202830 * )
-      NEW met2 ( 1202830 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1201750 58990 ) ( * 1688780 )
-      NEW met1 ( 89930 58990 ) M1M2_PR
-      NEW met1 ( 1201750 58990 ) M1M2_PR ;
-    - wbs_dat_i[30] ( PIN wbs_dat_i[30] ) ( mprj wbs_dat_i[30] ) + USE SIGNAL
-      + ROUTED met2 ( 599610 1700 0 ) ( * 16150 )
-      NEW met1 ( 593630 16150 ) ( 599610 * )
-      NEW met2 ( 593630 16150 ) ( * 80410 )
-      NEW met2 ( 1359760 1688780 ) ( 1360450 * )
-      NEW met2 ( 1359760 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1360450 80410 ) ( * 1688780 )
-      NEW met1 ( 593630 80410 ) ( 1360450 * )
-      NEW met1 ( 599610 16150 ) M1M2_PR
-      NEW met1 ( 593630 16150 ) M1M2_PR
-      NEW met1 ( 593630 80410 ) M1M2_PR
-      NEW met1 ( 1360450 80410 ) M1M2_PR ;
-    - wbs_dat_i[31] ( PIN wbs_dat_i[31] ) ( mprj wbs_dat_i[31] ) + USE SIGNAL
-      + ROUTED met1 ( 1359990 1652570 ) ( 1365050 * )
-      NEW met2 ( 1359990 80750 ) ( * 1652570 )
-      NEW met2 ( 1365050 1688780 ) ( 1365210 * )
-      NEW met2 ( 1365210 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1365050 1652570 ) ( * 1688780 )
-      NEW met2 ( 615250 1700 ) ( 617550 * 0 )
-      NEW met2 ( 615250 1700 ) ( * 80750 )
-      NEW met1 ( 615250 80750 ) ( 1359990 * )
-      NEW met1 ( 1359990 1652570 ) M1M2_PR
-      NEW met1 ( 1365050 1652570 ) M1M2_PR
-      NEW met1 ( 1359990 80750 ) M1M2_PR
-      NEW met1 ( 615250 80750 ) M1M2_PR ;
-    - wbs_dat_i[3] ( PIN wbs_dat_i[3] ) ( mprj wbs_dat_i[3] ) + USE SIGNAL
-      + ROUTED met2 ( 112930 1700 ) ( 115230 * 0 )
-      NEW met2 ( 112930 1700 ) ( * 72420 )
-      NEW met3 ( 112930 72420 ) ( 1209110 * )
-      NEW met2 ( 1209110 1688780 ) ( 1210190 * )
-      NEW met2 ( 1210190 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1209110 72420 ) ( * 1688780 )
-      NEW met2 ( 112930 72420 ) M2M3_PR
-      NEW met2 ( 1209110 72420 ) M2M3_PR ;
-    - wbs_dat_i[4] ( PIN wbs_dat_i[4] ) ( mprj wbs_dat_i[4] ) + USE SIGNAL
-      + ROUTED met2 ( 138690 1700 0 ) ( * 79220 )
-      NEW met3 ( 138690 79220 ) ( 1216010 * )
-      NEW met2 ( 1216010 1688780 ) ( 1217550 * )
-      NEW met2 ( 1217550 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1216010 79220 ) ( * 1688780 )
-      NEW met2 ( 138690 79220 ) M2M3_PR
-      NEW met2 ( 1216010 79220 ) M2M3_PR ;
-    - wbs_dat_i[5] ( PIN wbs_dat_i[5] ) ( mprj wbs_dat_i[5] ) + USE SIGNAL
-      + ROUTED met2 ( 154330 1700 ) ( 156630 * 0 )
-      NEW met2 ( 154330 1700 ) ( * 79390 )
-      NEW met1 ( 154330 79390 ) ( 1222450 * )
-      NEW met2 ( 1222450 1688780 ) ( 1223070 * )
-      NEW met2 ( 1223070 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1222450 79390 ) ( * 1688780 )
-      NEW met1 ( 154330 79390 ) M1M2_PR
-      NEW met1 ( 1222450 79390 ) M1M2_PR ;
-    - wbs_dat_i[6] ( PIN wbs_dat_i[6] ) ( mprj wbs_dat_i[6] ) + USE SIGNAL
-      + ROUTED met2 ( 172730 1700 ) ( 174110 * 0 )
-      NEW met2 ( 172730 1700 ) ( * 79730 )
-      NEW met1 ( 172730 79730 ) ( 1228890 * )
-      NEW met2 ( 1228660 1688780 ) ( 1228890 * )
-      NEW met2 ( 1228660 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1228890 79730 ) ( * 1688780 )
-      NEW met1 ( 172730 79730 ) M1M2_PR
-      NEW met1 ( 1228890 79730 ) M1M2_PR ;
-    - wbs_dat_i[7] ( PIN wbs_dat_i[7] ) ( mprj wbs_dat_i[7] ) + USE SIGNAL
-      + ROUTED met2 ( 186530 82800 ) ( * 92990 )
-      NEW met2 ( 186530 82800 ) ( 192050 * )
-      NEW met2 ( 192050 1700 0 ) ( * 82800 )
-      NEW met1 ( 186530 92990 ) ( 1229350 * )
-      NEW met1 ( 1229350 1688950 ) ( 1234110 * )
-      NEW met2 ( 1234110 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1229350 92990 ) ( * 1688950 )
-      NEW met1 ( 186530 92990 ) M1M2_PR
-      NEW met1 ( 1229350 92990 ) M1M2_PR
-      NEW met1 ( 1229350 1688950 ) M1M2_PR
-      NEW met1 ( 1234110 1688950 ) M1M2_PR ;
-    - wbs_dat_i[8] ( PIN wbs_dat_i[8] ) ( mprj wbs_dat_i[8] ) + USE SIGNAL
-      + ROUTED met2 ( 207230 82800 ) ( * 93330 )
-      NEW met2 ( 207230 82800 ) ( 209530 * )
-      NEW met2 ( 209530 1700 0 ) ( * 82800 )
-      NEW met1 ( 207230 93330 ) ( 1236250 * )
-      NEW met2 ( 1236250 93330 ) ( * 1676700 )
-      NEW met2 ( 1236250 1676700 ) ( 1237630 * )
-      NEW met2 ( 1237630 1676700 ) ( * 1688780 )
-      NEW met2 ( 1237630 1688780 ) ( 1239170 * )
-      NEW met2 ( 1239170 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 207230 93330 ) M1M2_PR
-      NEW met1 ( 1236250 93330 ) M1M2_PR ;
-    - wbs_dat_i[9] ( PIN wbs_dat_i[9] ) ( mprj wbs_dat_i[9] ) + USE SIGNAL
-      + ROUTED met2 ( 225630 1700 ) ( 227470 * 0 )
-      NEW met2 ( 225630 1700 ) ( * 16830 )
-      NEW met1 ( 221030 16830 ) ( 225630 * )
-      NEW met2 ( 221030 16830 ) ( * 93670 )
-      NEW met2 ( 1243610 1688780 ) ( 1244690 * )
-      NEW met2 ( 1244690 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1243610 93670 ) ( * 1688780 )
-      NEW met1 ( 221030 93670 ) ( 1243610 * )
-      NEW met1 ( 225630 16830 ) M1M2_PR
-      NEW met1 ( 221030 16830 ) M1M2_PR
-      NEW met1 ( 221030 93670 ) M1M2_PR
-      NEW met1 ( 1243610 93670 ) M1M2_PR ;
-    - wbs_dat_o[0] ( PIN wbs_dat_o[0] ) ( mprj wbs_dat_o[0] ) + USE SIGNAL
-      + ROUTED met2 ( 1187950 92820 ) ( * 1676700 )
-      NEW met2 ( 1187950 1676700 ) ( 1188410 * )
-      NEW met2 ( 1188410 1676700 ) ( * 1688780 )
-      NEW met2 ( 1188410 1688780 ) ( 1189950 * )
-      NEW met2 ( 1189950 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 48530 1700 ) ( 49910 * 0 )
-      NEW met3 ( 48530 92820 ) ( 1187950 * )
-      NEW met2 ( 48530 1700 ) ( * 92820 )
-      NEW met2 ( 1187950 92820 ) M2M3_PR
-      NEW met2 ( 48530 92820 ) M2M3_PR ;
-    - wbs_dat_o[10] ( PIN wbs_dat_o[10] ) ( mprj wbs_dat_o[10] ) + USE SIGNAL
-      + ROUTED met2 ( 1250510 1688780 ) ( 1252050 * )
-      NEW met2 ( 1252050 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1250510 94010 ) ( * 1688780 )
-      NEW met1 ( 248630 94010 ) ( 1250510 * )
-      NEW met2 ( 248630 82800 ) ( * 94010 )
-      NEW met2 ( 248630 82800 ) ( 250930 * )
-      NEW met2 ( 250930 1700 0 ) ( * 82800 )
-      NEW met1 ( 1250510 94010 ) M1M2_PR
-      NEW met1 ( 248630 94010 ) M1M2_PR ;
-    - wbs_dat_o[11] ( PIN wbs_dat_o[11] ) ( mprj wbs_dat_o[11] ) + USE SIGNAL
-      + ROUTED met2 ( 1256490 1688780 ) ( 1257570 * )
-      NEW met2 ( 1257570 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1256490 94350 ) ( * 1688780 )
-      NEW met2 ( 267030 1700 ) ( 268870 * 0 )
-      NEW met2 ( 267030 1700 ) ( * 16830 )
-      NEW met1 ( 262430 16830 ) ( 267030 * )
-      NEW met1 ( 262430 94350 ) ( 1256490 * )
-      NEW met2 ( 262430 16830 ) ( * 94350 )
-      NEW met1 ( 1256490 94350 ) M1M2_PR
-      NEW met1 ( 267030 16830 ) M1M2_PR
-      NEW met1 ( 262430 16830 ) M1M2_PR
-      NEW met1 ( 262430 94350 ) M1M2_PR ;
-    - wbs_dat_o[12] ( PIN wbs_dat_o[12] ) ( mprj wbs_dat_o[12] ) + USE SIGNAL
-      + ROUTED met2 ( 284050 1700 ) ( 286350 * 0 )
-      NEW met2 ( 283130 82800 ) ( * 95030 )
-      NEW met2 ( 283130 82800 ) ( 284050 * )
-      NEW met2 ( 284050 1700 ) ( * 82800 )
-      NEW met2 ( 1263160 1688780 ) ( 1263390 * )
-      NEW met2 ( 1263160 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1263390 95030 ) ( * 1688780 )
-      NEW met1 ( 283130 95030 ) ( 1263390 * )
-      NEW met1 ( 283130 95030 ) M1M2_PR
-      NEW met1 ( 1263390 95030 ) M1M2_PR ;
-    - wbs_dat_o[13] ( PIN wbs_dat_o[13] ) ( mprj wbs_dat_o[13] ) + USE SIGNAL
-      + ROUTED met2 ( 303830 82800 ) ( * 99790 )
-      NEW met2 ( 303830 82800 ) ( 304290 * )
-      NEW met2 ( 304290 1700 0 ) ( * 82800 )
-      NEW met2 ( 1264310 99790 ) ( * 1580100 )
-      NEW met2 ( 1264310 1580100 ) ( 1267990 * )
-      NEW met2 ( 1267990 1688780 ) ( 1268610 * )
-      NEW met2 ( 1268610 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1267990 1580100 ) ( * 1688780 )
-      NEW met1 ( 303830 99790 ) ( 1264310 * )
-      NEW met1 ( 303830 99790 ) M1M2_PR
-      NEW met1 ( 1264310 99790 ) M1M2_PR ;
-    - wbs_dat_o[14] ( PIN wbs_dat_o[14] ) ( mprj wbs_dat_o[14] ) + USE SIGNAL
-      + ROUTED met2 ( 317630 82800 ) ( * 100130 )
-      NEW met2 ( 317630 82800 ) ( 321770 * )
-      NEW met2 ( 321770 1700 0 ) ( * 82800 )
-      NEW met2 ( 1271210 100130 ) ( * 1580100 )
-      NEW met2 ( 1271210 1580100 ) ( 1273510 * )
-      NEW met2 ( 1273510 1688780 ) ( 1274130 * )
-      NEW met2 ( 1274130 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1273510 1580100 ) ( * 1688780 )
-      NEW met1 ( 317630 100130 ) ( 1271210 * )
-      NEW met1 ( 317630 100130 ) M1M2_PR
-      NEW met1 ( 1271210 100130 ) M1M2_PR ;
-    - wbs_dat_o[15] ( PIN wbs_dat_o[15] ) ( mprj wbs_dat_o[15] ) + USE SIGNAL
-      + ROUTED met2 ( 1278110 1688780 ) ( 1279650 * )
-      NEW met2 ( 1279650 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1278110 100470 ) ( * 1688780 )
-      NEW met2 ( 338330 1700 ) ( 339710 * 0 )
-      NEW met1 ( 338330 100470 ) ( 1278110 * )
-      NEW met2 ( 338330 1700 ) ( * 100470 )
-      NEW met1 ( 1278110 100470 ) M1M2_PR
-      NEW met1 ( 338330 100470 ) M1M2_PR ;
-    - wbs_dat_o[16] ( PIN wbs_dat_o[16] ) ( mprj wbs_dat_o[16] ) + USE SIGNAL
-      + ROUTED met2 ( 1284550 1688780 ) ( 1285170 * )
-      NEW met2 ( 1285170 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1284550 100810 ) ( * 1688780 )
-      NEW met1 ( 352130 100810 ) ( 1284550 * )
-      NEW met2 ( 352130 82800 ) ( * 100810 )
-      NEW met2 ( 352130 82800 ) ( 357650 * )
-      NEW met2 ( 357650 1700 0 ) ( * 82800 )
-      NEW met1 ( 1284550 100810 ) M1M2_PR
-      NEW met1 ( 352130 100810 ) M1M2_PR ;
-    - wbs_dat_o[17] ( PIN wbs_dat_o[17] ) ( mprj wbs_dat_o[17] ) + USE SIGNAL
-      + ROUTED met2 ( 375130 1700 0 ) ( * 24990 )
-      NEW met1 ( 375130 24990 ) ( 727950 * )
-      NEW met2 ( 727950 24990 ) ( * 1681810 )
-      NEW met2 ( 1290530 1681810 ) ( * 1688780 )
-      NEW met2 ( 1290530 1688780 ) ( 1290690 * )
-      NEW met2 ( 1290690 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 727950 1681810 ) ( 1290530 * )
-      NEW met1 ( 375130 24990 ) M1M2_PR
-      NEW met1 ( 727950 24990 ) M1M2_PR
-      NEW met1 ( 727950 1681810 ) M1M2_PR
-      NEW met1 ( 1290530 1681810 ) M1M2_PR ;
-    - wbs_dat_o[18] ( PIN wbs_dat_o[18] ) ( mprj wbs_dat_o[18] ) + USE SIGNAL
-      + ROUTED met2 ( 391230 1700 ) ( 393070 * 0 )
-      NEW met2 ( 391230 1700 ) ( * 16830 )
-      NEW met1 ( 386630 16830 ) ( 391230 * )
-      NEW met2 ( 386630 16830 ) ( * 101150 )
-      NEW met1 ( 386630 101150 ) ( 1291450 * )
-      NEW met1 ( 1291450 1688950 ) ( 1295750 * )
-      NEW met2 ( 1295750 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1291450 101150 ) ( * 1688950 )
-      NEW met1 ( 391230 16830 ) M1M2_PR
-      NEW met1 ( 386630 16830 ) M1M2_PR
-      NEW met1 ( 386630 101150 ) M1M2_PR
-      NEW met1 ( 1291450 101150 ) M1M2_PR
-      NEW met1 ( 1291450 1688950 ) M1M2_PR
-      NEW met1 ( 1295750 1688950 ) M1M2_PR ;
-    - wbs_dat_o[19] ( PIN wbs_dat_o[19] ) ( mprj wbs_dat_o[19] ) + USE SIGNAL
-      + ROUTED met2 ( 410550 1700 0 ) ( * 26690 )
-      NEW met1 ( 410550 26690 ) ( 748650 * )
-      NEW met2 ( 748650 26690 ) ( * 1682150 )
-      NEW met2 ( 1299730 1682150 ) ( * 1689290 )
-      NEW met2 ( 1299730 1689290 ) ( 1301270 * )
-      NEW met2 ( 1301270 1689290 ) ( * 1690140 0 )
-      NEW met1 ( 748650 1682150 ) ( 1299730 * )
-      NEW met1 ( 410550 26690 ) M1M2_PR
-      NEW met1 ( 748650 26690 ) M1M2_PR
-      NEW met1 ( 748650 1682150 ) M1M2_PR
-      NEW met1 ( 1299730 1682150 ) M1M2_PR ;
-    - wbs_dat_o[1] ( PIN wbs_dat_o[1] ) ( mprj wbs_dat_o[1] ) + USE SIGNAL
-      + ROUTED met2 ( 73830 1700 0 ) ( * 17510 )
-      NEW met1 ( 73830 17510 ) ( 1193930 * )
-      NEW met1 ( 1193930 1688950 ) ( 1197310 * )
-      NEW met2 ( 1197310 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1193930 17510 ) ( * 1688950 )
-      NEW met1 ( 73830 17510 ) M1M2_PR
-      NEW met1 ( 1193930 17510 ) M1M2_PR
-      NEW met1 ( 1193930 1688950 ) M1M2_PR
-      NEW met1 ( 1197310 1688950 ) M1M2_PR ;
-    - wbs_dat_o[20] ( PIN wbs_dat_o[20] ) ( mprj wbs_dat_o[20] ) + USE SIGNAL
-      + ROUTED met2 ( 769350 27030 ) ( * 1682490 )
-      NEW met2 ( 428490 1700 0 ) ( * 27030 )
-      NEW met1 ( 428490 27030 ) ( 769350 * )
-      NEW met2 ( 1306630 1682490 ) ( * 1688780 )
-      NEW met2 ( 1306630 1688780 ) ( 1306790 * )
-      NEW met2 ( 1306790 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 769350 1682490 ) ( 1306630 * )
-      NEW met1 ( 769350 27030 ) M1M2_PR
-      NEW met1 ( 769350 1682490 ) M1M2_PR
-      NEW met1 ( 428490 27030 ) M1M2_PR
-      NEW met1 ( 1306630 1682490 ) M1M2_PR ;
-    - wbs_dat_o[21] ( PIN wbs_dat_o[21] ) ( mprj wbs_dat_o[21] ) + USE SIGNAL
-      + ROUTED met2 ( 445970 1700 0 ) ( * 16660 )
-      NEW met3 ( 445970 16660 ) ( 1311690 * )
-      NEW met2 ( 1311690 1688780 ) ( 1312310 * )
-      NEW met2 ( 1312310 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1311690 16660 ) ( * 1688780 )
-      NEW met2 ( 445970 16660 ) M2M3_PR
-      NEW met2 ( 1311690 16660 ) M2M3_PR ;
-    - wbs_dat_o[22] ( PIN wbs_dat_o[22] ) ( mprj wbs_dat_o[22] ) + USE SIGNAL
-      + ROUTED met2 ( 463910 1700 0 ) ( * 24650 )
-      NEW met1 ( 463910 24650 ) ( 817650 * )
-      NEW met2 ( 817650 24650 ) ( * 1682830 )
-      NEW met2 ( 1317670 1682830 ) ( * 1689290 )
-      NEW met2 ( 1317670 1689290 ) ( 1317830 * )
-      NEW met2 ( 1317830 1689290 ) ( * 1690140 0 )
-      NEW met1 ( 817650 1682830 ) ( 1317670 * )
-      NEW met1 ( 463910 24650 ) M1M2_PR
-      NEW met1 ( 817650 24650 ) M1M2_PR
-      NEW met1 ( 817650 1682830 ) M1M2_PR
-      NEW met1 ( 1317670 1682830 ) M1M2_PR ;
-    - wbs_dat_o[23] ( PIN wbs_dat_o[23] ) ( mprj wbs_dat_o[23] ) + USE SIGNAL
-      + ROUTED met2 ( 481390 1700 0 ) ( * 20570 )
-      NEW met1 ( 481390 20570 ) ( 1318130 * )
-      NEW met1 ( 1318130 1688950 ) ( 1323350 * )
-      NEW met2 ( 1323350 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1318130 20570 ) ( * 1688950 )
-      NEW met1 ( 481390 20570 ) M1M2_PR
-      NEW met1 ( 1318130 20570 ) M1M2_PR
-      NEW met1 ( 1318130 1688950 ) M1M2_PR
-      NEW met1 ( 1323350 1688950 ) M1M2_PR ;
-    - wbs_dat_o[24] ( PIN wbs_dat_o[24] ) ( mprj wbs_dat_o[24] ) + USE SIGNAL
-      + ROUTED met2 ( 499330 1700 0 ) ( * 26350 )
-      NEW met1 ( 499330 26350 ) ( 838350 * )
-      NEW met2 ( 838350 26350 ) ( * 1683170 )
-      NEW met1 ( 1290690 1683170 ) ( * 1683510 )
-      NEW met1 ( 1290690 1683510 ) ( 1294670 * )
-      NEW met1 ( 1294670 1683170 ) ( * 1683510 )
-      NEW met1 ( 1294670 1683170 ) ( 1328710 * )
-      NEW met2 ( 1328710 1683170 ) ( * 1688780 )
-      NEW met2 ( 1328710 1688780 ) ( 1328870 * )
-      NEW met2 ( 1328870 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 838350 1683170 ) ( 1290690 * )
-      NEW met1 ( 499330 26350 ) M1M2_PR
-      NEW met1 ( 838350 26350 ) M1M2_PR
-      NEW met1 ( 838350 1683170 ) M1M2_PR
-      NEW met1 ( 1328710 1683170 ) M1M2_PR ;
-    - wbs_dat_o[25] ( PIN wbs_dat_o[25] ) ( mprj wbs_dat_o[25] ) + USE SIGNAL
-      + ROUTED met2 ( 516810 1700 0 ) ( * 16830 )
-      NEW met2 ( 1183350 16830 ) ( * 1678410 )
-      NEW met1 ( 516810 16830 ) ( 1183350 * )
-      NEW met2 ( 1334230 1678410 ) ( * 1689290 )
-      NEW met2 ( 1334230 1689290 ) ( 1334390 * )
-      NEW met2 ( 1334390 1689290 ) ( * 1690140 0 )
-      NEW met1 ( 1183350 1678410 ) ( 1334230 * )
-      NEW met1 ( 516810 16830 ) M1M2_PR
-      NEW met1 ( 1183350 16830 ) M1M2_PR
-      NEW met1 ( 1183350 1678410 ) M1M2_PR
-      NEW met1 ( 1334230 1678410 ) M1M2_PR ;
-    - wbs_dat_o[26] ( PIN wbs_dat_o[26] ) ( mprj wbs_dat_o[26] ) + USE SIGNAL
-      + ROUTED met2 ( 1190250 16490 ) ( * 1678070 )
-      NEW met2 ( 1338830 1678070 ) ( * 1689460 )
-      NEW met2 ( 1338830 1689460 ) ( 1339910 * )
-      NEW met2 ( 1339910 1689460 ) ( * 1690140 0 )
-      NEW met2 ( 534750 1700 0 ) ( * 16150 )
-      NEW met1 ( 534750 16150 ) ( 565800 * )
-      NEW met1 ( 565800 16150 ) ( * 16490 )
-      NEW met1 ( 565800 16490 ) ( 1190250 * )
-      NEW met1 ( 1190250 1678070 ) ( 1338830 * )
-      NEW met1 ( 1190250 16490 ) M1M2_PR
-      NEW met1 ( 1190250 1678070 ) M1M2_PR
-      NEW met1 ( 1338830 1678070 ) M1M2_PR
-      NEW met1 ( 534750 16150 ) M1M2_PR ;
-    - wbs_dat_o[27] ( PIN wbs_dat_o[27] ) ( mprj wbs_dat_o[27] ) + USE SIGNAL
-      + ROUTED met2 ( 886650 27370 ) ( * 1683510 )
-      NEW met2 ( 1345270 1683510 ) ( * 1688780 )
-      NEW met2 ( 1345270 1688780 ) ( 1345430 * )
-      NEW met2 ( 1345430 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 552690 1700 0 ) ( * 27370 )
-      NEW met1 ( 552690 27370 ) ( 886650 * )
-      NEW met1 ( 886650 1683510 ) ( 1290300 * )
-      NEW met1 ( 1290300 1683510 ) ( * 1683850 )
-      NEW met1 ( 1290300 1683850 ) ( 1295130 * )
-      NEW met1 ( 1295130 1683510 ) ( * 1683850 )
-      NEW met1 ( 1295130 1683510 ) ( 1345270 * )
-      NEW met1 ( 886650 27370 ) M1M2_PR
-      NEW met1 ( 886650 1683510 ) M1M2_PR
-      NEW met1 ( 1345270 1683510 ) M1M2_PR
-      NEW met1 ( 552690 27370 ) M1M2_PR ;
-    - wbs_dat_o[28] ( PIN wbs_dat_o[28] ) ( mprj wbs_dat_o[28] ) + USE SIGNAL
-      + ROUTED met2 ( 570170 1700 0 ) ( * 15810 )
-      NEW met2 ( 1350790 1677390 ) ( * 1688780 )
-      NEW met2 ( 1350790 1688780 ) ( 1350950 * )
-      NEW met2 ( 1350950 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 570170 15810 ) ( 614100 * )
-      NEW met1 ( 614100 15810 ) ( * 16150 )
-      NEW met1 ( 614100 16150 ) ( 1204050 * )
-      NEW met2 ( 1204050 16150 ) ( * 1677390 )
-      NEW met1 ( 1204050 1677390 ) ( 1350790 * )
-      NEW met1 ( 570170 15810 ) M1M2_PR
-      NEW met1 ( 1350790 1677390 ) M1M2_PR
-      NEW met1 ( 1204050 16150 ) M1M2_PR
-      NEW met1 ( 1204050 1677390 ) M1M2_PR ;
-    - wbs_dat_o[29] ( PIN wbs_dat_o[29] ) ( mprj wbs_dat_o[29] ) + USE SIGNAL
-      + ROUTED met2 ( 588110 1700 0 ) ( * 25670 )
-      NEW met2 ( 1355850 1679770 ) ( * 1688780 )
-      NEW met2 ( 1355850 1688780 ) ( 1356010 * )
-      NEW met2 ( 1356010 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 588110 25670 ) ( 928050 * )
-      NEW met2 ( 928050 25670 ) ( * 1679770 )
-      NEW met1 ( 928050 1679770 ) ( 1355850 * )
-      NEW met1 ( 588110 25670 ) M1M2_PR
-      NEW met1 ( 1355850 1679770 ) M1M2_PR
-      NEW met1 ( 928050 25670 ) M1M2_PR
-      NEW met1 ( 928050 1679770 ) M1M2_PR ;
-    - wbs_dat_o[2] ( PIN wbs_dat_o[2] ) ( mprj wbs_dat_o[2] ) + USE SIGNAL
-      + ROUTED met2 ( 97290 1700 0 ) ( * 18190 )
-      NEW met1 ( 97290 18190 ) ( 1202210 * )
-      NEW met2 ( 1202210 18190 ) ( * 1580100 )
-      NEW met2 ( 1202210 1580100 ) ( 1203590 * )
-      NEW met2 ( 1203590 1688780 ) ( 1204670 * )
-      NEW met2 ( 1204670 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1203590 1580100 ) ( * 1688780 )
-      NEW met1 ( 97290 18190 ) M1M2_PR
-      NEW met1 ( 1202210 18190 ) M1M2_PR ;
-    - wbs_dat_o[30] ( PIN wbs_dat_o[30] ) ( mprj wbs_dat_o[30] ) + USE SIGNAL
-      + ROUTED met2 ( 605590 1700 0 ) ( * 25330 )
-      NEW met2 ( 1361370 1679430 ) ( * 1688780 )
-      NEW met2 ( 1361370 1688780 ) ( 1361530 * )
-      NEW met2 ( 1361530 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 605590 25330 ) ( 941850 * )
-      NEW met2 ( 941850 25330 ) ( * 1679430 )
-      NEW met1 ( 941850 1679430 ) ( 1361370 * )
-      NEW met1 ( 605590 25330 ) M1M2_PR
-      NEW met1 ( 1361370 1679430 ) M1M2_PR
-      NEW met1 ( 941850 25330 ) M1M2_PR
-      NEW met1 ( 941850 1679430 ) M1M2_PR ;
-    - wbs_dat_o[31] ( PIN wbs_dat_o[31] ) ( mprj wbs_dat_o[31] ) + USE SIGNAL
-      + ROUTED met2 ( 969450 26010 ) ( * 1679090 )
-      NEW met2 ( 1366890 1679090 ) ( * 1689460 )
-      NEW met2 ( 1366890 1689460 ) ( 1367050 * )
-      NEW met2 ( 1367050 1689460 ) ( * 1690140 0 )
-      NEW met2 ( 623530 1700 0 ) ( * 26010 )
-      NEW met1 ( 623530 26010 ) ( 969450 * )
-      NEW met1 ( 969450 1679090 ) ( 1366890 * )
-      NEW met1 ( 969450 26010 ) M1M2_PR
-      NEW met1 ( 969450 1679090 ) M1M2_PR
-      NEW met1 ( 1366890 1679090 ) M1M2_PR
-      NEW met1 ( 623530 26010 ) M1M2_PR ;
-    - wbs_dat_o[3] ( PIN wbs_dat_o[3] ) ( mprj wbs_dat_o[3] ) + USE SIGNAL
-      + ROUTED met2 ( 121210 1700 0 ) ( * 18530 )
-      NEW met1 ( 121210 18530 ) ( 1208190 * )
-      NEW met1 ( 1208190 1652570 ) ( 1211870 * )
-      NEW met2 ( 1208190 18530 ) ( * 1652570 )
-      NEW met2 ( 1211870 1688780 ) ( 1212030 * )
-      NEW met2 ( 1212030 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1211870 1652570 ) ( * 1688780 )
-      NEW met1 ( 121210 18530 ) M1M2_PR
-      NEW met1 ( 1208190 18530 ) M1M2_PR
-      NEW met1 ( 1208190 1652570 ) M1M2_PR
-      NEW met1 ( 1211870 1652570 ) M1M2_PR ;
-    - wbs_dat_o[4] ( PIN wbs_dat_o[4] ) ( mprj wbs_dat_o[4] ) + USE SIGNAL
-      + ROUTED met2 ( 144670 1700 0 ) ( * 19210 )
-      NEW met1 ( 144670 19210 ) ( 1214630 * )
-      NEW met1 ( 1214630 1688950 ) ( 1219390 * )
-      NEW met2 ( 1219390 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1214630 19210 ) ( * 1688950 )
-      NEW met1 ( 144670 19210 ) M1M2_PR
-      NEW met1 ( 1214630 19210 ) M1M2_PR
-      NEW met1 ( 1214630 1688950 ) M1M2_PR
-      NEW met1 ( 1219390 1688950 ) M1M2_PR ;
-    - wbs_dat_o[5] ( PIN wbs_dat_o[5] ) ( mprj wbs_dat_o[5] ) + USE SIGNAL
-      + ROUTED met2 ( 162150 1700 0 ) ( * 19550 )
-      NEW met1 ( 162150 19550 ) ( 1221530 * )
-      NEW met1 ( 1221530 1688950 ) ( 1224910 * )
-      NEW met2 ( 1224910 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1221530 19550 ) ( * 1688950 )
-      NEW met1 ( 162150 19550 ) M1M2_PR
-      NEW met1 ( 1221530 19550 ) M1M2_PR
-      NEW met1 ( 1221530 1688950 ) M1M2_PR
-      NEW met1 ( 1224910 1688950 ) M1M2_PR ;
-    - wbs_dat_o[6] ( PIN wbs_dat_o[6] ) ( mprj wbs_dat_o[6] ) + USE SIGNAL
-      + ROUTED met2 ( 179630 82800 ) ( 180090 * )
-      NEW met2 ( 180090 1700 0 ) ( * 82800 )
-      NEW met2 ( 179630 82800 ) ( * 1681130 )
-      NEW met2 ( 1230270 1681130 ) ( * 1688780 )
-      NEW met2 ( 1230270 1688780 ) ( 1230430 * )
-      NEW met2 ( 1230430 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 179630 1681130 ) ( 1230270 * )
-      NEW met1 ( 179630 1681130 ) M1M2_PR
-      NEW met1 ( 1230270 1681130 ) M1M2_PR ;
-    - wbs_dat_o[7] ( PIN wbs_dat_o[7] ) ( mprj wbs_dat_o[7] ) + USE SIGNAL
-      + ROUTED met2 ( 198030 1700 0 ) ( * 19890 )
-      NEW met1 ( 198030 19890 ) ( 1236710 * )
-      NEW met1 ( 1235330 1660050 ) ( 1236710 * )
-      NEW met2 ( 1236710 19890 ) ( * 1660050 )
-      NEW met2 ( 1235330 1688780 ) ( 1235490 * )
-      NEW met2 ( 1235490 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1235330 1660050 ) ( * 1688780 )
-      NEW met1 ( 198030 19890 ) M1M2_PR
-      NEW met1 ( 1236710 19890 ) M1M2_PR
-      NEW met1 ( 1235330 1660050 ) M1M2_PR
-      NEW met1 ( 1236710 1660050 ) M1M2_PR ;
-    - wbs_dat_o[8] ( PIN wbs_dat_o[8] ) ( mprj wbs_dat_o[8] ) + USE SIGNAL
-      + ROUTED met2 ( 214130 1700 ) ( 215510 * 0 )
-      NEW met2 ( 214130 1700 ) ( * 1681470 )
-      NEW met2 ( 1240850 1681470 ) ( * 1688780 )
-      NEW met2 ( 1240850 1688780 ) ( 1241010 * )
-      NEW met2 ( 1241010 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 214130 1681470 ) ( 1240850 * )
-      NEW met1 ( 214130 1681470 ) M1M2_PR
-      NEW met1 ( 1240850 1681470 ) M1M2_PR ;
-    - wbs_dat_o[9] ( PIN wbs_dat_o[9] ) ( mprj wbs_dat_o[9] ) + USE SIGNAL
-      + ROUTED met1 ( 1242230 1688950 ) ( 1246530 * )
-      NEW met2 ( 1246530 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1242230 20230 ) ( * 1688950 )
-      NEW met2 ( 233450 1700 0 ) ( * 20230 )
-      NEW met1 ( 233450 20230 ) ( 1242230 * )
-      NEW met1 ( 1242230 20230 ) M1M2_PR
-      NEW met1 ( 1242230 1688950 ) M1M2_PR
-      NEW met1 ( 1246530 1688950 ) M1M2_PR
-      NEW met1 ( 233450 20230 ) M1M2_PR ;
-    - wbs_sel_i[0] ( PIN wbs_sel_i[0] ) ( mprj wbs_sel_i[0] ) + USE SIGNAL
-      + ROUTED met2 ( 1191630 1680450 ) ( * 1688780 )
-      NEW met2 ( 1191630 1688780 ) ( 1191790 * )
-      NEW met2 ( 1191790 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 55430 82800 ) ( 55890 * )
-      NEW met2 ( 55890 1700 0 ) ( * 82800 )
-      NEW met2 ( 55430 82800 ) ( * 1680450 )
-      NEW met1 ( 55430 1680450 ) ( 1191630 * )
-      NEW met1 ( 1191630 1680450 ) M1M2_PR
-      NEW met1 ( 55430 1680450 ) M1M2_PR ;
-    - wbs_sel_i[1] ( PIN wbs_sel_i[1] ) ( mprj wbs_sel_i[1] ) + USE SIGNAL
-      + ROUTED met2 ( 79810 1700 0 ) ( * 17850 )
-      NEW met1 ( 79810 17850 ) ( 1194390 * )
-      NEW met1 ( 1194390 1689290 ) ( 1199150 * )
-      NEW met2 ( 1199150 1689290 ) ( * 1690140 0 )
-      NEW met2 ( 1194390 17850 ) ( * 1689290 )
-      NEW met1 ( 79810 17850 ) M1M2_PR
-      NEW met1 ( 1194390 17850 ) M1M2_PR
-      NEW met1 ( 1194390 1689290 ) M1M2_PR
-      NEW met1 ( 1199150 1689290 ) M1M2_PR ;
-    - wbs_sel_i[2] ( PIN wbs_sel_i[2] ) ( mprj wbs_sel_i[2] ) + USE SIGNAL
-      + ROUTED met2 ( 100970 1700 ) ( 103270 * 0 )
-      NEW met2 ( 96830 82800 ) ( 100970 * )
-      NEW met2 ( 100970 1700 ) ( * 82800 )
-      NEW met2 ( 96830 82800 ) ( * 1680790 )
-      NEW met2 ( 1206350 1680790 ) ( * 1688780 )
-      NEW met2 ( 1206350 1688780 ) ( 1206510 * )
-      NEW met2 ( 1206510 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 96830 1680790 ) ( 1206350 * )
-      NEW met1 ( 96830 1680790 ) M1M2_PR
-      NEW met1 ( 1206350 1680790 ) M1M2_PR ;
-    - wbs_sel_i[3] ( PIN wbs_sel_i[3] ) ( mprj wbs_sel_i[3] ) + USE SIGNAL
-      + ROUTED met2 ( 126730 1700 0 ) ( * 18870 )
-      NEW met1 ( 126730 18870 ) ( 1207730 * )
-      NEW met1 ( 1207730 1688950 ) ( 1213870 * )
-      NEW met2 ( 1213870 1688950 ) ( * 1690140 0 )
-      NEW met2 ( 1207730 18870 ) ( * 1688950 )
-      NEW met1 ( 126730 18870 ) M1M2_PR
-      NEW met1 ( 1207730 18870 ) M1M2_PR
-      NEW met1 ( 1207730 1688950 ) M1M2_PR
-      NEW met1 ( 1213870 1688950 ) M1M2_PR ;
-    - wbs_stb_i ( PIN wbs_stb_i ) ( mprj wbs_stb_i ) + USE SIGNAL
-      + ROUTED met2 ( 20930 82800 ) ( 26450 * )
-      NEW met2 ( 26450 1700 0 ) ( * 82800 )
-      NEW met2 ( 20930 82800 ) ( * 1680110 )
-      NEW met2 ( 1182430 1680110 ) ( * 1688780 )
-      NEW met2 ( 1182430 1688780 ) ( 1182590 * )
-      NEW met2 ( 1182590 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 20930 1680110 ) ( 1182430 * )
-      NEW met1 ( 20930 1680110 ) M1M2_PR
-      NEW met1 ( 1182430 1680110 ) M1M2_PR ;
-    - wbs_we_i ( PIN wbs_we_i ) ( mprj wbs_we_i ) + USE SIGNAL
-      + ROUTED met2 ( 32430 1700 0 ) ( * 17170 )
-      NEW met2 ( 1181510 17170 ) ( * 1580100 )
-      NEW met2 ( 1181510 1580100 ) ( 1182890 * )
-      NEW met2 ( 1182890 1688780 ) ( 1184430 * )
-      NEW met2 ( 1184430 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1182890 1580100 ) ( * 1688780 )
-      NEW met1 ( 32430 17170 ) ( 1181510 * )
-      NEW met1 ( 32430 17170 ) M1M2_PR
-      NEW met1 ( 1181510 17170 ) M1M2_PR ;
-END NETS
 END DESIGN
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index 8c696b9..f7cee8c 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,7 +1,8 @@
-u_qspi_master                2250             650           N
-u_uart_i2c_usb_spi           2250            1350           N
-u_pinmux                     2250            2250           N
-u_pll                        2500            3148           N
+u_4x8bit_dac                 1850            2500            N
+u_qspi_master                2250             450           N
+u_uart_i2c_usb_spi           2250            1100           N
+u_pinmux                     2250            2000           N
+u_pll                        2500            3028           N
 
 u_riscv_top.i_core_top_0    75	      1400 	      N
 u_riscv_top.i_core_top_1    1200	      1400	      FN
diff --git a/openlane/user_project_wrapper/pdn_cfg.tcl b/openlane/user_project_wrapper/pdn_cfg.tcl
index c1e213d..b2a2b42 100644
--- a/openlane/user_project_wrapper/pdn_cfg.tcl
+++ b/openlane/user_project_wrapper/pdn_cfg.tcl
@@ -93,7 +93,7 @@
         -pitch $::env(FP_PDN_VPITCH) \
         -offset $::env(FP_PDN_VOFFSET) \
         -spacing $::env(FP_PDN_VSPACING) \
-	-nets "$::env(VDD_NET) $::env(GND_NET)" \
+	    -nets "$::env(PDN_STRIPE)" \
         -starts_with POWER -extend_to_core_ring
 
     add_pdn_stripe \
@@ -103,7 +103,7 @@
         -pitch $::env(FP_PDN_HPITCH) \
         -offset $::env(FP_PDN_HOFFSET) \
         -spacing $::env(FP_PDN_HSPACING) \
-	-nets "$::env(VDD_NET) $::env(GND_NET)" \
+	-nets "$::env(PDN_STRIPE)" \
         -starts_with POWER -extend_to_core_ring
 
     add_pdn_connect \
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl
index f2b9028..407a338 100755
--- a/openlane/wb_host/config.tcl
+++ b/openlane/wb_host/config.tcl
@@ -85,8 +85,10 @@
 set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
 
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 450 425"
+set ::env(DIE_AREA) "0 0 400 425"
 
+set ::env(GRT_OBS) "                              \
+	                met4  0 0 400 425"
 
 # If you're going to use multiple power domains, then keep this disabled.
 set ::env(RUN_CVC) 0
@@ -111,6 +113,10 @@
 set ::env(RT_MAX_LAYER) {met4}
 #set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
 
+#Lef 
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+
 set ::env(DIODE_INSERTION_STRATEGY) 4
 
 
diff --git a/openlane/wb_host/pin_order.cfg b/openlane/wb_host/pin_order.cfg
index 26c9f8e..8c93e59 100644
--- a/openlane/wb_host/pin_order.cfg
+++ b/openlane/wb_host/pin_order.cfg
@@ -158,51 +158,89 @@
 
 
 #N
-wbd_int_rst_n         0100 0 2
-cfg_clk_ctrl1\[31\]
-cfg_clk_ctrl1\[30\]
-cfg_clk_ctrl1\[29\]
-cfg_clk_ctrl1\[28\]
-cfg_clk_ctrl1\[27\]
-cfg_clk_ctrl1\[26\]
-cfg_clk_ctrl1\[25\]
-cfg_clk_ctrl1\[24\]
-cfg_clk_ctrl1\[23\]
-cfg_clk_ctrl1\[22\]
-cfg_clk_ctrl1\[21\]
-cfg_clk_ctrl1\[20\]
-cfg_clk_ctrl1\[19\]
-cfg_clk_ctrl1\[18\]
-cfg_clk_ctrl1\[17\]
-cfg_clk_ctrl1\[16\]
-cfg_clk_ctrl1\[15\]
-cfg_clk_ctrl1\[14\]
-cfg_clk_ctrl1\[13\]
-cfg_clk_ctrl1\[12\]
-cfg_clk_ctrl1\[11\]
-cfg_clk_ctrl1\[10\]
-cfg_clk_ctrl1\[9\]
-cfg_clk_ctrl1\[8\]
-cfg_clk_ctrl1\[3\]
-cfg_clk_ctrl1\[2\]
-cfg_clk_ctrl1\[1\]
-cfg_clk_ctrl1\[0\]
+cfg_clk_skew_ctrl2\[31\]   0000 0 2 
+cfg_clk_skew_ctrl2\[30\]
+cfg_clk_skew_ctrl2\[29\]
+cfg_clk_skew_ctrl2\[28\]
+cfg_clk_skew_ctrl2\[27\]
+cfg_clk_skew_ctrl2\[26\]
+cfg_clk_skew_ctrl2\[25\]
+cfg_clk_skew_ctrl2\[24\]
+
+cfg_clk_skew_ctrl1\[31\]
+cfg_clk_skew_ctrl1\[30\]
+cfg_clk_skew_ctrl1\[29\]
+cfg_clk_skew_ctrl1\[28\]
+
+cfg_clk_skew_ctrl1\[7\]
+cfg_cska_wh\[3\]
+cfg_clk_skew_ctrl1\[6\]
+cfg_cska_wh\[2\]
+cfg_clk_skew_ctrl1\[5\]
+cfg_cska_wh\[1\]
+cfg_clk_skew_ctrl1\[4\]
+cfg_cska_wh\[0\]
+
+wbd_int_rst_n              0100 0 2
+cfg_clk_skew_ctrl2\[23\]
+cfg_clk_skew_ctrl2\[22\]
+cfg_clk_skew_ctrl2\[21\]
+cfg_clk_skew_ctrl2\[20\]
+cfg_clk_skew_ctrl2\[19\]
+cfg_clk_skew_ctrl2\[18\]
+cfg_clk_skew_ctrl2\[17\]
+cfg_clk_skew_ctrl2\[16\]
+cfg_clk_skew_ctrl2\[15\]
+cfg_clk_skew_ctrl2\[14\]
+cfg_clk_skew_ctrl2\[13\]
+cfg_clk_skew_ctrl2\[12\]
+cfg_clk_skew_ctrl2\[11\]
+cfg_clk_skew_ctrl2\[10\]
+cfg_clk_skew_ctrl2\[9\]
+cfg_clk_skew_ctrl2\[8\]
+cfg_clk_skew_ctrl2\[7\]
+cfg_clk_skew_ctrl2\[6\]
+cfg_clk_skew_ctrl2\[5\]
+cfg_clk_skew_ctrl2\[4\]
+cfg_clk_skew_ctrl2\[3\]
+cfg_clk_skew_ctrl2\[2\]
+cfg_clk_skew_ctrl2\[1\]
+cfg_clk_skew_ctrl2\[0\]
+
+cfg_clk_skew_ctrl1\[27\]
+cfg_clk_skew_ctrl1\[26\]
+cfg_clk_skew_ctrl1\[25\]
+cfg_clk_skew_ctrl1\[24\]
+cfg_clk_skew_ctrl1\[23\]
+cfg_clk_skew_ctrl1\[22\]
+cfg_clk_skew_ctrl1\[21\]
+cfg_clk_skew_ctrl1\[20\]
+cfg_clk_skew_ctrl1\[19\]
+cfg_clk_skew_ctrl1\[18\]
+cfg_clk_skew_ctrl1\[17\]
+cfg_clk_skew_ctrl1\[16\]
+cfg_clk_skew_ctrl1\[15\]
+cfg_clk_skew_ctrl1\[14\]
+cfg_clk_skew_ctrl1\[13\]
+cfg_clk_skew_ctrl1\[12\]
+cfg_clk_skew_ctrl1\[11\]
+cfg_clk_skew_ctrl1\[10\]
+cfg_clk_skew_ctrl1\[9\]
+cfg_clk_skew_ctrl1\[8\]
+
+cfg_clk_skew_ctrl1\[3\]
+cfg_clk_skew_ctrl1\[2\]
+cfg_clk_skew_ctrl1\[1\]
+cfg_clk_skew_ctrl1\[0\]
+
 wbd_clk_int
 wbs_clk_out   
 wbs_clk_i            
 wbd_clk_wh
-cfg_clk_ctrl1\[7\]
-cfg_cska_wh\[3\]
-cfg_clk_ctrl1\[6\]
-cfg_cska_wh\[2\]
-cfg_clk_ctrl1\[5\]
-cfg_cska_wh\[1\]
-cfg_clk_ctrl1\[4\]
-cfg_cska_wh\[0\]
 
 
 
-wbs_stb_o       160 0 2 
+wbs_stb_o       200 0 2 
 wbs_we_o         
 wbs_adr_o\[31\]  
 wbs_adr_o\[30\]  
@@ -309,15 +347,7 @@
 wbs_cyc_o      
 
 
-cfg_strap_pad_ctrl
-e_reset_n
-int_pll_clock
-p_reset_n
-s_reset_n
-xtal_clk
-strap_uartm\[1\]
-strap_uartm\[0\]
-strap_sticky\[31\]
+strap_sticky\[31\] 325 0 2
 strap_sticky\[30\]
 strap_sticky\[29\]
 strap_sticky\[28\]
@@ -349,6 +379,10 @@
 strap_sticky\[2\]
 strap_sticky\[1\]
 strap_sticky\[0\]
+
+strap_uartm\[1\]
+strap_uartm\[0\]
+
 system_strap\[31\]
 system_strap\[30\]
 system_strap\[29\]
@@ -381,3 +415,11 @@
 system_strap\[2\]
 system_strap\[1\]
 system_strap\[0\]
+
+cfg_strap_pad_ctrl  
+e_reset_n
+p_reset_n
+
+int_pll_clock
+xtal_clk
+s_reset_n
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
index 58b9acb..8b7baf5 100755
--- a/openlane/wb_interconnect/config.tcl
+++ b/openlane/wb_interconnect/config.tcl
@@ -52,7 +52,7 @@
 set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
 
 set ::env(SYNTH_PARAMETERS) "CH_CLK_WD=4\
-	                 CH_DATA_WD=53 \
+	                 CH_DATA_WD=146 \
 			 "
 
 set ::env(SYNTH_READ_BLACKBOX_LIB) 1
@@ -73,6 +73,7 @@
 set ::env(FP_SIZING) absolute
 set ::env(DIE_AREA) "0 0 300 1725"
 
+#set ::env(GRT_OBS) "met4  0 0 300 1725"
 
 # If you're going to use multiple power domains, then keep this disabled.
 set ::env(RUN_CVC) 0
@@ -123,6 +124,10 @@
 #set ::env(GLB_RT_MAXLAYER) 5
 set ::env(RT_MAX_LAYER) {met4}
 
+#Lef 
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+
 
 set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
 set ::env(QUIT_ON_MAGIC_DRC) "1"
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg
index 93ca457..46750ad 100644
--- a/openlane/wb_interconnect/pin_order.cfg
+++ b/openlane/wb_interconnect/pin_order.cfg
@@ -4,6 +4,30 @@
 
 #S
 rst_n                000  0 2
+ch_data_in\[43\]
+ch_data_in\[42\]
+ch_data_in\[41\]
+ch_data_in\[40\]
+ch_data_in\[39\]
+ch_data_in\[38\]
+ch_data_in\[37\]
+ch_data_in\[36\]
+ch_data_in\[35\]
+ch_data_in\[34\]
+ch_data_in\[33\]
+ch_data_in\[32\]
+ch_data_in\[31\]
+ch_data_in\[30\]
+ch_data_in\[29\]
+ch_data_in\[28\]
+ch_data_in\[27\]
+ch_data_in\[26\]
+ch_data_in\[25\]
+ch_data_in\[24\]
+ch_data_in\[23\]
+ch_data_in\[22\]
+ch_data_in\[21\]
+ch_data_in\[20\]
 ch_data_in\[19\]
 ch_data_in\[18\]
 ch_data_in\[17\]
@@ -24,10 +48,12 @@
 ch_data_in\[2\]
 ch_data_in\[1\]
 ch_data_in\[0\]
+
 cfg_cska_wi\[3\]     
 cfg_cska_wi\[2\]     
 cfg_cska_wi\[1\]     
 cfg_cska_wi\[0\] 
+
 ch_clk_in\[3\]
 ch_clk_in\[2\]
 ch_clk_in\[1\]
@@ -37,7 +63,7 @@
 clk_i               
 
 
-m0_wbd_stb_i         060 0 2
+m0_wbd_stb_i         100 0 2
 m0_wbd_we_i         
 m0_wbd_adr_i\[31\]  
 m0_wbd_adr_i\[30\]  
@@ -144,44 +170,88 @@
 m0_wbd_err_o        
 m0_wbd_cyc_i        
 
+ch_data_out\[145\]  225 0 2
+ch_data_out\[144\]  
+ch_data_out\[143\]  
+ch_data_out\[142\]  
+ch_data_out\[141\]  
+ch_data_out\[140\]  
+ch_data_out\[139\]  
+ch_data_out\[138\]  
+ch_data_out\[137\]  
+ch_data_out\[136\]  
+ch_data_out\[135\]  
+ch_data_out\[134\]  
+ch_data_out\[133\]  
+ch_data_out\[132\]  
+ch_data_out\[131\]  
+ch_data_out\[130\]  
+ch_data_out\[129\]  
+ch_data_out\[128\]  
+ch_data_out\[127\]  
+ch_data_out\[126\]  
+ch_data_out\[125\]  
+ch_data_out\[124\]  
+ch_data_out\[123\]  
+ch_data_out\[122\]  
+ch_data_out\[121\]  
+ch_data_out\[120\]  
+ch_data_out\[119\]  
+ch_data_out\[118\]  
+ch_data_out\[117\]  
+ch_data_out\[116\]  
+ch_data_out\[115\]  
+ch_data_out\[114\]  
+
+ch_data_out\[113\]  
+ch_data_out\[112\]  
+
+ch_data_in\[111\]  
+ch_data_in\[110\]  
+ch_data_in\[109\]  
+ch_data_in\[108\]  
+ch_data_in\[107\]  
+ch_data_in\[106\]  
+ch_data_in\[105\]  
+ch_data_in\[104\]  
+ch_data_in\[103\]  
+ch_data_in\[102\]  
+ch_data_in\[101\]  
+ch_data_in\[100\]  
+ch_data_in\[99\]  
+ch_data_in\[98\]  
+ch_data_in\[97\]  
+ch_data_in\[96\]  
+ch_data_in\[95\]  
+ch_data_in\[94\]  
+ch_data_in\[93\]  
+ch_data_in\[92\]  
+ch_data_in\[91\]  
+ch_data_in\[90\]  
+ch_data_in\[89\]  
+ch_data_in\[88\]  
+ch_data_in\[87\]  
+ch_data_in\[86\]  
+ch_data_in\[85\]  
+ch_data_in\[84\]  
+ch_data_in\[83\]  
+ch_data_in\[82\]  
+ch_data_in\[81\]  
+ch_data_in\[80\]  
+
+ch_data_in\[79\]  
+ch_data_in\[78\]  
+ch_data_in\[77\]  
+
 
 
 #W
-ch_data_out\[52\]   000 0 2
-ch_data_out\[51\] 
-ch_data_out\[50\] 
-ch_data_out\[49\] 
-ch_data_out\[48\] 
-ch_data_out\[47\] 
-ch_data_out\[46\] 
-ch_data_out\[45\] 
-ch_data_out\[44\] 
-ch_data_out\[43\] 
-ch_data_out\[42\] 
-ch_data_out\[41\] 
-ch_data_out\[40\] 
-ch_data_out\[39\] 
-ch_data_out\[38\] 
-ch_data_out\[37\] 
-ch_data_out\[36\] 
-ch_data_out\[35\] 
-ch_data_out\[34\] 
-ch_data_out\[33\] 
-ch_data_out\[32\] 
-ch_data_out\[31\] 
-ch_data_out\[30\] 
-ch_data_out\[29\] 
-ch_data_out\[28\] 
-ch_data_out\[27\] 
-ch_data_out\[26\] 
-ch_data_out\[25\] 
-ch_data_out\[24\] 
-ch_data_out\[23\] 
+ch_data_out\[23\]   000 0 2
 ch_data_out\[22\] 
 ch_data_out\[21\] 
 ch_data_out\[20\] 
 
-ch_data_out\[3\]   
+ch_data_out\[3\]   050 0 2
 ch_data_out\[2\]
 ch_data_out\[1\]
 ch_data_out\[0\]
@@ -189,6 +259,7 @@
 ch_clk_out\[0\]
 
 m1_wbd_stb_i         100 0 2 
+m1_wbd_cyc_i        
 m1_wbd_we_i         
 m1_wbd_adr_i\[31\]  
 m1_wbd_adr_i\[30\]  
@@ -294,12 +365,12 @@
 m1_wbd_dat_o\[2\]   
 m1_wbd_dat_o\[1\]   
 m1_wbd_dat_o\[0\]   
-m1_wbd_ack_o        
 m1_wbd_lack_o        
+m1_wbd_ack_o        
 m1_wbd_err_o        
-m1_wbd_cyc_i        
 
 m2_wbd_stb_i        300 0 2
+m2_wbd_cyc_i       
 m2_wbd_we_i         
 m2_wbd_adr_i\[31\]  
 m2_wbd_adr_i\[30\]  
@@ -415,9 +486,9 @@
 m2_wbd_ack_o        
 m2_wbd_lack_o        
 m2_wbd_err_o        
-m2_wbd_cyc_i       
 
 m3_wbd_stb_i        500 0 2
+m3_wbd_cyc_i       
 m3_wbd_we_i         
 m3_wbd_adr_i\[31\]  
 m3_wbd_adr_i\[30\]  
@@ -501,8 +572,62 @@
 m3_wbd_ack_o        
 m3_wbd_lack_o        
 m3_wbd_err_o        
-m3_wbd_cyc_i       
 
+ch_data_out\[43\]   650 0 2
+ch_data_out\[42\] 
+ch_data_out\[41\] 
+ch_data_out\[40\] 
+ch_data_out\[39\] 
+ch_data_out\[38\] 
+ch_data_out\[37\] 
+ch_data_out\[36\] 
+ch_data_out\[35\] 
+ch_data_out\[34\] 
+ch_data_out\[33\] 
+ch_data_out\[32\] 
+ch_data_out\[31\] 
+ch_data_out\[30\] 
+ch_data_out\[29\] 
+ch_data_out\[28\] 
+
+ch_data_out\[76\]   1600 0 2
+ch_data_out\[75\] 
+ch_data_out\[74\] 
+ch_data_out\[73\] 
+ch_data_out\[72\] 
+ch_data_out\[71\] 
+ch_data_out\[70\] 
+ch_data_out\[69\] 
+ch_data_out\[68\] 
+ch_data_out\[67\] 
+ch_data_out\[66\] 
+ch_data_out\[65\] 
+ch_data_out\[64\] 
+ch_data_out\[63\] 
+ch_data_out\[62\] 
+ch_data_out\[61\] 
+ch_data_out\[60\] 
+ch_data_out\[59\] 
+ch_data_out\[58\] 
+ch_data_out\[57\] 
+ch_data_out\[56\] 
+ch_data_out\[55\] 
+ch_data_out\[54\] 
+ch_data_out\[53\] 
+ch_data_out\[52\] 
+ch_data_out\[51\] 
+ch_data_out\[50\] 
+ch_data_out\[49\] 
+ch_data_out\[48\] 
+ch_data_out\[47\] 
+ch_data_out\[46\] 
+ch_data_out\[45\] 
+ch_data_out\[44\] 
+
+ch_data_out\[27\] 
+ch_data_out\[26\] 
+ch_data_out\[25\] 
+ch_data_out\[24\] 
 
 #E
 ch_data_out\[19\]   0000 0  2  
@@ -633,13 +758,13 @@
 s0_wbd_cyc_o        
 
 
-ch_data_out\[11\]    0700 0  2  
+ch_data_out\[11\]    0650 0  2  
 ch_data_out\[10\]
 ch_data_out\[9\]
 ch_data_out\[8\]
 ch_clk_out\[2\]
 
-s1_wbd_stb_o          0800 0 2
+s1_wbd_stb_o          0750 0 2
 s1_wbd_we_o         
 s1_wbd_adr_o\[8\]   
 s1_wbd_adr_o\[7\]   
@@ -721,7 +846,106 @@
 s1_wbd_ack_i        
 s1_wbd_cyc_o  
 
-ch_data_in\[52\]  1500 0 2
+
+ch_data_in\[145\]  1350 0 2
+ch_data_in\[144\]  
+ch_data_in\[143\]  
+ch_data_in\[142\]  
+ch_data_in\[141\]  
+ch_data_in\[140\]  
+ch_data_in\[139\]  
+ch_data_in\[138\]  
+ch_data_in\[137\]  
+ch_data_in\[136\]  
+ch_data_in\[135\]  
+ch_data_in\[134\]  
+ch_data_in\[133\]  
+ch_data_in\[132\]  
+ch_data_in\[131\]  
+ch_data_in\[130\]  
+ch_data_in\[129\]  
+ch_data_in\[128\]  
+ch_data_in\[127\]  
+ch_data_in\[126\]  
+ch_data_in\[125\]  
+ch_data_in\[124\]  
+ch_data_in\[123\]  
+ch_data_in\[122\]  
+ch_data_in\[121\]  
+ch_data_in\[120\]  
+ch_data_in\[119\]  
+ch_data_in\[118\]  
+ch_data_in\[117\]  
+ch_data_in\[116\]  
+ch_data_in\[115\]  
+ch_data_in\[114\]  
+
+ch_data_in\[113\]  
+ch_data_in\[112\]  
+
+
+ch_data_out\[111\]  
+ch_data_out\[110\]  
+ch_data_out\[109\]  
+ch_data_out\[108\]  
+ch_data_out\[107\]  
+ch_data_out\[106\]  
+ch_data_out\[105\]  
+ch_data_out\[104\]  
+ch_data_out\[103\]  
+ch_data_out\[102\]  
+ch_data_out\[101\]  
+ch_data_out\[100\]  
+ch_data_out\[99\]  
+ch_data_out\[98\]  
+ch_data_out\[97\]  
+ch_data_out\[96\]  
+ch_data_out\[95\]  
+ch_data_out\[94\]  
+ch_data_out\[93\]  
+ch_data_out\[92\]  
+ch_data_out\[91\]  
+ch_data_out\[90\]  
+ch_data_out\[89\]  
+ch_data_out\[88\]  
+ch_data_out\[87\]  
+ch_data_out\[86\]  
+ch_data_out\[85\]  
+ch_data_out\[84\]  
+ch_data_out\[83\]  
+ch_data_out\[82\]  
+ch_data_out\[81\]  
+ch_data_out\[80\]  
+
+ch_data_out\[79\]  
+ch_data_out\[78\]  
+ch_data_out\[77\]  
+
+ch_data_in\[76\]  1550 0 2
+ch_data_in\[75\]  
+ch_data_in\[74\]  
+ch_data_in\[73\]  
+ch_data_in\[72\]  
+ch_data_in\[71\]  
+ch_data_in\[70\]  
+ch_data_in\[69\]  
+ch_data_in\[68\]  
+ch_data_in\[67\]  
+ch_data_in\[66\]  
+ch_data_in\[65\]  
+ch_data_in\[64\]  
+ch_data_in\[63\]  
+ch_data_in\[62\]  
+ch_data_in\[61\]  
+ch_data_in\[60\]  
+ch_data_in\[59\]  
+ch_data_in\[58\]  
+ch_data_in\[57\]  
+ch_data_in\[56\]  
+ch_data_in\[55\]  
+ch_data_in\[54\]  
+ch_data_in\[53\]  
+ch_data_in\[52\]  
 ch_data_in\[51\]  
 ch_data_in\[50\]  
 ch_data_in\[49\]  
@@ -730,30 +954,6 @@
 ch_data_in\[46\]  
 ch_data_in\[45\]  
 ch_data_in\[44\]  
-ch_data_in\[43\]  
-ch_data_in\[42\]  
-ch_data_in\[41\]  
-ch_data_in\[40\]  
-ch_data_in\[39\]  
-ch_data_in\[38\]  
-ch_data_in\[37\]  
-ch_data_in\[36\]  
-ch_data_in\[35\]
-ch_data_in\[34\]
-ch_data_in\[33\]
-ch_data_in\[32\]
-ch_data_in\[31\]
-ch_data_in\[30\]
-ch_data_in\[29\]
-ch_data_in\[28\]
-ch_data_in\[27\]
-ch_data_in\[26\]
-ch_data_in\[25\]
-ch_data_in\[24\]
-ch_data_in\[23\]
-ch_data_in\[22\]
-ch_data_in\[21\]
-ch_data_in\[20\]
 
 ch_data_out\[15\]    
 ch_data_out\[14\]
@@ -761,7 +961,7 @@
 ch_data_out\[12\]
 ch_clk_out\[3\]
 
-s2_wbd_stb_o         1600 0 2
+s2_wbd_stb_o         1610 0 2
 s2_wbd_we_o         
 s2_wbd_adr_o\[9\]   
 s2_wbd_adr_o\[8\]   
@@ -844,3 +1044,4 @@
 s2_wbd_ack_i        
 s2_wbd_cyc_o        
 
+
diff --git a/openlane/ycr4_iconnect/config.tcl b/openlane/ycr4_iconnect/config.tcl
index d7fb61d..e10ab74 100644
--- a/openlane/ycr4_iconnect/config.tcl
+++ b/openlane/ycr4_iconnect/config.tcl
@@ -34,6 +34,7 @@
 set ::env(LEC_ENABLE) 0
 
 set ::env(VERILOG_FILES) "\
+    $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/lib/clk_skew_adjust.gv                  \
 	$::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/top/ycr4_iconnect.sv                  \
 	$::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/top/ycr4_cross_bar.sv                 \
 	$::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/top/ycr4_router.sv                    \
@@ -60,11 +61,11 @@
 ## Floorplan
 set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 390 1900"
+set ::env(DIE_AREA) "0 0 400 2000"
 
 set ::env(PL_TARGET_DENSITY) 0.20
-#set ::env(CELL_PAD) 2
-#set ::env(GRT_ADJUSTMENT) {0.2}
+#set ::env(CELL_PAD) 8
+set ::env(GRT_ADJUSTMENT) {0.2}
 
 #set ::env(GLB_RT_ADJUSTMENT) {0.2}
 
diff --git a/openlane/ycr4_iconnect/pin_order.cfg b/openlane/ycr4_iconnect/pin_order.cfg
index 6799122..2b289e1 100644
--- a/openlane/ycr4_iconnect/pin_order.cfg
+++ b/openlane/ycr4_iconnect/pin_order.cfg
@@ -1839,6 +1839,12 @@
 core_irq_lines_i\[0\]
 core_irq_soft_i
 
+cfg_ccska\[3\]
+cfg_ccska\[2\]
+cfg_ccska\[1\]
+cfg_ccska\[0\]
+core_clk_int
+core_clk_skew
 core_clk          
 rtc_clk
 pwrup_rst_n
diff --git a/openlane/ycr_core_top/base.sdc b/openlane/ycr_core_top/base.sdc
index 874dabb..70129d1 100644
--- a/openlane/ycr_core_top/base.sdc
+++ b/openlane/ycr_core_top/base.sdc
@@ -13,30 +13,30 @@
 set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
 
 #IMEM Constraints
-set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_cmd_o}]
-set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_req_o}]
-set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_addr_o[*]}]
-set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_bl_o[*]}]
+set_output_delay -max 7.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_cmd_o}]
+set_output_delay -max 7.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_req_o}]
+set_output_delay -max 7.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_addr_o[*]}]
+set_output_delay -max 7.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_bl_o[*]}]
 
 set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_cmd_o}]
 set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_req_o}]
 set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_addr_o[*]}]
 set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_bl_o[*]}]
 
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_req_ack_i}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_rdata_i[*]}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_resp_i[*]}]
+set_input_delay -max 7.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_req_ack_i}]
+set_input_delay -max 7.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_rdata_i[*]}]
+set_input_delay -max 7.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_resp_i[*]}]
 
 set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_req_ack_i}]
 set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_rdata_i[*]}]
 set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_resp_i[*]}]
 
 #DMEM Constraints
-set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_cmd_o}]
-set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_req_o}]
+set_output_delay -max 7.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_cmd_o}]
+set_output_delay -max 7.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_req_o}]
 set_output_delay -max 7.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_addr_o[*]}]
-set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_wdata_o[*]}]
-set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_width_o[*]}]
+set_output_delay -max 7.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_wdata_o[*]}]
+set_output_delay -max 7.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_width_o[*]}]
 
 set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_cmd_o}]
 set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_req_o}]
@@ -44,9 +44,9 @@
 set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_wdata_o[*]}]
 set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_width_o[*]}]
 
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_req_ack_i}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_rdata_i[*]}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_resp_i[*]}]
+set_input_delay -max 7.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_req_ack_i}]
+set_input_delay -max 7.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_rdata_i[*]}]
+set_input_delay -max 7.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_resp_i[*]}]
 
 set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_req_ack_i}]
 set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_rdata_i[*]}]
diff --git a/openlane/ycr_core_top/config.tcl b/openlane/ycr_core_top/config.tcl
index cb42943..d9b5dd5 100644
--- a/openlane/ycr_core_top/config.tcl
+++ b/openlane/ycr_core_top/config.tcl
@@ -33,6 +33,8 @@
 set ::env(LEC_ENABLE) 0
 
 set ::env(VERILOG_FILES) "\
+    $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/lib/clk_skew_adjust.gv                  \
+    $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/lib/ctech_cells.sv                      \
 	$::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_top.sv           \
 	$::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/core/ycr_core_top.sv                    \
 	$::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/core/ycr_dm.sv                          \
@@ -77,7 +79,7 @@
 set ::env(DIE_AREA) "0 0 540 950 "
 
 set ::env(PL_TARGET_DENSITY) 0.45
-set ::env(CELL_PAD) "8"
+#set ::env(CELL_PAD) "8"
 
 ## Routing
 set ::env(GRT_ADJUSTMENT) 0.2
@@ -108,6 +110,10 @@
 
 #Need to cross-check why global timing opimization creating setup vio with hugh hold fix
 set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "1"
+set ::env(GLB_OPTIMIZE_MIRRORING) {1}
+set ::env(PL_OPTIMIZE_MIRRORING) {1}
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) {1}
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) {0}
 
 #PDN
 set ::env(FP_PDN_VPITCH) 100
diff --git a/openlane/ycr_core_top/pin_order.cfg b/openlane/ycr_core_top/pin_order.cfg
index 8fc1648..f3daaa8 100644
--- a/openlane/ycr_core_top/pin_order.cfg
+++ b/openlane/ycr_core_top/pin_order.cfg
@@ -1,6 +1,21 @@
 #BUS_SORT
 #MANUAL_PLACE
 #E
+pwrup_rst_n       
+rst_n
+
+cfg_ccska\[3\]
+cfg_ccska\[2\]
+cfg_ccska\[1\]
+cfg_ccska\[0\]
+core_clk_int
+core_clk_skew
+
+clk
+clk_o
+core_rst_n_o
+core_rdc_qlfy_o
+
 core_uid\[1\]              0200 00 2
 core_uid\[0\]   
 imem2core_req_ack_i
@@ -331,13 +346,3 @@
 core_irq_soft_i
 cpu_rst_n
 
-#S
-pwrup_rst_n       
-rst_n
-
-
-
-clk
-clk_o
-core_rst_n_o
-core_rdc_qlfy_o
diff --git a/openlane/ycr_intf/base.sdc b/openlane/ycr_intf/base.sdc
index db8fbe6..f8eb2c5 100644
--- a/openlane/ycr_intf/base.sdc
+++ b/openlane/ycr_intf/base.sdc
@@ -245,6 +245,9 @@
 puts "\[INFO\]: Setting load to: $cap_load"
 set_load  $cap_load [all_outputs]
 
+set_max_transition 1.00 [current_design]
+set_max_capacitance 0.2 [current_design]
+set_max_fanout 10 [current_design]
 ###############################################################################
 # Design Rules
 ###############################################################################
diff --git a/openlane/ycr_intf/config.tcl b/openlane/ycr_intf/config.tcl
index 4e0c943..72878b2 100644
--- a/openlane/ycr_intf/config.tcl
+++ b/openlane/ycr_intf/config.tcl
@@ -69,17 +69,25 @@
 
 set ::env(PL_TARGET_DENSITY) 0.37
 
-set ::env(FP_IO_VEXTEND) {4}
-set ::env(FP_IO_HEXTEND) {4}
-
-#LVS Issue - DEF Base looks to having issue
-set ::env(MAGIC_EXT_USE_GDS) {1}
+#set ::env(FP_IO_VEXTEND) {6}
+#set ::env(FP_IO_HEXTEND) {6}
 
 set ::env(RT_MAX_LAYER) {met4}
 #set ::env(GLB_RT_MAXLAYER) "5"
 #set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
 set ::env(DIODE_INSERTION_STRATEGY) 3
 
+#LVS Issue - DEF Base looks to having issue
+set ::env(MAGIC_EXT_USE_GDS) {1}
+
+set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5}
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}
+
+set ::env(GLB_RESIZER_MAX_CAP_MARGIN) {0.25}
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) {0.25}
+
+set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {500}
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {500}
 
 set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
 set ::env(QUIT_ON_MAGIC_DRC) "1"
diff --git a/openlane/ycr_intf/pin_order.cfg b/openlane/ycr_intf/pin_order.cfg
index 016df72..cbeff2f 100644
--- a/openlane/ycr_intf/pin_order.cfg
+++ b/openlane/ycr_intf/pin_order.cfg
@@ -391,7 +391,6 @@
 
 wb_rst_n                500 0
 pwrup_rst_n            
-core_clk
 cpu_intf_rst_n      
 
 #W
@@ -528,15 +527,24 @@
 
 
 #E
-cfg_cska_riscv\[3\]     0000 0   2
-cfg_cska_riscv\[2\]
-cfg_cska_riscv\[1\]
-cfg_cska_riscv\[0\]
+cfg_ccska\[3\]     0000 0    2 
+cfg_ccska\[2\]
+cfg_ccska\[1\]
+cfg_ccska\[0\]
+core_clk_int
+core_clk_skew
+core_clk
+
+cfg_wcska\[3\]     0050 0   2
+cfg_wcska\[2\]
+cfg_wcska\[1\]
+cfg_wcska\[0\]
 wbd_clk_int
-wbd_clk_riscv
+wbd_clk_skew
 wb_clk            
 
 wbd_dmem_stb_o         0100 0 2 
+wbd_dmem_cyc_o         
 wbd_dmem_we_o           
 wbd_dmem_adr_o\[31\]    
 wbd_dmem_adr_o\[30\]    
@@ -647,6 +655,7 @@
 wbd_dmem_err_i       
 
 wb_dcache_stb_o       0300 0  2
+wb_dcache_cyc_o       
 wb_dcache_we_o        
 wb_dcache_adr_o\[31\] 
 wb_dcache_adr_o\[30\] 
@@ -762,9 +771,9 @@
 wb_dcache_ack_i      
 wb_dcache_lack_i      
 wb_dcache_err_i      
-wb_dcache_cyc_o       
 
 wb_icache_stb_o       500 0  2
+wb_icache_cyc_o
 wb_icache_we_o        
 wb_icache_adr_o\[31\] 
 wb_icache_adr_o\[30\] 
@@ -848,7 +857,6 @@
 wb_icache_ack_i      
 wb_icache_lack_i      
 wb_icache_err_i      
-wb_icache_cyc_o
 
 cfg_icache_pfet_dis       
 cfg_icache_ntag_pfet_dis
diff --git a/signoff/pinmux_top/OPENLANE_VERSION b/signoff/pinmux_top/OPENLANE_VERSION
index b5bf449..fabca1a 100644
--- a/signoff/pinmux_top/OPENLANE_VERSION
+++ b/signoff/pinmux_top/OPENLANE_VERSION
@@ -1 +1 @@
-openlane b6bacc9d1ab469917fda7ceea61ea3a18984b818
+OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
diff --git a/signoff/pinmux_top/PDK_SOURCES b/signoff/pinmux_top/PDK_SOURCES
index f9d0f46..ef91c87 100644
--- a/signoff/pinmux_top/PDK_SOURCES
+++ b/signoff/pinmux_top/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 44a43c23c81b45b8e774ae7a84899a5a778b6b0b
+open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c
diff --git a/signoff/qspim_top/OPENLANE_VERSION b/signoff/qspim_top/OPENLANE_VERSION
index b5bf449..fabca1a 100644
--- a/signoff/qspim_top/OPENLANE_VERSION
+++ b/signoff/qspim_top/OPENLANE_VERSION
@@ -1 +1 @@
-openlane b6bacc9d1ab469917fda7ceea61ea3a18984b818
+OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
diff --git a/signoff/qspim_top/PDK_SOURCES b/signoff/qspim_top/PDK_SOURCES
index f9d0f46..ef91c87 100644
--- a/signoff/qspim_top/PDK_SOURCES
+++ b/signoff/qspim_top/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 44a43c23c81b45b8e774ae7a84899a5a778b6b0b
+open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c
diff --git a/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION b/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION
index b5bf449..fabca1a 100644
--- a/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION
+++ b/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION
@@ -1 +1 @@
-openlane b6bacc9d1ab469917fda7ceea61ea3a18984b818
+OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
diff --git a/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES b/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES
index f9d0f46..ef91c87 100644
--- a/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES
+++ b/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 44a43c23c81b45b8e774ae7a84899a5a778b6b0b
+open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c
diff --git a/signoff/wb_host/OPENLANE_VERSION b/signoff/wb_host/OPENLANE_VERSION
index b5bf449..fabca1a 100644
--- a/signoff/wb_host/OPENLANE_VERSION
+++ b/signoff/wb_host/OPENLANE_VERSION
@@ -1 +1 @@
-openlane b6bacc9d1ab469917fda7ceea61ea3a18984b818
+OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
diff --git a/signoff/wb_host/PDK_SOURCES b/signoff/wb_host/PDK_SOURCES
index f9d0f46..ef91c87 100644
--- a/signoff/wb_host/PDK_SOURCES
+++ b/signoff/wb_host/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 44a43c23c81b45b8e774ae7a84899a5a778b6b0b
+open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c
diff --git a/signoff/wb_interconnect/OPENLANE_VERSION b/signoff/wb_interconnect/OPENLANE_VERSION
index b5bf449..fabca1a 100644
--- a/signoff/wb_interconnect/OPENLANE_VERSION
+++ b/signoff/wb_interconnect/OPENLANE_VERSION
@@ -1 +1 @@
-openlane b6bacc9d1ab469917fda7ceea61ea3a18984b818
+OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
diff --git a/signoff/wb_interconnect/PDK_SOURCES b/signoff/wb_interconnect/PDK_SOURCES
index f9d0f46..ef91c87 100644
--- a/signoff/wb_interconnect/PDK_SOURCES
+++ b/signoff/wb_interconnect/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 44a43c23c81b45b8e774ae7a84899a5a778b6b0b
+open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c
diff --git a/signoff/ycr4_iconnect/OPENLANE_VERSION b/signoff/ycr4_iconnect/OPENLANE_VERSION
index b5bf449..fabca1a 100644
--- a/signoff/ycr4_iconnect/OPENLANE_VERSION
+++ b/signoff/ycr4_iconnect/OPENLANE_VERSION
@@ -1 +1 @@
-openlane b6bacc9d1ab469917fda7ceea61ea3a18984b818
+OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
diff --git a/signoff/ycr4_iconnect/PDK_SOURCES b/signoff/ycr4_iconnect/PDK_SOURCES
index f9d0f46..ef91c87 100644
--- a/signoff/ycr4_iconnect/PDK_SOURCES
+++ b/signoff/ycr4_iconnect/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 44a43c23c81b45b8e774ae7a84899a5a778b6b0b
+open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c
diff --git a/signoff/ycr_core_top/OPENLANE_VERSION b/signoff/ycr_core_top/OPENLANE_VERSION
index b5bf449..fabca1a 100644
--- a/signoff/ycr_core_top/OPENLANE_VERSION
+++ b/signoff/ycr_core_top/OPENLANE_VERSION
@@ -1 +1 @@
-openlane b6bacc9d1ab469917fda7ceea61ea3a18984b818
+OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
diff --git a/signoff/ycr_core_top/PDK_SOURCES b/signoff/ycr_core_top/PDK_SOURCES
index f9d0f46..ef91c87 100644
--- a/signoff/ycr_core_top/PDK_SOURCES
+++ b/signoff/ycr_core_top/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 44a43c23c81b45b8e774ae7a84899a5a778b6b0b
+open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c
diff --git a/signoff/ycr_intf/OPENLANE_VERSION b/signoff/ycr_intf/OPENLANE_VERSION
index b5bf449..fabca1a 100644
--- a/signoff/ycr_intf/OPENLANE_VERSION
+++ b/signoff/ycr_intf/OPENLANE_VERSION
@@ -1 +1 @@
-openlane b6bacc9d1ab469917fda7ceea61ea3a18984b818
+OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
diff --git a/signoff/ycr_intf/PDK_SOURCES b/signoff/ycr_intf/PDK_SOURCES
index f9d0f46..ef91c87 100644
--- a/signoff/ycr_intf/PDK_SOURCES
+++ b/signoff/ycr_intf/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 44a43c23c81b45b8e774ae7a84899a5a778b6b0b
+open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c
diff --git a/sta/scripts/caravel_timing.tcl b/sta/scripts/caravel_timing.tcl
index cb531fe..3475f43 100644
--- a/sta/scripts/caravel_timing.tcl
+++ b/sta/scripts/caravel_timing.tcl
@@ -43,15 +43,17 @@
 	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/caravel.v	
 
 	# User project netlist
-        read_verilog $::env(USER_ROOT)/verilog/gl/qspim_top.v
-        read_verilog $::env(USER_ROOT)/verilog/gl/ycr4_iconnect.v
-        read_verilog $::env(USER_ROOT)/verilog/gl/ycr_intf.v
-        read_verilog $::env(USER_ROOT)/verilog/gl/ycr_core_top.v
-        read_verilog $::env(USER_ROOT)/verilog/gl/uart_i2c_usb_spi_top.v
-        read_verilog $::env(USER_ROOT)/verilog/gl/wb_host.v  
-        read_verilog $::env(USER_ROOT)/verilog/gl/wb_interconnect.v
-        read_verilog $::env(USER_ROOT)/verilog/gl/pinmux_top.v
-        read_verilog $::env(USER_ROOT)/verilog/gl/user_project_wrapper.v  
+    read_verilog $::env(USER_ROOT)/verilog/gl/qspim_top.v
+    read_verilog $::env(USER_ROOT)/verilog/gl/ycr4_iconnect.v
+    read_verilog $::env(USER_ROOT)/verilog/gl/ycr_intf.v
+    read_verilog $::env(USER_ROOT)/verilog/gl/ycr_core_top.v
+    read_verilog $::env(USER_ROOT)/verilog/gl/uart_i2c_usb_spi_top.v
+    read_verilog $::env(USER_ROOT)/verilog/gl/wb_host.v  
+    read_verilog $::env(USER_ROOT)/verilog/gl/wb_interconnect.v
+    read_verilog $::env(USER_ROOT)/verilog/gl/pinmux_top.v
+    read_verilog $::env(USER_ROOT)/verilog/gl/dg_pll.v
+    read_verilog $::env(USER_ROOT)/verilog/gl/dac_top.v
+    read_verilog $::env(USER_ROOT)/verilog/gl/user_project_wrapper.v  
 
 
 	link_design caravel	
@@ -157,11 +159,13 @@
         read_spef -path mprj/u_uart_i2c_usb_spi               $::env(USER_ROOT)/spef/uart_i2c_usb_spi_top.spef
         read_spef -path mprj/u_wb_host                        $::env(USER_ROOT)/spef/wb_host.spef
         read_spef -path mprj/u_intercon                       $::env(USER_ROOT)/spef/wb_interconnect.spef
-	read_spef -path mprj/u_pll                            $::env(USER_ROOT)/spef/digital_pll.spef	
+	    read_spef -path mprj/u_pll                            $::env(USER_ROOT)/spef/dg_pll.spef	
+	    read_spef -path mprj/u_4x8bit_dac                     $::env(USER_ROOT)/spef/dac_top.spef	
         read_spef -path mprj                                  $::env(USER_ROOT)/spef/user_project_wrapper.spef  
 
 
 	read_sdc -echo ./sdc/caravel.sdc	
+	set_propagated_clock [all_clocks]
 	check_setup  -verbose >  unconstraints.rpt
 	report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50	
 	report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50	
diff --git a/sta/sdc/caravel.sdc b/sta/sdc/caravel.sdc
index 047d5a6..d39e591 100644
--- a/sta/sdc/caravel.sdc
+++ b/sta/sdc/caravel.sdc
@@ -61,10 +61,10 @@
 set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[1]}]
 set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[0]}]
 
-set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[3]}]
-set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[2]}]
-set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[1]}]
-set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[0]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[3]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[0]}]
 
 set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[3]}]
 set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[2]}]
@@ -76,6 +76,37 @@
 set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[0]}]
 set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[1]}]
 
+# clock skew cntrl-2
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[3]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[0]}]
+
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[3]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[0]}]
+
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[3]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[0]}]
+
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_1/cfg_ccska[3]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_1/cfg_ccska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_1/cfg_ccska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_1/cfg_ccska[0]}]
+
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_2/cfg_ccska[3]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_2/cfg_ccska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_2/cfg_ccska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_2/cfg_ccska[0]}]
+
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_3/cfg_ccska[3]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_3/cfg_ccska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_3/cfg_ccska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_3/cfg_ccska[0]}]
+
 #Keept the SRAM clock driving edge at pos edge
 set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_sram_lphase[0]}]
 set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_sram_lphase[1]}]
diff --git a/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v b/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v
index b618915..368b494 100644
--- a/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v
+++ b/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v
@@ -168,7 +168,7 @@
         tb_uart.uart_init;
         tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, uart_stick_parity, uart_timeout, uart_divisor);
 
-        repeat (1000) @(posedge clock);  // wait for Processor Get Ready
+        repeat (10000) @(posedge clock);  // wait for Processor Get Ready
 	    flag  = 0;
 		check_sum = 0;
             
diff --git a/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v b/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v
index 7f5b1c0..7cce107 100644
--- a/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v
+++ b/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v
@@ -205,6 +205,7 @@
         tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, 
                                            uart_stick_parity, uart_timeout, uart_divisor);
 
+        repeat (10000) @(posedge clock);  // wait for Processor Get Ready
 	    flag  = 0;
 		check_sum = 0;
         dCnt = 0;
diff --git a/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v b/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v
index d1141a8..6f91eae 100644
--- a/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v
+++ b/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v
@@ -165,7 +165,7 @@
                 tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, 
                                                uart_stick_parity, uart_timeout, uart_divisor);
 
-                repeat (1000) @(posedge clock);  // wait for Processor Get Ready
+                repeat (8000) @(posedge clock);  // wait for Processor Get Ready
 	        flag  = 1;
                 
                 
diff --git a/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v
index 72c3fbe..1ae2309 100644
--- a/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v
+++ b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v
@@ -117,13 +117,14 @@
 	`ifdef WFDUMP
 	   initial begin
 	   	$dumpfile("simx.vcd");
-	   	$dumpvars(3, `TB_TOP);
-	   	$dumpvars(0, `TB_TOP.u_top.u_riscv_top.i_core_top_0);
-	   	$dumpvars(0, `TB_TOP.u_top.u_riscv_top.u_connect);
-	   	$dumpvars(0, `TB_TOP.u_top.u_riscv_top.u_intf);
-	   	$dumpvars(0, `TB_TOP.u_top.u_uart_i2c_usb_spi.u_uart0_core);
-	   	$dumpvars(0, `TB_TOP.u_top.u_uart_i2c_usb_spi.u_i2cm);
-	   	$dumpvars(0, `TB_TOP.u_top.u_pinmux);
+	   	$dumpvars(1, `TB_TOP);
+	   	$dumpvars(0, `TB_TOP.tb_uart);
+	   	//$dumpvars(0, `TB_TOP.u_top.u_riscv_top.i_core_top_0);
+	   	//$dumpvars(0, `TB_TOP.u_top.u_riscv_top.u_connect);
+	   	//$dumpvars(0, `TB_TOP.u_top.u_riscv_top.u_intf);
+	   	$dumpvars(1, `TB_TOP.u_top.u_uart_i2c_usb_spi);
+	   	//$dumpvars(0, `TB_TOP.u_top.u_uart_i2c_usb_spi.u_i2cm);
+	   	//$dumpvars(0, `TB_TOP.u_top.u_pinmux);
 	   end
        `endif
 
@@ -172,13 +173,13 @@
         tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, 
                                        uart_stick_parity, uart_timeout, uart_divisor);
 
-         u_i2c_slave_0.debug = 0; // disable i2c bfm debug message
-         u_i2c_slave_1.debug = 0; // disable i2c bfm debug message
-         u_i2c_slave_2.debug = 0; // disable i2c bfm debug message
-         u_i2c_slave_3.debug = 0; // disable i2c bfm debug message
-         u_i2c_slave_4.debug = 0; // disable i2c bfm debug message
+        u_i2c_slave_0.debug = 0; // disable i2c bfm debug message
+        u_i2c_slave_1.debug = 0; // disable i2c bfm debug message
+        u_i2c_slave_2.debug = 0; // disable i2c bfm debug message
+        u_i2c_slave_3.debug = 0; // disable i2c bfm debug message
+        u_i2c_slave_4.debug = 0; // disable i2c bfm debug message
 
-        repeat (1000) @(posedge clock);  // wait for Processor Get Ready
+        repeat (10000) @(posedge clock);  // wait for Processor Get Ready
 	    flag  = 0;
 		check_sum = 0;
         compare_start = 1;
diff --git a/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v b/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v
index 40f9df8..882a549 100644
--- a/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v
+++ b/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v
@@ -175,7 +175,7 @@
          u_i2c_slave_0.debug = 1; // disable i2c bfm debug message
          u_i2c_slave_1.debug = 1; // disable i2c bfm debug message
 
-        repeat (1000) @(posedge clock);  // wait for Processor Get Ready
+        repeat (10000) @(posedge clock);  // wait for Processor Get Ready
 	    flag  = 0;
 		check_sum = 0;
         compare_start = 1;
diff --git a/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v b/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v
index 31ac5a0..f3f29e1 100644
--- a/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v
+++ b/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v
@@ -175,7 +175,7 @@
         tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, 
                                        uart_stick_parity, uart_timeout, uart_divisor);
 
-        repeat (1000) @(posedge clock);  // wait for Processor Get Ready
+        repeat (10000) @(posedge clock);  // wait for Processor Get Ready
 	    flag  = 0;
 		check_sum = 0;
         compare_start = 1;
@@ -193,7 +193,7 @@
               end
            end
            begin
-              repeat (600000) @(posedge clock);  // wait for Processor Get Ready
+              repeat (510000) @(posedge clock);  // wait for Processor Get Ready
            end
            join_any
         
diff --git a/verilog/dv/common/agents/caravel_task.sv b/verilog/dv/common/agents/caravel_task.sv
index 70ff764..3937734 100644
--- a/verilog/dv/common/agents/caravel_task.sv
+++ b/verilog/dv/common/agents/caravel_task.sv
@@ -13,9 +13,9 @@
 ****/
 
 `ifdef RISC_BOOT // RISCV Based Test case
-parameter bit  [15:0] PAD_STRAP = 16'b0000_0001_1011_0000;
+parameter bit  [15:0] PAD_STRAP = 16'b0000_0001_1010_0000;
 `else
-parameter bit  [15:0] PAD_STRAP = 16'b0000_0000_1011_0000;
+parameter bit  [15:0] PAD_STRAP = 16'b0000_0000_1010_0000;
 `endif
 
 /***********************************************
diff --git a/verilog/dv/common/agents/uart_agent.v b/verilog/dv/common/agents/uart_agent.v
index 5ca1813..0aab170 100644
--- a/verilog/dv/common/agents/uart_agent.v
+++ b/verilog/dv/common/agents/uart_agent.v
@@ -146,10 +146,9 @@
 
 ////////////////////////////////////////////////////////////////////////////////
 task read_char_chk;
-input 	expected_data;
+input [7:0]	expected_data;
 
 integer i;
-reg	[7:0] expected_data;
 reg 	[7:0] data;
 reg	parity;
 
@@ -340,7 +339,6 @@
 
 
 integer i;
-reg	[7:0] expected_data;
 reg 	[7:0] data;
 reg	parity;
 
diff --git a/verilog/dv/common/agents/usb_agents.v b/verilog/dv/common/agents/usb_agents.v
index c266567..4d144d0 100644
--- a/verilog/dv/common/agents/usb_agents.v
+++ b/verilog/dv/common/agents/usb_agents.v
@@ -274,7 +274,7 @@
 input [15:0] value; 
 input [15:0] index; 
 input [15:0] length;
-output       status;
+output[7:0]  status;
 reg   [7:0]  status;
 integer idx;
 begin
diff --git a/verilog/dv/common/agents/user_tasks.sv b/verilog/dv/common/agents/user_tasks.sv
index 0ea83c8..6bda236 100644
--- a/verilog/dv/common/agents/user_tasks.sv
+++ b/verilog/dv/common/agents/user_tasks.sv
@@ -90,7 +90,7 @@
 begin
    // Run in Fast Sim Mode
    `ifdef GL
-       force u_top.u_wb_host._09718_.Q= 1'b1; 
+       force u_top.u_wb_host._10673_.Q= 1'b1; 
    `else
        force u_top.u_wb_host.u_reg.u_fastsim_buf.X = 1'b1; 
     `endif
@@ -204,6 +204,7 @@
 
 //---------------------------------------------------------
 // Create Pull Up/Down Based on Reset Strap Parameter
+// System strap are in io_in[13] to [20] and 29 to [36]
 //---------------------------------------------------------
 genvar gCnt;
 generate
@@ -222,6 +223,13 @@
        end
     end
  end 
+ // Add Non Strap with pull-up to avoid unkown propagation during gate sim 
+ for(gCnt=0; gCnt<13; gCnt++) begin : g_nostrap1
+    pullup(io_in[gCnt]); 
+ end 
+ for(gCnt=21; gCnt<29; gCnt++) begin : g_nostrap2
+    pullup(io_in[gCnt]); 
+ end 
 endgenerate
 
 `ifdef RISC_BOOT // RISCV Based Test case
@@ -449,6 +457,32 @@
  baud_div = baud_div-1;
  end
  endtask
+ 
+/*************************************************************************
+ * This is I2C Prescale value computation logic
+ * Note: from I2c Logic 3 Prescale value SCL = 0, and 2 Prescale value SCL=1
+ *       Filtering logic uses two sample of Precale/4-1 period.
+ *       I2C Clock = System Clock / ((5*(Prescale-1)) + (2 * ((Prescale/4)-1)))
+ *   for 50Mhz system clock, 400Khz I2C clock
+ *       400,000 =  50,000,000 * (5*(Prescale-1) + 2*(Prescale/4+1)+2)
+ *      5*Prescale -5 + 2*Prescale/4 + 2 + 2= 50,000,000/400,000
+ *      5*prescale -5 + Prescale/2 + 4 = 125
+ *      (10*prescale+Prescale)/2 - 1 = 125
+ *      (11 *Prescale)/2 = 125+1
+ *      Prescale = 126*2/11
+
+ * *************************************************************************/
+ task tb_set_i2c_prescale;
+ input [31:0] ref_clk;
+ input [31:0] rate;
+ output [15:0] prescale;
+ reg   [15:0] prescale;
+ begin 
+   prescale   = ref_clk/rate; 
+   prescale = prescale +1; 
+   prescale = (prescale *2)/11; 
+ end
+ endtask
 
 /**
 `ifdef GL
diff --git a/verilog/dv/common/bfm/bfm_spim.v b/verilog/dv/common/bfm/bfm_spim.v
index f04f8b9..2bf556f 100644
--- a/verilog/dv/common/bfm/bfm_spim.v
+++ b/verilog/dv/common/bfm/bfm_spim.v
@@ -172,8 +172,7 @@
 endtask
 // Write 4 Byte
 task send_dword;
-input dword;
-reg [31:0] dword;
+input [31:0] dword;
 begin
   send_word(dword[31:16]);
   send_word(dword[15:0]);
@@ -182,8 +181,7 @@
 
 // Write 2 Byte
 task send_word;
-input word;
-reg [15:0] word;
+input [15:0] word;
 begin
   send_byte(word[15:8]);
   send_byte(word[7:0]);
@@ -194,8 +192,7 @@
 
 // Write 1 Byte
 task send_byte;
-input data;
-reg [7:0] data;
+input [7:0] data;
 integer i;
 begin
 
@@ -217,7 +214,7 @@
 
 // READ 4 BYTE
 task receive_dword;
-output dword;
+output [31:0] dword;
 reg [31:0] dword;
 begin
   receive_word(dword[31:16]);
@@ -227,7 +224,7 @@
 
 // READ 2 BYTE
 task receive_word;
-output word;
+output [15:0] word;
 reg [15:0] word;
 begin
   receive_byte(word[15:8]);
@@ -239,7 +236,7 @@
 
 // READ 1 BYTE
 task receive_byte;
-output data;
+output [7:0] data;
 reg [7:0] data;
 integer i;
 begin
diff --git a/verilog/dv/risc_boot/Makefile b/verilog/dv/risc_boot/Makefile
index db9d549..758f0ed 100644
--- a/verilog/dv/risc_boot/Makefile
+++ b/verilog/dv/risc_boot/Makefile
@@ -165,11 +165,11 @@
 ## RTL
 ifeq ($(SIM),RTL)
    ifeq ($(DUMP),OFF)
-	iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DRISC_BOOT -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
+	iverilog -g2012 -Ttyp -DFUNCTIONAL -DSIM -DRISC_BOOT -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
         -f$(VERILOG_PATH)/includes/includes.rtl.caravel \
         -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $<
     else  
-	iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DRISC_BOOT -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
+	iverilog -g2012 -DWFDUMP -Ttyp -DFUNCTIONAL -DRISC_BOOT -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
         -f$(VERILOG_PATH)/includes/includes.rtl.caravel \
         -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $<
    endif
diff --git a/verilog/dv/risc_boot/risc_boot_tb.v b/verilog/dv/risc_boot/risc_boot_tb.v
index 51bde45..ef56ee4 100644
--- a/verilog/dv/risc_boot/risc_boot_tb.v
+++ b/verilog/dv/risc_boot/risc_boot_tb.v
@@ -18,18 +18,17 @@
 ////                                                              ////
 ////  User Risc Core Boot Validation                              ////
 ////                                                              ////
-////  This file is part of the YIFive cores project               ////
-////  https://github.com/dineshannayya/yifive_r0.git              ////
-////  http://www.opencores.org/cores/yifive/                      ////
+////  This file is part of the riscduino cores project            ////
+////  https://github.com/dineshannayya/riscuino.git               ////
+////  http://www.opencores.org/cores/riscuino/                    ////
 ////                                                              ////
 ////  Description                                                 ////
-////     1. User Risc core is booted using  compiled code of      ////
-////        user_risc_boot.hex                                    ////
-////     2. User Risc core uses Serial Flash and SDRAM to boot    ////
-////     3. After successful boot, Risc core will  write signature////
-////        in to  user register from 0x3000_0018 to 0x3000_002C  ////
-////     4. Through the External Wishbone Interface we read back  ////
-////         and validate the user register to declared pass fail ////
+////    1. Strap is set to RISC core auto Boot mode               ////
+////    2. With Reset removal from caravel, User core boot up     ////
+////    3. Risc-V firmware have UART Loop back mode               ////
+////    4. Any UART Data Transmited by testbench will be loop back////
+////    5. There are 40 Random char are transmited and compared   ////
+////       againt received data                                   ////
 ////                                                              ////
 ////  To Do:                                                      ////
 ////    nothing                                                   ////
@@ -132,9 +131,10 @@
            $dumpfile("simx.vcd");
            $dumpvars(1,risc_boot_tb);
            //$dumpvars(1,risc_boot_tb.u_spi_flash_256mb);
-           $dumpvars(2,risc_boot_tb.u_top);
+           //$dumpvars(2,risc_boot_tb.u_top);
            $dumpvars(1,risc_boot_tb.u_top.mprj);
            $dumpvars(0,risc_boot_tb.u_top.mprj.u_wb_host);
+           $dumpvars(0,risc_boot_tb.u_top.mprj.u_pinmux);
            //$dumpvars(0,risc_boot_tb.tb_uart);
            //$dumpvars(0,risc_boot_tb.u_user_spiflash);
 	   $display("Waveform Dump started");
@@ -165,7 +165,7 @@
 
  $value$plusargs("risc_core_id=%d", d_risc_id);
 
-   init();
+         init();
 
            uart_data_bit           = 2'b11;
            uart_stop_bits          = 0; // 0: 1 stop bit; 1: 2 stop bit;
@@ -186,7 +186,7 @@
 					     uart_stick_parity, uart_timeout, uart_divisor);
 
 
-                wait_riscv_boot();
+        wait_riscv_boot();
 		repeat (50000) @(posedge clock);  
 
 		for (i=0; i<40; i=i+1)
diff --git a/verilog/dv/riscv_regress/Makefile b/verilog/dv/riscv_regress/Makefile
index d52ebf4..c3e3679 100644
--- a/verilog/dv/riscv_regress/Makefile
+++ b/verilog/dv/riscv_regress/Makefile
@@ -15,7 +15,7 @@
 
 export USER_PROJECT_VERILOG ?=  $(DESIGNS)/verilog
 ## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
 GCC_PREFIX?=riscv64-unknown-elf
 
 
diff --git a/verilog/dv/riscv_regress/user_risc_regress_tb.v b/verilog/dv/riscv_regress/user_risc_regress_tb.v
index 973c08a..2c53c8c 100644
--- a/verilog/dv/riscv_regress/user_risc_regress_tb.v
+++ b/verilog/dv/riscv_regress/user_risc_regress_tb.v
@@ -233,6 +233,7 @@
 	   	$dumpvars(0, user_risc_regress_tb.u_top.u_riscv_top);
 	   	$dumpvars(0, user_risc_regress_tb.u_top.u_qspi_master);
 	   	$dumpvars(0, user_risc_regress_tb.u_top.u_intercon);
+	   	$dumpvars(0, user_risc_regress_tb.u_top.u_pinmux);
 	   end
        `endif
 
diff --git a/verilog/dv/user_aes/user_aes.c b/verilog/dv/user_aes/user_aes.c
index 2830ebe..1b7a697 100644
--- a/verilog/dv/user_aes/user_aes.c
+++ b/verilog/dv/user_aes/user_aes.c
@@ -60,6 +60,7 @@
    reg_glbl_cfg0 |= 0x1F;       // Remove Reset for UART
    reg_glbl_multi_func &=0x7FFFFFFF; // Disable UART Master Bit[31] = 0
    reg_glbl_multi_func |=0x100; // Enable UART Multi func
+   reg_gpio_dsel  =0xFF00; // Enable PORT B As output
    reg_uart0_ctrl = 0x07;       // Enable Uart Access {3'h0,2'b00,1'b1,1'b1,1'b1}
    // GLBL_CFG_MAIL_BOX used as mail box, each core update boot up handshake at 8 bit
    // bit[7:0]   - core-0
diff --git a/verilog/dv/user_aes/user_aes_tb.v b/verilog/dv/user_aes/user_aes_tb.v
index 3d47bd3..55aba10 100644
--- a/verilog/dv/user_aes/user_aes_tb.v
+++ b/verilog/dv/user_aes/user_aes_tb.v
@@ -21,9 +21,7 @@
 ////  This file is part of the Riscduino cores project            ////
 ////                                                              ////
 ////  Description                                                 ////
-////   This is a standalone test bench to validate the            ////
-////   Digital core with Risc core executing code from TCM/SRAM.  ////
-////   with icache and dcache bypass mode                         ////
+////      To validate Software AES Encription & Decription        ////
 ////                                                              ////
 ////  To Do:                                                      ////
 ////    nothing                                                   ////
@@ -32,7 +30,7 @@
 ////      - Dinesh Annayya, dinesha@opencores.org                 ////
 ////                                                              ////
 ////  Revision :                                                  ////
-////    0.1 - 16th Feb 2021, Dinesh A                             ////
+////    0.1 - 7th Nov 2022, Dinesh A                              ////
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
@@ -98,24 +96,24 @@
 
 
      /************* Port-B Mapping **********************************
-     *   Pin-14       PB0/CLKO/ICP1             digital_io[11]
-     *   Pin-15       PB1/SS[1]OC1A(PWM3)       digital_io[12]
-     *   Pin-16       PB2/SS[0]/OC1B(PWM4)      digital_io[13]
-     *   Pin-17       PB3/MOSI/OC2A(PWM5)       digital_io[14]
-     *   Pin-18       PB4/MISO                  digital_io[15]
-     *   Pin-19       PB5/SCK                   digital_io[16]
-     *   Pin-9        PB6/XTAL1/TOSC1           digital_io[6]
-     *   Pin-10       PB7/XTAL2/TOSC2           digital_io[7]
+     *   Pin-14       PB0/CLKO/ICP1             digital_io[16]
+     *   Pin-15       PB1/SS[1]OC1A(PWM3)       digital_io[17]
+     *   Pin-16       PB2/SS[0]/OC1B(PWM4)      digital_io[18]
+     *   Pin-17       PB3/MOSI/OC2A(PWM5)       digital_io[19]
+     *   Pin-18       PB4/MISO                  digital_io[20]
+     *   Pin-19       PB5/SCK                   digital_io[21]
+     *   Pin-9        PB6/XTAL1/TOSC1           digital_io[11]
+     *   Pin-10       PB7/XTAL2/TOSC2           digital_io[12]
      *   ********************************************************/
 
-     wire [7:0]  port_b_in = {   io_out[7],
-		                 io_out[6],
-		                 io_out[16],
-		                 io_out[15],
-			         io_out[14],
-			         io_out[13],
-		                 io_out[12],
-		                 io_out[11]
+     wire [7:0]  port_b_in = {   io_out[12],
+		                         io_out[11],
+		                         io_out[21],
+		                         io_out[20],
+			                     io_out[19],
+			                     io_out[18],
+		                         io_out[17],
+		                         io_out[16]
 			     };
 	initial begin
 		test_fail = 0;
@@ -195,7 +193,7 @@
                      repeat (1400000) @(posedge clock); 
 	          end
 	          begin
-                     wait(port_b_in == 8'h18);
+                     wait(port_b_in == 8'h18 || port_b_in == 8'hA8);
 	          end
 	          begin
                      while(1) begin
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
index feab774..2865bda 100644
--- a/verilog/dv/user_basic/user_basic_tb.v
+++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -145,33 +145,33 @@
 reg [1:0]  strap_skew;
 wire [31:0] skew_config;
 
-assign skew_config[3:0]   =   (strap_skew == 2'b00) ?  SKEW_RESET_VAL[3:0] :
-                              (strap_skew == 2'b01) ?  SKEW_RESET_VAL[3:0] + 2 :
-                              (strap_skew == 2'b10) ?  SKEW_RESET_VAL[3:0] + 4 : SKEW_RESET_VAL[3:0]-4;
+assign skew_config[3:0]   =   (strap_skew == 2'b00) ?  CLK_SKEW1_RESET_VAL[3:0] :
+                              (strap_skew == 2'b01) ?  CLK_SKEW1_RESET_VAL[3:0] + 2 :
+                              (strap_skew == 2'b10) ?  CLK_SKEW1_RESET_VAL[3:0] + 4 : CLK_SKEW1_RESET_VAL[3:0]-4;
 
-assign skew_config[7:4]   =   (strap_skew == 2'b00) ?  SKEW_RESET_VAL[7:4]  :
-                              (strap_skew == 2'b01) ?  SKEW_RESET_VAL[7:4] + 2 :
-                              (strap_skew == 2'b10) ?  SKEW_RESET_VAL[7:4] + 4 : SKEW_RESET_VAL[7:4]-4;
+assign skew_config[7:4]   =   (strap_skew == 2'b00) ?  CLK_SKEW1_RESET_VAL[7:4]  :
+                              (strap_skew == 2'b01) ?  CLK_SKEW1_RESET_VAL[7:4] + 2 :
+                              (strap_skew == 2'b10) ?  CLK_SKEW1_RESET_VAL[7:4] + 4 : CLK_SKEW1_RESET_VAL[7:4]-4;
 
-assign skew_config[11:8]  =   (strap_skew == 2'b00) ?  SKEW_RESET_VAL[11:8]  :
-                              (strap_skew == 2'b01) ?  SKEW_RESET_VAL[11:8] + 2 :
-                              (strap_skew == 2'b10) ?  SKEW_RESET_VAL[11:8] + 4 : SKEW_RESET_VAL[11:8]-4;
+assign skew_config[11:8]  =   (strap_skew == 2'b00) ?  CLK_SKEW1_RESET_VAL[11:8]  :
+                              (strap_skew == 2'b01) ?  CLK_SKEW1_RESET_VAL[11:8] + 2 :
+                              (strap_skew == 2'b10) ?  CLK_SKEW1_RESET_VAL[11:8] + 4 : CLK_SKEW1_RESET_VAL[11:8]-4;
 
-assign skew_config[15:12] =   (strap_skew == 2'b00) ?  SKEW_RESET_VAL[15:12]  :
-                              (strap_skew == 2'b01) ?  SKEW_RESET_VAL[15:12] + 2 :
-                              (strap_skew == 2'b10) ?  SKEW_RESET_VAL[15:12] + 4 : SKEW_RESET_VAL[15:12]-4;
+assign skew_config[15:12] =   (strap_skew == 2'b00) ?  CLK_SKEW1_RESET_VAL[15:12]  :
+                              (strap_skew == 2'b01) ?  CLK_SKEW1_RESET_VAL[15:12] + 2 :
+                              (strap_skew == 2'b10) ?  CLK_SKEW1_RESET_VAL[15:12] + 4 : CLK_SKEW1_RESET_VAL[15:12]-4;
 
-assign skew_config[19:16] =   (strap_skew == 2'b00) ?  SKEW_RESET_VAL[19:16]  :
-                              (strap_skew == 2'b01) ?  SKEW_RESET_VAL[19:16] + 2 :
-                              (strap_skew == 2'b10) ?  SKEW_RESET_VAL[19:16] + 4 : SKEW_RESET_VAL[19:16]-4;
+assign skew_config[19:16] =   (strap_skew == 2'b00) ?  CLK_SKEW1_RESET_VAL[19:16]  :
+                              (strap_skew == 2'b01) ?  CLK_SKEW1_RESET_VAL[19:16] + 2 :
+                              (strap_skew == 2'b10) ?  CLK_SKEW1_RESET_VAL[19:16] + 4 : CLK_SKEW1_RESET_VAL[19:16]-4;
 
-assign skew_config[23:20] =   (strap_skew == 2'b00) ?  SKEW_RESET_VAL[23:20]  :
-                              (strap_skew == 2'b01) ?  SKEW_RESET_VAL[23:20] + 2 :
-                              (strap_skew == 2'b10) ?  SKEW_RESET_VAL[23:20] + 4 : SKEW_RESET_VAL[23:20]-4;
+assign skew_config[23:20] =   (strap_skew == 2'b00) ?  CLK_SKEW1_RESET_VAL[23:20]  :
+                              (strap_skew == 2'b01) ?  CLK_SKEW1_RESET_VAL[23:20] + 2 :
+                              (strap_skew == 2'b10) ?  CLK_SKEW1_RESET_VAL[23:20] + 4 : CLK_SKEW1_RESET_VAL[23:20]-4;
 
-assign skew_config[27:24] =   (strap_skew == 2'b00) ?  SKEW_RESET_VAL[27:24] :
-                              (strap_skew == 2'b01) ?  SKEW_RESET_VAL[27:24] + 2 :
-                              (strap_skew == 2'b10) ?  SKEW_RESET_VAL[27:24] + 4 : SKEW_RESET_VAL[27:24]-4;
+assign skew_config[27:24] =   (strap_skew == 2'b00) ?  CLK_SKEW1_RESET_VAL[27:24] :
+                              (strap_skew == 2'b01) ?  CLK_SKEW1_RESET_VAL[27:24] + 2 :
+                              (strap_skew == 2'b10) ?  CLK_SKEW1_RESET_VAL[27:24] + 4 : CLK_SKEW1_RESET_VAL[27:24]-4;
 
 assign skew_config[31:28] = 4'b0;
 
@@ -194,7 +194,7 @@
 	`ifdef WFDUMP
 	   initial begin
 	   	$dumpfile("simx.vcd");
-	   	$dumpvars(0, `TB_TOP);
+	   	$dumpvars(1, `TB_TOP);
 	   	$dumpvars(1, `TB_TOP.u_top);
 	   	$dumpvars(0, `TB_TOP.u_top.u_pll);
 	   	$dumpvars(0, `TB_TOP.u_top.u_wb_host);
@@ -279,7 +279,8 @@
               wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_PAD_STRAP,read_data,strap_in);
               wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_STRAP_STICKY,read_data,strap_sticky);
               wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SYSTEM_STRAP,read_data,strap_sticky);
-              wb_user_core_read_check(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,read_data,clk_ctrl2);
+              wb_user_core_read(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,read_data);
+              if(read_data[23:16] != clk_ctrl2) test_fail = 1;
               clock_monitor2(cpu_clk_cfg,wbs_clk_cfg);
           end
        end
@@ -479,9 +480,40 @@
       
        `endif
        $display("##########################################################");
-        $display("Step-10,Monitor: Checking the chip signature :");
-        $display("###################################################");
+       $display("Step-10,Monitor: Analog Config checks                     ");
+       $display("##########################################################");
        test_id = 10;
+       test_step = 14;
+
+        // Remove Wb/PinMux Reset
+        wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+
+        wb_user_core_write(`ADDR_SPACE_ANALOG+`ANALOG_CFG_DAC0,'h11);
+        wb_user_core_write(`ADDR_SPACE_ANALOG+`ANALOG_CFG_DAC1,'h22);
+        wb_user_core_write(`ADDR_SPACE_ANALOG+`ANALOG_CFG_DAC2,'h33);
+        wb_user_core_write(`ADDR_SPACE_ANALOG+`ANALOG_CFG_DAC3,'h44);
+        wb_user_core_read_check(`ADDR_SPACE_ANALOG+`ANALOG_CFG_DAC0,read_data,'h11);
+        wb_user_core_read_check(`ADDR_SPACE_ANALOG+`ANALOG_CFG_DAC1,read_data,'h22);
+        wb_user_core_read_check(`ADDR_SPACE_ANALOG+`ANALOG_CFG_DAC2,read_data,'h33);
+        wb_user_core_read_check(`ADDR_SPACE_ANALOG+`ANALOG_CFG_DAC3,read_data,'h44);
+        repeat (10) @(posedge clock);
+        if((u_top.u_4x8bit_dac.DIn0 != 'h11) || (u_top.u_4x8bit_dac.DIn1 != 'h22) ||
+           (u_top.u_4x8bit_dac.DIn2 != 'h33) || (u_top.u_4x8bit_dac.DIn3 != 'h44)) begin
+           test_fail = 1;
+        end
+
+        if(test_fail == 1) begin
+           $display("ERROR: Step-10,Monitor: Analog Config check - FAILED");
+        end else begin
+           $display("STATUS: Step-10,Monitor: Ananlog Config check - PASSED");
+
+        $display("##########################################################");
+
+          end
+       $display("##########################################################");
+       $display("Step-11,Monitor: Checking the chip signature :");
+       $display("###################################################");
+       test_id = 11;
         test_step = 14;
         // Remove Wb/PinMux Reset
         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
@@ -490,9 +522,9 @@
          wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,CHIP_RELEASE_DATE);
          wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,CHIP_REVISION);
          if(test_fail == 1) begin
-            $display("ERROR: Step-10,Monitor: Checking the chip signature - FAILED");
+            $display("ERROR: Step-11,Monitor: Checking the chip signature - FAILED");
          end else begin
-            $display("STATUS: Step-10,Monitor: Checking the chip signature - PASSED");
+            $display("STATUS: Step-11,Monitor: Checking the chip signature - PASSED");
 
          $display("##########################################################");
 
@@ -636,7 +668,7 @@
 input real exp_period;
 begin
    `ifdef GL
-   force clock_mon = u_top.u_wb_host._09314_.Q;
+   force clock_mon = u_top.u_wb_host._09635_.Q;
     `else
    force clock_mon = u_top.u_wb_host.u_uart2wb.u_core.line_clk_16x;
     `endif
diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v
index 0547990..5b52174 100644
--- a/verilog/dv/user_i2cm/user_i2cm_tb.v
+++ b/verilog/dv/user_i2cm/user_i2cm_tb.v
@@ -68,7 +68,7 @@
 `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
 `include "i2c_slave_model.v"
 
-module tb_top;
+module user_i2cm_tb;
 parameter real CLK1_PERIOD  = 20; // 50Mhz
 parameter real CLK2_PERIOD = 2.5;
 parameter real IPLL_PERIOD = 5.008;
@@ -76,6 +76,7 @@
 
 `include "user_tasks.sv"
 
+reg [15:0] prescale;
 
 //----------------------------------
 // Uart Configuration
@@ -87,7 +88,7 @@
 	`ifdef WFDUMP
 	   initial begin
 	   	$dumpfile("simx.vcd");
-	   	$dumpvars(0, tb_top);
+	   	$dumpvars(0, user_i2cm_tb);
 	   end
        `endif
 
@@ -119,9 +120,12 @@
     @(posedge  clock);
     $display("---------- Initialize I2C Master ----------"); 
 
+    // Sysclock: 50Mhz, I2C : 400Khz
+    tb_set_i2c_prescale(50000000,400000,prescale);
+    
     //Wrire Prescale registers
-     wb_user_core_write(`ADDR_SPACE_I2CM+(8'h0<<2),8'hC7);  
-     wb_user_core_write(`ADDR_SPACE_I2CM+(8'h1<<2),8'h00);  
+     wb_user_core_write(`ADDR_SPACE_I2CM+(8'h0<<2),prescale[7:0]);  
+     wb_user_core_write(`ADDR_SPACE_I2CM+(8'h1<<2),prescale[15:8]);  
     // Core Enable
      wb_user_core_write(`ADDR_SPACE_I2CM+(8'h2<<2),8'h80);  
     
diff --git a/verilog/dv/user_pwm/user_pwm_tb.v b/verilog/dv/user_pwm/user_pwm_tb.v
index b8bce21..3c425ce 100644
--- a/verilog/dv/user_pwm/user_pwm_tb.v
+++ b/verilog/dv/user_pwm/user_pwm_tb.v
@@ -98,9 +98,11 @@
 	   initial begin
 	   	$dumpfile("simx.vcd");
 	   	$dumpvars(1, `TB_GLBL);
-	   	$dumpvars(0, `TB_GLBL.u_top.u_wb_host);
+	   	$dumpvars(1, `TB_GLBL.pwm_monitor);
+	   	$dumpvars(1, `TB_GLBL.check_clock_period);
+	   	$dumpvars(1, `TB_GLBL.u_top.u_wb_host);
 	   	$dumpvars(0, `TB_GLBL.u_top.u_pinmux);
-	   	$dumpvars(0, `TB_GLBL.u_top.u_intercon);
+	   	$dumpvars(1, `TB_GLBL.u_top.u_intercon);
 	   end
        `endif
 
@@ -741,7 +743,7 @@
           $display("STATUS: Step-10, PWM One Shot + mode:3 + Comparator Center - PASSED");
        end
        $display("Check Sum: %x ",check_sum);
-       if(check_sum != 16'hc638) test_fail = 1;
+       if(check_sum != 16'hc692) test_fail = 1;
 
 		repeat (100) @(posedge clock);
 			// $display("+1000 cycles");
@@ -777,6 +779,16 @@
 wire pwm4 = pwm_wfm[4];
 wire pwm5 = pwm_wfm[5];
 
+
+reg [2:0] pwm_sel;
+
+assign clock_mon = (pwm_sel == 0) ? pwm0 :
+                   (pwm_sel == 1) ? pwm1 :
+                   (pwm_sel == 2) ? pwm2 :
+                   (pwm_sel == 3) ? pwm3 :
+                   (pwm_sel == 4) ? pwm4 : pwm5;
+
+                   
 task pwm_monitor;
 input [31:0] pwm0_period;
 input [31:0] pwm1_period;
@@ -785,29 +797,29 @@
 input [31:0] pwm4_period;
 input [31:0] pwm5_period;
 begin
-   force clock_mon = pwm0;
+   pwm_sel = 3'h0;
+   repeat (100) @(posedge clock);
    check_clock_period("PWM0 Clock",pwm0_period);
-   release clock_mon;
 
-   force clock_mon = pwm1;
+   pwm_sel = 3'h1;
+   repeat (100) @(posedge clock);
    check_clock_period("PWM1 Clock",pwm1_period);
-   release clock_mon;
 
-   force clock_mon = pwm2;
+   pwm_sel = 3'h2;
+   repeat (100) @(posedge clock);
    check_clock_period("PWM2 Clock",pwm2_period);
-   release clock_mon;
 
-   force clock_mon = pwm3;
+   pwm_sel = 3'h3;
+   repeat (100) @(posedge clock);
    check_clock_period("PWM3 Clock",pwm3_period);
-   release clock_mon;
 
-   force clock_mon = pwm4;
+   pwm_sel = 3'h4;
+   repeat (100) @(posedge clock);
    check_clock_period("PWM4 Clock",pwm4_period);
-   release clock_mon;
 
-   force clock_mon = pwm5;
+   pwm_sel = 3'h5;
+   repeat (100) @(posedge clock);
    check_clock_period("PWM5 Clock",pwm5_period);
-   release clock_mon;
 end
 endtask
 
@@ -821,7 +833,7 @@
 time prev_t, next_t, periodd;
 begin
     $timeformat(-12,3,"ns",10);
-   repeat(1) @(posedge clock_mon);
+   repeat(2) @(posedge clock_mon);
    repeat(1) @(posedge clock_mon);
    prev_t  = $realtime;
    repeat(2) @(posedge clock_mon);
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index 8029645..935aa9e 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -118,6 +118,7 @@
 	   	$dumpvars(1, `TB_TOP);
 	   	$dumpvars(2, `TB_TOP.u_top);
 	   	$dumpvars(0, `TB_TOP.u_top.u_wb_host);
+	   	$dumpvars(2, `TB_TOP.u_top.u_riscv_top);
 	   	$dumpvars(0, `TB_TOP.u_top.u_pinmux);
 	   end
        `endif
diff --git a/verilog/dv/user_uart_master/user_uart_master_tb.v b/verilog/dv/user_uart_master/user_uart_master_tb.v
index 25cbfd3..57d6802 100644
--- a/verilog/dv/user_uart_master/user_uart_master_tb.v
+++ b/verilog/dv/user_uart_master/user_uart_master_tb.v
@@ -145,7 +145,7 @@
 	                          uart_stick_parity, uart_timeout, uart_divisor);
 
 
-    tb_master_uart.write_char('\n'); // for uart baud auto detect purpose
+    tb_master_uart.write_char(8'h0A); // for uart baud auto detect purpose - New Line Character \n
    //$write ("\n(%t)Response:\n",$time);
    flag = 0;
    while(flag == 0)
diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c
index 4c7a868..f1bd1f3 100644
--- a/verilog/dv/wb_port/wb_port.c
+++ b/verilog/dv/wb_port/wb_port.c
@@ -33,10 +33,20 @@
 int i = 0; 
 int clk = 0;
 
+void putdword(uint32_t Data)
+{
+	reg_uart_data = Data >> 24; // MSB [31:24];
+	reg_uart_data = Data >> 16; // MSB [23:16];
+	reg_uart_data = Data >> 8;  // MSB [15:8];
+	reg_uart_data = Data;       // MSB [7:0];
+}
+
+
 void main()
 {
 
 	int bFail = 0;
+    char DataIn[5];
 	/* 
 	IO Control Registers
 	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
@@ -127,4 +137,5 @@
     } else {
         reg_mprj_datal = 0xAB600000;
     }
+    putdword(reg_mprj_datal);
 }
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project
index d905c9a..a5097ab 100644
--- a/verilog/includes/includes.gl.caravel_user_project
+++ b/verilog/includes/includes.gl.caravel_user_project
@@ -18,4 +18,7 @@
 $(USER_PROJECT_VERILOG)/gl/uart_i2c_usb_spi_top.v
 $(USER_PROJECT_VERILOG)/gl/wb_interconnect.v
 
+-v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/dg_pll.v
+-v $(USER_PROJECT_VERILOG)/rtl/dac/src/dac_top.v
+
 
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index 55b2bc8..3010d19 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -32,6 +32,11 @@
 -v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type1.sv
 -v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type2.sv
 -v $(USER_PROJECT_VERILOG)/rtl/lib/clk_div8.v
+
+-v $(USER_PROJECT_VERILOG)/rtl/dac/src/dac_top.v
+
+-v $(USER_PROJECT_VERILOG)/rtl/dig2ana/src/dig2ana_reg.sv
+
 -v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_top.sv
 -v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_if.sv
 -v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_fifo.sv
@@ -139,3 +144,6 @@
 -v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v
 -v $(USER_PROJECT_VERILOG)/rtl/lib/clk_skew_adjust.gv
 -v $(USER_PROJECT_VERILOG)/rtl/lib/ctech_cells.sv
+
+
+-v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/dg_pll.v
diff --git a/verilog/includes/includes.rtl.lib b/verilog/includes/includes.rtl.lib
index 5045805..9db7739 100644
--- a/verilog/includes/includes.rtl.lib
+++ b/verilog/includes/includes.rtl.lib
@@ -1,3 +1,2 @@
--v $(USER_PROJECT_VERILOG)/rtl/digital_pll/src/digital_pll_controller.v
--v $(USER_PROJECT_VERILOG)/rtl/digital_pll/src/digital_pll.v
--v $(USER_PROJECT_VERILOG)/rtl/digital_pll/src/ring_osc2x13.v
+-v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/digital_pll_controller.v
+-v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/ring_osc2x13.v
diff --git a/verilog/rtl/dac/src/dac_top.v b/verilog/rtl/dac/src/dac_top.v
new file mode 100644
index 0000000..951076d
--- /dev/null
+++ b/verilog/rtl/dac/src/dac_top.v
@@ -0,0 +1,24 @@
+module dac_top (Vout0,
+    Vout1,
+    Vout2,
+    Vout3,
+    Vref,
+    vccd1,
+    vssd1,
+    DIn0,
+    DIn1,
+    DIn2,
+    DIn3);
+ output Vout0;
+ output Vout1;
+ output Vout2;
+ output Vout3;
+ input Vref;
+ input vccd1;
+ input vssd1;
+ input [7:0] DIn0;
+ input [7:0] DIn1;
+ input [7:0] DIn2;
+ input [7:0] DIn3;
+
+endmodule
diff --git a/verilog/rtl/digital_pll/src/digital_pll.v b/verilog/rtl/dg_pll/src/dg_pll.v
similarity index 98%
rename from verilog/rtl/digital_pll/src/digital_pll.v
rename to verilog/rtl/dg_pll/src/dg_pll.v
index 79cb52e..a364783 100644
--- a/verilog/rtl/digital_pll/src/digital_pll.v
+++ b/verilog/rtl/dg_pll/src/dg_pll.v
@@ -54,7 +54,7 @@
 // Digital PLL (ring oscillator + controller)
 // Technically this is a frequency locked loop, not a phase locked loop.
 
-module digital_pll(
+module dg_pll(
 `ifdef USE_POWER_PINS
     VPWR,
     VGND,
diff --git a/verilog/rtl/digital_pll/src/digital_pll_controller.v b/verilog/rtl/dg_pll/src/digital_pll_controller.v
similarity index 100%
rename from verilog/rtl/digital_pll/src/digital_pll_controller.v
rename to verilog/rtl/dg_pll/src/digital_pll_controller.v
diff --git a/verilog/rtl/digital_pll/src/ring_osc2x13.v b/verilog/rtl/dg_pll/src/ring_osc2x13.v
similarity index 100%
rename from verilog/rtl/digital_pll/src/ring_osc2x13.v
rename to verilog/rtl/dg_pll/src/ring_osc2x13.v
diff --git a/verilog/rtl/dig2ana/src/dig2ana_reg.sv b/verilog/rtl/dig2ana/src/dig2ana_reg.sv
new file mode 100644
index 0000000..b0ad653
--- /dev/null
+++ b/verilog/rtl/dig2ana/src/dig2ana_reg.sv
@@ -0,0 +1,206 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  Digital To Analog Register                                  ////
+////                                                              ////
+////  This file is part of the riscduino cores project            ////
+////  https://github.com/dineshannayya/riscduino.git              ////
+////                                                              ////
+////  Description                                                 ////
+////     Manages all the analog related config                    ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision :                                                  ////
+////    0.1 - 29rd Sept 2022, Dinesh A                            ////
+////          initial version                                     ////
+//////////////////////////////////////////////////////////////////////
+
+
+module dig2ana_reg #(   
+                        parameter DW = 32,    // DATA WIDTH
+                        parameter AW = 4,     // ADDRESS WIDTH
+                        parameter BW = 4      // BYTE WIDTH
+                    ) (
+                       // System Signals
+                       // Inputs
+		               input logic           mclk                 ,
+                       input logic           h_reset_n            ,
+
+		               // Reg Bus Interface Signal
+                       input logic           reg_cs               ,
+                       input logic           reg_wr               ,
+                       input logic [AW-1:0]  reg_addr             ,
+                       input logic [DW-1:0]  reg_wdata            ,
+                       input logic [BW-1:0]  reg_be               ,
+
+                       // Outputs
+                       output logic [DW-1:0] reg_rdata            ,
+                       output logic          reg_ack              ,
+
+                       output logic [7:0]    cfg_dac0_mux_sel     ,
+                       output logic [7:0]    cfg_dac1_mux_sel     ,
+                       output logic [7:0]    cfg_dac2_mux_sel     ,
+                       output logic [7:0]    cfg_dac3_mux_sel     
+
+
+
+                ); 
+
+//-----------------------------------------------------------------------
+// Internal Wire Declarations
+//-----------------------------------------------------------------------
+
+logic          sw_rd_en              ;
+logic          sw_wr_en              ;
+logic [AW-1:0] sw_addr               ; 
+logic [DW-1:0] sw_reg_wdata          ;
+logic [BW-1:0] sw_be                 ;
+
+logic [DW-1:0] reg_out               ;
+logic [DW-1:0] reg_0                 ; 
+logic [DW-1:0] reg_1                 ; 
+logic [DW-1:0] reg_2                 ; 
+logic [DW-1:0] reg_3                 ; 
+
+
+assign       sw_addr       = reg_addr;
+assign       sw_be         = reg_be;
+assign       sw_rd_en      = reg_cs & !reg_wr;
+assign       sw_wr_en      = reg_cs & reg_wr;
+assign       sw_reg_wdata  = reg_wdata;
+
+//-----------------------------------------------------------------------
+// register read enable and write enable decoding logic
+//-----------------------------------------------------------------------
+wire   sw_wr_en_0  = sw_wr_en  & (sw_addr == 4'h0);
+wire   sw_wr_en_1  = sw_wr_en  & (sw_addr == 4'h1);
+wire   sw_wr_en_2  = sw_wr_en  & (sw_addr == 4'h2);
+wire   sw_wr_en_3  = sw_wr_en  & (sw_addr == 4'h3);
+
+
+
+always @ (posedge mclk or negedge h_reset_n)
+begin : preg_out_Seq
+   if (h_reset_n == 1'b0) begin
+      reg_rdata  <= 'h0;
+      reg_ack    <= 1'b0;
+   end else if (reg_cs && !reg_ack) begin
+      reg_rdata  <= reg_out[DW-1:0] ;
+      reg_ack    <= 1'b1;
+   end else begin
+      reg_ack    <= 1'b0;
+   end
+end
+
+//-----------------------------------------------------------------------
+//   reg-0
+//-----------------------------------------------------------------
+
+assign cfg_dac0_mux_sel = reg_0[7:0];
+generic_register #(8,8'h0  ) u_reg0_be0 (
+	      .we            ({8{sw_wr_en_0 & 
+                             sw_be[0]   }}  ),		 
+	      .data_in       (sw_reg_wdata[7:0]    ),
+	      .reset_n       (h_reset_n           ),
+	      .clk           (mclk              ),
+	      
+	      //List of Outs
+	      .data_out      (reg_0[7:0]        )
+          );
+
+assign reg_0[31:8] = 'h0;
+
+//-----------------------------------------------------------------------
+//   reg-1
+//-----------------------------------------------------------------
+
+assign cfg_dac1_mux_sel = reg_1[7:0];
+generic_register #(8,8'h0  ) u_reg1_be0 (
+	      .we            ({8{sw_wr_en_1 & 
+                             sw_be[0]   }}  ),		 
+	      .data_in       (sw_reg_wdata[7:0]    ),
+	      .reset_n       (h_reset_n           ),
+	      .clk           (mclk              ),
+	      
+	      //List of Outs
+	      .data_out      (reg_1[7:0]        )
+          );
+
+assign reg_1[31:8] = 'h0;
+
+//-----------------------------------------------------------------------
+//   reg-2
+//-----------------------------------------------------------------
+
+assign cfg_dac2_mux_sel = reg_2[7:0];
+generic_register #(8,8'h0  ) u_reg2_be0 (
+	      .we            ({8{sw_wr_en_2 & 
+                             sw_be[0]   }}  ),		 
+	      .data_in       (sw_reg_wdata[7:0]    ),
+	      .reset_n       (h_reset_n           ),
+	      .clk           (mclk              ),
+	      
+	      //List of Outs
+	      .data_out      (reg_2[7:0]        )
+          );
+
+assign reg_2[31:8] = 'h0;
+
+//-----------------------------------------------------------------------
+//   reg-3
+//-----------------------------------------------------------------
+
+assign cfg_dac3_mux_sel = reg_3[7:0];
+generic_register #(8,8'h0  ) u_reg3_be0 (
+	      .we            ({8{sw_wr_en_3 & 
+                             sw_be[0]   }}  ),		 
+	      .data_in       (sw_reg_wdata[7:0]    ),
+	      .reset_n       (h_reset_n           ),
+	      .clk           (mclk              ),
+	      
+	      //List of Outs
+	      .data_out      (reg_3[7:0]        )
+          );
+
+assign reg_3[31:8] = 'h0;
+
+//-----------------------------------------------------------------------
+// Register Read Path Multiplexer instantiation
+//-----------------------------------------------------------------------
+
+always_comb
+begin 
+  reg_out [31:0] = 32'h0;
+
+  case (sw_addr [3:0])
+    4'b0000 : reg_out [31:0] = reg_0  ;     
+    4'b0001 : reg_out [31:0] = reg_1  ;    
+    4'b0010 : reg_out [31:0] = reg_2  ;     
+    4'b0011 : reg_out [31:0] = reg_3  ;    
+    default  : reg_out [31:0] = 32'h0;
+  endcase
+end
+
+
+endmodule
diff --git a/verilog/rtl/lib/async_reg_bus.sv b/verilog/rtl/lib/async_reg_bus.sv
index 2c02701..3392cbf 100644
--- a/verilog/rtl/lib/async_reg_bus.sv
+++ b/verilog/rtl/lib/async_reg_bus.sv
@@ -1,4 +1,21 @@
-
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesh.annayya@gmail.com>
+//
+//////////////////////////////////////////////////////////////////////
 
 //----------------------------------------------------------------------------------------------
 // This block translate the Reg Bus transaction from in_clk clock domain to out_clk clock domain.
diff --git a/verilog/rtl/pinmux/src/glbl_reg.sv b/verilog/rtl/pinmux/src/glbl_reg.sv
index acbd36f..4262fc4 100644
--- a/verilog/rtl/pinmux/src/glbl_reg.sv
+++ b/verilog/rtl/pinmux/src/glbl_reg.sv
@@ -260,8 +260,8 @@
 //    7 -  Riscdunio (MPW-9)
 
 wire [15:0] manu_id      =  16'h8268; // Asci value of RD
-wire [3:0]  total_core   =  4'h04;
-wire [3:0]  chip_id      =  4'h05;
+wire [3:0]  total_core   =  4'h4;
+wire [3:0]  chip_id      =  4'h5;
 wire [7:0]  chip_rev     =  8'h01;
 
 assign reg_0 = {manu_id,total_core,chip_id,chip_rev};
@@ -367,7 +367,26 @@
 assign  irq_lines     = reg_3[31:0] & reg_4[31:0]; 
 
 // In Arduino GPIO[7:0] is corresponds to PORT-A which is not available for user access
-wire [31:0] hware_intr_req = {gpio_intr[31:8], 2'b0,pwm_intr,usb_intr, i2cm_intr,timer_intr[2:0]};
+
+logic usb_intr_s,usb_intr_ss;   // Usb Interrupt Double Sync
+logic i2cm_intr_s,i2cm_intr_ss; // I2C Interrupt Double Sync
+
+always @ (posedge mclk or negedge s_reset_n)
+begin  
+   if (s_reset_n == 1'b0) begin
+     usb_intr_s   <= 'h0;
+     usb_intr_ss  <= 'h0;
+     i2cm_intr_s  <= 'h0;
+     i2cm_intr_ss <= 'h0;
+   end else begin
+     usb_intr_s   <= usb_intr;
+     usb_intr_ss  <= usb_intr_s;
+     i2cm_intr_s  <= i2cm_intr;
+     i2cm_intr_ss <= i2cm_intr_s;
+   end
+end
+
+wire [31:0] hware_intr_req = {gpio_intr[31:8], 2'b0,pwm_intr,usb_intr_ss, i2cm_intr_ss,timer_intr[2:0]};
 
 generic_intr_stat_reg #(.WD(32),
 	                .RESET_DEFAULT(0)) u_reg4 (
@@ -760,6 +779,9 @@
 	                       (cfg_mon_sel == 4'b110) ? usb_clk      : 
 	                       (cfg_mon_sel == 4'b111) ? rtc_clk      : 1'b0;
 
+wire dbg_clk_ref_buf;
+ctech_clk_buf u_clkbuf_dbg_ref (.A (dbg_clk_ref), . X(dbg_clk_ref_buf));
+
 //  DIv16 to debug monitor purpose
 logic dbg_clk_div16;
 
@@ -767,7 +789,7 @@
    // Outputs
        .clk_o         (dbg_clk_div16    ),
    // Inputs
-       .mclk          (dbg_clk_ref      ),
+       .mclk          (dbg_clk_ref_buf  ),
        .reset_n       (e_reset_n        ), 
        .clk_div_ratio (4'hE             )
    );
diff --git a/verilog/rtl/pinmux/src/gpio_intr.sv b/verilog/rtl/pinmux/src/gpio_intr.sv
deleted file mode 100644
index 9bcefee..0000000
--- a/verilog/rtl/pinmux/src/gpio_intr.sv
+++ /dev/null
@@ -1,43 +0,0 @@
-
-// GPIO Interrupt Generation
-module gpio_intr_gen (
-   input  logic         mclk                     ,// System clk
-   input  logic         h_reset_n                ,// system reset
-   input  logic [31:0]  gpio_prev_indata         ,// previously captured GPIO I/P pins data
-   input  logic [31:0]  cfg_gpio_data_in         ,// GPIO I/P pins data captured into this
-   input  logic [31:0]  cfg_gpio_out_data        ,// GPIO statuc O/P data from config reg
-   input  logic [31:0]  cfg_gpio_dir_sel         ,// decides on GPIO pin is I/P or O/P at pad level
-   input  logic [31:0]  cfg_gpio_posedge_int_sel ,// select posedge interrupt
-   input  logic [31:0]  cfg_gpio_negedge_int_sel ,// select negedge interrupt
-   
-   
-   output logic [31:0]  pad_gpio_out             ,// GPIO O/P to the gpio cfg reg
-   output logic [31:0]  gpio_int_event            // to the cfg interrupt status reg 
- 
-);
-
-
-integer i;
-//-----------------------------------------------------------------------
-// Logic for interrupt detection 
-//-----------------------------------------------------------------------
-
-reg [31:0]  local_gpio_int_event;             // to the cfg interrupt status reg 
-always_comb
-begin
-   for (i=0; i<32; i=i+1)
-   begin 
-   // looking for rising edge int 
-      local_gpio_int_event[i] = ((cfg_gpio_posedge_int_sel[i] & ~gpio_prev_indata[i] 
-                                   &  cfg_gpio_data_in[i]) | 
-                                 (cfg_gpio_negedge_int_sel[i] & gpio_prev_indata[i] & 
-                                     ~cfg_gpio_data_in[i]));
-                                // looking for falling edge int 
-   end
-end
-
-assign gpio_int_event   = local_gpio_int_event[31:0]; // goes as O/P to the cfg reg 
-
-assign pad_gpio_out     = cfg_gpio_out_data[31:0]     ;// O/P on the GPIO bus
-
-endmodule
diff --git a/verilog/rtl/pinmux/src/gpio_reg.sv b/verilog/rtl/pinmux/src/gpio_reg.sv
deleted file mode 100644
index 10b90bd..0000000
--- a/verilog/rtl/pinmux/src/gpio_reg.sv
+++ /dev/null
@@ -1,325 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//      http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
-//
-//////////////////////////////////////////////////////////////////////
-////                                                              ////
-////  GPIO Register                                               ////
-////                                                              ////
-////  This file is part of the riscduino cores project            ////
-////  https://github.com/dineshannayya/riscduino.git              ////
-////                                                              ////
-////  Description                                                 ////
-////                                                              ////
-////  To Do:                                                      ////
-////    nothing                                                   ////
-////                                                              ////
-////  Author(s):                                                  ////
-////      - Dinesh Annayya, dinesha@opencores.org                 ////
-////                                                              ////
-////  Revision :                                                  ////
-////    0.1 - 15th Aug 2022, Dinesh A                             ////
-////          initial version                                     ////
-//////////////////////////////////////////////////////////////////////
-//
-module gpio_reg  (
-                       // System Signals
-                       // Inputs
-		               input logic           mclk               ,
-                       input logic           h_reset_n          ,
-
-		               // Reg Bus Interface Signal
-                       input logic           reg_cs             ,
-                       input logic           reg_wr             ,
-                       input logic [3:0]     reg_addr           ,
-                       input logic [31:0]    reg_wdata          ,
-                       input logic [3:0]     reg_be             ,
-
-                       // Outputs
-                       output logic [31:0]   reg_rdata          ,
-                       output logic          reg_ack            ,
-
-
-                       input  logic  [31:0]  gpio_in_data             ,
-                       output logic  [31:0]  gpio_prev_indata         ,// previously captured GPIO I/P pins data
-                       input  logic  [31:0]  gpio_int_event           ,
-                       output logic  [31:0]  cfg_gpio_out_data        ,// GPIO statuc O/P data from config reg
-                       output logic  [31:0]  cfg_gpio_dir_sel         ,// decides on GPIO pin is I/P or O/P at pad level, 0 -> Input, 1 -> Output
-                       output logic  [31:0]  cfg_gpio_out_type        ,// GPIO Type, 1 - WS_281X port
-                       output logic  [31:0]  cfg_multi_func_sel       ,// GPIO Multi function type
-                       output logic  [31:0]  cfg_gpio_posedge_int_sel ,// select posedge interrupt
-                       output logic  [31:0]  cfg_gpio_negedge_int_sel ,// select negedge interrupt
-                       output logic  [31:00] cfg_gpio_data_in         ,
-
-                       output logic  [31:0]  gpio_intr          
-
-
-                ); 
-
-//-----------------------------------------------------------------------
-// Internal Wire Declarations
-//-----------------------------------------------------------------------
-
-logic          sw_rd_en        ;
-logic          sw_wr_en        ;
-logic [3:0]    sw_addr         ; // addressing 16 registers
-logic [31:0]   sw_reg_wdata    ;
-logic [3:0]    sw_be           ;
-
-logic [31:0]   reg_out         ;
-logic [31:0]   reg_0           ; // GPIO Direction Select
-logic [31:0]   reg_1           ; // GPIO TYPE - Unused
-logic [31:0]   reg_2           ; // GPIO IN DATA
-logic [31:0]   reg_3           ; // GPIO OUT DATA
-logic [31:0]   reg_4           ; // GPIO INTERRUPT STATUS/CLEAR
-logic [31:0]   reg_5           ; // GPIO INTERRUPT SET
-logic [31:0]   reg_6           ; // GPIO INTERRUPT MASK
-logic [31:0]   reg_7           ; // GPIO POSEDGE INTERRUPT SEL
-logic [31:0]   reg_8           ; // GPIO NEGEDGE INTERRUPT SEL
-
-assign       sw_addr       = reg_addr;
-assign       sw_rd_en      = reg_cs & !reg_wr;
-assign       sw_wr_en      = reg_cs & reg_wr;
-assign       sw_be         = reg_be;
-assign       sw_reg_wdata  = reg_wdata;
-
-//-----------------------------------------------------------------------
-// register read enable and write enable decoding logic
-//-----------------------------------------------------------------------
-wire   sw_wr_en_0 = sw_wr_en  & (sw_addr == 4'h0);
-wire   sw_wr_en_1 = sw_wr_en  & (sw_addr == 4'h1);
-wire   sw_wr_en_2 = sw_wr_en  & (sw_addr == 4'h2);
-wire   sw_wr_en_3 = sw_wr_en  & (sw_addr == 4'h3);
-wire   sw_wr_en_4 = sw_wr_en  & (sw_addr == 4'h4);
-wire   sw_wr_en_5 = sw_wr_en  & (sw_addr == 4'h5);
-wire   sw_wr_en_6 = sw_wr_en  & (sw_addr == 4'h6);
-wire   sw_wr_en_7 = sw_wr_en  & (sw_addr == 4'h7);
-wire   sw_wr_en_8 = sw_wr_en  & (sw_addr == 4'h8);
-
-wire   sw_rd_en_0 = sw_rd_en  & (sw_addr == 4'h0);
-wire   sw_rd_en_1 = sw_rd_en  & (sw_addr == 4'h1);
-wire   sw_rd_en_2 = sw_rd_en  & (sw_addr == 4'h2);
-wire   sw_rd_en_3 = sw_rd_en  & (sw_addr == 4'h3);
-wire   sw_rd_en_4 = sw_rd_en  & (sw_addr == 4'h4);
-wire   sw_rd_en_5 = sw_rd_en  & (sw_addr == 4'h5);
-wire   sw_rd_en_6 = sw_rd_en  & (sw_addr == 4'h6);
-wire   sw_rd_en_7 = sw_rd_en  & (sw_addr == 4'h7);
-wire   sw_rd_en_8 = sw_rd_en  & (sw_addr == 4'h8);
-
-
-always @ (posedge mclk or negedge h_reset_n)
-begin : preg_out_Seq
-   if (h_reset_n == 1'b0) begin
-      reg_rdata  <= 'h0;
-      reg_ack    <= 1'b0;
-   end else if (reg_cs && !reg_ack) begin
-      reg_rdata  <= reg_out;
-      reg_ack    <= 1'b1;
-   end else begin
-      reg_ack    <= 1'b0;
-   end
-end
-
-//-----------------------------------------------------------------------
-// Logic for cfg_gpio_dir_sel 
-//-----------------------------------------------------------------------
-assign cfg_gpio_dir_sel = reg_0[31:0]; // data to the GPIO O/P pins 
-
-gen_32b_reg  #(32'h0) u_reg_0	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_0    ),
-	      .we         (sw_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_0         )
-	      );
-//-----------------------------------------------------------------------
-// Logic for cfg_gpio_out_type 
-//-----------------------------------------------------------------------
-assign cfg_gpio_out_type = reg_1[31:0]; // Un-used
-
-gen_32b_reg  #(32'h0) u_reg_1	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_1    ),
-	      .we         (sw_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_1         )
-	      );
-//-----------------------------------------------------------------------
-// Logic for gpio_data_in 
-//-----------------------------------------------------------------------
-logic [31:0] gpio_in_data_s;
-logic [31:0] gpio_in_data_ss;
-// Double Sync the gpio pin data for edge detection
-always @ (posedge mclk or negedge h_reset_n)
-begin 
-  if (h_reset_n == 1'b0) begin
-    reg_2  <= 'h0 ;
-    gpio_in_data_s  <= 32'd0;
-    gpio_in_data_ss <= 32'd0;
-  end
-  else begin
-    gpio_in_data_s   <= gpio_in_data;
-    gpio_in_data_ss <= gpio_in_data_s;
-    reg_2           <= gpio_in_data_ss;
-  end
-end
-
-
-assign cfg_gpio_data_in = reg_2[31:0]; // to be used for edge interrupt detect
-assign gpio_prev_indata = gpio_in_data_ss;
-
-//-----------------------------------------------------------------------
-// Logic for cfg_gpio_out_data 
-//-----------------------------------------------------------------------
-assign cfg_gpio_out_data = reg_3[31:0]; // data to the GPIO control blk 
-
-gen_32b_reg  #(32'h0) u_reg_3	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_3    ),
-	      .we         (sw_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_3         )
-	      );
-
-
-
-//--------------------------------------------------------
-// Interrupt Status Generation
-// Note: Reg_4 --> Interrupt Status Register, Writting '1' will clear the
-//                 corresponding interrupt status bit. Writting '0' has no
-//                 effect 
-//       Reg_5 --> Writting one to this register will set the interrupt in
-//                  interrupt status register (reg_4), Writting '0' does not has any
-//                  effect.
-/// Always update int_status, even if no register write is occuring.
-//	    Interrupt posting is higher priority than int clear by host 
-//--------------------------------------------------------
-wire [31:0] gpio_int_status = reg_4;				      
-
-generic_intr_stat_reg #(.WD(32),
-	                .RESET_DEFAULT(0))  u_reg_4 (
-		 //inputs
-		 .clk         (mclk              ),
-		 .reset_n     (h_reset_n         ),
-	     .reg_we      ({
-		               {8{sw_wr_en_4 & reg_ack & sw_be[2]}},
-		               {8{sw_wr_en_4 & reg_ack & sw_be[2]}},
-		               {8{sw_wr_en_4 & reg_ack & sw_be[1]}},
-		               {8{sw_wr_en_4 & reg_ack & sw_be[0]}}
-		               }  ),		 
-		 .reg_din    (sw_reg_wdata[31:0] ),
-		 .hware_req  (gpio_int_event | {
-		               {8{sw_wr_en_5 & reg_ack}} & sw_reg_wdata[31:24],
-		               {8{sw_wr_en_5 & reg_ack}} & sw_reg_wdata[23:16],
-		               {8{sw_wr_en_5 & reg_ack}} & sw_reg_wdata[15:8] ,
-		               {8{sw_wr_en_5 & reg_ack}} & sw_reg_wdata[7:0]   
-		               }     ),
-		 
-		 //outputs
-		 .data_out    (reg_4[31:0]       )
-	      );
-//-------------------------------------------------
-// Returns same value as interrupt status register
-//------------------------------------------------
-
-assign reg_5 = reg_4;
-//-----------------------------------------------------------------------
-// Logic for cfg_gpio_int_mask :  GPIO interrupt mask  
-//-----------------------------------------------------------------------
-wire [31:0]  cfg_gpio_int_mask = reg_6[31:0]; // to be used for read
-
-assign gpio_intr  = reg_4 & reg_6; // interrupt pin to the RISC
-
-
-//  Register-11
-gen_32b_reg  #(32'h0) u_reg_6	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_6    ),
-	      .we         (sw_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_6         )
-	      );
-//-----------------------------------------------------------------------
-// Logic for cfg_gpio_posedge_int_sel :  Enable posedge GPIO interrupt 
-//-----------------------------------------------------------------------
-assign  cfg_gpio_posedge_int_sel = reg_7[31:0]; // to be used for read
-gen_32b_reg  #(32'h0) u_reg_7	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_7    ),
-	      .we         (sw_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_7        )
-	      );
-//-----------------------------------------------------------------------
-// Logic for cfg_gpio_negedge_int_sel :  Enable negedge GPIO interrupt 
-//-----------------------------------------------------------------------
-assign cfg_gpio_negedge_int_sel = reg_8[31:0]; // to be used for read
-gen_32b_reg  #(32'h0) u_reg_8	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_8    ),
-	      .we         (sw_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_8        )
-	      );
-
-
-//-----------------------------------------------------------------------
-// Register Read Path Multiplexer instantiation
-//-----------------------------------------------------------------------
-
-always_comb
-begin 
-  reg_out [31:0] = 32'h0;
-
-  case (sw_addr [3:0])
-    4'b0000    : reg_out [31:0] = reg_0 [31:0];     
-    4'b0001    : reg_out [31:0] = reg_1 [31:0];    
-    4'b0010    : reg_out [31:0] = reg_2 [31:0];     
-    4'b0011    : reg_out [31:0] = reg_3 [31:0];    
-    4'b0100    : reg_out [31:0] = reg_4 [31:0];    
-    4'b0101    : reg_out [31:0] = reg_5 [31:0];    
-    4'b0110    : reg_out [31:0] = reg_6 [31:0];    
-    4'b0111    : reg_out [31:0] = reg_7 [31:0];    
-    4'b1000    : reg_out [31:0] = reg_8 [31:0];    
-    default    : reg_out [31:0] = 32'h0;
-  endcase
-end
-
-endmodule
diff --git a/verilog/rtl/pinmux/src/gpio_top.sv b/verilog/rtl/pinmux/src/gpio_top.sv
deleted file mode 100644
index 097623f..0000000
--- a/verilog/rtl/pinmux/src/gpio_top.sv
+++ /dev/null
@@ -1,130 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//      http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
-//
-//////////////////////////////////////////////////////////////////////
-////                                                              ////
-////  GPIO Top                                                     ////
-////                                                              ////
-////  This file is part of the riscduino cores project            ////
-////  https://github.com/dineshannayya/riscduino.git              ////
-////                                                              ////
-////  Description                                                 ////
-///                                                               ////
-////                                                              ////
-////  To Do:                                                      ////
-////    nothing                                                   ////
-////                                                              ////
-////  Author(s):                                                  ////
-////      - Dinesh Annayya, dinesha@opencores.org                 ////
-////                                                              ////
-////  Revision :                                                  ////
-////    0.1 - 15th Aug 2022, Dinesh A                             ////
-////          initial version                                     ////
-//////////////////////////////////////////////////////////////////////
-
-module gpio_top  (
-                       // System Signals
-                       // Inputs
-		               input logic           mclk,
-                       input logic           h_reset_n,
-
-		               // Reg Bus Interface Signal
-                       input logic           reg_cs,
-                       input logic           reg_wr,
-                       input logic [3:0]     reg_addr,
-                       input logic [31:0]    reg_wdata,
-                       input logic [3:0]     reg_be,
-
-                       // Outputs
-                       output logic [31:0]   reg_rdata,
-                       output logic          reg_ack,
-
-                       output logic  [31:0]  cfg_gpio_out_type ,// GPIO Type, 1 - ws281x
-                       output  logic [31:0]  cfg_gpio_dir_sel, 
-                       input   logic [31:0]  pad_gpio_in,
-                       output  logic [31:0]  pad_gpio_out,
-
-                       output  logic [31:0]  gpio_intr
-
-                ); 
-
-
-logic  [31:0]  gpio_prev_indata         ;// previously captured GPIO I/P pins data
-logic  [31:0]  cfg_gpio_out_data        ;// GPIO statuc O/P data from config reg
-logic  [31:0]  cfg_multi_func_sel       ;// GPIO Multi function type
-logic  [31:0]  cfg_gpio_posedge_int_sel ;// select posedge interrupt
-logic  [31:0]  cfg_gpio_negedge_int_sel ;// select negedge interrupt
-logic  [31:00] cfg_gpio_data_in         ;
-logic [31:0]   gpio_int_event           ;
-
-
-gpio_reg  u_reg (
-		       .mclk                         (mclk                    ),
-               .h_reset_n                    (h_reset_n               ),
-
-		       // Reg Bus Interface Signal
-               .reg_cs                       (reg_cs                  ),
-               .reg_wr                       (reg_wr                  ),
-               .reg_addr                     (reg_addr                ),
-               .reg_wdata                    (reg_wdata               ),
-               .reg_be                       (reg_be                  ),
-
-               // Outputs
-               .reg_rdata                    (reg_rdata               ),
-               .reg_ack                      (reg_ack                 ),
-
-            // GPIO input pins
-               .gpio_in_data                 (pad_gpio_in             ),
-               .gpio_prev_indata             (gpio_prev_indata        ),
-               .gpio_int_event               (gpio_int_event          ),
-
-            // GPIO config pins
-               .cfg_gpio_out_data            (cfg_gpio_out_data       ),
-               .cfg_gpio_dir_sel             (cfg_gpio_dir_sel        ),
-               .cfg_gpio_out_type            (cfg_gpio_out_type       ),
-               .cfg_gpio_posedge_int_sel     (cfg_gpio_posedge_int_sel),
-               .cfg_gpio_negedge_int_sel     (cfg_gpio_negedge_int_sel),
-               .cfg_multi_func_sel           (cfg_multi_func_sel      ),
-	           .cfg_gpio_data_in             (cfg_gpio_data_in        ),
-
-               .gpio_intr                    (gpio_intr               )
-
-
-                ); 
-
-
-gpio_intr_gen u_gpio_intr (
-   // System Signals
-   // Inputs
-          .mclk                    (mclk                    ),
-          .h_reset_n               (h_reset_n                ),
-
-   // GPIO cfg input pins
-          .gpio_prev_indata        (gpio_prev_indata        ),
-          .cfg_gpio_data_in        (cfg_gpio_data_in        ),
-          .cfg_gpio_dir_sel        (cfg_gpio_dir_sel        ),
-          .cfg_gpio_out_data       (cfg_gpio_out_data       ),
-          .cfg_gpio_posedge_int_sel(cfg_gpio_posedge_int_sel),
-          .cfg_gpio_negedge_int_sel(cfg_gpio_negedge_int_sel),
-
-
-   // GPIO output pins
-          .pad_gpio_out            (pad_gpio_out            ),
-          .gpio_int_event          (gpio_int_event          )  
-  );
-
-endmodule
diff --git a/verilog/rtl/pinmux/src/pinmux_top.sv b/verilog/rtl/pinmux/src/pinmux_top.sv
index 82cbeae..58419e2 100755
--- a/verilog/rtl/pinmux/src/pinmux_top.sv
+++ b/verilog/rtl/pinmux/src/pinmux_top.sv
@@ -196,8 +196,14 @@
                output logic[4:0]       cfg_pll_fed_div    , // PLL feedback division ratio
                output logic            cfg_dco_mode       , // Run PLL in DCO mode
                output logic[25:0]      cfg_dc_trim        , // External trim for DCO mode
-               output logic            pll_ref_clk         // Input oscillator to match
+               output logic            pll_ref_clk        , // Input oscillator to match
 
+               
+               // DAC Config
+               output logic [7:0]    cfg_dac0_mux_sel     ,
+               output logic [7:0]    cfg_dac1_mux_sel     ,
+               output logic [7:0]    cfg_dac2_mux_sel     ,
+               output logic [7:0]    cfg_dac3_mux_sel     
 
    ); 
 
@@ -261,6 +267,7 @@
 `define SEL_TIMER   3'b011   // TIMER REGISTER
 `define SEL_SEMA    3'b100   // SEMAPHORE REGISTER
 `define SEL_WS      3'b101   // WS281x  REGISTER
+`define SEL_D2A     3'b110   // Digital2Analog  REGISTER
 
 
 //----------------------------------------
@@ -284,28 +291,11 @@
 logic [31:0]  reg_ws_rdata;
 logic         reg_ws_ack;
 
+logic [31:0]  reg_d2a_rdata;
+logic         reg_d2a_ack;
+
 logic [7:0]   pwm_gpio_in;
 
-assign reg_rdata = (reg_addr[9:7] == `SEL_GLBL)  ? {reg_glbl_rdata} : 
-	               (reg_addr[9:7] == `SEL_GPIO)  ? {reg_gpio_rdata} :
-	               (reg_addr[9:7] == `SEL_PWM)   ? {reg_pwm_rdata}  :
-	               (reg_addr[9:7] == `SEL_TIMER) ? reg_timer_rdata  : 
-	               (reg_addr[9:7] == `SEL_SEMA)  ? {16'h0,reg_sema_rdata} : 
-	               (reg_addr[9:7] == `SEL_WS)    ? reg_ws_rdata     : 'h0;
-
-assign reg_ack   = (reg_addr[9:7] == `SEL_GLBL)  ? reg_glbl_ack   : 
-	               (reg_addr[9:7] == `SEL_GPIO)  ? reg_gpio_ack   : 
-	               (reg_addr[9:7] == `SEL_PWM)   ? reg_pwm_ack    : 
-	               (reg_addr[9:7] == `SEL_TIMER) ? reg_timer_ack  : 
-	               (reg_addr[9:7] == `SEL_SEMA)  ? reg_sema_ack   : 
-	               (reg_addr[9:7] == `SEL_WS)    ? reg_ws_ack     : 1'b0;
-
-wire reg_glbl_cs  = (reg_addr[9:7] == `SEL_GLBL) ? reg_cs : 1'b0;
-wire reg_gpio_cs  = (reg_addr[9:7] == `SEL_GPIO) ? reg_cs : 1'b0;
-wire reg_pwm_cs   = (reg_addr[9:7] == `SEL_PWM)  ? reg_cs : 1'b0;
-wire reg_timer_cs = (reg_addr[9:7] == `SEL_TIMER)? reg_cs : 1'b0;
-wire reg_sema_cs  = (reg_addr[9:7] == `SEL_SEMA) ? reg_cs : 1'b0;
-wire reg_ws_cs    = (reg_addr[9:7] == `SEL_WS) ? reg_cs : 1'b0;
 
 //---------------------------------------------------------------------
 
@@ -621,6 +611,72 @@
 
    ); 
 
+//-----------------------------------------------------------------------
+// Digital To Analog Register
+//-----------------------------------------------------------------------
+dig2ana_reg  u_d2a(
+              // System Signals
+              // Inputs
+		      .mclk                     ( mclk                      ),
+              .h_reset_n                (s_reset_ssn                ),
+
+		      // Reg Bus Interface Signal
+              .reg_cs                   (reg_d2a_cs                 ),
+              .reg_wr                   (reg_wr                     ),
+              .reg_addr                 (reg_addr[5:2]              ),
+              .reg_wdata                (reg_wdata[31:0]            ),
+              .reg_be                   (reg_be[3:0]                ),
+
+              // Outputs
+              .reg_rdata                (reg_d2a_rdata              ),
+              .reg_ack                  (reg_d2a_ack                ),
+
+              .cfg_dac0_mux_sel         (cfg_dac0_mux_sel           ),
+              .cfg_dac1_mux_sel         (cfg_dac1_mux_sel           ),
+              .cfg_dac2_mux_sel         (cfg_dac2_mux_sel           ),
+              .cfg_dac3_mux_sel         (cfg_dac3_mux_sel           )
+
+
+         );
+
+//-------------------------------------------------
+// Register Block Selection Logic
+//-------------------------------------------------
+reg [2:0] reg_blk_sel;
+
+always @(posedge mclk or negedge s_reset_ssn)
+begin
+   if(s_reset_ssn == 1'b0) begin
+     reg_blk_sel <= 'h0;
+   end
+   else begin
+      if(reg_cs) reg_blk_sel <= reg_addr[9:7];
+   end
+end
+
+assign reg_rdata = (reg_blk_sel == `SEL_GLBL)  ? {reg_glbl_rdata} : 
+	               (reg_blk_sel == `SEL_GPIO)  ? {reg_gpio_rdata} :
+	               (reg_blk_sel == `SEL_PWM)   ? {reg_pwm_rdata}  :
+	               (reg_blk_sel == `SEL_TIMER) ? reg_timer_rdata  : 
+	               (reg_blk_sel == `SEL_SEMA)  ? {16'h0,reg_sema_rdata} : 
+	               (reg_blk_sel == `SEL_WS)    ? reg_ws_rdata     : 
+	               (reg_blk_sel == `SEL_D2A)   ? reg_d2a_rdata    : 'h0;
+
+assign reg_ack   = (reg_blk_sel == `SEL_GLBL)  ? reg_glbl_ack   : 
+	               (reg_blk_sel == `SEL_GPIO)  ? reg_gpio_ack   : 
+	               (reg_blk_sel == `SEL_PWM)   ? reg_pwm_ack    : 
+	               (reg_blk_sel == `SEL_TIMER) ? reg_timer_ack  : 
+	               (reg_blk_sel == `SEL_SEMA)  ? reg_sema_ack   : 
+	               (reg_blk_sel == `SEL_WS)    ? reg_ws_ack     : 
+	               (reg_blk_sel == `SEL_D2A)   ? reg_d2a_ack    : 1'b0;
+
+wire reg_glbl_cs  = (reg_addr[9:7] == `SEL_GLBL) ? reg_cs : 1'b0;
+wire reg_gpio_cs  = (reg_addr[9:7] == `SEL_GPIO) ? reg_cs : 1'b0;
+wire reg_pwm_cs   = (reg_addr[9:7] == `SEL_PWM)  ? reg_cs : 1'b0;
+wire reg_timer_cs = (reg_addr[9:7] == `SEL_TIMER)? reg_cs : 1'b0;
+wire reg_sema_cs  = (reg_addr[9:7] == `SEL_SEMA) ? reg_cs : 1'b0;
+wire reg_ws_cs    = (reg_addr[9:7] == `SEL_WS)   ? reg_cs : 1'b0;
+wire reg_d2a_cs   = (reg_addr[9:7] == `SEL_D2A)  ? reg_cs : 1'b0;
 endmodule 
 
 
diff --git a/verilog/rtl/pinmux/src/pwm.sv b/verilog/rtl/pinmux/src/pwm.sv
deleted file mode 100644
index 7a30772..0000000
--- a/verilog/rtl/pinmux/src/pwm.sv
+++ /dev/null
@@ -1,44 +0,0 @@
-
-//-------------------------------------------------------------------
-// PWM waveform period:  1000/((cfg_pwm_high+1) + (cfg_pwm_low+1))
-// For 1 Second with Duty cycle 50 =   1000/((499+1) + (499+1))
-// For 1 Second with 1ms On and 999ms Off =  1000/((0+1) + (998+1))
-// Timing Run's with 1 Milisecond pulse
-//-------------------------------------------------------------------
-
-module pwm(
-	output  logic         waveform,
-
-	input  logic         h_reset_n,
-	input  logic         mclk,
-	input  logic         pulse1m_mclk,
-	input  logic         cfg_pwm_enb,
-	input  logic [15:0]  cfg_pwm_high,
-	input  logic [15:0]  cfg_pwm_low
-);
-
-logic [15:0]  pwm_cnt  ; // PWM on/off counter
-
-
-always @(posedge mclk or negedge h_reset_n)
-begin 
-   if ( ~h_reset_n )
-   begin
-      pwm_cnt  <= 16'h0;
-      waveform <= 1'b0;
-   end
-   else if ( pulse1m_mclk  && cfg_pwm_enb)
-   begin 
-      if ( pwm_cnt == 16'h0 && waveform  == 1'b0) begin
-         pwm_cnt       <= cfg_pwm_high;
-         waveform      <= ~waveform;
-      end else if ( pwm_cnt == 16'h0 && waveform  == 1'b1) begin
-         pwm_cnt       <= cfg_pwm_low;
-         waveform      <= ~waveform;
-      end else begin
-     	   pwm_cnt <= pwm_cnt - 1;
-      end
-   end
-end 
-
-endmodule
diff --git a/verilog/rtl/pinmux/src/pwm_reg.sv b/verilog/rtl/pinmux/src/pwm_reg.sv
deleted file mode 100644
index 702c138..0000000
--- a/verilog/rtl/pinmux/src/pwm_reg.sv
+++ /dev/null
@@ -1,255 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//      http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
-//
-//////////////////////////////////////////////////////////////////////
-////                                                              ////
-////  PWM Register                                                ////
-////                                                              ////
-////  This file is part of the riscduino cores project            ////
-////  https://github.com/dineshannayya/riscduino.git              ////
-////                                                              ////
-////  Description                                                 ////
-////                                                              ////
-////  To Do:                                                      ////
-////    nothing                                                   ////
-////                                                              ////
-////  Author(s):                                                  ////
-////      - Dinesh Annayya, dinesha@opencores.org                 ////
-////                                                              ////
-////  Revision :                                                  ////
-////    0.1 - 15th Aug 2022, Dinesh A                             ////
-////          initial version                                     ////
-//////////////////////////////////////////////////////////////////////
-//
-module pwm_reg  (
-                       // System Signals
-                       // Inputs
-		               input logic           mclk               ,
-                       input logic           h_reset_n          ,
-
-		               // Reg Bus Interface Signal
-                       input logic           reg_cs             ,
-                       input logic           reg_wr             ,
-                       input logic [2:0]     reg_addr           ,
-                       input logic [31:0]    reg_wdata          ,
-                       input logic [3:0]     reg_be             ,
-
-                       // Outputs
-                       output logic [31:0]   reg_rdata          ,
-                       output logic          reg_ack            ,
-
-                       output logic [15:0]    cfg_pwm0_high     ,
-                       output logic [15:0]    cfg_pwm0_low      ,
-                       output logic [15:0]    cfg_pwm1_high     ,
-                       output logic [15:0]    cfg_pwm1_low      ,
-                       output logic [15:0]    cfg_pwm2_high     ,
-                       output logic [15:0]    cfg_pwm2_low      ,
-                       output logic [15:0]    cfg_pwm3_high     ,
-                       output logic [15:0]    cfg_pwm3_low      ,
-                       output logic [15:0]    cfg_pwm4_high     ,
-                       output logic [15:0]    cfg_pwm4_low      ,
-                       output logic [15:0]    cfg_pwm5_high     ,
-                       output logic [15:0]    cfg_pwm5_low      
-
-                ); 
-
-//-----------------------------------------------------------------------
-// Internal Wire Declarations
-//-----------------------------------------------------------------------
-
-logic          sw_rd_en        ;
-logic          sw_wr_en        ;
-logic [2:0]    sw_addr         ; // addressing 16 registers
-logic [31:0]   sw_reg_wdata    ;
-logic [3:0]    sw_be           ;
-
-logic [31:0]   reg_out         ;
-logic [31:0]   reg_0           ; // CONFIG - Unused
-logic [31:0]   reg_1           ; // PWM-REG-0
-logic [31:0]   reg_2           ; // PWM-REG-1
-logic [31:0]   reg_3           ; // PWM-REG-2
-logic [31:0]   reg_4           ; // PWM-REG-3
-logic [31:0]   reg_5           ; // PWM-REG-4
-logic [31:0]   reg_6           ; // PWM-REG-5
-
-assign       sw_addr       = reg_addr;
-assign       sw_rd_en      = reg_cs & !reg_wr;
-assign       sw_wr_en      = reg_cs & reg_wr;
-assign       sw_be         = reg_be;
-assign       sw_reg_wdata  = reg_wdata;
-
-//-----------------------------------------------------------------------
-// register read enable and write enable decoding logic
-//-----------------------------------------------------------------------
-wire   sw_wr_en_0 = sw_wr_en  & (sw_addr == 3'h0);
-wire   sw_wr_en_1 = sw_wr_en  & (sw_addr == 3'h1);
-wire   sw_wr_en_2 = sw_wr_en  & (sw_addr == 3'h2);
-wire   sw_wr_en_3 = sw_wr_en  & (sw_addr == 3'h3);
-wire   sw_wr_en_4 = sw_wr_en  & (sw_addr == 3'h4);
-wire   sw_wr_en_5 = sw_wr_en  & (sw_addr == 3'h5);
-wire   sw_wr_en_6 = sw_wr_en  & (sw_addr == 3'h6);
-
-wire   sw_rd_en_0 = sw_rd_en  & (sw_addr == 3'h0);
-wire   sw_rd_en_1 = sw_rd_en  & (sw_addr == 3'h1);
-wire   sw_rd_en_2 = sw_rd_en  & (sw_addr == 3'h2);
-wire   sw_rd_en_3 = sw_rd_en  & (sw_addr == 3'h3);
-wire   sw_rd_en_4 = sw_rd_en  & (sw_addr == 3'h4);
-wire   sw_rd_en_5 = sw_rd_en  & (sw_addr == 3'h5);
-wire   sw_rd_en_6 = sw_rd_en  & (sw_addr == 3'h6);
-
-
-always @ (posedge mclk or negedge h_reset_n)
-begin : preg_out_Seq
-   if (h_reset_n == 1'b0) begin
-      reg_rdata  <= 'h0;
-      reg_ack    <= 1'b0;
-   end else if (reg_cs && !reg_ack) begin
-      reg_rdata  <= reg_out;
-      reg_ack    <= 1'b1;
-   end else begin
-      reg_ack    <= 1'b0;
-   end
-end
-
-//--------------------------------------------
-// reg-0: Reserve for pwm global config
-//---------------------------------------------
-assign reg_0 = 'h0;
-//-----------------------------------------------------------------------
-// Logic for PWM-0 Config
-//-----------------------------------------------------------------------
-assign  cfg_pwm0_low  = reg_1[15:0];  // low period of w/f 
-assign  cfg_pwm0_high = reg_1[31:16]; // high period of w/f 
-
-gen_32b_reg  #(32'h0) u_reg_1	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_1    ),
-	      .we         (sw_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_1         )
-	      );
-
-
-//-----------------------------------------------------------------------
-// Logic for PWM-1 Config
-//-----------------------------------------------------------------------
-assign  cfg_pwm1_low  = reg_2[15:0];  // low period of w/f 
-assign  cfg_pwm1_high = reg_2[31:16]; // high period of w/f 
-gen_32b_reg  #(32'h0) u_reg_2	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_2    ),
-	      .we         (sw_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_2         )
-	      );
-
-//-----------------------------------------------------------------------
-// Logic for PWM-2 Config
-//-----------------------------------------------------------------------
-assign  cfg_pwm2_low  = reg_3[15:0];  // low period of w/f 
-assign  cfg_pwm2_high = reg_3[31:16]; // high period of w/f 
-gen_32b_reg  #(32'h0) u_reg_3	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_3   ),
-	      .we         (sw_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_3        )
-	      );
-
-//-----------------------------------------------------------------------
-// Logic for PWM-3 Config
-//-----------------------------------------------------------------------
-assign  cfg_pwm3_low  = reg_4[15:0];  // low period of w/f 
-assign  cfg_pwm3_high = reg_4[31:16]; // high period of w/f 
-gen_32b_reg  #(32'h0) u_reg_4	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_4   ),
-	      .we         (sw_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_4        )
-	      );
-
-//-----------------------------------------------------------------------
-// Logic for PWM-4 Config
-//-----------------------------------------------------------------------
-assign  cfg_pwm4_low  = reg_5[15:0];  // low period of w/f 
-assign  cfg_pwm4_high = reg_5[31:16]; // high period of w/f 
-
-gen_32b_reg  #(32'h0) u_reg_5	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_5   ),
-	      .we         (sw_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_5        )
-	      );
-
-//-----------------------------------------------------------------------
-// Logic for PWM-5 Config
-//-----------------------------------------------------------------------
-assign  cfg_pwm5_low  = reg_6[15:0];  // low period of w/f 
-assign  cfg_pwm5_high = reg_6[31:16]; // high period of w/f 
-
-gen_32b_reg  #(32'h0) u_reg_6	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_6    ),
-	      .we         (sw_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_6        )
-	      );
-
-
-always_comb
-begin 
-  reg_out [31:0] = 32'h0;
-
-  case (sw_addr [2:0])
-    3'b000    : reg_out [31:0] = reg_0 [31:0];     
-    3'b001    : reg_out [31:0] = reg_1 [31:0];    
-    3'b010    : reg_out [31:0] = reg_2 [31:0];     
-    3'b011    : reg_out [31:0] = reg_3 [31:0];    
-    3'b100    : reg_out [31:0] = reg_4 [31:0];    
-    3'b101    : reg_out [31:0] = reg_5 [31:0];    
-    3'b110    : reg_out [31:0] = reg_6 [31:0];    
-    default   : reg_out [31:0] = 32'h0;
-  endcase
-end
-
-endmodule
diff --git a/verilog/rtl/pinmux/src/pwm_top.sv b/verilog/rtl/pinmux/src/pwm_top.sv
deleted file mode 100644
index 2b8d3a5..0000000
--- a/verilog/rtl/pinmux/src/pwm_top.sv
+++ /dev/null
@@ -1,172 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//      http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
-//
-//////////////////////////////////////////////////////////////////////
-////                                                              ////
-////  PWM Top                                                     ////
-////                                                              ////
-////  This file is part of the riscduino cores project            ////
-////  https://github.com/dineshannayya/riscduino.git              ////
-////                                                              ////
-////  Description                                                 ////
-///     Includes 6 PWM                                            ////
-////                                                              ////
-////  To Do:                                                      ////
-////    nothing                                                   ////
-////                                                              ////
-////  Author(s):                                                  ////
-////      - Dinesh Annayya, dinesha@opencores.org                 ////
-////                                                              ////
-////  Revision :                                                  ////
-////    0.1 - 15th Aug 2022, Dinesh A                             ////
-////          initial version                                     ////
-//////////////////////////////////////////////////////////////////////
-
-module pwm_top  (
-                       // System Signals
-                       // Inputs
-		               input logic           mclk,
-                       input logic           h_reset_n,
-
-		               // Reg Bus Interface Signal
-                       input logic           reg_cs,
-                       input logic           reg_wr,
-                       input logic [2:0]     reg_addr,
-                       input logic [31:0]    reg_wdata,
-                       input logic [3:0]     reg_be,
-
-                       // Outputs
-                       output logic [31:0]   reg_rdata,
-                       output logic          reg_ack,
-
-                   
-                       input  logic          pulse_1ms, 
-                       input  logic [5:0]    cfg_pwm_enb,
-                       output logic [5:0]    pwm_wfm 
-
-                ); 
-
-//---------------------------------------------------
-// 6 PWM variabled
-//---------------------------------------------------
-
-logic [15:0]    cfg_pwm0_high           ;
-logic [15:0]    cfg_pwm0_low            ;
-logic [15:0]    cfg_pwm1_high           ;
-logic [15:0]    cfg_pwm1_low            ;
-logic [15:0]    cfg_pwm2_high           ;
-logic [15:0]    cfg_pwm2_low            ;
-logic [15:0]    cfg_pwm3_high           ;
-logic [15:0]    cfg_pwm3_low            ;
-logic [15:0]    cfg_pwm4_high           ;
-logic [15:0]    cfg_pwm4_low            ;
-logic [15:0]    cfg_pwm5_high           ;
-logic [15:0]    cfg_pwm5_low            ;
-
-
-
-pwm_reg  u_reg (
-		       .mclk             (mclk                ),
-               .h_reset_n        (h_reset_n           ),
-
-		       // Reg Bus Interface Signal
-               .reg_cs           (reg_cs              ),
-               .reg_wr           (reg_wr              ),
-               .reg_addr         (reg_addr            ),
-               .reg_wdata        (reg_wdata           ),
-               .reg_be           (reg_be              ),
-
-               // Outputs
-               .reg_rdata        (reg_rdata           ),
-               .reg_ack          (reg_ack             ),
-
-               .cfg_pwm0_high    (cfg_pwm0_high       ),
-               .cfg_pwm0_low     (cfg_pwm0_low        ),
-               .cfg_pwm1_high    (cfg_pwm1_high       ),
-               .cfg_pwm1_low     (cfg_pwm1_low        ),
-               .cfg_pwm2_high    (cfg_pwm2_high       ),
-               .cfg_pwm2_low     (cfg_pwm2_low        ),
-               .cfg_pwm3_high    (cfg_pwm3_high       ),
-               .cfg_pwm3_low     (cfg_pwm3_low        ),
-               .cfg_pwm4_high    (cfg_pwm4_high       ),
-               .cfg_pwm4_low     (cfg_pwm4_low        ),
-               .cfg_pwm5_high    (cfg_pwm5_high       ),
-               .cfg_pwm5_low     (cfg_pwm5_low        )
-
-                ); 
-
-
-// 6 PWM Waveform Generator
-pwm  u_pwm_0 (
-	  .waveform                    (pwm_wfm[0]         ), 
-	  .h_reset_n                   (h_reset_n          ),
-	  .mclk                        (mclk               ),
-	  .pulse1m_mclk                (pulse_1ms          ),
-	  .cfg_pwm_enb                 (cfg_pwm_enb[0]     ),
-	  .cfg_pwm_high                (cfg_pwm0_high      ),
-	  .cfg_pwm_low                 (cfg_pwm0_low       )
-     );
-
-pwm  u_pwm_1 (
-	  .waveform                    (pwm_wfm[1]         ), 
-	  .h_reset_n                   (h_reset_n          ),
-	  .mclk                        (mclk               ),
-	  .pulse1m_mclk                (pulse_1ms          ),
-	  .cfg_pwm_enb                 (cfg_pwm_enb[1]     ),
-	  .cfg_pwm_high                (cfg_pwm1_high      ),
-	  .cfg_pwm_low                 (cfg_pwm1_low       )
-     );
-   
-pwm  u_pwm_2 (
-	  .waveform                    (pwm_wfm[2]         ), 
-	  .h_reset_n                   (h_reset_n          ),
-	  .mclk                        (mclk               ),
-	  .pulse1m_mclk                (pulse_1ms          ),
-	  .cfg_pwm_enb                 (cfg_pwm_enb[2]     ),
-	  .cfg_pwm_high                (cfg_pwm2_high      ),
-	  .cfg_pwm_low                 (cfg_pwm2_low       )
-     );
-
-pwm  u_pwm_3 (
-	  .waveform                    (pwm_wfm[3]         ), 
-	  .h_reset_n                   (h_reset_n          ),
-	  .mclk                        (mclk               ),
-	  .pulse1m_mclk                (pulse_1ms          ),
-	  .cfg_pwm_enb                 (cfg_pwm_enb[3]     ),
-	  .cfg_pwm_high                (cfg_pwm3_high      ),
-	  .cfg_pwm_low                 (cfg_pwm3_low       )
-     );
-pwm  u_pwm_4 (
-	  .waveform                    (pwm_wfm[4]         ), 
-	  .h_reset_n                   (h_reset_n          ),
-	  .mclk                        (mclk               ),
-	  .pulse1m_mclk                (pulse_1ms          ),
-	  .cfg_pwm_enb                 (cfg_pwm_enb[4]     ),
-	  .cfg_pwm_high                (cfg_pwm4_high      ),
-	  .cfg_pwm_low                 (cfg_pwm4_low       )
-     );
-pwm  u_pwm_5 (
-	  .waveform                    (pwm_wfm[5]         ), 
-	  .h_reset_n                   (h_reset_n          ),
-	  .mclk                        (mclk               ),
-	  .pulse1m_mclk                (pulse_1ms          ),
-	  .cfg_pwm_enb                 (cfg_pwm_enb[5]     ),
-	  .cfg_pwm_high                (cfg_pwm5_high      ),
-	  .cfg_pwm_low                 (cfg_pwm5_low       )
-     );
-
-endmodule
diff --git a/verilog/rtl/pinmux/src/timer.sv b/verilog/rtl/pinmux/src/timer.sv
deleted file mode 100755
index 55b7349..0000000
--- a/verilog/rtl/pinmux/src/timer.sv
+++ /dev/null
@@ -1,66 +0,0 @@
-
-module timer
-  (
-     input logic	     reset_n,	// system syn reset
-     input logic	     mclk,		// master clock
-     input logic 	     pulse_1us,
-     input logic 	     pulse_1ms,
-     input logic 	     pulse_1s,
-
-     input logic             cfg_timer_enb,     
-     input logic             cfg_timer_update, 
-     input logic [15:0]      cfg_timer_compare,
-     input logic [1:0]       cfg_timer_clksel,	// to select the timer 1us/1ms reference clock
-
-     output logic  	     timer_intr
-
-   );
-
-
-
-
-reg 		timer_hit_s1;
-wire 		timer_hit;
-reg [15:0]      timer_counter;
-wire		timer_pulse;
-
-
-// select between 1us timer and 1ms timer
-assign timer_pulse = (cfg_timer_clksel == 2'b00) ? pulse_1us : 
-	             (cfg_timer_clksel == 2'b01) ? pulse_1ms : pulse_1s;
-  
-
-/************************************************
-	Timer Counter
-************************************************/
-always @(negedge reset_n or posedge mclk)
-begin
-   if (!reset_n)
-	timer_counter <= 16'b0;
-   else if (cfg_timer_update || (timer_pulse && timer_hit))
-	timer_counter <=  cfg_timer_compare;
-   else if (timer_pulse && cfg_timer_enb)
-	timer_counter <=  timer_counter - 1;
-end
-
-
-   
-/***********************************************
-	Timer Interrupt Generation
-***********************************************/
-   assign timer_hit = (timer_counter == 1'b0);
-
-   assign timer_intr = !timer_hit_s1 && timer_hit && cfg_timer_enb;
-
-   
-   always @(negedge reset_n or posedge mclk)
-     begin
-	if (!reset_n) begin
-	   timer_hit_s1 <= 1'b1;
-        end else begin
-	   timer_hit_s1 <= timer_hit;
-	end
-     end
-
-   
-endmodule
diff --git a/verilog/rtl/pinmux/src/timer_reg.sv b/verilog/rtl/pinmux/src/timer_reg.sv
deleted file mode 100644
index 1a561f6..0000000
--- a/verilog/rtl/pinmux/src/timer_reg.sv
+++ /dev/null
@@ -1,212 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//      http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
-//
-//////////////////////////////////////////////////////////////////////
-////                                                              ////
-////  Timer Register                                              ////
-////                                                              ////
-////  This file is part of the riscduino cores project            ////
-////  https://github.com/dineshannayya/riscduino.git              ////
-////                                                              ////
-////  Description                                                 ////
-////                                                              ////
-////  To Do:                                                      ////
-////    nothing                                                   ////
-////                                                              ////
-////  Author(s):                                                  ////
-////      - Dinesh Annayya, dinesha@opencores.org                 ////
-////                                                              ////
-////  Revision :                                                  ////
-////    0.1 - 15th Aug 2022, Dinesh A                             ////
-////          initial version                                     ////
-//////////////////////////////////////////////////////////////////////
-//
-module timer_reg  (
-                       // System Signals
-                       // Inputs
-		               input logic           mclk               ,
-                       input logic           h_reset_n          ,
-
-		               // Reg Bus Interface Signal
-                       input logic           reg_cs             ,
-                       input logic           reg_wr             ,
-                       input logic [1:0]     reg_addr           ,
-                       input logic [31:0]    reg_wdata          ,
-                       input logic [3:0]     reg_be             ,
-
-                       // Outputs
-                       output logic [31:0]   reg_rdata          ,
-                       output logic          reg_ack            ,
-
-                       output logic [9:0]    cfg_pulse_1us      ,
-                       output logic [2:0]    cfg_timer_update   , // CPU write to timer register
-                       output logic [18:0]   cfg_timer0         , // Timer-0 register
-                       output logic [18:0]   cfg_timer1         , // Timer-1 register
-                       output logic [18:0]   cfg_timer2           // Timer-2 register
-
-                ); 
-
-//-----------------------------------------------------------------------
-// Internal Wire Declarations
-//-----------------------------------------------------------------------
-
-logic          sw_rd_en        ;
-logic          sw_wr_en        ;
-logic [1:0]    sw_addr         ; // addressing 16 registers
-logic [31:0]   sw_reg_wdata    ;
-logic [3:0]    sw_be           ;
-
-logic [31:0]   reg_out         ;
-logic [31:0]   reg_0           ;  // TIMER GLOBAL CONFIG
-logic [31:0]   reg_1           ;  // TIMER-0
-logic [31:0]   reg_2           ;  // TIMER-1
-logic [31:0]   reg_3           ;  // TIMER-2
-
-assign       sw_addr       = reg_addr;
-assign       sw_rd_en      = reg_cs & !reg_wr;
-assign       sw_wr_en      = reg_cs & reg_wr;
-assign       sw_be         = reg_be;
-assign       sw_reg_wdata  = reg_wdata;
-
-//-----------------------------------------------------------------------
-// register read enable and write enable decoding logic
-//-----------------------------------------------------------------------
-wire   sw_wr_en_0 = sw_wr_en  & (sw_addr == 2'h0);
-wire   sw_wr_en_1 = sw_wr_en  & (sw_addr == 2'h1);
-wire   sw_wr_en_2 = sw_wr_en  & (sw_addr == 2'h2);
-wire   sw_wr_en_3 = sw_wr_en  & (sw_addr == 2'h3);
-
-wire   sw_rd_en_0 = sw_rd_en  & (sw_addr == 2'h0);
-wire   sw_rd_en_1 = sw_rd_en  & (sw_addr == 2'h1);
-wire   sw_rd_en_2 = sw_rd_en  & (sw_addr == 2'h2);
-wire   sw_rd_en_3 = sw_rd_en  & (sw_addr == 2'h3);
-
-
-always @ (posedge mclk or negedge h_reset_n)
-begin : preg_out_Seq
-   if (h_reset_n == 1'b0) begin
-      reg_rdata  <= 'h0;
-      reg_ack    <= 1'b0;
-   end else if (reg_cs && !reg_ack) begin
-      reg_rdata  <= reg_out;
-      reg_ack    <= 1'b1;
-   end else begin
-      reg_ack    <= 1'b0;
-   end
-end
-
-
-//----------------------------------------------
-// reg-0: GLBL_CFG
-//------------------------------------------
-
-gen_32b_reg  #('h0) u_reg_0	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_0    ),
-	      .we         (sw_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_0         )
-	      );
-
-assign cfg_pulse_1us       = reg_0[9:0];
-
-//-----------------------------------------------------------------------
-//   reg-1
-// Assumption: wr_en is two cycle and reg_ack is asserted in second cycle
-//     In first cycle, local register will be updated
-//     In second cycle, update indication sent to timer block
-//   -----------------------------------------------------------------
-assign cfg_timer0          = reg_1[18:0];
-assign cfg_timer_update[0] = sw_wr_en_1 & reg_ack; 
-
-gen_32b_reg  #(32'h0) u_reg_1	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_1    ),
-	      .we         (sw_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_1[31:0]  )
-	      );
-
-//-----------------------------------------------------------------------
-//   reg-2
-// Assumption: wr_en is two cycle and reg_ack is asserted in second cycle
-//     In first cycle, local register will be updated
-//     In second cycle, update indication sent to timer block
-//   -----------------------------------------------------------------
-assign cfg_timer1          = reg_2[18:0];
-assign cfg_timer_update[1] = sw_wr_en_2 & reg_ack;
-
-gen_32b_reg  #(32'h0) u_reg_2	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_2    ),
-	      .we         (sw_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_2[31:0]   )
-	      );
-
-
-//-----------------------------------------------------------------------
-//   reg-3
-// Assumption: wr_en is two cycle and reg_ack is asserted in second cycle
-//     In first cycle, local register will be updated
-//     In second cycle, update indication sent to timer block
-//   -----------------------------------------------------------------
-assign cfg_timer2          = reg_3[18:0];
-assign cfg_timer_update[2] = sw_wr_en_3 & reg_ack;
-
-gen_32b_reg  #(32'h0) u_reg_3	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_3    ),
-	      .we         (sw_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_3[31:0]   )
-	      );
-
-//-----------------------------------------------------------------------
-// Register Read Path Multiplexer instantiation
-//-----------------------------------------------------------------------
-
-always_comb
-begin 
-  reg_out [31:0] = 32'h0;
-
-  case (sw_addr [1:0])
-    2'b00    : reg_out [31:0] = reg_0 [31:0];     
-    2'b01    : reg_out [31:0] = reg_1 [31:0];    
-    2'b10    : reg_out [31:0] = reg_2 [31:0];     
-    2'b11    : reg_out [31:0] = reg_3 [31:0];    
-    default  : reg_out [31:0] = 32'h0;
-  endcase
-end
-
-endmodule
diff --git a/verilog/rtl/pinmux/src/timer_top.sv b/verilog/rtl/pinmux/src/timer_top.sv
deleted file mode 100644
index 127d62f..0000000
--- a/verilog/rtl/pinmux/src/timer_top.sv
+++ /dev/null
@@ -1,191 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//      http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
-//
-//////////////////////////////////////////////////////////////////////
-////                                                              ////
-////  Timer Top                                                   ////
-////                                                              ////
-////  This file is part of the riscduino cores project            ////
-////  https://github.com/dineshannayya/riscduino.git              ////
-////                                                              ////
-////  Description                                                 ////
-////                                                              ////
-////  To Do:                                                      ////
-////    nothing                                                   ////
-////                                                              ////
-////  Author(s):                                                  ////
-////      - Dinesh Annayya, dinesha@opencores.org                 ////
-////                                                              ////
-////  Revision :                                                  ////
-////    0.1 - 15th Aug 2022, Dinesh A                             ////
-////          initial version                                     ////
-//////////////////////////////////////////////////////////////////////
-
-module timer_top  (
-                       // System Signals
-                       // Inputs
-		               input logic           mclk,
-                       input logic           h_reset_n,
-
-		               // Reg Bus Interface Signal
-                       input logic           reg_cs,
-                       input logic           reg_wr,
-                       input logic [1:0]     reg_addr,
-                       input logic [31:0]    reg_wdata,
-                       input logic [3:0]     reg_be,
-
-                       // Outputs
-                       output logic [31:0]   reg_rdata,
-                       output logic          reg_ack,
-
-                       output logic          pulse_1ms,
-                       output logic [2:0]    timer_intr 
-
-                ); 
-
-//---------------------------------------------------------
-// Timer Register                          
-// -------------------------------------------------------
-logic [2:0]    cfg_timer_update        ; // CPU write to timer register
-logic [18:0]   cfg_timer0              ; // Timer-0 register
-logic [18:0]   cfg_timer1              ; // Timer-1 register
-logic [18:0]   cfg_timer2              ; // Timer-2 register
-
-/* clock pulse */
-//********************************************************
-logic           pulse_1us               ; // 1 UsSecond Pulse for waveform Generator
-logic           pulse_1s                ; // 1Second Pulse for waveform Generator
-logic [9:0]     cfg_pulse_1us           ; // 1us pulse generation config
-
-timer_reg  u_reg (
-		       .mclk             (mclk                ),
-               .h_reset_n        (h_reset_n           ),
-
-		       // Reg Bus Interface Signal
-               .reg_cs           (reg_cs              ),
-               .reg_wr           (reg_wr              ),
-               .reg_addr         (reg_addr            ),
-               .reg_wdata        (reg_wdata           ),
-               .reg_be           (reg_be              ),
-
-               // Outputs
-               .reg_rdata        (reg_rdata           ),
-               .reg_ack          (reg_ack             ),
-
-               .cfg_pulse_1us    (cfg_pulse_1us       ),
-               .cfg_timer_update (cfg_timer_update    ),
-               .cfg_timer0       (cfg_timer0          ),
-               .cfg_timer1       (cfg_timer1          ),
-               .cfg_timer2       (cfg_timer2          )
-
-                ); 
-
-// 1us pulse
-pulse_gen_type2  #(.WD(10)) u_pulse_1us (
-
-	.clk_pulse_o               (pulse_1us        ),
-	.clk                       (mclk             ),
-    .reset_n                   (h_reset_n        ),
-	.cfg_max_cnt               (cfg_pulse_1us    )
-
-     );
-
-// 1us/1000 to 1millisecond pulse
-pulse_gen_type1 u_pulse_1ms (
-
-	.clk_pulse_o               (pulse_1ms       ),
-	.clk                       (mclk            ),
-    .reset_n                   (h_reset_n       ),
-	.trigger                   (pulse_1us       )
-
-      );
-
-// 1ms/1000 => 1 second pulse
-pulse_gen_type1 u_pulse_1s (
-
-	.clk_pulse_o               (pulse_1s    ),
-	.clk                       (mclk        ),
-    .reset_n                   (h_reset_n   ),
-	.trigger                   (pulse_1ms   )
-
-       );
-
-// Timer
-
-wire [1:0]  cfg_timer0_clksel = cfg_timer0[18:17];
-wire        cfg_timer0_enb    = cfg_timer0[16];
-wire [15:0] cfg_timer0_compare = cfg_timer0[15:0];
-
-timer  u_timer_0
-  (
-     .reset_n                      (h_reset_n            ),// system syn reset
-     .mclk                         (mclk                 ),// master clock
-     .pulse_1us                    (pulse_1us            ),
-     .pulse_1ms                    (pulse_1ms            ),
-     .pulse_1s                     (pulse_1s             ),
-
-     .cfg_timer_update             (cfg_timer_update[0]  ), 
-     .cfg_timer_enb                (cfg_timer0_enb       ),     
-     .cfg_timer_compare            (cfg_timer0_compare   ),
-     .cfg_timer_clksel             (cfg_timer0_clksel    ),// to select the timer 1us/1ms reference clock
-
-     .timer_intr                   (timer_intr[0]         )
-   );
-
-// Timer
-wire [1:0] cfg_timer1_clksel   = cfg_timer1[18:17];
-wire       cfg_timer1_enb      = cfg_timer1[16];
-wire [15:0] cfg_timer1_compare = cfg_timer1[15:0];
-timer  u_timer_1
-  (
-     .reset_n                      (h_reset_n            ),// system syn reset
-     .mclk                         (mclk                 ),// master clock
-     .pulse_1us                    (pulse_1us            ),
-     .pulse_1ms                    (pulse_1ms            ),
-     .pulse_1s                     (pulse_1s             ),
-
-     .cfg_timer_update             (cfg_timer_update[1]  ), 
-     .cfg_timer_enb                (cfg_timer1_enb       ),     
-     .cfg_timer_compare            (cfg_timer1_compare   ),
-     .cfg_timer_clksel             (cfg_timer1_clksel    ),// to select the timer 1us/1ms reference clock
-
-     .timer_intr                   (timer_intr[1]         )
-   );
-
-// Timer
-wire [1:0] cfg_timer2_clksel = cfg_timer2[18:17];
-wire       cfg_timer2_enb    = cfg_timer2[16];
-wire [15:0] cfg_timer2_compare = cfg_timer2[15:0];
-
-timer  u_timer_2
-  (
-     .reset_n                      (h_reset_n            ),// system syn reset
-     .mclk                         (mclk                 ),// master clock
-     .pulse_1us                    (pulse_1us            ),
-     .pulse_1ms                    (pulse_1ms            ),
-     .pulse_1s                     (pulse_1s             ),
-
-     .cfg_timer_update             (cfg_timer_update[2]  ), 
-     .cfg_timer_enb                (cfg_timer2_enb       ),     
-     .cfg_timer_compare            (cfg_timer2_compare   ),
-     .cfg_timer_clksel             (cfg_timer2_clksel    ),// to select the timer 1us/1ms reference clock
-
-     .timer_intr                   (timer_intr[2]        )
-   );
-
-
-endmodule
diff --git a/verilog/rtl/pinmux/src/ws281x_driver.sv b/verilog/rtl/pinmux/src/ws281x_driver.sv
deleted file mode 100644
index 9974a83..0000000
--- a/verilog/rtl/pinmux/src/ws281x_driver.sv
+++ /dev/null
@@ -1,110 +0,0 @@
-
-// 24 bit ws281x led driver
-
-module ws281x_driver (
-    input  logic          clk                  ,   // Clock input.
-    input  logic          reset_n              ,   // Resets the internal state of the driver
-
-    input  logic[15:0]    cfg_reset_period     ,   // Reset period interm of clk
-    input  logic [9:0]    cfg_clk_period       ,   // Total bit clock period
-    input  logic [9:0]    cfg_th0_period        ,   // bit-0 drive low period
-    input  logic [9:0]    cfg_th1_period        ,   // bit-1 drive low period
-
-    input  logic          port_enb               , 
-    input  logic          data_available       , 
-    input  logic [7:0]    green_in             ,   // 8-bit green data
-    input  logic [7:0]    red_in               ,   // 8-bit red data
-    input  logic [7:0]    blue_in              ,   // 8-bit blue data
-    output logic          data_rd              ,   // data read
-    
-    output logic          txd                      // Signal to send to WS2811 chain.
-    );
-	
-
-   parameter  STATE_RESET    = 1'd0;
-   parameter  STATE_TRANSMIT = 1'd1;
-   /////////////////////////////////////////////////////////////
-   // Timing parameters for the WS2811                        //
-   // The LEDs are reset by driving D0 low for at least 50us. //
-   // Data is transmitted using a 800kHz signal.              //
-   // A '1' is 50% duty cycle, a '0' is 20% duty cycle.       //
-   /////////////////////////////////////////////////////////////
-
-   reg [15:0]             clk_cnt       ;   // Clock divider for a cycle
-   reg                    state         ;   // FSM state
-   reg [23:0]             led_data      ;   // Current byte to send
-   reg [4:0]              bit_cnt       ;   // Current bit index to send
-
-
-
-   
-   always @ (posedge clk or negedge reset_n) begin
-      if (reset_n == 1'b0) begin
-         state         <= STATE_RESET;
-         txd           <= 0;
-         data_rd       <= 0;
-         bit_cnt       <= 23;
-         clk_cnt       <= 0;
-         led_data      <= 0;
-      end
-      else begin
-         case (state)
-           STATE_RESET: begin
-              if(port_enb) begin
-                  if (clk_cnt == cfg_reset_period) begin
-                     if(data_available) begin
-                         led_data      <= {green_in,red_in,blue_in};
-                         bit_cnt       <= 23;
-                         clk_cnt       <= 0;
-                         txd           <= 1;
-                         data_rd       <= 1;
-                         state         <= STATE_TRANSMIT;
-                     end
-                  end
-                  else begin
-                    // De-assert txd       , and wait for 75 us.
-                     txd        <= 0;
-                     clk_cnt    <= clk_cnt + 1;
-                  end
-              end else begin
-                 txd        <= 0;
-                 clk_cnt    <= 0;
-              end
-           end // case: STATE_RESET
-           STATE_TRANSMIT: begin
-              // Advance cycle counter
-              if (clk_cnt   == cfg_clk_period) begin
-                 txd        <= 1;
-                 clk_cnt    <= 'h0;
-                 if (bit_cnt != 0) begin
-                     bit_cnt <= bit_cnt -1;
-                     // Start sending next bit of data
-                     led_data     <= {led_data [22:0], 1'b0};
-                 end else begin
-                    if(data_available) begin // if new data available
-                        led_data      <= {green_in,red_in,blue_in};
-                        bit_cnt       <= 23;
-                        data_rd       <= 1;
-                    end else begin
-                       state   <= STATE_RESET;
-                    end
-
-                 end
-              end else begin
-                  data_rd       <= 0;
-                  // De-assert txd   after a certain amount of time, depending on if you're transmitting a 1 or 0.
-                  if (led_data[23] == 0 && clk_cnt   >= cfg_th0_period) begin
-                     txd   <= 0;
-                  end
-                  else if (led_data[23] == 1 && clk_cnt   >= cfg_th1_period) begin
-                     txd   <= 0;
-                  end
-                  clk_cnt   <= clk_cnt   + 1;
-              end
-           end
-         endcase
-      end
-   end
-   
-endmodule
-
diff --git a/verilog/rtl/pinmux/src/ws281x_reg.sv b/verilog/rtl/pinmux/src/ws281x_reg.sv
deleted file mode 100644
index 31f25c1..0000000
--- a/verilog/rtl/pinmux/src/ws281x_reg.sv
+++ /dev/null
@@ -1,278 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//      http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
-//
-//////////////////////////////////////////////////////////////////////
-////                                                              ////
-////  ws281x Register                                             ////
-////                                                              ////
-////  This file is part of the riscduino cores project            ////
-////  https://github.com/dineshannayya/riscduino.git              ////
-////                                                              ////
-////  Description                                                 ////
-////     Manages the 4x ws281x driver register                    ////
-////                                                              ////
-////  To Do:                                                      ////
-////    nothing                                                   ////
-////                                                              ////
-////  Author(s):                                                  ////
-////      - Dinesh Annayya, dinesha@opencores.org                 ////
-////                                                              ////
-////  Revision :                                                  ////
-////    0.1 - 23rd Aug 2022, Dinesh A                             ////
-////          initial version                                     ////
-//////////////////////////////////////////////////////////////////////
-
-
-module ws281x_reg  #(   parameter NP = 2,     // Number of PORT
-                        parameter DW = 32,    // DATA WIDTH
-                        parameter AW = 4,     // ADDRESS WIDTH
-                        parameter BW = 4      // BYTE WIDTH
-                    ) (
-                       // System Signals
-                       // Inputs
-		               input logic           mclk                 ,
-                       input logic           h_reset_n            ,
-
-		               // Reg Bus Interface Signal
-                       input logic           reg_cs               ,
-                       input logic           reg_wr               ,
-                       input logic [AW-1:0]  reg_addr             ,
-                       input logic [DW-1:0]  reg_wdata            ,
-                       input logic [BW-1:0]  reg_be               ,
-
-                       // Outputs
-                       output logic [DW-1:0] reg_rdata            ,
-                       output logic          reg_ack              ,
-
-                       output logic[15:0]    cfg_reset_period     ,   // Reset period interm of clk
-                       output logic [9:0]    cfg_clk_period       ,   // Total bit clock period
-                       output logic [9:0]    cfg_th0_period        ,   // bit-0 drive low period
-                       output logic [9:0]    cfg_th1_period        ,   // bit-1 drive low period
-
-                       // wd281x port-0 data
-                       output  logic          port0_enb            ,
-                       input  logic          port0_rd             ,
-                       output logic [23:0]   port0_data           ,
-                       output logic          port0_dval           ,
-
-                       // wd281x port-1 data
-                       output  logic          port1_enb            ,
-                       input  logic          port1_rd             ,
-                       output logic [23:0]   port1_data           ,
-                       output logic          port1_dval           
-
-                       //// wd281x port-2 data
-                       //output  logic          port2_enb            ,
-                       //input  logic          port2_rd             ,
-                       //output logic [23:0]   port2_data           ,
-                       //output logic          port2_dval           ,
-
-                       //// wd281x port-3 data
-                       //output  logic         port3_enb            ,
-                       //input  logic          port3_rd             ,    
-                       //output logic [23:0]   port3_data           ,
-                       //output logic          port3_dval             
-
-
-                ); 
-
-//-----------------------------------------------------------------------
-// Internal Wire Declarations
-//-----------------------------------------------------------------------
-
-logic          sw_rd_en              ;
-logic          sw_wr_en              ;
-logic [AW-1:0] sw_addr               ; 
-logic [DW-1:0] sw_reg_wdata          ;
-logic [BW-1:0] sw_be                 ;
-
-logic [DW-1:0] reg_out               ;
-logic [DW-1:0] reg_0                 ; 
-logic [DW-1:0] reg_1                 ; 
-logic [DW-1:0] reg_2                 ; 
-logic [DW-1:0] reg_3                 ; 
-
-logic [NP-1:0] fifo_full             ;
-logic [NP-1:0] fifo_empty            ;
-logic [NP-1:0] fifo_wr               ;
-logic [NP-1:0] fifo_rd               ;
-logic [23:0]   fifo_rdata[0:NP-1]    ;
-logic [NP-1:0] port_op_done          ;
-
-assign       sw_addr       = reg_addr;
-assign       sw_be         = reg_be;
-assign       sw_rd_en      = reg_cs & !reg_wr;
-assign       sw_wr_en      = reg_cs & reg_wr;
-assign       sw_reg_wdata  = reg_wdata;
-
-//-----------------------------------------------------------------------
-// register read enable and write enable decoding logic
-//-----------------------------------------------------------------------
-wire   sw_wr_en_0  = sw_wr_en  & (sw_addr == 4'h0);
-wire   sw_wr_en_1  = sw_wr_en  & (sw_addr == 4'h1);
-wire   sw_wr_en_2  = sw_wr_en  & (sw_addr == 4'h2);
-wire   sw_wr_en_3  = sw_wr_en  & (sw_addr == 4'h3);
-wire   sw_wr_en_4  = sw_wr_en  & (sw_addr == 4'h4) & !fifo_full[0]; // Write only if fifo is not full
-wire   sw_wr_en_5  = sw_wr_en  & (sw_addr == 4'h5) & !fifo_full[1]; // Write only if fifo is not full
-wire   sw_wr_en_6  = sw_wr_en  & (sw_addr == 4'h6) & !fifo_full[2]; // Write only if fifo is not full
-wire   sw_wr_en_7  = sw_wr_en  & (sw_addr == 4'h7) & !fifo_full[3]; // Write only if fifo is not full
-
-
-// Generated seperate write enable case to block the reg ack duration when fifo is full
-wire  sw_wr_en_t =  sw_wr_en_0 | sw_wr_en_1 | sw_wr_en_2 | sw_wr_en_3 | sw_wr_en_4 | sw_wr_en_5 | sw_wr_en_6 | sw_wr_en_7;
-
-
-always @ (posedge mclk or negedge h_reset_n)
-begin : preg_out_Seq
-   if (h_reset_n == 1'b0) begin
-      reg_rdata  <= 'h0;
-      reg_ack    <= 1'b0;
-   end else if (reg_cs && !reg_ack && sw_rd_en) begin
-      reg_rdata  <= reg_out[DW-1:0] ;
-      reg_ack    <= 1'b1;
-   end else if (reg_cs && !reg_ack && sw_wr_en_t) begin // Block Ack generation when FIFO is full
-      reg_ack    <= 1'b1;
-   end else begin
-      reg_ack    <= 1'b0;
-   end
-end
-
-//----------------------------------------
-// Hardware Command Register
-//  Assumption: Maximum 32 port assumed
-//----------------------------------------
-
-assign port0_enb    = reg_0[0];
-assign port1_enb    = reg_0[1];
-//assign port2_enb    = reg_0[2];
-//assign port3_enb    = reg_0[3];
-
- generic_register	#(.WD(4)) u_reg_0(
-	      //List of Inputs
-	      .we         ({4{sw_wr_en_0 & 
-                          sw_be[0]   }}),
-	      .data_in    (sw_reg_wdata[3:0]),
-	      .reset_n    (h_reset_n        ),
-	      .clk        (mclk             ),
-	      
-	      //List of Outs
-	      .data_out   (reg_0[3:0]       )
-	      );
-
-// CONFIG-0
-assign cfg_reset_period = reg_1[15:0];
-gen_16b_reg  #(32'h0) u_reg_1	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n           ),
-	      .clk        (mclk                ),
-	      .cs         (sw_wr_en_1          ),
-	      .we         (sw_be[1:0]          ),		 
-	      .data_in    (sw_reg_wdata[15:0]  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_1[15:0]         )
-	      );
-
-// CONFIG-1
-
-assign cfg_th1_period  = reg_2[29:20]; // High Exit Period for Data-1
-assign cfg_th0_period  = reg_2[19:10];  // High Exit period for Data-0
-assign cfg_clk_period  = reg_2[9:0];
-
-gen_32b_reg  #(32'h0) u_reg_2	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_2    ),
-	      .we         (sw_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_2         )
-	      );
-
-
-
-assign port0_dval =!fifo_empty[0];
-assign port1_dval =!fifo_empty[1];
-//assign port2_dval =!fifo_empty[2];
-//assign port3_dval =!fifo_empty[3];
-
-assign reg_3 = { 2'b00,fifo_empty[1],fifo_full[1],
-                 2'b00,fifo_empty[0],fifo_full[0]};
-
-
-//----------------------------------------------------
-//  DATA FIFO
-//----------------------------------------------------
-
-assign fifo_wr[0] = sw_wr_en_4 & reg_ack;
-assign fifo_wr[1] = sw_wr_en_5 & reg_ack;
-//assign fifo_wr[2] = sw_wr_en_6 & reg_ack;
-//assign fifo_wr[3] = sw_wr_en_7 & reg_ack;
-
-assign fifo_rd[0] = port0_rd;
-assign fifo_rd[1] = port1_rd;
-//assign fifo_rd[2] = port2_rd;
-//assign fifo_rd[3] = port3_rd;
-
-assign port0_data = fifo_rdata[0];
-assign port1_data = fifo_rdata[1];
-//assign port2_data = fifo_rdata[2];
-//assign port3_data = fifo_rdata[3];
-
-genvar port;
-generate
-for (port = 0; $unsigned(port) < NP; port=port+1) begin : gfifo
-
-sync_fifo #(.W(24), .D(8)) u_fifo
-           (
-            .clk         (mclk                 ),
-	        .reset_n     (h_reset_n            ),
-		    .wr_en       (fifo_wr[port]        ),
-		    .wr_data     (sw_reg_wdata[23:0]   ),
-		    .full        (fifo_full[port]      ),
-		    .empty       (fifo_empty[port]     ),
-		    .rd_en       (fifo_rd[port]        ),
-		    .rd_data     (fifo_rdata[port]     ) 
-           );
-
-end
-endgenerate // gfifo
-
-
-//-----------------------------------------------------------------------
-// Register Read Path Multiplexer instantiation
-//-----------------------------------------------------------------------
-
-always_comb
-begin 
-  reg_out [31:0] = 32'h0;
-
-  case (sw_addr [3:0])
-    4'b0000    : reg_out [31:0] = reg_0 [31:0];     
-    4'b0001    : reg_out [31:0] = reg_1 [31:0];    
-    4'b0010    : reg_out [31:0] = reg_2 [31:0];     
-    4'b0011    : reg_out [31:0] = reg_3 [31:0];    
-    4'b0100    : reg_out [31:0] = port0_data;
-    4'b0101    : reg_out [31:0] = port1_data;
-//    4'b0110    : reg_out [31:0] = port2_data;
-//    4'b0111    : reg_out [31:0] = port3_data;
-    default    : reg_out [31:0] = 32'h0;
-  endcase
-end
-endmodule
diff --git a/verilog/rtl/pinmux/src/ws281x_top.sv b/verilog/rtl/pinmux/src/ws281x_top.sv
deleted file mode 100644
index 6ab06fa..0000000
--- a/verilog/rtl/pinmux/src/ws281x_top.sv
+++ /dev/null
@@ -1,194 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//      http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
-//
-//////////////////////////////////////////////////////////////////////
-////                                                              ////
-////  ws281x Top                                                  ////
-////                                                              ////
-////  This file is part of the riscduino cores project            ////
-////  https://github.com/dineshannayya/riscduino.git              ////
-////                                                              ////
-////  Description                                                 ////
-////                                                              ////
-////  To Do:                                                      ////
-////    nothing                                                   ////
-////                                                              ////
-////  Author(s):                                                  ////
-////      - Dinesh Annayya, dinesha@opencores.org                 ////
-////                                                              ////
-////  Revision :                                                  ////
-////    0.1 - 23rd Aug 2022, Dinesh A                             ////
-////          initial version                                     ////
-//////////////////////////////////////////////////////////////////////
-
-module ws281x_top  (
-                       // System Signals
-                       // Inputs
-		               input logic           mclk,
-                       input logic           h_reset_n,
-
-		               // Reg Bus Interface Signal
-                       input logic           reg_cs,
-                       input logic           reg_wr,
-                       input logic [3:0]     reg_addr,
-                       input logic [31:0]    reg_wdata,
-                       input logic [3:0]     reg_be,
-
-                       // Outputs
-                       output logic [31:0]   reg_rdata,
-                       output logic          reg_ack,
-
-                       output logic [3:0]    txd 
-
-                ); 
-
-assign txd[2] = txd[0];
-assign txd[3] = txd[1];
-
-logic[15:0]    cfg_reset_period     ;   // Reset period interm of clk
-logic [9:0]    cfg_clk_period       ;   // Total bit clock period
-logic [9:0]    cfg_th0_period       ;   // bit-0 drive low period
-logic [9:0]    cfg_th1_period       ;   // bit-1 drive low period
-
-logic [23:0]   port0_data           ;
-logic [23:0]   port1_data           ;
-//logic [23:0]   port2_data         ;
-//logic [23:0]   port3_data         ;
-
-ws281x_reg  u_reg (
-                .mclk                ( mclk                 ),
-                .h_reset_n           ( h_reset_n            ),
-
-                .reg_cs              ( reg_cs               ),
-                .reg_wr              ( reg_wr               ),
-                .reg_addr            ( reg_addr             ),
-                .reg_wdata           ( reg_wdata            ),
-                .reg_be              ( reg_be               ),
-
-                .reg_rdata           ( reg_rdata            ),
-                .reg_ack             ( reg_ack              ),
-
-                .cfg_reset_period    ( cfg_reset_period     ),   // Reset period interm of clk
-                .cfg_clk_period      ( cfg_clk_period       ),   // Total bit clock period
-                .cfg_th0_period      ( cfg_th0_period       ),   // bit-0 drive low period
-                .cfg_th1_period      ( cfg_th1_period       ),   // bit-1 drive low period
-
-                .port0_enb           ( port0_enb            ),
-                .port0_rd            ( port0_rd             ),
-                .port0_data          ( port0_data           ),
-                .port0_dval          ( port0_dval           ),
-
-                .port1_enb           ( port1_enb            ),
-                .port1_rd            ( port1_rd             ),
-                .port1_data          ( port1_data           ),
-                .port1_dval          ( port1_dval           )
-
-                //.port2_enb           ( port2_enb            ),
-                //.port2_rd            ( port2_rd             ),
-                //.port2_data          ( port2_data           ),
-                //.port2_dval          ( port2_dval           ),
-
-                //.port3_enb           ( port3_enb            ),
-                //.port3_rd            ( port3_rd             ),    
-                //.port3_data          ( port3_data           ),
-                //.port3_dval          ( port3_dval           )  
-
-                ); 
-
-
-//wx281x port-0
-ws281x_driver u_txd_0(
-    .clk                 (mclk             ), // Clock input.
-    .reset_n             (h_reset_n        ), // Resets the internal state of the driver
-
-    .cfg_reset_period    (cfg_reset_period ), // Reset period interm of clk
-    .cfg_clk_period      (cfg_clk_period   ), // Total bit clock period
-    .cfg_th0_period      (cfg_th0_period   ), // bit-0 drive low period
-    .cfg_th1_period      (cfg_th1_period   ), // bit-1 drive low period
-
-    .port_enb            (port0_enb        ), 
-    .data_available      (port0_dval       ), 
-    .green_in            (port0_data[23:16]), // 8-bit green data
-    .red_in              (port0_data[15:8] ), // 8-bit red data
-    .blue_in             (port0_data[7:0]  ), // 8-bit blue data
-    .data_rd             (port0_rd         ), // data read
-
-    .txd                 (txd[0]           )  // Signal to send to WS2811 chain.
-    );
-
-//wx281x port-1
-ws281x_driver u_txd_1(
-    .clk                 (mclk             ), // Clock input.
-    .reset_n             (h_reset_n        ), // Resets the internal state of the driver
-
-    .cfg_reset_period    (cfg_reset_period ), // Reset period interm of clk
-    .cfg_clk_period      (cfg_clk_period   ), // Total bit clock period
-    .cfg_th0_period      (cfg_th0_period   ), // bit-0 drive low period
-    .cfg_th1_period      (cfg_th1_period   ), // bit-1 drive low period
-
-    .port_enb            (port1_enb        ), 
-    .data_available      (port1_dval       ), 
-    .green_in            (port1_data[23:16]), // 8-bit green data
-    .red_in              (port1_data[15:8] ), // 8-bit red data
-    .blue_in             (port1_data[7:0]  ), // 8-bit blue data
-    .data_rd             (port1_rd         ), // data read
-
-    .txd                 (txd[1]           )  // Signal to send to WS2811 chain.
-    );
-
-/***
-//wx281x port-2
-ws281x_driver u_txd_2(
-    .clk                 (mclk             ), // Clock input.
-    .reset_n             (h_reset_n        ), // Resets the internal state of the driver
-
-    .cfg_reset_period    (cfg_reset_period ), // Reset period interm of clk
-    .cfg_clk_period      (cfg_clk_period   ), // Total bit clock period
-    .cfg_th0_period      (cfg_th0_period   ), // bit-0 drive low period
-    .cfg_th1_period      (cfg_th1_period   ), // bit-1 drive low period
-
-    .port_enb            (port2_enb     ), 
-    .data_available      (port2_dval       ), 
-    .green_in            (port2_data[23:16]), // 8-bit green data
-    .red_in              (port2_data[15:8] ), // 8-bit red data
-    .blue_in             (port2_data[7:0]  ), // 8-bit blue data
-    .data_rd             (port2_rd         ), // data read
-
-    .txd                 (txd[2]           )  // Signal to send to WS2811 chain.
-    );
-
-//wx281x port-3
-ws281x_driver u_txd_3(
-    .clk                 (mclk             ), // Clock input.
-    .reset_n             (h_reset_n        ), // Resets the internal state of the driver
-
-    .cfg_reset_period    (cfg_reset_period ), // Reset period interm of clk
-    .cfg_clk_period      (cfg_clk_period   ), // Total bit clock period
-    .cfg_th0_period      (cfg_th0_period   ), // bit-0 drive low period
-    .cfg_th1_period      (cfg_th1_period   ), // bit-1 drive low period
-
-    .port_enb            (port3_enb        ), 
-    .data_available      (port3_dval       ), 
-    .green_in            (port3_data[23:16]), // 8-bit green data
-    .red_in              (port3_data[15:8] ), // 8-bit red data
-    .blue_in             (port3_data[7:0]  ), // 8-bit blue data
-    .data_rd             (port3_rd         ), // data read
-
-    .txd                 (txd[3]           )  // Signal to send to WS2811 chain.
-    );
-***/
-endmodule
diff --git a/verilog/rtl/pwm/src/pwm.sv b/verilog/rtl/pwm/src/pwm.sv
index 922c369..2ed7a03 100644
--- a/verilog/rtl/pwm/src/pwm.sv
+++ b/verilog/rtl/pwm/src/pwm.sv
@@ -45,7 +45,7 @@
 logic [15:0]  pwm_cnt     ; // PWM counter
 logic         cnt_trg     ;
 logic         pwm_wfm_i   ;
-logic         pwm_wfm_hold;
+logic         pwm_wfm_r   ; // Register pwm
 logic         comp0_match ;
 logic         comp1_match ;
 logic         comp2_match ;
@@ -214,25 +214,27 @@
 always @(posedge mclk or negedge h_reset_n)
 begin 
    if ( ~h_reset_n ) begin
-      pwm_wfm_hold  <= 1'b0;
-   end else if(cfg_pwm_enb) begin
-      pwm_wfm_hold <= pwm_wfm_i;
+      pwm_wfm_r     <= 1'b0;
+   end else begin 
+      if(cfg_pwm_hold) begin
+          if(cfg_pwm_enb ) begin
+              pwm_wfm_r   <= pwm_wfm_i;
+          end 
+      end else begin
+         pwm_wfm_r   <= pwm_wfm_i;
+      end
    end
 end
 
+
 //--------------------------------------------
 // Final Waveform output generation based
 // on pwm_hold and pwm_inv combination
 //--------------------------------------------
 always_comb begin
    pwm_wfm_o = 0;
-   if(!cfg_pwm_enb && cfg_pwm_hold) begin
-      if(cfg_pwm_inv) pwm_wfm_o = !pwm_wfm_hold;
-      else            pwm_wfm_o = pwm_wfm_hold;
-   end else begin
-      if(cfg_pwm_inv) pwm_wfm_o = !pwm_wfm_i;
-      else            pwm_wfm_o = pwm_wfm_i;
-   end
+   if(cfg_pwm_inv) pwm_wfm_o = !pwm_wfm_r;
+   else            pwm_wfm_o = pwm_wfm_r;
 end
 
 //----------------------------------------
diff --git a/verilog/rtl/pwm/src/pwm_top.sv b/verilog/rtl/pwm/src/pwm_top.sv
index 7e914d2..a95845e 100644
--- a/verilog/rtl/pwm/src/pwm_top.sv
+++ b/verilog/rtl/pwm/src/pwm_top.sv
@@ -99,23 +99,6 @@
 `define SEL_PWM4    3'b101   // PWM-4
 `define SEL_PWM5    3'b110   // PWM-5
 
-assign reg_rdata = (reg_addr[4:2] == `SEL_GLBL)  ? {reg_rdata_glbl} : 
-	               (reg_addr[4:2] == `SEL_PWM0)  ? {reg_rdata_pwm0} :
-	               (reg_addr[4:2] == `SEL_PWM1)  ? {reg_rdata_pwm1} :
-	               (reg_addr[4:2] == `SEL_PWM2)  ? {reg_rdata_pwm2} :'h0;
-
-assign reg_ack   = (reg_addr[4:2] == `SEL_GLBL)  ? reg_ack_glbl   : 
-	               (reg_addr[4:2] == `SEL_PWM0)  ? reg_ack_pwm0   : 
-	               (reg_addr[4:2] == `SEL_PWM1)  ? reg_ack_pwm1   : 
-	               (reg_addr[4:2] == `SEL_PWM2)  ? reg_ack_pwm2   : 'h0;
-
-assign reg_cs_glbl    = (reg_addr[4:2] == `SEL_GLBL) ? reg_cs : 1'b0;
-assign reg_cs_pwm[0]  = (reg_addr[4:2] == `SEL_PWM0) ? reg_cs : 1'b0;
-assign reg_cs_pwm[1]  = (reg_addr[4:2] == `SEL_PWM1) ? reg_cs : 1'b0;
-assign reg_cs_pwm[2]  = (reg_addr[4:2] == `SEL_PWM2) ? reg_cs : 1'b0;
-assign reg_cs_pwm[3]  = (reg_addr[4:2] == `SEL_PWM3) ? reg_cs : 1'b0;
-assign reg_cs_pwm[4]  = (reg_addr[4:2] == `SEL_PWM4) ? reg_cs : 1'b0;
-assign reg_cs_pwm[5]  = (reg_addr[4:2] == `SEL_PWM5) ? reg_cs : 1'b0;
 
 pwm_glbl_reg  u_glbl_reg (
 		       .mclk             (mclk                ),
@@ -317,4 +300,36 @@
 assign pwm_ovflow[5]  = 1'b0;
 assign gpio_tgr[5]    = 1'b0;
 
+
+//-----------------------------------
+// Register Select
+//------------------------------------
+logic [2:0] blk_sel;
+
+always @(posedge mclk or negedge h_reset_n)
+begin
+   if(h_reset_n == 1'b0) begin
+      blk_sel <= 3'b0;
+   end else begin
+      blk_sel <= reg_addr[4:2];
+   end
+end
+
+assign reg_rdata = (blk_sel == `SEL_GLBL)  ? {reg_rdata_glbl} : 
+	               (blk_sel == `SEL_PWM0)  ? {reg_rdata_pwm0} :
+	               (blk_sel == `SEL_PWM1)  ? {reg_rdata_pwm1} :
+	               (blk_sel == `SEL_PWM2)  ? {reg_rdata_pwm2} :'h0;
+
+assign reg_ack   = (blk_sel == `SEL_GLBL)  ? reg_ack_glbl   : 
+	               (blk_sel == `SEL_PWM0)  ? reg_ack_pwm0   : 
+	               (blk_sel == `SEL_PWM1)  ? reg_ack_pwm1   : 
+	               (blk_sel == `SEL_PWM2)  ? reg_ack_pwm2   : 'h0;
+
+assign reg_cs_glbl    = (reg_addr[4:2] == `SEL_GLBL) ? reg_cs : 1'b0;
+assign reg_cs_pwm[0]  = (reg_addr[4:2] == `SEL_PWM0) ? reg_cs : 1'b0;
+assign reg_cs_pwm[1]  = (reg_addr[4:2] == `SEL_PWM1) ? reg_cs : 1'b0;
+assign reg_cs_pwm[2]  = (reg_addr[4:2] == `SEL_PWM2) ? reg_cs : 1'b0;
+assign reg_cs_pwm[3]  = (reg_addr[4:2] == `SEL_PWM3) ? reg_cs : 1'b0;
+assign reg_cs_pwm[4]  = (reg_addr[4:2] == `SEL_PWM4) ? reg_cs : 1'b0;
+assign reg_cs_pwm[5]  = (reg_addr[4:2] == `SEL_PWM5) ? reg_cs : 1'b0;
 endmodule
diff --git a/verilog/rtl/qspim b/verilog/rtl/qspim
index ee4d23b..abbea37 160000
--- a/verilog/rtl/qspim
+++ b/verilog/rtl/qspim
@@ -1 +1 @@
-Subproject commit ee4d23bb8a6edf84545f1aa0ba5db083d12440d7
+Subproject commit abbea3730b710e8ee387dad5bcd2242dc10a59e7
diff --git a/verilog/rtl/user_params.svh b/verilog/rtl/user_params.svh
index 325c436..d4ae6a0 100644
--- a/verilog/rtl/user_params.svh
+++ b/verilog/rtl/user_params.svh
@@ -4,13 +4,14 @@
 // ASCI Representation of RISC = 32'h8273_8343
 parameter CHIP_SIGNATURE = 32'h8273_8343;
 // Software Reg-1, Release date: <DAY><MONTH><YEAR>
-parameter CHIP_RELEASE_DATE = 32'h1409_2022;
+parameter CHIP_RELEASE_DATE = 32'h2011_2022;
 // Software Reg-2: Poject Revison 5.1 = 0005200
-parameter CHIP_REVISION   = 32'h0005_5000;
+parameter CHIP_REVISION   = 32'h0005_8000;
 
-parameter SKEW_RESET_VAL = 32'b0000_0000_1000_0111_1001_1000_1001_0111;
+parameter CLK_SKEW1_RESET_VAL = 32'b0000_0000_1000_1100_1010_1010_1001_0011;
+parameter CLK_SKEW2_RESET_VAL = 32'b0000_0000_0000_0000_0000_0000_0000_0111;
 
-parameter PSTRAP_DEFAULT_VALUE = 15'b000_0111_1010_0000;
+parameter PSTRAP_DEFAULT_VALUE = 15'b000_0011_1010_0000;
 
 /*****************************************************
 pad_strap_in decoding
@@ -40,8 +41,8 @@
                  0 - Cache Enable
                  1 - Bypass cache  (Default)
      bit [10]  - Riscv SRAM clock edge selection
-                 0 - Normal
-                 1 - Invert        (Default)
+                 0 - Normal      (Default)
+                 1 - Invert        
      bit [12:11] - Skew selection
                  2'b00 - Default value  (Default)
                  2'b01 - Default value + 2               
@@ -138,13 +139,13 @@
 `define STRAP_RISCV_CACHE_BYPASS   13
 `define STRAP_RISCV_SRAM_CLK_EDGE  14
 `define STRAP_QSPI_PRE_SRAM        15      // Previous SRAM Strap Status
-`define STRAP_CLK_SKEW_WI          17:16
-`define STRAP_CLK_SKEW_WH          19:18
-`define STRAP_CLK_SKEW_RISCV       21:20
-`define STRAP_CLK_SKEW_QSPI        23:22
-`define STRAP_CLK_SKEW_UART        25:24
-`define STRAP_CLK_SKEW_PINMUX      27:26
-`define STRAP_CLK_SKEW_QSPI_CO     29:28
+`define STRAP_SCLK_SKEW_WI          17:16
+`define STRAP_SCLK_SKEW_WH          19:18
+`define STRAP_SCLK_SKEW_RISCV       21:20
+`define STRAP_SCLK_SKEW_QSPI        23:22
+`define STRAP_SCLK_SKEW_UART        25:24
+`define STRAP_SCLK_SKEW_PINMUX      27:26
+`define STRAP_SCLK_SKEW_QSPI_CO     29:28
 `define STRAP_QSPI_INIT_BYPASS     30
 `define STRAP_SOFT_REBOOT_REQ      31
 
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index f6d483d..3fcb96f 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -277,7 +277,11 @@
 ////          2'b00 - Auto, 2'b01 - 50Mhz, 2'b10 - 4Mhz,          ////
 ////          2'b11 - LA control                                  ////
 ////          B. digital_pll is re-synth with maual placement     ////
-////                                                              ////
+////    5.6  Sept 29 2022, Dinesh A                               ////
+////         A. 4x 8bit DAC Integration                           ////
+////         B. clock skew control added for core clock           ////
+////    5.8  Nov 20, 2022, Dinesh A                               ////
+////         A. Pinmux - Double Sync added for usb & i2c inter    ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
 //// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
@@ -602,22 +606,23 @@
 
 
 wire [7:0]                     cfg_glb_ctrl                           ;
-wire [31:0]                    cfg_clk_ctrl1                          ;
-wire [3:0]                     cfg_cska_wi                            ; // clock skew adjust for wishbone interconnect
-wire [3:0]                     cfg_cska_wh                            ; // clock skew adjust for web host
+wire [31:0]                    cfg_clk_skew_ctrl1                     ;
+wire [31:0]                    cfg_clk_skew_ctrl2                     ;
+wire [3:0]                     cfg_wcska_wi                            ; // clock skew adjust for wishbone interconnect
+wire [3:0]                     cfg_wcska_wh                            ; // clock skew adjust for web host
 
-wire [3:0]                     cfg_cska_riscv                         ; // clock skew adjust for riscv
-wire [3:0]                     cfg_cska_uart                          ; // clock skew adjust for uart
-wire [3:0]                     cfg_cska_qspi                          ; // clock skew adjust for spi
-wire [3:0]                     cfg_cska_pinmux                        ; // clock skew adjust for pinmux
-wire [3:0]                     cfg_cska_qspi_co                       ; // clock skew adjust for global reg
+wire [3:0]                     cfg_wcska_riscv                         ; // clock skew adjust for riscv
+wire [3:0]                     cfg_wcska_uart                          ; // clock skew adjust for uart
+wire [3:0]                     cfg_wcska_qspi                          ; // clock skew adjust for spi
+wire [3:0]                     cfg_wcska_pinmux                        ; // clock skew adjust for pinmux
+wire [3:0]                     cfg_wcska_qspi_co                       ; // clock skew adjust for global reg
 
 // Bus Repeater Signals  output from Wishbone Interface
-wire [3:0]                     cfg_cska_riscv_rp                      ; // clock skew adjust for riscv
-wire [3:0]                     cfg_cska_uart_rp                       ; // clock skew adjust for uart
-wire [3:0]                     cfg_cska_qspi_rp                       ; // clock skew adjust for spi
-wire [3:0]                     cfg_cska_pinmux_rp                     ; // clock skew adjust for pinmux
-wire [3:0]                     cfg_cska_qspi_co_rp                    ; // clock skew adjust for global reg
+wire [3:0]                     cfg_wcska_riscv_rp                      ; // clock skew adjust for riscv
+wire [3:0]                     cfg_wcska_uart_rp                       ; // clock skew adjust for uart
+wire [3:0]                     cfg_wcska_qspi_rp                       ; // clock skew adjust for spi
+wire [3:0]                     cfg_wcska_pinmux_rp                     ; // clock skew adjust for pinmux
+wire [3:0]                     cfg_wcska_qspi_co_rp                    ; // clock skew adjust for global reg
 
 wire [31:0]                    irq_lines_rp                           ; // Repeater
 wire                           soft_irq_rp                            ; // Repeater
@@ -759,12 +764,29 @@
 wire                           s_reset_n                              ;
 wire                           cfg_strap_pad_ctrl                     ;
 
+wire                           e_reset_n_rp                           ;
+wire                           p_reset_n_rp                           ;
+wire                           s_reset_n_rp                           ;
+wire                           cfg_strap_pad_ctrl_rp                  ;
+//----------------------------------------------------------------------
+// DAC Config
+//----------------------------------------------------------------------
+wire [7:0]                     cfg_dac0_mux_sel                       ;
+wire [7:0]                     cfg_dac1_mux_sel                       ;
+wire [7:0]                     cfg_dac2_mux_sel                       ;
+wire [7:0]                     cfg_dac3_mux_sel                       ;
+
 //---------------------------------------------------------------------
 // Strap
 //---------------------------------------------------------------------
 wire [31:0]                    system_strap                           ;
 wire [31:0]                    strap_sticky                           ;
 wire [1:0]                     strap_uartm                            ;
+
+wire [31:0]                    system_strap_rp                        ;
+wire [31:0]                    strap_sticky_rp                        ;
+wire [1:0]                     strap_uartm_rp                         ;
+
 wire [1:0]  strap_qspi_flash       = system_strap[`STRAP_QSPI_FLASH];
 wire        strap_qspi_sram        = system_strap[`STRAP_QSPI_SRAM];
 wire        strap_qspi_pre_sram    = system_strap[`STRAP_QSPI_PRE_SRAM];
@@ -782,17 +804,33 @@
 wire                           cfg_bypass_dcache       = cfg_riscv_ctrl[11];
 
 /////////////////////////////////////////////////////////
-// Clock Skew Ctrl
+// System/WB Clock Skew Ctrl
 ////////////////////////////////////////////////////////
 
-assign cfg_cska_wi          = cfg_clk_ctrl1[3:0];
-assign cfg_cska_wh          = cfg_clk_ctrl1[7:4];
-assign cfg_cska_riscv       = cfg_clk_ctrl1[11:8];
-assign cfg_cska_qspi        = cfg_clk_ctrl1[15:12];
-assign cfg_cska_uart        = cfg_clk_ctrl1[19:16];
-assign cfg_cska_pinmux      = cfg_clk_ctrl1[23:20];
-assign cfg_cska_qspi_co     = cfg_clk_ctrl1[27:24];
+assign cfg_wcska_wi          = cfg_clk_skew_ctrl1[3:0];
+assign cfg_wcska_wh          = cfg_clk_skew_ctrl1[7:4];
+assign cfg_wcska_riscv       = cfg_clk_skew_ctrl1[11:8];
+assign cfg_wcska_qspi        = cfg_clk_skew_ctrl1[15:12];
+assign cfg_wcska_uart        = cfg_clk_skew_ctrl1[19:16];
+assign cfg_wcska_pinmux      = cfg_clk_skew_ctrl1[23:20];
+assign cfg_wcska_qspi_co     = cfg_clk_skew_ctrl1[27:24];
 
+/////////////////////////////////////////////////////////
+// RISCV Clock skew control
+/////////////////////////////////////////////////////////
+wire [3:0] cfg_ccska_riscv_intf_rp  ;
+wire [3:0] cfg_ccska_riscv_icon_rp  ;
+wire [3:0] cfg_ccska_riscv_core0_rp ;
+wire [3:0] cfg_ccska_riscv_core1_rp ;
+wire [3:0] cfg_ccska_riscv_core2_rp ;
+wire [3:0] cfg_ccska_riscv_core3_rp ;
+
+wire [3:0] cfg_ccska_riscv_intf   = cfg_clk_skew_ctrl2[3:0];
+wire [3:0] cfg_ccska_riscv_icon   = cfg_clk_skew_ctrl2[7:4];
+wire [3:0] cfg_ccska_riscv_core0  = cfg_clk_skew_ctrl2[11:8];
+wire [3:0] cfg_ccska_riscv_core1  = cfg_clk_skew_ctrl2[15:12];
+wire [3:0] cfg_ccska_riscv_core2  = cfg_clk_skew_ctrl2[19:16];
+wire [3:0] cfg_ccska_riscv_core3  = cfg_clk_skew_ctrl2[23:20];
 
 assign la_data_out[127:0]    = {pinmux_debug,spi_debug,riscv_debug};
 
@@ -817,8 +855,8 @@
           .s_reset_n               (s_reset_n               ),  // soft reset
           .cfg_strap_pad_ctrl      (cfg_strap_pad_ctrl      ),
 	      .system_strap            (system_strap            ),
-	      .strap_sticky            (strap_sticky            ),
-	      .strap_uartm             (strap_uartm             ),
+	      .strap_sticky            (strap_sticky_rp         ),
+	      .strap_uartm             (strap_uartm_rp          ),
 
           .wbd_int_rst_n           (wbd_int_rst_n           ),
           .wbd_pll_rst_n           (wbd_pll_rst_n           ),
@@ -839,7 +877,7 @@
     // Clock Skeq Adjust
           .wbd_clk_int             (wbd_clk_int             ),
           .wbd_clk_wh              (wbd_clk_wh              ),  
-          .cfg_cska_wh             (cfg_cska_wh             ),
+          .cfg_cska_wh             (cfg_wcska_wh             ),
 
     // Slave Port
           .wbs_clk_out             (wbd_clk_int             ),
@@ -854,7 +892,8 @@
           .wbs_ack_i               (wbd_int_ack_o           ),  
           .wbs_err_i               (wbd_int_err_o           ),  
 
-          .cfg_clk_ctrl1           (cfg_clk_ctrl1           ),
+          .cfg_clk_skew_ctrl1      (cfg_clk_skew_ctrl1      ),
+          .cfg_clk_skew_ctrl2      (cfg_clk_skew_ctrl2      ),
 
           .la_data_in              (la_data_in[17:0]        ),
 
@@ -873,7 +912,7 @@
 
 
 // This rtl/gds picked from efabless caravel project 
-digital_pll   u_pll(
+dg_pll   u_pll(
 `ifdef USE_POWER_PINS
     .VPWR                           (vccd1                  ),
     .VGND                           (vssd1                  ),
@@ -897,9 +936,9 @@
           .vccd1                   (vccd1                   ),// User area 1 1.8V supply
           .vssd1                   (vssd1                   ),// User area 1 digital ground
 `endif
-          .wbd_clk_int             (wbd_clk_risc_rp         ), 
-          .cfg_cska_riscv          (cfg_cska_riscv_rp       ), 
-          .wbd_clk_riscv           (wbd_clk_riscv_skew      ),
+          .wbd_clk_int             (wbd_clk_risc_rp            ), 
+          .cfg_wcska_riscv_intf    (cfg_wcska_riscv_rp         ), 
+          .wbd_clk_skew            (wbd_clk_riscv_skew         ),
 
     // Reset
           .pwrup_rst_n             (wbd_int_rst_n           ),
@@ -914,48 +953,55 @@
 	  .cfg_bypass_dcache       (cfg_bypass_dcache       ),
 
     // Clock
-          .core_clk                (cpu_clk                 ),
-          .rtc_clk                 (rtc_clk                 ),
+          .core_clk_int            (cpu_clk                    ),
+          .cfg_ccska_riscv_intf    (cfg_ccska_riscv_intf_rp    ),
+          .cfg_ccska_riscv_icon    (cfg_ccska_riscv_icon_rp    ),
+          .cfg_ccska_riscv_core0   (cfg_ccska_riscv_core0_rp   ),
+          .cfg_ccska_riscv_core1   (cfg_ccska_riscv_core1_rp   ),
+          .cfg_ccska_riscv_core2   (cfg_ccska_riscv_core2_rp   ),
+          .cfg_ccska_riscv_core3   (cfg_ccska_riscv_core3_rp   ),
+
+          .rtc_clk                 (rtc_clk                    ),
 
 
     // IRQ
-          .irq_lines               (irq_lines_rp            ), 
-          .soft_irq                (soft_irq_rp             ), // TODO - Interrupts
+          .irq_lines               (irq_lines_rp               ), 
+          .soft_irq                (soft_irq_rp                ), // TODO - Interrupts
 
     // DFT
-    //    .test_mode               (1'b0                    ), // Moved inside IP
-    //    .test_rst_n              (1'b1                    ), // Moved inside IP
+    //    .test_mode               (1'b0                       ), // Moved inside IP
+    //    .test_rst_n              (1'b1                       ), // Moved inside IP
 
 `ifndef SCR1_TCM_MEM
     // SRAM-0 PORT-0
-          .sram0_clk0         (sram0_clk0                   ),
-          .sram0_csb0         (sram0_csb0                   ),
-          .sram0_web0         (sram0_web0                   ),
-          .sram0_addr0        (sram0_addr0                  ),
-          .sram0_wmask0       (sram0_wmask0                 ),
-          .sram0_din0         (sram0_din0                   ),
-          .sram0_dout0        (sram0_dout0                  ),
+          .sram0_clk0             (sram0_clk0                  ),
+          .sram0_csb0             (sram0_csb0                  ),
+          .sram0_web0             (sram0_web0                  ),
+          .sram0_addr0            (sram0_addr0                 ),
+          .sram0_wmask0           (sram0_wmask0                ),
+          .sram0_din0             (sram0_din0                  ),
+          .sram0_dout0            (sram0_dout0                 ),
     
     // SRAM-0 PORT-0
-          .sram0_clk1         (sram0_clk1                   ),
-          .sram0_csb1         (sram0_csb1                   ),
-          .sram0_addr1        (sram0_addr1                  ),
-          .sram0_dout1        (sram0_dout1                  ),
+          .sram0_clk1             (sram0_clk1                   ),
+          .sram0_csb1             (sram0_csb1                   ),
+          .sram0_addr1            (sram0_addr1                  ),
+          .sram0_dout1            (sram0_dout1                  ),
 
   //  // SRAM-1 PORT-0
-  //      .sram1_clk0         (sram1_clk0                   ),
-  //      .sram1_csb0         (sram1_csb0                   ),
-  //      .sram1_web0         (sram1_web0                   ),
-  //      .sram1_addr0        (sram1_addr0                  ),
-  //      .sram1_wmask0       (sram1_wmask0                 ),
-  //      .sram1_din0         (sram1_din0                   ),
-  //      .sram1_dout0        (sram1_dout0                  ),
+  //      .sram1_clk0             (sram1_clk0                   ),
+  //      .sram1_csb0             (sram1_csb0                   ),
+  //      .sram1_web0             (sram1_web0                   ),
+  //      .sram1_addr0            (sram1_addr0                  ),
+  //      .sram1_wmask0           (sram1_wmask0                 ),
+  //      .sram1_din0             (sram1_din0                   ),
+  //      .sram1_dout0            (sram1_dout0                  ),
   //  
   //  // SRAM PORT-0
-  //      .sram1_clk1         (sram1_clk1                   ),
-  //      .sram1_csb1         (sram1_csb1                   ),
-  //      .sram1_addr1        (sram1_addr1                  ),
-  //      .sram1_dout1        (sram1_dout1                  ),
+  //      .sram1_clk1             (sram1_clk1                   ),
+  //      .sram1_csb1             (sram1_csb1                   ),
+  //      .sram1_addr1            (sram1_addr1                  ),
+  //      .sram1_dout1            (sram1_dout1                  ),
 `endif
     
           .wb_rst_n                (wbd_int_rst_n           ),
@@ -1142,8 +1188,8 @@
           .cfg_init_bypass         (strap_qspi_init_bypass  ),
 
     // Clock Skew Adjust
-          .cfg_cska_sp_co          (cfg_cska_qspi_co_rp     ),
-          .cfg_cska_spi            (cfg_cska_qspi_rp        ),
+          .cfg_cska_sp_co          (cfg_wcska_qspi_co_rp     ),
+          .cfg_cska_spi            (cfg_wcska_qspi_rp        ),
           .wbd_clk_int             (wbd_clk_qspi_rp         ),
           .wbd_clk_spi             (wbd_clk_spi             ),
 
@@ -1175,7 +1221,7 @@
 wb_interconnect  #(
 	`ifndef SYNTHESIS
           .CH_CLK_WD           (4                       ),
-	      .CH_DATA_WD          (53                      )
+	      .CH_DATA_WD          (146                     )
         `endif
 	) u_intercon (
 `ifdef USE_POWER_PINS
@@ -1193,31 +1239,57 @@
                                      wbd_clk_qspi_rp, 
                                      wbd_clk_risc_rp}              ),
 	  .ch_data_in              ({
+                                  strap_sticky[31:0],
+                                  strap_uartm[1:0],
+                                  system_strap[31:0],
+                                  p_reset_n,
+                                  e_reset_n,
+                                  cfg_strap_pad_ctrl,
 			 
 	                              soft_irq,
 			                      irq_lines[31:0],
 
-			                      cfg_cska_qspi_co[3:0],
-		                          cfg_cska_pinmux[3:0],
-			                      cfg_cska_uart[3:0],
-		                          cfg_cska_qspi[3:0],
-                                  cfg_cska_riscv[3:0]
+			                      cfg_ccska_riscv_core3[3:0],
+			                      cfg_ccska_riscv_core2[3:0],
+			                      cfg_ccska_riscv_core1[3:0],
+			                      cfg_ccska_riscv_core0[3:0],
+			                      cfg_ccska_riscv_icon[3:0],
+			                      cfg_ccska_riscv_intf[3:0],
+
+			                      cfg_wcska_qspi_co[3:0],
+		                          cfg_wcska_pinmux[3:0],
+			                      cfg_wcska_uart[3:0],
+		                          cfg_wcska_qspi[3:0],
+                                  cfg_wcska_riscv[3:0]
 			             }                             ),
 	  .ch_data_out             ({
+                                  strap_sticky_rp[31:0],
+                                  strap_uartm_rp[1:0],
+                                  system_strap_rp[31:0],
+                                  p_reset_n_rp,
+                                  e_reset_n_rp,
+                                  cfg_strap_pad_ctrl_rp,
 
 	                              soft_irq_rp,
 			                      irq_lines_rp[31:0],
 
-			                      cfg_cska_qspi_co_rp[3:0],
-		                          cfg_cska_pinmux_rp[3:0],
-			                      cfg_cska_uart_rp[3:0],
-		                          cfg_cska_qspi_rp[3:0],
-                                  cfg_cska_riscv_rp[3:0]
-                                    }                              ),
+			                      cfg_ccska_riscv_core3_rp[3:0],
+			                      cfg_ccska_riscv_core2_rp[3:0],
+			                      cfg_ccska_riscv_core1_rp[3:0],
+			                      cfg_ccska_riscv_core0_rp[3:0],
+			                      cfg_ccska_riscv_icon_rp[3:0],
+			                      cfg_ccska_riscv_intf_rp[3:0],
+
+			                      cfg_wcska_qspi_co_rp[3:0],
+		                          cfg_wcska_pinmux_rp[3:0],
+			                      cfg_wcska_uart_rp[3:0],
+		                          cfg_wcska_qspi_rp[3:0],
+                                  cfg_wcska_riscv_rp[3:0]
+                               } ),
      // Clock Skew adjust
-	  .wbd_clk_int             (wbd_clk_int             ), 
-	  .cfg_cska_wi             (cfg_cska_wi             ), 
-	  .wbd_clk_wi              (wbd_clk_wi_skew         ),
+	  .wbd_clk_int                 (wbd_clk_int             ), 
+	  .cfg_cska_wi                 (cfg_wcska_wi            ), 
+	  .wbd_clk_wi                  (wbd_clk_wi_skew         ),
 
           .clk_i                   (wbd_clk_wi_skew         ), 
           .rst_n                   (wbd_int_rst_n           ),
@@ -1321,7 +1393,7 @@
           .vssd1                   (vssd1                   ),// User area 1 digital ground
 `endif
           .wbd_clk_int             (wbd_clk_uart_rp         ), 
-          .cfg_cska_uart           (cfg_cska_uart_rp        ), 
+          .cfg_cska_uart           (cfg_wcska_uart_rp        ), 
           .wbd_clk_uart            (wbd_clk_uart_skew       ),
 
           .uart_rstn               (uart_rst_n              ), // uart reset
@@ -1379,19 +1451,19 @@
           .vssd1                   (vssd1                   ),// User area 1 digital ground
 `endif
         //clk skew adjust
-          .cfg_cska_pinmux         (cfg_cska_pinmux_rp      ),
+          .cfg_cska_pinmux         (cfg_wcska_pinmux_rp      ),
           .wbd_clk_int             (wbd_clk_pinmux_rp       ),
           .wbd_clk_pinmux          (wbd_clk_pinmux_skew     ),
 
         // System Signals
         // Inputs
           .mclk                    (wbd_clk_pinmux_skew     ),
-          .e_reset_n               (e_reset_n               ),
-          .p_reset_n               (p_reset_n               ),
+          .e_reset_n               (e_reset_n_rp            ),
+          .p_reset_n               (p_reset_n_rp            ),
           .s_reset_n               (wbd_int_rst_n           ),
 
-          .cfg_strap_pad_ctrl      (cfg_strap_pad_ctrl      ),
-          .system_strap            (system_strap            ),
+          .cfg_strap_pad_ctrl      (cfg_strap_pad_ctrl_rp   ),
+          .system_strap            (system_strap_rp         ),
           .strap_sticky            (strap_sticky            ),
 	      .strap_uartm             (strap_uartm             ),
 
@@ -1492,68 +1564,29 @@
        .cfg_pll_fed_div        (cfg_pll_fed_div         ), 
        .cfg_dco_mode           (cfg_dco_mode            ), 
        .cfg_dc_trim            (cfg_dc_trim             ),
-       .pll_ref_clk            (pll_ref_clk             )
+       .pll_ref_clk            (pll_ref_clk             ),
 
+       .cfg_dac0_mux_sel       (cfg_dac0_mux_sel        ),
+       .cfg_dac1_mux_sel       (cfg_dac1_mux_sel        ),
+       .cfg_dac2_mux_sel       (cfg_dac2_mux_sel        ),
+       .cfg_dac3_mux_sel       (cfg_dac3_mux_sel        )
 
    ); 
 
-/***
-sar_adc  u_adc (
+
+dac_top  u_4x8bit_dac(
 `ifdef USE_POWER_PINS
-        .vccd1 (vccd1),// User area 1 1.8V supply
-        .vssd1 (vssd1),// User area 1 digital ground
-        .vccd2 (vccd1), // (vccd2),// User area 2 1.8V supply (analog) - DOTO: Need Fix
-        .vssd2 (vssd1), // (vssd2),// User area 2 ground      (analog) - DOTO: Need Fix
+    .vccd1                 (vdda1                  ),
+    .vssd1                 (vssa1                  ),
 `endif
-
-    
-        .clk           (wbd_clk_adc_rp ),// The clock (digital)
-        .reset_n       (wbd_int_rst_n   ),// Active low reset (digital)
-
-    // Reg Bus Interface Signal
-        .reg_cs        (wbd_adc_stb_o   ),
-        .reg_wr        (wbd_adc_we_o    ),
-        .reg_addr      (wbd_adc_adr_o[7:0] ),
-        .reg_wdata     (wbd_adc_dat_o   ),
-        .reg_be        (wbd_adc_sel_o   ),
-
-    // Outputs
-        .reg_rdata     (wbd_adc_dat_i   ),
-        .reg_ack       (wbd_adc_ack_i   ),
-
-        .pulse1m_mclk  (pulse1m_mclk),
-
-
-	// DAC I/F
-        .sar2dac         (sar2dac       ), 
-        //.analog_dac_out  (analog_dac_out) ,  // TODO: Need to connect to DAC O/P
-        .analog_dac_out  (analog_io[6]) , 
-
-        // ADC Input 
-        .analog_din(analog_io[5:0])    // (Analog)
-
-);
-***/
-
-/****
-* TODO: Need to uncomment the DAC
-DAC_8BIT u_dac (
-     `ifdef USE_POWER_PINS
-        .vdd(vccd2),
-        .gnd(vssd2),
-    `endif 
-        .d0(sar2dac[0]),
-        .d1(sar2dac[1]),
-        .d2(sar2dac[2]),
-        .d3(sar2dac[3]),
-        .d4(sar2dac[4]),
-        .d5(sar2dac[5]),
-        .d6(sar2dac[6]),
-        .d7(sar2dac[7]),
-        .inp1(analog_io[6]),
-        .out_v(analog_dac_out)
-    );
-
-**/
-
+    .Vref (analog_io[23]),
+    .DIn0 (cfg_dac0_mux_sel),
+    .DIn1 (cfg_dac1_mux_sel),
+    .DIn2 (cfg_dac2_mux_sel),
+    .DIn3 (cfg_dac3_mux_sel),
+    .Vout0(analog_io[15]   ),
+    .Vout1(analog_io[16]   ),
+    .Vout2(analog_io[17]   ),
+    .Vout3(analog_io[18]   )
+   );
 endmodule : user_project_wrapper
diff --git a/verilog/rtl/user_reg_map.v b/verilog/rtl/user_reg_map.v
index 28b4293..3c904f9 100644
--- a/verilog/rtl/user_reg_map.v
+++ b/verilog/rtl/user_reg_map.v
@@ -15,6 +15,7 @@
 `define ADDR_SPACE_TIMER   32'h3002_0180
 `define ADDR_SPACE_SEMA    32'h3002_0200
 `define ADDR_SPACE_WS281X  32'h3002_0280
+`define ADDR_SPACE_ANALOG  32'h3002_0300
 `define ADDR_SPACE_WBHOST  32'h3008_0000
 
 //--------------------------------------------------
@@ -125,6 +126,15 @@
 `define SEMA_CFG_LOCK_14      8'h38  // reg_14 - Semaphore Lock Bit-14
 `define SEMA_CFG_STATUS       8'h3C  // reg_15 - Semaphore Lock Status
 
+
+//----------------------------------------------------
+// Analog Configuration
+//----------------------------------------------------
+`define ANALOG_CFG_DAC0          8'h00
+`define ANALOG_CFG_DAC1          8'h04
+`define ANALOG_CFG_DAC2          8'h08
+`define ANALOG_CFG_DAC3          8'h0C
+
 //----------------------------------------------------------
 // QSPI Register Map
 //----------------------------------------------------------
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv
index d56b92a..cc966e2 100644
--- a/verilog/rtl/wb_host/src/wb_host.sv
+++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -142,7 +142,8 @@
        input   logic               wbs_ack_i        ,  // acknowlegement
        input   logic               wbs_err_i        ,  // error
 
-       output logic [31:0]         cfg_clk_ctrl1    ,
+       output logic [31:0]         cfg_clk_skew_ctrl1    ,
+       output logic [31:0]         cfg_clk_skew_ctrl2    ,
 
        input  logic [17:0]         la_data_in       ,
 
@@ -487,7 +488,8 @@
                .wbs_clk_out        (wbs_clk_out    ),  // System clock
 
                .cfg_bank_sel       (cfg_bank_sel  ),
-               .cfg_clk_ctrl1      (cfg_clk_ctrl1  ),
+               .cfg_clk_skew_ctrl1 (cfg_clk_skew_ctrl1  ),
+               .cfg_clk_skew_ctrl2 (cfg_clk_skew_ctrl2  ),
 
                .cfg_fast_sim       (cfg_fast_sim   )
     );
diff --git a/verilog/rtl/wb_host/src/wbh_reg.sv b/verilog/rtl/wb_host/src/wbh_reg.sv
index 5985135..ab3ad2b 100644
--- a/verilog/rtl/wb_host/src/wbh_reg.sv
+++ b/verilog/rtl/wb_host/src/wbh_reg.sv
@@ -61,12 +61,14 @@
 
               
                        output  logic [15:0]  cfg_bank_sel       ,
-                       output logic [31:0]   cfg_clk_ctrl1      ,
+                       output logic [31:0]   cfg_clk_skew_ctrl1 ,
+                       output logic [31:0]   cfg_clk_skew_ctrl2 ,
 
                        output logic          cfg_fast_sim       
     );
 
 logic [2:0]         sw_addr               ;
+logic [3:0]         sw_be                 ;
 logic               sw_rd_en              ;
 logic               sw_wr_en              ;
 logic               sw_wr_en_0            ;
@@ -78,10 +80,10 @@
 logic [31:0]        reg_out               ;
 
 logic [31:0]        reg_0                 ;  // Software_Reg_0
-logic [7:0]         cfg_clk_ctrl2         ;
+logic [7:0]         cfg_clk_ctrl         ;
 logic  [3:0]        cfg_wb_clk_ctrl       ;
 logic  [3:0]        cfg_cpu_clk_ctrl      ;
-logic  [31:0]       cfg_glb_ctrl          ;
+logic  [15:0]       cfg_glb_ctrl          ;
 logic               wbs_clk_div           ;
 logic               wbs_ref_clk_div_2     ;
 logic               wbs_ref_clk_div_4     ;
@@ -89,6 +91,7 @@
 
 
 assign  sw_addr       = reg_addr ;
+assign  sw_be         = reg_be ;
 assign  sw_rd_en      = reg_cs & !reg_wr;
 assign  sw_wr_en      = reg_cs & reg_wr;
 
@@ -120,10 +123,29 @@
 end
 
 
+//-----------------------------------
+// reg-out mux
+//-----------------------------------
+
+always @( *)
+begin 
+  reg_out [31:0] = 'h0;
+
+  case (sw_addr [2:0])
+    3'b000 :   reg_out [31:0] = {8'h0,cfg_clk_ctrl[7:0],cfg_glb_ctrl[15:0]};
+    3'b001 :   reg_out [31:0] = {16'h0,cfg_bank_sel [15:0]};     
+    3'b010 :   reg_out [31:0] = cfg_clk_skew_ctrl1 [31:0];    
+    3'b011 :   reg_out [31:0] = cfg_clk_skew_ctrl2[31:0];    
+    3'b101 :   reg_out [31:0] = system_strap [31:0];     
+    default : reg_out [31:0] = 'h0;
+  endcase
+end
+
+
+//-----------------------------------
+// reg-0
 //-------------------------------------
-// Global + Clock Control
-// -------------------------------------
-assign cfg_glb_ctrl     = reg_0[31:0];
+
 // Reset control
 // On Power-up wb & pll power default enabled
 ctech_buf u_buf_wb_rst        (.A(cfg_glb_ctrl[0] & s_reset_n),.X(wbd_int_rst_n));
@@ -132,38 +154,36 @@
 
 //assign cfg_fast_sim        = cfg_glb_ctrl[8]; 
 ctech_clk_buf u_fastsim_buf (.A (cfg_glb_ctrl[8]), . X(cfg_fast_sim)); // To Bypass Reset FSM initial wait time
-
-
-assign cfg_wb_clk_ctrl      = cfg_clk_ctrl2[3:0];
-assign cfg_cpu_clk_ctrl     = cfg_clk_ctrl2[7:4];
-
-
-always @( *)
-begin 
-  reg_out [31:0] = 'h0;
-
-  case (sw_addr [2:0])
-    3'b000 :   reg_out [31:0] = reg_0;
-    3'b001 :   reg_out [31:0] = {16'h0,cfg_bank_sel [15:0]};     
-    3'b010 :   reg_out [31:0] = cfg_clk_ctrl1 [31:0];    
-    3'b011 :   reg_out [31:0] = {24'h0,cfg_clk_ctrl2 [7:0]};    
-    3'b101 :   reg_out [31:0] = system_strap [31:0];     
-    default : reg_out [31:0] = 'h0;
-  endcase
-end
-
-
-
-generic_register #(32,32'h3  ) u_glb_ctrl (
-	      .we            ({32{sw_wr_en_0}}   ),		 
-	      .data_in       (reg_wdata[31:0]    ),
-	      .reset_n       (e_reset_n         ),
-	      .clk           (mclk         ),
+gen_16b_reg #(16'h3  ) u_glb_ctrl (
+          .cs            (sw_wr_en_0       ),
+	      .we            (sw_be[1:0]       ),		 
+	      .data_in       (reg_wdata[15:0]  ),
+	      .reset_n       (e_reset_n        ),
+	      .clk           (mclk             ),
 	      
 	      //List of Outs
-	      .data_out      (reg_0[31:0])
+	      .data_out      (cfg_glb_ctrl[15:0])
           );
 
+
+//--------------------------------
+// clock control
+//--------------------------------
+assign cfg_wb_clk_ctrl      = cfg_clk_ctrl[3:0];
+assign cfg_cpu_clk_ctrl     = cfg_clk_ctrl[7:4];
+always @ (posedge mclk) begin 
+  if (p_reset_n == 1'b0) begin
+     cfg_clk_ctrl  <= strap_sticky[7:0] ;
+  end
+  else begin 
+     if(sw_wr_en_0 & sw_be[2] ) 
+       cfg_clk_ctrl   <= reg_wdata[23:16];
+  end
+end
+//-------------------------------------------------
+// reg-1
+//-------------------------------------------------
+
 generic_register #(16,16'h1000 ) u_bank_sel (
 	      .we            ({16{sw_wr_en_1}}   ),		 
 	      .data_in       (reg_wdata[15:0]    ),
@@ -175,75 +195,68 @@
           );
 
 //-----------------------------------------------
-// clock control-1
+// reg-2: clock skew control-1
 //----------------------------------------------
 
 wire [31:0] rst_clk_ctrl1;
 
-assign rst_clk_ctrl1[3:0]   = (strap_sticky[`STRAP_CLK_SKEW_WI] == 2'b00) ?  SKEW_RESET_VAL[3:0] :
-                              (strap_sticky[`STRAP_CLK_SKEW_WI] == 2'b01) ?  SKEW_RESET_VAL[3:0] + 2 :
-                              (strap_sticky[`STRAP_CLK_SKEW_WI] == 2'b10) ?  SKEW_RESET_VAL[3:0] + 4 : SKEW_RESET_VAL[3:0]-4;
+assign rst_clk_ctrl1[3:0]   = (strap_sticky[`STRAP_SCLK_SKEW_WI] == 2'b00) ? CLK_SKEW1_RESET_VAL[3:0] :
+                              (strap_sticky[`STRAP_SCLK_SKEW_WI] == 2'b01) ? CLK_SKEW1_RESET_VAL[3:0] + 2 :
+                              (strap_sticky[`STRAP_SCLK_SKEW_WI] == 2'b10) ? CLK_SKEW1_RESET_VAL[3:0] + 4 : CLK_SKEW1_RESET_VAL[3:0]-4;
 
-assign rst_clk_ctrl1[7:4]   = (strap_sticky[`STRAP_CLK_SKEW_WH] == 2'b00) ?  SKEW_RESET_VAL[7:4]  :
-                              (strap_sticky[`STRAP_CLK_SKEW_WH] == 2'b01) ?  SKEW_RESET_VAL[7:4] + 2 :
-                              (strap_sticky[`STRAP_CLK_SKEW_WH] == 2'b10) ?  SKEW_RESET_VAL[7:4] + 4 : SKEW_RESET_VAL[7:4]-4;
+assign rst_clk_ctrl1[7:4]   = (strap_sticky[`STRAP_SCLK_SKEW_WH] == 2'b00) ? CLK_SKEW1_RESET_VAL[7:4]  :
+                              (strap_sticky[`STRAP_SCLK_SKEW_WH] == 2'b01) ? CLK_SKEW1_RESET_VAL[7:4] + 2 :
+                              (strap_sticky[`STRAP_SCLK_SKEW_WH] == 2'b10) ? CLK_SKEW1_RESET_VAL[7:4] + 4 : CLK_SKEW1_RESET_VAL[7:4]-4;
 
-assign rst_clk_ctrl1[11:8]  = (strap_sticky[`STRAP_CLK_SKEW_RISCV] == 2'b00) ?  SKEW_RESET_VAL[11:8]  :
-                              (strap_sticky[`STRAP_CLK_SKEW_RISCV] == 2'b01) ?  SKEW_RESET_VAL[11:8] + 2 :
-                              (strap_sticky[`STRAP_CLK_SKEW_RISCV] == 2'b10) ?  SKEW_RESET_VAL[11:8] + 4 : SKEW_RESET_VAL[11:8]-4;
+assign rst_clk_ctrl1[11:8]  = (strap_sticky[`STRAP_SCLK_SKEW_RISCV] == 2'b00) ?  CLK_SKEW1_RESET_VAL[11:8]  :
+                              (strap_sticky[`STRAP_SCLK_SKEW_RISCV] == 2'b01) ?  CLK_SKEW1_RESET_VAL[11:8] + 2 :
+                              (strap_sticky[`STRAP_SCLK_SKEW_RISCV] == 2'b10) ?  CLK_SKEW1_RESET_VAL[11:8] + 4 : CLK_SKEW1_RESET_VAL[11:8]-4;
 
-assign rst_clk_ctrl1[15:12] = (strap_sticky[`STRAP_CLK_SKEW_QSPI] == 2'b00) ?  SKEW_RESET_VAL[15:12]  :
-                              (strap_sticky[`STRAP_CLK_SKEW_QSPI] == 2'b01) ?  SKEW_RESET_VAL[15:12] + 2 :
-                              (strap_sticky[`STRAP_CLK_SKEW_QSPI] == 2'b10) ?  SKEW_RESET_VAL[15:12] + 4 : SKEW_RESET_VAL[15:12]-4;
+assign rst_clk_ctrl1[15:12] = (strap_sticky[`STRAP_SCLK_SKEW_QSPI] == 2'b00) ?  CLK_SKEW1_RESET_VAL[15:12]  :
+                              (strap_sticky[`STRAP_SCLK_SKEW_QSPI] == 2'b01) ?  CLK_SKEW1_RESET_VAL[15:12] + 2 :
+                              (strap_sticky[`STRAP_SCLK_SKEW_QSPI] == 2'b10) ?  CLK_SKEW1_RESET_VAL[15:12] + 4 : CLK_SKEW1_RESET_VAL[15:12]-4;
 
-assign rst_clk_ctrl1[19:16] = (strap_sticky[`STRAP_CLK_SKEW_UART] == 2'b00) ?  SKEW_RESET_VAL[19:16]  :
-                              (strap_sticky[`STRAP_CLK_SKEW_UART] == 2'b01) ?  SKEW_RESET_VAL[19:16] + 2 :
-                              (strap_sticky[`STRAP_CLK_SKEW_UART] == 2'b10) ?  SKEW_RESET_VAL[19:16] + 4 : SKEW_RESET_VAL[19:16]-4;
+assign rst_clk_ctrl1[19:16] = (strap_sticky[`STRAP_SCLK_SKEW_UART] == 2'b00) ?  CLK_SKEW1_RESET_VAL[19:16]  :
+                              (strap_sticky[`STRAP_SCLK_SKEW_UART] == 2'b01) ?  CLK_SKEW1_RESET_VAL[19:16] + 2 :
+                              (strap_sticky[`STRAP_SCLK_SKEW_UART] == 2'b10) ?  CLK_SKEW1_RESET_VAL[19:16] + 4 : CLK_SKEW1_RESET_VAL[19:16]-4;
 
-assign rst_clk_ctrl1[23:20] = (strap_sticky[`STRAP_CLK_SKEW_PINMUX] == 2'b00) ?  SKEW_RESET_VAL[23:20]  :
-                              (strap_sticky[`STRAP_CLK_SKEW_PINMUX] == 2'b01) ?  SKEW_RESET_VAL[23:20] + 2 :
-                              (strap_sticky[`STRAP_CLK_SKEW_PINMUX] == 2'b10) ?  SKEW_RESET_VAL[23:20] + 4 : SKEW_RESET_VAL[23:20]-4;
+assign rst_clk_ctrl1[23:20] = (strap_sticky[`STRAP_SCLK_SKEW_PINMUX] == 2'b00) ?  CLK_SKEW1_RESET_VAL[23:20]  :
+                              (strap_sticky[`STRAP_SCLK_SKEW_PINMUX] == 2'b01) ?  CLK_SKEW1_RESET_VAL[23:20] + 2 :
+                              (strap_sticky[`STRAP_SCLK_SKEW_PINMUX] == 2'b10) ?  CLK_SKEW1_RESET_VAL[23:20] + 4 : CLK_SKEW1_RESET_VAL[23:20]-4;
 
-assign rst_clk_ctrl1[27:24] = (strap_sticky[`STRAP_CLK_SKEW_QSPI_CO] == 2'b00) ?  SKEW_RESET_VAL[27:24] :
-                              (strap_sticky[`STRAP_CLK_SKEW_QSPI_CO] == 2'b01) ?  SKEW_RESET_VAL[27:24] + 2 :
-                              (strap_sticky[`STRAP_CLK_SKEW_QSPI_CO] == 2'b10) ?  SKEW_RESET_VAL[27:24] + 4 : SKEW_RESET_VAL[27:24]-4;
+assign rst_clk_ctrl1[27:24] = (strap_sticky[`STRAP_SCLK_SKEW_QSPI_CO] == 2'b00) ?  CLK_SKEW1_RESET_VAL[27:24] :
+                              (strap_sticky[`STRAP_SCLK_SKEW_QSPI_CO] == 2'b01) ?  CLK_SKEW1_RESET_VAL[27:24] + 2 :
+                              (strap_sticky[`STRAP_SCLK_SKEW_QSPI_CO] == 2'b10) ?  CLK_SKEW1_RESET_VAL[27:24] + 4 : CLK_SKEW1_RESET_VAL[27:24]-4;
 
 assign rst_clk_ctrl1[31:28] = 4'b0;
 
 
 always @ (posedge mclk ) begin 
   if (p_reset_n == 1'b0) begin
-     cfg_clk_ctrl1  <= rst_clk_ctrl1 ;
+     cfg_clk_skew_ctrl1  <= rst_clk_ctrl1 ;
   end
   else begin 
      if(sw_wr_en_2 ) 
-       cfg_clk_ctrl1   <= reg_wdata[31:0];
+       cfg_clk_skew_ctrl1   <= reg_wdata[31:0];
   end
 end
 
-//--------------------------------
-// clock control-2
-//--------------------------------
-always @ (posedge mclk) begin 
-  if (p_reset_n == 1'b0) begin
-     cfg_clk_ctrl2  <= strap_sticky[7:0] ;
-  end
-  else begin 
-     if(sw_wr_en_3 ) 
-       cfg_clk_ctrl2   <= reg_wdata[7:0];
-  end
-end
-
+//-----------------------------------------------
+// reg-3: clock skew control-2
+//     This skew control the RISCV clock, Since riscv clock need to stable on power-up
+//     we have not given any strap control for it.
+//----------------------------------------------
 
 always @ (posedge mclk ) begin 
   if (p_reset_n == 1'b0) begin
-     cfg_clk_ctrl2  <= strap_sticky[7:0] ;
+     cfg_clk_skew_ctrl2  <= CLK_SKEW2_RESET_VAL ;
   end
   else begin 
      if(sw_wr_en_3 ) 
-       cfg_clk_ctrl2   <= reg_wdata[7:0];
+       cfg_clk_skew_ctrl2   <= reg_wdata[31:0];
   end
 end
+
 //-------------------------------------------------------------
 // Note: system_strap reset (p_reset_n) will be released
 //     eariler than s_reset_n to take care of strap loading