blob: cf834b70d452547d4bc08b86199bdd32b9bf4de1 [file] [log] [blame]
#BUS_SORT
#MANUAL_PLACE
#W
sram0_clk0 0 0 2
sram0_csb0
sram0_web0
sram0_addr0\[0\]
sram0_addr0\[1\]
sram0_addr0\[2\]
sram0_addr0\[3\]
sram0_addr0\[4\]
sram0_addr0\[5\]
sram0_addr0\[6\]
sram0_addr0\[7\]
sram0_addr0\[8\]
sram0_wmask0\[0\]
sram0_wmask0\[1\]
sram0_wmask0\[2\]
sram0_wmask0\[3\]
sram0_din0\[0\]
sram0_din0\[1\]
sram0_din0\[2\]
sram0_din0\[3\]
sram0_din0\[4\]
sram0_din0\[5\]
sram0_din0\[6\]
sram0_din0\[7\]
sram0_din0\[8\]
sram0_din0\[9\]
sram0_din0\[10\]
sram0_din0\[11\]
sram0_din0\[12\]
sram0_din0\[13\]
sram0_din0\[14\]
sram0_din0\[15\]
sram0_din0\[16\]
sram0_din0\[17\]
sram0_din0\[18\]
sram0_din0\[19\]
sram0_din0\[20\]
sram0_din0\[21\]
sram0_din0\[22\]
sram0_din0\[23\]
sram0_din0\[24\]
sram0_din0\[25\]
sram0_din0\[26\]
sram0_din0\[27\]
sram0_din0\[28\]
sram0_din0\[29\]
sram0_din0\[30\]
sram0_din0\[31\]
sram0_dout0\[0\] 0100 0 2
sram0_dout0\[1\]
sram0_dout0\[2\]
sram0_dout0\[3\]
sram0_dout0\[4\]
sram0_dout0\[5\]
sram0_dout0\[6\]
sram0_dout0\[7\]
sram0_dout0\[8\]
sram0_dout0\[9\]
sram0_dout0\[10\]
sram0_dout0\[11\]
sram0_dout0\[12\]
sram0_dout0\[13\]
sram0_dout0\[14\]
sram0_dout0\[15\]
sram0_dout0\[16\]
sram0_dout0\[17\]
sram0_dout0\[18\]
sram0_dout0\[19\]
sram0_dout0\[20\]
sram0_dout0\[21\]
sram0_dout0\[22\]
sram0_dout0\[23\]
sram0_dout0\[24\]
sram0_dout0\[25\]
sram0_dout0\[26\]
sram0_dout0\[27\]
sram0_dout0\[28\]
sram0_dout0\[29\]
sram0_dout0\[30\]
sram0_dout0\[31\]
sram0_clk1 0200 0 2
sram0_csb1
sram0_addr1\[8\]
sram0_addr1\[7\]
sram0_addr1\[6\]
sram0_addr1\[5\]
sram0_addr1\[4\]
sram0_addr1\[3\]
sram0_addr1\[2\]
sram0_addr1\[1\]
sram0_addr1\[0\]
sram0_dout1\[0\] 0250 0 2
sram0_dout1\[1\]
sram0_dout1\[2\]
sram0_dout1\[3\]
sram0_dout1\[4\]
sram0_dout1\[5\]
sram0_dout1\[6\]
sram0_dout1\[7\]
sram0_dout1\[8\]
sram0_dout1\[9\]
sram0_dout1\[10\]
sram0_dout1\[11\]
sram0_dout1\[12\]
sram0_dout1\[13\]
sram0_dout1\[14\]
sram0_dout1\[15\]
sram0_dout1\[16\]
sram0_dout1\[17\]
sram0_dout1\[18\]
sram0_dout1\[19\]
sram0_dout1\[20\]
sram0_dout1\[21\]
sram0_dout1\[22\]
sram0_dout1\[23\]
sram0_dout1\[24\]
sram0_dout1\[25\]
sram0_dout1\[26\]
sram0_dout1\[27\]
sram0_dout1\[28\]
sram0_dout1\[29\]
sram0_dout1\[30\]
sram0_dout1\[31\]
#S
icache_mem_clk0
icache_mem_csb0
icache_mem_web0
icache_mem_addr0\[0\]
icache_mem_addr0\[1\]
icache_mem_addr0\[2\]
icache_mem_addr0\[3\]
icache_mem_addr0\[4\]
icache_mem_addr0\[5\]
icache_mem_addr0\[6\]
icache_mem_addr0\[7\]
icache_mem_addr0\[8\]
icache_mem_wmask0\[0\]
icache_mem_wmask0\[1\]
icache_mem_wmask0\[2\]
icache_mem_wmask0\[3\]
icache_mem_din0\[0\]
icache_mem_din0\[1\]
icache_mem_din0\[2\]
icache_mem_din0\[3\]
icache_mem_din0\[4\]
icache_mem_din0\[5\]
icache_mem_din0\[6\]
icache_mem_din0\[7\]
icache_mem_din0\[8\]
icache_mem_din0\[9\]
icache_mem_din0\[10\]
icache_mem_din0\[11\]
icache_mem_din0\[12\]
icache_mem_din0\[13\]
icache_mem_din0\[14\]
icache_mem_din0\[15\]
icache_mem_din0\[16\]
icache_mem_din0\[17\]
icache_mem_din0\[18\]
icache_mem_din0\[19\]
icache_mem_din0\[20\]
icache_mem_din0\[21\]
icache_mem_din0\[22\]
icache_mem_din0\[23\]
icache_mem_din0\[24\]
icache_mem_din0\[25\]
icache_mem_din0\[26\]
icache_mem_din0\[27\]
icache_mem_din0\[28\]
icache_mem_din0\[29\]
icache_mem_din0\[30\]
icache_mem_din0\[31\]
icache_mem_clk1 100 0 2
icache_mem_csb1
icache_mem_addr1\[8\]
icache_mem_addr1\[7\]
icache_mem_addr1\[6\]
icache_mem_addr1\[5\]
icache_mem_addr1\[4\]
icache_mem_addr1\[3\]
icache_mem_addr1\[2\]
icache_mem_addr1\[1\]
icache_mem_addr1\[0\]
icache_mem_dout1\[0\] 150 0 2
icache_mem_dout1\[1\]
icache_mem_dout1\[2\]
icache_mem_dout1\[3\]
icache_mem_dout1\[4\]
icache_mem_dout1\[5\]
icache_mem_dout1\[6\]
icache_mem_dout1\[7\]
icache_mem_dout1\[8\]
icache_mem_dout1\[9\]
icache_mem_dout1\[10\]
icache_mem_dout1\[11\]
icache_mem_dout1\[12\]
icache_mem_dout1\[13\]
icache_mem_dout1\[14\]
icache_mem_dout1\[15\]
icache_mem_dout1\[16\]
icache_mem_dout1\[17\]
icache_mem_dout1\[18\]
icache_mem_dout1\[19\]
icache_mem_dout1\[20\]
icache_mem_dout1\[21\]
icache_mem_dout1\[22\]
icache_mem_dout1\[23\]
icache_mem_dout1\[24\]
icache_mem_dout1\[25\]
icache_mem_dout1\[26\]
icache_mem_dout1\[27\]
icache_mem_dout1\[28\]
icache_mem_dout1\[29\]
icache_mem_dout1\[30\]
icache_mem_dout1\[31\]
dcache_mem_clk0 400 0 2
dcache_mem_csb0
dcache_mem_web0
dcache_mem_addr0\[0\]
dcache_mem_addr0\[1\]
dcache_mem_addr0\[2\]
dcache_mem_addr0\[3\]
dcache_mem_addr0\[4\]
dcache_mem_addr0\[5\]
dcache_mem_addr0\[6\]
dcache_mem_addr0\[7\]
dcache_mem_addr0\[8\]
dcache_mem_wmask0\[0\]
dcache_mem_wmask0\[1\]
dcache_mem_wmask0\[2\]
dcache_mem_wmask0\[3\]
dcache_mem_din0\[0\]
dcache_mem_din0\[1\]
dcache_mem_din0\[2\]
dcache_mem_din0\[3\]
dcache_mem_din0\[4\]
dcache_mem_din0\[5\]
dcache_mem_din0\[6\]
dcache_mem_din0\[7\]
dcache_mem_din0\[8\]
dcache_mem_din0\[9\]
dcache_mem_din0\[10\]
dcache_mem_din0\[11\]
dcache_mem_din0\[12\]
dcache_mem_din0\[13\]
dcache_mem_din0\[14\]
dcache_mem_din0\[15\]
dcache_mem_din0\[16\]
dcache_mem_din0\[17\]
dcache_mem_din0\[18\]
dcache_mem_din0\[19\]
dcache_mem_din0\[20\]
dcache_mem_din0\[21\]
dcache_mem_din0\[22\]
dcache_mem_din0\[23\]
dcache_mem_din0\[24\]
dcache_mem_din0\[25\]
dcache_mem_din0\[26\]
dcache_mem_din0\[27\]
dcache_mem_din0\[28\]
dcache_mem_din0\[29\]
dcache_mem_din0\[30\]
dcache_mem_din0\[31\]
dcache_mem_dout0\[0\] 500 0 2
dcache_mem_dout0\[1\]
dcache_mem_dout0\[2\]
dcache_mem_dout0\[3\]
dcache_mem_dout0\[4\]
dcache_mem_dout0\[5\]
dcache_mem_dout0\[6\]
dcache_mem_dout0\[7\]
dcache_mem_dout0\[8\]
dcache_mem_dout0\[9\]
dcache_mem_dout0\[10\]
dcache_mem_dout0\[11\]
dcache_mem_dout0\[12\]
dcache_mem_dout0\[13\]
dcache_mem_dout0\[14\]
dcache_mem_dout0\[15\]
dcache_mem_dout0\[16\]
dcache_mem_dout0\[17\]
dcache_mem_dout0\[18\]
dcache_mem_dout0\[19\]
dcache_mem_dout0\[20\]
dcache_mem_dout0\[21\]
dcache_mem_dout0\[22\]
dcache_mem_dout0\[23\]
dcache_mem_dout0\[24\]
dcache_mem_dout0\[25\]
dcache_mem_dout0\[26\]
dcache_mem_dout0\[27\]
dcache_mem_dout0\[28\]
dcache_mem_dout0\[29\]
dcache_mem_dout0\[30\]
dcache_mem_dout0\[31\]
dcache_mem_clk1 600 0 2
dcache_mem_csb1
dcache_mem_addr1\[8\]
dcache_mem_addr1\[7\]
dcache_mem_addr1\[6\]
dcache_mem_addr1\[5\]
dcache_mem_addr1\[4\]
dcache_mem_addr1\[3\]
dcache_mem_addr1\[2\]
dcache_mem_addr1\[1\]
dcache_mem_addr1\[0\]
dcache_mem_dout1\[0\] 650 0 2
dcache_mem_dout1\[1\]
dcache_mem_dout1\[2\]
dcache_mem_dout1\[3\]
dcache_mem_dout1\[4\]
dcache_mem_dout1\[5\]
dcache_mem_dout1\[6\]
dcache_mem_dout1\[7\]
dcache_mem_dout1\[8\]
dcache_mem_dout1\[9\]
dcache_mem_dout1\[10\]
dcache_mem_dout1\[11\]
dcache_mem_dout1\[12\]
dcache_mem_dout1\[13\]
dcache_mem_dout1\[14\]
dcache_mem_dout1\[15\]
dcache_mem_dout1\[16\]
dcache_mem_dout1\[17\]
dcache_mem_dout1\[18\]
dcache_mem_dout1\[19\]
dcache_mem_dout1\[20\]
dcache_mem_dout1\[21\]
dcache_mem_dout1\[22\]
dcache_mem_dout1\[23\]
dcache_mem_dout1\[24\]
dcache_mem_dout1\[25\]
dcache_mem_dout1\[26\]
dcache_mem_dout1\[27\]
dcache_mem_dout1\[28\]
dcache_mem_dout1\[29\]
dcache_mem_dout1\[30\]
dcache_mem_dout1\[31\]
riscv_debug\[0\]
riscv_debug\[1\]
riscv_debug\[2\]
riscv_debug\[3\]
riscv_debug\[4\]
riscv_debug\[5\]
riscv_debug\[6\]
riscv_debug\[7\]
riscv_debug\[8\]
riscv_debug\[9\]
riscv_debug\[10\]
riscv_debug\[11\]
riscv_debug\[12\]
riscv_debug\[13\]
riscv_debug\[14\]
riscv_debug\[15\]
riscv_debug\[16\]
riscv_debug\[17\]
riscv_debug\[18\]
riscv_debug\[19\]
riscv_debug\[20\]
riscv_debug\[21\]
riscv_debug\[22\]
riscv_debug\[23\]
riscv_debug\[24\]
riscv_debug\[25\]
riscv_debug\[26\]
riscv_debug\[27\]
riscv_debug\[28\]
riscv_debug\[29\]
riscv_debug\[30\]
riscv_debug\[31\]
riscv_debug\[32\]
riscv_debug\[33\]
riscv_debug\[34\]
riscv_debug\[35\]
riscv_debug\[36\]
riscv_debug\[37\]
riscv_debug\[38\]
riscv_debug\[39\]
riscv_debug\[40\]
riscv_debug\[41\]
riscv_debug\[42\]
riscv_debug\[43\]
riscv_debug\[44\]
riscv_debug\[45\]
riscv_debug\[46\]
riscv_debug\[47\]
riscv_debug\[48\]
riscv_debug\[49\]
riscv_debug\[50\]
riscv_debug\[51\]
riscv_debug\[52\]
riscv_debug\[53\]
riscv_debug\[54\]
riscv_debug\[55\]
riscv_debug\[56\]
riscv_debug\[57\]
riscv_debug\[58\]
riscv_debug\[59\]
riscv_debug\[60\]
riscv_debug\[61\]
riscv_debug\[62\]
riscv_debug\[63\]
wb_rst_n 750 0
pwrup_rst_n
rst_n
core_clk
rtc_clk
core_debug_sel\[1\]
core_debug_sel\[0\]
cpu_core_rst_n\[1\]
cpu_core_rst_n\[0\]
#E
cfg_cska_riscv\[3\] 0000 0 2
cfg_cska_riscv\[2\]
cfg_cska_riscv\[1\]
cfg_cska_riscv\[0\]
wbd_clk_int
wbd_clk_riscv
wb_clk
wbd_dmem_stb_o 0100 0 2
wbd_dmem_we_o
wbd_dmem_adr_o\[31\]
wbd_dmem_adr_o\[30\]
wbd_dmem_adr_o\[29\]
wbd_dmem_adr_o\[28\]
wbd_dmem_adr_o\[27\]
wbd_dmem_adr_o\[26\]
wbd_dmem_adr_o\[25\]
wbd_dmem_adr_o\[24\]
wbd_dmem_adr_o\[23\]
wbd_dmem_adr_o\[22\]
wbd_dmem_adr_o\[21\]
wbd_dmem_adr_o\[20\]
wbd_dmem_adr_o\[19\]
wbd_dmem_adr_o\[18\]
wbd_dmem_adr_o\[17\]
wbd_dmem_adr_o\[16\]
wbd_dmem_adr_o\[15\]
wbd_dmem_adr_o\[14\]
wbd_dmem_adr_o\[13\]
wbd_dmem_adr_o\[12\]
wbd_dmem_adr_o\[11\]
wbd_dmem_adr_o\[10\]
wbd_dmem_adr_o\[9\]
wbd_dmem_adr_o\[8\]
wbd_dmem_adr_o\[7\]
wbd_dmem_adr_o\[6\]
wbd_dmem_adr_o\[5\]
wbd_dmem_adr_o\[4\]
wbd_dmem_adr_o\[3\]
wbd_dmem_adr_o\[2\]
wbd_dmem_adr_o\[1\]
wbd_dmem_adr_o\[0\]
wbd_dmem_sel_o\[3\]
wbd_dmem_sel_o\[2\]
wbd_dmem_sel_o\[1\]
wbd_dmem_sel_o\[0\]
wbd_dmem_dat_o\[31\]
wbd_dmem_dat_o\[30\]
wbd_dmem_dat_o\[29\]
wbd_dmem_dat_o\[28\]
wbd_dmem_dat_o\[27\]
wbd_dmem_dat_o\[26\]
wbd_dmem_dat_o\[25\]
wbd_dmem_dat_o\[24\]
wbd_dmem_dat_o\[23\]
wbd_dmem_dat_o\[22\]
wbd_dmem_dat_o\[21\]
wbd_dmem_dat_o\[20\]
wbd_dmem_dat_o\[19\]
wbd_dmem_dat_o\[18\]
wbd_dmem_dat_o\[17\]
wbd_dmem_dat_o\[16\]
wbd_dmem_dat_o\[15\]
wbd_dmem_dat_o\[14\]
wbd_dmem_dat_o\[13\]
wbd_dmem_dat_o\[12\]
wbd_dmem_dat_o\[11\]
wbd_dmem_dat_o\[10\]
wbd_dmem_dat_o\[9\]
wbd_dmem_dat_o\[8\]
wbd_dmem_dat_o\[7\]
wbd_dmem_dat_o\[6\]
wbd_dmem_dat_o\[5\]
wbd_dmem_dat_o\[4\]
wbd_dmem_dat_o\[3\]
wbd_dmem_dat_o\[2\]
wbd_dmem_dat_o\[1\]
wbd_dmem_dat_o\[0\]
wbd_dmem_dat_i\[31\]
wbd_dmem_dat_i\[30\]
wbd_dmem_dat_i\[29\]
wbd_dmem_dat_i\[28\]
wbd_dmem_dat_i\[27\]
wbd_dmem_dat_i\[26\]
wbd_dmem_dat_i\[25\]
wbd_dmem_dat_i\[24\]
wbd_dmem_dat_i\[23\]
wbd_dmem_dat_i\[22\]
wbd_dmem_dat_i\[21\]
wbd_dmem_dat_i\[20\]
wbd_dmem_dat_i\[19\]
wbd_dmem_dat_i\[18\]
wbd_dmem_dat_i\[17\]
wbd_dmem_dat_i\[16\]
wbd_dmem_dat_i\[15\]
wbd_dmem_dat_i\[14\]
wbd_dmem_dat_i\[13\]
wbd_dmem_dat_i\[12\]
wbd_dmem_dat_i\[11\]
wbd_dmem_dat_i\[10\]
wbd_dmem_dat_i\[9\]
wbd_dmem_dat_i\[8\]
wbd_dmem_dat_i\[7\]
wbd_dmem_dat_i\[6\]
wbd_dmem_dat_i\[5\]
wbd_dmem_dat_i\[4\]
wbd_dmem_dat_i\[3\]
wbd_dmem_dat_i\[2\]
wbd_dmem_dat_i\[1\]
wbd_dmem_dat_i\[0\]
wbd_dmem_ack_i
wbd_dmem_err_i
wb_dcache_stb_o 0250 0 2
wb_dcache_we_o
wb_dcache_adr_o\[31\]
wb_dcache_adr_o\[30\]
wb_dcache_adr_o\[29\]
wb_dcache_adr_o\[28\]
wb_dcache_adr_o\[27\]
wb_dcache_adr_o\[26\]
wb_dcache_adr_o\[25\]
wb_dcache_adr_o\[24\]
wb_dcache_adr_o\[23\]
wb_dcache_adr_o\[22\]
wb_dcache_adr_o\[21\]
wb_dcache_adr_o\[20\]
wb_dcache_adr_o\[19\]
wb_dcache_adr_o\[18\]
wb_dcache_adr_o\[17\]
wb_dcache_adr_o\[16\]
wb_dcache_adr_o\[15\]
wb_dcache_adr_o\[14\]
wb_dcache_adr_o\[13\]
wb_dcache_adr_o\[12\]
wb_dcache_adr_o\[11\]
wb_dcache_adr_o\[10\]
wb_dcache_adr_o\[9\]
wb_dcache_adr_o\[8\]
wb_dcache_adr_o\[7\]
wb_dcache_adr_o\[6\]
wb_dcache_adr_o\[5\]
wb_dcache_adr_o\[4\]
wb_dcache_adr_o\[3\]
wb_dcache_adr_o\[2\]
wb_dcache_adr_o\[1\]
wb_dcache_adr_o\[0\]
wb_dcache_sel_o\[3\]
wb_dcache_sel_o\[2\]
wb_dcache_sel_o\[1\]
wb_dcache_sel_o\[0\]
wb_dcache_bl_o\[9\]
wb_dcache_bl_o\[8\]
wb_dcache_bl_o\[7\]
wb_dcache_bl_o\[6\]
wb_dcache_bl_o\[5\]
wb_dcache_bl_o\[4\]
wb_dcache_bl_o\[3\]
wb_dcache_bl_o\[2\]
wb_dcache_bl_o\[1\]
wb_dcache_bl_o\[0\]
wb_dcache_bry_o
wb_dcache_dat_o\[31\]
wb_dcache_dat_o\[30\]
wb_dcache_dat_o\[29\]
wb_dcache_dat_o\[28\]
wb_dcache_dat_o\[27\]
wb_dcache_dat_o\[26\]
wb_dcache_dat_o\[25\]
wb_dcache_dat_o\[24\]
wb_dcache_dat_o\[23\]
wb_dcache_dat_o\[22\]
wb_dcache_dat_o\[21\]
wb_dcache_dat_o\[20\]
wb_dcache_dat_o\[19\]
wb_dcache_dat_o\[18\]
wb_dcache_dat_o\[17\]
wb_dcache_dat_o\[16\]
wb_dcache_dat_o\[15\]
wb_dcache_dat_o\[14\]
wb_dcache_dat_o\[13\]
wb_dcache_dat_o\[12\]
wb_dcache_dat_o\[11\]
wb_dcache_dat_o\[10\]
wb_dcache_dat_o\[9\]
wb_dcache_dat_o\[8\]
wb_dcache_dat_o\[7\]
wb_dcache_dat_o\[6\]
wb_dcache_dat_o\[5\]
wb_dcache_dat_o\[4\]
wb_dcache_dat_o\[3\]
wb_dcache_dat_o\[2\]
wb_dcache_dat_o\[1\]
wb_dcache_dat_o\[0\]
wb_dcache_dat_i\[31\]
wb_dcache_dat_i\[30\]
wb_dcache_dat_i\[29\]
wb_dcache_dat_i\[28\]
wb_dcache_dat_i\[27\]
wb_dcache_dat_i\[26\]
wb_dcache_dat_i\[25\]
wb_dcache_dat_i\[24\]
wb_dcache_dat_i\[23\]
wb_dcache_dat_i\[22\]
wb_dcache_dat_i\[21\]
wb_dcache_dat_i\[20\]
wb_dcache_dat_i\[19\]
wb_dcache_dat_i\[18\]
wb_dcache_dat_i\[17\]
wb_dcache_dat_i\[16\]
wb_dcache_dat_i\[15\]
wb_dcache_dat_i\[14\]
wb_dcache_dat_i\[13\]
wb_dcache_dat_i\[12\]
wb_dcache_dat_i\[11\]
wb_dcache_dat_i\[10\]
wb_dcache_dat_i\[9\]
wb_dcache_dat_i\[8\]
wb_dcache_dat_i\[7\]
wb_dcache_dat_i\[6\]
wb_dcache_dat_i\[5\]
wb_dcache_dat_i\[4\]
wb_dcache_dat_i\[3\]
wb_dcache_dat_i\[2\]
wb_dcache_dat_i\[1\]
wb_dcache_dat_i\[0\]
wb_dcache_ack_i
wb_dcache_lack_i
wb_dcache_err_i
wb_dcache_cyc_o
wb_icache_stb_o 450 0 2
wb_icache_we_o
wb_icache_adr_o\[31\]
wb_icache_adr_o\[30\]
wb_icache_adr_o\[29\]
wb_icache_adr_o\[28\]
wb_icache_adr_o\[27\]
wb_icache_adr_o\[26\]
wb_icache_adr_o\[25\]
wb_icache_adr_o\[24\]
wb_icache_adr_o\[23\]
wb_icache_adr_o\[22\]
wb_icache_adr_o\[21\]
wb_icache_adr_o\[20\]
wb_icache_adr_o\[19\]
wb_icache_adr_o\[18\]
wb_icache_adr_o\[17\]
wb_icache_adr_o\[16\]
wb_icache_adr_o\[15\]
wb_icache_adr_o\[14\]
wb_icache_adr_o\[13\]
wb_icache_adr_o\[12\]
wb_icache_adr_o\[11\]
wb_icache_adr_o\[10\]
wb_icache_adr_o\[9\]
wb_icache_adr_o\[8\]
wb_icache_adr_o\[7\]
wb_icache_adr_o\[6\]
wb_icache_adr_o\[5\]
wb_icache_adr_o\[4\]
wb_icache_adr_o\[3\]
wb_icache_adr_o\[2\]
wb_icache_adr_o\[1\]
wb_icache_adr_o\[0\]
wb_icache_sel_o\[3\]
wb_icache_sel_o\[2\]
wb_icache_sel_o\[1\]
wb_icache_sel_o\[0\]
wb_icache_bl_o\[9\]
wb_icache_bl_o\[8\]
wb_icache_bl_o\[7\]
wb_icache_bl_o\[6\]
wb_icache_bl_o\[5\]
wb_icache_bl_o\[4\]
wb_icache_bl_o\[3\]
wb_icache_bl_o\[2\]
wb_icache_bl_o\[1\]
wb_icache_bl_o\[0\]
wb_icache_bry_o
wb_icache_dat_i\[31\]
wb_icache_dat_i\[30\]
wb_icache_dat_i\[29\]
wb_icache_dat_i\[28\]
wb_icache_dat_i\[27\]
wb_icache_dat_i\[26\]
wb_icache_dat_i\[25\]
wb_icache_dat_i\[24\]
wb_icache_dat_i\[23\]
wb_icache_dat_i\[22\]
wb_icache_dat_i\[21\]
wb_icache_dat_i\[20\]
wb_icache_dat_i\[19\]
wb_icache_dat_i\[18\]
wb_icache_dat_i\[17\]
wb_icache_dat_i\[16\]
wb_icache_dat_i\[15\]
wb_icache_dat_i\[14\]
wb_icache_dat_i\[13\]
wb_icache_dat_i\[12\]
wb_icache_dat_i\[11\]
wb_icache_dat_i\[10\]
wb_icache_dat_i\[9\]
wb_icache_dat_i\[8\]
wb_icache_dat_i\[7\]
wb_icache_dat_i\[6\]
wb_icache_dat_i\[5\]
wb_icache_dat_i\[4\]
wb_icache_dat_i\[3\]
wb_icache_dat_i\[2\]
wb_icache_dat_i\[1\]
wb_icache_dat_i\[0\]
wb_icache_ack_i
wb_icache_lack_i
wb_icache_err_i
wb_icache_cyc_o
cpu_intf_rst_n
#N
core0_uid 000 0 2
cpu_core_rst_n_sync\[0\]
core0_imem_req_ack
core0_imem_req
core0_imem_cmd
core0_imem_addr\[31\]
core0_imem_addr\[30\]
core0_imem_addr\[29\]
core0_imem_addr\[28\]
core0_imem_addr\[27\]
core0_imem_addr\[26\]
core0_imem_addr\[25\]
core0_imem_addr\[24\]
core0_imem_addr\[23\]
core0_imem_addr\[22\]
core0_imem_addr\[21\]
core0_imem_addr\[20\]
core0_imem_addr\[19\]
core0_imem_addr\[18\]
core0_imem_addr\[17\]
core0_imem_addr\[16\]
core0_imem_addr\[15\]
core0_imem_addr\[14\]
core0_imem_addr\[13\]
core0_imem_addr\[12\]
core0_imem_addr\[11\]
core0_imem_addr\[10\]
core0_imem_addr\[9\]
core0_imem_addr\[8\]
core0_imem_addr\[7\]
core0_imem_addr\[6\]
core0_imem_addr\[5\]
core0_imem_addr\[4\]
core0_imem_addr\[3\]
core0_imem_addr\[2\]
core0_imem_addr\[1\]
core0_imem_addr\[0\]
core0_imem_bl\[2\]
core0_imem_bl\[1\]
core0_imem_bl\[0\]
core0_imem_rdata\[31\]
core0_imem_rdata\[30\]
core0_imem_rdata\[29\]
core0_imem_rdata\[28\]
core0_imem_rdata\[27\]
core0_imem_rdata\[26\]
core0_imem_rdata\[25\]
core0_imem_rdata\[24\]
core0_imem_rdata\[23\]
core0_imem_rdata\[22\]
core0_imem_rdata\[21\]
core0_imem_rdata\[20\]
core0_imem_rdata\[19\]
core0_imem_rdata\[18\]
core0_imem_rdata\[17\]
core0_imem_rdata\[16\]
core0_imem_rdata\[15\]
core0_imem_rdata\[14\]
core0_imem_rdata\[13\]
core0_imem_rdata\[12\]
core0_imem_rdata\[11\]
core0_imem_rdata\[10\]
core0_imem_rdata\[9\]
core0_imem_rdata\[8\]
core0_imem_rdata\[7\]
core0_imem_rdata\[6\]
core0_imem_rdata\[5\]
core0_imem_rdata\[4\]
core0_imem_rdata\[3\]
core0_imem_rdata\[2\]
core0_imem_rdata\[1\]
core0_imem_rdata\[0\]
core0_imem_resp\[1\]
core0_imem_resp\[0\]
core0_dmem_req_ack 100 0 2
core0_dmem_req
core0_dmem_cmd
core0_dmem_width\[1\]
core0_dmem_width\[0\]
core0_dmem_addr\[31\]
core0_dmem_addr\[30\]
core0_dmem_addr\[29\]
core0_dmem_addr\[28\]
core0_dmem_addr\[27\]
core0_dmem_addr\[26\]
core0_dmem_addr\[25\]
core0_dmem_addr\[24\]
core0_dmem_addr\[23\]
core0_dmem_addr\[22\]
core0_dmem_addr\[21\]
core0_dmem_addr\[20\]
core0_dmem_addr\[19\]
core0_dmem_addr\[18\]
core0_dmem_addr\[17\]
core0_dmem_addr\[16\]
core0_dmem_addr\[15\]
core0_dmem_addr\[14\]
core0_dmem_addr\[13\]
core0_dmem_addr\[12\]
core0_dmem_addr\[11\]
core0_dmem_addr\[10\]
core0_dmem_addr\[9\]
core0_dmem_addr\[8\]
core0_dmem_addr\[7\]
core0_dmem_addr\[6\]
core0_dmem_addr\[5\]
core0_dmem_addr\[4\]
core0_dmem_addr\[3\]
core0_dmem_addr\[2\]
core0_dmem_addr\[1\]
core0_dmem_addr\[0\]
core0_dmem_wdata\[31\]
core0_dmem_wdata\[30\]
core0_dmem_wdata\[29\]
core0_dmem_wdata\[28\]
core0_dmem_wdata\[27\]
core0_dmem_wdata\[26\]
core0_dmem_wdata\[25\]
core0_dmem_wdata\[24\]
core0_dmem_wdata\[23\]
core0_dmem_wdata\[22\]
core0_dmem_wdata\[21\]
core0_dmem_wdata\[20\]
core0_dmem_wdata\[19\]
core0_dmem_wdata\[18\]
core0_dmem_wdata\[17\]
core0_dmem_wdata\[16\]
core0_dmem_wdata\[15\]
core0_dmem_wdata\[14\]
core0_dmem_wdata\[13\]
core0_dmem_wdata\[12\]
core0_dmem_wdata\[11\]
core0_dmem_wdata\[10\]
core0_dmem_wdata\[9\]
core0_dmem_wdata\[8\]
core0_dmem_wdata\[7\]
core0_dmem_wdata\[6\]
core0_dmem_wdata\[5\]
core0_dmem_wdata\[4\]
core0_dmem_wdata\[3\]
core0_dmem_wdata\[2\]
core0_dmem_wdata\[1\]
core0_dmem_wdata\[0\]
core0_dmem_rdata\[31\]
core0_dmem_rdata\[30\]
core0_dmem_rdata\[29\]
core0_dmem_rdata\[28\]
core0_dmem_rdata\[27\]
core0_dmem_rdata\[26\]
core0_dmem_rdata\[25\]
core0_dmem_rdata\[24\]
core0_dmem_rdata\[23\]
core0_dmem_rdata\[22\]
core0_dmem_rdata\[21\]
core0_dmem_rdata\[20\]
core0_dmem_rdata\[19\]
core0_dmem_rdata\[18\]
core0_dmem_rdata\[17\]
core0_dmem_rdata\[16\]
core0_dmem_rdata\[15\]
core0_dmem_rdata\[14\]
core0_dmem_rdata\[13\]
core0_dmem_rdata\[12\]
core0_dmem_rdata\[11\]
core0_dmem_rdata\[10\]
core0_dmem_rdata\[9\]
core0_dmem_rdata\[8\]
core0_dmem_rdata\[7\]
core0_dmem_rdata\[6\]
core0_dmem_rdata\[5\]
core0_dmem_rdata\[4\]
core0_dmem_rdata\[3\]
core0_dmem_rdata\[2\]
core0_dmem_rdata\[1\]
core0_dmem_rdata\[0\]
core0_dmem_resp\[1\]
core0_dmem_resp\[0\]
core0_debug\[48\] 200 0 2
core0_debug\[47\]
core0_debug\[46\]
core0_debug\[45\]
core0_debug\[44\]
core0_debug\[43\]
core0_debug\[42\]
core0_debug\[41\]
core0_debug\[40\]
core0_debug\[39\]
core0_debug\[38\]
core0_debug\[37\]
core0_debug\[36\]
core0_debug\[35\]
core0_debug\[34\]
core0_debug\[33\]
core0_debug\[32\]
core0_debug\[31\]
core0_debug\[30\]
core0_debug\[29\]
core0_debug\[28\]
core0_debug\[27\]
core0_debug\[26\]
core0_debug\[25\]
core0_debug\[24\]
core0_debug\[23\]
core0_debug\[22\]
core0_debug\[21\]
core0_debug\[20\]
core0_debug\[19\]
core0_debug\[18\]
core0_debug\[17\]
core0_debug\[16\]
core0_debug\[15\]
core0_debug\[14\]
core0_debug\[13\]
core0_debug\[12\]
core0_debug\[11\]
core0_debug\[10\]
core0_debug\[9\]
core0_debug\[8\]
core0_debug\[7\]
core0_debug\[6\]
core0_debug\[5\]
core0_debug\[4\]
core0_debug\[3\]
core0_debug\[2\]
core0_debug\[1\]
core0_debug\[0\]
core1_uid 400 0 2
cpu_core_rst_n_sync\[1\]
core1_imem_req_ack
core1_imem_req
core1_imem_cmd
core1_imem_addr\[31\]
core1_imem_addr\[30\]
core1_imem_addr\[29\]
core1_imem_addr\[28\]
core1_imem_addr\[27\]
core1_imem_addr\[26\]
core1_imem_addr\[25\]
core1_imem_addr\[24\]
core1_imem_addr\[23\]
core1_imem_addr\[22\]
core1_imem_addr\[21\]
core1_imem_addr\[20\]
core1_imem_addr\[19\]
core1_imem_addr\[18\]
core1_imem_addr\[17\]
core1_imem_addr\[16\]
core1_imem_addr\[15\]
core1_imem_addr\[14\]
core1_imem_addr\[13\]
core1_imem_addr\[12\]
core1_imem_addr\[11\]
core1_imem_addr\[10\]
core1_imem_addr\[9\]
core1_imem_addr\[8\]
core1_imem_addr\[7\]
core1_imem_addr\[6\]
core1_imem_addr\[5\]
core1_imem_addr\[4\]
core1_imem_addr\[3\]
core1_imem_addr\[2\]
core1_imem_addr\[1\]
core1_imem_addr\[0\]
core1_imem_bl\[2\]
core1_imem_bl\[1\]
core1_imem_bl\[0\]
core1_imem_rdata\[31\]
core1_imem_rdata\[30\]
core1_imem_rdata\[29\]
core1_imem_rdata\[28\]
core1_imem_rdata\[27\]
core1_imem_rdata\[26\]
core1_imem_rdata\[25\]
core1_imem_rdata\[24\]
core1_imem_rdata\[23\]
core1_imem_rdata\[22\]
core1_imem_rdata\[21\]
core1_imem_rdata\[20\]
core1_imem_rdata\[19\]
core1_imem_rdata\[18\]
core1_imem_rdata\[17\]
core1_imem_rdata\[16\]
core1_imem_rdata\[15\]
core1_imem_rdata\[14\]
core1_imem_rdata\[13\]
core1_imem_rdata\[12\]
core1_imem_rdata\[11\]
core1_imem_rdata\[10\]
core1_imem_rdata\[9\]
core1_imem_rdata\[8\]
core1_imem_rdata\[7\]
core1_imem_rdata\[6\]
core1_imem_rdata\[5\]
core1_imem_rdata\[4\]
core1_imem_rdata\[3\]
core1_imem_rdata\[2\]
core1_imem_rdata\[1\]
core1_imem_rdata\[0\]
core1_imem_resp\[1\]
core1_imem_resp\[0\]
core1_dmem_req_ack 0500 0 2
core1_dmem_req
core1_dmem_cmd
core1_dmem_width\[1\]
core1_dmem_width\[0\]
core1_dmem_addr\[31\]
core1_dmem_addr\[30\]
core1_dmem_addr\[29\]
core1_dmem_addr\[28\]
core1_dmem_addr\[27\]
core1_dmem_addr\[26\]
core1_dmem_addr\[25\]
core1_dmem_addr\[24\]
core1_dmem_addr\[23\]
core1_dmem_addr\[22\]
core1_dmem_addr\[21\]
core1_dmem_addr\[20\]
core1_dmem_addr\[19\]
core1_dmem_addr\[18\]
core1_dmem_addr\[17\]
core1_dmem_addr\[16\]
core1_dmem_addr\[15\]
core1_dmem_addr\[14\]
core1_dmem_addr\[13\]
core1_dmem_addr\[12\]
core1_dmem_addr\[11\]
core1_dmem_addr\[10\]
core1_dmem_addr\[9\]
core1_dmem_addr\[8\]
core1_dmem_addr\[7\]
core1_dmem_addr\[6\]
core1_dmem_addr\[5\]
core1_dmem_addr\[4\]
core1_dmem_addr\[3\]
core1_dmem_addr\[2\]
core1_dmem_addr\[1\]
core1_dmem_addr\[0\]
core1_dmem_wdata\[31\]
core1_dmem_wdata\[30\]
core1_dmem_wdata\[29\]
core1_dmem_wdata\[28\]
core1_dmem_wdata\[27\]
core1_dmem_wdata\[26\]
core1_dmem_wdata\[25\]
core1_dmem_wdata\[24\]
core1_dmem_wdata\[23\]
core1_dmem_wdata\[22\]
core1_dmem_wdata\[21\]
core1_dmem_wdata\[20\]
core1_dmem_wdata\[19\]
core1_dmem_wdata\[18\]
core1_dmem_wdata\[17\]
core1_dmem_wdata\[16\]
core1_dmem_wdata\[15\]
core1_dmem_wdata\[14\]
core1_dmem_wdata\[13\]
core1_dmem_wdata\[12\]
core1_dmem_wdata\[11\]
core1_dmem_wdata\[10\]
core1_dmem_wdata\[9\]
core1_dmem_wdata\[8\]
core1_dmem_wdata\[7\]
core1_dmem_wdata\[6\]
core1_dmem_wdata\[5\]
core1_dmem_wdata\[4\]
core1_dmem_wdata\[3\]
core1_dmem_wdata\[2\]
core1_dmem_wdata\[1\]
core1_dmem_wdata\[0\]
core1_dmem_rdata\[31\]
core1_dmem_rdata\[30\]
core1_dmem_rdata\[29\]
core1_dmem_rdata\[28\]
core1_dmem_rdata\[27\]
core1_dmem_rdata\[26\]
core1_dmem_rdata\[25\]
core1_dmem_rdata\[24\]
core1_dmem_rdata\[23\]
core1_dmem_rdata\[22\]
core1_dmem_rdata\[21\]
core1_dmem_rdata\[20\]
core1_dmem_rdata\[19\]
core1_dmem_rdata\[18\]
core1_dmem_rdata\[17\]
core1_dmem_rdata\[16\]
core1_dmem_rdata\[15\]
core1_dmem_rdata\[14\]
core1_dmem_rdata\[13\]
core1_dmem_rdata\[12\]
core1_dmem_rdata\[11\]
core1_dmem_rdata\[10\]
core1_dmem_rdata\[9\]
core1_dmem_rdata\[8\]
core1_dmem_rdata\[7\]
core1_dmem_rdata\[6\]
core1_dmem_rdata\[5\]
core1_dmem_rdata\[4\]
core1_dmem_rdata\[3\]
core1_dmem_rdata\[2\]
core1_dmem_rdata\[1\]
core1_dmem_rdata\[0\]
core1_dmem_resp\[1\]
core1_dmem_resp\[0\]
core1_debug\[48\] 0600 0 2
core1_debug\[47\]
core1_debug\[46\]
core1_debug\[45\]
core1_debug\[44\]
core1_debug\[43\]
core1_debug\[42\]
core1_debug\[41\]
core1_debug\[40\]
core1_debug\[39\]
core1_debug\[38\]
core1_debug\[37\]
core1_debug\[36\]
core1_debug\[35\]
core1_debug\[34\]
core1_debug\[33\]
core1_debug\[32\]
core1_debug\[31\]
core1_debug\[30\]
core1_debug\[29\]
core1_debug\[28\]
core1_debug\[27\]
core1_debug\[26\]
core1_debug\[25\]
core1_debug\[24\]
core1_debug\[23\]
core1_debug\[22\]
core1_debug\[21\]
core1_debug\[20\]
core1_debug\[19\]
core1_debug\[18\]
core1_debug\[17\]
core1_debug\[16\]
core1_debug\[15\]
core1_debug\[14\]
core1_debug\[13\]
core1_debug\[12\]
core1_debug\[11\]
core1_debug\[10\]
core1_debug\[9\]
core1_debug\[8\]
core1_debug\[7\]
core1_debug\[6\]
core1_debug\[5\]
core1_debug\[4\]
core1_debug\[3\]
core1_debug\[2\]
core1_debug\[1\]
core1_debug\[0\]
timer_irq 0700 0 2
timer_val\[63\]
timer_val\[62\]
timer_val\[61\]
timer_val\[60\]
timer_val\[59\]
timer_val\[58\]
timer_val\[57\]
timer_val\[56\]
timer_val\[55\]
timer_val\[54\]
timer_val\[53\]
timer_val\[52\]
timer_val\[51\]
timer_val\[50\]
timer_val\[49\]
timer_val\[48\]
timer_val\[47\]
timer_val\[46\]
timer_val\[45\]
timer_val\[44\]
timer_val\[43\]
timer_val\[42\]
timer_val\[41\]
timer_val\[40\]
timer_val\[39\]
timer_val\[38\]
timer_val\[37\]
timer_val\[36\]
timer_val\[35\]
timer_val\[34\]
timer_val\[33\]
timer_val\[32\]
timer_val\[31\]
timer_val\[30\]
timer_val\[29\]
timer_val\[28\]
timer_val\[27\]
timer_val\[26\]
timer_val\[25\]
timer_val\[24\]
timer_val\[23\]
timer_val\[22\]
timer_val\[21\]
timer_val\[20\]
timer_val\[19\]
timer_val\[18\]
timer_val\[17\]
timer_val\[16\]
timer_val\[15\]
timer_val\[14\]
timer_val\[13\]
timer_val\[12\]
timer_val\[11\]
timer_val\[10\]
timer_val\[9\]
timer_val\[8\]
timer_val\[7\]
timer_val\[6\]
timer_val\[5\]
timer_val\[4\]
timer_val\[3\]
timer_val\[2\]
timer_val\[1\]
timer_val\[0\]
pwrup_rst_n_sync
rst_n_sync
test_mode
test_rst_n