diff --git a/README.md b/README.md
index 8c96f4c..6f3c17d 100644
--- a/README.md
+++ b/README.md
@@ -70,6 +70,8 @@
     * 6 Channel ADC (in Progress)
     * 6 x PWM
     * 3 x Timer (16 Bit), 1us/1ms/1second resolution
+    * 2 x ws281x driver
+    * 16 Hardware Semaphore
     * Pin Compatbible to arduino uno
     * Wishbone compatible design
     * Written in System Verilog
@@ -188,49 +190,50 @@
 
 <table>
   <tr align="center"> <td> ATMGA328 Pin No</td> <td> Functionality           </td> <td> Arudino Pin Name</td> <td> Carvel Pin Mapping                   </td></tr>
-  <tr align="center"> <td> Pin-1           </td> <td> PC6/RESET              </td> <td>                 </td> <td> digital_io[0]                        </td></tr>
-  <tr align="center"> <td> Pin-2           </td> <td> PD0/RXD[0]             </td> <td>  D0             </td> <td> digital_io[1]                        </td></tr>
-  <tr align="center"> <td> Pin-3           </td> <td> PD1/TXD[0]             </td> <td>  D1             </td> <td> digital_io[2]                        </td></tr>
-  <tr align="center"> <td> Pin-4           </td> <td> PD2/RXD[1]/INT0        </td> <td>  D2             </td> <td> digital_io[3]                        </td></tr>
-  <tr align="center"> <td> Pin-5           </td> <td> PD3/INT1/OC2B(PWM0)    </td> <td>  D3             </td> <td> digital_io[4]                        </td></tr>
-  <tr align="center"> <td> Pin-6           </td> <td> PD4/TXD[1]             </td> <td>  D4             </td> <td> digital_io[5]                        </td></tr>
+  <tr align="center"> <td> Pin-1           </td> <td> PC6/RESET              </td> <td>                 </td> <td> digital_io[5]                        </td></tr>
+  <tr align="center"> <td> Pin-2           </td> <td> PD0/RXD[0]             </td> <td>  D0             </td> <td> digital_io[6]                        </td></tr>
+  <tr align="center"> <td> Pin-3           </td> <td> PD1/TXD[0]             </td> <td>  D1             </td> <td> digital_io[7]                        </td></tr>
+  <tr align="center"> <td> Pin-4           </td> <td> PD2/RXD[1]/INT0        </td> <td>  D2             </td> <td> digital_io[8]                        </td></tr>
+  <tr align="center"> <td> Pin-5           </td> <td> PD3/INT1/OC2B(PWM0)    </td> <td>  D3             </td> <td> digital_io[9]                        </td></tr>
+  <tr align="center"> <td> Pin-6           </td> <td> PD4/TXD[1]             </td> <td>  D4             </td> <td> digital_io[10]                        </td></tr>
   <tr align="center"> <td> Pin-7           </td> <td> VCC                    </td> <td>                 </td> <td>  -                                   </td></tr>
   <tr align="center"> <td> Pin-8           </td> <td> GND                    </td> <td>                 </td> <td>  -                                   </td></tr>
-  <tr align="center"> <td> Pin-9           </td> <td> PB6/XTAL1/TOSC1        </td> <td>                 </td> <td> digital_io[6]                        </td></tr>
-  <tr align="center"> <td> Pin-10          </td> <td> PB7/XTAL2/TOSC2        </td> <td>                 </td> <td> digital_io[7]                        </td></tr>
-  <tr align="center"> <td> Pin-11          </td> <td> PD5/SS[3]/OC0B(PWM1)/T1      </td> <td> D5              </td> <td> digital_io[8]                        </td></tr>
-  <tr align="center"> <td> Pin-12          </td> <td> PD6/SS[2]/OC0A(PWM2)/AIN0    </td> <td> D6              </td> <td> digital_io[9] /analog_io[2]          </td></tr>
-  <tr align="center"> <td> Pin-13          </td> <td> PD7/A1N1               </td> <td> D7              </td> <td> digital_io[10]/analog_io[3]          </td></tr>
-  <tr align="center"> <td> Pin-14          </td> <td> PB0/CLKO/ICP1          </td> <td> D8              </td> <td> digital_io[11]                       </td></tr>
-  <tr align="center"> <td> Pin-15          </td> <td> PB1/SS[1]OC1A(PWM3)         </td> <td> D9              </td> <td> digital_io[12]                       </td></tr>
-  <tr align="center"> <td> Pin-16          </td> <td> PB2/SS[0]/OC1B(PWM4)      </td> <td> D10             </td> <td> digital_io[13]                       </td></tr>
-  <tr align="center"> <td> Pin-17          </td> <td> PB3/MOSI/OC2A(PWM5)    </td> <td> D11             </td> <td> digital_io[14]                       </td></tr>
-  <tr align="center"> <td> Pin-18          </td> <td> PB4/MISO               </td> <td> D12             </td> <td> digital_io[15]                       </td></tr>
-  <tr align="center"> <td> Pin-19          </td> <td> PB5/SCK                </td> <td> D13             </td> <td> digital_io[16]                       </td></tr>
+  <tr align="center"> <td> Pin-9           </td> <td> PB6/XTAL1/TOSC1        </td> <td>                 </td> <td> digital_io[11]                        </td></tr>
+  <tr align="center"> <td> Pin-10          </td> <td> PB7/XTAL2/TOSC2        </td> <td>                 </td> <td> digital_io[12]                        </td></tr>
+  <tr align="center"> <td> Pin-11          </td> <td> PD5/SS[3]/OC0B(PWM1)/T1      </td> <td> D5        </td> <td> digital_io[13]                        </td></tr>
+  <tr align="center"> <td> Pin-12          </td> <td> PD6/SS[2]/OC0A(PWM2)/AIN0    </td> <td> D6        </td> <td> digital_io[14] /analog_io[2]          </td></tr>
+  <tr align="center"> <td> Pin-13          </td> <td> PD7/A1N1               </td> <td> D7              </td> <td> digital_io[15]/analog_io[3]          </td></tr>
+  <tr align="center"> <td> Pin-14          </td> <td> PB0/CLKO/ICP1          </td> <td> D8              </td> <td> digital_io[16]                       </td></tr>
+  <tr align="center"> <td> Pin-15          </td> <td> PB1/SS[1]OC1A(PWM3)         </td> <td> D9         </td> <td> digital_io[17]                       </td></tr>
+  <tr align="center"> <td> Pin-16          </td> <td> PB2/SS[0]/OC1B(PWM4)      </td> <td> D10          </td> <td> digital_io[18]                       </td></tr>
+  <tr align="center"> <td> Pin-17          </td> <td> PB3/MOSI/OC2A(PWM5)    </td> <td> D11             </td> <td> digital_io[19]                       </td></tr>
+  <tr align="center"> <td> Pin-18          </td> <td> PB4/MISO               </td> <td> D12             </td> <td> digital_io[20]                       </td></tr>
+  <tr align="center"> <td> Pin-19          </td> <td> PB5/SCK                </td> <td> D13             </td> <td> digital_io[21]                       </td></tr>
   <tr align="center"> <td> Pin-20          </td> <td> AVCC                   </td> <td>                 </td> <td> -                                    </td></tr>
   <tr align="center"> <td> Pin-21          </td> <td> AREF                   </td> <td>                 </td> <td> analog_io[10]                        </td></tr>
   <tr align="center"> <td> Pin-22          </td> <td> GND                    </td> <td>                 </td> <td> -                                    </td></tr>
-  <tr align="center"> <td> Pin-23          </td> <td> PC0/ADC0               </td> <td>  A0             </td> <td> digital_io[18]/analog_io[11]         </td></tr>
-  <tr align="center"> <td> Pin-24          </td> <td> PC1/ADC1               </td> <td>  A1             </td> <td> digital_io[19]/analog_io[12]         </td></tr>
-  <tr align="center"> <td> Pin-25          </td> <td> PC2/ADC2               </td> <td>  A2             </td> <td> digital_io[20]/analog_io[13]         </td></tr>
-  <tr align="center"> <td> Pin-26          </td> <td> PC3/ADC3               </td> <td>  A3             </td> <td> digital_io[21]/analog_io[14]         </td></tr>
-  <tr align="center"> <td> Pin-27          </td> <td> PC4/ADC4/SDA           </td> <td>  A4             </td> <td> digital_io[22]/analog_io[15]         </td></tr>
-  <tr align="center"> <td> Pin-28          </td> <td> PC5/ADC5/SCL           </td> <td>  A5             </td> <td> digital_io[23]/analog_io[16]         </td></tr>
+  <tr align="center"> <td> Pin-23          </td> <td> PC0/uartm_rxd/ADC0     </td> <td>  A0             </td> <td> digital_io[22]/analog_io[11]         </td></tr>
+  <tr align="center"> <td> Pin-24          </td> <td> PC1/uartm/ADC1         </td> <td>  A1             </td> <td> digital_io[23]/analog_io[12]         </td></tr>
+  <tr align="center"> <td> Pin-25          </td> <td> PC2/usb_dp/ADC2        </td> <td>  A2             </td> <td> digital_io[24]/analog_io[13]         </td></tr>
+  <tr align="center"> <td> Pin-26          </td> <td> PC3/usb_dn/ADC3        </td> <td>  A3             </td> <td> digital_io[25]/analog_io[14]         </td></tr>
+  <tr align="center"> <td> Pin-27          </td> <td> PC4/ADC4/SDA           </td> <td>  A4             </td> <td> digital_io[26]/analog_io[15]         </td></tr>
+  <tr align="center"> <td> Pin-28          </td> <td> PC5/ADC5/SCL           </td> <td>  A5             </td> <td> digital_io[27]/analog_io[16]         </td></tr>
   <tr align="center"> <td colspan="4">   Additional Pad used for Externam ROM/RAM/USB </td></tr>
-  <tr align="center"> <td> Sflash          </td> <td> sflash_sck             </td> <td>                 </td> <td> digital_io[24]                       </td></tr>
-  <tr align="center"> <td> SFlash          </td> <td> sflash_ss0             </td> <td>                 </td> <td> digital_io[25]                       </td></tr>
-  <tr align="center"> <td> SFlash          </td> <td> sflash_ss1             </td> <td>                 </td> <td> digital_io[26]                       </td></tr>
-  <tr align="center"> <td> SFlash          </td> <td> sflash_ss2             </td> <td>                 </td> <td> digital_io[27]                       </td></tr>
-  <tr align="center"> <td> SFlash          </td> <td> sflash_ss3             </td> <td>                 </td> <td> digital_io[28]                       </td></tr>
-  <tr align="center"> <td> SFlash          </td> <td> sflash_io0             </td> <td>                 </td> <td> digital_io[29]                       </td></tr>
-  <tr align="center"> <td> SFlash          </td> <td> sflash_io1             </td> <td>                 </td> <td> digital_io[30]                       </td></tr>
-  <tr align="center"> <td> SFlash          </td> <td> sflash_io2             </td> <td>                 </td> <td> digital_io[31]                       </td></tr>
-  <tr align="center"> <td> SFlash          </td> <td> sflash_io3             </td> <td>                 </td> <td> digital_io[32]                       </td></tr>
-  <tr align="center"> <td> SSRAM           </td> <td> dbg_clk_mon            </td> <td>                 </td> <td> digital_io[33]                       </td></tr>
-  <tr align="center"> <td> SSRAM           </td> <td> uartm rxd              </td> <td>                 </td> <td> digital_io[34]                       </td></tr>
-  <tr align="center"> <td> SSRAM           </td> <td> uartm txd              </td> <td>                 </td> <td> digital_io[35]                       </td></tr>
-  <tr align="center"> <td> usb1.1          </td> <td> usb_dp                 </td> <td>                 </td> <td> digital_io[36]                       </td></tr>
-  <tr align="center"> <td> usb1.1          </td> <td> usb_dn                 </td> <td>                 </td> <td> digital_io[37]                       </td></tr>
+  <tr align="center"> <td> Sflash          </td> <td> sflash_sck             </td> <td>                 </td> <td> digital_io[28]                       </td></tr>
+  <tr align="center"> <td> SFlash          </td> <td> sflash_ss0             </td> <td>                 </td> <td> digital_io[29]                       </td></tr>
+  <tr align="center"> <td> SFlash          </td> <td> sflash_ss1             </td> <td>                 </td> <td> digital_io[30]                       </td></tr>
+  <tr align="center"> <td> SFlash          </td> <td> sflash_ss2             </td> <td>                 </td> <td> digital_io[31]                       </td></tr>
+  <tr align="center"> <td> SFlash          </td> <td> sflash_ss3             </td> <td>                 </td> <td> digital_io[32]                       </td></tr>
+  <tr align="center"> <td> SFlash          </td> <td> sflash_io0             </td> <td>                 </td> <td> digital_io[33]                       </td></tr>
+  <tr align="center"> <td> SFlash          </td> <td> sflash_io1             </td> <td>                 </td> <td> digital_io[34]                       </td></tr>
+  <tr align="center"> <td> SFlash          </td> <td> sflash_io2             </td> <td>                 </td> <td> digital_io[35]                       </td></tr>
+  <tr align="center"> <td> SFlash          </td> <td> sflash_io3             </td> <td>                 </td> <td> digital_io[36]                       </td></tr>
+  <tr align="center"> <td> DEBUG           </td> <td> dbg_clk_mon            </td> <td>                 </td> <td> digital_io[37]                       </td></tr>
+  <tr align="center"> <td> SPARE           </td> <td> PA0                    </td> <td>                 </td> <td> digital_io[0]                       </td></tr>
+  <tr align="center"> <td> SPARE           </td> <td> PA1                    </td> <td>                 </td> <td> digital_io[1]                       </td></tr>
+  <tr align="center"> <td> SPARE           </td> <td> PA2                    </td> <td>                 </td> <td> digital_io[2]                       </td></tr>
+  <tr align="center"> <td> SPARE           </td> <td> PA3                    </td> <td>                 </td> <td> digital_io[3]                       </td></tr>
+  <tr align="center"> <td> SPARE           </td> <td> PA4                     </td> <td>                </td> <td> digital_io[4]                       </td></tr>
 </table>
 
 
@@ -251,8 +254,8 @@
 Following Design changes are done on the basic version of syntacore RISC core
 ```
    * Some of the sv syntex are changed to standard verilog format to make compatibile with opensource tool iverilog & yosys
-   * local Instruction Memory is increased from 4 to 8 location
-   * Instruction Request are changed from Single word to 4 Word Burst
+   * local Instruction Memory depth increased from 4 to 8 location
+   * Instruction Mem Request are changed from Single word to 4 Word Burst
    * Multiplication and Divsion are changed to improve timing
    * Additional pipe line stages added to improve the RISC timing closure near to 50Mhz
    * 2KB instruction cache 
@@ -372,180 +375,6 @@
 
 
 
-# SOC Register Map
-##### Register Map: Wishbone HOST
-
-| Offset | Name       | Description   |
-| ------ | ---------  | ------------- |
-| 0x00   | GLBL_CTRL  | [RW] Global Wishbone Access Control Register |
-| 0x04   | BANK_CTRL  | [RW] Bank Selection, MSB 8 bit Address |
-| 0x08   | CLK_SKEW_CTRL1| [RW] Clock Skew Control2 |
-| 0x0c   | CLK_SKEW_CTRL2 | [RW] Clock Skew Control2 |
-
-##### Register: GLBL_CTRL
-
-| Bits  | Name          | Description    |
-| ----  | ----          | -------------- |
-| 31:24 | Resevered     | Unsused |
-| 23:20 | RTC_CLK_CTRL  | RTC Clock Div Selection |
-| 19:16 | CPU_CLK_CTRL  | CPU Clock Div Selection |
-| 15:12 | SDARM_CLK_CTRL| SDRAM Clock Div Selection |
-| 10:8  | WB_CLK_CTRL   | Core Wishbone Clock Div Selection |
-|   7   | UART_I2C_SEL  | 0 - UART , 1 - I2C Master IO Selection |
-|   5   | I2C_RST       | I2C Reset Control |
-|   4   | UART_RST      | UART Reset Control |
-|   3   | SDRAM_RST     | SDRAM Reset Control |
-|   2   | SPI_RST       | SPI Reset Control |
-|   1   | CPU_RST       | CPU Reset Control |
-|   0   | WB_RST        | Wishbone Core Reset Control |
-
-##### Register: BANK_CTRL
-
-| Bits  | Name          | Description    |
-| ----  | ----          | -------------- |
-| 31:24 | Resevered     | Unsused |
-| 7:0   | BANK_SEL      | Holds the upper 8 bit address core Wishbone Address |
-
-##### Register: CLK_SKEW_CTRL1
-
-| Bits  | Name          | Description    |
-| ----  | ----          | -------------- |
-| 31:28 | Resevered     | Unsused |
-| 27:24 | CLK_SKEW_WB   | WishBone Core Clk Skew Control |
-| 23:20 | CLK_SKEW_GLBL | Glbal Register Clk Skew Control |
-| 19:16 | CLK_SKEW_SDRAM| SDRAM Clk Skew Control |
-| 15:12 | CLK_SKEW_SPI  | SPI Clk Skew Control |
-| 11:8  | CLK_SKEW_UART | UART/I2C Clk Skew Control |
-| 7:4   | CLK_SKEW_RISC | RISC Clk Skew Control |
-| 3:0   | CLK_SKEW_WI   | Wishbone Clk Skew Control |
-
-##### Register Map: SPI MASTER
-
-| Offset | Name       | Description   |
-| ------ | ---------  | ------------- |
-| 0x00   | GLBL_CTRL  | [RW] Global SPI Access Control Register |
-| 0x04   | DMEM_CTRL1 | [RW] Direct SPI Memory Access Control Register1 |
-| 0x08   | DMEM_CTRL2 | [RW] Direct SPI Memory Access Control Register2 |
-| 0x0c   | IMEM_CTRL1 | [RW] Indirect SPI Memory Access Control Register1 |
-| 0x10   | IMEM_CTRL2 | [RW] Indirect SPI Memory Access Control Register2 |
-| 0x14   | IMEM_ADDR  | [RW] Indirect SPI Memory Address  |
-| 0x18   | IMEM_WDATA | [W]  Indirect SPI Memory Write Data |
-| 0x1c   | IMEM_RDATA | [R]  Indirect SPI Memory Read Data |
-| 0x20   | SPI_STATUS | [R] SPI Debug Status |
-
-##### Register: GLBL_CTRL
-
-| Bits  | Name        | Description    |
-| ----  | ----        | -------------- |
-| 31:16 | Resevered   | Unsused |
-| 15:8  | SPI_CLK_DIV | SPI Clock Div Rato Selection |
-| 7:4   | Reserved    | Unused |
-| 3:2   | CS_LATE     | CS DE_ASSERTION CONTROL |
-| 1:0   | CS_EARLY    | CS ASSERTION CONTROL |
-
-##### Register: DMEM_CTRL1
-
-| Bits | Name       | Description    |
-| ---- | ----       | -------------- |
-| 31:9 | Resevered  | Unsused        |
-| 8    | FSM_RST    | Direct Mem State Machine Reset |
-| 7:6  | SPI_SWITCH | Phase at which SPI Mode need to switch |
-| 5:4  | SPI_MODE   | SPI Mode, 0 - Single, 1 - Dual, 2 - Quad, 3 - QDDR |
-| 3:0  | CS_SELECT  | CHIP SELECT |
-
-##### Register: DMEM_CTRL2
-
-| Bits | Name       | Description    |
-| ---- | ----       | -------------- |
-| 31:24 | DATA_CNT  | Total Data Byte Count        |
-| 23:22 | DUMMY_CNT | Total Dummy Byte Count |
-| 21:20 | ADDR_CNT  | Total Address Byte Count |
-| 19:16 | SPI_SEQ   | SPI Access Sequence |
-| 15:8  | MODE_REG  | Mode Register Value |
-| 7:0   | CMD_REG   | Command Register Value |
-
-##### Register: IMEM_CTRL1
-
-| Bits | Name       | Description    |
-| ---- | ----       | -------------- |
-| 31:9 | Resevered  | Unsused        |
-| 8    | FSM_RST    | InDirect Mem State Machine Reset |
-| 7:6  | SPI_SWITCH | Phase at which SPI Mode need to switch |
-| 5:4  | SPI_MODE   | SPI Mode, 0 - Single, 1 - Dual, 2 - Quad, 3 - QDDR |
-| 3:0  | CS_SELECT  | CHIP SELECT |
-
-##### Register: IMEM_CTRL2
-
-| Bits | Name       | Description    |
-| ---- | ----       | -------------- |
-| 31:24 | DATA_CNT  | Total Data Byte Count        |
-| 23:22 | DUMMY_CNT | Total Dummy Byte Count |
-| 21:20 | ADDR_CNT  | Total Address Byte Count |
-| 19:16 | SPI_SEQ   | SPI Access Sequence |
-| 15:8  | MODE_REG  | Mode Register Value |
-| 7:0   | CMD_REG   | Command Register Value |
-
-##### Register: IMEM_ADDR
-
-| Bits | Name       | Description    |
-| ---- | ----       | -------------- |
-| 31:0 | ADDR       | Indirect Memory Address  |
-
-##### Register: IMEM_WDATA
-
-| Bits | Name       | Description    |
-| ---- | ----       | -------------- |
-| 31:0 | WDATA      | Indirect Memory Write Data  |
-
-##### Register: IMEM_RDATA
-
-| Bits | Name       | Description    |
-| ---- | ----       | -------------- |
-| 31:0 | RDATA      | Indirect Memory Read Data  |
-
-##### Register: SPI_STATUS
-
-| Bits | Name       | Description    |
-| ---- | ----       | -------------- |
-| 31:0 | DEBUG      | SPI Debug Status  |
-
-
-##### Register Map: Global Register
-
-| Offset | Name        | Description   |
-| ------ | ---------   | ------------- |
-| 0x00   | SOFT_REG0   | [RW] Software Register0 |
-| 0x04   | RISC_FUSE   | [RW] Risc Fuse Value  |
-| 0x08   | SOFT_REG2   | [RW] Software Register2 |
-| 0x0c   | INTR_CTRL   | [RW] Interrupt Control |
-| 0x10   | SDRAM_CTRL1 | [RW] Indirect SPI Memory Access Control Register2 |
-| 0x14   | SDRAM_CTRL2 | [RW] Indirect SPI Memory Address  |
-| 0x18   | SOFT_REG6   | [RW] Software Register6 |
-| 0x1C   | SOFT_REG7   | [RW] Software Register7 |
-| 0x20   | SOFT_REG8   | [RW] Software Register8 |
-| 0x24   | SOFT_REG9   | [RW] Software Register9 |
-| 0x28   | SOFT_REG10  | [RW] Software Register10 |
-| 0x2C   | SOFT_REG11  | [RW] Software Register11 |
-| 0x30   | SOFT_REG12  | [RW] Software Register12 |
-| 0x34   | SOFT_REG13  | [RW] Software Register13 |
-| 0x38   | SOFT_REG14  | [RW] Software Register14 |
-| 0x3C   | SOFT_REG15  | [RW] Software Register15 |
-
-##### Register: RISC_FUSE
-
-| Bits  | Name        | Description    |
-| ----  | ----        | -------------- |
-| 31:0  | RISC_FUSE   | RISC Core Fuse Value |
-
-##### Register: INTR_CTRL
-
-| Bits  | Name        | Description    |
-| ----  | ----        | -------------- |
-| 31:20 | Reserved    | Unused         |
-| 19:17 | USER_IRQ    | User Interrupt generation toward riscv         |
-| 16    | SOFT_IRQ    | Software Interrupt generation toward riscv     |
-| 15:0  | EXT_IRQ     | External Interrupt generation toward riscv     |
-
 
 
 
@@ -621,25 +450,47 @@
 
 The simulation package includes the following tests:
 
-* **risc_boot**           - Complete caravel User Risc core boot 
-* **wb_port**             - Complete caravel User Wishbone validation
-* **uart_master**         - complete caravel user uart master test
-* **user_risc_boot**      - Standalone User Risc core boot
-* **user_sspi**           - Standalone SSPI test
-* **user_qspi**           - Standalone Quad SPI test
-* **user_spi**            - Standalone SPI test
-* **user_i2c**            - Standalone I2C test
-* **user_usb**            - Standalone USB Host test
-* **user_risc_boot**      - Standalone Risc Boot test
-* **user_uart**           - Standalone Risc with UART-0 Test
-* **user_uart1**          - Standalone Risc with UART-1 Test
-* **user_gpio**           - Standalone GPIO Test
-* **user_pwm**            - Standalone pwm Test
-* **user_timer**          - Standalone timer Test
-* **user_uart_master**    - Standalone uart master test
-* **riscv_regress**       - Standalone riscv compliance and regression test suite
+## Standalone Riscduino SOC Specific Test case 
+* **1.user_basic**          - Basic test case to validate strap and clocks
+* **2.user_uart**           - Standalone Risc with UART-0 Test
+* **3.user_uart1**          - Standalone Risc with UART-1 Test
+* **4.user_risc_boot**      - Standalone User Risc core boot
+* **4.risc_boot**           - Complete caravel User Risc core boot 
+* **5.user_qspi**           - Standalone Quad SPI test
+* **6.user_sspi**           - Standalone SSPI test
+* **7.user_i2c**            - Standalone I2C test
+* **8.user_usb**            - Standalone USB Host test
+* **9.user_gpio**           - Standalone GPIO Test
+* **10.user_aes**           - AES computation through Riscv core
+* **11.user_spi_isp**       - Device boot with SPI as ISP
+* **12.user_timer**         - Standalone timer Test
+* **13.user_uart_master**   - Standalone uart master test
+* **14.user_sram_exec**     - Riscv Boot with code running in SRAM
+* **15.user_cache_bypass**  - Riscv Boot without icache and dcache
+* **16.user_pwm**            -Standalone pwm Test
+* **17.user_sema**           -Standalone validation of hardware Semaphore function
+* **18.riscv_regress**       - Standalone riscv compliance and regression test suite
 
+## Caravel+RISCDUINO Integrated Specific Test case 
+* **1.wb_port**             - Complete caravel User Wishbone validation
+* **2.uart_master**         - complete caravel user uart master test
+* **3.risc_boot**           - Complete caravel User Risc core boot 
 
+## Arduino Based Test Case
+* **1.arduino_arrays**                - Validation of Array function
+* **2.arduino_digital_port_control**  - Validation for AD5206 digital potentiometer through SPI
+* **3.arduino_i2c_scaner**            - I2C port scanner        
+* **4.arduino_risc_boot**             - Riscv Basic Boot
+* **5.arduino_timer_intr**            - Timer Interrupt handling
+* **6.arduino_ascii_table**           - Ascii Table Display
+* **7.arduino_gpio_intr**             - GPIO Interrupt generation
+* **8.arduino_i2c_wr_rd**             - I2C Write and Read access
+* **9.arduino_string**                - Validation of String function
+* **10.arduino_ws281x**               - Validation of ws281x serial protocol 
+* **11.arduino_character_analysis**   - uart Input Character analysis
+* **12.arduino_hello_world**          - Basic hello world display
+* **13.arduino_multi_serial**         - Validation of Two Serail port
+* **14.arduino_switchCase2**          - Validation of switch case
 
 # Running Simulation