diff --git a/openlane/pinmux/config.tcl b/openlane/pinmux/config.tcl
index 7650732..19c5a63 100755
--- a/openlane/pinmux/config.tcl
+++ b/openlane/pinmux/config.tcl
@@ -72,7 +72,7 @@
 set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
 
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 550 450"
+set ::env(DIE_AREA) "0 0 500 400"
 
 
 # If you're going to use multiple power domains, then keep this disabled.
@@ -82,7 +82,7 @@
 
 
 set ::env(PL_TIME_DRIVEN) 1
-set ::env(PL_TARGET_DENSITY) "0.30"
+set ::env(PL_TARGET_DENSITY) "0.38"
 set ::env(CELL_PAD) "4"
 
 
diff --git a/signoff/pinmux/PDK_SOURCES b/signoff/pinmux/PDK_SOURCES
index b08beb4..16447f5 100644
--- a/signoff/pinmux/PDK_SOURCES
+++ b/signoff/pinmux/PDK_SOURCES
@@ -1 +1,3 @@
-open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6
+skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+open_pdks 7519dfb04400f224f140749cda44ee7de6f5e095
+magic 7d601628e4e05fd17fcb80c3552dacb64e9f6e7b
\ No newline at end of file
diff --git a/signoff/user_project_wrapper/PDK_SOURCES b/signoff/user_project_wrapper/PDK_SOURCES
index b08beb4..16447f5 100644
--- a/signoff/user_project_wrapper/PDK_SOURCES
+++ b/signoff/user_project_wrapper/PDK_SOURCES
@@ -1 +1,3 @@
-open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6
+skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+open_pdks 7519dfb04400f224f140749cda44ee7de6f5e095
+magic 7d601628e4e05fd17fcb80c3552dacb64e9f6e7b
\ No newline at end of file
diff --git a/verilog/dv/riscv_regress/Makefile b/verilog/dv/riscv_regress/Makefile
index 15194cc..fd2adcb 100644
--- a/verilog/dv/riscv_regress/Makefile
+++ b/verilog/dv/riscv_regress/Makefile
@@ -70,7 +70,7 @@
             VECT_IRQ  ?= 0
             IPIC      ?= 0
             TCM       ?= 0
-            SIM_CFG_DEF  = YCR_CFG_$(CFG)
+            SIM_CFG_DEF  = YCR1_CFG_$(CFG)
         endif
     endif
 endif