diff --git a/mpw_precheck/logs/gds.info b/mpw_precheck/logs/gds.info
new file mode 100644
index 0000000..86992e7
--- /dev/null
+++ b/mpw_precheck/logs/gds.info
@@ -0,0 +1 @@
+user_project_wrapper.gds: 11ce2a835a013823c4f4b9bf82aa5f1f991c0748
\ No newline at end of file
diff --git a/mpw_precheck/logs/git.info b/mpw_precheck/logs/git.info
new file mode 100644
index 0000000..d96e992
--- /dev/null
+++ b/mpw_precheck/logs/git.info
@@ -0,0 +1,3 @@
+Repository: https://github.com/dineshannayya/riscduino_qcore.git
+Branch: main
+Commit: 7de904f44beac532e0ad4f5a177d326beca3a6db
diff --git a/mpw_precheck/logs/klayout_beol_check.log b/mpw_precheck/logs/klayout_beol_check.log
new file mode 100644
index 0000000..ec3f747
--- /dev/null
+++ b/mpw_precheck/logs/klayout_beol_check.log
@@ -0,0 +1,1005 @@
+/opt/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::FEOL
+/opt/checks/tech-files/sky130A_mr.drc:40: warning: previous definition of FEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:54: warning: already initialized constant DRC::DRCEngine::BEOL
+/opt/checks/tech-files/sky130A_mr.drc:41: warning: previous definition of BEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/checks/tech-files/sky130A_mr.drc:42: warning: previous definition of OFFGRID was here
+/opt/checks/tech-files/sky130A_mr.drc:68: warning: already initialized constant DRC::DRCEngine::SEAL
+/opt/checks/tech-files/sky130A_mr.drc:43: warning: previous definition of SEAL was here
+/opt/checks/tech-files/sky130A_mr.drc:74: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/opt/checks/tech-files/sky130A_mr.drc:44: warning: previous definition of FLOATING_MET was here
+"input" in: sky130A_mr.drc:124
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+    Elapsed: 0.230s  Memory: 965.00M
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+DRC section
+BEOL section
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+END: 67/20 (li)
+START: 67/44 (mcon)
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+END: 76/20 (pad)
+Writing report database: /mnt/uffs/user/u5295_dinesha/design/riscduino-qcore_q3_/jobs/mpw_precheck/2313daf6-2262-4ba5-8fab-30bc2b344377/outputs/reports/klayout_beol_check.xml ..
+Total elapsed: 2197.180s  Memory: 6875.00M
+ 
+Cell exclusion list:
+   rule    | cell
+   nwell.6 | sky130_fd_io__gpiov2_amux, sky130_fd_io__simple_pad_and_busses, sram
+   nsd.1   | sram
+   nsd.2   | sram
+   psd.1   | sram
+   psd.2   | sram
+ 
+release 2022.6.30_01.07
diff --git a/mpw_precheck/logs/klayout_beol_check.total b/mpw_precheck/logs/klayout_beol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_beol_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_feol_check.log b/mpw_precheck/logs/klayout_feol_check.log
new file mode 100644
index 0000000..8658cf9
--- /dev/null
+++ b/mpw_precheck/logs/klayout_feol_check.log
@@ -0,0 +1,817 @@
+/opt/checks/tech-files/sky130A_mr.drc:48: warning: already initialized constant DRC::DRCEngine::FEOL
+/opt/checks/tech-files/sky130A_mr.drc:40: warning: previous definition of FEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::BEOL
+/opt/checks/tech-files/sky130A_mr.drc:41: warning: previous definition of BEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/checks/tech-files/sky130A_mr.drc:42: warning: previous definition of OFFGRID was here
+/opt/checks/tech-files/sky130A_mr.drc:68: warning: already initialized constant DRC::DRCEngine::SEAL
+/opt/checks/tech-files/sky130A_mr.drc:43: warning: previous definition of SEAL was here
+/opt/checks/tech-files/sky130A_mr.drc:74: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/opt/checks/tech-files/sky130A_mr.drc:44: warning: previous definition of FLOATING_MET was here
+"input" in: sky130A_mr.drc:124
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+"and" in: sky130A_mr.drc:371
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+"enclosing" in: sky130A_mr.drc:372
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+"output" in: sky130A_mr.drc:372
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+"enclosing" in: sky130A_mr.drc:373
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+"output" in: sky130A_mr.drc:373
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+"separation" in: sky130A_mr.drc:374
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+"not_interacting" in: sky130A_mr.drc:375
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+"separation" in: sky130A_mr.drc:375
+    Edge pairs: 0 (flat)  0 (hierarchical)
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+"output" in: sky130A_mr.drc:375
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1848.00M
+END: 89/44 (capm)
+START: 97/44 (cap2m)
+"width" in: sky130A_mr.drc:380
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+"output" in: sky130A_mr.drc:380
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+"output" in: sky130A_mr.drc:388
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1848.00M
+END: 97/44 (cap2m)
+FEOL section
+START: 75/20 (hvi)
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+"output" in: sky130A_mr.drc:690
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+    Elapsed: 0.000s  Memory: 1848.00M
+END: 75/20 (hvi)
+START: 125/20 (hvntm)
+"not" in: sky130A_mr.drc:695
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+"output" in: sky130A_mr.drc:696
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+"space" in: sky130A_mr.drc:697
+    Edge pairs: 0 (flat)  0 (hierarchical)
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+"output" in: sky130A_mr.drc:697
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1848.00M
+END: 125/20 (hvntm)
+Writing report database: /mnt/uffs/user/u5295_dinesha/design/riscduino-qcore_q3_/jobs/mpw_precheck/2313daf6-2262-4ba5-8fab-30bc2b344377/outputs/reports/klayout_feol_check.xml ..
+Total elapsed: 221.150s  Memory: 1816.00M
+ 
+Cell exclusion list:
+   rule    | cell
+   nwell.6 | sky130_fd_io__gpiov2_amux, sky130_fd_io__simple_pad_and_busses, sram
+   nsd.1   | sram
+   nsd.2   | sram
+   psd.1   | sram
+   psd.2   | sram
+ 
+release 2022.6.30_01.07
diff --git a/mpw_precheck/logs/klayout_feol_check.total b/mpw_precheck/logs/klayout_feol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_feol_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_met_min_ca_density_check.log b/mpw_precheck/logs/klayout_met_min_ca_density_check.log
new file mode 100644
index 0000000..5f5b422
--- /dev/null
+++ b/mpw_precheck/logs/klayout_met_min_ca_density_check.log
@@ -0,0 +1,79 @@
+"polygons" in: met_min_ca_density.lydrc:35
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+    Elapsed: 0.440s  Memory: 971.00M
+"polygons" in: met_min_ca_density.lydrc:36
+    Polygons (raw): 10029059 (flat)  363932 (hierarchical)
+    Elapsed: 0.330s  Memory: 980.00M
+"polygons" in: met_min_ca_density.lydrc:38
+    Polygons (raw): 8405258 (flat)  2028219 (hierarchical)
+    Elapsed: 1.350s  Memory: 1036.00M
+"polygons" in: met_min_ca_density.lydrc:39
+    Polygons (raw): 1734175 (flat)  728275 (hierarchical)
+    Elapsed: 0.580s  Memory: 1044.00M
+"polygons" in: met_min_ca_density.lydrc:41
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+    Elapsed: 0.770s  Memory: 1071.00M
+"polygons" in: met_min_ca_density.lydrc:42
+    Polygons (raw): 396414 (flat)  256629 (hierarchical)
+    Elapsed: 0.320s  Memory: 1073.00M
+"polygons" in: met_min_ca_density.lydrc:44
+    Polygons (raw): 476951 (flat)  250572 (hierarchical)
+    Elapsed: 0.320s  Memory: 1078.00M
+"polygons" in: met_min_ca_density.lydrc:45
+    Polygons (raw): 333085 (flat)  222990 (hierarchical)
+    Elapsed: 0.290s  Memory: 1083.00M
+"polygons" in: met_min_ca_density.lydrc:47
+    Polygons (raw): 78448 (flat)  36267 (hierarchical)
+    Elapsed: 0.190s  Memory: 1084.00M
+"polygons" in: met_min_ca_density.lydrc:48
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+    Elapsed: 0.000s  Memory: 1084.00M
+"polygons" in: met_min_ca_density.lydrc:49
+    Polygons (raw): 39566 (flat)  39566 (hierarchical)
+    Elapsed: 0.030s  Memory: 1086.00M
+"polygons" in: met_min_ca_density.lydrc:51
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+    Elapsed: 0.010s  Memory: 1086.00M
+"input" in: met_min_ca_density.lydrc:53
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+    Elapsed: 0.170s  Memory: 1086.00M
+"area" in: met_min_ca_density.lydrc:55
+    Elapsed: 3.670s  Memory: 1103.00M
+"polygons" in: met_min_ca_density.lydrc:59
+    Polygons (raw): 8093585 (flat)  369670 (hierarchical)
+    Elapsed: 0.370s  Memory: 1105.00M
+"area" in: met_min_ca_density.lydrc:59
+    Elapsed: 35.650s  Memory: 1622.00M
+li1_ca_density is 0.7098827172590092
+"polygons" in: met_min_ca_density.lydrc:69
+    Polygons (raw): 8405258 (flat)  2028219 (hierarchical)
+    Elapsed: 1.360s  Memory: 1622.00M
+"area" in: met_min_ca_density.lydrc:69
+    Elapsed: 38.060s  Memory: 1679.00M
+m1_ca_density is 0.8234382260298295
+"polygons" in: met_min_ca_density.lydrc:79
+    Polygons (raw): 3129651 (flat)  979282 (hierarchical)
+    Elapsed: 0.790s  Memory: 1679.00M
+"area" in: met_min_ca_density.lydrc:79
+    Elapsed: 7.510s  Memory: 1680.00M
+m2_ca_density is 0.8953573365358422
+"polygons" in: met_min_ca_density.lydrc:89
+    Polygons (raw): 476951 (flat)  250572 (hierarchical)
+    Elapsed: 0.330s  Memory: 1680.00M
+"area" in: met_min_ca_density.lydrc:89
+    Elapsed: 2.170s  Memory: 1680.00M
+m3_ca_density is 0.9514959358411815
+"polygons" in: met_min_ca_density.lydrc:99
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+    Elapsed: 0.200s  Memory: 1680.00M
+"area" in: met_min_ca_density.lydrc:99
+    Elapsed: 0.590s  Memory: 1680.00M
+m4_ca_density is 0.7431872040930495
+"polygons" in: met_min_ca_density.lydrc:109
+    Polygons (raw): 191 (flat)  191 (hierarchical)
+    Elapsed: 0.010s  Memory: 1680.00M
+"area" in: met_min_ca_density.lydrc:109
+    Elapsed: 0.260s  Memory: 1680.00M
+m5_ca_density is 0.668242188667497
+Writing report database: /mnt/uffs/user/u5295_dinesha/design/riscduino-qcore_q3_/jobs/mpw_precheck/2313daf6-2262-4ba5-8fab-30bc2b344377/outputs/reports/klayout_met_min_ca_density_check.xml ..
+Total elapsed: 101.970s  Memory: 1648.00M
diff --git a/mpw_precheck/logs/klayout_met_min_ca_density_check.total b/mpw_precheck/logs/klayout_met_min_ca_density_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_met_min_ca_density_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_offgrid_check.log b/mpw_precheck/logs/klayout_offgrid_check.log
new file mode 100644
index 0000000..9f7f63d
--- /dev/null
+++ b/mpw_precheck/logs/klayout_offgrid_check.log
@@ -0,0 +1,765 @@
+/opt/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::FEOL
+/opt/checks/tech-files/sky130A_mr.drc:40: warning: previous definition of FEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::BEOL
+/opt/checks/tech-files/sky130A_mr.drc:41: warning: previous definition of BEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:60: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/checks/tech-files/sky130A_mr.drc:42: warning: previous definition of OFFGRID was here
+/opt/checks/tech-files/sky130A_mr.drc:68: warning: already initialized constant DRC::DRCEngine::SEAL
+/opt/checks/tech-files/sky130A_mr.drc:43: warning: previous definition of SEAL was here
+/opt/checks/tech-files/sky130A_mr.drc:74: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/opt/checks/tech-files/sky130A_mr.drc:44: warning: previous definition of FLOATING_MET was here
+"input" in: sky130A_mr.drc:124
+    Polygons (raw): 1639243 (flat)  965 (hierarchical)
+    Elapsed: 0.240s  Memory: 965.00M
+"polygons" in: sky130A_mr.drc:125
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+    Elapsed: 0.170s  Memory: 965.00M
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+    Elapsed: 0.150s  Memory: 965.00M
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+    Elapsed: 0.010s  Memory: 965.00M
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+"polygons" in: sky130A_mr.drc:137
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+    Elapsed: 0.140s  Memory: 965.00M
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+    Elapsed: 0.360s  Memory: 976.00M
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+    Elapsed: 0.350s  Memory: 984.00M
+"polygons" in: sky130A_mr.drc:149
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+    Elapsed: 1.340s  Memory: 1040.00M
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+    Elapsed: 0.570s  Memory: 1048.00M
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+"polygons" in: sky130A_mr.drc:161
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+"output" in: sky130A_mr.drc:751
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"ongrid" in: sky130A_mr.drc:752
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 8.110s  Memory: 2892.00M
+"output" in: sky130A_mr.drc:752
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"with_angle" in: sky130A_mr.drc:753
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.350s  Memory: 2892.00M
+"output" in: sky130A_mr.drc:753
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"ongrid" in: sky130A_mr.drc:754
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 2.570s  Memory: 2892.00M
+"output" in: sky130A_mr.drc:754
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"with_angle" in: sky130A_mr.drc:755
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.230s  Memory: 2892.00M
+"output" in: sky130A_mr.drc:755
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"ongrid" in: sky130A_mr.drc:756
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 2.390s  Memory: 2892.00M
+"output" in: sky130A_mr.drc:756
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"with_angle" in: sky130A_mr.drc:757
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.070s  Memory: 2892.00M
+"output" in: sky130A_mr.drc:757
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"ongrid" in: sky130A_mr.drc:758
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 2.210s  Memory: 2892.00M
+"output" in: sky130A_mr.drc:758
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 2892.00M
+"with_angle" in: sky130A_mr.drc:759
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.210s  Memory: 2892.00M
+"output" in: sky130A_mr.drc:759
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 2892.00M
+"ongrid" in: sky130A_mr.drc:760
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.340s  Memory: 2892.00M
+"output" in: sky130A_mr.drc:760
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"with_angle" in: sky130A_mr.drc:761
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"output" in: sky130A_mr.drc:761
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"ongrid" in: sky130A_mr.drc:762
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.730s  Memory: 2892.00M
+"output" in: sky130A_mr.drc:762
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"with_angle" in: sky130A_mr.drc:763
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.020s  Memory: 2892.00M
+"output" in: sky130A_mr.drc:763
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"ongrid" in: sky130A_mr.drc:764
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.710s  Memory: 2892.00M
+"output" in: sky130A_mr.drc:764
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"with_angle" in: sky130A_mr.drc:765
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.050s  Memory: 2892.00M
+"output" in: sky130A_mr.drc:765
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"ongrid" in: sky130A_mr.drc:766
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.360s  Memory: 2892.00M
+"output" in: sky130A_mr.drc:766
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"with_angle" in: sky130A_mr.drc:767
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"output" in: sky130A_mr.drc:767
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"ongrid" in: sky130A_mr.drc:768
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.350s  Memory: 2892.00M
+"output" in: sky130A_mr.drc:768
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"with_angle" in: sky130A_mr.drc:769
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"output" in: sky130A_mr.drc:769
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"ongrid" in: sky130A_mr.drc:770
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.360s  Memory: 2892.00M
+"output" in: sky130A_mr.drc:770
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 2892.00M
+"with_angle" in: sky130A_mr.drc:771
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"output" in: sky130A_mr.drc:771
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"ongrid" in: sky130A_mr.drc:772
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.350s  Memory: 2892.00M
+"output" in: sky130A_mr.drc:772
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"with_angle" in: sky130A_mr.drc:773
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"output" in: sky130A_mr.drc:773
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"ongrid" in: sky130A_mr.drc:774
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.350s  Memory: 2892.00M
+"output" in: sky130A_mr.drc:774
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"with_angle" in: sky130A_mr.drc:775
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"output" in: sky130A_mr.drc:775
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"ongrid" in: sky130A_mr.drc:776
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.350s  Memory: 2892.00M
+"output" in: sky130A_mr.drc:776
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"with_angle" in: sky130A_mr.drc:777
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"output" in: sky130A_mr.drc:777
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"ongrid" in: sky130A_mr.drc:778
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.350s  Memory: 2892.00M
+"output" in: sky130A_mr.drc:778
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"with_angle" in: sky130A_mr.drc:779
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"output" in: sky130A_mr.drc:779
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"ongrid" in: sky130A_mr.drc:780
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.350s  Memory: 2892.00M
+"output" in: sky130A_mr.drc:780
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 2892.00M
+"with_angle" in: sky130A_mr.drc:781
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"output" in: sky130A_mr.drc:781
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+"ongrid" in: sky130A_mr.drc:782
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.360s  Memory: 2892.00M
+"output" in: sky130A_mr.drc:782
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2892.00M
+Writing report database: /mnt/uffs/user/u5295_dinesha/design/riscduino-qcore_q3_/jobs/mpw_precheck/2313daf6-2262-4ba5-8fab-30bc2b344377/outputs/reports/klayout_offgrid_check.xml ..
+Total elapsed: 254.610s  Memory: 2770.00M
+ 
+Cell exclusion list:
+   rule    | cell
+   nwell.6 | sky130_fd_io__gpiov2_amux, sky130_fd_io__simple_pad_and_busses, sram
+   nsd.1   | sram
+   nsd.2   | sram
+   psd.1   | sram
+   psd.2   | sram
+ 
+release 2022.6.30_01.07
diff --git a/mpw_precheck/logs/klayout_offgrid_check.total b/mpw_precheck/logs/klayout_offgrid_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_offgrid_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.log b/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
new file mode 100644
index 0000000..c7ce8c5
--- /dev/null
+++ b/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
@@ -0,0 +1,29 @@
+Running pin_label_purposes_overlapping_drawing.rb.drc on file=/root/riscduino-qcore_q3_/gds/user_project_wrapper.gds, topcell=user_project_wrapper, output to /mnt/uffs/user/u5295_dinesha/design/riscduino-qcore_q3_/jobs/mpw_precheck/2313daf6-2262-4ba5-8fab-30bc2b344377/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
+  deep:true tiled:false threads:8
+--- #err|description, table for cell: user_project_wrapper
+NO-Check ----        pwell:64/44/EMP   122/16/dat    64/59/EMP    44/16/EMP     44/5/EMP
+         ----        nwell:64/20/dat    64/16/dat     64/5/EMP
+         ----         diff:65/20/dat    65/16/EMP     65/6/EMP
+         ----          tap:65/44/dat    65/48/EMP     65/5/EMP
+         ----         poly:66/20/dat    66/16/EMP     66/5/EMP
+         ----       licon1:66/44/dat    66/58/EMP
+         ----          li1:67/20/dat    67/16/dat     67/5/dat
+         ----         mcon:67/44/dat    67/48/EMP
+         ----         met1:68/20/dat    68/16/dat     68/5/dat
+         ----          via:68/44/dat    68/58/EMP
+         ----         met2:69/20/dat    69/16/dat     69/5/dat
+         ----         via2:69/44/dat    69/58/EMP
+         ----         met3:70/20/dat    70/16/dat     70/5/dat
+         ----         via3:70/44/dat    70/48/EMP
+         ----         met4:71/20/dat    71/16/dat     71/5/dat
+         ----         via4:71/44/dat    71/48/EMP
+         ----         met5:72/20/dat    72/16/EMP     72/5/dat
+         ----          pad:76/20/EMP     76/5/EMP    76/16/EMP
+         ----          pnp:82/44/EMP    82/59/EMP
+         ----          npn:82/20/EMP     82/5/EMP
+         ----          rdl:74/20/EMP    74/16/EMP     74/5/EMP
+         ----     inductor:82/24/EMP    82/25/EMP
+       0 total error(s) among 0 error type(s), 33 checks, cell: user_project_wrapper
+Writing report...
+VmPeak:	 2669160 kB
+VmHWM:	 1359144 kB
diff --git a/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.total b/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_zeroarea_check.log b/mpw_precheck/logs/klayout_zeroarea_check.log
new file mode 100644
index 0000000..9414539
--- /dev/null
+++ b/mpw_precheck/logs/klayout_zeroarea_check.log
@@ -0,0 +1,6 @@
+writing to /mnt/uffs/user/u5295_dinesha/design/riscduino-qcore_q3_/jobs/mpw_precheck/2313daf6-2262-4ba5-8fab-30bc2b344377/outputs/user_project_wrapper_no_zero_areas.gds
+0 zero-area shapes
+0 zero-length paths,  0 zero-length paths deleted.
+0 total zero-area objects,  0 total objects deleted.
+VmPeak:	 1868312 kB
+VmHWM:	 1477076 kB
diff --git a/mpw_precheck/logs/klayout_zeroarea_check.total b/mpw_precheck/logs/klayout_zeroarea_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_zeroarea_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/magic_drc_check.log b/mpw_precheck/logs/magic_drc_check.log
new file mode 100644
index 0000000..228a799
--- /dev/null
+++ b/mpw_precheck/logs/magic_drc_check.log
@@ -0,0 +1,600 @@
+
+Magic 8.3 revision 340 - Compiled on Thu Nov 17 13:45:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Error parsing "/opt/checks/tech-files/sky130A.magicrc": can't read "::env(PDK_PATH)": no such variable
+Bad local startup file "/opt/checks/tech-files/sky130A.magicrc", continuing without.
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/opt/checks/drc_checks/magic/magic_drc_check.tcl" from command line.
+Detected an SRAM module
+Pre-loading a maglef of the SRAM block: sky130_sram_2kbyte_1rw1r_32x512_8
+Cell sky130_sram_2kbyte_1rw1r_32x512_8 has technology "sky130A", but current technology is "minimum"
+Loading technology sky130A
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Cell path is now "$CAD_ROOT/magic/sys/current $CAD_ROOT/magic/tutorial /opt/pdks/volare/sky130/versions/0059588eebfc704681dc2368bd1d33d96281d10f/sky130A/libs.ref/sky130_fd_io/mag /opt/pdks/volare/sky130/versions/0059588eebfc704681dc2368bd1d33d96281d10f/sky130A/libs.ref/sky130_fd_io/maglef /opt/pdks/volare/sky130/versions/0059588eebfc704681dc2368bd1d33d96281d10f/sky130A/libs.ref/sky130_fd_pr/mag /opt/pdks/volare/sky130/versions/0059588eebfc704681dc2368bd1d33d96281d10f/sky130A/libs.ref/sky130_fd_pr/maglef /opt/pdks/volare/sky130/versions/0059588eebfc704681dc2368bd1d33d96281d10f/sky130A/libs.ref/sky130_fd_sc_hd/mag /opt/pdks/volare/sky130/versions/0059588eebfc704681dc2368bd1d33d96281d10f/sky130A/libs.ref/sky130_fd_sc_hd/maglef /opt/pdks/volare/sky130/versions/0059588eebfc704681dc2368bd1d33d96281d10f/sky130A/libs.ref/sky130_fd_sc_hvl/mag /opt/pdks/volare/sky130/versions/0059588eebfc704681dc2368bd1d33d96281d10f/sky130A/libs.ref/sky130_fd_sc_hvl/maglef /opt/pdks/volare/sky130/versions/0059588eebfc704681dc2368bd1d33d96281d10f/sky130A/libs.ref/sky130_ml_xx_hd/mag /opt/pdks/volare/sky130/versions/0059588eebfc704681dc2368bd1d33d96281d10f/sky130A/libs.ref/sky130_sram_macros/mag /opt/pdks/volare/sky130/versions/0059588eebfc704681dc2368bd1d33d96281d10f/sky130A/libs.ref/sky130_sram_macros/maglef"
+Scaled magic input cell sky130_sram_2kbyte_1rw1r_32x512_8 geometry by factor of 2
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_project_wrapper
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_39".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_38".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_33".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_32".
+Reading "sky130_fd_bd_sram__openram_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wmask_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_data_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_29".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_28".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_360_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sli_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w0_740_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m7_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m7_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_delay_chain".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_10".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_rw".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_18".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_6".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_r".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec_0".
+CIF file read warning: CIF style sky130(vendor): units rescaled by factor of 5 / 1
+Reading "sky130_fd_bd_sram__openram_dp_nand2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec".
+Reading "sky130_fd_bd_sram__openram_dp_nand3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode3x8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_decoder".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_27".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_26".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_25".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_24".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w2_880_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array_0".
+Reading "sky130_fd_bd_sram__openram_sense_amp".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_sense_amp_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_23".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_21".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_22".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w0_550_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_mask_and_array".
+Reading "sky130_fd_bd_sram__openram_write_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_8".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_row".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 2620068): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 2620772): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 2621732): Unknown layer/datatype in boundary, layer=22 type=21
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_col".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array_0".
+Reading "sky130_fd_bd_sram__openram_dp_cell_dummy".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3113978): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3117754): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3121946): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3126746): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3128794): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dummy_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_replica".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3308236): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3312012): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3316204): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3322668): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3324844): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column".
+Reading "sky130_fd_bd_sram__openram_dp_cell".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3565294): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3569070): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3573262): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3579726): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3581902): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bitcell_array".
+    5000 uses
+    10000 uses
+    15000 uses
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_bitcell_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bank".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8".
+Warning:  cell sky130_sram_2kbyte_1rw1r_32x512_8 already existed before reading GDS!
+Using pre-existing cell definition
+Reading "sky130_fd_sc_hd__o32a_2".
+Reading "sky130_fd_sc_hd__o21ai_2".
+Reading "sky130_ef_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__o2bb2a_2".
+Reading "sky130_fd_sc_hd__a221o_2".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__and4b_2".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__a31oi_2".
+Reading "sky130_fd_sc_hd__or4_2".
+Reading "sky130_fd_sc_hd__or3b_2".
+Reading "sky130_fd_sc_hd__or3_2".
+Reading "sky130_fd_sc_hd__and2b_2".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__xor2_2".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__a22o_2".
+Reading "sky130_fd_sc_hd__o21a_2".
+Reading "sky130_fd_sc_hd__a21oi_2".
+Reading "sky130_fd_sc_hd__nand2b_2".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__a21o_2".
+Reading "sky130_fd_sc_hd__o22a_2".
+Reading "sky130_fd_sc_hd__nand3b_2".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__a311o_2".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__a211o_2".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__clkinv_2".
+Reading "sky130_fd_sc_hd__and3_2".
+Reading "sky130_fd_sc_hd__a32o_2".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__xnor2_2".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__dfrtp_2".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__a2bb2o_2".
+Reading "sky130_fd_sc_hd__a22oi_1".
+Reading "sky130_fd_sc_hd__and4bb_4".
+Reading "sky130_fd_sc_hd__o211ai_4".
+Reading "sky130_fd_sc_hd__nand4_1".
+Reading "sky130_fd_sc_hd__a21bo_2".
+Reading "sky130_fd_sc_hd__nor4b_4".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__o41a_1".
+Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__o22ai_1".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "sky130_fd_sc_hd__a41o_1".
+Reading "sky130_fd_sc_hd__o32a_4".
+Reading "sky130_fd_sc_hd__a22oi_2".
+Reading "sky130_fd_sc_hd__nor4_1".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__a311o_1".
+Reading "sky130_fd_sc_hd__o211ai_2".
+Reading "sky130_fd_sc_hd__o31ai_4".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__a31o_4".
+Reading "sky130_fd_sc_hd__xor2_1".
+Reading "sky130_fd_sc_hd__a21boi_1".
+Reading "sky130_fd_sc_hd__dfstp_2".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__o22ai_4".
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__o2111ai_4".
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "sky130_fd_sc_hd__a21bo_1".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__o211a_1".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__o22ai_2".
+Reading "sky130_fd_sc_hd__a2111o_1".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__o21ba_1".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__o221a_1".
+Reading "sky130_fd_sc_hd__o31a_2".
+Reading "sky130_fd_sc_hd__a22oi_4".
+Reading "sky130_fd_sc_hd__dfxtp_4".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__mux4_2".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__or3b_1".
+Reading "sky130_fd_sc_hd__a22o_4".
+Reading "sky130_fd_sc_hd__a211oi_4".
+Reading "sky130_fd_sc_hd__a221oi_1".
+Reading "sky130_fd_sc_hd__a221oi_4".
+Reading "sky130_fd_sc_hd__o311a_2".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__a31o_1".
+Reading "sky130_fd_sc_hd__dfxtp_2".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__o2bb2a_1".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__a211oi_1".
+Reading "sky130_fd_sc_hd__mux4_1".
+Reading "sky130_fd_sc_hd__and4bb_1".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__or4_4".
+Reading "sky130_fd_sc_hd__or3_1".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__or4b_4".
+Reading "sky130_fd_sc_hd__or3_4".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__or4b_1".
+Reading "sky130_fd_sc_hd__nor4_4".
+Reading "sky130_fd_sc_hd__nand3_1".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__a2bb2o_1".
+Reading "sky130_fd_sc_hd__dfstp_1".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__or4_1".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_fd_sc_hd__dfrtp_1".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__o31ai_1".
+Reading "sky130_fd_sc_hd__nand2b_1".
+Reading "sky130_fd_sc_hd__a311oi_1".
+Reading "sky130_fd_sc_hd__nand2b_4".
+Reading "sky130_fd_sc_hd__or4bb_1".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__nor3_2".
+Reading "sky130_fd_sc_hd__nand4b_1".
+Reading "sky130_fd_sc_hd__xor2_4".
+Reading "sky130_fd_sc_hd__o21ba_2".
+Reading "sky130_fd_sc_hd__a2111o_2".
+Reading "sky130_fd_sc_hd__or3b_4".
+Reading "sky130_fd_sc_hd__a31oi_4".
+Reading "sky130_fd_sc_hd__nand3b_1".
+Reading "sky130_fd_sc_hd__nor4b_2".
+Reading "sky130_fd_sc_hd__a41o_2".
+Reading "sky130_fd_sc_hd__nor3b_4".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__a2111oi_4".
+Reading "sky130_fd_sc_hd__o32ai_1".
+Reading "sky130_fd_sc_hd__and4bb_2".
+Reading "sky130_fd_sc_hd__or4b_2".
+Reading "sky130_fd_sc_hd__nor3b_1".
+Reading "sky130_fd_sc_hd__nor4_2".
+Reading "sky130_fd_sc_hd__a311oi_4".
+Reading "sky130_fd_sc_hd__o21bai_2".
+Reading "sky130_fd_sc_hd__nor3b_2".
+Reading "sky130_fd_sc_hd__a311oi_2".
+Reading "sky130_fd_sc_hd__and3b_4".
+Reading "sky130_fd_sc_hd__a2bb2o_4".
+Reading "sky130_fd_sc_hd__a21bo_4".
+Reading "sky130_fd_sc_hd__xnor2_4".
+Reading "sky130_fd_sc_hd__o311ai_4".
+Reading "sky130_fd_sc_hd__o2bb2a_4".
+Reading "sky130_fd_sc_hd__o211a_4".
+Reading "sky130_fd_sc_hd__and2b_4".
+Reading "sky130_fd_sc_hd__o21bai_4".
+Reading "sky130_fd_sc_hd__nand3b_4".
+Reading "sky130_fd_sc_hd__o2111ai_1".
+Reading "sky130_fd_sc_hd__nand4_4".
+Reading "sky130_fd_sc_hd__o221ai_2".
+Reading "sky130_fd_sc_hd__o211ai_1".
+Reading "sky130_fd_sc_hd__o2bb2ai_4".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__nor4b_1".
+Reading "sky130_fd_sc_hd__o2111a_2".
+Reading "ycr_core_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+Reading "sky130_fd_sc_hd__and3b_2".
+Reading "sky130_fd_sc_hd__nand4_2".
+Reading "sky130_fd_sc_hd__o31ai_2".
+Reading "sky130_fd_sc_hd__nand3_2".
+Reading "sky130_fd_sc_hd__or2b_1".
+Reading "sky130_fd_sc_hd__o2bb2ai_2".
+Reading "sky130_fd_sc_hd__or2b_2".
+Reading "sky130_fd_sc_hd__and4_4".
+Reading "sky130_fd_sc_hd__a221o_4".
+Reading "sky130_fd_sc_hd__or4bb_4".
+Reading "sky130_fd_sc_hd__or2b_4".
+Reading "sky130_fd_sc_hd__o41ai_4".
+Reading "sky130_fd_sc_hd__a21boi_4".
+Reading "sky130_fd_sc_hd__o221ai_1".
+Reading "sky130_fd_sc_hd__o31a_4".
+Reading "sky130_fd_sc_hd__buf_1".
+Reading "sky130_fd_sc_hd__dlygate4sd1_1".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "ycr4_iconnect".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+    75000 uses
+    80000 uses
+    85000 uses
+    90000 uses
+    95000 uses
+    100000 uses
+Reading "sky130_fd_sc_hd__a2111oi_2".
+Reading "sky130_fd_sc_hd__a2111oi_1".
+CIF file read warning: Input off lambda grid by 2/5; snapped to grid.
+Reading "sky130_fd_sc_hd__o2bb2ai_1".
+Reading "sky130_fd_sc_hd__o41a_4".
+Reading "sky130_fd_sc_hd__nand4b_4".
+Reading "sky130_fd_sc_hd__a32o_4".
+Reading "sky130_fd_sc_hd__or4bb_2".
+Reading "ycr_intf".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+Reading "switchn".
+Reading "resistor".
+Reading "resistor_3xh".
+Reading "switch2".
+Reading "switch2n".
+Reading "2bit_DAC".
+Reading "resistor_h".
+Reading "3bit_DAC".
+Reading "4bit_DAC".
+Reading "5bit_DAC".
+Reading "6bit_DAC".
+Reading "7bit_DAC".
+Reading "8bit_DAC".
+Reading "2x8bit_DAC".
+Reading "4x8bit_DAC".
+Reading "dac_top".
+Reading "sky130_fd_sc_hd__einvn_8".
+Reading "sky130_fd_sc_hd__clkinv_1".
+Reading "sky130_fd_sc_hd__einvp_2".
+Reading "sky130_fd_sc_hd__einvn_2".
+Reading "sky130_fd_sc_hd__a21boi_2".
+Reading "sky130_fd_sc_hd__clkinv_8".
+Reading "sky130_fd_sc_hd__einvp_1".
+Reading "dg_pll".
+Reading "sky130_fd_sc_hd__a41oi_4".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__o311a_4".
+Reading "sky130_fd_sc_hd__o221a_4".
+Reading "sky130_fd_sc_hd__a41o_4".
+Reading "wb_interconnect".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "sky130_fd_sc_hd__o41a_2".
+Reading "sky130_fd_sc_hd__a211oi_2".
+Reading "sky130_fd_sc_hd__clkdlybuf4s50_1".
+Reading "qspim_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+Reading "sky130_fd_sc_hd__dlclkp_1".
+Reading "sky130_fd_sc_hd__dlclkp_4".
+Reading "sky130_fd_sc_hd__a32oi_4".
+Reading "sky130_fd_sc_hd__o311ai_2".
+Reading "sky130_fd_sc_hd__o2111ai_2".
+Reading "wb_host".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+Reading "sky130_fd_sc_hd__and4b_4".
+Reading "sky130_fd_sc_hd__nor2b_2".
+Reading "sky130_fd_sc_hd__nor2b_1".
+Reading "uart_i2c_usb_spi_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+Reading "sky130_fd_sc_hd__dlxtn_1".
+Reading "sky130_fd_sc_hd__dlxtn_2".
+Reading "sky130_fd_sc_hd__nand4b_2".
+Reading "sky130_fd_sc_hd__a32oi_1".
+Reading "pinmux_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+Reading "user_project_wrapper".
+[INFO]: Loading user_project_wrapper
+
+DRC style is now "drc(full)"
+Loading DRC CIF style.
+No errors found.
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+[INFO]: DRC Checking DONE (/mnt/uffs/user/u5295_dinesha/design/riscduino-qcore_q3_/jobs/mpw_precheck/2313daf6-2262-4ba5-8fab-30bc2b344377/outputs/reports/magic_drc_check.drc.report)
+[INFO]: Saving mag view with DRC errors(/mnt/uffs/user/u5295_dinesha/design/riscduino-qcore_q3_/jobs/mpw_precheck/2313daf6-2262-4ba5-8fab-30bc2b344377/outputs/user_project_wrapper.magic.drc.mag)
+[INFO]: Saved
diff --git a/mpw_precheck/logs/magic_drc_check.total b/mpw_precheck/logs/magic_drc_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/magic_drc_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/pdks.info b/mpw_precheck/logs/pdks.info
new file mode 100644
index 0000000..f65aecb
--- /dev/null
+++ b/mpw_precheck/logs/pdks.info
@@ -0,0 +1,2 @@
+Open PDKs 0059588eebfc704681dc2368bd1d33d96281d10f
+SKY130A PDK f70d8ca46961ff92719d8870a18a076370b85f6c
\ No newline at end of file
diff --git a/mpw_precheck/logs/precheck.log b/mpw_precheck/logs/precheck.log
new file mode 100644
index 0000000..9aa6888
--- /dev/null
+++ b/mpw_precheck/logs/precheck.log
@@ -0,0 +1,80 @@
+2022-12-04 03:01:37 - [INFO] - {{Project Git Info}} Repository: https://github.com/dineshannayya/riscduino_qcore.git | Branch: main | Commit: 7de904f44beac532e0ad4f5a177d326beca3a6db
+2022-12-04 03:01:37 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: riscduino-qcore_q3_
+2022-12-04 03:01:39 - [INFO] - {{Project Type Info}} digital
+2022-12-04 03:01:40 - [INFO] - {{Project GDS Info}} user_project_wrapper: 11ce2a835a013823c4f4b9bf82aa5f1f991c0748
+2022-12-04 03:01:40 - [INFO] - {{Tools Info}} KLayout: v0.27.12 | Magic: v8.3.340
+2022-12-04 03:01:40 - [INFO] - {{PDKs Info}} SKY130A: f70d8ca46961ff92719d8870a18a076370b85f6c | Open PDKs: 0059588eebfc704681dc2368bd1d33d96281d10f
+2022-12-04 03:01:40 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'riscduino-qcore_q3_/jobs/mpw_precheck/2313daf6-2262-4ba5-8fab-30bc2b344377/logs'
+2022-12-04 03:01:40 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, GPIO-Defines, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
+2022-12-04 03:01:40 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 14: License
+2022-12-04 03:01:41 - [INFO] - An approved LICENSE (Apache-2.0) was found in riscduino-qcore_q3_.
+2022-12-04 03:01:41 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
+2022-12-04 03:01:42 - [INFO] - An approved LICENSE (Apache-2.0) was found in riscduino-qcore_q3_.
+2022-12-04 03:01:42 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
+2022-12-04 03:01:42 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino-qcore_q3_/verilog/dv/common/bfm/usb_device/core/usb1d_ctrl.v): 'utf-8' codec can't decode byte 0x96 in position 5130: invalid start byte
+2022-12-04 03:01:42 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino-qcore_q3_/verilog/dv/common/model/mt48lc8m8a2.v): 'utf-8' codec can't decode byte 0xa9 in position 1830: invalid start byte
+2022-12-04 03:01:42 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino-qcore_q3_/verilog/dv/user_gpio/.user_timer_tb.v.swp): 'utf-8' codec can't decode byte 0xc1 in position 16: invalid start byte
+2022-12-04 03:01:42 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino-qcore_q3_/verilog/dv/user_uart/.user_uart.c.un~): 'utf-8' codec can't decode byte 0x9f in position 3: invalid start byte
+2022-12-04 03:01:42 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 385 non-compliant file(s) with the SPDX Standard.
+2022-12-04 03:01:42 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['riscduino-qcore_q3_/run_regress', 'riscduino-qcore_q3_/hacks/patch/pdngen.patch', 'riscduino-qcore_q3_/hacks/patch/resizer.patch', 'riscduino-qcore_q3_/hacks/src/OpenROAD/PdnGen.tcl', 'riscduino-qcore_q3_/hacks/src/OpenROAD/Resizer.cc', 'riscduino-qcore_q3_/hacks/src/OpenSTA/network/ConcreteNetwork.cc', 'riscduino-qcore_q3_/hacks/src/OpenSTA/tcl/NetworkEdit.tcl', 'riscduino-qcore_q3_/hacks/src/OpenSTA/tcl/Sta.tcl', 'riscduino-qcore_q3_/hacks/src/openlane/io_place.py', 'riscduino-qcore_q3_/hacks/src/openlane/synth.tcl', 'riscduino-qcore_q3_/hacks/src/openlane/synth_top.tcl', 'riscduino-qcore_q3_/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib', 'riscduino-qcore_q3_/openlane/Read.me', 'riscduino-qcore_q3_/openlane/pinmux_top/base.sdc', 'riscduino-qcore_q3_/openlane/qspim_top/base.sdc']
+2022-12-04 03:01:42 - [INFO] - For the full SPDX compliance report check: riscduino-qcore_q3_/jobs/mpw_precheck/2313daf6-2262-4ba5-8fab-30bc2b344377/logs/spdx_compliance_report.log
+2022-12-04 03:01:42 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 14: Makefile
+2022-12-04 03:01:42 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
+2022-12-04 03:01:42 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 14: Default
+2022-12-04 03:01:42 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
+2022-12-04 03:01:44 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
+2022-12-04 03:01:44 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 14: Documentation
+2022-12-04 03:01:44 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
+2022-12-04 03:01:44 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 14: Consistency
+2022-12-04 03:01:52 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in caravel are connected to power
+2022-12-04 03:01:52 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravel netlist passed all consistency checks.
+2022-12-04 03:01:52 - [INFO] - PORTS CHECK PASSED: Netlist user_project_wrapper ports match the golden wrapper ports
+2022-12-04 03:01:52 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_project_wrapper contains at least 1 instances (16 instances). 
+2022-12-04 03:01:52 - [INFO] - MODELING CHECK PASSED: Netlist user_project_wrapper is structural.
+2022-12-04 03:01:52 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_project_wrapper matches the provided structural netlist.
+2022-12-04 03:01:52 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in user_project_wrapper are connected to power
+2022-12-04 03:01:52 - [INFO] - PORT TYPES CHECK PASSED: Netlist user_project_wrapper port types match the golden wrapper port types.
+2022-12-04 03:01:52 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_project_wrapper netlist passed all consistency checks.
+2022-12-04 03:01:52 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
+2022-12-04 03:01:52 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 14: GPIO-Defines
+2022-12-04 03:01:52 - [INFO] - GPIO-DEFINES: Checking verilog/rtl/user_defines.v, parsing files: ['/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_base.v', 'riscduino-qcore_q3_/verilog/rtl/user_defines.v', '/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_observe.v']
+2022-12-04 03:01:53 - [INFO] - GPIO-DEFINES report path: riscduino-qcore_q3_/jobs/mpw_precheck/2313daf6-2262-4ba5-8fab-30bc2b344377/outputs/reports/gpio_defines.report
+2022-12-04 03:01:53 - [INFO] - {{GPIO-DEFINES CHECK PASSED}} The user verilog/rtl/user_defines.v is valid.
+2022-12-04 03:01:53 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 14: XOR
+2022-12-04 03:05:31 - [INFO] - {{XOR CHECK UPDATE}} Total XOR differences: 0, for more details view riscduino-qcore_q3_/jobs/mpw_precheck/2313daf6-2262-4ba5-8fab-30bc2b344377/outputs/user_project_wrapper.xor.gds
+2022-12-04 03:05:31 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
+2022-12-04 03:05:31 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 14: Magic DRC
+2022-12-04 03:44:31 - [INFO] - 0 DRC violations
+2022-12-04 03:44:31 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-04 03:44:31 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 14: Klayout FEOL
+2022-12-04 03:44:31 - [INFO] - in CUSTOM klayout_gds_drc_check
+2022-12-04 03:44:31 - [INFO] - run: klayout -b -r /opt/checks/tech-files/sky130A_mr.drc -rd input=riscduino-qcore_q3_/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=riscduino-qcore_q3_/jobs/mpw_precheck/2313daf6-2262-4ba5-8fab-30bc2b344377/outputs/reports/klayout_feol_check.xml -rd feol=true >& riscduino-qcore_q3_/jobs/mpw_precheck/2313daf6-2262-4ba5-8fab-30bc2b344377/logs/klayout_feol_check.log
+2022-12-04 03:47:27 - [INFO] - No DRC Violations found
+2022-12-04 03:47:27 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-04 03:47:27 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 14: Klayout BEOL
+2022-12-04 03:47:27 - [INFO] - in CUSTOM klayout_gds_drc_check
+2022-12-04 03:47:27 - [INFO] - run: klayout -b -r /opt/checks/tech-files/sky130A_mr.drc -rd input=riscduino-qcore_q3_/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=riscduino-qcore_q3_/jobs/mpw_precheck/2313daf6-2262-4ba5-8fab-30bc2b344377/outputs/reports/klayout_beol_check.xml -rd beol=true >& riscduino-qcore_q3_/jobs/mpw_precheck/2313daf6-2262-4ba5-8fab-30bc2b344377/logs/klayout_beol_check.log
+2022-12-04 04:09:18 - [INFO] - No DRC Violations found
+2022-12-04 04:09:18 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-04 04:09:18 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 14: Klayout Offgrid
+2022-12-04 04:09:18 - [INFO] - in CUSTOM klayout_gds_drc_check
+2022-12-04 04:09:18 - [INFO] - run: klayout -b -r /opt/checks/tech-files/sky130A_mr.drc -rd input=riscduino-qcore_q3_/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=riscduino-qcore_q3_/jobs/mpw_precheck/2313daf6-2262-4ba5-8fab-30bc2b344377/outputs/reports/klayout_offgrid_check.xml -rd offgrid=true >& riscduino-qcore_q3_/jobs/mpw_precheck/2313daf6-2262-4ba5-8fab-30bc2b344377/logs/klayout_offgrid_check.log
+2022-12-04 04:13:34 - [INFO] - No DRC Violations found
+2022-12-04 04:13:34 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-04 04:13:34 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 14: Klayout Metal Minimum Clear Area Density
+2022-12-04 04:13:34 - [INFO] - in CUSTOM klayout_gds_drc_check
+2022-12-04 04:13:34 - [INFO] - run: klayout -b -r /opt/checks/drc_checks/klayout/met_min_ca_density.lydrc -rd input=riscduino-qcore_q3_/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=riscduino-qcore_q3_/jobs/mpw_precheck/2313daf6-2262-4ba5-8fab-30bc2b344377/outputs/reports/klayout_met_min_ca_density_check.xml >& riscduino-qcore_q3_/jobs/mpw_precheck/2313daf6-2262-4ba5-8fab-30bc2b344377/logs/klayout_met_min_ca_density_check.log
+2022-12-04 04:15:17 - [INFO] - No DRC Violations found
+2022-12-04 04:15:17 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-04 04:15:17 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 14: Klayout Pin Label Purposes Overlapping Drawing
+2022-12-04 04:15:17 - [INFO] - in CUSTOM klayout_gds_drc_check
+2022-12-04 04:15:17 - [INFO] - run: klayout -b -r /opt/checks/drc_checks/klayout/pin_label_purposes_overlapping_drawing.rb.drc -rd input=riscduino-qcore_q3_/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=riscduino-qcore_q3_/jobs/mpw_precheck/2313daf6-2262-4ba5-8fab-30bc2b344377/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml -rd top_cell_name=user_project_wrapper >& riscduino-qcore_q3_/jobs/mpw_precheck/2313daf6-2262-4ba5-8fab-30bc2b344377/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
+2022-12-04 04:15:55 - [INFO] - No DRC Violations found
+2022-12-04 04:15:55 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-04 04:15:55 - [INFO] - {{STEP UPDATE}} Executing Check 14 of 14: Klayout ZeroArea
+2022-12-04 04:15:55 - [INFO] - in CUSTOM klayout_gds_drc_check
+2022-12-04 04:15:55 - [INFO] - run: klayout -b -r /opt/checks/drc_checks/klayout/zeroarea.rb.drc -rd input=riscduino-qcore_q3_/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=riscduino-qcore_q3_/jobs/mpw_precheck/2313daf6-2262-4ba5-8fab-30bc2b344377/outputs/reports/klayout_zeroarea_check.xml -rd cleaned_output=riscduino-qcore_q3_/jobs/mpw_precheck/2313daf6-2262-4ba5-8fab-30bc2b344377/outputs/user_project_wrapper_no_zero_areas.gds >& riscduino-qcore_q3_/jobs/mpw_precheck/2313daf6-2262-4ba5-8fab-30bc2b344377/logs/klayout_zeroarea_check.log
+2022-12-04 04:16:16 - [INFO] - No DRC Violations found
+2022-12-04 04:16:16 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-04 04:16:16 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'riscduino-qcore_q3_/jobs/mpw_precheck/2313daf6-2262-4ba5-8fab-30bc2b344377/logs'
+2022-12-04 04:16:16 - [INFO] - {{SUCCESS}} All Checks Passed !!!
diff --git a/mpw_precheck/logs/spdx_compliance_report.log b/mpw_precheck/logs/spdx_compliance_report.log
new file mode 100644
index 0000000..99a923a
--- /dev/null
+++ b/mpw_precheck/logs/spdx_compliance_report.log
@@ -0,0 +1,385 @@
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+/root/riscduino-qcore_q3_/verilog/rtl/yifive/ycr4c/src/wb_top.files
+/root/riscduino-qcore_q3_/verilog/rtl/yifive/ycr4c/src/cache/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
+/root/riscduino-qcore_q3_/verilog/rtl/yifive/ycr4c/src/cache/src/core/ycr_cache_defs.svh
+/root/riscduino-qcore_q3_/verilog/rtl/yifive/ycr4c/src/cache/src/model/sky130_sram_2kbyte_1rw1r_32x512_8.v
+/root/riscduino-qcore_q3_/verilog/rtl/yifive/ycr4c/src/includes/ycr_cache_defs.svh
+/root/riscduino-qcore_q3_/verilog/rtl/yifive/ycr4c/src/lib/ctech_cells.sv
+/root/riscduino-qcore_q3_/verilog/rtl/yifive/ycr4c/synth/base.sdc
+/root/riscduino-qcore_q3_/verilog/rtl/yifive/ycr4c/synth/scripts/libtrim.pl
+/root/riscduino-qcore_q3_/verilog/rtl/yifive/ycr4c/tb/ahb_tb.files
+/root/riscduino-qcore_q3_/verilog/rtl/yifive/ycr4c/tb/axi_tb.files
+/root/riscduino-qcore_q3_/verilog/rtl/yifive/ycr4c/tb/sky130_sram_2kbyte_1rw1r_32x512_8.v
+/root/riscduino-qcore_q3_/verilog/rtl/yifive/ycr4c/tb/uprj_netlists.v
+/root/riscduino-qcore_q3_/verilog/rtl/yifive/ycr4c/tb/wb_tb.files
+/root/riscduino-qcore_q3_/verilog/rtl/yifive/ycr4c/tb/ycr_memory_tb_ahb.sv
+/root/riscduino-qcore_q3_/verilog/rtl/yifive/ycr4c/tb/ycr_memory_tb_axi.sv
+/root/riscduino-qcore_q3_/verilog/rtl/yifive/ycr4c/tb/ycr_memory_tb_wb.sv
+/root/riscduino-qcore_q3_/verilog/rtl/yifive/ycr4c/tb/ycr_top_tb_ahb.sv
+/root/riscduino-qcore_q3_/verilog/rtl/yifive/ycr4c/tb/ycr_top_tb_axi.sv
+/root/riscduino-qcore_q3_/verilog/rtl/yifive/ycr4c/tb/ycr_top_tb_runtests.sv
+/root/riscduino-qcore_q3_/verilog/rtl/yifive/ycr4c/tb/ycr_top_tb_wb.sv
diff --git a/mpw_precheck/logs/tools.info b/mpw_precheck/logs/tools.info
new file mode 100644
index 0000000..4056146
--- /dev/null
+++ b/mpw_precheck/logs/tools.info
@@ -0,0 +1,2 @@
+KLayout: 0.27.12
+Magic: 8.3.340
\ No newline at end of file
diff --git a/mpw_precheck/logs/xor_check.log b/mpw_precheck/logs/xor_check.log
new file mode 100644
index 0000000..c102968
--- /dev/null
+++ b/mpw_precheck/logs/xor_check.log
@@ -0,0 +1,747 @@
+Reading file /root/riscduino-qcore_q3_/gds/user_project_wrapper.gds for cell user_project_wrapper
+dbu=0.001
+cell user_project_wrapper dbu-bbox(ll;ur)=(-43630,-38270;2963250,3557950)
+cell user_project_wrapper dbu-bbox(left,bottom,right,top)=(-43630,-38270,2963250,3557950)
+cell user_project_wrapper dbu-size(width,height)=(3006880,3596220)
+cell user_project_wrapper micron-bbox(left,bottom,right,top)=(-43.63,-38.27,2963.25,3557.9500000000003)
+cell user_project_wrapper micron-size(width,height)=(3006.88,3596.2200000000003)
+Done.
+
+Magic 8.3 revision 340 - Compiled on Thu Nov 17 13:45:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/checks/xor_check/erase_box.tcl" from command line.
+CIF input style is now "sky130(vendor)"
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_project_wrapper
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_39".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_38".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_33".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_32".
+Reading "sky130_fd_bd_sram__openram_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wmask_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_data_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_29".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_28".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_360_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sli_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w0_740_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m7_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m7_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_delay_chain".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_10".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_rw".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_18".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_6".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_r".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec_0".
+CIF file read warning: CIF style sky130(vendor): units rescaled by factor of 5 / 1
+Reading "sky130_fd_bd_sram__openram_dp_nand2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec".
+Reading "sky130_fd_bd_sram__openram_dp_nand3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode3x8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_decoder".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_27".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_26".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_25".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_24".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w2_880_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array_0".
+Reading "sky130_fd_bd_sram__openram_sense_amp".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_sense_amp_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_23".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_21".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_22".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w0_550_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_mask_and_array".
+Reading "sky130_fd_bd_sram__openram_write_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_8".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_row".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 2620068): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 2620772): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 2621732): Unknown layer/datatype in boundary, layer=22 type=21
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_col".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array_0".
+Reading "sky130_fd_bd_sram__openram_dp_cell_dummy".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3113978): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3117754): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3121946): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3126746): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3128794): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dummy_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_replica".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3308236): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3312012): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3316204): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3322668): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3324844): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column".
+Reading "sky130_fd_bd_sram__openram_dp_cell".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3565294): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3569070): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3573262): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3579726): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3581902): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bitcell_array".
+    5000 uses
+    10000 uses
+    15000 uses
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_bitcell_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bank".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8".
+    5000 uses
+Reading "sky130_fd_sc_hd__o32a_2".
+Reading "sky130_fd_sc_hd__o21ai_2".
+Reading "sky130_ef_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__o2bb2a_2".
+Reading "sky130_fd_sc_hd__a221o_2".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__and4b_2".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__a31oi_2".
+Reading "sky130_fd_sc_hd__or4_2".
+Reading "sky130_fd_sc_hd__or3b_2".
+Reading "sky130_fd_sc_hd__or3_2".
+Reading "sky130_fd_sc_hd__and2b_2".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__xor2_2".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__a22o_2".
+Reading "sky130_fd_sc_hd__o21a_2".
+Reading "sky130_fd_sc_hd__a21oi_2".
+Reading "sky130_fd_sc_hd__nand2b_2".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__a21o_2".
+Reading "sky130_fd_sc_hd__o22a_2".
+Reading "sky130_fd_sc_hd__nand3b_2".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__a311o_2".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__a211o_2".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__clkinv_2".
+Reading "sky130_fd_sc_hd__and3_2".
+Reading "sky130_fd_sc_hd__a32o_2".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__xnor2_2".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__dfrtp_2".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__a2bb2o_2".
+Reading "sky130_fd_sc_hd__a22oi_1".
+Reading "sky130_fd_sc_hd__and4bb_4".
+Reading "sky130_fd_sc_hd__o211ai_4".
+Reading "sky130_fd_sc_hd__nand4_1".
+Reading "sky130_fd_sc_hd__a21bo_2".
+Reading "sky130_fd_sc_hd__nor4b_4".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__o41a_1".
+Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__o22ai_1".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "sky130_fd_sc_hd__a41o_1".
+Reading "sky130_fd_sc_hd__o32a_4".
+Reading "sky130_fd_sc_hd__a22oi_2".
+Reading "sky130_fd_sc_hd__nor4_1".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__a311o_1".
+Reading "sky130_fd_sc_hd__o211ai_2".
+Reading "sky130_fd_sc_hd__o31ai_4".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__a31o_4".
+Reading "sky130_fd_sc_hd__xor2_1".
+Reading "sky130_fd_sc_hd__a21boi_1".
+Reading "sky130_fd_sc_hd__dfstp_2".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__o22ai_4".
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__o2111ai_4".
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "sky130_fd_sc_hd__a21bo_1".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__o211a_1".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__o22ai_2".
+Reading "sky130_fd_sc_hd__a2111o_1".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__o21ba_1".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__o221a_1".
+Reading "sky130_fd_sc_hd__o31a_2".
+Reading "sky130_fd_sc_hd__a22oi_4".
+Reading "sky130_fd_sc_hd__dfxtp_4".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__mux4_2".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__or3b_1".
+Reading "sky130_fd_sc_hd__a22o_4".
+Reading "sky130_fd_sc_hd__a211oi_4".
+Reading "sky130_fd_sc_hd__a221oi_1".
+Reading "sky130_fd_sc_hd__a221oi_4".
+Reading "sky130_fd_sc_hd__o311a_2".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__a31o_1".
+Reading "sky130_fd_sc_hd__dfxtp_2".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__o2bb2a_1".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__a211oi_1".
+Reading "sky130_fd_sc_hd__mux4_1".
+Reading "sky130_fd_sc_hd__and4bb_1".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__or4_4".
+Reading "sky130_fd_sc_hd__or3_1".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__or4b_4".
+Reading "sky130_fd_sc_hd__or3_4".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__or4b_1".
+Reading "sky130_fd_sc_hd__nor4_4".
+Reading "sky130_fd_sc_hd__nand3_1".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__a2bb2o_1".
+Reading "sky130_fd_sc_hd__dfstp_1".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__or4_1".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_fd_sc_hd__dfrtp_1".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__o31ai_1".
+Reading "sky130_fd_sc_hd__nand2b_1".
+Reading "sky130_fd_sc_hd__a311oi_1".
+Reading "sky130_fd_sc_hd__nand2b_4".
+Reading "sky130_fd_sc_hd__or4bb_1".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__nor3_2".
+Reading "sky130_fd_sc_hd__nand4b_1".
+Reading "sky130_fd_sc_hd__xor2_4".
+Reading "sky130_fd_sc_hd__o21ba_2".
+Reading "sky130_fd_sc_hd__a2111o_2".
+Reading "sky130_fd_sc_hd__or3b_4".
+Reading "sky130_fd_sc_hd__a31oi_4".
+Reading "sky130_fd_sc_hd__nand3b_1".
+Reading "sky130_fd_sc_hd__nor4b_2".
+Reading "sky130_fd_sc_hd__a41o_2".
+Reading "sky130_fd_sc_hd__nor3b_4".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__a2111oi_4".
+Reading "sky130_fd_sc_hd__o32ai_1".
+Reading "sky130_fd_sc_hd__and4bb_2".
+Reading "sky130_fd_sc_hd__or4b_2".
+Reading "sky130_fd_sc_hd__nor3b_1".
+Reading "sky130_fd_sc_hd__nor4_2".
+Reading "sky130_fd_sc_hd__a311oi_4".
+Reading "sky130_fd_sc_hd__o21bai_2".
+Reading "sky130_fd_sc_hd__nor3b_2".
+Reading "sky130_fd_sc_hd__a311oi_2".
+Reading "sky130_fd_sc_hd__and3b_4".
+Reading "sky130_fd_sc_hd__a2bb2o_4".
+Reading "sky130_fd_sc_hd__a21bo_4".
+Reading "sky130_fd_sc_hd__xnor2_4".
+Reading "sky130_fd_sc_hd__o311ai_4".
+Reading "sky130_fd_sc_hd__o2bb2a_4".
+Reading "sky130_fd_sc_hd__o211a_4".
+Reading "sky130_fd_sc_hd__and2b_4".
+Reading "sky130_fd_sc_hd__o21bai_4".
+Reading "sky130_fd_sc_hd__nand3b_4".
+Reading "sky130_fd_sc_hd__o2111ai_1".
+Reading "sky130_fd_sc_hd__nand4_4".
+Reading "sky130_fd_sc_hd__o221ai_2".
+Reading "sky130_fd_sc_hd__o211ai_1".
+Reading "sky130_fd_sc_hd__o2bb2ai_4".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__nor4b_1".
+Reading "sky130_fd_sc_hd__o2111a_2".
+Reading "ycr_core_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+Reading "sky130_fd_sc_hd__and3b_2".
+Reading "sky130_fd_sc_hd__nand4_2".
+Reading "sky130_fd_sc_hd__o31ai_2".
+Reading "sky130_fd_sc_hd__nand3_2".
+Reading "sky130_fd_sc_hd__or2b_1".
+Reading "sky130_fd_sc_hd__o2bb2ai_2".
+Reading "sky130_fd_sc_hd__or2b_2".
+Reading "sky130_fd_sc_hd__and4_4".
+Reading "sky130_fd_sc_hd__a221o_4".
+Reading "sky130_fd_sc_hd__or4bb_4".
+Reading "sky130_fd_sc_hd__or2b_4".
+Reading "sky130_fd_sc_hd__o41ai_4".
+Reading "sky130_fd_sc_hd__a21boi_4".
+Reading "sky130_fd_sc_hd__o221ai_1".
+Reading "sky130_fd_sc_hd__o31a_4".
+Reading "sky130_fd_sc_hd__buf_1".
+Reading "sky130_fd_sc_hd__dlygate4sd1_1".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "ycr4_iconnect".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+    75000 uses
+    80000 uses
+    85000 uses
+    90000 uses
+    95000 uses
+    100000 uses
+Reading "sky130_fd_sc_hd__a2111oi_2".
+Reading "sky130_fd_sc_hd__a2111oi_1".
+CIF file read warning: Input off lambda grid by 2/5; snapped to grid.
+Reading "sky130_fd_sc_hd__o2bb2ai_1".
+Reading "sky130_fd_sc_hd__o41a_4".
+Reading "sky130_fd_sc_hd__nand4b_4".
+Reading "sky130_fd_sc_hd__a32o_4".
+Reading "sky130_fd_sc_hd__or4bb_2".
+Reading "ycr_intf".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+Reading "switchn".
+Reading "resistor".
+Reading "resistor_3xh".
+Reading "switch2".
+Reading "switch2n".
+Reading "2bit_DAC".
+Reading "resistor_h".
+Reading "3bit_DAC".
+Reading "4bit_DAC".
+Reading "5bit_DAC".
+Reading "6bit_DAC".
+Reading "7bit_DAC".
+Reading "8bit_DAC".
+Reading "2x8bit_DAC".
+Reading "4x8bit_DAC".
+Reading "dac_top".
+Reading "sky130_fd_sc_hd__einvn_8".
+Reading "sky130_fd_sc_hd__clkinv_1".
+Reading "sky130_fd_sc_hd__einvp_2".
+Reading "sky130_fd_sc_hd__einvn_2".
+Reading "sky130_fd_sc_hd__a21boi_2".
+Reading "sky130_fd_sc_hd__clkinv_8".
+Reading "sky130_fd_sc_hd__einvp_1".
+Reading "dg_pll".
+Reading "sky130_fd_sc_hd__a41oi_4".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__o311a_4".
+Reading "sky130_fd_sc_hd__o221a_4".
+Reading "sky130_fd_sc_hd__a41o_4".
+Reading "wb_interconnect".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "sky130_fd_sc_hd__o41a_2".
+Reading "sky130_fd_sc_hd__a211oi_2".
+Reading "sky130_fd_sc_hd__clkdlybuf4s50_1".
+Reading "qspim_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+Reading "sky130_fd_sc_hd__dlclkp_1".
+Reading "sky130_fd_sc_hd__dlclkp_4".
+Reading "sky130_fd_sc_hd__a32oi_4".
+Reading "sky130_fd_sc_hd__o311ai_2".
+Reading "sky130_fd_sc_hd__o2111ai_2".
+Reading "wb_host".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+Reading "sky130_fd_sc_hd__and4b_4".
+Reading "sky130_fd_sc_hd__nor2b_2".
+Reading "sky130_fd_sc_hd__nor2b_1".
+Reading "uart_i2c_usb_spi_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+Reading "sky130_fd_sc_hd__dlxtn_1".
+Reading "sky130_fd_sc_hd__dlxtn_2".
+Reading "sky130_fd_sc_hd__nand4b_2".
+Reading "sky130_fd_sc_hd__a32oi_1".
+Reading "pinmux_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+Reading "user_project_wrapper".
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  42.880 x 3520.000  (-42.880,  0.000), ( 0.000,  3520.000)  150937.594
+lambda:   4288.00 x 352000.00  (-4288.00,  0.00 ), (  0.00,  352000.00)  1509376000.00
+internal:   8576 x 704000  ( -8576,  0    ), (     0,  704000)  6037504000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  42.500 x 3520.000  ( 2920.000,  0.000), ( 2962.500,  3520.000)  149600.000
+lambda:   4250.00 x 352000.00  ( 292000.00,  0.00 ), ( 296250.00,  352000.00)  1496000000.00
+internal:   8500 x 704000  ( 584000,  0    ), ( 592500,  704000)  5984000000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.380 x 37.530  (-42.880, -37.530), ( 2962.500,  0.000)  112791.906
+lambda:   300538.00 x 3753.00  (-4288.00, -3753.00), ( 296250.00,  0.00 )  1127919104.00
+internal: 601076 x 7506    ( -8576, -7506 ), ( 592500,  0    )  4511676456
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.380 x 37.210  (-42.880,  3520.000), ( 2962.500,  3557.210)  111830.188
+lambda:   300538.00 x 3721.00  (-4288.00,  352000.00), ( 296250.00,  355721.00)  1118301952.00
+internal: 601076 x 7442    ( -8576,  704000), ( 592500,  711442)  4473207592
+   Generating output for cell xor_target
+
+Magic 8.3 revision 340 - Compiled on Thu Nov 17 13:45:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/checks/xor_check/erase_box.tcl" from command line.
+CIF input style is now "sky130(vendor)"
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_project_wrapper
+Reading "user_project_wrapper".
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  42.880 x 3520.000  (-42.880,  0.000), ( 0.000,  3520.000)  150937.594
+lambda:   4288.00 x 352000.00  (-4288.00,  0.00 ), (  0.00,  352000.00)  1509376000.00
+internal:   8576 x 704000  ( -8576,  0    ), (     0,  704000)  6037504000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  42.500 x 3520.000  ( 2920.000,  0.000), ( 2962.500,  3520.000)  149600.000
+lambda:   4250.00 x 352000.00  ( 292000.00,  0.00 ), ( 296250.00,  352000.00)  1496000000.00
+internal:   8500 x 704000  ( 584000,  0    ), ( 592500,  704000)  5984000000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.380 x 37.530  (-42.880, -37.530), ( 2962.500,  0.000)  112791.906
+lambda:   300538.00 x 3753.00  (-4288.00, -3753.00), ( 296250.00,  0.00 )  1127919104.00
+internal: 601076 x 7506    ( -8576, -7506 ), ( 592500,  0    )  4511676456
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.380 x 37.210  (-42.880,  3520.000), ( 2962.500,  3557.210)  111830.188
+lambda:   300538.00 x 3721.00  (-4288.00,  352000.00), ( 296250.00,  355721.00)  1118301952.00
+internal: 601076 x 7442    ( -8576,  704000), ( 592500,  711442)  4473207592
+   Generating output for cell xor_target
+Reading /mnt/uffs/user/u5295_dinesha/design/riscduino-qcore_q3_/jobs/mpw_precheck/2313daf6-2262-4ba5-8fab-30bc2b344377/outputs/user_project_wrapper_erased.gds ..
+Reading /mnt/uffs/user/u5295_dinesha/design/riscduino-qcore_q3_/jobs/mpw_precheck/2313daf6-2262-4ba5-8fab-30bc2b344377/outputs/user_project_wrapper_empty_erased.gds ..
+--- Running XOR for 69/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 530 (flat)  530 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 530 (flat)  530 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+--- Running XOR for 70/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 107 (flat)  107 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 107 (flat)  107 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+--- Running XOR for 71/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 16 (flat)  16 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 16 (flat)  16 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+--- Running XOR for 71/44 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 116 (flat)  116 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 116 (flat)  116 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+--- Running XOR for 72/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 16 (flat)  16 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 16 (flat)  16 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+--- Running XOR for 81/14 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 1 (flat)  1 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 1 (flat)  1 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+Writing layout file: /mnt/uffs/user/u5295_dinesha/design/riscduino-qcore_q3_/jobs/mpw_precheck/2313daf6-2262-4ba5-8fab-30bc2b344377/outputs/user_project_wrapper.xor.gds ..
+Total elapsed: 0.140s  Memory: 524.00M
diff --git a/mpw_precheck/logs/xor_check.total b/mpw_precheck/logs/xor_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/xor_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/outputs/reports/gpio_defines.report b/mpw_precheck/outputs/reports/gpio_defines.report
new file mode 100644
index 0000000..a5b0eaf
--- /dev/null
+++ b/mpw_precheck/outputs/reports/gpio_defines.report
@@ -0,0 +1,33 @@
+USER_CONFIG_GPIO_5_INIT    13'h1800
+USER_CONFIG_GPIO_6_INIT    13'h1800
+USER_CONFIG_GPIO_7_INIT    13'h1800
+USER_CONFIG_GPIO_8_INIT    13'h1800
+USER_CONFIG_GPIO_9_INIT    13'h1800
+USER_CONFIG_GPIO_10_INIT   13'h1800
+USER_CONFIG_GPIO_11_INIT   13'h1800
+USER_CONFIG_GPIO_12_INIT   13'h1800
+USER_CONFIG_GPIO_13_INIT   13'h1800
+USER_CONFIG_GPIO_14_INIT   13'h1800
+USER_CONFIG_GPIO_15_INIT   13'h1800
+USER_CONFIG_GPIO_16_INIT   13'h1800
+USER_CONFIG_GPIO_17_INIT   13'h1800
+USER_CONFIG_GPIO_18_INIT   13'h1800
+USER_CONFIG_GPIO_19_INIT   13'h1800
+USER_CONFIG_GPIO_20_INIT   13'h1800
+USER_CONFIG_GPIO_21_INIT   13'h1800
+USER_CONFIG_GPIO_22_INIT   13'h1800
+USER_CONFIG_GPIO_23_INIT   13'h1800
+USER_CONFIG_GPIO_24_INIT   13'h1800
+USER_CONFIG_GPIO_25_INIT   13'h1800
+USER_CONFIG_GPIO_26_INIT   13'h1800
+USER_CONFIG_GPIO_27_INIT   13'h1800
+USER_CONFIG_GPIO_28_INIT   13'h1800
+USER_CONFIG_GPIO_29_INIT   13'h1800
+USER_CONFIG_GPIO_30_INIT   13'h1800
+USER_CONFIG_GPIO_31_INIT   13'h1800
+USER_CONFIG_GPIO_32_INIT   13'h1800
+USER_CONFIG_GPIO_33_INIT   13'h1800
+USER_CONFIG_GPIO_34_INIT   13'h1800
+USER_CONFIG_GPIO_35_INIT   13'h1800
+USER_CONFIG_GPIO_36_INIT   13'h1800
+USER_CONFIG_GPIO_37_INIT   13'h1800
diff --git a/mpw_precheck/outputs/reports/klayout_beol_check.xml b/mpw_precheck/outputs/reports/klayout_beol_check.xml
new file mode 100644
index 0000000..5ffd971
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_beol_check.xml
@@ -0,0 +1,447 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>li.1</name>
+   <description>li.1 : min. li width : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.3</name>
+   <description>li.3 : min. li spacing : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.5</name>
+   <description>li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.6</name>
+   <description>li.6 : min. li area : 0.0561um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1</name>
+   <description>ct.1: non-ring mcon should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1_a</name>
+   <description>ct.1_a : minimum width of mcon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1_b</name>
+   <description>ct.1_b : maximum length of mcon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.2</name>
+   <description>ct.2 : min. mcon spacing : 0.19um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.4</name>
+   <description>ct.4 : mcon should covered by li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.1</name>
+   <description>m1.1 : min. m1 width : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.2</name>
+   <description>m1.2 : min. m1 spacing : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.3ab</name>
+   <description>m1.3ab : min. 3um.m1 spacing m1 : 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>791_m1.4</name>
+   <description>791_m1.4 : min. m1 enclosure of mcon : 0.03um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4</name>
+   <description>m1.4 : mcon periphery must be enclosed by m1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4a</name>
+   <description>m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4a_a</name>
+   <description>m1.4a_a : mcon periph must be enclosed by met1 for specific cells</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.6</name>
+   <description>m1.6 : min. m1 area : 0.083um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.7</name>
+   <description>m1.7 : min. m1 with holes area : 0.14um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.5</name>
+   <description>m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a</name>
+   <description>via.1a : via outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a_a</name>
+   <description>via.1a_a : min. width of via outside of moduleCut : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a_b</name>
+   <description>via.1a_b : maximum length of via : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.2</name>
+   <description>via.2 : min. via spacing : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.4a</name>
+   <description>via.4a : min. m1 enclosure of 0.15um via : 0.055um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.4a_a</name>
+   <description>via.4a_a : 0.15um via must be enclosed by met1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.5a</name>
+   <description>via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.1</name>
+   <description>m2.1 : min. m2 width : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.2</name>
+   <description>m2.2 : min. m2 spacing : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.3ab</name>
+   <description>m2.3ab : min. 3um.m2 spacing m2 : 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.6</name>
+   <description>m2.6 : min. m2 area : 0.0676um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.7</name>
+   <description>m2.7 : min. m2 holes area : 0.14um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.4</name>
+   <description>m2.4 : min. m2 enclosure of via : 0.055um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.4_a</name>
+   <description>m2.4_a : via in periphery must be enclosed by met2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.5</name>
+   <description>m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a</name>
+   <description>via2.1a : via2 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a_a</name>
+   <description>via2.1a_a : min. width of via2 outside of moduleCut : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a_b</name>
+   <description>via2.1a_b : maximum length of via2 : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.2</name>
+   <description>via2.2 : min. via2 spacing : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.4</name>
+   <description>via2.4 : min. m2 enclosure of via2 : 0.04um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.4_a</name>
+   <description>via2.4_a : via must be enclosed by met2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.5</name>
+   <description>via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.1</name>
+   <description>m3.1 : min. m3 width : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.2</name>
+   <description>m3.2 : min. m3 spacing : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.3cd</name>
+   <description>m3.3cd : min. 3um.m3 spacing m3 : 0.4um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.4</name>
+   <description>m3.4 : min. m3 enclosure of via2 : 0.065um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.4_a</name>
+   <description>m3.4_a : via2 must be enclosed by met3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1</name>
+   <description>via3.1 : via3 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1_a</name>
+   <description>via3.1_a : min. width of via3 outside of moduleCut : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1_b</name>
+   <description>via3.1_b : maximum length of via3 : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.2</name>
+   <description>via3.2 : min. via3 spacing : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.4</name>
+   <description>via3.4 : min. m3 enclosure of via3 : 0.06um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.4_a</name>
+   <description>via3.4_a : non-ring via3 must be enclosed by met3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.5</name>
+   <description>via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.1</name>
+   <description>m4.1 : min. m4 width : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.2</name>
+   <description>m4.2 : min. m4 spacing : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.4a</name>
+   <description>m4.4a : min. m4 area : 0.240um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.5ab</name>
+   <description>m4.5ab : min. 3um.m4 spacing m4 : 0.4um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.3</name>
+   <description>m4.3 : min. m4 enclosure of via3 : 0.065um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.3_a</name>
+   <description>m4.3_a : via3 must be enclosed by met4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1</name>
+   <description>via4.1 : via4 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1_a</name>
+   <description>via4.1_a : min. width of via4 outside of moduleCut : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1_b</name>
+   <description>via4.1_b : maximum length of via4 : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.2</name>
+   <description>via4.2 : min. via4 spacing : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.4</name>
+   <description>via4.4 : min. m4 enclosure of via4 : 0.19um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.4_a</name>
+   <description>via4.4_a : m4 must enclose all via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.1</name>
+   <description>m5.1 : min. m5 width : 1.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.2</name>
+   <description>m5.2 : min. m5 spacing : 1.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.3</name>
+   <description>m5.3 : min. m5 enclosure of via4 : 0.31um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.3_a</name>
+   <description>m5.3_a : via must be enclosed by m5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.4</name>
+   <description>m5.4 : min. m5 area : 4.0um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad.2</name>
+   <description>pad.2 : min. pad spacing : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_feol_check.xml b/mpw_precheck/outputs/reports/klayout_feol_check.xml
new file mode 100644
index 0000000..71b30a8
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_feol_check.xml
@@ -0,0 +1,375 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>dnwell.2</name>
+   <description>dnwell.2 : min. dnwell width : 3.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell.1</name>
+   <description>nwell.1 : min. nwell width : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell.2a</name>
+   <description>nwell.2a : min. nwell spacing (merged if less) : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell.6</name>
+   <description>nwell.6 : min enclosure of nwellHole by dnwell : 1.03um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp.1</name>
+   <description>hvtp.1 : min. hvtp width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp.2</name>
+   <description>hvtp.2 : min. hvtp spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.1</name>
+   <description>hvtr.1 : min. hvtr width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.2</name>
+   <description>hvtr.2 : min. hvtr spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.2_a</name>
+   <description>hvtr.2_a : hvtr must not overlap hvtp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn.1a</name>
+   <description>lvtn.1a : min. lvtn width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn.2</name>
+   <description>lvtn.2 : min. lvtn spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm.1</name>
+   <description>ncm.1 : min. ncm width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm.2a</name>
+   <description>ncm.2a : min. ncm spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1</name>
+   <description>difftap.1 : min. diff width across areaid:ce : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_a</name>
+   <description>difftap.1_a : min. diff width in periphery : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_b</name>
+   <description>difftap.1_b : min. tap width across areaid:ce : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_c</name>
+   <description>difftap.1_c : min. tap width in periphery : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.3</name>
+   <description>difftap.3 : min. difftap spacing : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm.1</name>
+   <description>tunm.1 : min. tunm width : 0.41um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm.2</name>
+   <description>tunm.2 : min. tunm spacing : 0.5um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly.1a</name>
+   <description>poly.1a : min. poly width : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly.2</name>
+   <description>poly.2 : min. poly spacing : 0.21um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm.1a</name>
+   <description>rpm.1a : min. rpm width : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm.2</name>
+   <description>rpm.2 : min. rpm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>urpm.1a</name>
+   <description>urpm.1a : min. rpm width : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>urpm.2</name>
+   <description>urpm.2 : min. rpm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc.1</name>
+   <description>npc.1 : min. npc width : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc.2</name>
+   <description>npc.2 : min. npc spacing, should be manually merged if less than : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsd.1</name>
+   <description>nsd.1 : min. nsdm width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsd.2</name>
+   <description>nsd.2 : min. nsdm spacing, should be manually merged if less than : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psd.1</name>
+   <description>psd.1 : min. psdm width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psd.2</name>
+   <description>psd.2 : min. psdm spacing, should be manually merged if less than : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.1</name>
+   <description>licon.1 : licon should be rectangle</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.1_a/b</name>
+   <description>licon.1_a/b : minimum/maximum width of licon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.13</name>
+   <description>licon.13 : min. difftap licon spacing to npc : 0.09um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.13_a</name>
+   <description>licon.13_a : licon of diffTap in periphery must not overlap npc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.17</name>
+   <description>licon.17 : Licons may not overlap both poly and (diff or tap)</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.1</name>
+   <description>capm.1 : min. capm width : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2a</name>
+   <description>capm.2a : min. capm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2b</name>
+   <description>capm.2b : min. capm spacing : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2b_a</name>
+   <description>capm.2b_a : min. spacing of m3_bot_plate : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.3</name>
+   <description>capm.3 : min. capm and m3 enclosure of m3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.3_a</name>
+   <description>capm.3_a : min. m3 enclosure of capm : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.4</name>
+   <description>capm.4 : min. capm enclosure of via3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.5</name>
+   <description>capm.5 : min. capm spacing to via3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.11</name>
+   <description>capm.11 : Min spacing of capm and met3 not overlapping capm : 0.5um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.1</name>
+   <description>cap2m.1 : min. cap2m width : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2a</name>
+   <description>cap2m.2a : min. cap2m spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2b</name>
+   <description>cap2m.2b : min. cap2m spacing : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2b_a</name>
+   <description>cap2m.2b_a : min. spacing of m4_bot_plate : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.3</name>
+   <description>cap2m.3 : min. m4 enclosure of cap2m : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.3_a</name>
+   <description>cap2m.3_a : min. m4 enclosure of cap2m : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.4</name>
+   <description>cap2m.4 : min. cap2m enclosure of via4 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.5</name>
+   <description>cap2m.5 : min. cap2m spacing to via4 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.11</name>
+   <description>cap2m.11 : Min spacing of cap2m and met4 not overlapping cap2m : 0.5um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi.1</name>
+   <description>hvi.1 : min. hvi width : 0.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi.2a</name>
+   <description>hvi.2a : min. hvi spacing : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm.1</name>
+   <description>hvntm.1 : min. hvntm width : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm.2</name>
+   <description>hvntm.2 : min. hvntm spacing : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_met_min_ca_density_check.xml b/mpw_precheck/outputs/reports/klayout_met_min_ca_density_check.xml
new file mode 100644
index 0000000..698a39a
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_met_min_ca_density_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>Density Checks</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/drc_checks/klayout/met_min_ca_density.lydrc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_offgrid_check.xml b/mpw_precheck/outputs/reports/klayout_offgrid_check.xml
new file mode 100644
index 0000000..95ebbc9
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_offgrid_check.xml
@@ -0,0 +1,483 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>dnwell_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on dnwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>dnwell_angle</name>
+   <description>x.3a : non 45 degree angle dnwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on nwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell_angle</name>
+   <description>x.3a : non 45 degree angle nwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwbm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pwbm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwbm_angle</name>
+   <description>x.3a : non 45 degree angle pwbm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwde_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pwde</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwde_angle</name>
+   <description>x.3a : non 45 degree angle pwde</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvtp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp_angle</name>
+   <description>x.3a : non 45 degree angle hvtp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvtr</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr_angle</name>
+   <description>x.3a : non 45 degree angle hvtr</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on lvtn</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn_angle</name>
+   <description>x.3a : non 45 degree angle lvtn</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on ncm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm_angle</name>
+   <description>x.3a : non 45 degree angle ncm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diff_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on diff</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tap_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on tap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diff_angle</name>
+   <description>x.2 : non 90 degree angle diff</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diff_angle</name>
+   <description>x.2c : non 45 degree angle diff</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tap_angle</name>
+   <description>x.2 : non 90 degree angle tap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tap_angle</name>
+   <description>x.2c : non 45 degree angle tap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on tunm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm_angle</name>
+   <description>x.3a : non 45 degree angle tunm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on poly</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly_angle</name>
+   <description>x.2 : non 90 degree angle poly</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on rpm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm_angle</name>
+   <description>x.3a : non 45 degree angle rpm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on npc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc_angle</name>
+   <description>x.3a : non 45 degree angle npc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsdm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on nsdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsdm_angle</name>
+   <description>x.3a : non 45 degree angle nsdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psdm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on psdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psdm_angle</name>
+   <description>x.3a : non 45 degree angle psdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on licon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon_angle</name>
+   <description>x.2 : non 90 degree angle licon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li_angle</name>
+   <description>x.3a : non 45 degree angle li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on mcon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct_angle</name>
+   <description>x.2 : non 90 degree angle mcon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vpp_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on vpp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vpp_angle</name>
+   <description>x.3a : non 45 degree angle vpp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1_angle</name>
+   <description>x.3a : non 45 degree angle m1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via_angle</name>
+   <description>x.2 : non 90 degree angle via</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2_angle</name>
+   <description>x.3a : non 45 degree angle m2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2_angle</name>
+   <description>x.2 : non 90 degree angle via2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3_angle</name>
+   <description>x.3a : non 45 degree angle m3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3_angle</name>
+   <description>x.2 : non 90 degree angle via3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on nsm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm_angle</name>
+   <description>x.3a : non 45 degree angle nsm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4_angle</name>
+   <description>x.3a : non 45 degree angle m4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4_angle</name>
+   <description>x.2 : non 90 degree angle via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5_angle</name>
+   <description>x.3a : non 45 degree angle m5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pad</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad_angle</name>
+   <description>x.3a : non 45 degree angle pad</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mf_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on mf</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mf_angle</name>
+   <description>x.2 : non 90 degree angle mf</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi_angle</name>
+   <description>x.3a : non 45 degree angle hvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvntm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm_angle</name>
+   <description>x.3a : non 45 degree angle hvntm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vhvi_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on vhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vhvi_angle</name>
+   <description>x.3a : non 45 degree angle vhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>uhvi_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on uhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>uhvi_angle</name>
+   <description>x.3a : non 45 degree angle uhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwell_rs_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pwell_rs</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwell_rs_angle</name>
+   <description>x.3a : non 45 degree angle pwell_rs</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>areaid_re_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on areaid.re</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml b/mpw_precheck/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
new file mode 100644
index 0000000..69dfb8c
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>pin_label_purposes_overlapping_drawing.rb.drc, input=/root/riscduino-qcore_q3_/gds/user_project_wrapper.gds, topcell=user_project_wrapper</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/drc_checks/klayout/pin_label_purposes_overlapping_drawing.rb.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_zeroarea_check.xml b/mpw_precheck/outputs/reports/klayout_zeroarea_check.xml
new file mode 100644
index 0000000..7f95f69
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_zeroarea_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>zero area check</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/drc_checks/klayout/zeroarea.rb.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.drc.report b/mpw_precheck/outputs/reports/magic_drc_check.drc.report
new file mode 100644
index 0000000..46ca7f3
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.drc.report
@@ -0,0 +1,5 @@
+user_project_wrapper
+----------------------------------------
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.rdb b/mpw_precheck/outputs/reports/magic_drc_check.rdb
new file mode 100644
index 0000000..ac5b3c4
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.rdb
@@ -0,0 +1,2 @@
+$user_project_wrapper
+ 100
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.tcl b/mpw_precheck/outputs/reports/magic_drc_check.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.tcl
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.tr b/mpw_precheck/outputs/reports/magic_drc_check.tr
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.tr
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.xml b/mpw_precheck/outputs/reports/magic_drc_check.xml
new file mode 100644
index 0000000..0eff265
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" ?>
+<report-database>
+    <categories/>
+    <cells>
+        <cell>
+            <name>user_project_wrapper</name>
+        </cell>
+    </cells>
+    <items/>
+</report-database>
diff --git a/mpw_precheck/outputs/user_project_wrapper.filtered.v b/mpw_precheck/outputs/user_project_wrapper.filtered.v
new file mode 100644
index 0000000..b461cc2
--- /dev/null
+++ b/mpw_precheck/outputs/user_project_wrapper.filtered.v
@@ -0,0 +1,9833 @@
+module user_project_wrapper (user_clock2,
+    wb_clk_i,
+    wb_rst_i,
+    wbs_ack_o,
+    wbs_cyc_i,
+    wbs_stb_i,
+    wbs_we_i,
+    vssa2,
+    vdda2,
+    vssa1,
+    vdda1,
+    vssd2,
+    vccd2,
+    vssd1,
+    vccd1,
+    analog_io,
+    io_in,
+    io_oeb,
+    io_out,
+    la_data_in,
+    la_data_out,
+    la_oenb,
+    user_irq,
+    wbs_adr_i,
+    wbs_dat_i,
+    wbs_dat_o,
+    wbs_sel_i);
+ input user_clock2;
+ input wb_clk_i;
+ input wb_rst_i;
+ output wbs_ack_o;
+ input wbs_cyc_i;
+ input wbs_stb_i;
+ input wbs_we_i;
+ input vssa2;
+ input vdda2;
+ input vssa1;
+ input vdda1;
+ input vssd2;
+ input vccd2;
+ input vssd1;
+ input vccd1;
+ inout [28:0] analog_io;
+ input [37:0] io_in;
+ output [37:0] io_oeb;
+ output [37:0] io_out;
+ input [127:0] la_data_in;
+ output [127:0] la_data_out;
+ input [127:0] la_oenb;
+ output [2:0] user_irq;
+ input [31:0] wbs_adr_i;
+ input [31:0] wbs_dat_i;
+ output [31:0] wbs_dat_o;
+ input [3:0] wbs_sel_i;
+
+ wire \cfg_ccska_aes_rp[0] ;
+ wire \cfg_ccska_aes_rp[1] ;
+ wire \cfg_ccska_aes_rp[2] ;
+ wire \cfg_ccska_aes_rp[3] ;
+ wire \cfg_ccska_fpu_rp[0] ;
+ wire \cfg_ccska_fpu_rp[1] ;
+ wire \cfg_ccska_fpu_rp[2] ;
+ wire \cfg_ccska_fpu_rp[3] ;
+ wire \cfg_clk_skew_ctrl1[0] ;
+ wire \cfg_clk_skew_ctrl1[10] ;
+ wire \cfg_clk_skew_ctrl1[11] ;
+ wire \cfg_clk_skew_ctrl1[12] ;
+ wire \cfg_clk_skew_ctrl1[13] ;
+ wire \cfg_clk_skew_ctrl1[14] ;
+ wire \cfg_clk_skew_ctrl1[15] ;
+ wire \cfg_clk_skew_ctrl1[16] ;
+ wire \cfg_clk_skew_ctrl1[17] ;
+ wire \cfg_clk_skew_ctrl1[18] ;
+ wire \cfg_clk_skew_ctrl1[19] ;
+ wire \cfg_clk_skew_ctrl1[1] ;
+ wire \cfg_clk_skew_ctrl1[20] ;
+ wire \cfg_clk_skew_ctrl1[21] ;
+ wire \cfg_clk_skew_ctrl1[22] ;
+ wire \cfg_clk_skew_ctrl1[23] ;
+ wire \cfg_clk_skew_ctrl1[24] ;
+ wire \cfg_clk_skew_ctrl1[25] ;
+ wire \cfg_clk_skew_ctrl1[26] ;
+ wire \cfg_clk_skew_ctrl1[27] ;
+ wire \cfg_clk_skew_ctrl1[28] ;
+ wire \cfg_clk_skew_ctrl1[29] ;
+ wire \cfg_clk_skew_ctrl1[2] ;
+ wire \cfg_clk_skew_ctrl1[30] ;
+ wire \cfg_clk_skew_ctrl1[31] ;
+ wire \cfg_clk_skew_ctrl1[3] ;
+ wire \cfg_clk_skew_ctrl1[4] ;
+ wire \cfg_clk_skew_ctrl1[5] ;
+ wire \cfg_clk_skew_ctrl1[6] ;
+ wire \cfg_clk_skew_ctrl1[7] ;
+ wire \cfg_clk_skew_ctrl1[8] ;
+ wire \cfg_clk_skew_ctrl1[9] ;
+ wire \cfg_clk_skew_ctrl2[0] ;
+ wire \cfg_clk_skew_ctrl2[10] ;
+ wire \cfg_clk_skew_ctrl2[11] ;
+ wire \cfg_clk_skew_ctrl2[12] ;
+ wire \cfg_clk_skew_ctrl2[13] ;
+ wire \cfg_clk_skew_ctrl2[14] ;
+ wire \cfg_clk_skew_ctrl2[15] ;
+ wire \cfg_clk_skew_ctrl2[16] ;
+ wire \cfg_clk_skew_ctrl2[17] ;
+ wire \cfg_clk_skew_ctrl2[18] ;
+ wire \cfg_clk_skew_ctrl2[19] ;
+ wire \cfg_clk_skew_ctrl2[1] ;
+ wire \cfg_clk_skew_ctrl2[20] ;
+ wire \cfg_clk_skew_ctrl2[21] ;
+ wire \cfg_clk_skew_ctrl2[22] ;
+ wire \cfg_clk_skew_ctrl2[23] ;
+ wire \cfg_clk_skew_ctrl2[24] ;
+ wire \cfg_clk_skew_ctrl2[25] ;
+ wire \cfg_clk_skew_ctrl2[26] ;
+ wire \cfg_clk_skew_ctrl2[27] ;
+ wire \cfg_clk_skew_ctrl2[28] ;
+ wire \cfg_clk_skew_ctrl2[29] ;
+ wire \cfg_clk_skew_ctrl2[2] ;
+ wire \cfg_clk_skew_ctrl2[30] ;
+ wire \cfg_clk_skew_ctrl2[31] ;
+ wire \cfg_clk_skew_ctrl2[3] ;
+ wire \cfg_clk_skew_ctrl2[4] ;
+ wire \cfg_clk_skew_ctrl2[5] ;
+ wire \cfg_clk_skew_ctrl2[6] ;
+ wire \cfg_clk_skew_ctrl2[7] ;
+ wire \cfg_clk_skew_ctrl2[8] ;
+ wire \cfg_clk_skew_ctrl2[9] ;
+ wire \cfg_dac0_mux_sel[0] ;
+ wire \cfg_dac0_mux_sel[1] ;
+ wire \cfg_dac0_mux_sel[2] ;
+ wire \cfg_dac0_mux_sel[3] ;
+ wire \cfg_dac0_mux_sel[4] ;
+ wire \cfg_dac0_mux_sel[5] ;
+ wire \cfg_dac0_mux_sel[6] ;
+ wire \cfg_dac0_mux_sel[7] ;
+ wire \cfg_dac1_mux_sel[0] ;
+ wire \cfg_dac1_mux_sel[1] ;
+ wire \cfg_dac1_mux_sel[2] ;
+ wire \cfg_dac1_mux_sel[3] ;
+ wire \cfg_dac1_mux_sel[4] ;
+ wire \cfg_dac1_mux_sel[5] ;
+ wire \cfg_dac1_mux_sel[6] ;
+ wire \cfg_dac1_mux_sel[7] ;
+ wire \cfg_dac2_mux_sel[0] ;
+ wire \cfg_dac2_mux_sel[1] ;
+ wire \cfg_dac2_mux_sel[2] ;
+ wire \cfg_dac2_mux_sel[3] ;
+ wire \cfg_dac2_mux_sel[4] ;
+ wire \cfg_dac2_mux_sel[5] ;
+ wire \cfg_dac2_mux_sel[6] ;
+ wire \cfg_dac2_mux_sel[7] ;
+ wire \cfg_dac3_mux_sel[0] ;
+ wire \cfg_dac3_mux_sel[1] ;
+ wire \cfg_dac3_mux_sel[2] ;
+ wire \cfg_dac3_mux_sel[3] ;
+ wire \cfg_dac3_mux_sel[4] ;
+ wire \cfg_dac3_mux_sel[5] ;
+ wire \cfg_dac3_mux_sel[6] ;
+ wire \cfg_dac3_mux_sel[7] ;
+ wire \cfg_dc_trim[0] ;
+ wire \cfg_dc_trim[10] ;
+ wire \cfg_dc_trim[11] ;
+ wire \cfg_dc_trim[12] ;
+ wire \cfg_dc_trim[13] ;
+ wire \cfg_dc_trim[14] ;
+ wire \cfg_dc_trim[15] ;
+ wire \cfg_dc_trim[16] ;
+ wire \cfg_dc_trim[17] ;
+ wire \cfg_dc_trim[18] ;
+ wire \cfg_dc_trim[19] ;
+ wire \cfg_dc_trim[1] ;
+ wire \cfg_dc_trim[20] ;
+ wire \cfg_dc_trim[21] ;
+ wire \cfg_dc_trim[22] ;
+ wire \cfg_dc_trim[23] ;
+ wire \cfg_dc_trim[24] ;
+ wire \cfg_dc_trim[25] ;
+ wire \cfg_dc_trim[2] ;
+ wire \cfg_dc_trim[3] ;
+ wire \cfg_dc_trim[4] ;
+ wire \cfg_dc_trim[5] ;
+ wire \cfg_dc_trim[6] ;
+ wire \cfg_dc_trim[7] ;
+ wire \cfg_dc_trim[8] ;
+ wire \cfg_dc_trim[9] ;
+ wire cfg_dco_mode;
+ wire cfg_pll_enb;
+ wire \cfg_pll_fed_div[0] ;
+ wire \cfg_pll_fed_div[1] ;
+ wire \cfg_pll_fed_div[2] ;
+ wire \cfg_pll_fed_div[3] ;
+ wire \cfg_pll_fed_div[4] ;
+ wire \cfg_riscv_ctrl[0] ;
+ wire \cfg_riscv_ctrl[10] ;
+ wire \cfg_riscv_ctrl[11] ;
+ wire \cfg_riscv_ctrl[12] ;
+ wire \cfg_riscv_ctrl[13] ;
+ wire \cfg_riscv_ctrl[14] ;
+ wire \cfg_riscv_ctrl[15] ;
+ wire \cfg_riscv_ctrl[1] ;
+ wire \cfg_riscv_ctrl[2] ;
+ wire \cfg_riscv_ctrl[3] ;
+ wire \cfg_riscv_ctrl[4] ;
+ wire \cfg_riscv_ctrl[5] ;
+ wire \cfg_riscv_ctrl[6] ;
+ wire \cfg_riscv_ctrl[7] ;
+ wire \cfg_riscv_ctrl[8] ;
+ wire \cfg_riscv_ctrl[9] ;
+ wire cfg_strap_pad_ctrl;
+ wire cfg_strap_pad_ctrl_rp;
+ wire \cfg_wcska_pinmux_rp[0] ;
+ wire \cfg_wcska_pinmux_rp[1] ;
+ wire \cfg_wcska_pinmux_rp[2] ;
+ wire \cfg_wcska_pinmux_rp[3] ;
+ wire \cfg_wcska_qspi_co_rp[0] ;
+ wire \cfg_wcska_qspi_co_rp[1] ;
+ wire \cfg_wcska_qspi_co_rp[2] ;
+ wire \cfg_wcska_qspi_co_rp[3] ;
+ wire \cfg_wcska_qspi_rp[0] ;
+ wire \cfg_wcska_qspi_rp[1] ;
+ wire \cfg_wcska_qspi_rp[2] ;
+ wire \cfg_wcska_qspi_rp[3] ;
+ wire \cfg_wcska_uart_rp[0] ;
+ wire \cfg_wcska_uart_rp[1] ;
+ wire \cfg_wcska_uart_rp[2] ;
+ wire \cfg_wcska_uart_rp[3] ;
+ wire cpu_clk;
+ wire \cpu_clk_rp[2] ;
+ wire e_reset_n;
+ wire e_reset_n_rp;
+ wire i2c_rst_n;
+ wire i2cm_clk_i;
+ wire i2cm_clk_o;
+ wire i2cm_clk_oen;
+ wire i2cm_data_i;
+ wire i2cm_data_o;
+ wire i2cm_data_oen;
+ wire i2cm_intr_o;
+ wire \irq_lines[0] ;
+ wire \irq_lines[10] ;
+ wire \irq_lines[11] ;
+ wire \irq_lines[12] ;
+ wire \irq_lines[13] ;
+ wire \irq_lines[14] ;
+ wire \irq_lines[15] ;
+ wire \irq_lines[16] ;
+ wire \irq_lines[17] ;
+ wire \irq_lines[18] ;
+ wire \irq_lines[19] ;
+ wire \irq_lines[1] ;
+ wire \irq_lines[20] ;
+ wire \irq_lines[21] ;
+ wire \irq_lines[22] ;
+ wire \irq_lines[23] ;
+ wire \irq_lines[24] ;
+ wire \irq_lines[25] ;
+ wire \irq_lines[26] ;
+ wire \irq_lines[27] ;
+ wire \irq_lines[28] ;
+ wire \irq_lines[29] ;
+ wire \irq_lines[2] ;
+ wire \irq_lines[30] ;
+ wire \irq_lines[31] ;
+ wire \irq_lines[3] ;
+ wire \irq_lines[4] ;
+ wire \irq_lines[5] ;
+ wire \irq_lines[6] ;
+ wire \irq_lines[7] ;
+ wire \irq_lines[8] ;
+ wire \irq_lines[9] ;
+ wire p_reset_n;
+ wire p_reset_n_rp;
+ wire \pll_clk_out[0] ;
+ wire \pll_clk_out[1] ;
+ wire pll_ref_clk;
+ wire pulse1m_mclk;
+ wire qspim_rst_n;
+ wire s_reset_n;
+ wire \sflash_di[0] ;
+ wire \sflash_di[1] ;
+ wire \sflash_di[2] ;
+ wire \sflash_di[3] ;
+ wire \sflash_do[0] ;
+ wire \sflash_do[1] ;
+ wire \sflash_do[2] ;
+ wire \sflash_do[3] ;
+ wire \sflash_oen[0] ;
+ wire \sflash_oen[1] ;
+ wire \sflash_oen[2] ;
+ wire \sflash_oen[3] ;
+ wire sflash_sck;
+ wire soft_irq;
+ wire \spi_csn[0] ;
+ wire \spi_csn[1] ;
+ wire \spi_csn[2] ;
+ wire \spi_csn[3] ;
+ wire sspim_rst_n;
+ wire sspim_sck;
+ wire sspim_si;
+ wire sspim_so;
+ wire \sspim_ssn[0] ;
+ wire \sspim_ssn[1] ;
+ wire \sspim_ssn[2] ;
+ wire \sspim_ssn[3] ;
+ wire sspis_sck;
+ wire sspis_si;
+ wire sspis_so;
+ wire sspis_ssn;
+ wire \strap_sticky[0] ;
+ wire \strap_sticky[10] ;
+ wire \strap_sticky[11] ;
+ wire \strap_sticky[12] ;
+ wire \strap_sticky[13] ;
+ wire \strap_sticky[14] ;
+ wire \strap_sticky[15] ;
+ wire \strap_sticky[16] ;
+ wire \strap_sticky[17] ;
+ wire \strap_sticky[18] ;
+ wire \strap_sticky[19] ;
+ wire \strap_sticky[1] ;
+ wire \strap_sticky[20] ;
+ wire \strap_sticky[21] ;
+ wire \strap_sticky[22] ;
+ wire \strap_sticky[23] ;
+ wire \strap_sticky[24] ;
+ wire \strap_sticky[25] ;
+ wire \strap_sticky[26] ;
+ wire \strap_sticky[27] ;
+ wire \strap_sticky[28] ;
+ wire \strap_sticky[29] ;
+ wire \strap_sticky[2] ;
+ wire \strap_sticky[30] ;
+ wire \strap_sticky[31] ;
+ wire \strap_sticky[3] ;
+ wire \strap_sticky[4] ;
+ wire \strap_sticky[5] ;
+ wire \strap_sticky[6] ;
+ wire \strap_sticky[7] ;
+ wire \strap_sticky[8] ;
+ wire \strap_sticky[9] ;
+ wire \strap_sticky_rp[0] ;
+ wire \strap_sticky_rp[10] ;
+ wire \strap_sticky_rp[11] ;
+ wire \strap_sticky_rp[12] ;
+ wire \strap_sticky_rp[13] ;
+ wire \strap_sticky_rp[14] ;
+ wire \strap_sticky_rp[15] ;
+ wire \strap_sticky_rp[16] ;
+ wire \strap_sticky_rp[17] ;
+ wire \strap_sticky_rp[18] ;
+ wire \strap_sticky_rp[19] ;
+ wire \strap_sticky_rp[1] ;
+ wire \strap_sticky_rp[20] ;
+ wire \strap_sticky_rp[21] ;
+ wire \strap_sticky_rp[22] ;
+ wire \strap_sticky_rp[23] ;
+ wire \strap_sticky_rp[24] ;
+ wire \strap_sticky_rp[25] ;
+ wire \strap_sticky_rp[26] ;
+ wire \strap_sticky_rp[27] ;
+ wire \strap_sticky_rp[28] ;
+ wire \strap_sticky_rp[29] ;
+ wire \strap_sticky_rp[2] ;
+ wire \strap_sticky_rp[30] ;
+ wire \strap_sticky_rp[31] ;
+ wire \strap_sticky_rp[3] ;
+ wire \strap_sticky_rp[4] ;
+ wire \strap_sticky_rp[5] ;
+ wire \strap_sticky_rp[6] ;
+ wire \strap_sticky_rp[7] ;
+ wire \strap_sticky_rp[8] ;
+ wire \strap_sticky_rp[9] ;
+ wire \strap_uartm[0] ;
+ wire \strap_uartm[1] ;
+ wire \strap_uartm_rp[0] ;
+ wire \strap_uartm_rp[1] ;
+ wire \system_strap[0] ;
+ wire \system_strap[10] ;
+ wire \system_strap[11] ;
+ wire \system_strap[12] ;
+ wire \system_strap[13] ;
+ wire \system_strap[14] ;
+ wire \system_strap[15] ;
+ wire \system_strap[16] ;
+ wire \system_strap[17] ;
+ wire \system_strap[18] ;
+ wire \system_strap[19] ;
+ wire \system_strap[1] ;
+ wire \system_strap[20] ;
+ wire \system_strap[21] ;
+ wire \system_strap[22] ;
+ wire \system_strap[23] ;
+ wire \system_strap[24] ;
+ wire \system_strap[25] ;
+ wire \system_strap[26] ;
+ wire \system_strap[27] ;
+ wire \system_strap[28] ;
+ wire \system_strap[29] ;
+ wire \system_strap[2] ;
+ wire \system_strap[30] ;
+ wire \system_strap[31] ;
+ wire \system_strap[3] ;
+ wire \system_strap[4] ;
+ wire \system_strap[5] ;
+ wire \system_strap[6] ;
+ wire \system_strap[7] ;
+ wire \system_strap[8] ;
+ wire \system_strap[9] ;
+ wire \system_strap_rp[0] ;
+ wire \system_strap_rp[10] ;
+ wire \system_strap_rp[11] ;
+ wire \system_strap_rp[12] ;
+ wire \system_strap_rp[13] ;
+ wire \system_strap_rp[14] ;
+ wire \system_strap_rp[15] ;
+ wire \system_strap_rp[16] ;
+ wire \system_strap_rp[17] ;
+ wire \system_strap_rp[18] ;
+ wire \system_strap_rp[19] ;
+ wire \system_strap_rp[1] ;
+ wire \system_strap_rp[20] ;
+ wire \system_strap_rp[21] ;
+ wire \system_strap_rp[22] ;
+ wire \system_strap_rp[23] ;
+ wire \system_strap_rp[24] ;
+ wire \system_strap_rp[25] ;
+ wire \system_strap_rp[26] ;
+ wire \system_strap_rp[27] ;
+ wire \system_strap_rp[28] ;
+ wire \system_strap_rp[29] ;
+ wire \system_strap_rp[2] ;
+ wire \system_strap_rp[30] ;
+ wire \system_strap_rp[31] ;
+ wire \system_strap_rp[3] ;
+ wire \system_strap_rp[4] ;
+ wire \system_strap_rp[5] ;
+ wire \system_strap_rp[6] ;
+ wire \system_strap_rp[7] ;
+ wire \system_strap_rp[8] ;
+ wire \system_strap_rp[9] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core0[0] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core0[1] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core0[2] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core0[3] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core1[0] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core1[1] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core1[2] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core1[3] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core2[0] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core2[1] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core2[2] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core2[3] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core3[0] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core3[1] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core3[2] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core3[3] ;
+ wire \u_riscv_top.cfg_ccska_riscv_icon[0] ;
+ wire \u_riscv_top.cfg_ccska_riscv_icon[1] ;
+ wire \u_riscv_top.cfg_ccska_riscv_icon[2] ;
+ wire \u_riscv_top.cfg_ccska_riscv_icon[3] ;
+ wire \u_riscv_top.cfg_ccska_riscv_intf[0] ;
+ wire \u_riscv_top.cfg_ccska_riscv_intf[1] ;
+ wire \u_riscv_top.cfg_ccska_riscv_intf[2] ;
+ wire \u_riscv_top.cfg_ccska_riscv_intf[3] ;
+ wire \u_riscv_top.cfg_dcache_force_flush ;
+ wire \u_riscv_top.cfg_wcska_riscv_intf[0] ;
+ wire \u_riscv_top.cfg_wcska_riscv_intf[1] ;
+ wire \u_riscv_top.cfg_wcska_riscv_intf[2] ;
+ wire \u_riscv_top.cfg_wcska_riscv_intf[3] ;
+ wire \u_riscv_top.core0_clk ;
+ wire \u_riscv_top.core0_debug[0] ;
+ wire \u_riscv_top.core0_debug[10] ;
+ wire \u_riscv_top.core0_debug[11] ;
+ wire \u_riscv_top.core0_debug[12] ;
+ wire \u_riscv_top.core0_debug[13] ;
+ wire \u_riscv_top.core0_debug[14] ;
+ wire \u_riscv_top.core0_debug[15] ;
+ wire \u_riscv_top.core0_debug[16] ;
+ wire \u_riscv_top.core0_debug[17] ;
+ wire \u_riscv_top.core0_debug[18] ;
+ wire \u_riscv_top.core0_debug[19] ;
+ wire \u_riscv_top.core0_debug[1] ;
+ wire \u_riscv_top.core0_debug[20] ;
+ wire \u_riscv_top.core0_debug[21] ;
+ wire \u_riscv_top.core0_debug[22] ;
+ wire \u_riscv_top.core0_debug[23] ;
+ wire \u_riscv_top.core0_debug[24] ;
+ wire \u_riscv_top.core0_debug[25] ;
+ wire \u_riscv_top.core0_debug[26] ;
+ wire \u_riscv_top.core0_debug[27] ;
+ wire \u_riscv_top.core0_debug[28] ;
+ wire \u_riscv_top.core0_debug[29] ;
+ wire \u_riscv_top.core0_debug[2] ;
+ wire \u_riscv_top.core0_debug[30] ;
+ wire \u_riscv_top.core0_debug[31] ;
+ wire \u_riscv_top.core0_debug[32] ;
+ wire \u_riscv_top.core0_debug[33] ;
+ wire \u_riscv_top.core0_debug[34] ;
+ wire \u_riscv_top.core0_debug[35] ;
+ wire \u_riscv_top.core0_debug[36] ;
+ wire \u_riscv_top.core0_debug[37] ;
+ wire \u_riscv_top.core0_debug[38] ;
+ wire \u_riscv_top.core0_debug[39] ;
+ wire \u_riscv_top.core0_debug[3] ;
+ wire \u_riscv_top.core0_debug[40] ;
+ wire \u_riscv_top.core0_debug[41] ;
+ wire \u_riscv_top.core0_debug[42] ;
+ wire \u_riscv_top.core0_debug[43] ;
+ wire \u_riscv_top.core0_debug[44] ;
+ wire \u_riscv_top.core0_debug[45] ;
+ wire \u_riscv_top.core0_debug[46] ;
+ wire \u_riscv_top.core0_debug[47] ;
+ wire \u_riscv_top.core0_debug[48] ;
+ wire \u_riscv_top.core0_debug[4] ;
+ wire \u_riscv_top.core0_debug[5] ;
+ wire \u_riscv_top.core0_debug[6] ;
+ wire \u_riscv_top.core0_debug[7] ;
+ wire \u_riscv_top.core0_debug[8] ;
+ wire \u_riscv_top.core0_debug[9] ;
+ wire \u_riscv_top.core0_dmem_addr[0] ;
+ wire \u_riscv_top.core0_dmem_addr[10] ;
+ wire \u_riscv_top.core0_dmem_addr[11] ;
+ wire \u_riscv_top.core0_dmem_addr[12] ;
+ wire \u_riscv_top.core0_dmem_addr[13] ;
+ wire \u_riscv_top.core0_dmem_addr[14] ;
+ wire \u_riscv_top.core0_dmem_addr[15] ;
+ wire \u_riscv_top.core0_dmem_addr[16] ;
+ wire \u_riscv_top.core0_dmem_addr[17] ;
+ wire \u_riscv_top.core0_dmem_addr[18] ;
+ wire \u_riscv_top.core0_dmem_addr[19] ;
+ wire \u_riscv_top.core0_dmem_addr[1] ;
+ wire \u_riscv_top.core0_dmem_addr[20] ;
+ wire \u_riscv_top.core0_dmem_addr[21] ;
+ wire \u_riscv_top.core0_dmem_addr[22] ;
+ wire \u_riscv_top.core0_dmem_addr[23] ;
+ wire \u_riscv_top.core0_dmem_addr[24] ;
+ wire \u_riscv_top.core0_dmem_addr[25] ;
+ wire \u_riscv_top.core0_dmem_addr[26] ;
+ wire \u_riscv_top.core0_dmem_addr[27] ;
+ wire \u_riscv_top.core0_dmem_addr[28] ;
+ wire \u_riscv_top.core0_dmem_addr[29] ;
+ wire \u_riscv_top.core0_dmem_addr[2] ;
+ wire \u_riscv_top.core0_dmem_addr[30] ;
+ wire \u_riscv_top.core0_dmem_addr[31] ;
+ wire \u_riscv_top.core0_dmem_addr[3] ;
+ wire \u_riscv_top.core0_dmem_addr[4] ;
+ wire \u_riscv_top.core0_dmem_addr[5] ;
+ wire \u_riscv_top.core0_dmem_addr[6] ;
+ wire \u_riscv_top.core0_dmem_addr[7] ;
+ wire \u_riscv_top.core0_dmem_addr[8] ;
+ wire \u_riscv_top.core0_dmem_addr[9] ;
+ wire \u_riscv_top.core0_dmem_cmd ;
+ wire \u_riscv_top.core0_dmem_rdata[0] ;
+ wire \u_riscv_top.core0_dmem_rdata[10] ;
+ wire \u_riscv_top.core0_dmem_rdata[11] ;
+ wire \u_riscv_top.core0_dmem_rdata[12] ;
+ wire \u_riscv_top.core0_dmem_rdata[13] ;
+ wire \u_riscv_top.core0_dmem_rdata[14] ;
+ wire \u_riscv_top.core0_dmem_rdata[15] ;
+ wire \u_riscv_top.core0_dmem_rdata[16] ;
+ wire \u_riscv_top.core0_dmem_rdata[17] ;
+ wire \u_riscv_top.core0_dmem_rdata[18] ;
+ wire \u_riscv_top.core0_dmem_rdata[19] ;
+ wire \u_riscv_top.core0_dmem_rdata[1] ;
+ wire \u_riscv_top.core0_dmem_rdata[20] ;
+ wire \u_riscv_top.core0_dmem_rdata[21] ;
+ wire \u_riscv_top.core0_dmem_rdata[22] ;
+ wire \u_riscv_top.core0_dmem_rdata[23] ;
+ wire \u_riscv_top.core0_dmem_rdata[24] ;
+ wire \u_riscv_top.core0_dmem_rdata[25] ;
+ wire \u_riscv_top.core0_dmem_rdata[26] ;
+ wire \u_riscv_top.core0_dmem_rdata[27] ;
+ wire \u_riscv_top.core0_dmem_rdata[28] ;
+ wire \u_riscv_top.core0_dmem_rdata[29] ;
+ wire \u_riscv_top.core0_dmem_rdata[2] ;
+ wire \u_riscv_top.core0_dmem_rdata[30] ;
+ wire \u_riscv_top.core0_dmem_rdata[31] ;
+ wire \u_riscv_top.core0_dmem_rdata[3] ;
+ wire \u_riscv_top.core0_dmem_rdata[4] ;
+ wire \u_riscv_top.core0_dmem_rdata[5] ;
+ wire \u_riscv_top.core0_dmem_rdata[6] ;
+ wire \u_riscv_top.core0_dmem_rdata[7] ;
+ wire \u_riscv_top.core0_dmem_rdata[8] ;
+ wire \u_riscv_top.core0_dmem_rdata[9] ;
+ wire \u_riscv_top.core0_dmem_req ;
+ wire \u_riscv_top.core0_dmem_req_ack ;
+ wire \u_riscv_top.core0_dmem_resp[0] ;
+ wire \u_riscv_top.core0_dmem_resp[1] ;
+ wire \u_riscv_top.core0_dmem_wdata[0] ;
+ wire \u_riscv_top.core0_dmem_wdata[10] ;
+ wire \u_riscv_top.core0_dmem_wdata[11] ;
+ wire \u_riscv_top.core0_dmem_wdata[12] ;
+ wire \u_riscv_top.core0_dmem_wdata[13] ;
+ wire \u_riscv_top.core0_dmem_wdata[14] ;
+ wire \u_riscv_top.core0_dmem_wdata[15] ;
+ wire \u_riscv_top.core0_dmem_wdata[16] ;
+ wire \u_riscv_top.core0_dmem_wdata[17] ;
+ wire \u_riscv_top.core0_dmem_wdata[18] ;
+ wire \u_riscv_top.core0_dmem_wdata[19] ;
+ wire \u_riscv_top.core0_dmem_wdata[1] ;
+ wire \u_riscv_top.core0_dmem_wdata[20] ;
+ wire \u_riscv_top.core0_dmem_wdata[21] ;
+ wire \u_riscv_top.core0_dmem_wdata[22] ;
+ wire \u_riscv_top.core0_dmem_wdata[23] ;
+ wire \u_riscv_top.core0_dmem_wdata[24] ;
+ wire \u_riscv_top.core0_dmem_wdata[25] ;
+ wire \u_riscv_top.core0_dmem_wdata[26] ;
+ wire \u_riscv_top.core0_dmem_wdata[27] ;
+ wire \u_riscv_top.core0_dmem_wdata[28] ;
+ wire \u_riscv_top.core0_dmem_wdata[29] ;
+ wire \u_riscv_top.core0_dmem_wdata[2] ;
+ wire \u_riscv_top.core0_dmem_wdata[30] ;
+ wire \u_riscv_top.core0_dmem_wdata[31] ;
+ wire \u_riscv_top.core0_dmem_wdata[3] ;
+ wire \u_riscv_top.core0_dmem_wdata[4] ;
+ wire \u_riscv_top.core0_dmem_wdata[5] ;
+ wire \u_riscv_top.core0_dmem_wdata[6] ;
+ wire \u_riscv_top.core0_dmem_wdata[7] ;
+ wire \u_riscv_top.core0_dmem_wdata[8] ;
+ wire \u_riscv_top.core0_dmem_wdata[9] ;
+ wire \u_riscv_top.core0_dmem_width[0] ;
+ wire \u_riscv_top.core0_dmem_width[1] ;
+ wire \u_riscv_top.core0_imem_addr[0] ;
+ wire \u_riscv_top.core0_imem_addr[10] ;
+ wire \u_riscv_top.core0_imem_addr[11] ;
+ wire \u_riscv_top.core0_imem_addr[12] ;
+ wire \u_riscv_top.core0_imem_addr[13] ;
+ wire \u_riscv_top.core0_imem_addr[14] ;
+ wire \u_riscv_top.core0_imem_addr[15] ;
+ wire \u_riscv_top.core0_imem_addr[16] ;
+ wire \u_riscv_top.core0_imem_addr[17] ;
+ wire \u_riscv_top.core0_imem_addr[18] ;
+ wire \u_riscv_top.core0_imem_addr[19] ;
+ wire \u_riscv_top.core0_imem_addr[1] ;
+ wire \u_riscv_top.core0_imem_addr[20] ;
+ wire \u_riscv_top.core0_imem_addr[21] ;
+ wire \u_riscv_top.core0_imem_addr[22] ;
+ wire \u_riscv_top.core0_imem_addr[23] ;
+ wire \u_riscv_top.core0_imem_addr[24] ;
+ wire \u_riscv_top.core0_imem_addr[25] ;
+ wire \u_riscv_top.core0_imem_addr[26] ;
+ wire \u_riscv_top.core0_imem_addr[27] ;
+ wire \u_riscv_top.core0_imem_addr[28] ;
+ wire \u_riscv_top.core0_imem_addr[29] ;
+ wire \u_riscv_top.core0_imem_addr[2] ;
+ wire \u_riscv_top.core0_imem_addr[30] ;
+ wire \u_riscv_top.core0_imem_addr[31] ;
+ wire \u_riscv_top.core0_imem_addr[3] ;
+ wire \u_riscv_top.core0_imem_addr[4] ;
+ wire \u_riscv_top.core0_imem_addr[5] ;
+ wire \u_riscv_top.core0_imem_addr[6] ;
+ wire \u_riscv_top.core0_imem_addr[7] ;
+ wire \u_riscv_top.core0_imem_addr[8] ;
+ wire \u_riscv_top.core0_imem_addr[9] ;
+ wire \u_riscv_top.core0_imem_bl[0] ;
+ wire \u_riscv_top.core0_imem_bl[1] ;
+ wire \u_riscv_top.core0_imem_bl[2] ;
+ wire \u_riscv_top.core0_imem_cmd ;
+ wire \u_riscv_top.core0_imem_rdata[0] ;
+ wire \u_riscv_top.core0_imem_rdata[10] ;
+ wire \u_riscv_top.core0_imem_rdata[11] ;
+ wire \u_riscv_top.core0_imem_rdata[12] ;
+ wire \u_riscv_top.core0_imem_rdata[13] ;
+ wire \u_riscv_top.core0_imem_rdata[14] ;
+ wire \u_riscv_top.core0_imem_rdata[15] ;
+ wire \u_riscv_top.core0_imem_rdata[16] ;
+ wire \u_riscv_top.core0_imem_rdata[17] ;
+ wire \u_riscv_top.core0_imem_rdata[18] ;
+ wire \u_riscv_top.core0_imem_rdata[19] ;
+ wire \u_riscv_top.core0_imem_rdata[1] ;
+ wire \u_riscv_top.core0_imem_rdata[20] ;
+ wire \u_riscv_top.core0_imem_rdata[21] ;
+ wire \u_riscv_top.core0_imem_rdata[22] ;
+ wire \u_riscv_top.core0_imem_rdata[23] ;
+ wire \u_riscv_top.core0_imem_rdata[24] ;
+ wire \u_riscv_top.core0_imem_rdata[25] ;
+ wire \u_riscv_top.core0_imem_rdata[26] ;
+ wire \u_riscv_top.core0_imem_rdata[27] ;
+ wire \u_riscv_top.core0_imem_rdata[28] ;
+ wire \u_riscv_top.core0_imem_rdata[29] ;
+ wire \u_riscv_top.core0_imem_rdata[2] ;
+ wire \u_riscv_top.core0_imem_rdata[30] ;
+ wire \u_riscv_top.core0_imem_rdata[31] ;
+ wire \u_riscv_top.core0_imem_rdata[3] ;
+ wire \u_riscv_top.core0_imem_rdata[4] ;
+ wire \u_riscv_top.core0_imem_rdata[5] ;
+ wire \u_riscv_top.core0_imem_rdata[6] ;
+ wire \u_riscv_top.core0_imem_rdata[7] ;
+ wire \u_riscv_top.core0_imem_rdata[8] ;
+ wire \u_riscv_top.core0_imem_rdata[9] ;
+ wire \u_riscv_top.core0_imem_req ;
+ wire \u_riscv_top.core0_imem_req_ack ;
+ wire \u_riscv_top.core0_imem_resp[0] ;
+ wire \u_riscv_top.core0_imem_resp[1] ;
+ wire \u_riscv_top.core0_irq_lines[0] ;
+ wire \u_riscv_top.core0_irq_lines[10] ;
+ wire \u_riscv_top.core0_irq_lines[11] ;
+ wire \u_riscv_top.core0_irq_lines[12] ;
+ wire \u_riscv_top.core0_irq_lines[13] ;
+ wire \u_riscv_top.core0_irq_lines[14] ;
+ wire \u_riscv_top.core0_irq_lines[15] ;
+ wire \u_riscv_top.core0_irq_lines[16] ;
+ wire \u_riscv_top.core0_irq_lines[17] ;
+ wire \u_riscv_top.core0_irq_lines[18] ;
+ wire \u_riscv_top.core0_irq_lines[19] ;
+ wire \u_riscv_top.core0_irq_lines[1] ;
+ wire \u_riscv_top.core0_irq_lines[20] ;
+ wire \u_riscv_top.core0_irq_lines[21] ;
+ wire \u_riscv_top.core0_irq_lines[22] ;
+ wire \u_riscv_top.core0_irq_lines[23] ;
+ wire \u_riscv_top.core0_irq_lines[24] ;
+ wire \u_riscv_top.core0_irq_lines[25] ;
+ wire \u_riscv_top.core0_irq_lines[26] ;
+ wire \u_riscv_top.core0_irq_lines[27] ;
+ wire \u_riscv_top.core0_irq_lines[28] ;
+ wire \u_riscv_top.core0_irq_lines[29] ;
+ wire \u_riscv_top.core0_irq_lines[2] ;
+ wire \u_riscv_top.core0_irq_lines[30] ;
+ wire \u_riscv_top.core0_irq_lines[31] ;
+ wire \u_riscv_top.core0_irq_lines[3] ;
+ wire \u_riscv_top.core0_irq_lines[4] ;
+ wire \u_riscv_top.core0_irq_lines[5] ;
+ wire \u_riscv_top.core0_irq_lines[6] ;
+ wire \u_riscv_top.core0_irq_lines[7] ;
+ wire \u_riscv_top.core0_irq_lines[8] ;
+ wire \u_riscv_top.core0_irq_lines[9] ;
+ wire \u_riscv_top.core0_soft_irq ;
+ wire \u_riscv_top.core0_timer_irq ;
+ wire \u_riscv_top.core0_timer_val[0] ;
+ wire \u_riscv_top.core0_timer_val[10] ;
+ wire \u_riscv_top.core0_timer_val[11] ;
+ wire \u_riscv_top.core0_timer_val[12] ;
+ wire \u_riscv_top.core0_timer_val[13] ;
+ wire \u_riscv_top.core0_timer_val[14] ;
+ wire \u_riscv_top.core0_timer_val[15] ;
+ wire \u_riscv_top.core0_timer_val[16] ;
+ wire \u_riscv_top.core0_timer_val[17] ;
+ wire \u_riscv_top.core0_timer_val[18] ;
+ wire \u_riscv_top.core0_timer_val[19] ;
+ wire \u_riscv_top.core0_timer_val[1] ;
+ wire \u_riscv_top.core0_timer_val[20] ;
+ wire \u_riscv_top.core0_timer_val[21] ;
+ wire \u_riscv_top.core0_timer_val[22] ;
+ wire \u_riscv_top.core0_timer_val[23] ;
+ wire \u_riscv_top.core0_timer_val[24] ;
+ wire \u_riscv_top.core0_timer_val[25] ;
+ wire \u_riscv_top.core0_timer_val[26] ;
+ wire \u_riscv_top.core0_timer_val[27] ;
+ wire \u_riscv_top.core0_timer_val[28] ;
+ wire \u_riscv_top.core0_timer_val[29] ;
+ wire \u_riscv_top.core0_timer_val[2] ;
+ wire \u_riscv_top.core0_timer_val[30] ;
+ wire \u_riscv_top.core0_timer_val[31] ;
+ wire \u_riscv_top.core0_timer_val[32] ;
+ wire \u_riscv_top.core0_timer_val[33] ;
+ wire \u_riscv_top.core0_timer_val[34] ;
+ wire \u_riscv_top.core0_timer_val[35] ;
+ wire \u_riscv_top.core0_timer_val[36] ;
+ wire \u_riscv_top.core0_timer_val[37] ;
+ wire \u_riscv_top.core0_timer_val[38] ;
+ wire \u_riscv_top.core0_timer_val[39] ;
+ wire \u_riscv_top.core0_timer_val[3] ;
+ wire \u_riscv_top.core0_timer_val[40] ;
+ wire \u_riscv_top.core0_timer_val[41] ;
+ wire \u_riscv_top.core0_timer_val[42] ;
+ wire \u_riscv_top.core0_timer_val[43] ;
+ wire \u_riscv_top.core0_timer_val[44] ;
+ wire \u_riscv_top.core0_timer_val[45] ;
+ wire \u_riscv_top.core0_timer_val[46] ;
+ wire \u_riscv_top.core0_timer_val[47] ;
+ wire \u_riscv_top.core0_timer_val[48] ;
+ wire \u_riscv_top.core0_timer_val[49] ;
+ wire \u_riscv_top.core0_timer_val[4] ;
+ wire \u_riscv_top.core0_timer_val[50] ;
+ wire \u_riscv_top.core0_timer_val[51] ;
+ wire \u_riscv_top.core0_timer_val[52] ;
+ wire \u_riscv_top.core0_timer_val[53] ;
+ wire \u_riscv_top.core0_timer_val[54] ;
+ wire \u_riscv_top.core0_timer_val[55] ;
+ wire \u_riscv_top.core0_timer_val[56] ;
+ wire \u_riscv_top.core0_timer_val[57] ;
+ wire \u_riscv_top.core0_timer_val[58] ;
+ wire \u_riscv_top.core0_timer_val[59] ;
+ wire \u_riscv_top.core0_timer_val[5] ;
+ wire \u_riscv_top.core0_timer_val[60] ;
+ wire \u_riscv_top.core0_timer_val[61] ;
+ wire \u_riscv_top.core0_timer_val[62] ;
+ wire \u_riscv_top.core0_timer_val[63] ;
+ wire \u_riscv_top.core0_timer_val[6] ;
+ wire \u_riscv_top.core0_timer_val[7] ;
+ wire \u_riscv_top.core0_timer_val[8] ;
+ wire \u_riscv_top.core0_timer_val[9] ;
+ wire \u_riscv_top.core0_uid[0] ;
+ wire \u_riscv_top.core0_uid[1] ;
+ wire \u_riscv_top.core1_clk ;
+ wire \u_riscv_top.core1_debug[0] ;
+ wire \u_riscv_top.core1_debug[10] ;
+ wire \u_riscv_top.core1_debug[11] ;
+ wire \u_riscv_top.core1_debug[12] ;
+ wire \u_riscv_top.core1_debug[13] ;
+ wire \u_riscv_top.core1_debug[14] ;
+ wire \u_riscv_top.core1_debug[15] ;
+ wire \u_riscv_top.core1_debug[16] ;
+ wire \u_riscv_top.core1_debug[17] ;
+ wire \u_riscv_top.core1_debug[18] ;
+ wire \u_riscv_top.core1_debug[19] ;
+ wire \u_riscv_top.core1_debug[1] ;
+ wire \u_riscv_top.core1_debug[20] ;
+ wire \u_riscv_top.core1_debug[21] ;
+ wire \u_riscv_top.core1_debug[22] ;
+ wire \u_riscv_top.core1_debug[23] ;
+ wire \u_riscv_top.core1_debug[24] ;
+ wire \u_riscv_top.core1_debug[25] ;
+ wire \u_riscv_top.core1_debug[26] ;
+ wire \u_riscv_top.core1_debug[27] ;
+ wire \u_riscv_top.core1_debug[28] ;
+ wire \u_riscv_top.core1_debug[29] ;
+ wire \u_riscv_top.core1_debug[2] ;
+ wire \u_riscv_top.core1_debug[30] ;
+ wire \u_riscv_top.core1_debug[31] ;
+ wire \u_riscv_top.core1_debug[32] ;
+ wire \u_riscv_top.core1_debug[33] ;
+ wire \u_riscv_top.core1_debug[34] ;
+ wire \u_riscv_top.core1_debug[35] ;
+ wire \u_riscv_top.core1_debug[36] ;
+ wire \u_riscv_top.core1_debug[37] ;
+ wire \u_riscv_top.core1_debug[38] ;
+ wire \u_riscv_top.core1_debug[39] ;
+ wire \u_riscv_top.core1_debug[3] ;
+ wire \u_riscv_top.core1_debug[40] ;
+ wire \u_riscv_top.core1_debug[41] ;
+ wire \u_riscv_top.core1_debug[42] ;
+ wire \u_riscv_top.core1_debug[43] ;
+ wire \u_riscv_top.core1_debug[44] ;
+ wire \u_riscv_top.core1_debug[45] ;
+ wire \u_riscv_top.core1_debug[46] ;
+ wire \u_riscv_top.core1_debug[47] ;
+ wire \u_riscv_top.core1_debug[48] ;
+ wire \u_riscv_top.core1_debug[4] ;
+ wire \u_riscv_top.core1_debug[5] ;
+ wire \u_riscv_top.core1_debug[6] ;
+ wire \u_riscv_top.core1_debug[7] ;
+ wire \u_riscv_top.core1_debug[8] ;
+ wire \u_riscv_top.core1_debug[9] ;
+ wire \u_riscv_top.core1_dmem_addr[0] ;
+ wire \u_riscv_top.core1_dmem_addr[10] ;
+ wire \u_riscv_top.core1_dmem_addr[11] ;
+ wire \u_riscv_top.core1_dmem_addr[12] ;
+ wire \u_riscv_top.core1_dmem_addr[13] ;
+ wire \u_riscv_top.core1_dmem_addr[14] ;
+ wire \u_riscv_top.core1_dmem_addr[15] ;
+ wire \u_riscv_top.core1_dmem_addr[16] ;
+ wire \u_riscv_top.core1_dmem_addr[17] ;
+ wire \u_riscv_top.core1_dmem_addr[18] ;
+ wire \u_riscv_top.core1_dmem_addr[19] ;
+ wire \u_riscv_top.core1_dmem_addr[1] ;
+ wire \u_riscv_top.core1_dmem_addr[20] ;
+ wire \u_riscv_top.core1_dmem_addr[21] ;
+ wire \u_riscv_top.core1_dmem_addr[22] ;
+ wire \u_riscv_top.core1_dmem_addr[23] ;
+ wire \u_riscv_top.core1_dmem_addr[24] ;
+ wire \u_riscv_top.core1_dmem_addr[25] ;
+ wire \u_riscv_top.core1_dmem_addr[26] ;
+ wire \u_riscv_top.core1_dmem_addr[27] ;
+ wire \u_riscv_top.core1_dmem_addr[28] ;
+ wire \u_riscv_top.core1_dmem_addr[29] ;
+ wire \u_riscv_top.core1_dmem_addr[2] ;
+ wire \u_riscv_top.core1_dmem_addr[30] ;
+ wire \u_riscv_top.core1_dmem_addr[31] ;
+ wire \u_riscv_top.core1_dmem_addr[3] ;
+ wire \u_riscv_top.core1_dmem_addr[4] ;
+ wire \u_riscv_top.core1_dmem_addr[5] ;
+ wire \u_riscv_top.core1_dmem_addr[6] ;
+ wire \u_riscv_top.core1_dmem_addr[7] ;
+ wire \u_riscv_top.core1_dmem_addr[8] ;
+ wire \u_riscv_top.core1_dmem_addr[9] ;
+ wire \u_riscv_top.core1_dmem_cmd ;
+ wire \u_riscv_top.core1_dmem_rdata[0] ;
+ wire \u_riscv_top.core1_dmem_rdata[10] ;
+ wire \u_riscv_top.core1_dmem_rdata[11] ;
+ wire \u_riscv_top.core1_dmem_rdata[12] ;
+ wire \u_riscv_top.core1_dmem_rdata[13] ;
+ wire \u_riscv_top.core1_dmem_rdata[14] ;
+ wire \u_riscv_top.core1_dmem_rdata[15] ;
+ wire \u_riscv_top.core1_dmem_rdata[16] ;
+ wire \u_riscv_top.core1_dmem_rdata[17] ;
+ wire \u_riscv_top.core1_dmem_rdata[18] ;
+ wire \u_riscv_top.core1_dmem_rdata[19] ;
+ wire \u_riscv_top.core1_dmem_rdata[1] ;
+ wire \u_riscv_top.core1_dmem_rdata[20] ;
+ wire \u_riscv_top.core1_dmem_rdata[21] ;
+ wire \u_riscv_top.core1_dmem_rdata[22] ;
+ wire \u_riscv_top.core1_dmem_rdata[23] ;
+ wire \u_riscv_top.core1_dmem_rdata[24] ;
+ wire \u_riscv_top.core1_dmem_rdata[25] ;
+ wire \u_riscv_top.core1_dmem_rdata[26] ;
+ wire \u_riscv_top.core1_dmem_rdata[27] ;
+ wire \u_riscv_top.core1_dmem_rdata[28] ;
+ wire \u_riscv_top.core1_dmem_rdata[29] ;
+ wire \u_riscv_top.core1_dmem_rdata[2] ;
+ wire \u_riscv_top.core1_dmem_rdata[30] ;
+ wire \u_riscv_top.core1_dmem_rdata[31] ;
+ wire \u_riscv_top.core1_dmem_rdata[3] ;
+ wire \u_riscv_top.core1_dmem_rdata[4] ;
+ wire \u_riscv_top.core1_dmem_rdata[5] ;
+ wire \u_riscv_top.core1_dmem_rdata[6] ;
+ wire \u_riscv_top.core1_dmem_rdata[7] ;
+ wire \u_riscv_top.core1_dmem_rdata[8] ;
+ wire \u_riscv_top.core1_dmem_rdata[9] ;
+ wire \u_riscv_top.core1_dmem_req ;
+ wire \u_riscv_top.core1_dmem_req_ack ;
+ wire \u_riscv_top.core1_dmem_resp[0] ;
+ wire \u_riscv_top.core1_dmem_resp[1] ;
+ wire \u_riscv_top.core1_dmem_wdata[0] ;
+ wire \u_riscv_top.core1_dmem_wdata[10] ;
+ wire \u_riscv_top.core1_dmem_wdata[11] ;
+ wire \u_riscv_top.core1_dmem_wdata[12] ;
+ wire \u_riscv_top.core1_dmem_wdata[13] ;
+ wire \u_riscv_top.core1_dmem_wdata[14] ;
+ wire \u_riscv_top.core1_dmem_wdata[15] ;
+ wire \u_riscv_top.core1_dmem_wdata[16] ;
+ wire \u_riscv_top.core1_dmem_wdata[17] ;
+ wire \u_riscv_top.core1_dmem_wdata[18] ;
+ wire \u_riscv_top.core1_dmem_wdata[19] ;
+ wire \u_riscv_top.core1_dmem_wdata[1] ;
+ wire \u_riscv_top.core1_dmem_wdata[20] ;
+ wire \u_riscv_top.core1_dmem_wdata[21] ;
+ wire \u_riscv_top.core1_dmem_wdata[22] ;
+ wire \u_riscv_top.core1_dmem_wdata[23] ;
+ wire \u_riscv_top.core1_dmem_wdata[24] ;
+ wire \u_riscv_top.core1_dmem_wdata[25] ;
+ wire \u_riscv_top.core1_dmem_wdata[26] ;
+ wire \u_riscv_top.core1_dmem_wdata[27] ;
+ wire \u_riscv_top.core1_dmem_wdata[28] ;
+ wire \u_riscv_top.core1_dmem_wdata[29] ;
+ wire \u_riscv_top.core1_dmem_wdata[2] ;
+ wire \u_riscv_top.core1_dmem_wdata[30] ;
+ wire \u_riscv_top.core1_dmem_wdata[31] ;
+ wire \u_riscv_top.core1_dmem_wdata[3] ;
+ wire \u_riscv_top.core1_dmem_wdata[4] ;
+ wire \u_riscv_top.core1_dmem_wdata[5] ;
+ wire \u_riscv_top.core1_dmem_wdata[6] ;
+ wire \u_riscv_top.core1_dmem_wdata[7] ;
+ wire \u_riscv_top.core1_dmem_wdata[8] ;
+ wire \u_riscv_top.core1_dmem_wdata[9] ;
+ wire \u_riscv_top.core1_dmem_width[0] ;
+ wire \u_riscv_top.core1_dmem_width[1] ;
+ wire \u_riscv_top.core1_imem_addr[0] ;
+ wire \u_riscv_top.core1_imem_addr[10] ;
+ wire \u_riscv_top.core1_imem_addr[11] ;
+ wire \u_riscv_top.core1_imem_addr[12] ;
+ wire \u_riscv_top.core1_imem_addr[13] ;
+ wire \u_riscv_top.core1_imem_addr[14] ;
+ wire \u_riscv_top.core1_imem_addr[15] ;
+ wire \u_riscv_top.core1_imem_addr[16] ;
+ wire \u_riscv_top.core1_imem_addr[17] ;
+ wire \u_riscv_top.core1_imem_addr[18] ;
+ wire \u_riscv_top.core1_imem_addr[19] ;
+ wire \u_riscv_top.core1_imem_addr[1] ;
+ wire \u_riscv_top.core1_imem_addr[20] ;
+ wire \u_riscv_top.core1_imem_addr[21] ;
+ wire \u_riscv_top.core1_imem_addr[22] ;
+ wire \u_riscv_top.core1_imem_addr[23] ;
+ wire \u_riscv_top.core1_imem_addr[24] ;
+ wire \u_riscv_top.core1_imem_addr[25] ;
+ wire \u_riscv_top.core1_imem_addr[26] ;
+ wire \u_riscv_top.core1_imem_addr[27] ;
+ wire \u_riscv_top.core1_imem_addr[28] ;
+ wire \u_riscv_top.core1_imem_addr[29] ;
+ wire \u_riscv_top.core1_imem_addr[2] ;
+ wire \u_riscv_top.core1_imem_addr[30] ;
+ wire \u_riscv_top.core1_imem_addr[31] ;
+ wire \u_riscv_top.core1_imem_addr[3] ;
+ wire \u_riscv_top.core1_imem_addr[4] ;
+ wire \u_riscv_top.core1_imem_addr[5] ;
+ wire \u_riscv_top.core1_imem_addr[6] ;
+ wire \u_riscv_top.core1_imem_addr[7] ;
+ wire \u_riscv_top.core1_imem_addr[8] ;
+ wire \u_riscv_top.core1_imem_addr[9] ;
+ wire \u_riscv_top.core1_imem_bl[0] ;
+ wire \u_riscv_top.core1_imem_bl[1] ;
+ wire \u_riscv_top.core1_imem_bl[2] ;
+ wire \u_riscv_top.core1_imem_cmd ;
+ wire \u_riscv_top.core1_imem_rdata[0] ;
+ wire \u_riscv_top.core1_imem_rdata[10] ;
+ wire \u_riscv_top.core1_imem_rdata[11] ;
+ wire \u_riscv_top.core1_imem_rdata[12] ;
+ wire \u_riscv_top.core1_imem_rdata[13] ;
+ wire \u_riscv_top.core1_imem_rdata[14] ;
+ wire \u_riscv_top.core1_imem_rdata[15] ;
+ wire \u_riscv_top.core1_imem_rdata[16] ;
+ wire \u_riscv_top.core1_imem_rdata[17] ;
+ wire \u_riscv_top.core1_imem_rdata[18] ;
+ wire \u_riscv_top.core1_imem_rdata[19] ;
+ wire \u_riscv_top.core1_imem_rdata[1] ;
+ wire \u_riscv_top.core1_imem_rdata[20] ;
+ wire \u_riscv_top.core1_imem_rdata[21] ;
+ wire \u_riscv_top.core1_imem_rdata[22] ;
+ wire \u_riscv_top.core1_imem_rdata[23] ;
+ wire \u_riscv_top.core1_imem_rdata[24] ;
+ wire \u_riscv_top.core1_imem_rdata[25] ;
+ wire \u_riscv_top.core1_imem_rdata[26] ;
+ wire \u_riscv_top.core1_imem_rdata[27] ;
+ wire \u_riscv_top.core1_imem_rdata[28] ;
+ wire \u_riscv_top.core1_imem_rdata[29] ;
+ wire \u_riscv_top.core1_imem_rdata[2] ;
+ wire \u_riscv_top.core1_imem_rdata[30] ;
+ wire \u_riscv_top.core1_imem_rdata[31] ;
+ wire \u_riscv_top.core1_imem_rdata[3] ;
+ wire \u_riscv_top.core1_imem_rdata[4] ;
+ wire \u_riscv_top.core1_imem_rdata[5] ;
+ wire \u_riscv_top.core1_imem_rdata[6] ;
+ wire \u_riscv_top.core1_imem_rdata[7] ;
+ wire \u_riscv_top.core1_imem_rdata[8] ;
+ wire \u_riscv_top.core1_imem_rdata[9] ;
+ wire \u_riscv_top.core1_imem_req ;
+ wire \u_riscv_top.core1_imem_req_ack ;
+ wire \u_riscv_top.core1_imem_resp[0] ;
+ wire \u_riscv_top.core1_imem_resp[1] ;
+ wire \u_riscv_top.core1_irq_lines[0] ;
+ wire \u_riscv_top.core1_irq_lines[10] ;
+ wire \u_riscv_top.core1_irq_lines[11] ;
+ wire \u_riscv_top.core1_irq_lines[12] ;
+ wire \u_riscv_top.core1_irq_lines[13] ;
+ wire \u_riscv_top.core1_irq_lines[14] ;
+ wire \u_riscv_top.core1_irq_lines[15] ;
+ wire \u_riscv_top.core1_irq_lines[16] ;
+ wire \u_riscv_top.core1_irq_lines[17] ;
+ wire \u_riscv_top.core1_irq_lines[18] ;
+ wire \u_riscv_top.core1_irq_lines[19] ;
+ wire \u_riscv_top.core1_irq_lines[1] ;
+ wire \u_riscv_top.core1_irq_lines[20] ;
+ wire \u_riscv_top.core1_irq_lines[21] ;
+ wire \u_riscv_top.core1_irq_lines[22] ;
+ wire \u_riscv_top.core1_irq_lines[23] ;
+ wire \u_riscv_top.core1_irq_lines[24] ;
+ wire \u_riscv_top.core1_irq_lines[25] ;
+ wire \u_riscv_top.core1_irq_lines[26] ;
+ wire \u_riscv_top.core1_irq_lines[27] ;
+ wire \u_riscv_top.core1_irq_lines[28] ;
+ wire \u_riscv_top.core1_irq_lines[29] ;
+ wire \u_riscv_top.core1_irq_lines[2] ;
+ wire \u_riscv_top.core1_irq_lines[30] ;
+ wire \u_riscv_top.core1_irq_lines[31] ;
+ wire \u_riscv_top.core1_irq_lines[3] ;
+ wire \u_riscv_top.core1_irq_lines[4] ;
+ wire \u_riscv_top.core1_irq_lines[5] ;
+ wire \u_riscv_top.core1_irq_lines[6] ;
+ wire \u_riscv_top.core1_irq_lines[7] ;
+ wire \u_riscv_top.core1_irq_lines[8] ;
+ wire \u_riscv_top.core1_irq_lines[9] ;
+ wire \u_riscv_top.core1_soft_irq ;
+ wire \u_riscv_top.core1_timer_irq ;
+ wire \u_riscv_top.core1_timer_val[0] ;
+ wire \u_riscv_top.core1_timer_val[10] ;
+ wire \u_riscv_top.core1_timer_val[11] ;
+ wire \u_riscv_top.core1_timer_val[12] ;
+ wire \u_riscv_top.core1_timer_val[13] ;
+ wire \u_riscv_top.core1_timer_val[14] ;
+ wire \u_riscv_top.core1_timer_val[15] ;
+ wire \u_riscv_top.core1_timer_val[16] ;
+ wire \u_riscv_top.core1_timer_val[17] ;
+ wire \u_riscv_top.core1_timer_val[18] ;
+ wire \u_riscv_top.core1_timer_val[19] ;
+ wire \u_riscv_top.core1_timer_val[1] ;
+ wire \u_riscv_top.core1_timer_val[20] ;
+ wire \u_riscv_top.core1_timer_val[21] ;
+ wire \u_riscv_top.core1_timer_val[22] ;
+ wire \u_riscv_top.core1_timer_val[23] ;
+ wire \u_riscv_top.core1_timer_val[24] ;
+ wire \u_riscv_top.core1_timer_val[25] ;
+ wire \u_riscv_top.core1_timer_val[26] ;
+ wire \u_riscv_top.core1_timer_val[27] ;
+ wire \u_riscv_top.core1_timer_val[28] ;
+ wire \u_riscv_top.core1_timer_val[29] ;
+ wire \u_riscv_top.core1_timer_val[2] ;
+ wire \u_riscv_top.core1_timer_val[30] ;
+ wire \u_riscv_top.core1_timer_val[31] ;
+ wire \u_riscv_top.core1_timer_val[32] ;
+ wire \u_riscv_top.core1_timer_val[33] ;
+ wire \u_riscv_top.core1_timer_val[34] ;
+ wire \u_riscv_top.core1_timer_val[35] ;
+ wire \u_riscv_top.core1_timer_val[36] ;
+ wire \u_riscv_top.core1_timer_val[37] ;
+ wire \u_riscv_top.core1_timer_val[38] ;
+ wire \u_riscv_top.core1_timer_val[39] ;
+ wire \u_riscv_top.core1_timer_val[3] ;
+ wire \u_riscv_top.core1_timer_val[40] ;
+ wire \u_riscv_top.core1_timer_val[41] ;
+ wire \u_riscv_top.core1_timer_val[42] ;
+ wire \u_riscv_top.core1_timer_val[43] ;
+ wire \u_riscv_top.core1_timer_val[44] ;
+ wire \u_riscv_top.core1_timer_val[45] ;
+ wire \u_riscv_top.core1_timer_val[46] ;
+ wire \u_riscv_top.core1_timer_val[47] ;
+ wire \u_riscv_top.core1_timer_val[48] ;
+ wire \u_riscv_top.core1_timer_val[49] ;
+ wire \u_riscv_top.core1_timer_val[4] ;
+ wire \u_riscv_top.core1_timer_val[50] ;
+ wire \u_riscv_top.core1_timer_val[51] ;
+ wire \u_riscv_top.core1_timer_val[52] ;
+ wire \u_riscv_top.core1_timer_val[53] ;
+ wire \u_riscv_top.core1_timer_val[54] ;
+ wire \u_riscv_top.core1_timer_val[55] ;
+ wire \u_riscv_top.core1_timer_val[56] ;
+ wire \u_riscv_top.core1_timer_val[57] ;
+ wire \u_riscv_top.core1_timer_val[58] ;
+ wire \u_riscv_top.core1_timer_val[59] ;
+ wire \u_riscv_top.core1_timer_val[5] ;
+ wire \u_riscv_top.core1_timer_val[60] ;
+ wire \u_riscv_top.core1_timer_val[61] ;
+ wire \u_riscv_top.core1_timer_val[62] ;
+ wire \u_riscv_top.core1_timer_val[63] ;
+ wire \u_riscv_top.core1_timer_val[6] ;
+ wire \u_riscv_top.core1_timer_val[7] ;
+ wire \u_riscv_top.core1_timer_val[8] ;
+ wire \u_riscv_top.core1_timer_val[9] ;
+ wire \u_riscv_top.core1_uid[0] ;
+ wire \u_riscv_top.core1_uid[1] ;
+ wire \u_riscv_top.core2_clk ;
+ wire \u_riscv_top.core2_debug[0] ;
+ wire \u_riscv_top.core2_debug[10] ;
+ wire \u_riscv_top.core2_debug[11] ;
+ wire \u_riscv_top.core2_debug[12] ;
+ wire \u_riscv_top.core2_debug[13] ;
+ wire \u_riscv_top.core2_debug[14] ;
+ wire \u_riscv_top.core2_debug[15] ;
+ wire \u_riscv_top.core2_debug[16] ;
+ wire \u_riscv_top.core2_debug[17] ;
+ wire \u_riscv_top.core2_debug[18] ;
+ wire \u_riscv_top.core2_debug[19] ;
+ wire \u_riscv_top.core2_debug[1] ;
+ wire \u_riscv_top.core2_debug[20] ;
+ wire \u_riscv_top.core2_debug[21] ;
+ wire \u_riscv_top.core2_debug[22] ;
+ wire \u_riscv_top.core2_debug[23] ;
+ wire \u_riscv_top.core2_debug[24] ;
+ wire \u_riscv_top.core2_debug[25] ;
+ wire \u_riscv_top.core2_debug[26] ;
+ wire \u_riscv_top.core2_debug[27] ;
+ wire \u_riscv_top.core2_debug[28] ;
+ wire \u_riscv_top.core2_debug[29] ;
+ wire \u_riscv_top.core2_debug[2] ;
+ wire \u_riscv_top.core2_debug[30] ;
+ wire \u_riscv_top.core2_debug[31] ;
+ wire \u_riscv_top.core2_debug[32] ;
+ wire \u_riscv_top.core2_debug[33] ;
+ wire \u_riscv_top.core2_debug[34] ;
+ wire \u_riscv_top.core2_debug[35] ;
+ wire \u_riscv_top.core2_debug[36] ;
+ wire \u_riscv_top.core2_debug[37] ;
+ wire \u_riscv_top.core2_debug[38] ;
+ wire \u_riscv_top.core2_debug[39] ;
+ wire \u_riscv_top.core2_debug[3] ;
+ wire \u_riscv_top.core2_debug[40] ;
+ wire \u_riscv_top.core2_debug[41] ;
+ wire \u_riscv_top.core2_debug[42] ;
+ wire \u_riscv_top.core2_debug[43] ;
+ wire \u_riscv_top.core2_debug[44] ;
+ wire \u_riscv_top.core2_debug[45] ;
+ wire \u_riscv_top.core2_debug[46] ;
+ wire \u_riscv_top.core2_debug[47] ;
+ wire \u_riscv_top.core2_debug[48] ;
+ wire \u_riscv_top.core2_debug[4] ;
+ wire \u_riscv_top.core2_debug[5] ;
+ wire \u_riscv_top.core2_debug[6] ;
+ wire \u_riscv_top.core2_debug[7] ;
+ wire \u_riscv_top.core2_debug[8] ;
+ wire \u_riscv_top.core2_debug[9] ;
+ wire \u_riscv_top.core2_dmem_addr[0] ;
+ wire \u_riscv_top.core2_dmem_addr[10] ;
+ wire \u_riscv_top.core2_dmem_addr[11] ;
+ wire \u_riscv_top.core2_dmem_addr[12] ;
+ wire \u_riscv_top.core2_dmem_addr[13] ;
+ wire \u_riscv_top.core2_dmem_addr[14] ;
+ wire \u_riscv_top.core2_dmem_addr[15] ;
+ wire \u_riscv_top.core2_dmem_addr[16] ;
+ wire \u_riscv_top.core2_dmem_addr[17] ;
+ wire \u_riscv_top.core2_dmem_addr[18] ;
+ wire \u_riscv_top.core2_dmem_addr[19] ;
+ wire \u_riscv_top.core2_dmem_addr[1] ;
+ wire \u_riscv_top.core2_dmem_addr[20] ;
+ wire \u_riscv_top.core2_dmem_addr[21] ;
+ wire \u_riscv_top.core2_dmem_addr[22] ;
+ wire \u_riscv_top.core2_dmem_addr[23] ;
+ wire \u_riscv_top.core2_dmem_addr[24] ;
+ wire \u_riscv_top.core2_dmem_addr[25] ;
+ wire \u_riscv_top.core2_dmem_addr[26] ;
+ wire \u_riscv_top.core2_dmem_addr[27] ;
+ wire \u_riscv_top.core2_dmem_addr[28] ;
+ wire \u_riscv_top.core2_dmem_addr[29] ;
+ wire \u_riscv_top.core2_dmem_addr[2] ;
+ wire \u_riscv_top.core2_dmem_addr[30] ;
+ wire \u_riscv_top.core2_dmem_addr[31] ;
+ wire \u_riscv_top.core2_dmem_addr[3] ;
+ wire \u_riscv_top.core2_dmem_addr[4] ;
+ wire \u_riscv_top.core2_dmem_addr[5] ;
+ wire \u_riscv_top.core2_dmem_addr[6] ;
+ wire \u_riscv_top.core2_dmem_addr[7] ;
+ wire \u_riscv_top.core2_dmem_addr[8] ;
+ wire \u_riscv_top.core2_dmem_addr[9] ;
+ wire \u_riscv_top.core2_dmem_cmd ;
+ wire \u_riscv_top.core2_dmem_rdata[0] ;
+ wire \u_riscv_top.core2_dmem_rdata[10] ;
+ wire \u_riscv_top.core2_dmem_rdata[11] ;
+ wire \u_riscv_top.core2_dmem_rdata[12] ;
+ wire \u_riscv_top.core2_dmem_rdata[13] ;
+ wire \u_riscv_top.core2_dmem_rdata[14] ;
+ wire \u_riscv_top.core2_dmem_rdata[15] ;
+ wire \u_riscv_top.core2_dmem_rdata[16] ;
+ wire \u_riscv_top.core2_dmem_rdata[17] ;
+ wire \u_riscv_top.core2_dmem_rdata[18] ;
+ wire \u_riscv_top.core2_dmem_rdata[19] ;
+ wire \u_riscv_top.core2_dmem_rdata[1] ;
+ wire \u_riscv_top.core2_dmem_rdata[20] ;
+ wire \u_riscv_top.core2_dmem_rdata[21] ;
+ wire \u_riscv_top.core2_dmem_rdata[22] ;
+ wire \u_riscv_top.core2_dmem_rdata[23] ;
+ wire \u_riscv_top.core2_dmem_rdata[24] ;
+ wire \u_riscv_top.core2_dmem_rdata[25] ;
+ wire \u_riscv_top.core2_dmem_rdata[26] ;
+ wire \u_riscv_top.core2_dmem_rdata[27] ;
+ wire \u_riscv_top.core2_dmem_rdata[28] ;
+ wire \u_riscv_top.core2_dmem_rdata[29] ;
+ wire \u_riscv_top.core2_dmem_rdata[2] ;
+ wire \u_riscv_top.core2_dmem_rdata[30] ;
+ wire \u_riscv_top.core2_dmem_rdata[31] ;
+ wire \u_riscv_top.core2_dmem_rdata[3] ;
+ wire \u_riscv_top.core2_dmem_rdata[4] ;
+ wire \u_riscv_top.core2_dmem_rdata[5] ;
+ wire \u_riscv_top.core2_dmem_rdata[6] ;
+ wire \u_riscv_top.core2_dmem_rdata[7] ;
+ wire \u_riscv_top.core2_dmem_rdata[8] ;
+ wire \u_riscv_top.core2_dmem_rdata[9] ;
+ wire \u_riscv_top.core2_dmem_req ;
+ wire \u_riscv_top.core2_dmem_req_ack ;
+ wire \u_riscv_top.core2_dmem_resp[0] ;
+ wire \u_riscv_top.core2_dmem_resp[1] ;
+ wire \u_riscv_top.core2_dmem_wdata[0] ;
+ wire \u_riscv_top.core2_dmem_wdata[10] ;
+ wire \u_riscv_top.core2_dmem_wdata[11] ;
+ wire \u_riscv_top.core2_dmem_wdata[12] ;
+ wire \u_riscv_top.core2_dmem_wdata[13] ;
+ wire \u_riscv_top.core2_dmem_wdata[14] ;
+ wire \u_riscv_top.core2_dmem_wdata[15] ;
+ wire \u_riscv_top.core2_dmem_wdata[16] ;
+ wire \u_riscv_top.core2_dmem_wdata[17] ;
+ wire \u_riscv_top.core2_dmem_wdata[18] ;
+ wire \u_riscv_top.core2_dmem_wdata[19] ;
+ wire \u_riscv_top.core2_dmem_wdata[1] ;
+ wire \u_riscv_top.core2_dmem_wdata[20] ;
+ wire \u_riscv_top.core2_dmem_wdata[21] ;
+ wire \u_riscv_top.core2_dmem_wdata[22] ;
+ wire \u_riscv_top.core2_dmem_wdata[23] ;
+ wire \u_riscv_top.core2_dmem_wdata[24] ;
+ wire \u_riscv_top.core2_dmem_wdata[25] ;
+ wire \u_riscv_top.core2_dmem_wdata[26] ;
+ wire \u_riscv_top.core2_dmem_wdata[27] ;
+ wire \u_riscv_top.core2_dmem_wdata[28] ;
+ wire \u_riscv_top.core2_dmem_wdata[29] ;
+ wire \u_riscv_top.core2_dmem_wdata[2] ;
+ wire \u_riscv_top.core2_dmem_wdata[30] ;
+ wire \u_riscv_top.core2_dmem_wdata[31] ;
+ wire \u_riscv_top.core2_dmem_wdata[3] ;
+ wire \u_riscv_top.core2_dmem_wdata[4] ;
+ wire \u_riscv_top.core2_dmem_wdata[5] ;
+ wire \u_riscv_top.core2_dmem_wdata[6] ;
+ wire \u_riscv_top.core2_dmem_wdata[7] ;
+ wire \u_riscv_top.core2_dmem_wdata[8] ;
+ wire \u_riscv_top.core2_dmem_wdata[9] ;
+ wire \u_riscv_top.core2_dmem_width[0] ;
+ wire \u_riscv_top.core2_dmem_width[1] ;
+ wire \u_riscv_top.core2_imem_addr[0] ;
+ wire \u_riscv_top.core2_imem_addr[10] ;
+ wire \u_riscv_top.core2_imem_addr[11] ;
+ wire \u_riscv_top.core2_imem_addr[12] ;
+ wire \u_riscv_top.core2_imem_addr[13] ;
+ wire \u_riscv_top.core2_imem_addr[14] ;
+ wire \u_riscv_top.core2_imem_addr[15] ;
+ wire \u_riscv_top.core2_imem_addr[16] ;
+ wire \u_riscv_top.core2_imem_addr[17] ;
+ wire \u_riscv_top.core2_imem_addr[18] ;
+ wire \u_riscv_top.core2_imem_addr[19] ;
+ wire \u_riscv_top.core2_imem_addr[1] ;
+ wire \u_riscv_top.core2_imem_addr[20] ;
+ wire \u_riscv_top.core2_imem_addr[21] ;
+ wire \u_riscv_top.core2_imem_addr[22] ;
+ wire \u_riscv_top.core2_imem_addr[23] ;
+ wire \u_riscv_top.core2_imem_addr[24] ;
+ wire \u_riscv_top.core2_imem_addr[25] ;
+ wire \u_riscv_top.core2_imem_addr[26] ;
+ wire \u_riscv_top.core2_imem_addr[27] ;
+ wire \u_riscv_top.core2_imem_addr[28] ;
+ wire \u_riscv_top.core2_imem_addr[29] ;
+ wire \u_riscv_top.core2_imem_addr[2] ;
+ wire \u_riscv_top.core2_imem_addr[30] ;
+ wire \u_riscv_top.core2_imem_addr[31] ;
+ wire \u_riscv_top.core2_imem_addr[3] ;
+ wire \u_riscv_top.core2_imem_addr[4] ;
+ wire \u_riscv_top.core2_imem_addr[5] ;
+ wire \u_riscv_top.core2_imem_addr[6] ;
+ wire \u_riscv_top.core2_imem_addr[7] ;
+ wire \u_riscv_top.core2_imem_addr[8] ;
+ wire \u_riscv_top.core2_imem_addr[9] ;
+ wire \u_riscv_top.core2_imem_bl[0] ;
+ wire \u_riscv_top.core2_imem_bl[1] ;
+ wire \u_riscv_top.core2_imem_bl[2] ;
+ wire \u_riscv_top.core2_imem_cmd ;
+ wire \u_riscv_top.core2_imem_rdata[0] ;
+ wire \u_riscv_top.core2_imem_rdata[10] ;
+ wire \u_riscv_top.core2_imem_rdata[11] ;
+ wire \u_riscv_top.core2_imem_rdata[12] ;
+ wire \u_riscv_top.core2_imem_rdata[13] ;
+ wire \u_riscv_top.core2_imem_rdata[14] ;
+ wire \u_riscv_top.core2_imem_rdata[15] ;
+ wire \u_riscv_top.core2_imem_rdata[16] ;
+ wire \u_riscv_top.core2_imem_rdata[17] ;
+ wire \u_riscv_top.core2_imem_rdata[18] ;
+ wire \u_riscv_top.core2_imem_rdata[19] ;
+ wire \u_riscv_top.core2_imem_rdata[1] ;
+ wire \u_riscv_top.core2_imem_rdata[20] ;
+ wire \u_riscv_top.core2_imem_rdata[21] ;
+ wire \u_riscv_top.core2_imem_rdata[22] ;
+ wire \u_riscv_top.core2_imem_rdata[23] ;
+ wire \u_riscv_top.core2_imem_rdata[24] ;
+ wire \u_riscv_top.core2_imem_rdata[25] ;
+ wire \u_riscv_top.core2_imem_rdata[26] ;
+ wire \u_riscv_top.core2_imem_rdata[27] ;
+ wire \u_riscv_top.core2_imem_rdata[28] ;
+ wire \u_riscv_top.core2_imem_rdata[29] ;
+ wire \u_riscv_top.core2_imem_rdata[2] ;
+ wire \u_riscv_top.core2_imem_rdata[30] ;
+ wire \u_riscv_top.core2_imem_rdata[31] ;
+ wire \u_riscv_top.core2_imem_rdata[3] ;
+ wire \u_riscv_top.core2_imem_rdata[4] ;
+ wire \u_riscv_top.core2_imem_rdata[5] ;
+ wire \u_riscv_top.core2_imem_rdata[6] ;
+ wire \u_riscv_top.core2_imem_rdata[7] ;
+ wire \u_riscv_top.core2_imem_rdata[8] ;
+ wire \u_riscv_top.core2_imem_rdata[9] ;
+ wire \u_riscv_top.core2_imem_req ;
+ wire \u_riscv_top.core2_imem_req_ack ;
+ wire \u_riscv_top.core2_imem_resp[0] ;
+ wire \u_riscv_top.core2_imem_resp[1] ;
+ wire \u_riscv_top.core2_irq_lines[0] ;
+ wire \u_riscv_top.core2_irq_lines[10] ;
+ wire \u_riscv_top.core2_irq_lines[11] ;
+ wire \u_riscv_top.core2_irq_lines[12] ;
+ wire \u_riscv_top.core2_irq_lines[13] ;
+ wire \u_riscv_top.core2_irq_lines[14] ;
+ wire \u_riscv_top.core2_irq_lines[15] ;
+ wire \u_riscv_top.core2_irq_lines[16] ;
+ wire \u_riscv_top.core2_irq_lines[17] ;
+ wire \u_riscv_top.core2_irq_lines[18] ;
+ wire \u_riscv_top.core2_irq_lines[19] ;
+ wire \u_riscv_top.core2_irq_lines[1] ;
+ wire \u_riscv_top.core2_irq_lines[20] ;
+ wire \u_riscv_top.core2_irq_lines[21] ;
+ wire \u_riscv_top.core2_irq_lines[22] ;
+ wire \u_riscv_top.core2_irq_lines[23] ;
+ wire \u_riscv_top.core2_irq_lines[24] ;
+ wire \u_riscv_top.core2_irq_lines[25] ;
+ wire \u_riscv_top.core2_irq_lines[26] ;
+ wire \u_riscv_top.core2_irq_lines[27] ;
+ wire \u_riscv_top.core2_irq_lines[28] ;
+ wire \u_riscv_top.core2_irq_lines[29] ;
+ wire \u_riscv_top.core2_irq_lines[2] ;
+ wire \u_riscv_top.core2_irq_lines[30] ;
+ wire \u_riscv_top.core2_irq_lines[31] ;
+ wire \u_riscv_top.core2_irq_lines[3] ;
+ wire \u_riscv_top.core2_irq_lines[4] ;
+ wire \u_riscv_top.core2_irq_lines[5] ;
+ wire \u_riscv_top.core2_irq_lines[6] ;
+ wire \u_riscv_top.core2_irq_lines[7] ;
+ wire \u_riscv_top.core2_irq_lines[8] ;
+ wire \u_riscv_top.core2_irq_lines[9] ;
+ wire \u_riscv_top.core2_soft_irq ;
+ wire \u_riscv_top.core2_timer_irq ;
+ wire \u_riscv_top.core2_timer_val[0] ;
+ wire \u_riscv_top.core2_timer_val[10] ;
+ wire \u_riscv_top.core2_timer_val[11] ;
+ wire \u_riscv_top.core2_timer_val[12] ;
+ wire \u_riscv_top.core2_timer_val[13] ;
+ wire \u_riscv_top.core2_timer_val[14] ;
+ wire \u_riscv_top.core2_timer_val[15] ;
+ wire \u_riscv_top.core2_timer_val[16] ;
+ wire \u_riscv_top.core2_timer_val[17] ;
+ wire \u_riscv_top.core2_timer_val[18] ;
+ wire \u_riscv_top.core2_timer_val[19] ;
+ wire \u_riscv_top.core2_timer_val[1] ;
+ wire \u_riscv_top.core2_timer_val[20] ;
+ wire \u_riscv_top.core2_timer_val[21] ;
+ wire \u_riscv_top.core2_timer_val[22] ;
+ wire \u_riscv_top.core2_timer_val[23] ;
+ wire \u_riscv_top.core2_timer_val[24] ;
+ wire \u_riscv_top.core2_timer_val[25] ;
+ wire \u_riscv_top.core2_timer_val[26] ;
+ wire \u_riscv_top.core2_timer_val[27] ;
+ wire \u_riscv_top.core2_timer_val[28] ;
+ wire \u_riscv_top.core2_timer_val[29] ;
+ wire \u_riscv_top.core2_timer_val[2] ;
+ wire \u_riscv_top.core2_timer_val[30] ;
+ wire \u_riscv_top.core2_timer_val[31] ;
+ wire \u_riscv_top.core2_timer_val[32] ;
+ wire \u_riscv_top.core2_timer_val[33] ;
+ wire \u_riscv_top.core2_timer_val[34] ;
+ wire \u_riscv_top.core2_timer_val[35] ;
+ wire \u_riscv_top.core2_timer_val[36] ;
+ wire \u_riscv_top.core2_timer_val[37] ;
+ wire \u_riscv_top.core2_timer_val[38] ;
+ wire \u_riscv_top.core2_timer_val[39] ;
+ wire \u_riscv_top.core2_timer_val[3] ;
+ wire \u_riscv_top.core2_timer_val[40] ;
+ wire \u_riscv_top.core2_timer_val[41] ;
+ wire \u_riscv_top.core2_timer_val[42] ;
+ wire \u_riscv_top.core2_timer_val[43] ;
+ wire \u_riscv_top.core2_timer_val[44] ;
+ wire \u_riscv_top.core2_timer_val[45] ;
+ wire \u_riscv_top.core2_timer_val[46] ;
+ wire \u_riscv_top.core2_timer_val[47] ;
+ wire \u_riscv_top.core2_timer_val[48] ;
+ wire \u_riscv_top.core2_timer_val[49] ;
+ wire \u_riscv_top.core2_timer_val[4] ;
+ wire \u_riscv_top.core2_timer_val[50] ;
+ wire \u_riscv_top.core2_timer_val[51] ;
+ wire \u_riscv_top.core2_timer_val[52] ;
+ wire \u_riscv_top.core2_timer_val[53] ;
+ wire \u_riscv_top.core2_timer_val[54] ;
+ wire \u_riscv_top.core2_timer_val[55] ;
+ wire \u_riscv_top.core2_timer_val[56] ;
+ wire \u_riscv_top.core2_timer_val[57] ;
+ wire \u_riscv_top.core2_timer_val[58] ;
+ wire \u_riscv_top.core2_timer_val[59] ;
+ wire \u_riscv_top.core2_timer_val[5] ;
+ wire \u_riscv_top.core2_timer_val[60] ;
+ wire \u_riscv_top.core2_timer_val[61] ;
+ wire \u_riscv_top.core2_timer_val[62] ;
+ wire \u_riscv_top.core2_timer_val[63] ;
+ wire \u_riscv_top.core2_timer_val[6] ;
+ wire \u_riscv_top.core2_timer_val[7] ;
+ wire \u_riscv_top.core2_timer_val[8] ;
+ wire \u_riscv_top.core2_timer_val[9] ;
+ wire \u_riscv_top.core2_uid[0] ;
+ wire \u_riscv_top.core2_uid[1] ;
+ wire \u_riscv_top.core3_clk ;
+ wire \u_riscv_top.core3_debug[0] ;
+ wire \u_riscv_top.core3_debug[10] ;
+ wire \u_riscv_top.core3_debug[11] ;
+ wire \u_riscv_top.core3_debug[12] ;
+ wire \u_riscv_top.core3_debug[13] ;
+ wire \u_riscv_top.core3_debug[14] ;
+ wire \u_riscv_top.core3_debug[15] ;
+ wire \u_riscv_top.core3_debug[16] ;
+ wire \u_riscv_top.core3_debug[17] ;
+ wire \u_riscv_top.core3_debug[18] ;
+ wire \u_riscv_top.core3_debug[19] ;
+ wire \u_riscv_top.core3_debug[1] ;
+ wire \u_riscv_top.core3_debug[20] ;
+ wire \u_riscv_top.core3_debug[21] ;
+ wire \u_riscv_top.core3_debug[22] ;
+ wire \u_riscv_top.core3_debug[23] ;
+ wire \u_riscv_top.core3_debug[24] ;
+ wire \u_riscv_top.core3_debug[25] ;
+ wire \u_riscv_top.core3_debug[26] ;
+ wire \u_riscv_top.core3_debug[27] ;
+ wire \u_riscv_top.core3_debug[28] ;
+ wire \u_riscv_top.core3_debug[29] ;
+ wire \u_riscv_top.core3_debug[2] ;
+ wire \u_riscv_top.core3_debug[30] ;
+ wire \u_riscv_top.core3_debug[31] ;
+ wire \u_riscv_top.core3_debug[32] ;
+ wire \u_riscv_top.core3_debug[33] ;
+ wire \u_riscv_top.core3_debug[34] ;
+ wire \u_riscv_top.core3_debug[35] ;
+ wire \u_riscv_top.core3_debug[36] ;
+ wire \u_riscv_top.core3_debug[37] ;
+ wire \u_riscv_top.core3_debug[38] ;
+ wire \u_riscv_top.core3_debug[39] ;
+ wire \u_riscv_top.core3_debug[3] ;
+ wire \u_riscv_top.core3_debug[40] ;
+ wire \u_riscv_top.core3_debug[41] ;
+ wire \u_riscv_top.core3_debug[42] ;
+ wire \u_riscv_top.core3_debug[43] ;
+ wire \u_riscv_top.core3_debug[44] ;
+ wire \u_riscv_top.core3_debug[45] ;
+ wire \u_riscv_top.core3_debug[46] ;
+ wire \u_riscv_top.core3_debug[47] ;
+ wire \u_riscv_top.core3_debug[48] ;
+ wire \u_riscv_top.core3_debug[4] ;
+ wire \u_riscv_top.core3_debug[5] ;
+ wire \u_riscv_top.core3_debug[6] ;
+ wire \u_riscv_top.core3_debug[7] ;
+ wire \u_riscv_top.core3_debug[8] ;
+ wire \u_riscv_top.core3_debug[9] ;
+ wire \u_riscv_top.core3_dmem_addr[0] ;
+ wire \u_riscv_top.core3_dmem_addr[10] ;
+ wire \u_riscv_top.core3_dmem_addr[11] ;
+ wire \u_riscv_top.core3_dmem_addr[12] ;
+ wire \u_riscv_top.core3_dmem_addr[13] ;
+ wire \u_riscv_top.core3_dmem_addr[14] ;
+ wire \u_riscv_top.core3_dmem_addr[15] ;
+ wire \u_riscv_top.core3_dmem_addr[16] ;
+ wire \u_riscv_top.core3_dmem_addr[17] ;
+ wire \u_riscv_top.core3_dmem_addr[18] ;
+ wire \u_riscv_top.core3_dmem_addr[19] ;
+ wire \u_riscv_top.core3_dmem_addr[1] ;
+ wire \u_riscv_top.core3_dmem_addr[20] ;
+ wire \u_riscv_top.core3_dmem_addr[21] ;
+ wire \u_riscv_top.core3_dmem_addr[22] ;
+ wire \u_riscv_top.core3_dmem_addr[23] ;
+ wire \u_riscv_top.core3_dmem_addr[24] ;
+ wire \u_riscv_top.core3_dmem_addr[25] ;
+ wire \u_riscv_top.core3_dmem_addr[26] ;
+ wire \u_riscv_top.core3_dmem_addr[27] ;
+ wire \u_riscv_top.core3_dmem_addr[28] ;
+ wire \u_riscv_top.core3_dmem_addr[29] ;
+ wire \u_riscv_top.core3_dmem_addr[2] ;
+ wire \u_riscv_top.core3_dmem_addr[30] ;
+ wire \u_riscv_top.core3_dmem_addr[31] ;
+ wire \u_riscv_top.core3_dmem_addr[3] ;
+ wire \u_riscv_top.core3_dmem_addr[4] ;
+ wire \u_riscv_top.core3_dmem_addr[5] ;
+ wire \u_riscv_top.core3_dmem_addr[6] ;
+ wire \u_riscv_top.core3_dmem_addr[7] ;
+ wire \u_riscv_top.core3_dmem_addr[8] ;
+ wire \u_riscv_top.core3_dmem_addr[9] ;
+ wire \u_riscv_top.core3_dmem_cmd ;
+ wire \u_riscv_top.core3_dmem_rdata[0] ;
+ wire \u_riscv_top.core3_dmem_rdata[10] ;
+ wire \u_riscv_top.core3_dmem_rdata[11] ;
+ wire \u_riscv_top.core3_dmem_rdata[12] ;
+ wire \u_riscv_top.core3_dmem_rdata[13] ;
+ wire \u_riscv_top.core3_dmem_rdata[14] ;
+ wire \u_riscv_top.core3_dmem_rdata[15] ;
+ wire \u_riscv_top.core3_dmem_rdata[16] ;
+ wire \u_riscv_top.core3_dmem_rdata[17] ;
+ wire \u_riscv_top.core3_dmem_rdata[18] ;
+ wire \u_riscv_top.core3_dmem_rdata[19] ;
+ wire \u_riscv_top.core3_dmem_rdata[1] ;
+ wire \u_riscv_top.core3_dmem_rdata[20] ;
+ wire \u_riscv_top.core3_dmem_rdata[21] ;
+ wire \u_riscv_top.core3_dmem_rdata[22] ;
+ wire \u_riscv_top.core3_dmem_rdata[23] ;
+ wire \u_riscv_top.core3_dmem_rdata[24] ;
+ wire \u_riscv_top.core3_dmem_rdata[25] ;
+ wire \u_riscv_top.core3_dmem_rdata[26] ;
+ wire \u_riscv_top.core3_dmem_rdata[27] ;
+ wire \u_riscv_top.core3_dmem_rdata[28] ;
+ wire \u_riscv_top.core3_dmem_rdata[29] ;
+ wire \u_riscv_top.core3_dmem_rdata[2] ;
+ wire \u_riscv_top.core3_dmem_rdata[30] ;
+ wire \u_riscv_top.core3_dmem_rdata[31] ;
+ wire \u_riscv_top.core3_dmem_rdata[3] ;
+ wire \u_riscv_top.core3_dmem_rdata[4] ;
+ wire \u_riscv_top.core3_dmem_rdata[5] ;
+ wire \u_riscv_top.core3_dmem_rdata[6] ;
+ wire \u_riscv_top.core3_dmem_rdata[7] ;
+ wire \u_riscv_top.core3_dmem_rdata[8] ;
+ wire \u_riscv_top.core3_dmem_rdata[9] ;
+ wire \u_riscv_top.core3_dmem_req ;
+ wire \u_riscv_top.core3_dmem_req_ack ;
+ wire \u_riscv_top.core3_dmem_resp[0] ;
+ wire \u_riscv_top.core3_dmem_resp[1] ;
+ wire \u_riscv_top.core3_dmem_wdata[0] ;
+ wire \u_riscv_top.core3_dmem_wdata[10] ;
+ wire \u_riscv_top.core3_dmem_wdata[11] ;
+ wire \u_riscv_top.core3_dmem_wdata[12] ;
+ wire \u_riscv_top.core3_dmem_wdata[13] ;
+ wire \u_riscv_top.core3_dmem_wdata[14] ;
+ wire \u_riscv_top.core3_dmem_wdata[15] ;
+ wire \u_riscv_top.core3_dmem_wdata[16] ;
+ wire \u_riscv_top.core3_dmem_wdata[17] ;
+ wire \u_riscv_top.core3_dmem_wdata[18] ;
+ wire \u_riscv_top.core3_dmem_wdata[19] ;
+ wire \u_riscv_top.core3_dmem_wdata[1] ;
+ wire \u_riscv_top.core3_dmem_wdata[20] ;
+ wire \u_riscv_top.core3_dmem_wdata[21] ;
+ wire \u_riscv_top.core3_dmem_wdata[22] ;
+ wire \u_riscv_top.core3_dmem_wdata[23] ;
+ wire \u_riscv_top.core3_dmem_wdata[24] ;
+ wire \u_riscv_top.core3_dmem_wdata[25] ;
+ wire \u_riscv_top.core3_dmem_wdata[26] ;
+ wire \u_riscv_top.core3_dmem_wdata[27] ;
+ wire \u_riscv_top.core3_dmem_wdata[28] ;
+ wire \u_riscv_top.core3_dmem_wdata[29] ;
+ wire \u_riscv_top.core3_dmem_wdata[2] ;
+ wire \u_riscv_top.core3_dmem_wdata[30] ;
+ wire \u_riscv_top.core3_dmem_wdata[31] ;
+ wire \u_riscv_top.core3_dmem_wdata[3] ;
+ wire \u_riscv_top.core3_dmem_wdata[4] ;
+ wire \u_riscv_top.core3_dmem_wdata[5] ;
+ wire \u_riscv_top.core3_dmem_wdata[6] ;
+ wire \u_riscv_top.core3_dmem_wdata[7] ;
+ wire \u_riscv_top.core3_dmem_wdata[8] ;
+ wire \u_riscv_top.core3_dmem_wdata[9] ;
+ wire \u_riscv_top.core3_dmem_width[0] ;
+ wire \u_riscv_top.core3_dmem_width[1] ;
+ wire \u_riscv_top.core3_imem_addr[0] ;
+ wire \u_riscv_top.core3_imem_addr[10] ;
+ wire \u_riscv_top.core3_imem_addr[11] ;
+ wire \u_riscv_top.core3_imem_addr[12] ;
+ wire \u_riscv_top.core3_imem_addr[13] ;
+ wire \u_riscv_top.core3_imem_addr[14] ;
+ wire \u_riscv_top.core3_imem_addr[15] ;
+ wire \u_riscv_top.core3_imem_addr[16] ;
+ wire \u_riscv_top.core3_imem_addr[17] ;
+ wire \u_riscv_top.core3_imem_addr[18] ;
+ wire \u_riscv_top.core3_imem_addr[19] ;
+ wire \u_riscv_top.core3_imem_addr[1] ;
+ wire \u_riscv_top.core3_imem_addr[20] ;
+ wire \u_riscv_top.core3_imem_addr[21] ;
+ wire \u_riscv_top.core3_imem_addr[22] ;
+ wire \u_riscv_top.core3_imem_addr[23] ;
+ wire \u_riscv_top.core3_imem_addr[24] ;
+ wire \u_riscv_top.core3_imem_addr[25] ;
+ wire \u_riscv_top.core3_imem_addr[26] ;
+ wire \u_riscv_top.core3_imem_addr[27] ;
+ wire \u_riscv_top.core3_imem_addr[28] ;
+ wire \u_riscv_top.core3_imem_addr[29] ;
+ wire \u_riscv_top.core3_imem_addr[2] ;
+ wire \u_riscv_top.core3_imem_addr[30] ;
+ wire \u_riscv_top.core3_imem_addr[31] ;
+ wire \u_riscv_top.core3_imem_addr[3] ;
+ wire \u_riscv_top.core3_imem_addr[4] ;
+ wire \u_riscv_top.core3_imem_addr[5] ;
+ wire \u_riscv_top.core3_imem_addr[6] ;
+ wire \u_riscv_top.core3_imem_addr[7] ;
+ wire \u_riscv_top.core3_imem_addr[8] ;
+ wire \u_riscv_top.core3_imem_addr[9] ;
+ wire \u_riscv_top.core3_imem_bl[0] ;
+ wire \u_riscv_top.core3_imem_bl[1] ;
+ wire \u_riscv_top.core3_imem_bl[2] ;
+ wire \u_riscv_top.core3_imem_cmd ;
+ wire \u_riscv_top.core3_imem_rdata[0] ;
+ wire \u_riscv_top.core3_imem_rdata[10] ;
+ wire \u_riscv_top.core3_imem_rdata[11] ;
+ wire \u_riscv_top.core3_imem_rdata[12] ;
+ wire \u_riscv_top.core3_imem_rdata[13] ;
+ wire \u_riscv_top.core3_imem_rdata[14] ;
+ wire \u_riscv_top.core3_imem_rdata[15] ;
+ wire \u_riscv_top.core3_imem_rdata[16] ;
+ wire \u_riscv_top.core3_imem_rdata[17] ;
+ wire \u_riscv_top.core3_imem_rdata[18] ;
+ wire \u_riscv_top.core3_imem_rdata[19] ;
+ wire \u_riscv_top.core3_imem_rdata[1] ;
+ wire \u_riscv_top.core3_imem_rdata[20] ;
+ wire \u_riscv_top.core3_imem_rdata[21] ;
+ wire \u_riscv_top.core3_imem_rdata[22] ;
+ wire \u_riscv_top.core3_imem_rdata[23] ;
+ wire \u_riscv_top.core3_imem_rdata[24] ;
+ wire \u_riscv_top.core3_imem_rdata[25] ;
+ wire \u_riscv_top.core3_imem_rdata[26] ;
+ wire \u_riscv_top.core3_imem_rdata[27] ;
+ wire \u_riscv_top.core3_imem_rdata[28] ;
+ wire \u_riscv_top.core3_imem_rdata[29] ;
+ wire \u_riscv_top.core3_imem_rdata[2] ;
+ wire \u_riscv_top.core3_imem_rdata[30] ;
+ wire \u_riscv_top.core3_imem_rdata[31] ;
+ wire \u_riscv_top.core3_imem_rdata[3] ;
+ wire \u_riscv_top.core3_imem_rdata[4] ;
+ wire \u_riscv_top.core3_imem_rdata[5] ;
+ wire \u_riscv_top.core3_imem_rdata[6] ;
+ wire \u_riscv_top.core3_imem_rdata[7] ;
+ wire \u_riscv_top.core3_imem_rdata[8] ;
+ wire \u_riscv_top.core3_imem_rdata[9] ;
+ wire \u_riscv_top.core3_imem_req ;
+ wire \u_riscv_top.core3_imem_req_ack ;
+ wire \u_riscv_top.core3_imem_resp[0] ;
+ wire \u_riscv_top.core3_imem_resp[1] ;
+ wire \u_riscv_top.core3_irq_lines[0] ;
+ wire \u_riscv_top.core3_irq_lines[10] ;
+ wire \u_riscv_top.core3_irq_lines[11] ;
+ wire \u_riscv_top.core3_irq_lines[12] ;
+ wire \u_riscv_top.core3_irq_lines[13] ;
+ wire \u_riscv_top.core3_irq_lines[14] ;
+ wire \u_riscv_top.core3_irq_lines[15] ;
+ wire \u_riscv_top.core3_irq_lines[16] ;
+ wire \u_riscv_top.core3_irq_lines[17] ;
+ wire \u_riscv_top.core3_irq_lines[18] ;
+ wire \u_riscv_top.core3_irq_lines[19] ;
+ wire \u_riscv_top.core3_irq_lines[1] ;
+ wire \u_riscv_top.core3_irq_lines[20] ;
+ wire \u_riscv_top.core3_irq_lines[21] ;
+ wire \u_riscv_top.core3_irq_lines[22] ;
+ wire \u_riscv_top.core3_irq_lines[23] ;
+ wire \u_riscv_top.core3_irq_lines[24] ;
+ wire \u_riscv_top.core3_irq_lines[25] ;
+ wire \u_riscv_top.core3_irq_lines[26] ;
+ wire \u_riscv_top.core3_irq_lines[27] ;
+ wire \u_riscv_top.core3_irq_lines[28] ;
+ wire \u_riscv_top.core3_irq_lines[29] ;
+ wire \u_riscv_top.core3_irq_lines[2] ;
+ wire \u_riscv_top.core3_irq_lines[30] ;
+ wire \u_riscv_top.core3_irq_lines[31] ;
+ wire \u_riscv_top.core3_irq_lines[3] ;
+ wire \u_riscv_top.core3_irq_lines[4] ;
+ wire \u_riscv_top.core3_irq_lines[5] ;
+ wire \u_riscv_top.core3_irq_lines[6] ;
+ wire \u_riscv_top.core3_irq_lines[7] ;
+ wire \u_riscv_top.core3_irq_lines[8] ;
+ wire \u_riscv_top.core3_irq_lines[9] ;
+ wire \u_riscv_top.core3_soft_irq ;
+ wire \u_riscv_top.core3_timer_irq ;
+ wire \u_riscv_top.core3_timer_val[0] ;
+ wire \u_riscv_top.core3_timer_val[10] ;
+ wire \u_riscv_top.core3_timer_val[11] ;
+ wire \u_riscv_top.core3_timer_val[12] ;
+ wire \u_riscv_top.core3_timer_val[13] ;
+ wire \u_riscv_top.core3_timer_val[14] ;
+ wire \u_riscv_top.core3_timer_val[15] ;
+ wire \u_riscv_top.core3_timer_val[16] ;
+ wire \u_riscv_top.core3_timer_val[17] ;
+ wire \u_riscv_top.core3_timer_val[18] ;
+ wire \u_riscv_top.core3_timer_val[19] ;
+ wire \u_riscv_top.core3_timer_val[1] ;
+ wire \u_riscv_top.core3_timer_val[20] ;
+ wire \u_riscv_top.core3_timer_val[21] ;
+ wire \u_riscv_top.core3_timer_val[22] ;
+ wire \u_riscv_top.core3_timer_val[23] ;
+ wire \u_riscv_top.core3_timer_val[24] ;
+ wire \u_riscv_top.core3_timer_val[25] ;
+ wire \u_riscv_top.core3_timer_val[26] ;
+ wire \u_riscv_top.core3_timer_val[27] ;
+ wire \u_riscv_top.core3_timer_val[28] ;
+ wire \u_riscv_top.core3_timer_val[29] ;
+ wire \u_riscv_top.core3_timer_val[2] ;
+ wire \u_riscv_top.core3_timer_val[30] ;
+ wire \u_riscv_top.core3_timer_val[31] ;
+ wire \u_riscv_top.core3_timer_val[32] ;
+ wire \u_riscv_top.core3_timer_val[33] ;
+ wire \u_riscv_top.core3_timer_val[34] ;
+ wire \u_riscv_top.core3_timer_val[35] ;
+ wire \u_riscv_top.core3_timer_val[36] ;
+ wire \u_riscv_top.core3_timer_val[37] ;
+ wire \u_riscv_top.core3_timer_val[38] ;
+ wire \u_riscv_top.core3_timer_val[39] ;
+ wire \u_riscv_top.core3_timer_val[3] ;
+ wire \u_riscv_top.core3_timer_val[40] ;
+ wire \u_riscv_top.core3_timer_val[41] ;
+ wire \u_riscv_top.core3_timer_val[42] ;
+ wire \u_riscv_top.core3_timer_val[43] ;
+ wire \u_riscv_top.core3_timer_val[44] ;
+ wire \u_riscv_top.core3_timer_val[45] ;
+ wire \u_riscv_top.core3_timer_val[46] ;
+ wire \u_riscv_top.core3_timer_val[47] ;
+ wire \u_riscv_top.core3_timer_val[48] ;
+ wire \u_riscv_top.core3_timer_val[49] ;
+ wire \u_riscv_top.core3_timer_val[4] ;
+ wire \u_riscv_top.core3_timer_val[50] ;
+ wire \u_riscv_top.core3_timer_val[51] ;
+ wire \u_riscv_top.core3_timer_val[52] ;
+ wire \u_riscv_top.core3_timer_val[53] ;
+ wire \u_riscv_top.core3_timer_val[54] ;
+ wire \u_riscv_top.core3_timer_val[55] ;
+ wire \u_riscv_top.core3_timer_val[56] ;
+ wire \u_riscv_top.core3_timer_val[57] ;
+ wire \u_riscv_top.core3_timer_val[58] ;
+ wire \u_riscv_top.core3_timer_val[59] ;
+ wire \u_riscv_top.core3_timer_val[5] ;
+ wire \u_riscv_top.core3_timer_val[60] ;
+ wire \u_riscv_top.core3_timer_val[61] ;
+ wire \u_riscv_top.core3_timer_val[62] ;
+ wire \u_riscv_top.core3_timer_val[63] ;
+ wire \u_riscv_top.core3_timer_val[6] ;
+ wire \u_riscv_top.core3_timer_val[7] ;
+ wire \u_riscv_top.core3_timer_val[8] ;
+ wire \u_riscv_top.core3_timer_val[9] ;
+ wire \u_riscv_top.core3_uid[0] ;
+ wire \u_riscv_top.core3_uid[1] ;
+ wire \u_riscv_top.core_clk_core0_skew ;
+ wire \u_riscv_top.core_clk_core1_skew ;
+ wire \u_riscv_top.core_clk_core2_skew ;
+ wire \u_riscv_top.core_clk_core3_skew ;
+ wire \u_riscv_top.core_clk_icon_skew ;
+ wire \u_riscv_top.core_clk_int[0] ;
+ wire \u_riscv_top.core_clk_int[1] ;
+ wire \u_riscv_top.core_clk_intf_skew ;
+ wire \u_riscv_top.core_clk_out[0] ;
+ wire \u_riscv_top.core_clk_out[1] ;
+ wire \u_riscv_top.core_clk_out[2] ;
+ wire \u_riscv_top.core_clk_out[3] ;
+ wire \u_riscv_top.core_dcache_addr[0] ;
+ wire \u_riscv_top.core_dcache_addr[10] ;
+ wire \u_riscv_top.core_dcache_addr[11] ;
+ wire \u_riscv_top.core_dcache_addr[12] ;
+ wire \u_riscv_top.core_dcache_addr[13] ;
+ wire \u_riscv_top.core_dcache_addr[14] ;
+ wire \u_riscv_top.core_dcache_addr[15] ;
+ wire \u_riscv_top.core_dcache_addr[16] ;
+ wire \u_riscv_top.core_dcache_addr[17] ;
+ wire \u_riscv_top.core_dcache_addr[18] ;
+ wire \u_riscv_top.core_dcache_addr[19] ;
+ wire \u_riscv_top.core_dcache_addr[1] ;
+ wire \u_riscv_top.core_dcache_addr[20] ;
+ wire \u_riscv_top.core_dcache_addr[21] ;
+ wire \u_riscv_top.core_dcache_addr[22] ;
+ wire \u_riscv_top.core_dcache_addr[23] ;
+ wire \u_riscv_top.core_dcache_addr[24] ;
+ wire \u_riscv_top.core_dcache_addr[25] ;
+ wire \u_riscv_top.core_dcache_addr[26] ;
+ wire \u_riscv_top.core_dcache_addr[27] ;
+ wire \u_riscv_top.core_dcache_addr[28] ;
+ wire \u_riscv_top.core_dcache_addr[29] ;
+ wire \u_riscv_top.core_dcache_addr[2] ;
+ wire \u_riscv_top.core_dcache_addr[30] ;
+ wire \u_riscv_top.core_dcache_addr[31] ;
+ wire \u_riscv_top.core_dcache_addr[3] ;
+ wire \u_riscv_top.core_dcache_addr[4] ;
+ wire \u_riscv_top.core_dcache_addr[5] ;
+ wire \u_riscv_top.core_dcache_addr[6] ;
+ wire \u_riscv_top.core_dcache_addr[7] ;
+ wire \u_riscv_top.core_dcache_addr[8] ;
+ wire \u_riscv_top.core_dcache_addr[9] ;
+ wire \u_riscv_top.core_dcache_cmd ;
+ wire \u_riscv_top.core_dcache_rdata[0] ;
+ wire \u_riscv_top.core_dcache_rdata[10] ;
+ wire \u_riscv_top.core_dcache_rdata[11] ;
+ wire \u_riscv_top.core_dcache_rdata[12] ;
+ wire \u_riscv_top.core_dcache_rdata[13] ;
+ wire \u_riscv_top.core_dcache_rdata[14] ;
+ wire \u_riscv_top.core_dcache_rdata[15] ;
+ wire \u_riscv_top.core_dcache_rdata[16] ;
+ wire \u_riscv_top.core_dcache_rdata[17] ;
+ wire \u_riscv_top.core_dcache_rdata[18] ;
+ wire \u_riscv_top.core_dcache_rdata[19] ;
+ wire \u_riscv_top.core_dcache_rdata[1] ;
+ wire \u_riscv_top.core_dcache_rdata[20] ;
+ wire \u_riscv_top.core_dcache_rdata[21] ;
+ wire \u_riscv_top.core_dcache_rdata[22] ;
+ wire \u_riscv_top.core_dcache_rdata[23] ;
+ wire \u_riscv_top.core_dcache_rdata[24] ;
+ wire \u_riscv_top.core_dcache_rdata[25] ;
+ wire \u_riscv_top.core_dcache_rdata[26] ;
+ wire \u_riscv_top.core_dcache_rdata[27] ;
+ wire \u_riscv_top.core_dcache_rdata[28] ;
+ wire \u_riscv_top.core_dcache_rdata[29] ;
+ wire \u_riscv_top.core_dcache_rdata[2] ;
+ wire \u_riscv_top.core_dcache_rdata[30] ;
+ wire \u_riscv_top.core_dcache_rdata[31] ;
+ wire \u_riscv_top.core_dcache_rdata[3] ;
+ wire \u_riscv_top.core_dcache_rdata[4] ;
+ wire \u_riscv_top.core_dcache_rdata[5] ;
+ wire \u_riscv_top.core_dcache_rdata[6] ;
+ wire \u_riscv_top.core_dcache_rdata[7] ;
+ wire \u_riscv_top.core_dcache_rdata[8] ;
+ wire \u_riscv_top.core_dcache_rdata[9] ;
+ wire \u_riscv_top.core_dcache_req ;
+ wire \u_riscv_top.core_dcache_req_ack ;
+ wire \u_riscv_top.core_dcache_resp[0] ;
+ wire \u_riscv_top.core_dcache_resp[1] ;
+ wire \u_riscv_top.core_dcache_wdata[0] ;
+ wire \u_riscv_top.core_dcache_wdata[10] ;
+ wire \u_riscv_top.core_dcache_wdata[11] ;
+ wire \u_riscv_top.core_dcache_wdata[12] ;
+ wire \u_riscv_top.core_dcache_wdata[13] ;
+ wire \u_riscv_top.core_dcache_wdata[14] ;
+ wire \u_riscv_top.core_dcache_wdata[15] ;
+ wire \u_riscv_top.core_dcache_wdata[16] ;
+ wire \u_riscv_top.core_dcache_wdata[17] ;
+ wire \u_riscv_top.core_dcache_wdata[18] ;
+ wire \u_riscv_top.core_dcache_wdata[19] ;
+ wire \u_riscv_top.core_dcache_wdata[1] ;
+ wire \u_riscv_top.core_dcache_wdata[20] ;
+ wire \u_riscv_top.core_dcache_wdata[21] ;
+ wire \u_riscv_top.core_dcache_wdata[22] ;
+ wire \u_riscv_top.core_dcache_wdata[23] ;
+ wire \u_riscv_top.core_dcache_wdata[24] ;
+ wire \u_riscv_top.core_dcache_wdata[25] ;
+ wire \u_riscv_top.core_dcache_wdata[26] ;
+ wire \u_riscv_top.core_dcache_wdata[27] ;
+ wire \u_riscv_top.core_dcache_wdata[28] ;
+ wire \u_riscv_top.core_dcache_wdata[29] ;
+ wire \u_riscv_top.core_dcache_wdata[2] ;
+ wire \u_riscv_top.core_dcache_wdata[30] ;
+ wire \u_riscv_top.core_dcache_wdata[31] ;
+ wire \u_riscv_top.core_dcache_wdata[3] ;
+ wire \u_riscv_top.core_dcache_wdata[4] ;
+ wire \u_riscv_top.core_dcache_wdata[5] ;
+ wire \u_riscv_top.core_dcache_wdata[6] ;
+ wire \u_riscv_top.core_dcache_wdata[7] ;
+ wire \u_riscv_top.core_dcache_wdata[8] ;
+ wire \u_riscv_top.core_dcache_wdata[9] ;
+ wire \u_riscv_top.core_dcache_width[0] ;
+ wire \u_riscv_top.core_dcache_width[1] ;
+ wire \u_riscv_top.core_dmem_addr[0] ;
+ wire \u_riscv_top.core_dmem_addr[10] ;
+ wire \u_riscv_top.core_dmem_addr[11] ;
+ wire \u_riscv_top.core_dmem_addr[12] ;
+ wire \u_riscv_top.core_dmem_addr[13] ;
+ wire \u_riscv_top.core_dmem_addr[14] ;
+ wire \u_riscv_top.core_dmem_addr[15] ;
+ wire \u_riscv_top.core_dmem_addr[16] ;
+ wire \u_riscv_top.core_dmem_addr[17] ;
+ wire \u_riscv_top.core_dmem_addr[18] ;
+ wire \u_riscv_top.core_dmem_addr[19] ;
+ wire \u_riscv_top.core_dmem_addr[1] ;
+ wire \u_riscv_top.core_dmem_addr[20] ;
+ wire \u_riscv_top.core_dmem_addr[21] ;
+ wire \u_riscv_top.core_dmem_addr[22] ;
+ wire \u_riscv_top.core_dmem_addr[23] ;
+ wire \u_riscv_top.core_dmem_addr[24] ;
+ wire \u_riscv_top.core_dmem_addr[25] ;
+ wire \u_riscv_top.core_dmem_addr[26] ;
+ wire \u_riscv_top.core_dmem_addr[27] ;
+ wire \u_riscv_top.core_dmem_addr[28] ;
+ wire \u_riscv_top.core_dmem_addr[29] ;
+ wire \u_riscv_top.core_dmem_addr[2] ;
+ wire \u_riscv_top.core_dmem_addr[30] ;
+ wire \u_riscv_top.core_dmem_addr[31] ;
+ wire \u_riscv_top.core_dmem_addr[3] ;
+ wire \u_riscv_top.core_dmem_addr[4] ;
+ wire \u_riscv_top.core_dmem_addr[5] ;
+ wire \u_riscv_top.core_dmem_addr[6] ;
+ wire \u_riscv_top.core_dmem_addr[7] ;
+ wire \u_riscv_top.core_dmem_addr[8] ;
+ wire \u_riscv_top.core_dmem_addr[9] ;
+ wire \u_riscv_top.core_dmem_bl[0] ;
+ wire \u_riscv_top.core_dmem_bl[1] ;
+ wire \u_riscv_top.core_dmem_bl[2] ;
+ wire \u_riscv_top.core_dmem_cmd ;
+ wire \u_riscv_top.core_dmem_rdata[0] ;
+ wire \u_riscv_top.core_dmem_rdata[10] ;
+ wire \u_riscv_top.core_dmem_rdata[11] ;
+ wire \u_riscv_top.core_dmem_rdata[12] ;
+ wire \u_riscv_top.core_dmem_rdata[13] ;
+ wire \u_riscv_top.core_dmem_rdata[14] ;
+ wire \u_riscv_top.core_dmem_rdata[15] ;
+ wire \u_riscv_top.core_dmem_rdata[16] ;
+ wire \u_riscv_top.core_dmem_rdata[17] ;
+ wire \u_riscv_top.core_dmem_rdata[18] ;
+ wire \u_riscv_top.core_dmem_rdata[19] ;
+ wire \u_riscv_top.core_dmem_rdata[1] ;
+ wire \u_riscv_top.core_dmem_rdata[20] ;
+ wire \u_riscv_top.core_dmem_rdata[21] ;
+ wire \u_riscv_top.core_dmem_rdata[22] ;
+ wire \u_riscv_top.core_dmem_rdata[23] ;
+ wire \u_riscv_top.core_dmem_rdata[24] ;
+ wire \u_riscv_top.core_dmem_rdata[25] ;
+ wire \u_riscv_top.core_dmem_rdata[26] ;
+ wire \u_riscv_top.core_dmem_rdata[27] ;
+ wire \u_riscv_top.core_dmem_rdata[28] ;
+ wire \u_riscv_top.core_dmem_rdata[29] ;
+ wire \u_riscv_top.core_dmem_rdata[2] ;
+ wire \u_riscv_top.core_dmem_rdata[30] ;
+ wire \u_riscv_top.core_dmem_rdata[31] ;
+ wire \u_riscv_top.core_dmem_rdata[3] ;
+ wire \u_riscv_top.core_dmem_rdata[4] ;
+ wire \u_riscv_top.core_dmem_rdata[5] ;
+ wire \u_riscv_top.core_dmem_rdata[6] ;
+ wire \u_riscv_top.core_dmem_rdata[7] ;
+ wire \u_riscv_top.core_dmem_rdata[8] ;
+ wire \u_riscv_top.core_dmem_rdata[9] ;
+ wire \u_riscv_top.core_dmem_req ;
+ wire \u_riscv_top.core_dmem_req_ack ;
+ wire \u_riscv_top.core_dmem_resp[0] ;
+ wire \u_riscv_top.core_dmem_resp[1] ;
+ wire \u_riscv_top.core_dmem_wdata[0] ;
+ wire \u_riscv_top.core_dmem_wdata[10] ;
+ wire \u_riscv_top.core_dmem_wdata[11] ;
+ wire \u_riscv_top.core_dmem_wdata[12] ;
+ wire \u_riscv_top.core_dmem_wdata[13] ;
+ wire \u_riscv_top.core_dmem_wdata[14] ;
+ wire \u_riscv_top.core_dmem_wdata[15] ;
+ wire \u_riscv_top.core_dmem_wdata[16] ;
+ wire \u_riscv_top.core_dmem_wdata[17] ;
+ wire \u_riscv_top.core_dmem_wdata[18] ;
+ wire \u_riscv_top.core_dmem_wdata[19] ;
+ wire \u_riscv_top.core_dmem_wdata[1] ;
+ wire \u_riscv_top.core_dmem_wdata[20] ;
+ wire \u_riscv_top.core_dmem_wdata[21] ;
+ wire \u_riscv_top.core_dmem_wdata[22] ;
+ wire \u_riscv_top.core_dmem_wdata[23] ;
+ wire \u_riscv_top.core_dmem_wdata[24] ;
+ wire \u_riscv_top.core_dmem_wdata[25] ;
+ wire \u_riscv_top.core_dmem_wdata[26] ;
+ wire \u_riscv_top.core_dmem_wdata[27] ;
+ wire \u_riscv_top.core_dmem_wdata[28] ;
+ wire \u_riscv_top.core_dmem_wdata[29] ;
+ wire \u_riscv_top.core_dmem_wdata[2] ;
+ wire \u_riscv_top.core_dmem_wdata[30] ;
+ wire \u_riscv_top.core_dmem_wdata[31] ;
+ wire \u_riscv_top.core_dmem_wdata[3] ;
+ wire \u_riscv_top.core_dmem_wdata[4] ;
+ wire \u_riscv_top.core_dmem_wdata[5] ;
+ wire \u_riscv_top.core_dmem_wdata[6] ;
+ wire \u_riscv_top.core_dmem_wdata[7] ;
+ wire \u_riscv_top.core_dmem_wdata[8] ;
+ wire \u_riscv_top.core_dmem_wdata[9] ;
+ wire \u_riscv_top.core_dmem_width[0] ;
+ wire \u_riscv_top.core_dmem_width[1] ;
+ wire \u_riscv_top.core_icache_addr[0] ;
+ wire \u_riscv_top.core_icache_addr[10] ;
+ wire \u_riscv_top.core_icache_addr[11] ;
+ wire \u_riscv_top.core_icache_addr[12] ;
+ wire \u_riscv_top.core_icache_addr[13] ;
+ wire \u_riscv_top.core_icache_addr[14] ;
+ wire \u_riscv_top.core_icache_addr[15] ;
+ wire \u_riscv_top.core_icache_addr[16] ;
+ wire \u_riscv_top.core_icache_addr[17] ;
+ wire \u_riscv_top.core_icache_addr[18] ;
+ wire \u_riscv_top.core_icache_addr[19] ;
+ wire \u_riscv_top.core_icache_addr[1] ;
+ wire \u_riscv_top.core_icache_addr[20] ;
+ wire \u_riscv_top.core_icache_addr[21] ;
+ wire \u_riscv_top.core_icache_addr[22] ;
+ wire \u_riscv_top.core_icache_addr[23] ;
+ wire \u_riscv_top.core_icache_addr[24] ;
+ wire \u_riscv_top.core_icache_addr[25] ;
+ wire \u_riscv_top.core_icache_addr[26] ;
+ wire \u_riscv_top.core_icache_addr[27] ;
+ wire \u_riscv_top.core_icache_addr[28] ;
+ wire \u_riscv_top.core_icache_addr[29] ;
+ wire \u_riscv_top.core_icache_addr[2] ;
+ wire \u_riscv_top.core_icache_addr[30] ;
+ wire \u_riscv_top.core_icache_addr[31] ;
+ wire \u_riscv_top.core_icache_addr[3] ;
+ wire \u_riscv_top.core_icache_addr[4] ;
+ wire \u_riscv_top.core_icache_addr[5] ;
+ wire \u_riscv_top.core_icache_addr[6] ;
+ wire \u_riscv_top.core_icache_addr[7] ;
+ wire \u_riscv_top.core_icache_addr[8] ;
+ wire \u_riscv_top.core_icache_addr[9] ;
+ wire \u_riscv_top.core_icache_bl[0] ;
+ wire \u_riscv_top.core_icache_bl[1] ;
+ wire \u_riscv_top.core_icache_bl[2] ;
+ wire \u_riscv_top.core_icache_cmd ;
+ wire \u_riscv_top.core_icache_rdata[0] ;
+ wire \u_riscv_top.core_icache_rdata[10] ;
+ wire \u_riscv_top.core_icache_rdata[11] ;
+ wire \u_riscv_top.core_icache_rdata[12] ;
+ wire \u_riscv_top.core_icache_rdata[13] ;
+ wire \u_riscv_top.core_icache_rdata[14] ;
+ wire \u_riscv_top.core_icache_rdata[15] ;
+ wire \u_riscv_top.core_icache_rdata[16] ;
+ wire \u_riscv_top.core_icache_rdata[17] ;
+ wire \u_riscv_top.core_icache_rdata[18] ;
+ wire \u_riscv_top.core_icache_rdata[19] ;
+ wire \u_riscv_top.core_icache_rdata[1] ;
+ wire \u_riscv_top.core_icache_rdata[20] ;
+ wire \u_riscv_top.core_icache_rdata[21] ;
+ wire \u_riscv_top.core_icache_rdata[22] ;
+ wire \u_riscv_top.core_icache_rdata[23] ;
+ wire \u_riscv_top.core_icache_rdata[24] ;
+ wire \u_riscv_top.core_icache_rdata[25] ;
+ wire \u_riscv_top.core_icache_rdata[26] ;
+ wire \u_riscv_top.core_icache_rdata[27] ;
+ wire \u_riscv_top.core_icache_rdata[28] ;
+ wire \u_riscv_top.core_icache_rdata[29] ;
+ wire \u_riscv_top.core_icache_rdata[2] ;
+ wire \u_riscv_top.core_icache_rdata[30] ;
+ wire \u_riscv_top.core_icache_rdata[31] ;
+ wire \u_riscv_top.core_icache_rdata[3] ;
+ wire \u_riscv_top.core_icache_rdata[4] ;
+ wire \u_riscv_top.core_icache_rdata[5] ;
+ wire \u_riscv_top.core_icache_rdata[6] ;
+ wire \u_riscv_top.core_icache_rdata[7] ;
+ wire \u_riscv_top.core_icache_rdata[8] ;
+ wire \u_riscv_top.core_icache_rdata[9] ;
+ wire \u_riscv_top.core_icache_req ;
+ wire \u_riscv_top.core_icache_req_ack ;
+ wire \u_riscv_top.core_icache_resp[0] ;
+ wire \u_riscv_top.core_icache_resp[1] ;
+ wire \u_riscv_top.core_icache_width[0] ;
+ wire \u_riscv_top.core_icache_width[1] ;
+ wire \u_riscv_top.cpu_core_rst_n[0] ;
+ wire \u_riscv_top.cpu_core_rst_n[1] ;
+ wire \u_riscv_top.cpu_core_rst_n[2] ;
+ wire \u_riscv_top.cpu_core_rst_n[3] ;
+ wire \u_riscv_top.cpu_intf_rst_n ;
+ wire \u_riscv_top.dcache_mem_addr0[0] ;
+ wire \u_riscv_top.dcache_mem_addr0[1] ;
+ wire \u_riscv_top.dcache_mem_addr0[2] ;
+ wire \u_riscv_top.dcache_mem_addr0[3] ;
+ wire \u_riscv_top.dcache_mem_addr0[4] ;
+ wire \u_riscv_top.dcache_mem_addr0[5] ;
+ wire \u_riscv_top.dcache_mem_addr0[6] ;
+ wire \u_riscv_top.dcache_mem_addr0[7] ;
+ wire \u_riscv_top.dcache_mem_addr0[8] ;
+ wire \u_riscv_top.dcache_mem_addr1[0] ;
+ wire \u_riscv_top.dcache_mem_addr1[1] ;
+ wire \u_riscv_top.dcache_mem_addr1[2] ;
+ wire \u_riscv_top.dcache_mem_addr1[3] ;
+ wire \u_riscv_top.dcache_mem_addr1[4] ;
+ wire \u_riscv_top.dcache_mem_addr1[5] ;
+ wire \u_riscv_top.dcache_mem_addr1[6] ;
+ wire \u_riscv_top.dcache_mem_addr1[7] ;
+ wire \u_riscv_top.dcache_mem_addr1[8] ;
+ wire \u_riscv_top.dcache_mem_clk0 ;
+ wire \u_riscv_top.dcache_mem_clk1 ;
+ wire \u_riscv_top.dcache_mem_csb0 ;
+ wire \u_riscv_top.dcache_mem_csb1 ;
+ wire \u_riscv_top.dcache_mem_din0[0] ;
+ wire \u_riscv_top.dcache_mem_din0[10] ;
+ wire \u_riscv_top.dcache_mem_din0[11] ;
+ wire \u_riscv_top.dcache_mem_din0[12] ;
+ wire \u_riscv_top.dcache_mem_din0[13] ;
+ wire \u_riscv_top.dcache_mem_din0[14] ;
+ wire \u_riscv_top.dcache_mem_din0[15] ;
+ wire \u_riscv_top.dcache_mem_din0[16] ;
+ wire \u_riscv_top.dcache_mem_din0[17] ;
+ wire \u_riscv_top.dcache_mem_din0[18] ;
+ wire \u_riscv_top.dcache_mem_din0[19] ;
+ wire \u_riscv_top.dcache_mem_din0[1] ;
+ wire \u_riscv_top.dcache_mem_din0[20] ;
+ wire \u_riscv_top.dcache_mem_din0[21] ;
+ wire \u_riscv_top.dcache_mem_din0[22] ;
+ wire \u_riscv_top.dcache_mem_din0[23] ;
+ wire \u_riscv_top.dcache_mem_din0[24] ;
+ wire \u_riscv_top.dcache_mem_din0[25] ;
+ wire \u_riscv_top.dcache_mem_din0[26] ;
+ wire \u_riscv_top.dcache_mem_din0[27] ;
+ wire \u_riscv_top.dcache_mem_din0[28] ;
+ wire \u_riscv_top.dcache_mem_din0[29] ;
+ wire \u_riscv_top.dcache_mem_din0[2] ;
+ wire \u_riscv_top.dcache_mem_din0[30] ;
+ wire \u_riscv_top.dcache_mem_din0[31] ;
+ wire \u_riscv_top.dcache_mem_din0[3] ;
+ wire \u_riscv_top.dcache_mem_din0[4] ;
+ wire \u_riscv_top.dcache_mem_din0[5] ;
+ wire \u_riscv_top.dcache_mem_din0[6] ;
+ wire \u_riscv_top.dcache_mem_din0[7] ;
+ wire \u_riscv_top.dcache_mem_din0[8] ;
+ wire \u_riscv_top.dcache_mem_din0[9] ;
+ wire \u_riscv_top.dcache_mem_dout0[0] ;
+ wire \u_riscv_top.dcache_mem_dout0[10] ;
+ wire \u_riscv_top.dcache_mem_dout0[11] ;
+ wire \u_riscv_top.dcache_mem_dout0[12] ;
+ wire \u_riscv_top.dcache_mem_dout0[13] ;
+ wire \u_riscv_top.dcache_mem_dout0[14] ;
+ wire \u_riscv_top.dcache_mem_dout0[15] ;
+ wire \u_riscv_top.dcache_mem_dout0[16] ;
+ wire \u_riscv_top.dcache_mem_dout0[17] ;
+ wire \u_riscv_top.dcache_mem_dout0[18] ;
+ wire \u_riscv_top.dcache_mem_dout0[19] ;
+ wire \u_riscv_top.dcache_mem_dout0[1] ;
+ wire \u_riscv_top.dcache_mem_dout0[20] ;
+ wire \u_riscv_top.dcache_mem_dout0[21] ;
+ wire \u_riscv_top.dcache_mem_dout0[22] ;
+ wire \u_riscv_top.dcache_mem_dout0[23] ;
+ wire \u_riscv_top.dcache_mem_dout0[24] ;
+ wire \u_riscv_top.dcache_mem_dout0[25] ;
+ wire \u_riscv_top.dcache_mem_dout0[26] ;
+ wire \u_riscv_top.dcache_mem_dout0[27] ;
+ wire \u_riscv_top.dcache_mem_dout0[28] ;
+ wire \u_riscv_top.dcache_mem_dout0[29] ;
+ wire \u_riscv_top.dcache_mem_dout0[2] ;
+ wire \u_riscv_top.dcache_mem_dout0[30] ;
+ wire \u_riscv_top.dcache_mem_dout0[31] ;
+ wire \u_riscv_top.dcache_mem_dout0[3] ;
+ wire \u_riscv_top.dcache_mem_dout0[4] ;
+ wire \u_riscv_top.dcache_mem_dout0[5] ;
+ wire \u_riscv_top.dcache_mem_dout0[6] ;
+ wire \u_riscv_top.dcache_mem_dout0[7] ;
+ wire \u_riscv_top.dcache_mem_dout0[8] ;
+ wire \u_riscv_top.dcache_mem_dout0[9] ;
+ wire \u_riscv_top.dcache_mem_dout1[0] ;
+ wire \u_riscv_top.dcache_mem_dout1[10] ;
+ wire \u_riscv_top.dcache_mem_dout1[11] ;
+ wire \u_riscv_top.dcache_mem_dout1[12] ;
+ wire \u_riscv_top.dcache_mem_dout1[13] ;
+ wire \u_riscv_top.dcache_mem_dout1[14] ;
+ wire \u_riscv_top.dcache_mem_dout1[15] ;
+ wire \u_riscv_top.dcache_mem_dout1[16] ;
+ wire \u_riscv_top.dcache_mem_dout1[17] ;
+ wire \u_riscv_top.dcache_mem_dout1[18] ;
+ wire \u_riscv_top.dcache_mem_dout1[19] ;
+ wire \u_riscv_top.dcache_mem_dout1[1] ;
+ wire \u_riscv_top.dcache_mem_dout1[20] ;
+ wire \u_riscv_top.dcache_mem_dout1[21] ;
+ wire \u_riscv_top.dcache_mem_dout1[22] ;
+ wire \u_riscv_top.dcache_mem_dout1[23] ;
+ wire \u_riscv_top.dcache_mem_dout1[24] ;
+ wire \u_riscv_top.dcache_mem_dout1[25] ;
+ wire \u_riscv_top.dcache_mem_dout1[26] ;
+ wire \u_riscv_top.dcache_mem_dout1[27] ;
+ wire \u_riscv_top.dcache_mem_dout1[28] ;
+ wire \u_riscv_top.dcache_mem_dout1[29] ;
+ wire \u_riscv_top.dcache_mem_dout1[2] ;
+ wire \u_riscv_top.dcache_mem_dout1[30] ;
+ wire \u_riscv_top.dcache_mem_dout1[31] ;
+ wire \u_riscv_top.dcache_mem_dout1[3] ;
+ wire \u_riscv_top.dcache_mem_dout1[4] ;
+ wire \u_riscv_top.dcache_mem_dout1[5] ;
+ wire \u_riscv_top.dcache_mem_dout1[6] ;
+ wire \u_riscv_top.dcache_mem_dout1[7] ;
+ wire \u_riscv_top.dcache_mem_dout1[8] ;
+ wire \u_riscv_top.dcache_mem_dout1[9] ;
+ wire \u_riscv_top.dcache_mem_web0 ;
+ wire \u_riscv_top.dcache_mem_wmask0[0] ;
+ wire \u_riscv_top.dcache_mem_wmask0[1] ;
+ wire \u_riscv_top.dcache_mem_wmask0[2] ;
+ wire \u_riscv_top.dcache_mem_wmask0[3] ;
+ wire \u_riscv_top.icache_mem_addr0[0] ;
+ wire \u_riscv_top.icache_mem_addr0[1] ;
+ wire \u_riscv_top.icache_mem_addr0[2] ;
+ wire \u_riscv_top.icache_mem_addr0[3] ;
+ wire \u_riscv_top.icache_mem_addr0[4] ;
+ wire \u_riscv_top.icache_mem_addr0[5] ;
+ wire \u_riscv_top.icache_mem_addr0[6] ;
+ wire \u_riscv_top.icache_mem_addr0[7] ;
+ wire \u_riscv_top.icache_mem_addr0[8] ;
+ wire \u_riscv_top.icache_mem_addr1[0] ;
+ wire \u_riscv_top.icache_mem_addr1[1] ;
+ wire \u_riscv_top.icache_mem_addr1[2] ;
+ wire \u_riscv_top.icache_mem_addr1[3] ;
+ wire \u_riscv_top.icache_mem_addr1[4] ;
+ wire \u_riscv_top.icache_mem_addr1[5] ;
+ wire \u_riscv_top.icache_mem_addr1[6] ;
+ wire \u_riscv_top.icache_mem_addr1[7] ;
+ wire \u_riscv_top.icache_mem_addr1[8] ;
+ wire \u_riscv_top.icache_mem_clk0 ;
+ wire \u_riscv_top.icache_mem_clk1 ;
+ wire \u_riscv_top.icache_mem_csb0 ;
+ wire \u_riscv_top.icache_mem_csb1 ;
+ wire \u_riscv_top.icache_mem_din0[0] ;
+ wire \u_riscv_top.icache_mem_din0[10] ;
+ wire \u_riscv_top.icache_mem_din0[11] ;
+ wire \u_riscv_top.icache_mem_din0[12] ;
+ wire \u_riscv_top.icache_mem_din0[13] ;
+ wire \u_riscv_top.icache_mem_din0[14] ;
+ wire \u_riscv_top.icache_mem_din0[15] ;
+ wire \u_riscv_top.icache_mem_din0[16] ;
+ wire \u_riscv_top.icache_mem_din0[17] ;
+ wire \u_riscv_top.icache_mem_din0[18] ;
+ wire \u_riscv_top.icache_mem_din0[19] ;
+ wire \u_riscv_top.icache_mem_din0[1] ;
+ wire \u_riscv_top.icache_mem_din0[20] ;
+ wire \u_riscv_top.icache_mem_din0[21] ;
+ wire \u_riscv_top.icache_mem_din0[22] ;
+ wire \u_riscv_top.icache_mem_din0[23] ;
+ wire \u_riscv_top.icache_mem_din0[24] ;
+ wire \u_riscv_top.icache_mem_din0[25] ;
+ wire \u_riscv_top.icache_mem_din0[26] ;
+ wire \u_riscv_top.icache_mem_din0[27] ;
+ wire \u_riscv_top.icache_mem_din0[28] ;
+ wire \u_riscv_top.icache_mem_din0[29] ;
+ wire \u_riscv_top.icache_mem_din0[2] ;
+ wire \u_riscv_top.icache_mem_din0[30] ;
+ wire \u_riscv_top.icache_mem_din0[31] ;
+ wire \u_riscv_top.icache_mem_din0[3] ;
+ wire \u_riscv_top.icache_mem_din0[4] ;
+ wire \u_riscv_top.icache_mem_din0[5] ;
+ wire \u_riscv_top.icache_mem_din0[6] ;
+ wire \u_riscv_top.icache_mem_din0[7] ;
+ wire \u_riscv_top.icache_mem_din0[8] ;
+ wire \u_riscv_top.icache_mem_din0[9] ;
+ wire \u_riscv_top.icache_mem_dout1[0] ;
+ wire \u_riscv_top.icache_mem_dout1[10] ;
+ wire \u_riscv_top.icache_mem_dout1[11] ;
+ wire \u_riscv_top.icache_mem_dout1[12] ;
+ wire \u_riscv_top.icache_mem_dout1[13] ;
+ wire \u_riscv_top.icache_mem_dout1[14] ;
+ wire \u_riscv_top.icache_mem_dout1[15] ;
+ wire \u_riscv_top.icache_mem_dout1[16] ;
+ wire \u_riscv_top.icache_mem_dout1[17] ;
+ wire \u_riscv_top.icache_mem_dout1[18] ;
+ wire \u_riscv_top.icache_mem_dout1[19] ;
+ wire \u_riscv_top.icache_mem_dout1[1] ;
+ wire \u_riscv_top.icache_mem_dout1[20] ;
+ wire \u_riscv_top.icache_mem_dout1[21] ;
+ wire \u_riscv_top.icache_mem_dout1[22] ;
+ wire \u_riscv_top.icache_mem_dout1[23] ;
+ wire \u_riscv_top.icache_mem_dout1[24] ;
+ wire \u_riscv_top.icache_mem_dout1[25] ;
+ wire \u_riscv_top.icache_mem_dout1[26] ;
+ wire \u_riscv_top.icache_mem_dout1[27] ;
+ wire \u_riscv_top.icache_mem_dout1[28] ;
+ wire \u_riscv_top.icache_mem_dout1[29] ;
+ wire \u_riscv_top.icache_mem_dout1[2] ;
+ wire \u_riscv_top.icache_mem_dout1[30] ;
+ wire \u_riscv_top.icache_mem_dout1[31] ;
+ wire \u_riscv_top.icache_mem_dout1[3] ;
+ wire \u_riscv_top.icache_mem_dout1[4] ;
+ wire \u_riscv_top.icache_mem_dout1[5] ;
+ wire \u_riscv_top.icache_mem_dout1[6] ;
+ wire \u_riscv_top.icache_mem_dout1[7] ;
+ wire \u_riscv_top.icache_mem_dout1[8] ;
+ wire \u_riscv_top.icache_mem_dout1[9] ;
+ wire \u_riscv_top.icache_mem_web0 ;
+ wire \u_riscv_top.icache_mem_wmask0[0] ;
+ wire \u_riscv_top.icache_mem_wmask0[1] ;
+ wire \u_riscv_top.icache_mem_wmask0[2] ;
+ wire \u_riscv_top.icache_mem_wmask0[3] ;
+ wire \u_riscv_top.irq_lines[0] ;
+ wire \u_riscv_top.irq_lines[10] ;
+ wire \u_riscv_top.irq_lines[11] ;
+ wire \u_riscv_top.irq_lines[12] ;
+ wire \u_riscv_top.irq_lines[13] ;
+ wire \u_riscv_top.irq_lines[14] ;
+ wire \u_riscv_top.irq_lines[15] ;
+ wire \u_riscv_top.irq_lines[16] ;
+ wire \u_riscv_top.irq_lines[17] ;
+ wire \u_riscv_top.irq_lines[18] ;
+ wire \u_riscv_top.irq_lines[19] ;
+ wire \u_riscv_top.irq_lines[1] ;
+ wire \u_riscv_top.irq_lines[20] ;
+ wire \u_riscv_top.irq_lines[21] ;
+ wire \u_riscv_top.irq_lines[22] ;
+ wire \u_riscv_top.irq_lines[23] ;
+ wire \u_riscv_top.irq_lines[24] ;
+ wire \u_riscv_top.irq_lines[25] ;
+ wire \u_riscv_top.irq_lines[26] ;
+ wire \u_riscv_top.irq_lines[27] ;
+ wire \u_riscv_top.irq_lines[28] ;
+ wire \u_riscv_top.irq_lines[29] ;
+ wire \u_riscv_top.irq_lines[2] ;
+ wire \u_riscv_top.irq_lines[30] ;
+ wire \u_riscv_top.irq_lines[31] ;
+ wire \u_riscv_top.irq_lines[3] ;
+ wire \u_riscv_top.irq_lines[4] ;
+ wire \u_riscv_top.irq_lines[5] ;
+ wire \u_riscv_top.irq_lines[6] ;
+ wire \u_riscv_top.irq_lines[7] ;
+ wire \u_riscv_top.irq_lines[8] ;
+ wire \u_riscv_top.irq_lines[9] ;
+ wire \u_riscv_top.pwrup_rst_n ;
+ wire \u_riscv_top.rtc_clk ;
+ wire \u_riscv_top.soft_irq ;
+ wire \u_riscv_top.sram0_addr0[0] ;
+ wire \u_riscv_top.sram0_addr0[1] ;
+ wire \u_riscv_top.sram0_addr0[2] ;
+ wire \u_riscv_top.sram0_addr0[3] ;
+ wire \u_riscv_top.sram0_addr0[4] ;
+ wire \u_riscv_top.sram0_addr0[5] ;
+ wire \u_riscv_top.sram0_addr0[6] ;
+ wire \u_riscv_top.sram0_addr0[7] ;
+ wire \u_riscv_top.sram0_addr0[8] ;
+ wire \u_riscv_top.sram0_addr1[0] ;
+ wire \u_riscv_top.sram0_addr1[1] ;
+ wire \u_riscv_top.sram0_addr1[2] ;
+ wire \u_riscv_top.sram0_addr1[3] ;
+ wire \u_riscv_top.sram0_addr1[4] ;
+ wire \u_riscv_top.sram0_addr1[5] ;
+ wire \u_riscv_top.sram0_addr1[6] ;
+ wire \u_riscv_top.sram0_addr1[7] ;
+ wire \u_riscv_top.sram0_addr1[8] ;
+ wire \u_riscv_top.sram0_clk0 ;
+ wire \u_riscv_top.sram0_clk1 ;
+ wire \u_riscv_top.sram0_csb0 ;
+ wire \u_riscv_top.sram0_csb1 ;
+ wire \u_riscv_top.sram0_din0[0] ;
+ wire \u_riscv_top.sram0_din0[10] ;
+ wire \u_riscv_top.sram0_din0[11] ;
+ wire \u_riscv_top.sram0_din0[12] ;
+ wire \u_riscv_top.sram0_din0[13] ;
+ wire \u_riscv_top.sram0_din0[14] ;
+ wire \u_riscv_top.sram0_din0[15] ;
+ wire \u_riscv_top.sram0_din0[16] ;
+ wire \u_riscv_top.sram0_din0[17] ;
+ wire \u_riscv_top.sram0_din0[18] ;
+ wire \u_riscv_top.sram0_din0[19] ;
+ wire \u_riscv_top.sram0_din0[1] ;
+ wire \u_riscv_top.sram0_din0[20] ;
+ wire \u_riscv_top.sram0_din0[21] ;
+ wire \u_riscv_top.sram0_din0[22] ;
+ wire \u_riscv_top.sram0_din0[23] ;
+ wire \u_riscv_top.sram0_din0[24] ;
+ wire \u_riscv_top.sram0_din0[25] ;
+ wire \u_riscv_top.sram0_din0[26] ;
+ wire \u_riscv_top.sram0_din0[27] ;
+ wire \u_riscv_top.sram0_din0[28] ;
+ wire \u_riscv_top.sram0_din0[29] ;
+ wire \u_riscv_top.sram0_din0[2] ;
+ wire \u_riscv_top.sram0_din0[30] ;
+ wire \u_riscv_top.sram0_din0[31] ;
+ wire \u_riscv_top.sram0_din0[3] ;
+ wire \u_riscv_top.sram0_din0[4] ;
+ wire \u_riscv_top.sram0_din0[5] ;
+ wire \u_riscv_top.sram0_din0[6] ;
+ wire \u_riscv_top.sram0_din0[7] ;
+ wire \u_riscv_top.sram0_din0[8] ;
+ wire \u_riscv_top.sram0_din0[9] ;
+ wire \u_riscv_top.sram0_dout0[0] ;
+ wire \u_riscv_top.sram0_dout0[10] ;
+ wire \u_riscv_top.sram0_dout0[11] ;
+ wire \u_riscv_top.sram0_dout0[12] ;
+ wire \u_riscv_top.sram0_dout0[13] ;
+ wire \u_riscv_top.sram0_dout0[14] ;
+ wire \u_riscv_top.sram0_dout0[15] ;
+ wire \u_riscv_top.sram0_dout0[16] ;
+ wire \u_riscv_top.sram0_dout0[17] ;
+ wire \u_riscv_top.sram0_dout0[18] ;
+ wire \u_riscv_top.sram0_dout0[19] ;
+ wire \u_riscv_top.sram0_dout0[1] ;
+ wire \u_riscv_top.sram0_dout0[20] ;
+ wire \u_riscv_top.sram0_dout0[21] ;
+ wire \u_riscv_top.sram0_dout0[22] ;
+ wire \u_riscv_top.sram0_dout0[23] ;
+ wire \u_riscv_top.sram0_dout0[24] ;
+ wire \u_riscv_top.sram0_dout0[25] ;
+ wire \u_riscv_top.sram0_dout0[26] ;
+ wire \u_riscv_top.sram0_dout0[27] ;
+ wire \u_riscv_top.sram0_dout0[28] ;
+ wire \u_riscv_top.sram0_dout0[29] ;
+ wire \u_riscv_top.sram0_dout0[2] ;
+ wire \u_riscv_top.sram0_dout0[30] ;
+ wire \u_riscv_top.sram0_dout0[31] ;
+ wire \u_riscv_top.sram0_dout0[3] ;
+ wire \u_riscv_top.sram0_dout0[4] ;
+ wire \u_riscv_top.sram0_dout0[5] ;
+ wire \u_riscv_top.sram0_dout0[6] ;
+ wire \u_riscv_top.sram0_dout0[7] ;
+ wire \u_riscv_top.sram0_dout0[8] ;
+ wire \u_riscv_top.sram0_dout0[9] ;
+ wire \u_riscv_top.sram0_dout1[0] ;
+ wire \u_riscv_top.sram0_dout1[10] ;
+ wire \u_riscv_top.sram0_dout1[11] ;
+ wire \u_riscv_top.sram0_dout1[12] ;
+ wire \u_riscv_top.sram0_dout1[13] ;
+ wire \u_riscv_top.sram0_dout1[14] ;
+ wire \u_riscv_top.sram0_dout1[15] ;
+ wire \u_riscv_top.sram0_dout1[16] ;
+ wire \u_riscv_top.sram0_dout1[17] ;
+ wire \u_riscv_top.sram0_dout1[18] ;
+ wire \u_riscv_top.sram0_dout1[19] ;
+ wire \u_riscv_top.sram0_dout1[1] ;
+ wire \u_riscv_top.sram0_dout1[20] ;
+ wire \u_riscv_top.sram0_dout1[21] ;
+ wire \u_riscv_top.sram0_dout1[22] ;
+ wire \u_riscv_top.sram0_dout1[23] ;
+ wire \u_riscv_top.sram0_dout1[24] ;
+ wire \u_riscv_top.sram0_dout1[25] ;
+ wire \u_riscv_top.sram0_dout1[26] ;
+ wire \u_riscv_top.sram0_dout1[27] ;
+ wire \u_riscv_top.sram0_dout1[28] ;
+ wire \u_riscv_top.sram0_dout1[29] ;
+ wire \u_riscv_top.sram0_dout1[2] ;
+ wire \u_riscv_top.sram0_dout1[30] ;
+ wire \u_riscv_top.sram0_dout1[31] ;
+ wire \u_riscv_top.sram0_dout1[3] ;
+ wire \u_riscv_top.sram0_dout1[4] ;
+ wire \u_riscv_top.sram0_dout1[5] ;
+ wire \u_riscv_top.sram0_dout1[6] ;
+ wire \u_riscv_top.sram0_dout1[7] ;
+ wire \u_riscv_top.sram0_dout1[8] ;
+ wire \u_riscv_top.sram0_dout1[9] ;
+ wire \u_riscv_top.sram0_web0 ;
+ wire \u_riscv_top.sram0_wmask0[0] ;
+ wire \u_riscv_top.sram0_wmask0[1] ;
+ wire \u_riscv_top.sram0_wmask0[2] ;
+ wire \u_riscv_top.sram0_wmask0[3] ;
+ wire \u_riscv_top.wb_clk ;
+ wire \u_riscv_top.wb_dcache_ack_i ;
+ wire \u_riscv_top.wb_dcache_adr_o[0] ;
+ wire \u_riscv_top.wb_dcache_adr_o[10] ;
+ wire \u_riscv_top.wb_dcache_adr_o[11] ;
+ wire \u_riscv_top.wb_dcache_adr_o[12] ;
+ wire \u_riscv_top.wb_dcache_adr_o[13] ;
+ wire \u_riscv_top.wb_dcache_adr_o[14] ;
+ wire \u_riscv_top.wb_dcache_adr_o[15] ;
+ wire \u_riscv_top.wb_dcache_adr_o[16] ;
+ wire \u_riscv_top.wb_dcache_adr_o[17] ;
+ wire \u_riscv_top.wb_dcache_adr_o[18] ;
+ wire \u_riscv_top.wb_dcache_adr_o[19] ;
+ wire \u_riscv_top.wb_dcache_adr_o[1] ;
+ wire \u_riscv_top.wb_dcache_adr_o[20] ;
+ wire \u_riscv_top.wb_dcache_adr_o[21] ;
+ wire \u_riscv_top.wb_dcache_adr_o[22] ;
+ wire \u_riscv_top.wb_dcache_adr_o[23] ;
+ wire \u_riscv_top.wb_dcache_adr_o[24] ;
+ wire \u_riscv_top.wb_dcache_adr_o[25] ;
+ wire \u_riscv_top.wb_dcache_adr_o[26] ;
+ wire \u_riscv_top.wb_dcache_adr_o[27] ;
+ wire \u_riscv_top.wb_dcache_adr_o[28] ;
+ wire \u_riscv_top.wb_dcache_adr_o[29] ;
+ wire \u_riscv_top.wb_dcache_adr_o[2] ;
+ wire \u_riscv_top.wb_dcache_adr_o[30] ;
+ wire \u_riscv_top.wb_dcache_adr_o[31] ;
+ wire \u_riscv_top.wb_dcache_adr_o[3] ;
+ wire \u_riscv_top.wb_dcache_adr_o[4] ;
+ wire \u_riscv_top.wb_dcache_adr_o[5] ;
+ wire \u_riscv_top.wb_dcache_adr_o[6] ;
+ wire \u_riscv_top.wb_dcache_adr_o[7] ;
+ wire \u_riscv_top.wb_dcache_adr_o[8] ;
+ wire \u_riscv_top.wb_dcache_adr_o[9] ;
+ wire \u_riscv_top.wb_dcache_bl_o[0] ;
+ wire \u_riscv_top.wb_dcache_bl_o[1] ;
+ wire \u_riscv_top.wb_dcache_bl_o[2] ;
+ wire \u_riscv_top.wb_dcache_bl_o[3] ;
+ wire \u_riscv_top.wb_dcache_bl_o[4] ;
+ wire \u_riscv_top.wb_dcache_bl_o[5] ;
+ wire \u_riscv_top.wb_dcache_bl_o[6] ;
+ wire \u_riscv_top.wb_dcache_bl_o[7] ;
+ wire \u_riscv_top.wb_dcache_bl_o[8] ;
+ wire \u_riscv_top.wb_dcache_bl_o[9] ;
+ wire \u_riscv_top.wb_dcache_bry_o ;
+ wire \u_riscv_top.wb_dcache_cyc_o ;
+ wire \u_riscv_top.wb_dcache_dat_i[0] ;
+ wire \u_riscv_top.wb_dcache_dat_i[10] ;
+ wire \u_riscv_top.wb_dcache_dat_i[11] ;
+ wire \u_riscv_top.wb_dcache_dat_i[12] ;
+ wire \u_riscv_top.wb_dcache_dat_i[13] ;
+ wire \u_riscv_top.wb_dcache_dat_i[14] ;
+ wire \u_riscv_top.wb_dcache_dat_i[15] ;
+ wire \u_riscv_top.wb_dcache_dat_i[16] ;
+ wire \u_riscv_top.wb_dcache_dat_i[17] ;
+ wire \u_riscv_top.wb_dcache_dat_i[18] ;
+ wire \u_riscv_top.wb_dcache_dat_i[19] ;
+ wire \u_riscv_top.wb_dcache_dat_i[1] ;
+ wire \u_riscv_top.wb_dcache_dat_i[20] ;
+ wire \u_riscv_top.wb_dcache_dat_i[21] ;
+ wire \u_riscv_top.wb_dcache_dat_i[22] ;
+ wire \u_riscv_top.wb_dcache_dat_i[23] ;
+ wire \u_riscv_top.wb_dcache_dat_i[24] ;
+ wire \u_riscv_top.wb_dcache_dat_i[25] ;
+ wire \u_riscv_top.wb_dcache_dat_i[26] ;
+ wire \u_riscv_top.wb_dcache_dat_i[27] ;
+ wire \u_riscv_top.wb_dcache_dat_i[28] ;
+ wire \u_riscv_top.wb_dcache_dat_i[29] ;
+ wire \u_riscv_top.wb_dcache_dat_i[2] ;
+ wire \u_riscv_top.wb_dcache_dat_i[30] ;
+ wire \u_riscv_top.wb_dcache_dat_i[31] ;
+ wire \u_riscv_top.wb_dcache_dat_i[3] ;
+ wire \u_riscv_top.wb_dcache_dat_i[4] ;
+ wire \u_riscv_top.wb_dcache_dat_i[5] ;
+ wire \u_riscv_top.wb_dcache_dat_i[6] ;
+ wire \u_riscv_top.wb_dcache_dat_i[7] ;
+ wire \u_riscv_top.wb_dcache_dat_i[8] ;
+ wire \u_riscv_top.wb_dcache_dat_i[9] ;
+ wire \u_riscv_top.wb_dcache_dat_o[0] ;
+ wire \u_riscv_top.wb_dcache_dat_o[10] ;
+ wire \u_riscv_top.wb_dcache_dat_o[11] ;
+ wire \u_riscv_top.wb_dcache_dat_o[12] ;
+ wire \u_riscv_top.wb_dcache_dat_o[13] ;
+ wire \u_riscv_top.wb_dcache_dat_o[14] ;
+ wire \u_riscv_top.wb_dcache_dat_o[15] ;
+ wire \u_riscv_top.wb_dcache_dat_o[16] ;
+ wire \u_riscv_top.wb_dcache_dat_o[17] ;
+ wire \u_riscv_top.wb_dcache_dat_o[18] ;
+ wire \u_riscv_top.wb_dcache_dat_o[19] ;
+ wire \u_riscv_top.wb_dcache_dat_o[1] ;
+ wire \u_riscv_top.wb_dcache_dat_o[20] ;
+ wire \u_riscv_top.wb_dcache_dat_o[21] ;
+ wire \u_riscv_top.wb_dcache_dat_o[22] ;
+ wire \u_riscv_top.wb_dcache_dat_o[23] ;
+ wire \u_riscv_top.wb_dcache_dat_o[24] ;
+ wire \u_riscv_top.wb_dcache_dat_o[25] ;
+ wire \u_riscv_top.wb_dcache_dat_o[26] ;
+ wire \u_riscv_top.wb_dcache_dat_o[27] ;
+ wire \u_riscv_top.wb_dcache_dat_o[28] ;
+ wire \u_riscv_top.wb_dcache_dat_o[29] ;
+ wire \u_riscv_top.wb_dcache_dat_o[2] ;
+ wire \u_riscv_top.wb_dcache_dat_o[30] ;
+ wire \u_riscv_top.wb_dcache_dat_o[31] ;
+ wire \u_riscv_top.wb_dcache_dat_o[3] ;
+ wire \u_riscv_top.wb_dcache_dat_o[4] ;
+ wire \u_riscv_top.wb_dcache_dat_o[5] ;
+ wire \u_riscv_top.wb_dcache_dat_o[6] ;
+ wire \u_riscv_top.wb_dcache_dat_o[7] ;
+ wire \u_riscv_top.wb_dcache_dat_o[8] ;
+ wire \u_riscv_top.wb_dcache_dat_o[9] ;
+ wire \u_riscv_top.wb_dcache_err_i ;
+ wire \u_riscv_top.wb_dcache_lack_i ;
+ wire \u_riscv_top.wb_dcache_sel_o[0] ;
+ wire \u_riscv_top.wb_dcache_sel_o[1] ;
+ wire \u_riscv_top.wb_dcache_sel_o[2] ;
+ wire \u_riscv_top.wb_dcache_sel_o[3] ;
+ wire \u_riscv_top.wb_dcache_stb_o ;
+ wire \u_riscv_top.wb_dcache_we_o ;
+ wire \u_riscv_top.wb_icache_ack_i ;
+ wire \u_riscv_top.wb_icache_adr_o[0] ;
+ wire \u_riscv_top.wb_icache_adr_o[10] ;
+ wire \u_riscv_top.wb_icache_adr_o[11] ;
+ wire \u_riscv_top.wb_icache_adr_o[12] ;
+ wire \u_riscv_top.wb_icache_adr_o[13] ;
+ wire \u_riscv_top.wb_icache_adr_o[14] ;
+ wire \u_riscv_top.wb_icache_adr_o[15] ;
+ wire \u_riscv_top.wb_icache_adr_o[16] ;
+ wire \u_riscv_top.wb_icache_adr_o[17] ;
+ wire \u_riscv_top.wb_icache_adr_o[18] ;
+ wire \u_riscv_top.wb_icache_adr_o[19] ;
+ wire \u_riscv_top.wb_icache_adr_o[1] ;
+ wire \u_riscv_top.wb_icache_adr_o[20] ;
+ wire \u_riscv_top.wb_icache_adr_o[21] ;
+ wire \u_riscv_top.wb_icache_adr_o[22] ;
+ wire \u_riscv_top.wb_icache_adr_o[23] ;
+ wire \u_riscv_top.wb_icache_adr_o[24] ;
+ wire \u_riscv_top.wb_icache_adr_o[25] ;
+ wire \u_riscv_top.wb_icache_adr_o[26] ;
+ wire \u_riscv_top.wb_icache_adr_o[27] ;
+ wire \u_riscv_top.wb_icache_adr_o[28] ;
+ wire \u_riscv_top.wb_icache_adr_o[29] ;
+ wire \u_riscv_top.wb_icache_adr_o[2] ;
+ wire \u_riscv_top.wb_icache_adr_o[30] ;
+ wire \u_riscv_top.wb_icache_adr_o[31] ;
+ wire \u_riscv_top.wb_icache_adr_o[3] ;
+ wire \u_riscv_top.wb_icache_adr_o[4] ;
+ wire \u_riscv_top.wb_icache_adr_o[5] ;
+ wire \u_riscv_top.wb_icache_adr_o[6] ;
+ wire \u_riscv_top.wb_icache_adr_o[7] ;
+ wire \u_riscv_top.wb_icache_adr_o[8] ;
+ wire \u_riscv_top.wb_icache_adr_o[9] ;
+ wire \u_riscv_top.wb_icache_bl_o[0] ;
+ wire \u_riscv_top.wb_icache_bl_o[1] ;
+ wire \u_riscv_top.wb_icache_bl_o[2] ;
+ wire \u_riscv_top.wb_icache_bl_o[3] ;
+ wire \u_riscv_top.wb_icache_bl_o[4] ;
+ wire \u_riscv_top.wb_icache_bl_o[5] ;
+ wire \u_riscv_top.wb_icache_bl_o[6] ;
+ wire \u_riscv_top.wb_icache_bl_o[7] ;
+ wire \u_riscv_top.wb_icache_bl_o[8] ;
+ wire \u_riscv_top.wb_icache_bl_o[9] ;
+ wire \u_riscv_top.wb_icache_bry_o ;
+ wire \u_riscv_top.wb_icache_cyc_o ;
+ wire \u_riscv_top.wb_icache_dat_i[0] ;
+ wire \u_riscv_top.wb_icache_dat_i[10] ;
+ wire \u_riscv_top.wb_icache_dat_i[11] ;
+ wire \u_riscv_top.wb_icache_dat_i[12] ;
+ wire \u_riscv_top.wb_icache_dat_i[13] ;
+ wire \u_riscv_top.wb_icache_dat_i[14] ;
+ wire \u_riscv_top.wb_icache_dat_i[15] ;
+ wire \u_riscv_top.wb_icache_dat_i[16] ;
+ wire \u_riscv_top.wb_icache_dat_i[17] ;
+ wire \u_riscv_top.wb_icache_dat_i[18] ;
+ wire \u_riscv_top.wb_icache_dat_i[19] ;
+ wire \u_riscv_top.wb_icache_dat_i[1] ;
+ wire \u_riscv_top.wb_icache_dat_i[20] ;
+ wire \u_riscv_top.wb_icache_dat_i[21] ;
+ wire \u_riscv_top.wb_icache_dat_i[22] ;
+ wire \u_riscv_top.wb_icache_dat_i[23] ;
+ wire \u_riscv_top.wb_icache_dat_i[24] ;
+ wire \u_riscv_top.wb_icache_dat_i[25] ;
+ wire \u_riscv_top.wb_icache_dat_i[26] ;
+ wire \u_riscv_top.wb_icache_dat_i[27] ;
+ wire \u_riscv_top.wb_icache_dat_i[28] ;
+ wire \u_riscv_top.wb_icache_dat_i[29] ;
+ wire \u_riscv_top.wb_icache_dat_i[2] ;
+ wire \u_riscv_top.wb_icache_dat_i[30] ;
+ wire \u_riscv_top.wb_icache_dat_i[31] ;
+ wire \u_riscv_top.wb_icache_dat_i[3] ;
+ wire \u_riscv_top.wb_icache_dat_i[4] ;
+ wire \u_riscv_top.wb_icache_dat_i[5] ;
+ wire \u_riscv_top.wb_icache_dat_i[6] ;
+ wire \u_riscv_top.wb_icache_dat_i[7] ;
+ wire \u_riscv_top.wb_icache_dat_i[8] ;
+ wire \u_riscv_top.wb_icache_dat_i[9] ;
+ wire \u_riscv_top.wb_icache_err_i ;
+ wire \u_riscv_top.wb_icache_lack_i ;
+ wire \u_riscv_top.wb_icache_sel_o[0] ;
+ wire \u_riscv_top.wb_icache_sel_o[1] ;
+ wire \u_riscv_top.wb_icache_sel_o[2] ;
+ wire \u_riscv_top.wb_icache_sel_o[3] ;
+ wire \u_riscv_top.wb_icache_stb_o ;
+ wire \u_riscv_top.wb_icache_we_o ;
+ wire \u_riscv_top.wbd_clk_int ;
+ wire \u_riscv_top.wbd_dmem_ack_i ;
+ wire \u_riscv_top.wbd_dmem_adr_o[0] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[10] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[11] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[12] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[13] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[14] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[15] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[16] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[17] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[18] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[19] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[1] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[20] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[21] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[22] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[23] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[24] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[25] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[26] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[27] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[28] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[29] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[2] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[30] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[31] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[3] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[4] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[5] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[6] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[7] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[8] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[9] ;
+ wire \u_riscv_top.wbd_dmem_bl_o[0] ;
+ wire \u_riscv_top.wbd_dmem_bl_o[1] ;
+ wire \u_riscv_top.wbd_dmem_bl_o[2] ;
+ wire \u_riscv_top.wbd_dmem_bry_o ;
+ wire \u_riscv_top.wbd_dmem_dat_i[0] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[10] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[11] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[12] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[13] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[14] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[15] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[16] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[17] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[18] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[19] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[1] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[20] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[21] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[22] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[23] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[24] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[25] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[26] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[27] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[28] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[29] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[2] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[30] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[31] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[3] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[4] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[5] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[6] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[7] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[8] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[9] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[0] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[10] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[11] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[12] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[13] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[14] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[15] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[16] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[17] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[18] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[19] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[1] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[20] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[21] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[22] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[23] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[24] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[25] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[26] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[27] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[28] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[29] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[2] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[30] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[31] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[3] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[4] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[5] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[6] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[7] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[8] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[9] ;
+ wire \u_riscv_top.wbd_dmem_err_i ;
+ wire \u_riscv_top.wbd_dmem_lack_i ;
+ wire \u_riscv_top.wbd_dmem_sel_o[0] ;
+ wire \u_riscv_top.wbd_dmem_sel_o[1] ;
+ wire \u_riscv_top.wbd_dmem_sel_o[2] ;
+ wire \u_riscv_top.wbd_dmem_sel_o[3] ;
+ wire \u_riscv_top.wbd_dmem_stb_o ;
+ wire \u_riscv_top.wbd_dmem_we_o ;
+ wire \uart_rst_n[0] ;
+ wire \uart_rst_n[1] ;
+ wire \uart_rxd[0] ;
+ wire \uart_rxd[1] ;
+ wire \uart_txd[0] ;
+ wire \uart_txd[1] ;
+ wire uartm_rxd;
+ wire uartm_txd;
+ wire usb_clk;
+ wire usb_dn_i;
+ wire usb_dn_o;
+ wire usb_dp_i;
+ wire usb_dp_o;
+ wire usb_intr_o;
+ wire usb_oen;
+ wire usb_rst_n;
+ wire wbd_clk_int;
+ wire wbd_clk_pinmux_rp;
+ wire wbd_clk_pinmux_skew;
+ wire wbd_clk_qspi_rp;
+ wire wbd_clk_spi;
+ wire wbd_clk_uart_rp;
+ wire wbd_clk_uart_skew;
+ wire wbd_clk_wh;
+ wire wbd_clk_wi_skew;
+ wire wbd_glbl_ack_i;
+ wire \wbd_glbl_adr_o[0] ;
+ wire \wbd_glbl_adr_o[1] ;
+ wire \wbd_glbl_adr_o[2] ;
+ wire \wbd_glbl_adr_o[3] ;
+ wire \wbd_glbl_adr_o[4] ;
+ wire \wbd_glbl_adr_o[5] ;
+ wire \wbd_glbl_adr_o[6] ;
+ wire \wbd_glbl_adr_o[7] ;
+ wire \wbd_glbl_adr_o[8] ;
+ wire \wbd_glbl_adr_o[9] ;
+ wire wbd_glbl_cyc_o;
+ wire \wbd_glbl_dat_i[0] ;
+ wire \wbd_glbl_dat_i[10] ;
+ wire \wbd_glbl_dat_i[11] ;
+ wire \wbd_glbl_dat_i[12] ;
+ wire \wbd_glbl_dat_i[13] ;
+ wire \wbd_glbl_dat_i[14] ;
+ wire \wbd_glbl_dat_i[15] ;
+ wire \wbd_glbl_dat_i[16] ;
+ wire \wbd_glbl_dat_i[17] ;
+ wire \wbd_glbl_dat_i[18] ;
+ wire \wbd_glbl_dat_i[19] ;
+ wire \wbd_glbl_dat_i[1] ;
+ wire \wbd_glbl_dat_i[20] ;
+ wire \wbd_glbl_dat_i[21] ;
+ wire \wbd_glbl_dat_i[22] ;
+ wire \wbd_glbl_dat_i[23] ;
+ wire \wbd_glbl_dat_i[24] ;
+ wire \wbd_glbl_dat_i[25] ;
+ wire \wbd_glbl_dat_i[26] ;
+ wire \wbd_glbl_dat_i[27] ;
+ wire \wbd_glbl_dat_i[28] ;
+ wire \wbd_glbl_dat_i[29] ;
+ wire \wbd_glbl_dat_i[2] ;
+ wire \wbd_glbl_dat_i[30] ;
+ wire \wbd_glbl_dat_i[31] ;
+ wire \wbd_glbl_dat_i[3] ;
+ wire \wbd_glbl_dat_i[4] ;
+ wire \wbd_glbl_dat_i[5] ;
+ wire \wbd_glbl_dat_i[6] ;
+ wire \wbd_glbl_dat_i[7] ;
+ wire \wbd_glbl_dat_i[8] ;
+ wire \wbd_glbl_dat_i[9] ;
+ wire \wbd_glbl_dat_o[0] ;
+ wire \wbd_glbl_dat_o[10] ;
+ wire \wbd_glbl_dat_o[11] ;
+ wire \wbd_glbl_dat_o[12] ;
+ wire \wbd_glbl_dat_o[13] ;
+ wire \wbd_glbl_dat_o[14] ;
+ wire \wbd_glbl_dat_o[15] ;
+ wire \wbd_glbl_dat_o[16] ;
+ wire \wbd_glbl_dat_o[17] ;
+ wire \wbd_glbl_dat_o[18] ;
+ wire \wbd_glbl_dat_o[19] ;
+ wire \wbd_glbl_dat_o[1] ;
+ wire \wbd_glbl_dat_o[20] ;
+ wire \wbd_glbl_dat_o[21] ;
+ wire \wbd_glbl_dat_o[22] ;
+ wire \wbd_glbl_dat_o[23] ;
+ wire \wbd_glbl_dat_o[24] ;
+ wire \wbd_glbl_dat_o[25] ;
+ wire \wbd_glbl_dat_o[26] ;
+ wire \wbd_glbl_dat_o[27] ;
+ wire \wbd_glbl_dat_o[28] ;
+ wire \wbd_glbl_dat_o[29] ;
+ wire \wbd_glbl_dat_o[2] ;
+ wire \wbd_glbl_dat_o[30] ;
+ wire \wbd_glbl_dat_o[31] ;
+ wire \wbd_glbl_dat_o[3] ;
+ wire \wbd_glbl_dat_o[4] ;
+ wire \wbd_glbl_dat_o[5] ;
+ wire \wbd_glbl_dat_o[6] ;
+ wire \wbd_glbl_dat_o[7] ;
+ wire \wbd_glbl_dat_o[8] ;
+ wire \wbd_glbl_dat_o[9] ;
+ wire \wbd_glbl_sel_o[0] ;
+ wire \wbd_glbl_sel_o[1] ;
+ wire \wbd_glbl_sel_o[2] ;
+ wire \wbd_glbl_sel_o[3] ;
+ wire wbd_glbl_stb_o;
+ wire wbd_glbl_we_o;
+ wire wbd_int_ack_o;
+ wire \wbd_int_adr_i[0] ;
+ wire \wbd_int_adr_i[10] ;
+ wire \wbd_int_adr_i[11] ;
+ wire \wbd_int_adr_i[12] ;
+ wire \wbd_int_adr_i[13] ;
+ wire \wbd_int_adr_i[14] ;
+ wire \wbd_int_adr_i[15] ;
+ wire \wbd_int_adr_i[16] ;
+ wire \wbd_int_adr_i[17] ;
+ wire \wbd_int_adr_i[18] ;
+ wire \wbd_int_adr_i[19] ;
+ wire \wbd_int_adr_i[1] ;
+ wire \wbd_int_adr_i[20] ;
+ wire \wbd_int_adr_i[21] ;
+ wire \wbd_int_adr_i[22] ;
+ wire \wbd_int_adr_i[23] ;
+ wire \wbd_int_adr_i[24] ;
+ wire \wbd_int_adr_i[25] ;
+ wire \wbd_int_adr_i[26] ;
+ wire \wbd_int_adr_i[27] ;
+ wire \wbd_int_adr_i[28] ;
+ wire \wbd_int_adr_i[29] ;
+ wire \wbd_int_adr_i[2] ;
+ wire \wbd_int_adr_i[30] ;
+ wire \wbd_int_adr_i[31] ;
+ wire \wbd_int_adr_i[3] ;
+ wire \wbd_int_adr_i[4] ;
+ wire \wbd_int_adr_i[5] ;
+ wire \wbd_int_adr_i[6] ;
+ wire \wbd_int_adr_i[7] ;
+ wire \wbd_int_adr_i[8] ;
+ wire \wbd_int_adr_i[9] ;
+ wire wbd_int_cyc_i;
+ wire \wbd_int_dat_i[0] ;
+ wire \wbd_int_dat_i[10] ;
+ wire \wbd_int_dat_i[11] ;
+ wire \wbd_int_dat_i[12] ;
+ wire \wbd_int_dat_i[13] ;
+ wire \wbd_int_dat_i[14] ;
+ wire \wbd_int_dat_i[15] ;
+ wire \wbd_int_dat_i[16] ;
+ wire \wbd_int_dat_i[17] ;
+ wire \wbd_int_dat_i[18] ;
+ wire \wbd_int_dat_i[19] ;
+ wire \wbd_int_dat_i[1] ;
+ wire \wbd_int_dat_i[20] ;
+ wire \wbd_int_dat_i[21] ;
+ wire \wbd_int_dat_i[22] ;
+ wire \wbd_int_dat_i[23] ;
+ wire \wbd_int_dat_i[24] ;
+ wire \wbd_int_dat_i[25] ;
+ wire \wbd_int_dat_i[26] ;
+ wire \wbd_int_dat_i[27] ;
+ wire \wbd_int_dat_i[28] ;
+ wire \wbd_int_dat_i[29] ;
+ wire \wbd_int_dat_i[2] ;
+ wire \wbd_int_dat_i[30] ;
+ wire \wbd_int_dat_i[31] ;
+ wire \wbd_int_dat_i[3] ;
+ wire \wbd_int_dat_i[4] ;
+ wire \wbd_int_dat_i[5] ;
+ wire \wbd_int_dat_i[6] ;
+ wire \wbd_int_dat_i[7] ;
+ wire \wbd_int_dat_i[8] ;
+ wire \wbd_int_dat_i[9] ;
+ wire \wbd_int_dat_o[0] ;
+ wire \wbd_int_dat_o[10] ;
+ wire \wbd_int_dat_o[11] ;
+ wire \wbd_int_dat_o[12] ;
+ wire \wbd_int_dat_o[13] ;
+ wire \wbd_int_dat_o[14] ;
+ wire \wbd_int_dat_o[15] ;
+ wire \wbd_int_dat_o[16] ;
+ wire \wbd_int_dat_o[17] ;
+ wire \wbd_int_dat_o[18] ;
+ wire \wbd_int_dat_o[19] ;
+ wire \wbd_int_dat_o[1] ;
+ wire \wbd_int_dat_o[20] ;
+ wire \wbd_int_dat_o[21] ;
+ wire \wbd_int_dat_o[22] ;
+ wire \wbd_int_dat_o[23] ;
+ wire \wbd_int_dat_o[24] ;
+ wire \wbd_int_dat_o[25] ;
+ wire \wbd_int_dat_o[26] ;
+ wire \wbd_int_dat_o[27] ;
+ wire \wbd_int_dat_o[28] ;
+ wire \wbd_int_dat_o[29] ;
+ wire \wbd_int_dat_o[2] ;
+ wire \wbd_int_dat_o[30] ;
+ wire \wbd_int_dat_o[31] ;
+ wire \wbd_int_dat_o[3] ;
+ wire \wbd_int_dat_o[4] ;
+ wire \wbd_int_dat_o[5] ;
+ wire \wbd_int_dat_o[6] ;
+ wire \wbd_int_dat_o[7] ;
+ wire \wbd_int_dat_o[8] ;
+ wire \wbd_int_dat_o[9] ;
+ wire wbd_int_err_o;
+ wire \wbd_int_sel_i[0] ;
+ wire \wbd_int_sel_i[1] ;
+ wire \wbd_int_sel_i[2] ;
+ wire \wbd_int_sel_i[3] ;
+ wire wbd_int_stb_i;
+ wire wbd_int_we_i;
+ wire wbd_pll_rst_n;
+ wire wbd_spim_ack_i;
+ wire \wbd_spim_adr_o[0] ;
+ wire \wbd_spim_adr_o[10] ;
+ wire \wbd_spim_adr_o[11] ;
+ wire \wbd_spim_adr_o[12] ;
+ wire \wbd_spim_adr_o[13] ;
+ wire \wbd_spim_adr_o[14] ;
+ wire \wbd_spim_adr_o[15] ;
+ wire \wbd_spim_adr_o[16] ;
+ wire \wbd_spim_adr_o[17] ;
+ wire \wbd_spim_adr_o[18] ;
+ wire \wbd_spim_adr_o[19] ;
+ wire \wbd_spim_adr_o[1] ;
+ wire \wbd_spim_adr_o[20] ;
+ wire \wbd_spim_adr_o[21] ;
+ wire \wbd_spim_adr_o[22] ;
+ wire \wbd_spim_adr_o[23] ;
+ wire \wbd_spim_adr_o[24] ;
+ wire \wbd_spim_adr_o[25] ;
+ wire \wbd_spim_adr_o[26] ;
+ wire \wbd_spim_adr_o[27] ;
+ wire \wbd_spim_adr_o[28] ;
+ wire \wbd_spim_adr_o[29] ;
+ wire \wbd_spim_adr_o[2] ;
+ wire \wbd_spim_adr_o[30] ;
+ wire \wbd_spim_adr_o[31] ;
+ wire \wbd_spim_adr_o[3] ;
+ wire \wbd_spim_adr_o[4] ;
+ wire \wbd_spim_adr_o[5] ;
+ wire \wbd_spim_adr_o[6] ;
+ wire \wbd_spim_adr_o[7] ;
+ wire \wbd_spim_adr_o[8] ;
+ wire \wbd_spim_adr_o[9] ;
+ wire \wbd_spim_bl_o[0] ;
+ wire \wbd_spim_bl_o[1] ;
+ wire \wbd_spim_bl_o[2] ;
+ wire \wbd_spim_bl_o[3] ;
+ wire \wbd_spim_bl_o[4] ;
+ wire \wbd_spim_bl_o[5] ;
+ wire \wbd_spim_bl_o[6] ;
+ wire \wbd_spim_bl_o[7] ;
+ wire \wbd_spim_bl_o[8] ;
+ wire \wbd_spim_bl_o[9] ;
+ wire wbd_spim_bry_o;
+ wire wbd_spim_cyc_o;
+ wire \wbd_spim_dat_i[0] ;
+ wire \wbd_spim_dat_i[10] ;
+ wire \wbd_spim_dat_i[11] ;
+ wire \wbd_spim_dat_i[12] ;
+ wire \wbd_spim_dat_i[13] ;
+ wire \wbd_spim_dat_i[14] ;
+ wire \wbd_spim_dat_i[15] ;
+ wire \wbd_spim_dat_i[16] ;
+ wire \wbd_spim_dat_i[17] ;
+ wire \wbd_spim_dat_i[18] ;
+ wire \wbd_spim_dat_i[19] ;
+ wire \wbd_spim_dat_i[1] ;
+ wire \wbd_spim_dat_i[20] ;
+ wire \wbd_spim_dat_i[21] ;
+ wire \wbd_spim_dat_i[22] ;
+ wire \wbd_spim_dat_i[23] ;
+ wire \wbd_spim_dat_i[24] ;
+ wire \wbd_spim_dat_i[25] ;
+ wire \wbd_spim_dat_i[26] ;
+ wire \wbd_spim_dat_i[27] ;
+ wire \wbd_spim_dat_i[28] ;
+ wire \wbd_spim_dat_i[29] ;
+ wire \wbd_spim_dat_i[2] ;
+ wire \wbd_spim_dat_i[30] ;
+ wire \wbd_spim_dat_i[31] ;
+ wire \wbd_spim_dat_i[3] ;
+ wire \wbd_spim_dat_i[4] ;
+ wire \wbd_spim_dat_i[5] ;
+ wire \wbd_spim_dat_i[6] ;
+ wire \wbd_spim_dat_i[7] ;
+ wire \wbd_spim_dat_i[8] ;
+ wire \wbd_spim_dat_i[9] ;
+ wire \wbd_spim_dat_o[0] ;
+ wire \wbd_spim_dat_o[10] ;
+ wire \wbd_spim_dat_o[11] ;
+ wire \wbd_spim_dat_o[12] ;
+ wire \wbd_spim_dat_o[13] ;
+ wire \wbd_spim_dat_o[14] ;
+ wire \wbd_spim_dat_o[15] ;
+ wire \wbd_spim_dat_o[16] ;
+ wire \wbd_spim_dat_o[17] ;
+ wire \wbd_spim_dat_o[18] ;
+ wire \wbd_spim_dat_o[19] ;
+ wire \wbd_spim_dat_o[1] ;
+ wire \wbd_spim_dat_o[20] ;
+ wire \wbd_spim_dat_o[21] ;
+ wire \wbd_spim_dat_o[22] ;
+ wire \wbd_spim_dat_o[23] ;
+ wire \wbd_spim_dat_o[24] ;
+ wire \wbd_spim_dat_o[25] ;
+ wire \wbd_spim_dat_o[26] ;
+ wire \wbd_spim_dat_o[27] ;
+ wire \wbd_spim_dat_o[28] ;
+ wire \wbd_spim_dat_o[29] ;
+ wire \wbd_spim_dat_o[2] ;
+ wire \wbd_spim_dat_o[30] ;
+ wire \wbd_spim_dat_o[31] ;
+ wire \wbd_spim_dat_o[3] ;
+ wire \wbd_spim_dat_o[4] ;
+ wire \wbd_spim_dat_o[5] ;
+ wire \wbd_spim_dat_o[6] ;
+ wire \wbd_spim_dat_o[7] ;
+ wire \wbd_spim_dat_o[8] ;
+ wire \wbd_spim_dat_o[9] ;
+ wire wbd_spim_err_i;
+ wire wbd_spim_lack_i;
+ wire \wbd_spim_sel_o[0] ;
+ wire \wbd_spim_sel_o[1] ;
+ wire \wbd_spim_sel_o[2] ;
+ wire \wbd_spim_sel_o[3] ;
+ wire wbd_spim_stb_o;
+ wire wbd_spim_we_o;
+ wire wbd_uart_ack_i;
+ wire \wbd_uart_adr_o[0] ;
+ wire \wbd_uart_adr_o[1] ;
+ wire \wbd_uart_adr_o[2] ;
+ wire \wbd_uart_adr_o[3] ;
+ wire \wbd_uart_adr_o[4] ;
+ wire \wbd_uart_adr_o[5] ;
+ wire \wbd_uart_adr_o[6] ;
+ wire \wbd_uart_adr_o[7] ;
+ wire \wbd_uart_adr_o[8] ;
+ wire wbd_uart_cyc_o;
+ wire \wbd_uart_dat_i[0] ;
+ wire \wbd_uart_dat_i[10] ;
+ wire \wbd_uart_dat_i[11] ;
+ wire \wbd_uart_dat_i[12] ;
+ wire \wbd_uart_dat_i[13] ;
+ wire \wbd_uart_dat_i[14] ;
+ wire \wbd_uart_dat_i[15] ;
+ wire \wbd_uart_dat_i[16] ;
+ wire \wbd_uart_dat_i[17] ;
+ wire \wbd_uart_dat_i[18] ;
+ wire \wbd_uart_dat_i[19] ;
+ wire \wbd_uart_dat_i[1] ;
+ wire \wbd_uart_dat_i[20] ;
+ wire \wbd_uart_dat_i[21] ;
+ wire \wbd_uart_dat_i[22] ;
+ wire \wbd_uart_dat_i[23] ;
+ wire \wbd_uart_dat_i[24] ;
+ wire \wbd_uart_dat_i[25] ;
+ wire \wbd_uart_dat_i[26] ;
+ wire \wbd_uart_dat_i[27] ;
+ wire \wbd_uart_dat_i[28] ;
+ wire \wbd_uart_dat_i[29] ;
+ wire \wbd_uart_dat_i[2] ;
+ wire \wbd_uart_dat_i[30] ;
+ wire \wbd_uart_dat_i[31] ;
+ wire \wbd_uart_dat_i[3] ;
+ wire \wbd_uart_dat_i[4] ;
+ wire \wbd_uart_dat_i[5] ;
+ wire \wbd_uart_dat_i[6] ;
+ wire \wbd_uart_dat_i[7] ;
+ wire \wbd_uart_dat_i[8] ;
+ wire \wbd_uart_dat_i[9] ;
+ wire \wbd_uart_dat_o[0] ;
+ wire \wbd_uart_dat_o[10] ;
+ wire \wbd_uart_dat_o[11] ;
+ wire \wbd_uart_dat_o[12] ;
+ wire \wbd_uart_dat_o[13] ;
+ wire \wbd_uart_dat_o[14] ;
+ wire \wbd_uart_dat_o[15] ;
+ wire \wbd_uart_dat_o[16] ;
+ wire \wbd_uart_dat_o[17] ;
+ wire \wbd_uart_dat_o[18] ;
+ wire \wbd_uart_dat_o[19] ;
+ wire \wbd_uart_dat_o[1] ;
+ wire \wbd_uart_dat_o[20] ;
+ wire \wbd_uart_dat_o[21] ;
+ wire \wbd_uart_dat_o[22] ;
+ wire \wbd_uart_dat_o[23] ;
+ wire \wbd_uart_dat_o[24] ;
+ wire \wbd_uart_dat_o[25] ;
+ wire \wbd_uart_dat_o[26] ;
+ wire \wbd_uart_dat_o[27] ;
+ wire \wbd_uart_dat_o[28] ;
+ wire \wbd_uart_dat_o[29] ;
+ wire \wbd_uart_dat_o[2] ;
+ wire \wbd_uart_dat_o[30] ;
+ wire \wbd_uart_dat_o[31] ;
+ wire \wbd_uart_dat_o[3] ;
+ wire \wbd_uart_dat_o[4] ;
+ wire \wbd_uart_dat_o[5] ;
+ wire \wbd_uart_dat_o[6] ;
+ wire \wbd_uart_dat_o[7] ;
+ wire \wbd_uart_dat_o[8] ;
+ wire \wbd_uart_dat_o[9] ;
+ wire \wbd_uart_sel_o[0] ;
+ wire \wbd_uart_sel_o[1] ;
+ wire \wbd_uart_sel_o[2] ;
+ wire \wbd_uart_sel_o[3] ;
+ wire wbd_uart_stb_o;
+ wire wbd_uart_we_o;
+ wire xtal_clk;
+
+ dac_top u_4x8bit_dac (.Vout0(analog_io[15]),
+    .Vout1(analog_io[16]),
+    .Vout2(analog_io[17]),
+    .Vout3(analog_io[18]),
+    .Vref(analog_io[23]),
+    .vccd1(vdda1),
+    .vssd1(vssa1),
+    .DIn0({\cfg_dac0_mux_sel[7] ,
+    \cfg_dac0_mux_sel[6] ,
+    \cfg_dac0_mux_sel[5] ,
+    \cfg_dac0_mux_sel[4] ,
+    \cfg_dac0_mux_sel[3] ,
+    \cfg_dac0_mux_sel[2] ,
+    \cfg_dac0_mux_sel[1] ,
+    \cfg_dac0_mux_sel[0] }),
+    .DIn1({\cfg_dac1_mux_sel[7] ,
+    \cfg_dac1_mux_sel[6] ,
+    \cfg_dac1_mux_sel[5] ,
+    \cfg_dac1_mux_sel[4] ,
+    \cfg_dac1_mux_sel[3] ,
+    \cfg_dac1_mux_sel[2] ,
+    \cfg_dac1_mux_sel[1] ,
+    \cfg_dac1_mux_sel[0] }),
+    .DIn2({\cfg_dac2_mux_sel[7] ,
+    \cfg_dac2_mux_sel[6] ,
+    \cfg_dac2_mux_sel[5] ,
+    \cfg_dac2_mux_sel[4] ,
+    \cfg_dac2_mux_sel[3] ,
+    \cfg_dac2_mux_sel[2] ,
+    \cfg_dac2_mux_sel[1] ,
+    \cfg_dac2_mux_sel[0] }),
+    .DIn3({\cfg_dac3_mux_sel[7] ,
+    \cfg_dac3_mux_sel[6] ,
+    \cfg_dac3_mux_sel[5] ,
+    \cfg_dac3_mux_sel[4] ,
+    \cfg_dac3_mux_sel[3] ,
+    \cfg_dac3_mux_sel[2] ,
+    \cfg_dac3_mux_sel[1] ,
+    \cfg_dac3_mux_sel[0] }));
+ sky130_sram_2kbyte_1rw1r_32x512_8 u_dcache_2kb (.csb0(\u_riscv_top.dcache_mem_csb0 ),
+    .csb1(\u_riscv_top.dcache_mem_csb1 ),
+    .web0(\u_riscv_top.dcache_mem_web0 ),
+    .clk0(\u_riscv_top.dcache_mem_clk0 ),
+    .clk1(\u_riscv_top.dcache_mem_clk1 ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .addr0({\u_riscv_top.dcache_mem_addr0[8] ,
+    \u_riscv_top.dcache_mem_addr0[7] ,
+    \u_riscv_top.dcache_mem_addr0[6] ,
+    \u_riscv_top.dcache_mem_addr0[5] ,
+    \u_riscv_top.dcache_mem_addr0[4] ,
+    \u_riscv_top.dcache_mem_addr0[3] ,
+    \u_riscv_top.dcache_mem_addr0[2] ,
+    \u_riscv_top.dcache_mem_addr0[1] ,
+    \u_riscv_top.dcache_mem_addr0[0] }),
+    .addr1({\u_riscv_top.dcache_mem_addr1[8] ,
+    \u_riscv_top.dcache_mem_addr1[7] ,
+    \u_riscv_top.dcache_mem_addr1[6] ,
+    \u_riscv_top.dcache_mem_addr1[5] ,
+    \u_riscv_top.dcache_mem_addr1[4] ,
+    \u_riscv_top.dcache_mem_addr1[3] ,
+    \u_riscv_top.dcache_mem_addr1[2] ,
+    \u_riscv_top.dcache_mem_addr1[1] ,
+    \u_riscv_top.dcache_mem_addr1[0] }),
+    .din0({\u_riscv_top.dcache_mem_din0[31] ,
+    \u_riscv_top.dcache_mem_din0[30] ,
+    \u_riscv_top.dcache_mem_din0[29] ,
+    \u_riscv_top.dcache_mem_din0[28] ,
+    \u_riscv_top.dcache_mem_din0[27] ,
+    \u_riscv_top.dcache_mem_din0[26] ,
+    \u_riscv_top.dcache_mem_din0[25] ,
+    \u_riscv_top.dcache_mem_din0[24] ,
+    \u_riscv_top.dcache_mem_din0[23] ,
+    \u_riscv_top.dcache_mem_din0[22] ,
+    \u_riscv_top.dcache_mem_din0[21] ,
+    \u_riscv_top.dcache_mem_din0[20] ,
+    \u_riscv_top.dcache_mem_din0[19] ,
+    \u_riscv_top.dcache_mem_din0[18] ,
+    \u_riscv_top.dcache_mem_din0[17] ,
+    \u_riscv_top.dcache_mem_din0[16] ,
+    \u_riscv_top.dcache_mem_din0[15] ,
+    \u_riscv_top.dcache_mem_din0[14] ,
+    \u_riscv_top.dcache_mem_din0[13] ,
+    \u_riscv_top.dcache_mem_din0[12] ,
+    \u_riscv_top.dcache_mem_din0[11] ,
+    \u_riscv_top.dcache_mem_din0[10] ,
+    \u_riscv_top.dcache_mem_din0[9] ,
+    \u_riscv_top.dcache_mem_din0[8] ,
+    \u_riscv_top.dcache_mem_din0[7] ,
+    \u_riscv_top.dcache_mem_din0[6] ,
+    \u_riscv_top.dcache_mem_din0[5] ,
+    \u_riscv_top.dcache_mem_din0[4] ,
+    \u_riscv_top.dcache_mem_din0[3] ,
+    \u_riscv_top.dcache_mem_din0[2] ,
+    \u_riscv_top.dcache_mem_din0[1] ,
+    \u_riscv_top.dcache_mem_din0[0] }),
+    .dout0({\u_riscv_top.dcache_mem_dout0[31] ,
+    \u_riscv_top.dcache_mem_dout0[30] ,
+    \u_riscv_top.dcache_mem_dout0[29] ,
+    \u_riscv_top.dcache_mem_dout0[28] ,
+    \u_riscv_top.dcache_mem_dout0[27] ,
+    \u_riscv_top.dcache_mem_dout0[26] ,
+    \u_riscv_top.dcache_mem_dout0[25] ,
+    \u_riscv_top.dcache_mem_dout0[24] ,
+    \u_riscv_top.dcache_mem_dout0[23] ,
+    \u_riscv_top.dcache_mem_dout0[22] ,
+    \u_riscv_top.dcache_mem_dout0[21] ,
+    \u_riscv_top.dcache_mem_dout0[20] ,
+    \u_riscv_top.dcache_mem_dout0[19] ,
+    \u_riscv_top.dcache_mem_dout0[18] ,
+    \u_riscv_top.dcache_mem_dout0[17] ,
+    \u_riscv_top.dcache_mem_dout0[16] ,
+    \u_riscv_top.dcache_mem_dout0[15] ,
+    \u_riscv_top.dcache_mem_dout0[14] ,
+    \u_riscv_top.dcache_mem_dout0[13] ,
+    \u_riscv_top.dcache_mem_dout0[12] ,
+    \u_riscv_top.dcache_mem_dout0[11] ,
+    \u_riscv_top.dcache_mem_dout0[10] ,
+    \u_riscv_top.dcache_mem_dout0[9] ,
+    \u_riscv_top.dcache_mem_dout0[8] ,
+    \u_riscv_top.dcache_mem_dout0[7] ,
+    \u_riscv_top.dcache_mem_dout0[6] ,
+    \u_riscv_top.dcache_mem_dout0[5] ,
+    \u_riscv_top.dcache_mem_dout0[4] ,
+    \u_riscv_top.dcache_mem_dout0[3] ,
+    \u_riscv_top.dcache_mem_dout0[2] ,
+    \u_riscv_top.dcache_mem_dout0[1] ,
+    \u_riscv_top.dcache_mem_dout0[0] }),
+    .dout1({\u_riscv_top.dcache_mem_dout1[31] ,
+    \u_riscv_top.dcache_mem_dout1[30] ,
+    \u_riscv_top.dcache_mem_dout1[29] ,
+    \u_riscv_top.dcache_mem_dout1[28] ,
+    \u_riscv_top.dcache_mem_dout1[27] ,
+    \u_riscv_top.dcache_mem_dout1[26] ,
+    \u_riscv_top.dcache_mem_dout1[25] ,
+    \u_riscv_top.dcache_mem_dout1[24] ,
+    \u_riscv_top.dcache_mem_dout1[23] ,
+    \u_riscv_top.dcache_mem_dout1[22] ,
+    \u_riscv_top.dcache_mem_dout1[21] ,
+    \u_riscv_top.dcache_mem_dout1[20] ,
+    \u_riscv_top.dcache_mem_dout1[19] ,
+    \u_riscv_top.dcache_mem_dout1[18] ,
+    \u_riscv_top.dcache_mem_dout1[17] ,
+    \u_riscv_top.dcache_mem_dout1[16] ,
+    \u_riscv_top.dcache_mem_dout1[15] ,
+    \u_riscv_top.dcache_mem_dout1[14] ,
+    \u_riscv_top.dcache_mem_dout1[13] ,
+    \u_riscv_top.dcache_mem_dout1[12] ,
+    \u_riscv_top.dcache_mem_dout1[11] ,
+    \u_riscv_top.dcache_mem_dout1[10] ,
+    \u_riscv_top.dcache_mem_dout1[9] ,
+    \u_riscv_top.dcache_mem_dout1[8] ,
+    \u_riscv_top.dcache_mem_dout1[7] ,
+    \u_riscv_top.dcache_mem_dout1[6] ,
+    \u_riscv_top.dcache_mem_dout1[5] ,
+    \u_riscv_top.dcache_mem_dout1[4] ,
+    \u_riscv_top.dcache_mem_dout1[3] ,
+    \u_riscv_top.dcache_mem_dout1[2] ,
+    \u_riscv_top.dcache_mem_dout1[1] ,
+    \u_riscv_top.dcache_mem_dout1[0] }),
+    .wmask0({\u_riscv_top.dcache_mem_wmask0[3] ,
+    \u_riscv_top.dcache_mem_wmask0[2] ,
+    \u_riscv_top.dcache_mem_wmask0[1] ,
+    \u_riscv_top.dcache_mem_wmask0[0] }));
+ sky130_sram_2kbyte_1rw1r_32x512_8 u_icache_2kb (.csb0(\u_riscv_top.icache_mem_csb0 ),
+    .csb1(\u_riscv_top.icache_mem_csb1 ),
+    .web0(\u_riscv_top.icache_mem_web0 ),
+    .clk0(\u_riscv_top.icache_mem_clk0 ),
+    .clk1(\u_riscv_top.icache_mem_clk1 ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .addr0({\u_riscv_top.icache_mem_addr0[8] ,
+    \u_riscv_top.icache_mem_addr0[7] ,
+    \u_riscv_top.icache_mem_addr0[6] ,
+    \u_riscv_top.icache_mem_addr0[5] ,
+    \u_riscv_top.icache_mem_addr0[4] ,
+    \u_riscv_top.icache_mem_addr0[3] ,
+    \u_riscv_top.icache_mem_addr0[2] ,
+    \u_riscv_top.icache_mem_addr0[1] ,
+    \u_riscv_top.icache_mem_addr0[0] }),
+    .addr1({\u_riscv_top.icache_mem_addr1[8] ,
+    \u_riscv_top.icache_mem_addr1[7] ,
+    \u_riscv_top.icache_mem_addr1[6] ,
+    \u_riscv_top.icache_mem_addr1[5] ,
+    \u_riscv_top.icache_mem_addr1[4] ,
+    \u_riscv_top.icache_mem_addr1[3] ,
+    \u_riscv_top.icache_mem_addr1[2] ,
+    \u_riscv_top.icache_mem_addr1[1] ,
+    \u_riscv_top.icache_mem_addr1[0] }),
+    .din0({\u_riscv_top.icache_mem_din0[31] ,
+    \u_riscv_top.icache_mem_din0[30] ,
+    \u_riscv_top.icache_mem_din0[29] ,
+    \u_riscv_top.icache_mem_din0[28] ,
+    \u_riscv_top.icache_mem_din0[27] ,
+    \u_riscv_top.icache_mem_din0[26] ,
+    \u_riscv_top.icache_mem_din0[25] ,
+    \u_riscv_top.icache_mem_din0[24] ,
+    \u_riscv_top.icache_mem_din0[23] ,
+    \u_riscv_top.icache_mem_din0[22] ,
+    \u_riscv_top.icache_mem_din0[21] ,
+    \u_riscv_top.icache_mem_din0[20] ,
+    \u_riscv_top.icache_mem_din0[19] ,
+    \u_riscv_top.icache_mem_din0[18] ,
+    \u_riscv_top.icache_mem_din0[17] ,
+    \u_riscv_top.icache_mem_din0[16] ,
+    \u_riscv_top.icache_mem_din0[15] ,
+    \u_riscv_top.icache_mem_din0[14] ,
+    \u_riscv_top.icache_mem_din0[13] ,
+    \u_riscv_top.icache_mem_din0[12] ,
+    \u_riscv_top.icache_mem_din0[11] ,
+    \u_riscv_top.icache_mem_din0[10] ,
+    \u_riscv_top.icache_mem_din0[9] ,
+    \u_riscv_top.icache_mem_din0[8] ,
+    \u_riscv_top.icache_mem_din0[7] ,
+    \u_riscv_top.icache_mem_din0[6] ,
+    \u_riscv_top.icache_mem_din0[5] ,
+    \u_riscv_top.icache_mem_din0[4] ,
+    \u_riscv_top.icache_mem_din0[3] ,
+    \u_riscv_top.icache_mem_din0[2] ,
+    \u_riscv_top.icache_mem_din0[1] ,
+    \u_riscv_top.icache_mem_din0[0] }),
+    .dout0({_NC1,
+    _NC2,
+    _NC3,
+    _NC4,
+    _NC5,
+    _NC6,
+    _NC7,
+    _NC8,
+    _NC9,
+    _NC10,
+    _NC11,
+    _NC12,
+    _NC13,
+    _NC14,
+    _NC15,
+    _NC16,
+    _NC17,
+    _NC18,
+    _NC19,
+    _NC20,
+    _NC21,
+    _NC22,
+    _NC23,
+    _NC24,
+    _NC25,
+    _NC26,
+    _NC27,
+    _NC28,
+    _NC29,
+    _NC30,
+    _NC31,
+    _NC32}),
+    .dout1({\u_riscv_top.icache_mem_dout1[31] ,
+    \u_riscv_top.icache_mem_dout1[30] ,
+    \u_riscv_top.icache_mem_dout1[29] ,
+    \u_riscv_top.icache_mem_dout1[28] ,
+    \u_riscv_top.icache_mem_dout1[27] ,
+    \u_riscv_top.icache_mem_dout1[26] ,
+    \u_riscv_top.icache_mem_dout1[25] ,
+    \u_riscv_top.icache_mem_dout1[24] ,
+    \u_riscv_top.icache_mem_dout1[23] ,
+    \u_riscv_top.icache_mem_dout1[22] ,
+    \u_riscv_top.icache_mem_dout1[21] ,
+    \u_riscv_top.icache_mem_dout1[20] ,
+    \u_riscv_top.icache_mem_dout1[19] ,
+    \u_riscv_top.icache_mem_dout1[18] ,
+    \u_riscv_top.icache_mem_dout1[17] ,
+    \u_riscv_top.icache_mem_dout1[16] ,
+    \u_riscv_top.icache_mem_dout1[15] ,
+    \u_riscv_top.icache_mem_dout1[14] ,
+    \u_riscv_top.icache_mem_dout1[13] ,
+    \u_riscv_top.icache_mem_dout1[12] ,
+    \u_riscv_top.icache_mem_dout1[11] ,
+    \u_riscv_top.icache_mem_dout1[10] ,
+    \u_riscv_top.icache_mem_dout1[9] ,
+    \u_riscv_top.icache_mem_dout1[8] ,
+    \u_riscv_top.icache_mem_dout1[7] ,
+    \u_riscv_top.icache_mem_dout1[6] ,
+    \u_riscv_top.icache_mem_dout1[5] ,
+    \u_riscv_top.icache_mem_dout1[4] ,
+    \u_riscv_top.icache_mem_dout1[3] ,
+    \u_riscv_top.icache_mem_dout1[2] ,
+    \u_riscv_top.icache_mem_dout1[1] ,
+    \u_riscv_top.icache_mem_dout1[0] }),
+    .wmask0({\u_riscv_top.icache_mem_wmask0[3] ,
+    \u_riscv_top.icache_mem_wmask0[2] ,
+    \u_riscv_top.icache_mem_wmask0[1] ,
+    \u_riscv_top.icache_mem_wmask0[0] }));
+ wb_interconnect u_intercon (.clk_i(wbd_clk_wi_skew),
+    .m0_wbd_ack_o(wbd_int_ack_o),
+    .m0_wbd_cyc_i(wbd_int_cyc_i),
+    .m0_wbd_err_o(wbd_int_err_o),
+    .m0_wbd_stb_i(wbd_int_stb_i),
+    .m0_wbd_we_i(wbd_int_we_i),
+    .m1_wbd_ack_o(\u_riscv_top.wbd_dmem_ack_i ),
+    .m1_wbd_bry_i(\u_riscv_top.wbd_dmem_bry_o ),
+    .m1_wbd_cyc_i(\u_riscv_top.wbd_dmem_stb_o ),
+    .m1_wbd_err_o(\u_riscv_top.wbd_dmem_err_i ),
+    .m1_wbd_lack_o(\u_riscv_top.wbd_dmem_lack_i ),
+    .m1_wbd_stb_i(\u_riscv_top.wbd_dmem_stb_o ),
+    .m1_wbd_we_i(\u_riscv_top.wbd_dmem_we_o ),
+    .m2_wbd_ack_o(\u_riscv_top.wb_dcache_ack_i ),
+    .m2_wbd_bry_i(\u_riscv_top.wb_dcache_bry_o ),
+    .m2_wbd_cyc_i(\u_riscv_top.wb_dcache_stb_o ),
+    .m2_wbd_err_o(\u_riscv_top.wb_dcache_err_i ),
+    .m2_wbd_lack_o(\u_riscv_top.wb_dcache_lack_i ),
+    .m2_wbd_stb_i(\u_riscv_top.wb_dcache_stb_o ),
+    .m2_wbd_we_i(\u_riscv_top.wb_dcache_we_o ),
+    .m3_wbd_ack_o(\u_riscv_top.wb_icache_ack_i ),
+    .m3_wbd_bry_i(\u_riscv_top.wb_icache_bry_o ),
+    .m3_wbd_cyc_i(\u_riscv_top.wb_icache_stb_o ),
+    .m3_wbd_err_o(\u_riscv_top.wb_icache_err_i ),
+    .m3_wbd_lack_o(\u_riscv_top.wb_icache_lack_i ),
+    .m3_wbd_stb_i(\u_riscv_top.wb_icache_stb_o ),
+    .m3_wbd_we_i(\u_riscv_top.wb_icache_we_o ),
+    .rst_n(\u_riscv_top.pwrup_rst_n ),
+    .s0_wbd_ack_i(wbd_spim_ack_i),
+    .s0_wbd_bry_o(wbd_spim_bry_o),
+    .s0_wbd_cyc_o(wbd_spim_cyc_o),
+    .s0_wbd_lack_i(wbd_spim_lack_i),
+    .s0_wbd_stb_o(wbd_spim_stb_o),
+    .s0_wbd_we_o(wbd_spim_we_o),
+    .s1_wbd_ack_i(wbd_uart_ack_i),
+    .s1_wbd_cyc_o(wbd_uart_cyc_o),
+    .s1_wbd_stb_o(wbd_uart_stb_o),
+    .s1_wbd_we_o(wbd_uart_we_o),
+    .s2_wbd_ack_i(wbd_glbl_ack_i),
+    .s2_wbd_cyc_o(wbd_glbl_cyc_o),
+    .s2_wbd_stb_o(wbd_glbl_stb_o),
+    .s2_wbd_we_o(wbd_glbl_we_o),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .wbd_clk_int(wbd_clk_int),
+    .wbd_clk_wi(wbd_clk_wi_skew),
+    .cfg_cska_wi({\cfg_clk_skew_ctrl1[3] ,
+    \cfg_clk_skew_ctrl1[2] ,
+    \cfg_clk_skew_ctrl1[1] ,
+    \cfg_clk_skew_ctrl1[0] }),
+    .ch_clk_in({cpu_clk,
+    cpu_clk,
+    cpu_clk,
+    wbd_clk_int,
+    wbd_clk_int,
+    wbd_clk_int,
+    wbd_clk_int}),
+    .ch_clk_out({\cpu_clk_rp[2] ,
+    \u_riscv_top.core_clk_int[1] ,
+    \u_riscv_top.core_clk_int[0] ,
+    wbd_clk_pinmux_rp,
+    wbd_clk_uart_rp,
+    wbd_clk_qspi_rp,
+    \u_riscv_top.wbd_clk_int }),
+    .ch_data_in({\cfg_clk_skew_ctrl2[31] ,
+    \cfg_clk_skew_ctrl2[30] ,
+    \cfg_clk_skew_ctrl2[29] ,
+    \cfg_clk_skew_ctrl2[28] ,
+    \cfg_clk_skew_ctrl2[27] ,
+    \cfg_clk_skew_ctrl2[26] ,
+    \cfg_clk_skew_ctrl2[25] ,
+    \cfg_clk_skew_ctrl2[24] ,
+    \strap_sticky[31] ,
+    \strap_sticky[30] ,
+    \strap_sticky[29] ,
+    \strap_sticky[28] ,
+    \strap_sticky[27] ,
+    \strap_sticky[26] ,
+    \strap_sticky[25] ,
+    \strap_sticky[24] ,
+    \strap_sticky[23] ,
+    \strap_sticky[22] ,
+    \strap_sticky[21] ,
+    \strap_sticky[20] ,
+    \strap_sticky[19] ,
+    \strap_sticky[18] ,
+    \strap_sticky[17] ,
+    \strap_sticky[16] ,
+    \strap_sticky[15] ,
+    \strap_sticky[14] ,
+    \strap_sticky[13] ,
+    \strap_sticky[12] ,
+    \strap_sticky[11] ,
+    \strap_sticky[10] ,
+    \strap_sticky[9] ,
+    \strap_sticky[8] ,
+    \strap_sticky[7] ,
+    \strap_sticky[6] ,
+    \strap_sticky[5] ,
+    \strap_sticky[4] ,
+    \strap_sticky[3] ,
+    \strap_sticky[2] ,
+    \strap_sticky[1] ,
+    \strap_sticky[0] ,
+    \strap_uartm[1] ,
+    \strap_uartm[0] ,
+    \system_strap[31] ,
+    \system_strap[30] ,
+    \system_strap[29] ,
+    \system_strap[28] ,
+    \system_strap[27] ,
+    \system_strap[26] ,
+    \system_strap[25] ,
+    \system_strap[24] ,
+    \system_strap[23] ,
+    \system_strap[22] ,
+    \system_strap[21] ,
+    \system_strap[20] ,
+    \system_strap[19] ,
+    \system_strap[18] ,
+    \system_strap[17] ,
+    \system_strap[16] ,
+    \system_strap[15] ,
+    \system_strap[14] ,
+    \system_strap[13] ,
+    \system_strap[12] ,
+    \system_strap[11] ,
+    \system_strap[10] ,
+    \system_strap[9] ,
+    \system_strap[8] ,
+    \system_strap[7] ,
+    \system_strap[6] ,
+    \system_strap[5] ,
+    \system_strap[4] ,
+    \system_strap[3] ,
+    \system_strap[2] ,
+    \system_strap[1] ,
+    \system_strap[0] ,
+    p_reset_n,
+    e_reset_n,
+    cfg_strap_pad_ctrl,
+    soft_irq,
+    \irq_lines[31] ,
+    \irq_lines[30] ,
+    \irq_lines[29] ,
+    \irq_lines[28] ,
+    \irq_lines[27] ,
+    \irq_lines[26] ,
+    \irq_lines[25] ,
+    \irq_lines[24] ,
+    \irq_lines[23] ,
+    \irq_lines[22] ,
+    \irq_lines[21] ,
+    \irq_lines[20] ,
+    \irq_lines[19] ,
+    \irq_lines[18] ,
+    \irq_lines[17] ,
+    \irq_lines[16] ,
+    \irq_lines[15] ,
+    \irq_lines[14] ,
+    \irq_lines[13] ,
+    \irq_lines[12] ,
+    \irq_lines[11] ,
+    \irq_lines[10] ,
+    \irq_lines[9] ,
+    \irq_lines[8] ,
+    \irq_lines[7] ,
+    \irq_lines[6] ,
+    \irq_lines[5] ,
+    \irq_lines[4] ,
+    \irq_lines[3] ,
+    \irq_lines[2] ,
+    \irq_lines[1] ,
+    \irq_lines[0] ,
+    \cfg_clk_skew_ctrl2[23] ,
+    \cfg_clk_skew_ctrl2[22] ,
+    \cfg_clk_skew_ctrl2[21] ,
+    \cfg_clk_skew_ctrl2[20] ,
+    \cfg_clk_skew_ctrl2[19] ,
+    \cfg_clk_skew_ctrl2[18] ,
+    \cfg_clk_skew_ctrl2[17] ,
+    \cfg_clk_skew_ctrl2[16] ,
+    \cfg_clk_skew_ctrl2[15] ,
+    \cfg_clk_skew_ctrl2[14] ,
+    \cfg_clk_skew_ctrl2[13] ,
+    \cfg_clk_skew_ctrl2[12] ,
+    \cfg_clk_skew_ctrl2[11] ,
+    \cfg_clk_skew_ctrl2[10] ,
+    \cfg_clk_skew_ctrl2[9] ,
+    \cfg_clk_skew_ctrl2[8] ,
+    \cfg_clk_skew_ctrl2[7] ,
+    \cfg_clk_skew_ctrl2[6] ,
+    \cfg_clk_skew_ctrl2[5] ,
+    \cfg_clk_skew_ctrl2[4] ,
+    \cfg_clk_skew_ctrl2[3] ,
+    \cfg_clk_skew_ctrl2[2] ,
+    \cfg_clk_skew_ctrl2[1] ,
+    \cfg_clk_skew_ctrl2[0] ,
+    \cfg_clk_skew_ctrl1[27] ,
+    \cfg_clk_skew_ctrl1[26] ,
+    \cfg_clk_skew_ctrl1[25] ,
+    \cfg_clk_skew_ctrl1[24] ,
+    \cfg_clk_skew_ctrl1[23] ,
+    \cfg_clk_skew_ctrl1[22] ,
+    \cfg_clk_skew_ctrl1[21] ,
+    \cfg_clk_skew_ctrl1[20] ,
+    \cfg_clk_skew_ctrl1[19] ,
+    \cfg_clk_skew_ctrl1[18] ,
+    \cfg_clk_skew_ctrl1[17] ,
+    \cfg_clk_skew_ctrl1[16] ,
+    \cfg_clk_skew_ctrl1[15] ,
+    \cfg_clk_skew_ctrl1[14] ,
+    \cfg_clk_skew_ctrl1[13] ,
+    \cfg_clk_skew_ctrl1[12] ,
+    \cfg_clk_skew_ctrl1[11] ,
+    \cfg_clk_skew_ctrl1[10] ,
+    \cfg_clk_skew_ctrl1[9] ,
+    \cfg_clk_skew_ctrl1[8] }),
+    .ch_data_out({\cfg_ccska_fpu_rp[3] ,
+    \cfg_ccska_fpu_rp[2] ,
+    \cfg_ccska_fpu_rp[1] ,
+    \cfg_ccska_fpu_rp[0] ,
+    \cfg_ccska_aes_rp[3] ,
+    \cfg_ccska_aes_rp[2] ,
+    \cfg_ccska_aes_rp[1] ,
+    \cfg_ccska_aes_rp[0] ,
+    \strap_sticky_rp[31] ,
+    \strap_sticky_rp[30] ,
+    \strap_sticky_rp[29] ,
+    \strap_sticky_rp[28] ,
+    \strap_sticky_rp[27] ,
+    \strap_sticky_rp[26] ,
+    \strap_sticky_rp[25] ,
+    \strap_sticky_rp[24] ,
+    \strap_sticky_rp[23] ,
+    \strap_sticky_rp[22] ,
+    \strap_sticky_rp[21] ,
+    \strap_sticky_rp[20] ,
+    \strap_sticky_rp[19] ,
+    \strap_sticky_rp[18] ,
+    \strap_sticky_rp[17] ,
+    \strap_sticky_rp[16] ,
+    \strap_sticky_rp[15] ,
+    \strap_sticky_rp[14] ,
+    \strap_sticky_rp[13] ,
+    \strap_sticky_rp[12] ,
+    \strap_sticky_rp[11] ,
+    \strap_sticky_rp[10] ,
+    \strap_sticky_rp[9] ,
+    \strap_sticky_rp[8] ,
+    \strap_sticky_rp[7] ,
+    \strap_sticky_rp[6] ,
+    \strap_sticky_rp[5] ,
+    \strap_sticky_rp[4] ,
+    \strap_sticky_rp[3] ,
+    \strap_sticky_rp[2] ,
+    \strap_sticky_rp[1] ,
+    \strap_sticky_rp[0] ,
+    \strap_uartm_rp[1] ,
+    \strap_uartm_rp[0] ,
+    \system_strap_rp[31] ,
+    \system_strap_rp[30] ,
+    \system_strap_rp[29] ,
+    \system_strap_rp[28] ,
+    \system_strap_rp[27] ,
+    \system_strap_rp[26] ,
+    \system_strap_rp[25] ,
+    \system_strap_rp[24] ,
+    \system_strap_rp[23] ,
+    \system_strap_rp[22] ,
+    \system_strap_rp[21] ,
+    \system_strap_rp[20] ,
+    \system_strap_rp[19] ,
+    \system_strap_rp[18] ,
+    \system_strap_rp[17] ,
+    \system_strap_rp[16] ,
+    \system_strap_rp[15] ,
+    \system_strap_rp[14] ,
+    \system_strap_rp[13] ,
+    \system_strap_rp[12] ,
+    \system_strap_rp[11] ,
+    \system_strap_rp[10] ,
+    \system_strap_rp[9] ,
+    \system_strap_rp[8] ,
+    \system_strap_rp[7] ,
+    \system_strap_rp[6] ,
+    \system_strap_rp[5] ,
+    \system_strap_rp[4] ,
+    \system_strap_rp[3] ,
+    \system_strap_rp[2] ,
+    \system_strap_rp[1] ,
+    \system_strap_rp[0] ,
+    p_reset_n_rp,
+    e_reset_n_rp,
+    cfg_strap_pad_ctrl_rp,
+    \u_riscv_top.soft_irq ,
+    \u_riscv_top.irq_lines[31] ,
+    \u_riscv_top.irq_lines[30] ,
+    \u_riscv_top.irq_lines[29] ,
+    \u_riscv_top.irq_lines[28] ,
+    \u_riscv_top.irq_lines[27] ,
+    \u_riscv_top.irq_lines[26] ,
+    \u_riscv_top.irq_lines[25] ,
+    \u_riscv_top.irq_lines[24] ,
+    \u_riscv_top.irq_lines[23] ,
+    \u_riscv_top.irq_lines[22] ,
+    \u_riscv_top.irq_lines[21] ,
+    \u_riscv_top.irq_lines[20] ,
+    \u_riscv_top.irq_lines[19] ,
+    \u_riscv_top.irq_lines[18] ,
+    \u_riscv_top.irq_lines[17] ,
+    \u_riscv_top.irq_lines[16] ,
+    \u_riscv_top.irq_lines[15] ,
+    \u_riscv_top.irq_lines[14] ,
+    \u_riscv_top.irq_lines[13] ,
+    \u_riscv_top.irq_lines[12] ,
+    \u_riscv_top.irq_lines[11] ,
+    \u_riscv_top.irq_lines[10] ,
+    \u_riscv_top.irq_lines[9] ,
+    \u_riscv_top.irq_lines[8] ,
+    \u_riscv_top.irq_lines[7] ,
+    \u_riscv_top.irq_lines[6] ,
+    \u_riscv_top.irq_lines[5] ,
+    \u_riscv_top.irq_lines[4] ,
+    \u_riscv_top.irq_lines[3] ,
+    \u_riscv_top.irq_lines[2] ,
+    \u_riscv_top.irq_lines[1] ,
+    \u_riscv_top.irq_lines[0] ,
+    \u_riscv_top.cfg_ccska_riscv_core3[3] ,
+    \u_riscv_top.cfg_ccska_riscv_core3[2] ,
+    \u_riscv_top.cfg_ccska_riscv_core3[1] ,
+    \u_riscv_top.cfg_ccska_riscv_core3[0] ,
+    \u_riscv_top.cfg_ccska_riscv_core2[3] ,
+    \u_riscv_top.cfg_ccska_riscv_core2[2] ,
+    \u_riscv_top.cfg_ccska_riscv_core2[1] ,
+    \u_riscv_top.cfg_ccska_riscv_core2[0] ,
+    \u_riscv_top.cfg_ccska_riscv_core1[3] ,
+    \u_riscv_top.cfg_ccska_riscv_core1[2] ,
+    \u_riscv_top.cfg_ccska_riscv_core1[1] ,
+    \u_riscv_top.cfg_ccska_riscv_core1[0] ,
+    \u_riscv_top.cfg_ccska_riscv_core0[3] ,
+    \u_riscv_top.cfg_ccska_riscv_core0[2] ,
+    \u_riscv_top.cfg_ccska_riscv_core0[1] ,
+    \u_riscv_top.cfg_ccska_riscv_core0[0] ,
+    \u_riscv_top.cfg_ccska_riscv_icon[3] ,
+    \u_riscv_top.cfg_ccska_riscv_icon[2] ,
+    \u_riscv_top.cfg_ccska_riscv_icon[1] ,
+    \u_riscv_top.cfg_ccska_riscv_icon[0] ,
+    \u_riscv_top.cfg_ccska_riscv_intf[3] ,
+    \u_riscv_top.cfg_ccska_riscv_intf[2] ,
+    \u_riscv_top.cfg_ccska_riscv_intf[1] ,
+    \u_riscv_top.cfg_ccska_riscv_intf[0] ,
+    \cfg_wcska_qspi_co_rp[3] ,
+    \cfg_wcska_qspi_co_rp[2] ,
+    \cfg_wcska_qspi_co_rp[1] ,
+    \cfg_wcska_qspi_co_rp[0] ,
+    \cfg_wcska_pinmux_rp[3] ,
+    \cfg_wcska_pinmux_rp[2] ,
+    \cfg_wcska_pinmux_rp[1] ,
+    \cfg_wcska_pinmux_rp[0] ,
+    \cfg_wcska_uart_rp[3] ,
+    \cfg_wcska_uart_rp[2] ,
+    \cfg_wcska_uart_rp[1] ,
+    \cfg_wcska_uart_rp[0] ,
+    \cfg_wcska_qspi_rp[3] ,
+    \cfg_wcska_qspi_rp[2] ,
+    \cfg_wcska_qspi_rp[1] ,
+    \cfg_wcska_qspi_rp[0] ,
+    \u_riscv_top.cfg_wcska_riscv_intf[3] ,
+    \u_riscv_top.cfg_wcska_riscv_intf[2] ,
+    \u_riscv_top.cfg_wcska_riscv_intf[1] ,
+    \u_riscv_top.cfg_wcska_riscv_intf[0] }),
+    .m0_wbd_adr_i({\wbd_int_adr_i[31] ,
+    \wbd_int_adr_i[30] ,
+    \wbd_int_adr_i[29] ,
+    \wbd_int_adr_i[28] ,
+    \wbd_int_adr_i[27] ,
+    \wbd_int_adr_i[26] ,
+    \wbd_int_adr_i[25] ,
+    \wbd_int_adr_i[24] ,
+    \wbd_int_adr_i[23] ,
+    \wbd_int_adr_i[22] ,
+    \wbd_int_adr_i[21] ,
+    \wbd_int_adr_i[20] ,
+    \wbd_int_adr_i[19] ,
+    \wbd_int_adr_i[18] ,
+    \wbd_int_adr_i[17] ,
+    \wbd_int_adr_i[16] ,
+    \wbd_int_adr_i[15] ,
+    \wbd_int_adr_i[14] ,
+    \wbd_int_adr_i[13] ,
+    \wbd_int_adr_i[12] ,
+    \wbd_int_adr_i[11] ,
+    \wbd_int_adr_i[10] ,
+    \wbd_int_adr_i[9] ,
+    \wbd_int_adr_i[8] ,
+    \wbd_int_adr_i[7] ,
+    \wbd_int_adr_i[6] ,
+    \wbd_int_adr_i[5] ,
+    \wbd_int_adr_i[4] ,
+    \wbd_int_adr_i[3] ,
+    \wbd_int_adr_i[2] ,
+    \wbd_int_adr_i[1] ,
+    \wbd_int_adr_i[0] }),
+    .m0_wbd_dat_i({\wbd_int_dat_i[31] ,
+    \wbd_int_dat_i[30] ,
+    \wbd_int_dat_i[29] ,
+    \wbd_int_dat_i[28] ,
+    \wbd_int_dat_i[27] ,
+    \wbd_int_dat_i[26] ,
+    \wbd_int_dat_i[25] ,
+    \wbd_int_dat_i[24] ,
+    \wbd_int_dat_i[23] ,
+    \wbd_int_dat_i[22] ,
+    \wbd_int_dat_i[21] ,
+    \wbd_int_dat_i[20] ,
+    \wbd_int_dat_i[19] ,
+    \wbd_int_dat_i[18] ,
+    \wbd_int_dat_i[17] ,
+    \wbd_int_dat_i[16] ,
+    \wbd_int_dat_i[15] ,
+    \wbd_int_dat_i[14] ,
+    \wbd_int_dat_i[13] ,
+    \wbd_int_dat_i[12] ,
+    \wbd_int_dat_i[11] ,
+    \wbd_int_dat_i[10] ,
+    \wbd_int_dat_i[9] ,
+    \wbd_int_dat_i[8] ,
+    \wbd_int_dat_i[7] ,
+    \wbd_int_dat_i[6] ,
+    \wbd_int_dat_i[5] ,
+    \wbd_int_dat_i[4] ,
+    \wbd_int_dat_i[3] ,
+    \wbd_int_dat_i[2] ,
+    \wbd_int_dat_i[1] ,
+    \wbd_int_dat_i[0] }),
+    .m0_wbd_dat_o({\wbd_int_dat_o[31] ,
+    \wbd_int_dat_o[30] ,
+    \wbd_int_dat_o[29] ,
+    \wbd_int_dat_o[28] ,
+    \wbd_int_dat_o[27] ,
+    \wbd_int_dat_o[26] ,
+    \wbd_int_dat_o[25] ,
+    \wbd_int_dat_o[24] ,
+    \wbd_int_dat_o[23] ,
+    \wbd_int_dat_o[22] ,
+    \wbd_int_dat_o[21] ,
+    \wbd_int_dat_o[20] ,
+    \wbd_int_dat_o[19] ,
+    \wbd_int_dat_o[18] ,
+    \wbd_int_dat_o[17] ,
+    \wbd_int_dat_o[16] ,
+    \wbd_int_dat_o[15] ,
+    \wbd_int_dat_o[14] ,
+    \wbd_int_dat_o[13] ,
+    \wbd_int_dat_o[12] ,
+    \wbd_int_dat_o[11] ,
+    \wbd_int_dat_o[10] ,
+    \wbd_int_dat_o[9] ,
+    \wbd_int_dat_o[8] ,
+    \wbd_int_dat_o[7] ,
+    \wbd_int_dat_o[6] ,
+    \wbd_int_dat_o[5] ,
+    \wbd_int_dat_o[4] ,
+    \wbd_int_dat_o[3] ,
+    \wbd_int_dat_o[2] ,
+    \wbd_int_dat_o[1] ,
+    \wbd_int_dat_o[0] }),
+    .m0_wbd_sel_i({\wbd_int_sel_i[3] ,
+    \wbd_int_sel_i[2] ,
+    \wbd_int_sel_i[1] ,
+    \wbd_int_sel_i[0] }),
+    .m1_wbd_adr_i({\u_riscv_top.wbd_dmem_adr_o[31] ,
+    \u_riscv_top.wbd_dmem_adr_o[30] ,
+    \u_riscv_top.wbd_dmem_adr_o[29] ,
+    \u_riscv_top.wbd_dmem_adr_o[28] ,
+    \u_riscv_top.wbd_dmem_adr_o[27] ,
+    \u_riscv_top.wbd_dmem_adr_o[26] ,
+    \u_riscv_top.wbd_dmem_adr_o[25] ,
+    \u_riscv_top.wbd_dmem_adr_o[24] ,
+    \u_riscv_top.wbd_dmem_adr_o[23] ,
+    \u_riscv_top.wbd_dmem_adr_o[22] ,
+    \u_riscv_top.wbd_dmem_adr_o[21] ,
+    \u_riscv_top.wbd_dmem_adr_o[20] ,
+    \u_riscv_top.wbd_dmem_adr_o[19] ,
+    \u_riscv_top.wbd_dmem_adr_o[18] ,
+    \u_riscv_top.wbd_dmem_adr_o[17] ,
+    \u_riscv_top.wbd_dmem_adr_o[16] ,
+    \u_riscv_top.wbd_dmem_adr_o[15] ,
+    \u_riscv_top.wbd_dmem_adr_o[14] ,
+    \u_riscv_top.wbd_dmem_adr_o[13] ,
+    \u_riscv_top.wbd_dmem_adr_o[12] ,
+    \u_riscv_top.wbd_dmem_adr_o[11] ,
+    \u_riscv_top.wbd_dmem_adr_o[10] ,
+    \u_riscv_top.wbd_dmem_adr_o[9] ,
+    \u_riscv_top.wbd_dmem_adr_o[8] ,
+    \u_riscv_top.wbd_dmem_adr_o[7] ,
+    \u_riscv_top.wbd_dmem_adr_o[6] ,
+    \u_riscv_top.wbd_dmem_adr_o[5] ,
+    \u_riscv_top.wbd_dmem_adr_o[4] ,
+    \u_riscv_top.wbd_dmem_adr_o[3] ,
+    \u_riscv_top.wbd_dmem_adr_o[2] ,
+    \u_riscv_top.wbd_dmem_adr_o[1] ,
+    \u_riscv_top.wbd_dmem_adr_o[0] }),
+    .m1_wbd_bl_i({\u_riscv_top.wbd_dmem_bl_o[2] ,
+    \u_riscv_top.wbd_dmem_bl_o[1] ,
+    \u_riscv_top.wbd_dmem_bl_o[0] }),
+    .m1_wbd_dat_i({\u_riscv_top.wbd_dmem_dat_o[31] ,
+    \u_riscv_top.wbd_dmem_dat_o[30] ,
+    \u_riscv_top.wbd_dmem_dat_o[29] ,
+    \u_riscv_top.wbd_dmem_dat_o[28] ,
+    \u_riscv_top.wbd_dmem_dat_o[27] ,
+    \u_riscv_top.wbd_dmem_dat_o[26] ,
+    \u_riscv_top.wbd_dmem_dat_o[25] ,
+    \u_riscv_top.wbd_dmem_dat_o[24] ,
+    \u_riscv_top.wbd_dmem_dat_o[23] ,
+    \u_riscv_top.wbd_dmem_dat_o[22] ,
+    \u_riscv_top.wbd_dmem_dat_o[21] ,
+    \u_riscv_top.wbd_dmem_dat_o[20] ,
+    \u_riscv_top.wbd_dmem_dat_o[19] ,
+    \u_riscv_top.wbd_dmem_dat_o[18] ,
+    \u_riscv_top.wbd_dmem_dat_o[17] ,
+    \u_riscv_top.wbd_dmem_dat_o[16] ,
+    \u_riscv_top.wbd_dmem_dat_o[15] ,
+    \u_riscv_top.wbd_dmem_dat_o[14] ,
+    \u_riscv_top.wbd_dmem_dat_o[13] ,
+    \u_riscv_top.wbd_dmem_dat_o[12] ,
+    \u_riscv_top.wbd_dmem_dat_o[11] ,
+    \u_riscv_top.wbd_dmem_dat_o[10] ,
+    \u_riscv_top.wbd_dmem_dat_o[9] ,
+    \u_riscv_top.wbd_dmem_dat_o[8] ,
+    \u_riscv_top.wbd_dmem_dat_o[7] ,
+    \u_riscv_top.wbd_dmem_dat_o[6] ,
+    \u_riscv_top.wbd_dmem_dat_o[5] ,
+    \u_riscv_top.wbd_dmem_dat_o[4] ,
+    \u_riscv_top.wbd_dmem_dat_o[3] ,
+    \u_riscv_top.wbd_dmem_dat_o[2] ,
+    \u_riscv_top.wbd_dmem_dat_o[1] ,
+    \u_riscv_top.wbd_dmem_dat_o[0] }),
+    .m1_wbd_dat_o({\u_riscv_top.wbd_dmem_dat_i[31] ,
+    \u_riscv_top.wbd_dmem_dat_i[30] ,
+    \u_riscv_top.wbd_dmem_dat_i[29] ,
+    \u_riscv_top.wbd_dmem_dat_i[28] ,
+    \u_riscv_top.wbd_dmem_dat_i[27] ,
+    \u_riscv_top.wbd_dmem_dat_i[26] ,
+    \u_riscv_top.wbd_dmem_dat_i[25] ,
+    \u_riscv_top.wbd_dmem_dat_i[24] ,
+    \u_riscv_top.wbd_dmem_dat_i[23] ,
+    \u_riscv_top.wbd_dmem_dat_i[22] ,
+    \u_riscv_top.wbd_dmem_dat_i[21] ,
+    \u_riscv_top.wbd_dmem_dat_i[20] ,
+    \u_riscv_top.wbd_dmem_dat_i[19] ,
+    \u_riscv_top.wbd_dmem_dat_i[18] ,
+    \u_riscv_top.wbd_dmem_dat_i[17] ,
+    \u_riscv_top.wbd_dmem_dat_i[16] ,
+    \u_riscv_top.wbd_dmem_dat_i[15] ,
+    \u_riscv_top.wbd_dmem_dat_i[14] ,
+    \u_riscv_top.wbd_dmem_dat_i[13] ,
+    \u_riscv_top.wbd_dmem_dat_i[12] ,
+    \u_riscv_top.wbd_dmem_dat_i[11] ,
+    \u_riscv_top.wbd_dmem_dat_i[10] ,
+    \u_riscv_top.wbd_dmem_dat_i[9] ,
+    \u_riscv_top.wbd_dmem_dat_i[8] ,
+    \u_riscv_top.wbd_dmem_dat_i[7] ,
+    \u_riscv_top.wbd_dmem_dat_i[6] ,
+    \u_riscv_top.wbd_dmem_dat_i[5] ,
+    \u_riscv_top.wbd_dmem_dat_i[4] ,
+    \u_riscv_top.wbd_dmem_dat_i[3] ,
+    \u_riscv_top.wbd_dmem_dat_i[2] ,
+    \u_riscv_top.wbd_dmem_dat_i[1] ,
+    \u_riscv_top.wbd_dmem_dat_i[0] }),
+    .m1_wbd_sel_i({\u_riscv_top.wbd_dmem_sel_o[3] ,
+    \u_riscv_top.wbd_dmem_sel_o[2] ,
+    \u_riscv_top.wbd_dmem_sel_o[1] ,
+    \u_riscv_top.wbd_dmem_sel_o[0] }),
+    .m2_wbd_adr_i({\u_riscv_top.wb_dcache_adr_o[31] ,
+    \u_riscv_top.wb_dcache_adr_o[30] ,
+    \u_riscv_top.wb_dcache_adr_o[29] ,
+    \u_riscv_top.wb_dcache_adr_o[28] ,
+    \u_riscv_top.wb_dcache_adr_o[27] ,
+    \u_riscv_top.wb_dcache_adr_o[26] ,
+    \u_riscv_top.wb_dcache_adr_o[25] ,
+    \u_riscv_top.wb_dcache_adr_o[24] ,
+    \u_riscv_top.wb_dcache_adr_o[23] ,
+    \u_riscv_top.wb_dcache_adr_o[22] ,
+    \u_riscv_top.wb_dcache_adr_o[21] ,
+    \u_riscv_top.wb_dcache_adr_o[20] ,
+    \u_riscv_top.wb_dcache_adr_o[19] ,
+    \u_riscv_top.wb_dcache_adr_o[18] ,
+    \u_riscv_top.wb_dcache_adr_o[17] ,
+    \u_riscv_top.wb_dcache_adr_o[16] ,
+    \u_riscv_top.wb_dcache_adr_o[15] ,
+    \u_riscv_top.wb_dcache_adr_o[14] ,
+    \u_riscv_top.wb_dcache_adr_o[13] ,
+    \u_riscv_top.wb_dcache_adr_o[12] ,
+    \u_riscv_top.wb_dcache_adr_o[11] ,
+    \u_riscv_top.wb_dcache_adr_o[10] ,
+    \u_riscv_top.wb_dcache_adr_o[9] ,
+    \u_riscv_top.wb_dcache_adr_o[8] ,
+    \u_riscv_top.wb_dcache_adr_o[7] ,
+    \u_riscv_top.wb_dcache_adr_o[6] ,
+    \u_riscv_top.wb_dcache_adr_o[5] ,
+    \u_riscv_top.wb_dcache_adr_o[4] ,
+    \u_riscv_top.wb_dcache_adr_o[3] ,
+    \u_riscv_top.wb_dcache_adr_o[2] ,
+    \u_riscv_top.wb_dcache_adr_o[1] ,
+    \u_riscv_top.wb_dcache_adr_o[0] }),
+    .m2_wbd_bl_i({\u_riscv_top.wb_dcache_bl_o[9] ,
+    \u_riscv_top.wb_dcache_bl_o[8] ,
+    \u_riscv_top.wb_dcache_bl_o[7] ,
+    \u_riscv_top.wb_dcache_bl_o[6] ,
+    \u_riscv_top.wb_dcache_bl_o[5] ,
+    \u_riscv_top.wb_dcache_bl_o[4] ,
+    \u_riscv_top.wb_dcache_bl_o[3] ,
+    \u_riscv_top.wb_dcache_bl_o[2] ,
+    \u_riscv_top.wb_dcache_bl_o[1] ,
+    \u_riscv_top.wb_dcache_bl_o[0] }),
+    .m2_wbd_dat_i({\u_riscv_top.wb_dcache_dat_o[31] ,
+    \u_riscv_top.wb_dcache_dat_o[30] ,
+    \u_riscv_top.wb_dcache_dat_o[29] ,
+    \u_riscv_top.wb_dcache_dat_o[28] ,
+    \u_riscv_top.wb_dcache_dat_o[27] ,
+    \u_riscv_top.wb_dcache_dat_o[26] ,
+    \u_riscv_top.wb_dcache_dat_o[25] ,
+    \u_riscv_top.wb_dcache_dat_o[24] ,
+    \u_riscv_top.wb_dcache_dat_o[23] ,
+    \u_riscv_top.wb_dcache_dat_o[22] ,
+    \u_riscv_top.wb_dcache_dat_o[21] ,
+    \u_riscv_top.wb_dcache_dat_o[20] ,
+    \u_riscv_top.wb_dcache_dat_o[19] ,
+    \u_riscv_top.wb_dcache_dat_o[18] ,
+    \u_riscv_top.wb_dcache_dat_o[17] ,
+    \u_riscv_top.wb_dcache_dat_o[16] ,
+    \u_riscv_top.wb_dcache_dat_o[15] ,
+    \u_riscv_top.wb_dcache_dat_o[14] ,
+    \u_riscv_top.wb_dcache_dat_o[13] ,
+    \u_riscv_top.wb_dcache_dat_o[12] ,
+    \u_riscv_top.wb_dcache_dat_o[11] ,
+    \u_riscv_top.wb_dcache_dat_o[10] ,
+    \u_riscv_top.wb_dcache_dat_o[9] ,
+    \u_riscv_top.wb_dcache_dat_o[8] ,
+    \u_riscv_top.wb_dcache_dat_o[7] ,
+    \u_riscv_top.wb_dcache_dat_o[6] ,
+    \u_riscv_top.wb_dcache_dat_o[5] ,
+    \u_riscv_top.wb_dcache_dat_o[4] ,
+    \u_riscv_top.wb_dcache_dat_o[3] ,
+    \u_riscv_top.wb_dcache_dat_o[2] ,
+    \u_riscv_top.wb_dcache_dat_o[1] ,
+    \u_riscv_top.wb_dcache_dat_o[0] }),
+    .m2_wbd_dat_o({\u_riscv_top.wb_dcache_dat_i[31] ,
+    \u_riscv_top.wb_dcache_dat_i[30] ,
+    \u_riscv_top.wb_dcache_dat_i[29] ,
+    \u_riscv_top.wb_dcache_dat_i[28] ,
+    \u_riscv_top.wb_dcache_dat_i[27] ,
+    \u_riscv_top.wb_dcache_dat_i[26] ,
+    \u_riscv_top.wb_dcache_dat_i[25] ,
+    \u_riscv_top.wb_dcache_dat_i[24] ,
+    \u_riscv_top.wb_dcache_dat_i[23] ,
+    \u_riscv_top.wb_dcache_dat_i[22] ,
+    \u_riscv_top.wb_dcache_dat_i[21] ,
+    \u_riscv_top.wb_dcache_dat_i[20] ,
+    \u_riscv_top.wb_dcache_dat_i[19] ,
+    \u_riscv_top.wb_dcache_dat_i[18] ,
+    \u_riscv_top.wb_dcache_dat_i[17] ,
+    \u_riscv_top.wb_dcache_dat_i[16] ,
+    \u_riscv_top.wb_dcache_dat_i[15] ,
+    \u_riscv_top.wb_dcache_dat_i[14] ,
+    \u_riscv_top.wb_dcache_dat_i[13] ,
+    \u_riscv_top.wb_dcache_dat_i[12] ,
+    \u_riscv_top.wb_dcache_dat_i[11] ,
+    \u_riscv_top.wb_dcache_dat_i[10] ,
+    \u_riscv_top.wb_dcache_dat_i[9] ,
+    \u_riscv_top.wb_dcache_dat_i[8] ,
+    \u_riscv_top.wb_dcache_dat_i[7] ,
+    \u_riscv_top.wb_dcache_dat_i[6] ,
+    \u_riscv_top.wb_dcache_dat_i[5] ,
+    \u_riscv_top.wb_dcache_dat_i[4] ,
+    \u_riscv_top.wb_dcache_dat_i[3] ,
+    \u_riscv_top.wb_dcache_dat_i[2] ,
+    \u_riscv_top.wb_dcache_dat_i[1] ,
+    \u_riscv_top.wb_dcache_dat_i[0] }),
+    .m2_wbd_sel_i({\u_riscv_top.wb_dcache_sel_o[3] ,
+    \u_riscv_top.wb_dcache_sel_o[2] ,
+    \u_riscv_top.wb_dcache_sel_o[1] ,
+    \u_riscv_top.wb_dcache_sel_o[0] }),
+    .m3_wbd_adr_i({\u_riscv_top.wb_icache_adr_o[31] ,
+    \u_riscv_top.wb_icache_adr_o[30] ,
+    \u_riscv_top.wb_icache_adr_o[29] ,
+    \u_riscv_top.wb_icache_adr_o[28] ,
+    \u_riscv_top.wb_icache_adr_o[27] ,
+    \u_riscv_top.wb_icache_adr_o[26] ,
+    \u_riscv_top.wb_icache_adr_o[25] ,
+    \u_riscv_top.wb_icache_adr_o[24] ,
+    \u_riscv_top.wb_icache_adr_o[23] ,
+    \u_riscv_top.wb_icache_adr_o[22] ,
+    \u_riscv_top.wb_icache_adr_o[21] ,
+    \u_riscv_top.wb_icache_adr_o[20] ,
+    \u_riscv_top.wb_icache_adr_o[19] ,
+    \u_riscv_top.wb_icache_adr_o[18] ,
+    \u_riscv_top.wb_icache_adr_o[17] ,
+    \u_riscv_top.wb_icache_adr_o[16] ,
+    \u_riscv_top.wb_icache_adr_o[15] ,
+    \u_riscv_top.wb_icache_adr_o[14] ,
+    \u_riscv_top.wb_icache_adr_o[13] ,
+    \u_riscv_top.wb_icache_adr_o[12] ,
+    \u_riscv_top.wb_icache_adr_o[11] ,
+    \u_riscv_top.wb_icache_adr_o[10] ,
+    \u_riscv_top.wb_icache_adr_o[9] ,
+    \u_riscv_top.wb_icache_adr_o[8] ,
+    \u_riscv_top.wb_icache_adr_o[7] ,
+    \u_riscv_top.wb_icache_adr_o[6] ,
+    \u_riscv_top.wb_icache_adr_o[5] ,
+    \u_riscv_top.wb_icache_adr_o[4] ,
+    \u_riscv_top.wb_icache_adr_o[3] ,
+    \u_riscv_top.wb_icache_adr_o[2] ,
+    \u_riscv_top.wb_icache_adr_o[1] ,
+    \u_riscv_top.wb_icache_adr_o[0] }),
+    .m3_wbd_bl_i({\u_riscv_top.wb_icache_bl_o[9] ,
+    \u_riscv_top.wb_icache_bl_o[8] ,
+    \u_riscv_top.wb_icache_bl_o[7] ,
+    \u_riscv_top.wb_icache_bl_o[6] ,
+    \u_riscv_top.wb_icache_bl_o[5] ,
+    \u_riscv_top.wb_icache_bl_o[4] ,
+    \u_riscv_top.wb_icache_bl_o[3] ,
+    \u_riscv_top.wb_icache_bl_o[2] ,
+    \u_riscv_top.wb_icache_bl_o[1] ,
+    \u_riscv_top.wb_icache_bl_o[0] }),
+    .m3_wbd_dat_o({\u_riscv_top.wb_icache_dat_i[31] ,
+    \u_riscv_top.wb_icache_dat_i[30] ,
+    \u_riscv_top.wb_icache_dat_i[29] ,
+    \u_riscv_top.wb_icache_dat_i[28] ,
+    \u_riscv_top.wb_icache_dat_i[27] ,
+    \u_riscv_top.wb_icache_dat_i[26] ,
+    \u_riscv_top.wb_icache_dat_i[25] ,
+    \u_riscv_top.wb_icache_dat_i[24] ,
+    \u_riscv_top.wb_icache_dat_i[23] ,
+    \u_riscv_top.wb_icache_dat_i[22] ,
+    \u_riscv_top.wb_icache_dat_i[21] ,
+    \u_riscv_top.wb_icache_dat_i[20] ,
+    \u_riscv_top.wb_icache_dat_i[19] ,
+    \u_riscv_top.wb_icache_dat_i[18] ,
+    \u_riscv_top.wb_icache_dat_i[17] ,
+    \u_riscv_top.wb_icache_dat_i[16] ,
+    \u_riscv_top.wb_icache_dat_i[15] ,
+    \u_riscv_top.wb_icache_dat_i[14] ,
+    \u_riscv_top.wb_icache_dat_i[13] ,
+    \u_riscv_top.wb_icache_dat_i[12] ,
+    \u_riscv_top.wb_icache_dat_i[11] ,
+    \u_riscv_top.wb_icache_dat_i[10] ,
+    \u_riscv_top.wb_icache_dat_i[9] ,
+    \u_riscv_top.wb_icache_dat_i[8] ,
+    \u_riscv_top.wb_icache_dat_i[7] ,
+    \u_riscv_top.wb_icache_dat_i[6] ,
+    \u_riscv_top.wb_icache_dat_i[5] ,
+    \u_riscv_top.wb_icache_dat_i[4] ,
+    \u_riscv_top.wb_icache_dat_i[3] ,
+    \u_riscv_top.wb_icache_dat_i[2] ,
+    \u_riscv_top.wb_icache_dat_i[1] ,
+    \u_riscv_top.wb_icache_dat_i[0] }),
+    .m3_wbd_sel_i({\u_riscv_top.wb_icache_sel_o[3] ,
+    \u_riscv_top.wb_icache_sel_o[2] ,
+    \u_riscv_top.wb_icache_sel_o[1] ,
+    \u_riscv_top.wb_icache_sel_o[0] }),
+    .s0_wbd_adr_o({\wbd_spim_adr_o[31] ,
+    \wbd_spim_adr_o[30] ,
+    \wbd_spim_adr_o[29] ,
+    \wbd_spim_adr_o[28] ,
+    \wbd_spim_adr_o[27] ,
+    \wbd_spim_adr_o[26] ,
+    \wbd_spim_adr_o[25] ,
+    \wbd_spim_adr_o[24] ,
+    \wbd_spim_adr_o[23] ,
+    \wbd_spim_adr_o[22] ,
+    \wbd_spim_adr_o[21] ,
+    \wbd_spim_adr_o[20] ,
+    \wbd_spim_adr_o[19] ,
+    \wbd_spim_adr_o[18] ,
+    \wbd_spim_adr_o[17] ,
+    \wbd_spim_adr_o[16] ,
+    \wbd_spim_adr_o[15] ,
+    \wbd_spim_adr_o[14] ,
+    \wbd_spim_adr_o[13] ,
+    \wbd_spim_adr_o[12] ,
+    \wbd_spim_adr_o[11] ,
+    \wbd_spim_adr_o[10] ,
+    \wbd_spim_adr_o[9] ,
+    \wbd_spim_adr_o[8] ,
+    \wbd_spim_adr_o[7] ,
+    \wbd_spim_adr_o[6] ,
+    \wbd_spim_adr_o[5] ,
+    \wbd_spim_adr_o[4] ,
+    \wbd_spim_adr_o[3] ,
+    \wbd_spim_adr_o[2] ,
+    \wbd_spim_adr_o[1] ,
+    \wbd_spim_adr_o[0] }),
+    .s0_wbd_bl_o({\wbd_spim_bl_o[9] ,
+    \wbd_spim_bl_o[8] ,
+    \wbd_spim_bl_o[7] ,
+    \wbd_spim_bl_o[6] ,
+    \wbd_spim_bl_o[5] ,
+    \wbd_spim_bl_o[4] ,
+    \wbd_spim_bl_o[3] ,
+    \wbd_spim_bl_o[2] ,
+    \wbd_spim_bl_o[1] ,
+    \wbd_spim_bl_o[0] }),
+    .s0_wbd_dat_i({\wbd_spim_dat_i[31] ,
+    \wbd_spim_dat_i[30] ,
+    \wbd_spim_dat_i[29] ,
+    \wbd_spim_dat_i[28] ,
+    \wbd_spim_dat_i[27] ,
+    \wbd_spim_dat_i[26] ,
+    \wbd_spim_dat_i[25] ,
+    \wbd_spim_dat_i[24] ,
+    \wbd_spim_dat_i[23] ,
+    \wbd_spim_dat_i[22] ,
+    \wbd_spim_dat_i[21] ,
+    \wbd_spim_dat_i[20] ,
+    \wbd_spim_dat_i[19] ,
+    \wbd_spim_dat_i[18] ,
+    \wbd_spim_dat_i[17] ,
+    \wbd_spim_dat_i[16] ,
+    \wbd_spim_dat_i[15] ,
+    \wbd_spim_dat_i[14] ,
+    \wbd_spim_dat_i[13] ,
+    \wbd_spim_dat_i[12] ,
+    \wbd_spim_dat_i[11] ,
+    \wbd_spim_dat_i[10] ,
+    \wbd_spim_dat_i[9] ,
+    \wbd_spim_dat_i[8] ,
+    \wbd_spim_dat_i[7] ,
+    \wbd_spim_dat_i[6] ,
+    \wbd_spim_dat_i[5] ,
+    \wbd_spim_dat_i[4] ,
+    \wbd_spim_dat_i[3] ,
+    \wbd_spim_dat_i[2] ,
+    \wbd_spim_dat_i[1] ,
+    \wbd_spim_dat_i[0] }),
+    .s0_wbd_dat_o({\wbd_spim_dat_o[31] ,
+    \wbd_spim_dat_o[30] ,
+    \wbd_spim_dat_o[29] ,
+    \wbd_spim_dat_o[28] ,
+    \wbd_spim_dat_o[27] ,
+    \wbd_spim_dat_o[26] ,
+    \wbd_spim_dat_o[25] ,
+    \wbd_spim_dat_o[24] ,
+    \wbd_spim_dat_o[23] ,
+    \wbd_spim_dat_o[22] ,
+    \wbd_spim_dat_o[21] ,
+    \wbd_spim_dat_o[20] ,
+    \wbd_spim_dat_o[19] ,
+    \wbd_spim_dat_o[18] ,
+    \wbd_spim_dat_o[17] ,
+    \wbd_spim_dat_o[16] ,
+    \wbd_spim_dat_o[15] ,
+    \wbd_spim_dat_o[14] ,
+    \wbd_spim_dat_o[13] ,
+    \wbd_spim_dat_o[12] ,
+    \wbd_spim_dat_o[11] ,
+    \wbd_spim_dat_o[10] ,
+    \wbd_spim_dat_o[9] ,
+    \wbd_spim_dat_o[8] ,
+    \wbd_spim_dat_o[7] ,
+    \wbd_spim_dat_o[6] ,
+    \wbd_spim_dat_o[5] ,
+    \wbd_spim_dat_o[4] ,
+    \wbd_spim_dat_o[3] ,
+    \wbd_spim_dat_o[2] ,
+    \wbd_spim_dat_o[1] ,
+    \wbd_spim_dat_o[0] }),
+    .s0_wbd_sel_o({\wbd_spim_sel_o[3] ,
+    \wbd_spim_sel_o[2] ,
+    \wbd_spim_sel_o[1] ,
+    \wbd_spim_sel_o[0] }),
+    .s1_wbd_adr_o({\wbd_uart_adr_o[8] ,
+    \wbd_uart_adr_o[7] ,
+    \wbd_uart_adr_o[6] ,
+    \wbd_uart_adr_o[5] ,
+    \wbd_uart_adr_o[4] ,
+    \wbd_uart_adr_o[3] ,
+    \wbd_uart_adr_o[2] ,
+    \wbd_uart_adr_o[1] ,
+    \wbd_uart_adr_o[0] }),
+    .s1_wbd_dat_i({\wbd_uart_dat_i[31] ,
+    \wbd_uart_dat_i[30] ,
+    \wbd_uart_dat_i[29] ,
+    \wbd_uart_dat_i[28] ,
+    \wbd_uart_dat_i[27] ,
+    \wbd_uart_dat_i[26] ,
+    \wbd_uart_dat_i[25] ,
+    \wbd_uart_dat_i[24] ,
+    \wbd_uart_dat_i[23] ,
+    \wbd_uart_dat_i[22] ,
+    \wbd_uart_dat_i[21] ,
+    \wbd_uart_dat_i[20] ,
+    \wbd_uart_dat_i[19] ,
+    \wbd_uart_dat_i[18] ,
+    \wbd_uart_dat_i[17] ,
+    \wbd_uart_dat_i[16] ,
+    \wbd_uart_dat_i[15] ,
+    \wbd_uart_dat_i[14] ,
+    \wbd_uart_dat_i[13] ,
+    \wbd_uart_dat_i[12] ,
+    \wbd_uart_dat_i[11] ,
+    \wbd_uart_dat_i[10] ,
+    \wbd_uart_dat_i[9] ,
+    \wbd_uart_dat_i[8] ,
+    \wbd_uart_dat_i[7] ,
+    \wbd_uart_dat_i[6] ,
+    \wbd_uart_dat_i[5] ,
+    \wbd_uart_dat_i[4] ,
+    \wbd_uart_dat_i[3] ,
+    \wbd_uart_dat_i[2] ,
+    \wbd_uart_dat_i[1] ,
+    \wbd_uart_dat_i[0] }),
+    .s1_wbd_dat_o({\wbd_uart_dat_o[31] ,
+    \wbd_uart_dat_o[30] ,
+    \wbd_uart_dat_o[29] ,
+    \wbd_uart_dat_o[28] ,
+    \wbd_uart_dat_o[27] ,
+    \wbd_uart_dat_o[26] ,
+    \wbd_uart_dat_o[25] ,
+    \wbd_uart_dat_o[24] ,
+    \wbd_uart_dat_o[23] ,
+    \wbd_uart_dat_o[22] ,
+    \wbd_uart_dat_o[21] ,
+    \wbd_uart_dat_o[20] ,
+    \wbd_uart_dat_o[19] ,
+    \wbd_uart_dat_o[18] ,
+    \wbd_uart_dat_o[17] ,
+    \wbd_uart_dat_o[16] ,
+    \wbd_uart_dat_o[15] ,
+    \wbd_uart_dat_o[14] ,
+    \wbd_uart_dat_o[13] ,
+    \wbd_uart_dat_o[12] ,
+    \wbd_uart_dat_o[11] ,
+    \wbd_uart_dat_o[10] ,
+    \wbd_uart_dat_o[9] ,
+    \wbd_uart_dat_o[8] ,
+    \wbd_uart_dat_o[7] ,
+    \wbd_uart_dat_o[6] ,
+    \wbd_uart_dat_o[5] ,
+    \wbd_uart_dat_o[4] ,
+    \wbd_uart_dat_o[3] ,
+    \wbd_uart_dat_o[2] ,
+    \wbd_uart_dat_o[1] ,
+    \wbd_uart_dat_o[0] }),
+    .s1_wbd_sel_o({\wbd_uart_sel_o[3] ,
+    \wbd_uart_sel_o[2] ,
+    \wbd_uart_sel_o[1] ,
+    \wbd_uart_sel_o[0] }),
+    .s2_wbd_adr_o({\wbd_glbl_adr_o[9] ,
+    \wbd_glbl_adr_o[8] ,
+    \wbd_glbl_adr_o[7] ,
+    \wbd_glbl_adr_o[6] ,
+    \wbd_glbl_adr_o[5] ,
+    \wbd_glbl_adr_o[4] ,
+    \wbd_glbl_adr_o[3] ,
+    \wbd_glbl_adr_o[2] ,
+    \wbd_glbl_adr_o[1] ,
+    \wbd_glbl_adr_o[0] }),
+    .s2_wbd_dat_i({\wbd_glbl_dat_i[31] ,
+    \wbd_glbl_dat_i[30] ,
+    \wbd_glbl_dat_i[29] ,
+    \wbd_glbl_dat_i[28] ,
+    \wbd_glbl_dat_i[27] ,
+    \wbd_glbl_dat_i[26] ,
+    \wbd_glbl_dat_i[25] ,
+    \wbd_glbl_dat_i[24] ,
+    \wbd_glbl_dat_i[23] ,
+    \wbd_glbl_dat_i[22] ,
+    \wbd_glbl_dat_i[21] ,
+    \wbd_glbl_dat_i[20] ,
+    \wbd_glbl_dat_i[19] ,
+    \wbd_glbl_dat_i[18] ,
+    \wbd_glbl_dat_i[17] ,
+    \wbd_glbl_dat_i[16] ,
+    \wbd_glbl_dat_i[15] ,
+    \wbd_glbl_dat_i[14] ,
+    \wbd_glbl_dat_i[13] ,
+    \wbd_glbl_dat_i[12] ,
+    \wbd_glbl_dat_i[11] ,
+    \wbd_glbl_dat_i[10] ,
+    \wbd_glbl_dat_i[9] ,
+    \wbd_glbl_dat_i[8] ,
+    \wbd_glbl_dat_i[7] ,
+    \wbd_glbl_dat_i[6] ,
+    \wbd_glbl_dat_i[5] ,
+    \wbd_glbl_dat_i[4] ,
+    \wbd_glbl_dat_i[3] ,
+    \wbd_glbl_dat_i[2] ,
+    \wbd_glbl_dat_i[1] ,
+    \wbd_glbl_dat_i[0] }),
+    .s2_wbd_dat_o({\wbd_glbl_dat_o[31] ,
+    \wbd_glbl_dat_o[30] ,
+    \wbd_glbl_dat_o[29] ,
+    \wbd_glbl_dat_o[28] ,
+    \wbd_glbl_dat_o[27] ,
+    \wbd_glbl_dat_o[26] ,
+    \wbd_glbl_dat_o[25] ,
+    \wbd_glbl_dat_o[24] ,
+    \wbd_glbl_dat_o[23] ,
+    \wbd_glbl_dat_o[22] ,
+    \wbd_glbl_dat_o[21] ,
+    \wbd_glbl_dat_o[20] ,
+    \wbd_glbl_dat_o[19] ,
+    \wbd_glbl_dat_o[18] ,
+    \wbd_glbl_dat_o[17] ,
+    \wbd_glbl_dat_o[16] ,
+    \wbd_glbl_dat_o[15] ,
+    \wbd_glbl_dat_o[14] ,
+    \wbd_glbl_dat_o[13] ,
+    \wbd_glbl_dat_o[12] ,
+    \wbd_glbl_dat_o[11] ,
+    \wbd_glbl_dat_o[10] ,
+    \wbd_glbl_dat_o[9] ,
+    \wbd_glbl_dat_o[8] ,
+    \wbd_glbl_dat_o[7] ,
+    \wbd_glbl_dat_o[6] ,
+    \wbd_glbl_dat_o[5] ,
+    \wbd_glbl_dat_o[4] ,
+    \wbd_glbl_dat_o[3] ,
+    \wbd_glbl_dat_o[2] ,
+    \wbd_glbl_dat_o[1] ,
+    \wbd_glbl_dat_o[0] }),
+    .s2_wbd_sel_o({\wbd_glbl_sel_o[3] ,
+    \wbd_glbl_sel_o[2] ,
+    \wbd_glbl_sel_o[1] ,
+    \wbd_glbl_sel_o[0] }));
+ pinmux_top u_pinmux (.cfg_dco_mode(cfg_dco_mode),
+    .cfg_pll_enb(cfg_pll_enb),
+    .cfg_strap_pad_ctrl(cfg_strap_pad_ctrl_rp),
+    .cpu_clk(\cpu_clk_rp[2] ),
+    .cpu_intf_rst_n(\u_riscv_top.cpu_intf_rst_n ),
+    .e_reset_n(e_reset_n_rp),
+    .i2cm_clk_i(i2cm_clk_i),
+    .i2cm_clk_o(i2cm_clk_o),
+    .i2cm_clk_oen(i2cm_clk_oen),
+    .i2cm_data_i(i2cm_data_i),
+    .i2cm_data_o(i2cm_data_o),
+    .i2cm_data_oen(i2cm_data_oen),
+    .i2cm_intr(i2cm_intr_o),
+    .i2cm_rst_n(i2c_rst_n),
+    .int_pll_clock(\pll_clk_out[0] ),
+    .mclk(wbd_clk_pinmux_skew),
+    .p_reset_n(p_reset_n_rp),
+    .pll_ref_clk(pll_ref_clk),
+    .pulse1m_mclk(pulse1m_mclk),
+    .qspim_rst_n(qspim_rst_n),
+    .reg_ack(wbd_glbl_ack_i),
+    .reg_cs(wbd_glbl_stb_o),
+    .reg_wr(wbd_glbl_we_o),
+    .rtc_clk(\u_riscv_top.rtc_clk ),
+    .s_reset_n(\u_riscv_top.pwrup_rst_n ),
+    .sflash_sck(sflash_sck),
+    .soft_irq(soft_irq),
+    .spim_miso(sspim_so),
+    .spim_mosi(sspim_si),
+    .spim_sck(sspim_sck),
+    .spis_miso(sspis_so),
+    .spis_mosi(sspis_si),
+    .spis_sck(sspis_sck),
+    .spis_ssn(sspis_ssn),
+    .sspim_rst_n(sspim_rst_n),
+    .uartm_rxd(uartm_rxd),
+    .uartm_txd(uartm_txd),
+    .usb_clk(usb_clk),
+    .usb_dn_i(usb_dn_i),
+    .usb_dn_o(usb_dn_o),
+    .usb_dp_i(usb_dp_i),
+    .usb_dp_o(usb_dp_o),
+    .usb_intr(usb_intr_o),
+    .usb_oen(usb_oen),
+    .usb_rst_n(usb_rst_n),
+    .user_clock1(wb_clk_i),
+    .user_clock2(user_clock2),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .wbd_clk_int(wbd_clk_pinmux_rp),
+    .wbd_clk_pinmux(wbd_clk_pinmux_skew),
+    .xtal_clk(xtal_clk),
+    .cfg_cska_pinmux({\cfg_wcska_pinmux_rp[3] ,
+    \cfg_wcska_pinmux_rp[2] ,
+    \cfg_wcska_pinmux_rp[1] ,
+    \cfg_wcska_pinmux_rp[0] }),
+    .cfg_dac0_mux_sel({\cfg_dac0_mux_sel[7] ,
+    \cfg_dac0_mux_sel[6] ,
+    \cfg_dac0_mux_sel[5] ,
+    \cfg_dac0_mux_sel[4] ,
+    \cfg_dac0_mux_sel[3] ,
+    \cfg_dac0_mux_sel[2] ,
+    \cfg_dac0_mux_sel[1] ,
+    \cfg_dac0_mux_sel[0] }),
+    .cfg_dac1_mux_sel({\cfg_dac1_mux_sel[7] ,
+    \cfg_dac1_mux_sel[6] ,
+    \cfg_dac1_mux_sel[5] ,
+    \cfg_dac1_mux_sel[4] ,
+    \cfg_dac1_mux_sel[3] ,
+    \cfg_dac1_mux_sel[2] ,
+    \cfg_dac1_mux_sel[1] ,
+    \cfg_dac1_mux_sel[0] }),
+    .cfg_dac2_mux_sel({\cfg_dac2_mux_sel[7] ,
+    \cfg_dac2_mux_sel[6] ,
+    \cfg_dac2_mux_sel[5] ,
+    \cfg_dac2_mux_sel[4] ,
+    \cfg_dac2_mux_sel[3] ,
+    \cfg_dac2_mux_sel[2] ,
+    \cfg_dac2_mux_sel[1] ,
+    \cfg_dac2_mux_sel[0] }),
+    .cfg_dac3_mux_sel({\cfg_dac3_mux_sel[7] ,
+    \cfg_dac3_mux_sel[6] ,
+    \cfg_dac3_mux_sel[5] ,
+    \cfg_dac3_mux_sel[4] ,
+    \cfg_dac3_mux_sel[3] ,
+    \cfg_dac3_mux_sel[2] ,
+    \cfg_dac3_mux_sel[1] ,
+    \cfg_dac3_mux_sel[0] }),
+    .cfg_dc_trim({\cfg_dc_trim[25] ,
+    \cfg_dc_trim[24] ,
+    \cfg_dc_trim[23] ,
+    \cfg_dc_trim[22] ,
+    \cfg_dc_trim[21] ,
+    \cfg_dc_trim[20] ,
+    \cfg_dc_trim[19] ,
+    \cfg_dc_trim[18] ,
+    \cfg_dc_trim[17] ,
+    \cfg_dc_trim[16] ,
+    \cfg_dc_trim[15] ,
+    \cfg_dc_trim[14] ,
+    \cfg_dc_trim[13] ,
+    \cfg_dc_trim[12] ,
+    \cfg_dc_trim[11] ,
+    \cfg_dc_trim[10] ,
+    \cfg_dc_trim[9] ,
+    \cfg_dc_trim[8] ,
+    \cfg_dc_trim[7] ,
+    \cfg_dc_trim[6] ,
+    \cfg_dc_trim[5] ,
+    \cfg_dc_trim[4] ,
+    \cfg_dc_trim[3] ,
+    \cfg_dc_trim[2] ,
+    \cfg_dc_trim[1] ,
+    \cfg_dc_trim[0] }),
+    .cfg_pll_fed_div({\cfg_pll_fed_div[4] ,
+    \cfg_pll_fed_div[3] ,
+    \cfg_pll_fed_div[2] ,
+    \cfg_pll_fed_div[1] ,
+    \cfg_pll_fed_div[0] }),
+    .cfg_riscv_ctrl({\cfg_riscv_ctrl[15] ,
+    \cfg_riscv_ctrl[14] ,
+    \cfg_riscv_ctrl[13] ,
+    \cfg_riscv_ctrl[12] ,
+    \cfg_riscv_ctrl[11] ,
+    \cfg_riscv_ctrl[10] ,
+    \cfg_riscv_ctrl[9] ,
+    \cfg_riscv_ctrl[8] ,
+    \cfg_riscv_ctrl[7] ,
+    \cfg_riscv_ctrl[6] ,
+    \cfg_riscv_ctrl[5] ,
+    \cfg_riscv_ctrl[4] ,
+    \cfg_riscv_ctrl[3] ,
+    \cfg_riscv_ctrl[2] ,
+    \cfg_riscv_ctrl[1] ,
+    \cfg_riscv_ctrl[0] }),
+    .cpu_core_rst_n({\u_riscv_top.cpu_core_rst_n[3] ,
+    \u_riscv_top.cpu_core_rst_n[2] ,
+    \u_riscv_top.cpu_core_rst_n[1] ,
+    \u_riscv_top.cpu_core_rst_n[0] }),
+    .digital_io_in({io_in[37],
+    io_in[36],
+    io_in[35],
+    io_in[34],
+    io_in[33],
+    io_in[32],
+    io_in[31],
+    io_in[30],
+    io_in[29],
+    io_in[28],
+    io_in[27],
+    io_in[26],
+    io_in[25],
+    io_in[24],
+    io_in[23],
+    io_in[22],
+    io_in[21],
+    io_in[20],
+    io_in[19],
+    io_in[18],
+    io_in[17],
+    io_in[16],
+    io_in[15],
+    io_in[14],
+    io_in[13],
+    io_in[12],
+    io_in[11],
+    io_in[10],
+    io_in[9],
+    io_in[8],
+    io_in[7],
+    io_in[6],
+    io_in[5],
+    io_in[4],
+    io_in[3],
+    io_in[2],
+    io_in[1],
+    io_in[0]}),
+    .digital_io_oen({io_oeb[37],
+    io_oeb[36],
+    io_oeb[35],
+    io_oeb[34],
+    io_oeb[33],
+    io_oeb[32],
+    io_oeb[31],
+    io_oeb[30],
+    io_oeb[29],
+    io_oeb[28],
+    io_oeb[27],
+    io_oeb[26],
+    io_oeb[25],
+    io_oeb[24],
+    io_oeb[23],
+    io_oeb[22],
+    io_oeb[21],
+    io_oeb[20],
+    io_oeb[19],
+    io_oeb[18],
+    io_oeb[17],
+    io_oeb[16],
+    io_oeb[15],
+    io_oeb[14],
+    io_oeb[13],
+    io_oeb[12],
+    io_oeb[11],
+    io_oeb[10],
+    io_oeb[9],
+    io_oeb[8],
+    io_oeb[7],
+    io_oeb[6],
+    io_oeb[5],
+    io_oeb[4],
+    io_oeb[3],
+    io_oeb[2],
+    io_oeb[1],
+    io_oeb[0]}),
+    .digital_io_out({io_out[37],
+    io_out[36],
+    io_out[35],
+    io_out[34],
+    io_out[33],
+    io_out[32],
+    io_out[31],
+    io_out[30],
+    io_out[29],
+    io_out[28],
+    io_out[27],
+    io_out[26],
+    io_out[25],
+    io_out[24],
+    io_out[23],
+    io_out[22],
+    io_out[21],
+    io_out[20],
+    io_out[19],
+    io_out[18],
+    io_out[17],
+    io_out[16],
+    io_out[15],
+    io_out[14],
+    io_out[13],
+    io_out[12],
+    io_out[11],
+    io_out[10],
+    io_out[9],
+    io_out[8],
+    io_out[7],
+    io_out[6],
+    io_out[5],
+    io_out[4],
+    io_out[3],
+    io_out[2],
+    io_out[1],
+    io_out[0]}),
+    .irq_lines({\irq_lines[31] ,
+    \irq_lines[30] ,
+    \irq_lines[29] ,
+    \irq_lines[28] ,
+    \irq_lines[27] ,
+    \irq_lines[26] ,
+    \irq_lines[25] ,
+    \irq_lines[24] ,
+    \irq_lines[23] ,
+    \irq_lines[22] ,
+    \irq_lines[21] ,
+    \irq_lines[20] ,
+    \irq_lines[19] ,
+    \irq_lines[18] ,
+    \irq_lines[17] ,
+    \irq_lines[16] ,
+    \irq_lines[15] ,
+    \irq_lines[14] ,
+    \irq_lines[13] ,
+    \irq_lines[12] ,
+    \irq_lines[11] ,
+    \irq_lines[10] ,
+    \irq_lines[9] ,
+    \irq_lines[8] ,
+    \irq_lines[7] ,
+    \irq_lines[6] ,
+    \irq_lines[5] ,
+    \irq_lines[4] ,
+    \irq_lines[3] ,
+    \irq_lines[2] ,
+    \irq_lines[1] ,
+    \irq_lines[0] }),
+    .pinmux_debug({la_data_out[127],
+    la_data_out[126],
+    la_data_out[125],
+    la_data_out[124],
+    la_data_out[123],
+    la_data_out[122],
+    la_data_out[121],
+    la_data_out[120],
+    la_data_out[119],
+    la_data_out[118],
+    la_data_out[117],
+    la_data_out[116],
+    la_data_out[115],
+    la_data_out[114],
+    la_data_out[113],
+    la_data_out[112],
+    la_data_out[111],
+    la_data_out[110],
+    la_data_out[109],
+    la_data_out[108],
+    la_data_out[107],
+    la_data_out[106],
+    la_data_out[105],
+    la_data_out[104],
+    la_data_out[103],
+    la_data_out[102],
+    la_data_out[101],
+    la_data_out[100],
+    la_data_out[99],
+    la_data_out[98],
+    la_data_out[97],
+    la_data_out[96]}),
+    .reg_addr({\wbd_glbl_adr_o[9] ,
+    \wbd_glbl_adr_o[8] ,
+    \wbd_glbl_adr_o[7] ,
+    \wbd_glbl_adr_o[6] ,
+    \wbd_glbl_adr_o[5] ,
+    \wbd_glbl_adr_o[4] ,
+    \wbd_glbl_adr_o[3] ,
+    \wbd_glbl_adr_o[2] ,
+    \wbd_glbl_adr_o[1] ,
+    \wbd_glbl_adr_o[0] }),
+    .reg_be({\wbd_glbl_sel_o[3] ,
+    \wbd_glbl_sel_o[2] ,
+    \wbd_glbl_sel_o[1] ,
+    \wbd_glbl_sel_o[0] }),
+    .reg_rdata({\wbd_glbl_dat_i[31] ,
+    \wbd_glbl_dat_i[30] ,
+    \wbd_glbl_dat_i[29] ,
+    \wbd_glbl_dat_i[28] ,
+    \wbd_glbl_dat_i[27] ,
+    \wbd_glbl_dat_i[26] ,
+    \wbd_glbl_dat_i[25] ,
+    \wbd_glbl_dat_i[24] ,
+    \wbd_glbl_dat_i[23] ,
+    \wbd_glbl_dat_i[22] ,
+    \wbd_glbl_dat_i[21] ,
+    \wbd_glbl_dat_i[20] ,
+    \wbd_glbl_dat_i[19] ,
+    \wbd_glbl_dat_i[18] ,
+    \wbd_glbl_dat_i[17] ,
+    \wbd_glbl_dat_i[16] ,
+    \wbd_glbl_dat_i[15] ,
+    \wbd_glbl_dat_i[14] ,
+    \wbd_glbl_dat_i[13] ,
+    \wbd_glbl_dat_i[12] ,
+    \wbd_glbl_dat_i[11] ,
+    \wbd_glbl_dat_i[10] ,
+    \wbd_glbl_dat_i[9] ,
+    \wbd_glbl_dat_i[8] ,
+    \wbd_glbl_dat_i[7] ,
+    \wbd_glbl_dat_i[6] ,
+    \wbd_glbl_dat_i[5] ,
+    \wbd_glbl_dat_i[4] ,
+    \wbd_glbl_dat_i[3] ,
+    \wbd_glbl_dat_i[2] ,
+    \wbd_glbl_dat_i[1] ,
+    \wbd_glbl_dat_i[0] }),
+    .reg_wdata({\wbd_glbl_dat_o[31] ,
+    \wbd_glbl_dat_o[30] ,
+    \wbd_glbl_dat_o[29] ,
+    \wbd_glbl_dat_o[28] ,
+    \wbd_glbl_dat_o[27] ,
+    \wbd_glbl_dat_o[26] ,
+    \wbd_glbl_dat_o[25] ,
+    \wbd_glbl_dat_o[24] ,
+    \wbd_glbl_dat_o[23] ,
+    \wbd_glbl_dat_o[22] ,
+    \wbd_glbl_dat_o[21] ,
+    \wbd_glbl_dat_o[20] ,
+    \wbd_glbl_dat_o[19] ,
+    \wbd_glbl_dat_o[18] ,
+    \wbd_glbl_dat_o[17] ,
+    \wbd_glbl_dat_o[16] ,
+    \wbd_glbl_dat_o[15] ,
+    \wbd_glbl_dat_o[14] ,
+    \wbd_glbl_dat_o[13] ,
+    \wbd_glbl_dat_o[12] ,
+    \wbd_glbl_dat_o[11] ,
+    \wbd_glbl_dat_o[10] ,
+    \wbd_glbl_dat_o[9] ,
+    \wbd_glbl_dat_o[8] ,
+    \wbd_glbl_dat_o[7] ,
+    \wbd_glbl_dat_o[6] ,
+    \wbd_glbl_dat_o[5] ,
+    \wbd_glbl_dat_o[4] ,
+    \wbd_glbl_dat_o[3] ,
+    \wbd_glbl_dat_o[2] ,
+    \wbd_glbl_dat_o[1] ,
+    \wbd_glbl_dat_o[0] }),
+    .sflash_di({\sflash_di[3] ,
+    \sflash_di[2] ,
+    \sflash_di[1] ,
+    \sflash_di[0] }),
+    .sflash_do({\sflash_do[3] ,
+    \sflash_do[2] ,
+    \sflash_do[1] ,
+    \sflash_do[0] }),
+    .sflash_oen({\sflash_oen[3] ,
+    \sflash_oen[2] ,
+    \sflash_oen[1] ,
+    \sflash_oen[0] }),
+    .sflash_ss({\spi_csn[3] ,
+    \spi_csn[2] ,
+    \spi_csn[1] ,
+    \spi_csn[0] }),
+    .spim_ssn({\sspim_ssn[3] ,
+    \sspim_ssn[2] ,
+    \sspim_ssn[1] ,
+    \sspim_ssn[0] }),
+    .strap_sticky({\strap_sticky[31] ,
+    \strap_sticky[30] ,
+    \strap_sticky[29] ,
+    \strap_sticky[28] ,
+    \strap_sticky[27] ,
+    \strap_sticky[26] ,
+    \strap_sticky[25] ,
+    \strap_sticky[24] ,
+    \strap_sticky[23] ,
+    \strap_sticky[22] ,
+    \strap_sticky[21] ,
+    \strap_sticky[20] ,
+    \strap_sticky[19] ,
+    \strap_sticky[18] ,
+    \strap_sticky[17] ,
+    \strap_sticky[16] ,
+    \strap_sticky[15] ,
+    \strap_sticky[14] ,
+    \strap_sticky[13] ,
+    \strap_sticky[12] ,
+    \strap_sticky[11] ,
+    \strap_sticky[10] ,
+    \strap_sticky[9] ,
+    \strap_sticky[8] ,
+    \strap_sticky[7] ,
+    \strap_sticky[6] ,
+    \strap_sticky[5] ,
+    \strap_sticky[4] ,
+    \strap_sticky[3] ,
+    \strap_sticky[2] ,
+    \strap_sticky[1] ,
+    \strap_sticky[0] }),
+    .strap_uartm({\strap_uartm[1] ,
+    \strap_uartm[0] }),
+    .system_strap({\system_strap_rp[31] ,
+    \system_strap_rp[30] ,
+    \system_strap_rp[29] ,
+    \system_strap_rp[28] ,
+    \system_strap_rp[27] ,
+    \system_strap_rp[26] ,
+    \system_strap_rp[25] ,
+    \system_strap_rp[24] ,
+    \system_strap_rp[23] ,
+    \system_strap_rp[22] ,
+    \system_strap_rp[21] ,
+    \system_strap_rp[20] ,
+    \system_strap_rp[19] ,
+    \system_strap_rp[18] ,
+    \system_strap_rp[17] ,
+    \system_strap_rp[16] ,
+    \system_strap_rp[15] ,
+    \system_strap_rp[14] ,
+    \system_strap_rp[13] ,
+    \system_strap_rp[12] ,
+    \system_strap_rp[11] ,
+    \system_strap_rp[10] ,
+    \system_strap_rp[9] ,
+    \system_strap_rp[8] ,
+    \system_strap_rp[7] ,
+    \system_strap_rp[6] ,
+    \system_strap_rp[5] ,
+    \system_strap_rp[4] ,
+    \system_strap_rp[3] ,
+    \system_strap_rp[2] ,
+    \system_strap_rp[1] ,
+    \system_strap_rp[0] }),
+    .uart_rst_n({\uart_rst_n[1] ,
+    \uart_rst_n[0] }),
+    .uart_rxd({\uart_rxd[1] ,
+    \uart_rxd[0] }),
+    .uart_txd({\uart_txd[1] ,
+    \uart_txd[0] }),
+    .user_irq({user_irq[2],
+    user_irq[1],
+    user_irq[0]}));
+ dg_pll u_pll (.VGND(vssd1),
+    .VPWR(vccd1),
+    .dco(cfg_dco_mode),
+    .enable(cfg_pll_enb),
+    .osc(pll_ref_clk),
+    .resetb(wbd_pll_rst_n),
+    .clockp({\pll_clk_out[1] ,
+    \pll_clk_out[0] }),
+    .div({\cfg_pll_fed_div[4] ,
+    \cfg_pll_fed_div[3] ,
+    \cfg_pll_fed_div[2] ,
+    \cfg_pll_fed_div[1] ,
+    \cfg_pll_fed_div[0] }),
+    .ext_trim({\cfg_dc_trim[25] ,
+    \cfg_dc_trim[24] ,
+    \cfg_dc_trim[23] ,
+    \cfg_dc_trim[22] ,
+    \cfg_dc_trim[21] ,
+    \cfg_dc_trim[20] ,
+    \cfg_dc_trim[19] ,
+    \cfg_dc_trim[18] ,
+    \cfg_dc_trim[17] ,
+    \cfg_dc_trim[16] ,
+    \cfg_dc_trim[15] ,
+    \cfg_dc_trim[14] ,
+    \cfg_dc_trim[13] ,
+    \cfg_dc_trim[12] ,
+    \cfg_dc_trim[11] ,
+    \cfg_dc_trim[10] ,
+    \cfg_dc_trim[9] ,
+    \cfg_dc_trim[8] ,
+    \cfg_dc_trim[7] ,
+    \cfg_dc_trim[6] ,
+    \cfg_dc_trim[5] ,
+    \cfg_dc_trim[4] ,
+    \cfg_dc_trim[3] ,
+    \cfg_dc_trim[2] ,
+    \cfg_dc_trim[1] ,
+    \cfg_dc_trim[0] }));
+ qspim_top u_qspi_master (.cfg_init_bypass(\system_strap[30] ),
+    .mclk(wbd_clk_spi),
+    .rst_n(qspim_rst_n),
+    .spi_clk(sflash_sck),
+    .strap_pre_sram(\system_strap[15] ),
+    .strap_sram(\system_strap[9] ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .wbd_ack_o(wbd_spim_ack_i),
+    .wbd_bry_i(wbd_spim_bry_o),
+    .wbd_clk_int(wbd_clk_qspi_rp),
+    .wbd_clk_spi(wbd_clk_spi),
+    .wbd_err_o(wbd_spim_err_i),
+    .wbd_lack_o(wbd_spim_lack_i),
+    .wbd_stb_i(wbd_spim_stb_o),
+    .wbd_we_i(wbd_spim_we_o),
+    .cfg_cska_sp_co({\cfg_wcska_qspi_co_rp[3] ,
+    \cfg_wcska_qspi_co_rp[2] ,
+    \cfg_wcska_qspi_co_rp[1] ,
+    \cfg_wcska_qspi_co_rp[0] }),
+    .cfg_cska_spi({\cfg_wcska_qspi_rp[3] ,
+    \cfg_wcska_qspi_rp[2] ,
+    \cfg_wcska_qspi_rp[1] ,
+    \cfg_wcska_qspi_rp[0] }),
+    .spi_csn({\spi_csn[3] ,
+    \spi_csn[2] ,
+    \spi_csn[1] ,
+    \spi_csn[0] }),
+    .spi_debug({la_data_out[95],
+    la_data_out[94],
+    la_data_out[93],
+    la_data_out[92],
+    la_data_out[91],
+    la_data_out[90],
+    la_data_out[89],
+    la_data_out[88],
+    la_data_out[87],
+    la_data_out[86],
+    la_data_out[85],
+    la_data_out[84],
+    la_data_out[83],
+    la_data_out[82],
+    la_data_out[81],
+    la_data_out[80],
+    la_data_out[79],
+    la_data_out[78],
+    la_data_out[77],
+    la_data_out[76],
+    la_data_out[75],
+    la_data_out[74],
+    la_data_out[73],
+    la_data_out[72],
+    la_data_out[71],
+    la_data_out[70],
+    la_data_out[69],
+    la_data_out[68],
+    la_data_out[67],
+    la_data_out[66],
+    la_data_out[65],
+    la_data_out[64]}),
+    .spi_oen({\sflash_oen[3] ,
+    \sflash_oen[2] ,
+    \sflash_oen[1] ,
+    \sflash_oen[0] }),
+    .spi_sdi({\sflash_di[3] ,
+    \sflash_di[2] ,
+    \sflash_di[1] ,
+    \sflash_di[0] }),
+    .spi_sdo({\sflash_do[3] ,
+    \sflash_do[2] ,
+    \sflash_do[1] ,
+    \sflash_do[0] }),
+    .strap_flash({\system_strap[11] ,
+    \system_strap[10] }),
+    .wbd_adr_i({\wbd_spim_adr_o[31] ,
+    \wbd_spim_adr_o[30] ,
+    \wbd_spim_adr_o[29] ,
+    \wbd_spim_adr_o[28] ,
+    \wbd_spim_adr_o[27] ,
+    \wbd_spim_adr_o[26] ,
+    \wbd_spim_adr_o[25] ,
+    \wbd_spim_adr_o[24] ,
+    \wbd_spim_adr_o[23] ,
+    \wbd_spim_adr_o[22] ,
+    \wbd_spim_adr_o[21] ,
+    \wbd_spim_adr_o[20] ,
+    \wbd_spim_adr_o[19] ,
+    \wbd_spim_adr_o[18] ,
+    \wbd_spim_adr_o[17] ,
+    \wbd_spim_adr_o[16] ,
+    \wbd_spim_adr_o[15] ,
+    \wbd_spim_adr_o[14] ,
+    \wbd_spim_adr_o[13] ,
+    \wbd_spim_adr_o[12] ,
+    \wbd_spim_adr_o[11] ,
+    \wbd_spim_adr_o[10] ,
+    \wbd_spim_adr_o[9] ,
+    \wbd_spim_adr_o[8] ,
+    \wbd_spim_adr_o[7] ,
+    \wbd_spim_adr_o[6] ,
+    \wbd_spim_adr_o[5] ,
+    \wbd_spim_adr_o[4] ,
+    \wbd_spim_adr_o[3] ,
+    \wbd_spim_adr_o[2] ,
+    \wbd_spim_adr_o[1] ,
+    \wbd_spim_adr_o[0] }),
+    .wbd_bl_i({\wbd_spim_bl_o[9] ,
+    \wbd_spim_bl_o[8] ,
+    \wbd_spim_bl_o[7] ,
+    \wbd_spim_bl_o[6] ,
+    \wbd_spim_bl_o[5] ,
+    \wbd_spim_bl_o[4] ,
+    \wbd_spim_bl_o[3] ,
+    \wbd_spim_bl_o[2] ,
+    \wbd_spim_bl_o[1] ,
+    \wbd_spim_bl_o[0] }),
+    .wbd_dat_i({\wbd_spim_dat_o[31] ,
+    \wbd_spim_dat_o[30] ,
+    \wbd_spim_dat_o[29] ,
+    \wbd_spim_dat_o[28] ,
+    \wbd_spim_dat_o[27] ,
+    \wbd_spim_dat_o[26] ,
+    \wbd_spim_dat_o[25] ,
+    \wbd_spim_dat_o[24] ,
+    \wbd_spim_dat_o[23] ,
+    \wbd_spim_dat_o[22] ,
+    \wbd_spim_dat_o[21] ,
+    \wbd_spim_dat_o[20] ,
+    \wbd_spim_dat_o[19] ,
+    \wbd_spim_dat_o[18] ,
+    \wbd_spim_dat_o[17] ,
+    \wbd_spim_dat_o[16] ,
+    \wbd_spim_dat_o[15] ,
+    \wbd_spim_dat_o[14] ,
+    \wbd_spim_dat_o[13] ,
+    \wbd_spim_dat_o[12] ,
+    \wbd_spim_dat_o[11] ,
+    \wbd_spim_dat_o[10] ,
+    \wbd_spim_dat_o[9] ,
+    \wbd_spim_dat_o[8] ,
+    \wbd_spim_dat_o[7] ,
+    \wbd_spim_dat_o[6] ,
+    \wbd_spim_dat_o[5] ,
+    \wbd_spim_dat_o[4] ,
+    \wbd_spim_dat_o[3] ,
+    \wbd_spim_dat_o[2] ,
+    \wbd_spim_dat_o[1] ,
+    \wbd_spim_dat_o[0] }),
+    .wbd_dat_o({\wbd_spim_dat_i[31] ,
+    \wbd_spim_dat_i[30] ,
+    \wbd_spim_dat_i[29] ,
+    \wbd_spim_dat_i[28] ,
+    \wbd_spim_dat_i[27] ,
+    \wbd_spim_dat_i[26] ,
+    \wbd_spim_dat_i[25] ,
+    \wbd_spim_dat_i[24] ,
+    \wbd_spim_dat_i[23] ,
+    \wbd_spim_dat_i[22] ,
+    \wbd_spim_dat_i[21] ,
+    \wbd_spim_dat_i[20] ,
+    \wbd_spim_dat_i[19] ,
+    \wbd_spim_dat_i[18] ,
+    \wbd_spim_dat_i[17] ,
+    \wbd_spim_dat_i[16] ,
+    \wbd_spim_dat_i[15] ,
+    \wbd_spim_dat_i[14] ,
+    \wbd_spim_dat_i[13] ,
+    \wbd_spim_dat_i[12] ,
+    \wbd_spim_dat_i[11] ,
+    \wbd_spim_dat_i[10] ,
+    \wbd_spim_dat_i[9] ,
+    \wbd_spim_dat_i[8] ,
+    \wbd_spim_dat_i[7] ,
+    \wbd_spim_dat_i[6] ,
+    \wbd_spim_dat_i[5] ,
+    \wbd_spim_dat_i[4] ,
+    \wbd_spim_dat_i[3] ,
+    \wbd_spim_dat_i[2] ,
+    \wbd_spim_dat_i[1] ,
+    \wbd_spim_dat_i[0] }),
+    .wbd_sel_i({\wbd_spim_sel_o[3] ,
+    \wbd_spim_sel_o[2] ,
+    \wbd_spim_sel_o[1] ,
+    \wbd_spim_sel_o[0] }));
+ ycr_core_top \u_riscv_top.i_core_top_0  (.clk(\u_riscv_top.core_clk_core0_skew ),
+    .clk_o(\u_riscv_top.core_clk_out[0] ),
+    .core2dmem_cmd_o(\u_riscv_top.core0_dmem_cmd ),
+    .core2dmem_req_o(\u_riscv_top.core0_dmem_req ),
+    .core2imem_cmd_o(\u_riscv_top.core0_imem_cmd ),
+    .core2imem_req_o(\u_riscv_top.core0_imem_req ),
+    .core_clk_int(\u_riscv_top.core0_clk ),
+    .core_clk_skew(\u_riscv_top.core_clk_core0_skew ),
+    .core_irq_mtimer_i(\u_riscv_top.core0_timer_irq ),
+    .core_irq_soft_i(\u_riscv_top.core0_soft_irq ),
+    .cpu_rst_n(\u_riscv_top.cpu_core_rst_n[0] ),
+    .dmem2core_req_ack_i(\u_riscv_top.core0_dmem_req_ack ),
+    .imem2core_req_ack_i(\u_riscv_top.core0_imem_req_ack ),
+    .pwrup_rst_n(\u_riscv_top.pwrup_rst_n ),
+    .rst_n(\u_riscv_top.pwrup_rst_n ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .cfg_ccska({\u_riscv_top.cfg_ccska_riscv_core0[3] ,
+    \u_riscv_top.cfg_ccska_riscv_core0[2] ,
+    \u_riscv_top.cfg_ccska_riscv_core0[1] ,
+    \u_riscv_top.cfg_ccska_riscv_core0[0] }),
+    .core2dmem_addr_o({\u_riscv_top.core0_dmem_addr[31] ,
+    \u_riscv_top.core0_dmem_addr[30] ,
+    \u_riscv_top.core0_dmem_addr[29] ,
+    \u_riscv_top.core0_dmem_addr[28] ,
+    \u_riscv_top.core0_dmem_addr[27] ,
+    \u_riscv_top.core0_dmem_addr[26] ,
+    \u_riscv_top.core0_dmem_addr[25] ,
+    \u_riscv_top.core0_dmem_addr[24] ,
+    \u_riscv_top.core0_dmem_addr[23] ,
+    \u_riscv_top.core0_dmem_addr[22] ,
+    \u_riscv_top.core0_dmem_addr[21] ,
+    \u_riscv_top.core0_dmem_addr[20] ,
+    \u_riscv_top.core0_dmem_addr[19] ,
+    \u_riscv_top.core0_dmem_addr[18] ,
+    \u_riscv_top.core0_dmem_addr[17] ,
+    \u_riscv_top.core0_dmem_addr[16] ,
+    \u_riscv_top.core0_dmem_addr[15] ,
+    \u_riscv_top.core0_dmem_addr[14] ,
+    \u_riscv_top.core0_dmem_addr[13] ,
+    \u_riscv_top.core0_dmem_addr[12] ,
+    \u_riscv_top.core0_dmem_addr[11] ,
+    \u_riscv_top.core0_dmem_addr[10] ,
+    \u_riscv_top.core0_dmem_addr[9] ,
+    \u_riscv_top.core0_dmem_addr[8] ,
+    \u_riscv_top.core0_dmem_addr[7] ,
+    \u_riscv_top.core0_dmem_addr[6] ,
+    \u_riscv_top.core0_dmem_addr[5] ,
+    \u_riscv_top.core0_dmem_addr[4] ,
+    \u_riscv_top.core0_dmem_addr[3] ,
+    \u_riscv_top.core0_dmem_addr[2] ,
+    \u_riscv_top.core0_dmem_addr[1] ,
+    \u_riscv_top.core0_dmem_addr[0] }),
+    .core2dmem_wdata_o({\u_riscv_top.core0_dmem_wdata[31] ,
+    \u_riscv_top.core0_dmem_wdata[30] ,
+    \u_riscv_top.core0_dmem_wdata[29] ,
+    \u_riscv_top.core0_dmem_wdata[28] ,
+    \u_riscv_top.core0_dmem_wdata[27] ,
+    \u_riscv_top.core0_dmem_wdata[26] ,
+    \u_riscv_top.core0_dmem_wdata[25] ,
+    \u_riscv_top.core0_dmem_wdata[24] ,
+    \u_riscv_top.core0_dmem_wdata[23] ,
+    \u_riscv_top.core0_dmem_wdata[22] ,
+    \u_riscv_top.core0_dmem_wdata[21] ,
+    \u_riscv_top.core0_dmem_wdata[20] ,
+    \u_riscv_top.core0_dmem_wdata[19] ,
+    \u_riscv_top.core0_dmem_wdata[18] ,
+    \u_riscv_top.core0_dmem_wdata[17] ,
+    \u_riscv_top.core0_dmem_wdata[16] ,
+    \u_riscv_top.core0_dmem_wdata[15] ,
+    \u_riscv_top.core0_dmem_wdata[14] ,
+    \u_riscv_top.core0_dmem_wdata[13] ,
+    \u_riscv_top.core0_dmem_wdata[12] ,
+    \u_riscv_top.core0_dmem_wdata[11] ,
+    \u_riscv_top.core0_dmem_wdata[10] ,
+    \u_riscv_top.core0_dmem_wdata[9] ,
+    \u_riscv_top.core0_dmem_wdata[8] ,
+    \u_riscv_top.core0_dmem_wdata[7] ,
+    \u_riscv_top.core0_dmem_wdata[6] ,
+    \u_riscv_top.core0_dmem_wdata[5] ,
+    \u_riscv_top.core0_dmem_wdata[4] ,
+    \u_riscv_top.core0_dmem_wdata[3] ,
+    \u_riscv_top.core0_dmem_wdata[2] ,
+    \u_riscv_top.core0_dmem_wdata[1] ,
+    \u_riscv_top.core0_dmem_wdata[0] }),
+    .core2dmem_width_o({\u_riscv_top.core0_dmem_width[1] ,
+    \u_riscv_top.core0_dmem_width[0] }),
+    .core2imem_addr_o({\u_riscv_top.core0_imem_addr[31] ,
+    \u_riscv_top.core0_imem_addr[30] ,
+    \u_riscv_top.core0_imem_addr[29] ,
+    \u_riscv_top.core0_imem_addr[28] ,
+    \u_riscv_top.core0_imem_addr[27] ,
+    \u_riscv_top.core0_imem_addr[26] ,
+    \u_riscv_top.core0_imem_addr[25] ,
+    \u_riscv_top.core0_imem_addr[24] ,
+    \u_riscv_top.core0_imem_addr[23] ,
+    \u_riscv_top.core0_imem_addr[22] ,
+    \u_riscv_top.core0_imem_addr[21] ,
+    \u_riscv_top.core0_imem_addr[20] ,
+    \u_riscv_top.core0_imem_addr[19] ,
+    \u_riscv_top.core0_imem_addr[18] ,
+    \u_riscv_top.core0_imem_addr[17] ,
+    \u_riscv_top.core0_imem_addr[16] ,
+    \u_riscv_top.core0_imem_addr[15] ,
+    \u_riscv_top.core0_imem_addr[14] ,
+    \u_riscv_top.core0_imem_addr[13] ,
+    \u_riscv_top.core0_imem_addr[12] ,
+    \u_riscv_top.core0_imem_addr[11] ,
+    \u_riscv_top.core0_imem_addr[10] ,
+    \u_riscv_top.core0_imem_addr[9] ,
+    \u_riscv_top.core0_imem_addr[8] ,
+    \u_riscv_top.core0_imem_addr[7] ,
+    \u_riscv_top.core0_imem_addr[6] ,
+    \u_riscv_top.core0_imem_addr[5] ,
+    \u_riscv_top.core0_imem_addr[4] ,
+    \u_riscv_top.core0_imem_addr[3] ,
+    \u_riscv_top.core0_imem_addr[2] ,
+    \u_riscv_top.core0_imem_addr[1] ,
+    \u_riscv_top.core0_imem_addr[0] }),
+    .core2imem_bl_o({\u_riscv_top.core0_imem_bl[2] ,
+    \u_riscv_top.core0_imem_bl[1] ,
+    \u_riscv_top.core0_imem_bl[0] }),
+    .core_debug({\u_riscv_top.core0_debug[48] ,
+    \u_riscv_top.core0_debug[47] ,
+    \u_riscv_top.core0_debug[46] ,
+    \u_riscv_top.core0_debug[45] ,
+    \u_riscv_top.core0_debug[44] ,
+    \u_riscv_top.core0_debug[43] ,
+    \u_riscv_top.core0_debug[42] ,
+    \u_riscv_top.core0_debug[41] ,
+    \u_riscv_top.core0_debug[40] ,
+    \u_riscv_top.core0_debug[39] ,
+    \u_riscv_top.core0_debug[38] ,
+    \u_riscv_top.core0_debug[37] ,
+    \u_riscv_top.core0_debug[36] ,
+    \u_riscv_top.core0_debug[35] ,
+    \u_riscv_top.core0_debug[34] ,
+    \u_riscv_top.core0_debug[33] ,
+    \u_riscv_top.core0_debug[32] ,
+    \u_riscv_top.core0_debug[31] ,
+    \u_riscv_top.core0_debug[30] ,
+    \u_riscv_top.core0_debug[29] ,
+    \u_riscv_top.core0_debug[28] ,
+    \u_riscv_top.core0_debug[27] ,
+    \u_riscv_top.core0_debug[26] ,
+    \u_riscv_top.core0_debug[25] ,
+    \u_riscv_top.core0_debug[24] ,
+    \u_riscv_top.core0_debug[23] ,
+    \u_riscv_top.core0_debug[22] ,
+    \u_riscv_top.core0_debug[21] ,
+    \u_riscv_top.core0_debug[20] ,
+    \u_riscv_top.core0_debug[19] ,
+    \u_riscv_top.core0_debug[18] ,
+    \u_riscv_top.core0_debug[17] ,
+    \u_riscv_top.core0_debug[16] ,
+    \u_riscv_top.core0_debug[15] ,
+    \u_riscv_top.core0_debug[14] ,
+    \u_riscv_top.core0_debug[13] ,
+    \u_riscv_top.core0_debug[12] ,
+    \u_riscv_top.core0_debug[11] ,
+    \u_riscv_top.core0_debug[10] ,
+    \u_riscv_top.core0_debug[9] ,
+    \u_riscv_top.core0_debug[8] ,
+    \u_riscv_top.core0_debug[7] ,
+    \u_riscv_top.core0_debug[6] ,
+    \u_riscv_top.core0_debug[5] ,
+    \u_riscv_top.core0_debug[4] ,
+    \u_riscv_top.core0_debug[3] ,
+    \u_riscv_top.core0_debug[2] ,
+    \u_riscv_top.core0_debug[1] ,
+    \u_riscv_top.core0_debug[0] }),
+    .core_irq_lines_i({\u_riscv_top.core0_irq_lines[31] ,
+    \u_riscv_top.core0_irq_lines[30] ,
+    \u_riscv_top.core0_irq_lines[29] ,
+    \u_riscv_top.core0_irq_lines[28] ,
+    \u_riscv_top.core0_irq_lines[27] ,
+    \u_riscv_top.core0_irq_lines[26] ,
+    \u_riscv_top.core0_irq_lines[25] ,
+    \u_riscv_top.core0_irq_lines[24] ,
+    \u_riscv_top.core0_irq_lines[23] ,
+    \u_riscv_top.core0_irq_lines[22] ,
+    \u_riscv_top.core0_irq_lines[21] ,
+    \u_riscv_top.core0_irq_lines[20] ,
+    \u_riscv_top.core0_irq_lines[19] ,
+    \u_riscv_top.core0_irq_lines[18] ,
+    \u_riscv_top.core0_irq_lines[17] ,
+    \u_riscv_top.core0_irq_lines[16] ,
+    \u_riscv_top.core0_irq_lines[15] ,
+    \u_riscv_top.core0_irq_lines[14] ,
+    \u_riscv_top.core0_irq_lines[13] ,
+    \u_riscv_top.core0_irq_lines[12] ,
+    \u_riscv_top.core0_irq_lines[11] ,
+    \u_riscv_top.core0_irq_lines[10] ,
+    \u_riscv_top.core0_irq_lines[9] ,
+    \u_riscv_top.core0_irq_lines[8] ,
+    \u_riscv_top.core0_irq_lines[7] ,
+    \u_riscv_top.core0_irq_lines[6] ,
+    \u_riscv_top.core0_irq_lines[5] ,
+    \u_riscv_top.core0_irq_lines[4] ,
+    \u_riscv_top.core0_irq_lines[3] ,
+    \u_riscv_top.core0_irq_lines[2] ,
+    \u_riscv_top.core0_irq_lines[1] ,
+    \u_riscv_top.core0_irq_lines[0] }),
+    .core_mtimer_val_i({\u_riscv_top.core0_timer_val[63] ,
+    \u_riscv_top.core0_timer_val[62] ,
+    \u_riscv_top.core0_timer_val[61] ,
+    \u_riscv_top.core0_timer_val[60] ,
+    \u_riscv_top.core0_timer_val[59] ,
+    \u_riscv_top.core0_timer_val[58] ,
+    \u_riscv_top.core0_timer_val[57] ,
+    \u_riscv_top.core0_timer_val[56] ,
+    \u_riscv_top.core0_timer_val[55] ,
+    \u_riscv_top.core0_timer_val[54] ,
+    \u_riscv_top.core0_timer_val[53] ,
+    \u_riscv_top.core0_timer_val[52] ,
+    \u_riscv_top.core0_timer_val[51] ,
+    \u_riscv_top.core0_timer_val[50] ,
+    \u_riscv_top.core0_timer_val[49] ,
+    \u_riscv_top.core0_timer_val[48] ,
+    \u_riscv_top.core0_timer_val[47] ,
+    \u_riscv_top.core0_timer_val[46] ,
+    \u_riscv_top.core0_timer_val[45] ,
+    \u_riscv_top.core0_timer_val[44] ,
+    \u_riscv_top.core0_timer_val[43] ,
+    \u_riscv_top.core0_timer_val[42] ,
+    \u_riscv_top.core0_timer_val[41] ,
+    \u_riscv_top.core0_timer_val[40] ,
+    \u_riscv_top.core0_timer_val[39] ,
+    \u_riscv_top.core0_timer_val[38] ,
+    \u_riscv_top.core0_timer_val[37] ,
+    \u_riscv_top.core0_timer_val[36] ,
+    \u_riscv_top.core0_timer_val[35] ,
+    \u_riscv_top.core0_timer_val[34] ,
+    \u_riscv_top.core0_timer_val[33] ,
+    \u_riscv_top.core0_timer_val[32] ,
+    \u_riscv_top.core0_timer_val[31] ,
+    \u_riscv_top.core0_timer_val[30] ,
+    \u_riscv_top.core0_timer_val[29] ,
+    \u_riscv_top.core0_timer_val[28] ,
+    \u_riscv_top.core0_timer_val[27] ,
+    \u_riscv_top.core0_timer_val[26] ,
+    \u_riscv_top.core0_timer_val[25] ,
+    \u_riscv_top.core0_timer_val[24] ,
+    \u_riscv_top.core0_timer_val[23] ,
+    \u_riscv_top.core0_timer_val[22] ,
+    \u_riscv_top.core0_timer_val[21] ,
+    \u_riscv_top.core0_timer_val[20] ,
+    \u_riscv_top.core0_timer_val[19] ,
+    \u_riscv_top.core0_timer_val[18] ,
+    \u_riscv_top.core0_timer_val[17] ,
+    \u_riscv_top.core0_timer_val[16] ,
+    \u_riscv_top.core0_timer_val[15] ,
+    \u_riscv_top.core0_timer_val[14] ,
+    \u_riscv_top.core0_timer_val[13] ,
+    \u_riscv_top.core0_timer_val[12] ,
+    \u_riscv_top.core0_timer_val[11] ,
+    \u_riscv_top.core0_timer_val[10] ,
+    \u_riscv_top.core0_timer_val[9] ,
+    \u_riscv_top.core0_timer_val[8] ,
+    \u_riscv_top.core0_timer_val[7] ,
+    \u_riscv_top.core0_timer_val[6] ,
+    \u_riscv_top.core0_timer_val[5] ,
+    \u_riscv_top.core0_timer_val[4] ,
+    \u_riscv_top.core0_timer_val[3] ,
+    \u_riscv_top.core0_timer_val[2] ,
+    \u_riscv_top.core0_timer_val[1] ,
+    \u_riscv_top.core0_timer_val[0] }),
+    .core_uid({\u_riscv_top.core0_uid[1] ,
+    \u_riscv_top.core0_uid[0] }),
+    .dmem2core_rdata_i({\u_riscv_top.core0_dmem_rdata[31] ,
+    \u_riscv_top.core0_dmem_rdata[30] ,
+    \u_riscv_top.core0_dmem_rdata[29] ,
+    \u_riscv_top.core0_dmem_rdata[28] ,
+    \u_riscv_top.core0_dmem_rdata[27] ,
+    \u_riscv_top.core0_dmem_rdata[26] ,
+    \u_riscv_top.core0_dmem_rdata[25] ,
+    \u_riscv_top.core0_dmem_rdata[24] ,
+    \u_riscv_top.core0_dmem_rdata[23] ,
+    \u_riscv_top.core0_dmem_rdata[22] ,
+    \u_riscv_top.core0_dmem_rdata[21] ,
+    \u_riscv_top.core0_dmem_rdata[20] ,
+    \u_riscv_top.core0_dmem_rdata[19] ,
+    \u_riscv_top.core0_dmem_rdata[18] ,
+    \u_riscv_top.core0_dmem_rdata[17] ,
+    \u_riscv_top.core0_dmem_rdata[16] ,
+    \u_riscv_top.core0_dmem_rdata[15] ,
+    \u_riscv_top.core0_dmem_rdata[14] ,
+    \u_riscv_top.core0_dmem_rdata[13] ,
+    \u_riscv_top.core0_dmem_rdata[12] ,
+    \u_riscv_top.core0_dmem_rdata[11] ,
+    \u_riscv_top.core0_dmem_rdata[10] ,
+    \u_riscv_top.core0_dmem_rdata[9] ,
+    \u_riscv_top.core0_dmem_rdata[8] ,
+    \u_riscv_top.core0_dmem_rdata[7] ,
+    \u_riscv_top.core0_dmem_rdata[6] ,
+    \u_riscv_top.core0_dmem_rdata[5] ,
+    \u_riscv_top.core0_dmem_rdata[4] ,
+    \u_riscv_top.core0_dmem_rdata[3] ,
+    \u_riscv_top.core0_dmem_rdata[2] ,
+    \u_riscv_top.core0_dmem_rdata[1] ,
+    \u_riscv_top.core0_dmem_rdata[0] }),
+    .dmem2core_resp_i({\u_riscv_top.core0_dmem_resp[1] ,
+    \u_riscv_top.core0_dmem_resp[0] }),
+    .imem2core_rdata_i({\u_riscv_top.core0_imem_rdata[31] ,
+    \u_riscv_top.core0_imem_rdata[30] ,
+    \u_riscv_top.core0_imem_rdata[29] ,
+    \u_riscv_top.core0_imem_rdata[28] ,
+    \u_riscv_top.core0_imem_rdata[27] ,
+    \u_riscv_top.core0_imem_rdata[26] ,
+    \u_riscv_top.core0_imem_rdata[25] ,
+    \u_riscv_top.core0_imem_rdata[24] ,
+    \u_riscv_top.core0_imem_rdata[23] ,
+    \u_riscv_top.core0_imem_rdata[22] ,
+    \u_riscv_top.core0_imem_rdata[21] ,
+    \u_riscv_top.core0_imem_rdata[20] ,
+    \u_riscv_top.core0_imem_rdata[19] ,
+    \u_riscv_top.core0_imem_rdata[18] ,
+    \u_riscv_top.core0_imem_rdata[17] ,
+    \u_riscv_top.core0_imem_rdata[16] ,
+    \u_riscv_top.core0_imem_rdata[15] ,
+    \u_riscv_top.core0_imem_rdata[14] ,
+    \u_riscv_top.core0_imem_rdata[13] ,
+    \u_riscv_top.core0_imem_rdata[12] ,
+    \u_riscv_top.core0_imem_rdata[11] ,
+    \u_riscv_top.core0_imem_rdata[10] ,
+    \u_riscv_top.core0_imem_rdata[9] ,
+    \u_riscv_top.core0_imem_rdata[8] ,
+    \u_riscv_top.core0_imem_rdata[7] ,
+    \u_riscv_top.core0_imem_rdata[6] ,
+    \u_riscv_top.core0_imem_rdata[5] ,
+    \u_riscv_top.core0_imem_rdata[4] ,
+    \u_riscv_top.core0_imem_rdata[3] ,
+    \u_riscv_top.core0_imem_rdata[2] ,
+    \u_riscv_top.core0_imem_rdata[1] ,
+    \u_riscv_top.core0_imem_rdata[0] }),
+    .imem2core_resp_i({\u_riscv_top.core0_imem_resp[1] ,
+    \u_riscv_top.core0_imem_resp[0] }));
+ ycr_core_top \u_riscv_top.i_core_top_1  (.clk(\u_riscv_top.core_clk_core1_skew ),
+    .clk_o(\u_riscv_top.core_clk_out[1] ),
+    .core2dmem_cmd_o(\u_riscv_top.core1_dmem_cmd ),
+    .core2dmem_req_o(\u_riscv_top.core1_dmem_req ),
+    .core2imem_cmd_o(\u_riscv_top.core1_imem_cmd ),
+    .core2imem_req_o(\u_riscv_top.core1_imem_req ),
+    .core_clk_int(\u_riscv_top.core1_clk ),
+    .core_clk_skew(\u_riscv_top.core_clk_core1_skew ),
+    .core_irq_mtimer_i(\u_riscv_top.core1_timer_irq ),
+    .core_irq_soft_i(\u_riscv_top.core1_soft_irq ),
+    .cpu_rst_n(\u_riscv_top.cpu_core_rst_n[1] ),
+    .dmem2core_req_ack_i(\u_riscv_top.core1_dmem_req_ack ),
+    .imem2core_req_ack_i(\u_riscv_top.core1_imem_req_ack ),
+    .pwrup_rst_n(\u_riscv_top.pwrup_rst_n ),
+    .rst_n(\u_riscv_top.pwrup_rst_n ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .cfg_ccska({\u_riscv_top.cfg_ccska_riscv_core1[3] ,
+    \u_riscv_top.cfg_ccska_riscv_core1[2] ,
+    \u_riscv_top.cfg_ccska_riscv_core1[1] ,
+    \u_riscv_top.cfg_ccska_riscv_core1[0] }),
+    .core2dmem_addr_o({\u_riscv_top.core1_dmem_addr[31] ,
+    \u_riscv_top.core1_dmem_addr[30] ,
+    \u_riscv_top.core1_dmem_addr[29] ,
+    \u_riscv_top.core1_dmem_addr[28] ,
+    \u_riscv_top.core1_dmem_addr[27] ,
+    \u_riscv_top.core1_dmem_addr[26] ,
+    \u_riscv_top.core1_dmem_addr[25] ,
+    \u_riscv_top.core1_dmem_addr[24] ,
+    \u_riscv_top.core1_dmem_addr[23] ,
+    \u_riscv_top.core1_dmem_addr[22] ,
+    \u_riscv_top.core1_dmem_addr[21] ,
+    \u_riscv_top.core1_dmem_addr[20] ,
+    \u_riscv_top.core1_dmem_addr[19] ,
+    \u_riscv_top.core1_dmem_addr[18] ,
+    \u_riscv_top.core1_dmem_addr[17] ,
+    \u_riscv_top.core1_dmem_addr[16] ,
+    \u_riscv_top.core1_dmem_addr[15] ,
+    \u_riscv_top.core1_dmem_addr[14] ,
+    \u_riscv_top.core1_dmem_addr[13] ,
+    \u_riscv_top.core1_dmem_addr[12] ,
+    \u_riscv_top.core1_dmem_addr[11] ,
+    \u_riscv_top.core1_dmem_addr[10] ,
+    \u_riscv_top.core1_dmem_addr[9] ,
+    \u_riscv_top.core1_dmem_addr[8] ,
+    \u_riscv_top.core1_dmem_addr[7] ,
+    \u_riscv_top.core1_dmem_addr[6] ,
+    \u_riscv_top.core1_dmem_addr[5] ,
+    \u_riscv_top.core1_dmem_addr[4] ,
+    \u_riscv_top.core1_dmem_addr[3] ,
+    \u_riscv_top.core1_dmem_addr[2] ,
+    \u_riscv_top.core1_dmem_addr[1] ,
+    \u_riscv_top.core1_dmem_addr[0] }),
+    .core2dmem_wdata_o({\u_riscv_top.core1_dmem_wdata[31] ,
+    \u_riscv_top.core1_dmem_wdata[30] ,
+    \u_riscv_top.core1_dmem_wdata[29] ,
+    \u_riscv_top.core1_dmem_wdata[28] ,
+    \u_riscv_top.core1_dmem_wdata[27] ,
+    \u_riscv_top.core1_dmem_wdata[26] ,
+    \u_riscv_top.core1_dmem_wdata[25] ,
+    \u_riscv_top.core1_dmem_wdata[24] ,
+    \u_riscv_top.core1_dmem_wdata[23] ,
+    \u_riscv_top.core1_dmem_wdata[22] ,
+    \u_riscv_top.core1_dmem_wdata[21] ,
+    \u_riscv_top.core1_dmem_wdata[20] ,
+    \u_riscv_top.core1_dmem_wdata[19] ,
+    \u_riscv_top.core1_dmem_wdata[18] ,
+    \u_riscv_top.core1_dmem_wdata[17] ,
+    \u_riscv_top.core1_dmem_wdata[16] ,
+    \u_riscv_top.core1_dmem_wdata[15] ,
+    \u_riscv_top.core1_dmem_wdata[14] ,
+    \u_riscv_top.core1_dmem_wdata[13] ,
+    \u_riscv_top.core1_dmem_wdata[12] ,
+    \u_riscv_top.core1_dmem_wdata[11] ,
+    \u_riscv_top.core1_dmem_wdata[10] ,
+    \u_riscv_top.core1_dmem_wdata[9] ,
+    \u_riscv_top.core1_dmem_wdata[8] ,
+    \u_riscv_top.core1_dmem_wdata[7] ,
+    \u_riscv_top.core1_dmem_wdata[6] ,
+    \u_riscv_top.core1_dmem_wdata[5] ,
+    \u_riscv_top.core1_dmem_wdata[4] ,
+    \u_riscv_top.core1_dmem_wdata[3] ,
+    \u_riscv_top.core1_dmem_wdata[2] ,
+    \u_riscv_top.core1_dmem_wdata[1] ,
+    \u_riscv_top.core1_dmem_wdata[0] }),
+    .core2dmem_width_o({\u_riscv_top.core1_dmem_width[1] ,
+    \u_riscv_top.core1_dmem_width[0] }),
+    .core2imem_addr_o({\u_riscv_top.core1_imem_addr[31] ,
+    \u_riscv_top.core1_imem_addr[30] ,
+    \u_riscv_top.core1_imem_addr[29] ,
+    \u_riscv_top.core1_imem_addr[28] ,
+    \u_riscv_top.core1_imem_addr[27] ,
+    \u_riscv_top.core1_imem_addr[26] ,
+    \u_riscv_top.core1_imem_addr[25] ,
+    \u_riscv_top.core1_imem_addr[24] ,
+    \u_riscv_top.core1_imem_addr[23] ,
+    \u_riscv_top.core1_imem_addr[22] ,
+    \u_riscv_top.core1_imem_addr[21] ,
+    \u_riscv_top.core1_imem_addr[20] ,
+    \u_riscv_top.core1_imem_addr[19] ,
+    \u_riscv_top.core1_imem_addr[18] ,
+    \u_riscv_top.core1_imem_addr[17] ,
+    \u_riscv_top.core1_imem_addr[16] ,
+    \u_riscv_top.core1_imem_addr[15] ,
+    \u_riscv_top.core1_imem_addr[14] ,
+    \u_riscv_top.core1_imem_addr[13] ,
+    \u_riscv_top.core1_imem_addr[12] ,
+    \u_riscv_top.core1_imem_addr[11] ,
+    \u_riscv_top.core1_imem_addr[10] ,
+    \u_riscv_top.core1_imem_addr[9] ,
+    \u_riscv_top.core1_imem_addr[8] ,
+    \u_riscv_top.core1_imem_addr[7] ,
+    \u_riscv_top.core1_imem_addr[6] ,
+    \u_riscv_top.core1_imem_addr[5] ,
+    \u_riscv_top.core1_imem_addr[4] ,
+    \u_riscv_top.core1_imem_addr[3] ,
+    \u_riscv_top.core1_imem_addr[2] ,
+    \u_riscv_top.core1_imem_addr[1] ,
+    \u_riscv_top.core1_imem_addr[0] }),
+    .core2imem_bl_o({\u_riscv_top.core1_imem_bl[2] ,
+    \u_riscv_top.core1_imem_bl[1] ,
+    \u_riscv_top.core1_imem_bl[0] }),
+    .core_debug({\u_riscv_top.core1_debug[48] ,
+    \u_riscv_top.core1_debug[47] ,
+    \u_riscv_top.core1_debug[46] ,
+    \u_riscv_top.core1_debug[45] ,
+    \u_riscv_top.core1_debug[44] ,
+    \u_riscv_top.core1_debug[43] ,
+    \u_riscv_top.core1_debug[42] ,
+    \u_riscv_top.core1_debug[41] ,
+    \u_riscv_top.core1_debug[40] ,
+    \u_riscv_top.core1_debug[39] ,
+    \u_riscv_top.core1_debug[38] ,
+    \u_riscv_top.core1_debug[37] ,
+    \u_riscv_top.core1_debug[36] ,
+    \u_riscv_top.core1_debug[35] ,
+    \u_riscv_top.core1_debug[34] ,
+    \u_riscv_top.core1_debug[33] ,
+    \u_riscv_top.core1_debug[32] ,
+    \u_riscv_top.core1_debug[31] ,
+    \u_riscv_top.core1_debug[30] ,
+    \u_riscv_top.core1_debug[29] ,
+    \u_riscv_top.core1_debug[28] ,
+    \u_riscv_top.core1_debug[27] ,
+    \u_riscv_top.core1_debug[26] ,
+    \u_riscv_top.core1_debug[25] ,
+    \u_riscv_top.core1_debug[24] ,
+    \u_riscv_top.core1_debug[23] ,
+    \u_riscv_top.core1_debug[22] ,
+    \u_riscv_top.core1_debug[21] ,
+    \u_riscv_top.core1_debug[20] ,
+    \u_riscv_top.core1_debug[19] ,
+    \u_riscv_top.core1_debug[18] ,
+    \u_riscv_top.core1_debug[17] ,
+    \u_riscv_top.core1_debug[16] ,
+    \u_riscv_top.core1_debug[15] ,
+    \u_riscv_top.core1_debug[14] ,
+    \u_riscv_top.core1_debug[13] ,
+    \u_riscv_top.core1_debug[12] ,
+    \u_riscv_top.core1_debug[11] ,
+    \u_riscv_top.core1_debug[10] ,
+    \u_riscv_top.core1_debug[9] ,
+    \u_riscv_top.core1_debug[8] ,
+    \u_riscv_top.core1_debug[7] ,
+    \u_riscv_top.core1_debug[6] ,
+    \u_riscv_top.core1_debug[5] ,
+    \u_riscv_top.core1_debug[4] ,
+    \u_riscv_top.core1_debug[3] ,
+    \u_riscv_top.core1_debug[2] ,
+    \u_riscv_top.core1_debug[1] ,
+    \u_riscv_top.core1_debug[0] }),
+    .core_irq_lines_i({\u_riscv_top.core1_irq_lines[31] ,
+    \u_riscv_top.core1_irq_lines[30] ,
+    \u_riscv_top.core1_irq_lines[29] ,
+    \u_riscv_top.core1_irq_lines[28] ,
+    \u_riscv_top.core1_irq_lines[27] ,
+    \u_riscv_top.core1_irq_lines[26] ,
+    \u_riscv_top.core1_irq_lines[25] ,
+    \u_riscv_top.core1_irq_lines[24] ,
+    \u_riscv_top.core1_irq_lines[23] ,
+    \u_riscv_top.core1_irq_lines[22] ,
+    \u_riscv_top.core1_irq_lines[21] ,
+    \u_riscv_top.core1_irq_lines[20] ,
+    \u_riscv_top.core1_irq_lines[19] ,
+    \u_riscv_top.core1_irq_lines[18] ,
+    \u_riscv_top.core1_irq_lines[17] ,
+    \u_riscv_top.core1_irq_lines[16] ,
+    \u_riscv_top.core1_irq_lines[15] ,
+    \u_riscv_top.core1_irq_lines[14] ,
+    \u_riscv_top.core1_irq_lines[13] ,
+    \u_riscv_top.core1_irq_lines[12] ,
+    \u_riscv_top.core1_irq_lines[11] ,
+    \u_riscv_top.core1_irq_lines[10] ,
+    \u_riscv_top.core1_irq_lines[9] ,
+    \u_riscv_top.core1_irq_lines[8] ,
+    \u_riscv_top.core1_irq_lines[7] ,
+    \u_riscv_top.core1_irq_lines[6] ,
+    \u_riscv_top.core1_irq_lines[5] ,
+    \u_riscv_top.core1_irq_lines[4] ,
+    \u_riscv_top.core1_irq_lines[3] ,
+    \u_riscv_top.core1_irq_lines[2] ,
+    \u_riscv_top.core1_irq_lines[1] ,
+    \u_riscv_top.core1_irq_lines[0] }),
+    .core_mtimer_val_i({\u_riscv_top.core1_timer_val[63] ,
+    \u_riscv_top.core1_timer_val[62] ,
+    \u_riscv_top.core1_timer_val[61] ,
+    \u_riscv_top.core1_timer_val[60] ,
+    \u_riscv_top.core1_timer_val[59] ,
+    \u_riscv_top.core1_timer_val[58] ,
+    \u_riscv_top.core1_timer_val[57] ,
+    \u_riscv_top.core1_timer_val[56] ,
+    \u_riscv_top.core1_timer_val[55] ,
+    \u_riscv_top.core1_timer_val[54] ,
+    \u_riscv_top.core1_timer_val[53] ,
+    \u_riscv_top.core1_timer_val[52] ,
+    \u_riscv_top.core1_timer_val[51] ,
+    \u_riscv_top.core1_timer_val[50] ,
+    \u_riscv_top.core1_timer_val[49] ,
+    \u_riscv_top.core1_timer_val[48] ,
+    \u_riscv_top.core1_timer_val[47] ,
+    \u_riscv_top.core1_timer_val[46] ,
+    \u_riscv_top.core1_timer_val[45] ,
+    \u_riscv_top.core1_timer_val[44] ,
+    \u_riscv_top.core1_timer_val[43] ,
+    \u_riscv_top.core1_timer_val[42] ,
+    \u_riscv_top.core1_timer_val[41] ,
+    \u_riscv_top.core1_timer_val[40] ,
+    \u_riscv_top.core1_timer_val[39] ,
+    \u_riscv_top.core1_timer_val[38] ,
+    \u_riscv_top.core1_timer_val[37] ,
+    \u_riscv_top.core1_timer_val[36] ,
+    \u_riscv_top.core1_timer_val[35] ,
+    \u_riscv_top.core1_timer_val[34] ,
+    \u_riscv_top.core1_timer_val[33] ,
+    \u_riscv_top.core1_timer_val[32] ,
+    \u_riscv_top.core1_timer_val[31] ,
+    \u_riscv_top.core1_timer_val[30] ,
+    \u_riscv_top.core1_timer_val[29] ,
+    \u_riscv_top.core1_timer_val[28] ,
+    \u_riscv_top.core1_timer_val[27] ,
+    \u_riscv_top.core1_timer_val[26] ,
+    \u_riscv_top.core1_timer_val[25] ,
+    \u_riscv_top.core1_timer_val[24] ,
+    \u_riscv_top.core1_timer_val[23] ,
+    \u_riscv_top.core1_timer_val[22] ,
+    \u_riscv_top.core1_timer_val[21] ,
+    \u_riscv_top.core1_timer_val[20] ,
+    \u_riscv_top.core1_timer_val[19] ,
+    \u_riscv_top.core1_timer_val[18] ,
+    \u_riscv_top.core1_timer_val[17] ,
+    \u_riscv_top.core1_timer_val[16] ,
+    \u_riscv_top.core1_timer_val[15] ,
+    \u_riscv_top.core1_timer_val[14] ,
+    \u_riscv_top.core1_timer_val[13] ,
+    \u_riscv_top.core1_timer_val[12] ,
+    \u_riscv_top.core1_timer_val[11] ,
+    \u_riscv_top.core1_timer_val[10] ,
+    \u_riscv_top.core1_timer_val[9] ,
+    \u_riscv_top.core1_timer_val[8] ,
+    \u_riscv_top.core1_timer_val[7] ,
+    \u_riscv_top.core1_timer_val[6] ,
+    \u_riscv_top.core1_timer_val[5] ,
+    \u_riscv_top.core1_timer_val[4] ,
+    \u_riscv_top.core1_timer_val[3] ,
+    \u_riscv_top.core1_timer_val[2] ,
+    \u_riscv_top.core1_timer_val[1] ,
+    \u_riscv_top.core1_timer_val[0] }),
+    .core_uid({\u_riscv_top.core1_uid[1] ,
+    \u_riscv_top.core1_uid[0] }),
+    .dmem2core_rdata_i({\u_riscv_top.core1_dmem_rdata[31] ,
+    \u_riscv_top.core1_dmem_rdata[30] ,
+    \u_riscv_top.core1_dmem_rdata[29] ,
+    \u_riscv_top.core1_dmem_rdata[28] ,
+    \u_riscv_top.core1_dmem_rdata[27] ,
+    \u_riscv_top.core1_dmem_rdata[26] ,
+    \u_riscv_top.core1_dmem_rdata[25] ,
+    \u_riscv_top.core1_dmem_rdata[24] ,
+    \u_riscv_top.core1_dmem_rdata[23] ,
+    \u_riscv_top.core1_dmem_rdata[22] ,
+    \u_riscv_top.core1_dmem_rdata[21] ,
+    \u_riscv_top.core1_dmem_rdata[20] ,
+    \u_riscv_top.core1_dmem_rdata[19] ,
+    \u_riscv_top.core1_dmem_rdata[18] ,
+    \u_riscv_top.core1_dmem_rdata[17] ,
+    \u_riscv_top.core1_dmem_rdata[16] ,
+    \u_riscv_top.core1_dmem_rdata[15] ,
+    \u_riscv_top.core1_dmem_rdata[14] ,
+    \u_riscv_top.core1_dmem_rdata[13] ,
+    \u_riscv_top.core1_dmem_rdata[12] ,
+    \u_riscv_top.core1_dmem_rdata[11] ,
+    \u_riscv_top.core1_dmem_rdata[10] ,
+    \u_riscv_top.core1_dmem_rdata[9] ,
+    \u_riscv_top.core1_dmem_rdata[8] ,
+    \u_riscv_top.core1_dmem_rdata[7] ,
+    \u_riscv_top.core1_dmem_rdata[6] ,
+    \u_riscv_top.core1_dmem_rdata[5] ,
+    \u_riscv_top.core1_dmem_rdata[4] ,
+    \u_riscv_top.core1_dmem_rdata[3] ,
+    \u_riscv_top.core1_dmem_rdata[2] ,
+    \u_riscv_top.core1_dmem_rdata[1] ,
+    \u_riscv_top.core1_dmem_rdata[0] }),
+    .dmem2core_resp_i({\u_riscv_top.core1_dmem_resp[1] ,
+    \u_riscv_top.core1_dmem_resp[0] }),
+    .imem2core_rdata_i({\u_riscv_top.core1_imem_rdata[31] ,
+    \u_riscv_top.core1_imem_rdata[30] ,
+    \u_riscv_top.core1_imem_rdata[29] ,
+    \u_riscv_top.core1_imem_rdata[28] ,
+    \u_riscv_top.core1_imem_rdata[27] ,
+    \u_riscv_top.core1_imem_rdata[26] ,
+    \u_riscv_top.core1_imem_rdata[25] ,
+    \u_riscv_top.core1_imem_rdata[24] ,
+    \u_riscv_top.core1_imem_rdata[23] ,
+    \u_riscv_top.core1_imem_rdata[22] ,
+    \u_riscv_top.core1_imem_rdata[21] ,
+    \u_riscv_top.core1_imem_rdata[20] ,
+    \u_riscv_top.core1_imem_rdata[19] ,
+    \u_riscv_top.core1_imem_rdata[18] ,
+    \u_riscv_top.core1_imem_rdata[17] ,
+    \u_riscv_top.core1_imem_rdata[16] ,
+    \u_riscv_top.core1_imem_rdata[15] ,
+    \u_riscv_top.core1_imem_rdata[14] ,
+    \u_riscv_top.core1_imem_rdata[13] ,
+    \u_riscv_top.core1_imem_rdata[12] ,
+    \u_riscv_top.core1_imem_rdata[11] ,
+    \u_riscv_top.core1_imem_rdata[10] ,
+    \u_riscv_top.core1_imem_rdata[9] ,
+    \u_riscv_top.core1_imem_rdata[8] ,
+    \u_riscv_top.core1_imem_rdata[7] ,
+    \u_riscv_top.core1_imem_rdata[6] ,
+    \u_riscv_top.core1_imem_rdata[5] ,
+    \u_riscv_top.core1_imem_rdata[4] ,
+    \u_riscv_top.core1_imem_rdata[3] ,
+    \u_riscv_top.core1_imem_rdata[2] ,
+    \u_riscv_top.core1_imem_rdata[1] ,
+    \u_riscv_top.core1_imem_rdata[0] }),
+    .imem2core_resp_i({\u_riscv_top.core1_imem_resp[1] ,
+    \u_riscv_top.core1_imem_resp[0] }));
+ ycr_core_top \u_riscv_top.i_core_top_2  (.clk(\u_riscv_top.core_clk_core2_skew ),
+    .clk_o(\u_riscv_top.core_clk_out[2] ),
+    .core2dmem_cmd_o(\u_riscv_top.core2_dmem_cmd ),
+    .core2dmem_req_o(\u_riscv_top.core2_dmem_req ),
+    .core2imem_cmd_o(\u_riscv_top.core2_imem_cmd ),
+    .core2imem_req_o(\u_riscv_top.core2_imem_req ),
+    .core_clk_int(\u_riscv_top.core2_clk ),
+    .core_clk_skew(\u_riscv_top.core_clk_core2_skew ),
+    .core_irq_mtimer_i(\u_riscv_top.core2_timer_irq ),
+    .core_irq_soft_i(\u_riscv_top.core2_soft_irq ),
+    .cpu_rst_n(\u_riscv_top.cpu_core_rst_n[2] ),
+    .dmem2core_req_ack_i(\u_riscv_top.core2_dmem_req_ack ),
+    .imem2core_req_ack_i(\u_riscv_top.core2_imem_req_ack ),
+    .pwrup_rst_n(\u_riscv_top.pwrup_rst_n ),
+    .rst_n(\u_riscv_top.pwrup_rst_n ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .cfg_ccska({\u_riscv_top.cfg_ccska_riscv_core2[3] ,
+    \u_riscv_top.cfg_ccska_riscv_core2[2] ,
+    \u_riscv_top.cfg_ccska_riscv_core2[1] ,
+    \u_riscv_top.cfg_ccska_riscv_core2[0] }),
+    .core2dmem_addr_o({\u_riscv_top.core2_dmem_addr[31] ,
+    \u_riscv_top.core2_dmem_addr[30] ,
+    \u_riscv_top.core2_dmem_addr[29] ,
+    \u_riscv_top.core2_dmem_addr[28] ,
+    \u_riscv_top.core2_dmem_addr[27] ,
+    \u_riscv_top.core2_dmem_addr[26] ,
+    \u_riscv_top.core2_dmem_addr[25] ,
+    \u_riscv_top.core2_dmem_addr[24] ,
+    \u_riscv_top.core2_dmem_addr[23] ,
+    \u_riscv_top.core2_dmem_addr[22] ,
+    \u_riscv_top.core2_dmem_addr[21] ,
+    \u_riscv_top.core2_dmem_addr[20] ,
+    \u_riscv_top.core2_dmem_addr[19] ,
+    \u_riscv_top.core2_dmem_addr[18] ,
+    \u_riscv_top.core2_dmem_addr[17] ,
+    \u_riscv_top.core2_dmem_addr[16] ,
+    \u_riscv_top.core2_dmem_addr[15] ,
+    \u_riscv_top.core2_dmem_addr[14] ,
+    \u_riscv_top.core2_dmem_addr[13] ,
+    \u_riscv_top.core2_dmem_addr[12] ,
+    \u_riscv_top.core2_dmem_addr[11] ,
+    \u_riscv_top.core2_dmem_addr[10] ,
+    \u_riscv_top.core2_dmem_addr[9] ,
+    \u_riscv_top.core2_dmem_addr[8] ,
+    \u_riscv_top.core2_dmem_addr[7] ,
+    \u_riscv_top.core2_dmem_addr[6] ,
+    \u_riscv_top.core2_dmem_addr[5] ,
+    \u_riscv_top.core2_dmem_addr[4] ,
+    \u_riscv_top.core2_dmem_addr[3] ,
+    \u_riscv_top.core2_dmem_addr[2] ,
+    \u_riscv_top.core2_dmem_addr[1] ,
+    \u_riscv_top.core2_dmem_addr[0] }),
+    .core2dmem_wdata_o({\u_riscv_top.core2_dmem_wdata[31] ,
+    \u_riscv_top.core2_dmem_wdata[30] ,
+    \u_riscv_top.core2_dmem_wdata[29] ,
+    \u_riscv_top.core2_dmem_wdata[28] ,
+    \u_riscv_top.core2_dmem_wdata[27] ,
+    \u_riscv_top.core2_dmem_wdata[26] ,
+    \u_riscv_top.core2_dmem_wdata[25] ,
+    \u_riscv_top.core2_dmem_wdata[24] ,
+    \u_riscv_top.core2_dmem_wdata[23] ,
+    \u_riscv_top.core2_dmem_wdata[22] ,
+    \u_riscv_top.core2_dmem_wdata[21] ,
+    \u_riscv_top.core2_dmem_wdata[20] ,
+    \u_riscv_top.core2_dmem_wdata[19] ,
+    \u_riscv_top.core2_dmem_wdata[18] ,
+    \u_riscv_top.core2_dmem_wdata[17] ,
+    \u_riscv_top.core2_dmem_wdata[16] ,
+    \u_riscv_top.core2_dmem_wdata[15] ,
+    \u_riscv_top.core2_dmem_wdata[14] ,
+    \u_riscv_top.core2_dmem_wdata[13] ,
+    \u_riscv_top.core2_dmem_wdata[12] ,
+    \u_riscv_top.core2_dmem_wdata[11] ,
+    \u_riscv_top.core2_dmem_wdata[10] ,
+    \u_riscv_top.core2_dmem_wdata[9] ,
+    \u_riscv_top.core2_dmem_wdata[8] ,
+    \u_riscv_top.core2_dmem_wdata[7] ,
+    \u_riscv_top.core2_dmem_wdata[6] ,
+    \u_riscv_top.core2_dmem_wdata[5] ,
+    \u_riscv_top.core2_dmem_wdata[4] ,
+    \u_riscv_top.core2_dmem_wdata[3] ,
+    \u_riscv_top.core2_dmem_wdata[2] ,
+    \u_riscv_top.core2_dmem_wdata[1] ,
+    \u_riscv_top.core2_dmem_wdata[0] }),
+    .core2dmem_width_o({\u_riscv_top.core2_dmem_width[1] ,
+    \u_riscv_top.core2_dmem_width[0] }),
+    .core2imem_addr_o({\u_riscv_top.core2_imem_addr[31] ,
+    \u_riscv_top.core2_imem_addr[30] ,
+    \u_riscv_top.core2_imem_addr[29] ,
+    \u_riscv_top.core2_imem_addr[28] ,
+    \u_riscv_top.core2_imem_addr[27] ,
+    \u_riscv_top.core2_imem_addr[26] ,
+    \u_riscv_top.core2_imem_addr[25] ,
+    \u_riscv_top.core2_imem_addr[24] ,
+    \u_riscv_top.core2_imem_addr[23] ,
+    \u_riscv_top.core2_imem_addr[22] ,
+    \u_riscv_top.core2_imem_addr[21] ,
+    \u_riscv_top.core2_imem_addr[20] ,
+    \u_riscv_top.core2_imem_addr[19] ,
+    \u_riscv_top.core2_imem_addr[18] ,
+    \u_riscv_top.core2_imem_addr[17] ,
+    \u_riscv_top.core2_imem_addr[16] ,
+    \u_riscv_top.core2_imem_addr[15] ,
+    \u_riscv_top.core2_imem_addr[14] ,
+    \u_riscv_top.core2_imem_addr[13] ,
+    \u_riscv_top.core2_imem_addr[12] ,
+    \u_riscv_top.core2_imem_addr[11] ,
+    \u_riscv_top.core2_imem_addr[10] ,
+    \u_riscv_top.core2_imem_addr[9] ,
+    \u_riscv_top.core2_imem_addr[8] ,
+    \u_riscv_top.core2_imem_addr[7] ,
+    \u_riscv_top.core2_imem_addr[6] ,
+    \u_riscv_top.core2_imem_addr[5] ,
+    \u_riscv_top.core2_imem_addr[4] ,
+    \u_riscv_top.core2_imem_addr[3] ,
+    \u_riscv_top.core2_imem_addr[2] ,
+    \u_riscv_top.core2_imem_addr[1] ,
+    \u_riscv_top.core2_imem_addr[0] }),
+    .core2imem_bl_o({\u_riscv_top.core2_imem_bl[2] ,
+    \u_riscv_top.core2_imem_bl[1] ,
+    \u_riscv_top.core2_imem_bl[0] }),
+    .core_debug({\u_riscv_top.core2_debug[48] ,
+    \u_riscv_top.core2_debug[47] ,
+    \u_riscv_top.core2_debug[46] ,
+    \u_riscv_top.core2_debug[45] ,
+    \u_riscv_top.core2_debug[44] ,
+    \u_riscv_top.core2_debug[43] ,
+    \u_riscv_top.core2_debug[42] ,
+    \u_riscv_top.core2_debug[41] ,
+    \u_riscv_top.core2_debug[40] ,
+    \u_riscv_top.core2_debug[39] ,
+    \u_riscv_top.core2_debug[38] ,
+    \u_riscv_top.core2_debug[37] ,
+    \u_riscv_top.core2_debug[36] ,
+    \u_riscv_top.core2_debug[35] ,
+    \u_riscv_top.core2_debug[34] ,
+    \u_riscv_top.core2_debug[33] ,
+    \u_riscv_top.core2_debug[32] ,
+    \u_riscv_top.core2_debug[31] ,
+    \u_riscv_top.core2_debug[30] ,
+    \u_riscv_top.core2_debug[29] ,
+    \u_riscv_top.core2_debug[28] ,
+    \u_riscv_top.core2_debug[27] ,
+    \u_riscv_top.core2_debug[26] ,
+    \u_riscv_top.core2_debug[25] ,
+    \u_riscv_top.core2_debug[24] ,
+    \u_riscv_top.core2_debug[23] ,
+    \u_riscv_top.core2_debug[22] ,
+    \u_riscv_top.core2_debug[21] ,
+    \u_riscv_top.core2_debug[20] ,
+    \u_riscv_top.core2_debug[19] ,
+    \u_riscv_top.core2_debug[18] ,
+    \u_riscv_top.core2_debug[17] ,
+    \u_riscv_top.core2_debug[16] ,
+    \u_riscv_top.core2_debug[15] ,
+    \u_riscv_top.core2_debug[14] ,
+    \u_riscv_top.core2_debug[13] ,
+    \u_riscv_top.core2_debug[12] ,
+    \u_riscv_top.core2_debug[11] ,
+    \u_riscv_top.core2_debug[10] ,
+    \u_riscv_top.core2_debug[9] ,
+    \u_riscv_top.core2_debug[8] ,
+    \u_riscv_top.core2_debug[7] ,
+    \u_riscv_top.core2_debug[6] ,
+    \u_riscv_top.core2_debug[5] ,
+    \u_riscv_top.core2_debug[4] ,
+    \u_riscv_top.core2_debug[3] ,
+    \u_riscv_top.core2_debug[2] ,
+    \u_riscv_top.core2_debug[1] ,
+    \u_riscv_top.core2_debug[0] }),
+    .core_irq_lines_i({\u_riscv_top.core2_irq_lines[31] ,
+    \u_riscv_top.core2_irq_lines[30] ,
+    \u_riscv_top.core2_irq_lines[29] ,
+    \u_riscv_top.core2_irq_lines[28] ,
+    \u_riscv_top.core2_irq_lines[27] ,
+    \u_riscv_top.core2_irq_lines[26] ,
+    \u_riscv_top.core2_irq_lines[25] ,
+    \u_riscv_top.core2_irq_lines[24] ,
+    \u_riscv_top.core2_irq_lines[23] ,
+    \u_riscv_top.core2_irq_lines[22] ,
+    \u_riscv_top.core2_irq_lines[21] ,
+    \u_riscv_top.core2_irq_lines[20] ,
+    \u_riscv_top.core2_irq_lines[19] ,
+    \u_riscv_top.core2_irq_lines[18] ,
+    \u_riscv_top.core2_irq_lines[17] ,
+    \u_riscv_top.core2_irq_lines[16] ,
+    \u_riscv_top.core2_irq_lines[15] ,
+    \u_riscv_top.core2_irq_lines[14] ,
+    \u_riscv_top.core2_irq_lines[13] ,
+    \u_riscv_top.core2_irq_lines[12] ,
+    \u_riscv_top.core2_irq_lines[11] ,
+    \u_riscv_top.core2_irq_lines[10] ,
+    \u_riscv_top.core2_irq_lines[9] ,
+    \u_riscv_top.core2_irq_lines[8] ,
+    \u_riscv_top.core2_irq_lines[7] ,
+    \u_riscv_top.core2_irq_lines[6] ,
+    \u_riscv_top.core2_irq_lines[5] ,
+    \u_riscv_top.core2_irq_lines[4] ,
+    \u_riscv_top.core2_irq_lines[3] ,
+    \u_riscv_top.core2_irq_lines[2] ,
+    \u_riscv_top.core2_irq_lines[1] ,
+    \u_riscv_top.core2_irq_lines[0] }),
+    .core_mtimer_val_i({\u_riscv_top.core2_timer_val[63] ,
+    \u_riscv_top.core2_timer_val[62] ,
+    \u_riscv_top.core2_timer_val[61] ,
+    \u_riscv_top.core2_timer_val[60] ,
+    \u_riscv_top.core2_timer_val[59] ,
+    \u_riscv_top.core2_timer_val[58] ,
+    \u_riscv_top.core2_timer_val[57] ,
+    \u_riscv_top.core2_timer_val[56] ,
+    \u_riscv_top.core2_timer_val[55] ,
+    \u_riscv_top.core2_timer_val[54] ,
+    \u_riscv_top.core2_timer_val[53] ,
+    \u_riscv_top.core2_timer_val[52] ,
+    \u_riscv_top.core2_timer_val[51] ,
+    \u_riscv_top.core2_timer_val[50] ,
+    \u_riscv_top.core2_timer_val[49] ,
+    \u_riscv_top.core2_timer_val[48] ,
+    \u_riscv_top.core2_timer_val[47] ,
+    \u_riscv_top.core2_timer_val[46] ,
+    \u_riscv_top.core2_timer_val[45] ,
+    \u_riscv_top.core2_timer_val[44] ,
+    \u_riscv_top.core2_timer_val[43] ,
+    \u_riscv_top.core2_timer_val[42] ,
+    \u_riscv_top.core2_timer_val[41] ,
+    \u_riscv_top.core2_timer_val[40] ,
+    \u_riscv_top.core2_timer_val[39] ,
+    \u_riscv_top.core2_timer_val[38] ,
+    \u_riscv_top.core2_timer_val[37] ,
+    \u_riscv_top.core2_timer_val[36] ,
+    \u_riscv_top.core2_timer_val[35] ,
+    \u_riscv_top.core2_timer_val[34] ,
+    \u_riscv_top.core2_timer_val[33] ,
+    \u_riscv_top.core2_timer_val[32] ,
+    \u_riscv_top.core2_timer_val[31] ,
+    \u_riscv_top.core2_timer_val[30] ,
+    \u_riscv_top.core2_timer_val[29] ,
+    \u_riscv_top.core2_timer_val[28] ,
+    \u_riscv_top.core2_timer_val[27] ,
+    \u_riscv_top.core2_timer_val[26] ,
+    \u_riscv_top.core2_timer_val[25] ,
+    \u_riscv_top.core2_timer_val[24] ,
+    \u_riscv_top.core2_timer_val[23] ,
+    \u_riscv_top.core2_timer_val[22] ,
+    \u_riscv_top.core2_timer_val[21] ,
+    \u_riscv_top.core2_timer_val[20] ,
+    \u_riscv_top.core2_timer_val[19] ,
+    \u_riscv_top.core2_timer_val[18] ,
+    \u_riscv_top.core2_timer_val[17] ,
+    \u_riscv_top.core2_timer_val[16] ,
+    \u_riscv_top.core2_timer_val[15] ,
+    \u_riscv_top.core2_timer_val[14] ,
+    \u_riscv_top.core2_timer_val[13] ,
+    \u_riscv_top.core2_timer_val[12] ,
+    \u_riscv_top.core2_timer_val[11] ,
+    \u_riscv_top.core2_timer_val[10] ,
+    \u_riscv_top.core2_timer_val[9] ,
+    \u_riscv_top.core2_timer_val[8] ,
+    \u_riscv_top.core2_timer_val[7] ,
+    \u_riscv_top.core2_timer_val[6] ,
+    \u_riscv_top.core2_timer_val[5] ,
+    \u_riscv_top.core2_timer_val[4] ,
+    \u_riscv_top.core2_timer_val[3] ,
+    \u_riscv_top.core2_timer_val[2] ,
+    \u_riscv_top.core2_timer_val[1] ,
+    \u_riscv_top.core2_timer_val[0] }),
+    .core_uid({\u_riscv_top.core2_uid[1] ,
+    \u_riscv_top.core2_uid[0] }),
+    .dmem2core_rdata_i({\u_riscv_top.core2_dmem_rdata[31] ,
+    \u_riscv_top.core2_dmem_rdata[30] ,
+    \u_riscv_top.core2_dmem_rdata[29] ,
+    \u_riscv_top.core2_dmem_rdata[28] ,
+    \u_riscv_top.core2_dmem_rdata[27] ,
+    \u_riscv_top.core2_dmem_rdata[26] ,
+    \u_riscv_top.core2_dmem_rdata[25] ,
+    \u_riscv_top.core2_dmem_rdata[24] ,
+    \u_riscv_top.core2_dmem_rdata[23] ,
+    \u_riscv_top.core2_dmem_rdata[22] ,
+    \u_riscv_top.core2_dmem_rdata[21] ,
+    \u_riscv_top.core2_dmem_rdata[20] ,
+    \u_riscv_top.core2_dmem_rdata[19] ,
+    \u_riscv_top.core2_dmem_rdata[18] ,
+    \u_riscv_top.core2_dmem_rdata[17] ,
+    \u_riscv_top.core2_dmem_rdata[16] ,
+    \u_riscv_top.core2_dmem_rdata[15] ,
+    \u_riscv_top.core2_dmem_rdata[14] ,
+    \u_riscv_top.core2_dmem_rdata[13] ,
+    \u_riscv_top.core2_dmem_rdata[12] ,
+    \u_riscv_top.core2_dmem_rdata[11] ,
+    \u_riscv_top.core2_dmem_rdata[10] ,
+    \u_riscv_top.core2_dmem_rdata[9] ,
+    \u_riscv_top.core2_dmem_rdata[8] ,
+    \u_riscv_top.core2_dmem_rdata[7] ,
+    \u_riscv_top.core2_dmem_rdata[6] ,
+    \u_riscv_top.core2_dmem_rdata[5] ,
+    \u_riscv_top.core2_dmem_rdata[4] ,
+    \u_riscv_top.core2_dmem_rdata[3] ,
+    \u_riscv_top.core2_dmem_rdata[2] ,
+    \u_riscv_top.core2_dmem_rdata[1] ,
+    \u_riscv_top.core2_dmem_rdata[0] }),
+    .dmem2core_resp_i({\u_riscv_top.core2_dmem_resp[1] ,
+    \u_riscv_top.core2_dmem_resp[0] }),
+    .imem2core_rdata_i({\u_riscv_top.core2_imem_rdata[31] ,
+    \u_riscv_top.core2_imem_rdata[30] ,
+    \u_riscv_top.core2_imem_rdata[29] ,
+    \u_riscv_top.core2_imem_rdata[28] ,
+    \u_riscv_top.core2_imem_rdata[27] ,
+    \u_riscv_top.core2_imem_rdata[26] ,
+    \u_riscv_top.core2_imem_rdata[25] ,
+    \u_riscv_top.core2_imem_rdata[24] ,
+    \u_riscv_top.core2_imem_rdata[23] ,
+    \u_riscv_top.core2_imem_rdata[22] ,
+    \u_riscv_top.core2_imem_rdata[21] ,
+    \u_riscv_top.core2_imem_rdata[20] ,
+    \u_riscv_top.core2_imem_rdata[19] ,
+    \u_riscv_top.core2_imem_rdata[18] ,
+    \u_riscv_top.core2_imem_rdata[17] ,
+    \u_riscv_top.core2_imem_rdata[16] ,
+    \u_riscv_top.core2_imem_rdata[15] ,
+    \u_riscv_top.core2_imem_rdata[14] ,
+    \u_riscv_top.core2_imem_rdata[13] ,
+    \u_riscv_top.core2_imem_rdata[12] ,
+    \u_riscv_top.core2_imem_rdata[11] ,
+    \u_riscv_top.core2_imem_rdata[10] ,
+    \u_riscv_top.core2_imem_rdata[9] ,
+    \u_riscv_top.core2_imem_rdata[8] ,
+    \u_riscv_top.core2_imem_rdata[7] ,
+    \u_riscv_top.core2_imem_rdata[6] ,
+    \u_riscv_top.core2_imem_rdata[5] ,
+    \u_riscv_top.core2_imem_rdata[4] ,
+    \u_riscv_top.core2_imem_rdata[3] ,
+    \u_riscv_top.core2_imem_rdata[2] ,
+    \u_riscv_top.core2_imem_rdata[1] ,
+    \u_riscv_top.core2_imem_rdata[0] }),
+    .imem2core_resp_i({\u_riscv_top.core2_imem_resp[1] ,
+    \u_riscv_top.core2_imem_resp[0] }));
+ ycr_core_top \u_riscv_top.i_core_top_3  (.clk(\u_riscv_top.core_clk_core3_skew ),
+    .clk_o(\u_riscv_top.core_clk_out[3] ),
+    .core2dmem_cmd_o(\u_riscv_top.core3_dmem_cmd ),
+    .core2dmem_req_o(\u_riscv_top.core3_dmem_req ),
+    .core2imem_cmd_o(\u_riscv_top.core3_imem_cmd ),
+    .core2imem_req_o(\u_riscv_top.core3_imem_req ),
+    .core_clk_int(\u_riscv_top.core3_clk ),
+    .core_clk_skew(\u_riscv_top.core_clk_core3_skew ),
+    .core_irq_mtimer_i(\u_riscv_top.core3_timer_irq ),
+    .core_irq_soft_i(\u_riscv_top.core3_soft_irq ),
+    .cpu_rst_n(\u_riscv_top.cpu_core_rst_n[3] ),
+    .dmem2core_req_ack_i(\u_riscv_top.core3_dmem_req_ack ),
+    .imem2core_req_ack_i(\u_riscv_top.core3_imem_req_ack ),
+    .pwrup_rst_n(\u_riscv_top.pwrup_rst_n ),
+    .rst_n(\u_riscv_top.pwrup_rst_n ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .cfg_ccska({\u_riscv_top.cfg_ccska_riscv_core3[3] ,
+    \u_riscv_top.cfg_ccska_riscv_core3[2] ,
+    \u_riscv_top.cfg_ccska_riscv_core3[1] ,
+    \u_riscv_top.cfg_ccska_riscv_core3[0] }),
+    .core2dmem_addr_o({\u_riscv_top.core3_dmem_addr[31] ,
+    \u_riscv_top.core3_dmem_addr[30] ,
+    \u_riscv_top.core3_dmem_addr[29] ,
+    \u_riscv_top.core3_dmem_addr[28] ,
+    \u_riscv_top.core3_dmem_addr[27] ,
+    \u_riscv_top.core3_dmem_addr[26] ,
+    \u_riscv_top.core3_dmem_addr[25] ,
+    \u_riscv_top.core3_dmem_addr[24] ,
+    \u_riscv_top.core3_dmem_addr[23] ,
+    \u_riscv_top.core3_dmem_addr[22] ,
+    \u_riscv_top.core3_dmem_addr[21] ,
+    \u_riscv_top.core3_dmem_addr[20] ,
+    \u_riscv_top.core3_dmem_addr[19] ,
+    \u_riscv_top.core3_dmem_addr[18] ,
+    \u_riscv_top.core3_dmem_addr[17] ,
+    \u_riscv_top.core3_dmem_addr[16] ,
+    \u_riscv_top.core3_dmem_addr[15] ,
+    \u_riscv_top.core3_dmem_addr[14] ,
+    \u_riscv_top.core3_dmem_addr[13] ,
+    \u_riscv_top.core3_dmem_addr[12] ,
+    \u_riscv_top.core3_dmem_addr[11] ,
+    \u_riscv_top.core3_dmem_addr[10] ,
+    \u_riscv_top.core3_dmem_addr[9] ,
+    \u_riscv_top.core3_dmem_addr[8] ,
+    \u_riscv_top.core3_dmem_addr[7] ,
+    \u_riscv_top.core3_dmem_addr[6] ,
+    \u_riscv_top.core3_dmem_addr[5] ,
+    \u_riscv_top.core3_dmem_addr[4] ,
+    \u_riscv_top.core3_dmem_addr[3] ,
+    \u_riscv_top.core3_dmem_addr[2] ,
+    \u_riscv_top.core3_dmem_addr[1] ,
+    \u_riscv_top.core3_dmem_addr[0] }),
+    .core2dmem_wdata_o({\u_riscv_top.core3_dmem_wdata[31] ,
+    \u_riscv_top.core3_dmem_wdata[30] ,
+    \u_riscv_top.core3_dmem_wdata[29] ,
+    \u_riscv_top.core3_dmem_wdata[28] ,
+    \u_riscv_top.core3_dmem_wdata[27] ,
+    \u_riscv_top.core3_dmem_wdata[26] ,
+    \u_riscv_top.core3_dmem_wdata[25] ,
+    \u_riscv_top.core3_dmem_wdata[24] ,
+    \u_riscv_top.core3_dmem_wdata[23] ,
+    \u_riscv_top.core3_dmem_wdata[22] ,
+    \u_riscv_top.core3_dmem_wdata[21] ,
+    \u_riscv_top.core3_dmem_wdata[20] ,
+    \u_riscv_top.core3_dmem_wdata[19] ,
+    \u_riscv_top.core3_dmem_wdata[18] ,
+    \u_riscv_top.core3_dmem_wdata[17] ,
+    \u_riscv_top.core3_dmem_wdata[16] ,
+    \u_riscv_top.core3_dmem_wdata[15] ,
+    \u_riscv_top.core3_dmem_wdata[14] ,
+    \u_riscv_top.core3_dmem_wdata[13] ,
+    \u_riscv_top.core3_dmem_wdata[12] ,
+    \u_riscv_top.core3_dmem_wdata[11] ,
+    \u_riscv_top.core3_dmem_wdata[10] ,
+    \u_riscv_top.core3_dmem_wdata[9] ,
+    \u_riscv_top.core3_dmem_wdata[8] ,
+    \u_riscv_top.core3_dmem_wdata[7] ,
+    \u_riscv_top.core3_dmem_wdata[6] ,
+    \u_riscv_top.core3_dmem_wdata[5] ,
+    \u_riscv_top.core3_dmem_wdata[4] ,
+    \u_riscv_top.core3_dmem_wdata[3] ,
+    \u_riscv_top.core3_dmem_wdata[2] ,
+    \u_riscv_top.core3_dmem_wdata[1] ,
+    \u_riscv_top.core3_dmem_wdata[0] }),
+    .core2dmem_width_o({\u_riscv_top.core3_dmem_width[1] ,
+    \u_riscv_top.core3_dmem_width[0] }),
+    .core2imem_addr_o({\u_riscv_top.core3_imem_addr[31] ,
+    \u_riscv_top.core3_imem_addr[30] ,
+    \u_riscv_top.core3_imem_addr[29] ,
+    \u_riscv_top.core3_imem_addr[28] ,
+    \u_riscv_top.core3_imem_addr[27] ,
+    \u_riscv_top.core3_imem_addr[26] ,
+    \u_riscv_top.core3_imem_addr[25] ,
+    \u_riscv_top.core3_imem_addr[24] ,
+    \u_riscv_top.core3_imem_addr[23] ,
+    \u_riscv_top.core3_imem_addr[22] ,
+    \u_riscv_top.core3_imem_addr[21] ,
+    \u_riscv_top.core3_imem_addr[20] ,
+    \u_riscv_top.core3_imem_addr[19] ,
+    \u_riscv_top.core3_imem_addr[18] ,
+    \u_riscv_top.core3_imem_addr[17] ,
+    \u_riscv_top.core3_imem_addr[16] ,
+    \u_riscv_top.core3_imem_addr[15] ,
+    \u_riscv_top.core3_imem_addr[14] ,
+    \u_riscv_top.core3_imem_addr[13] ,
+    \u_riscv_top.core3_imem_addr[12] ,
+    \u_riscv_top.core3_imem_addr[11] ,
+    \u_riscv_top.core3_imem_addr[10] ,
+    \u_riscv_top.core3_imem_addr[9] ,
+    \u_riscv_top.core3_imem_addr[8] ,
+    \u_riscv_top.core3_imem_addr[7] ,
+    \u_riscv_top.core3_imem_addr[6] ,
+    \u_riscv_top.core3_imem_addr[5] ,
+    \u_riscv_top.core3_imem_addr[4] ,
+    \u_riscv_top.core3_imem_addr[3] ,
+    \u_riscv_top.core3_imem_addr[2] ,
+    \u_riscv_top.core3_imem_addr[1] ,
+    \u_riscv_top.core3_imem_addr[0] }),
+    .core2imem_bl_o({\u_riscv_top.core3_imem_bl[2] ,
+    \u_riscv_top.core3_imem_bl[1] ,
+    \u_riscv_top.core3_imem_bl[0] }),
+    .core_debug({\u_riscv_top.core3_debug[48] ,
+    \u_riscv_top.core3_debug[47] ,
+    \u_riscv_top.core3_debug[46] ,
+    \u_riscv_top.core3_debug[45] ,
+    \u_riscv_top.core3_debug[44] ,
+    \u_riscv_top.core3_debug[43] ,
+    \u_riscv_top.core3_debug[42] ,
+    \u_riscv_top.core3_debug[41] ,
+    \u_riscv_top.core3_debug[40] ,
+    \u_riscv_top.core3_debug[39] ,
+    \u_riscv_top.core3_debug[38] ,
+    \u_riscv_top.core3_debug[37] ,
+    \u_riscv_top.core3_debug[36] ,
+    \u_riscv_top.core3_debug[35] ,
+    \u_riscv_top.core3_debug[34] ,
+    \u_riscv_top.core3_debug[33] ,
+    \u_riscv_top.core3_debug[32] ,
+    \u_riscv_top.core3_debug[31] ,
+    \u_riscv_top.core3_debug[30] ,
+    \u_riscv_top.core3_debug[29] ,
+    \u_riscv_top.core3_debug[28] ,
+    \u_riscv_top.core3_debug[27] ,
+    \u_riscv_top.core3_debug[26] ,
+    \u_riscv_top.core3_debug[25] ,
+    \u_riscv_top.core3_debug[24] ,
+    \u_riscv_top.core3_debug[23] ,
+    \u_riscv_top.core3_debug[22] ,
+    \u_riscv_top.core3_debug[21] ,
+    \u_riscv_top.core3_debug[20] ,
+    \u_riscv_top.core3_debug[19] ,
+    \u_riscv_top.core3_debug[18] ,
+    \u_riscv_top.core3_debug[17] ,
+    \u_riscv_top.core3_debug[16] ,
+    \u_riscv_top.core3_debug[15] ,
+    \u_riscv_top.core3_debug[14] ,
+    \u_riscv_top.core3_debug[13] ,
+    \u_riscv_top.core3_debug[12] ,
+    \u_riscv_top.core3_debug[11] ,
+    \u_riscv_top.core3_debug[10] ,
+    \u_riscv_top.core3_debug[9] ,
+    \u_riscv_top.core3_debug[8] ,
+    \u_riscv_top.core3_debug[7] ,
+    \u_riscv_top.core3_debug[6] ,
+    \u_riscv_top.core3_debug[5] ,
+    \u_riscv_top.core3_debug[4] ,
+    \u_riscv_top.core3_debug[3] ,
+    \u_riscv_top.core3_debug[2] ,
+    \u_riscv_top.core3_debug[1] ,
+    \u_riscv_top.core3_debug[0] }),
+    .core_irq_lines_i({\u_riscv_top.core3_irq_lines[31] ,
+    \u_riscv_top.core3_irq_lines[30] ,
+    \u_riscv_top.core3_irq_lines[29] ,
+    \u_riscv_top.core3_irq_lines[28] ,
+    \u_riscv_top.core3_irq_lines[27] ,
+    \u_riscv_top.core3_irq_lines[26] ,
+    \u_riscv_top.core3_irq_lines[25] ,
+    \u_riscv_top.core3_irq_lines[24] ,
+    \u_riscv_top.core3_irq_lines[23] ,
+    \u_riscv_top.core3_irq_lines[22] ,
+    \u_riscv_top.core3_irq_lines[21] ,
+    \u_riscv_top.core3_irq_lines[20] ,
+    \u_riscv_top.core3_irq_lines[19] ,
+    \u_riscv_top.core3_irq_lines[18] ,
+    \u_riscv_top.core3_irq_lines[17] ,
+    \u_riscv_top.core3_irq_lines[16] ,
+    \u_riscv_top.core3_irq_lines[15] ,
+    \u_riscv_top.core3_irq_lines[14] ,
+    \u_riscv_top.core3_irq_lines[13] ,
+    \u_riscv_top.core3_irq_lines[12] ,
+    \u_riscv_top.core3_irq_lines[11] ,
+    \u_riscv_top.core3_irq_lines[10] ,
+    \u_riscv_top.core3_irq_lines[9] ,
+    \u_riscv_top.core3_irq_lines[8] ,
+    \u_riscv_top.core3_irq_lines[7] ,
+    \u_riscv_top.core3_irq_lines[6] ,
+    \u_riscv_top.core3_irq_lines[5] ,
+    \u_riscv_top.core3_irq_lines[4] ,
+    \u_riscv_top.core3_irq_lines[3] ,
+    \u_riscv_top.core3_irq_lines[2] ,
+    \u_riscv_top.core3_irq_lines[1] ,
+    \u_riscv_top.core3_irq_lines[0] }),
+    .core_mtimer_val_i({\u_riscv_top.core3_timer_val[63] ,
+    \u_riscv_top.core3_timer_val[62] ,
+    \u_riscv_top.core3_timer_val[61] ,
+    \u_riscv_top.core3_timer_val[60] ,
+    \u_riscv_top.core3_timer_val[59] ,
+    \u_riscv_top.core3_timer_val[58] ,
+    \u_riscv_top.core3_timer_val[57] ,
+    \u_riscv_top.core3_timer_val[56] ,
+    \u_riscv_top.core3_timer_val[55] ,
+    \u_riscv_top.core3_timer_val[54] ,
+    \u_riscv_top.core3_timer_val[53] ,
+    \u_riscv_top.core3_timer_val[52] ,
+    \u_riscv_top.core3_timer_val[51] ,
+    \u_riscv_top.core3_timer_val[50] ,
+    \u_riscv_top.core3_timer_val[49] ,
+    \u_riscv_top.core3_timer_val[48] ,
+    \u_riscv_top.core3_timer_val[47] ,
+    \u_riscv_top.core3_timer_val[46] ,
+    \u_riscv_top.core3_timer_val[45] ,
+    \u_riscv_top.core3_timer_val[44] ,
+    \u_riscv_top.core3_timer_val[43] ,
+    \u_riscv_top.core3_timer_val[42] ,
+    \u_riscv_top.core3_timer_val[41] ,
+    \u_riscv_top.core3_timer_val[40] ,
+    \u_riscv_top.core3_timer_val[39] ,
+    \u_riscv_top.core3_timer_val[38] ,
+    \u_riscv_top.core3_timer_val[37] ,
+    \u_riscv_top.core3_timer_val[36] ,
+    \u_riscv_top.core3_timer_val[35] ,
+    \u_riscv_top.core3_timer_val[34] ,
+    \u_riscv_top.core3_timer_val[33] ,
+    \u_riscv_top.core3_timer_val[32] ,
+    \u_riscv_top.core3_timer_val[31] ,
+    \u_riscv_top.core3_timer_val[30] ,
+    \u_riscv_top.core3_timer_val[29] ,
+    \u_riscv_top.core3_timer_val[28] ,
+    \u_riscv_top.core3_timer_val[27] ,
+    \u_riscv_top.core3_timer_val[26] ,
+    \u_riscv_top.core3_timer_val[25] ,
+    \u_riscv_top.core3_timer_val[24] ,
+    \u_riscv_top.core3_timer_val[23] ,
+    \u_riscv_top.core3_timer_val[22] ,
+    \u_riscv_top.core3_timer_val[21] ,
+    \u_riscv_top.core3_timer_val[20] ,
+    \u_riscv_top.core3_timer_val[19] ,
+    \u_riscv_top.core3_timer_val[18] ,
+    \u_riscv_top.core3_timer_val[17] ,
+    \u_riscv_top.core3_timer_val[16] ,
+    \u_riscv_top.core3_timer_val[15] ,
+    \u_riscv_top.core3_timer_val[14] ,
+    \u_riscv_top.core3_timer_val[13] ,
+    \u_riscv_top.core3_timer_val[12] ,
+    \u_riscv_top.core3_timer_val[11] ,
+    \u_riscv_top.core3_timer_val[10] ,
+    \u_riscv_top.core3_timer_val[9] ,
+    \u_riscv_top.core3_timer_val[8] ,
+    \u_riscv_top.core3_timer_val[7] ,
+    \u_riscv_top.core3_timer_val[6] ,
+    \u_riscv_top.core3_timer_val[5] ,
+    \u_riscv_top.core3_timer_val[4] ,
+    \u_riscv_top.core3_timer_val[3] ,
+    \u_riscv_top.core3_timer_val[2] ,
+    \u_riscv_top.core3_timer_val[1] ,
+    \u_riscv_top.core3_timer_val[0] }),
+    .core_uid({\u_riscv_top.core3_uid[1] ,
+    \u_riscv_top.core3_uid[0] }),
+    .dmem2core_rdata_i({\u_riscv_top.core3_dmem_rdata[31] ,
+    \u_riscv_top.core3_dmem_rdata[30] ,
+    \u_riscv_top.core3_dmem_rdata[29] ,
+    \u_riscv_top.core3_dmem_rdata[28] ,
+    \u_riscv_top.core3_dmem_rdata[27] ,
+    \u_riscv_top.core3_dmem_rdata[26] ,
+    \u_riscv_top.core3_dmem_rdata[25] ,
+    \u_riscv_top.core3_dmem_rdata[24] ,
+    \u_riscv_top.core3_dmem_rdata[23] ,
+    \u_riscv_top.core3_dmem_rdata[22] ,
+    \u_riscv_top.core3_dmem_rdata[21] ,
+    \u_riscv_top.core3_dmem_rdata[20] ,
+    \u_riscv_top.core3_dmem_rdata[19] ,
+    \u_riscv_top.core3_dmem_rdata[18] ,
+    \u_riscv_top.core3_dmem_rdata[17] ,
+    \u_riscv_top.core3_dmem_rdata[16] ,
+    \u_riscv_top.core3_dmem_rdata[15] ,
+    \u_riscv_top.core3_dmem_rdata[14] ,
+    \u_riscv_top.core3_dmem_rdata[13] ,
+    \u_riscv_top.core3_dmem_rdata[12] ,
+    \u_riscv_top.core3_dmem_rdata[11] ,
+    \u_riscv_top.core3_dmem_rdata[10] ,
+    \u_riscv_top.core3_dmem_rdata[9] ,
+    \u_riscv_top.core3_dmem_rdata[8] ,
+    \u_riscv_top.core3_dmem_rdata[7] ,
+    \u_riscv_top.core3_dmem_rdata[6] ,
+    \u_riscv_top.core3_dmem_rdata[5] ,
+    \u_riscv_top.core3_dmem_rdata[4] ,
+    \u_riscv_top.core3_dmem_rdata[3] ,
+    \u_riscv_top.core3_dmem_rdata[2] ,
+    \u_riscv_top.core3_dmem_rdata[1] ,
+    \u_riscv_top.core3_dmem_rdata[0] }),
+    .dmem2core_resp_i({\u_riscv_top.core3_dmem_resp[1] ,
+    \u_riscv_top.core3_dmem_resp[0] }),
+    .imem2core_rdata_i({\u_riscv_top.core3_imem_rdata[31] ,
+    \u_riscv_top.core3_imem_rdata[30] ,
+    \u_riscv_top.core3_imem_rdata[29] ,
+    \u_riscv_top.core3_imem_rdata[28] ,
+    \u_riscv_top.core3_imem_rdata[27] ,
+    \u_riscv_top.core3_imem_rdata[26] ,
+    \u_riscv_top.core3_imem_rdata[25] ,
+    \u_riscv_top.core3_imem_rdata[24] ,
+    \u_riscv_top.core3_imem_rdata[23] ,
+    \u_riscv_top.core3_imem_rdata[22] ,
+    \u_riscv_top.core3_imem_rdata[21] ,
+    \u_riscv_top.core3_imem_rdata[20] ,
+    \u_riscv_top.core3_imem_rdata[19] ,
+    \u_riscv_top.core3_imem_rdata[18] ,
+    \u_riscv_top.core3_imem_rdata[17] ,
+    \u_riscv_top.core3_imem_rdata[16] ,
+    \u_riscv_top.core3_imem_rdata[15] ,
+    \u_riscv_top.core3_imem_rdata[14] ,
+    \u_riscv_top.core3_imem_rdata[13] ,
+    \u_riscv_top.core3_imem_rdata[12] ,
+    \u_riscv_top.core3_imem_rdata[11] ,
+    \u_riscv_top.core3_imem_rdata[10] ,
+    \u_riscv_top.core3_imem_rdata[9] ,
+    \u_riscv_top.core3_imem_rdata[8] ,
+    \u_riscv_top.core3_imem_rdata[7] ,
+    \u_riscv_top.core3_imem_rdata[6] ,
+    \u_riscv_top.core3_imem_rdata[5] ,
+    \u_riscv_top.core3_imem_rdata[4] ,
+    \u_riscv_top.core3_imem_rdata[3] ,
+    \u_riscv_top.core3_imem_rdata[2] ,
+    \u_riscv_top.core3_imem_rdata[1] ,
+    \u_riscv_top.core3_imem_rdata[0] }),
+    .imem2core_resp_i({\u_riscv_top.core3_imem_resp[1] ,
+    \u_riscv_top.core3_imem_resp[0] }));
+ ycr4_iconnect \u_riscv_top.u_connect  (.VGND(vssd1),
+    .VPWR(vccd1),
+    .cfg_bypass_dcache(\cfg_riscv_ctrl[11] ),
+    .cfg_bypass_icache(\cfg_riscv_ctrl[10] ),
+    .cfg_dcache_force_flush(\u_riscv_top.cfg_dcache_force_flush ),
+    .core0_clk(\u_riscv_top.core0_clk ),
+    .core0_dmem_cmd(\u_riscv_top.core0_dmem_cmd ),
+    .core0_dmem_req(\u_riscv_top.core0_dmem_req ),
+    .core0_dmem_req_ack(\u_riscv_top.core0_dmem_req_ack ),
+    .core0_imem_cmd(\u_riscv_top.core0_imem_cmd ),
+    .core0_imem_req(\u_riscv_top.core0_imem_req ),
+    .core0_imem_req_ack(\u_riscv_top.core0_imem_req_ack ),
+    .core0_irq_soft(\u_riscv_top.core0_soft_irq ),
+    .core0_timer_irq(\u_riscv_top.core0_timer_irq ),
+    .core1_clk(\u_riscv_top.core1_clk ),
+    .core1_dmem_cmd(\u_riscv_top.core1_dmem_cmd ),
+    .core1_dmem_req(\u_riscv_top.core1_dmem_req ),
+    .core1_dmem_req_ack(\u_riscv_top.core1_dmem_req_ack ),
+    .core1_imem_cmd(\u_riscv_top.core1_imem_cmd ),
+    .core1_imem_req(\u_riscv_top.core1_imem_req ),
+    .core1_imem_req_ack(\u_riscv_top.core1_imem_req_ack ),
+    .core1_irq_soft(\u_riscv_top.core1_soft_irq ),
+    .core1_timer_irq(\u_riscv_top.core1_timer_irq ),
+    .core2_clk(\u_riscv_top.core2_clk ),
+    .core2_dmem_cmd(\u_riscv_top.core2_dmem_cmd ),
+    .core2_dmem_req(\u_riscv_top.core2_dmem_req ),
+    .core2_dmem_req_ack(\u_riscv_top.core2_dmem_req_ack ),
+    .core2_imem_cmd(\u_riscv_top.core2_imem_cmd ),
+    .core2_imem_req(\u_riscv_top.core2_imem_req ),
+    .core2_imem_req_ack(\u_riscv_top.core2_imem_req_ack ),
+    .core2_irq_soft(\u_riscv_top.core2_soft_irq ),
+    .core2_timer_irq(\u_riscv_top.core2_timer_irq ),
+    .core3_clk(\u_riscv_top.core3_clk ),
+    .core3_dmem_cmd(\u_riscv_top.core3_dmem_cmd ),
+    .core3_dmem_req(\u_riscv_top.core3_dmem_req ),
+    .core3_dmem_req_ack(\u_riscv_top.core3_dmem_req_ack ),
+    .core3_imem_cmd(\u_riscv_top.core3_imem_cmd ),
+    .core3_imem_req(\u_riscv_top.core3_imem_req ),
+    .core3_imem_req_ack(\u_riscv_top.core3_imem_req_ack ),
+    .core3_irq_soft(\u_riscv_top.core3_soft_irq ),
+    .core3_timer_irq(\u_riscv_top.core3_timer_irq ),
+    .core_clk(\u_riscv_top.core_clk_icon_skew ),
+    .core_clk_int(\u_riscv_top.core_clk_int[1] ),
+    .core_clk_skew(\u_riscv_top.core_clk_icon_skew ),
+    .core_dcache_cmd(\u_riscv_top.core_dcache_cmd ),
+    .core_dcache_req(\u_riscv_top.core_dcache_req ),
+    .core_dcache_req_ack(\u_riscv_top.core_dcache_req_ack ),
+    .core_dmem_cmd(\u_riscv_top.core_dmem_cmd ),
+    .core_dmem_req(\u_riscv_top.core_dmem_req ),
+    .core_dmem_req_ack(\u_riscv_top.core_dmem_req_ack ),
+    .core_icache_cmd(\u_riscv_top.core_icache_cmd ),
+    .core_icache_req(\u_riscv_top.core_icache_req ),
+    .core_icache_req_ack(\u_riscv_top.core_icache_req_ack ),
+    .core_irq_soft_i(\u_riscv_top.soft_irq ),
+    .cpu_intf_rst_n(\u_riscv_top.cpu_intf_rst_n ),
+    .pwrup_rst_n(\u_riscv_top.pwrup_rst_n ),
+    .rtc_clk(\u_riscv_top.rtc_clk ),
+    .sram0_clk0(\u_riscv_top.sram0_clk0 ),
+    .sram0_clk1(\u_riscv_top.sram0_clk1 ),
+    .sram0_csb0(\u_riscv_top.sram0_csb0 ),
+    .sram0_csb1(\u_riscv_top.sram0_csb1 ),
+    .sram0_web0(\u_riscv_top.sram0_web0 ),
+    .cfg_ccska({\u_riscv_top.cfg_ccska_riscv_icon[3] ,
+    \u_riscv_top.cfg_ccska_riscv_icon[2] ,
+    \u_riscv_top.cfg_ccska_riscv_icon[1] ,
+    \u_riscv_top.cfg_ccska_riscv_icon[0] }),
+    .cfg_sram_lphase({\cfg_riscv_ctrl[3] ,
+    \cfg_riscv_ctrl[2] }),
+    .core0_debug({\u_riscv_top.core0_debug[48] ,
+    \u_riscv_top.core0_debug[47] ,
+    \u_riscv_top.core0_debug[46] ,
+    \u_riscv_top.core0_debug[45] ,
+    \u_riscv_top.core0_debug[44] ,
+    \u_riscv_top.core0_debug[43] ,
+    \u_riscv_top.core0_debug[42] ,
+    \u_riscv_top.core0_debug[41] ,
+    \u_riscv_top.core0_debug[40] ,
+    \u_riscv_top.core0_debug[39] ,
+    \u_riscv_top.core0_debug[38] ,
+    \u_riscv_top.core0_debug[37] ,
+    \u_riscv_top.core0_debug[36] ,
+    \u_riscv_top.core0_debug[35] ,
+    \u_riscv_top.core0_debug[34] ,
+    \u_riscv_top.core0_debug[33] ,
+    \u_riscv_top.core0_debug[32] ,
+    \u_riscv_top.core0_debug[31] ,
+    \u_riscv_top.core0_debug[30] ,
+    \u_riscv_top.core0_debug[29] ,
+    \u_riscv_top.core0_debug[28] ,
+    \u_riscv_top.core0_debug[27] ,
+    \u_riscv_top.core0_debug[26] ,
+    \u_riscv_top.core0_debug[25] ,
+    \u_riscv_top.core0_debug[24] ,
+    \u_riscv_top.core0_debug[23] ,
+    \u_riscv_top.core0_debug[22] ,
+    \u_riscv_top.core0_debug[21] ,
+    \u_riscv_top.core0_debug[20] ,
+    \u_riscv_top.core0_debug[19] ,
+    \u_riscv_top.core0_debug[18] ,
+    \u_riscv_top.core0_debug[17] ,
+    \u_riscv_top.core0_debug[16] ,
+    \u_riscv_top.core0_debug[15] ,
+    \u_riscv_top.core0_debug[14] ,
+    \u_riscv_top.core0_debug[13] ,
+    \u_riscv_top.core0_debug[12] ,
+    \u_riscv_top.core0_debug[11] ,
+    \u_riscv_top.core0_debug[10] ,
+    \u_riscv_top.core0_debug[9] ,
+    \u_riscv_top.core0_debug[8] ,
+    \u_riscv_top.core0_debug[7] ,
+    \u_riscv_top.core0_debug[6] ,
+    \u_riscv_top.core0_debug[5] ,
+    \u_riscv_top.core0_debug[4] ,
+    \u_riscv_top.core0_debug[3] ,
+    \u_riscv_top.core0_debug[2] ,
+    \u_riscv_top.core0_debug[1] ,
+    \u_riscv_top.core0_debug[0] }),
+    .core0_dmem_addr({\u_riscv_top.core0_dmem_addr[31] ,
+    \u_riscv_top.core0_dmem_addr[30] ,
+    \u_riscv_top.core0_dmem_addr[29] ,
+    \u_riscv_top.core0_dmem_addr[28] ,
+    \u_riscv_top.core0_dmem_addr[27] ,
+    \u_riscv_top.core0_dmem_addr[26] ,
+    \u_riscv_top.core0_dmem_addr[25] ,
+    \u_riscv_top.core0_dmem_addr[24] ,
+    \u_riscv_top.core0_dmem_addr[23] ,
+    \u_riscv_top.core0_dmem_addr[22] ,
+    \u_riscv_top.core0_dmem_addr[21] ,
+    \u_riscv_top.core0_dmem_addr[20] ,
+    \u_riscv_top.core0_dmem_addr[19] ,
+    \u_riscv_top.core0_dmem_addr[18] ,
+    \u_riscv_top.core0_dmem_addr[17] ,
+    \u_riscv_top.core0_dmem_addr[16] ,
+    \u_riscv_top.core0_dmem_addr[15] ,
+    \u_riscv_top.core0_dmem_addr[14] ,
+    \u_riscv_top.core0_dmem_addr[13] ,
+    \u_riscv_top.core0_dmem_addr[12] ,
+    \u_riscv_top.core0_dmem_addr[11] ,
+    \u_riscv_top.core0_dmem_addr[10] ,
+    \u_riscv_top.core0_dmem_addr[9] ,
+    \u_riscv_top.core0_dmem_addr[8] ,
+    \u_riscv_top.core0_dmem_addr[7] ,
+    \u_riscv_top.core0_dmem_addr[6] ,
+    \u_riscv_top.core0_dmem_addr[5] ,
+    \u_riscv_top.core0_dmem_addr[4] ,
+    \u_riscv_top.core0_dmem_addr[3] ,
+    \u_riscv_top.core0_dmem_addr[2] ,
+    \u_riscv_top.core0_dmem_addr[1] ,
+    \u_riscv_top.core0_dmem_addr[0] }),
+    .core0_dmem_rdata({\u_riscv_top.core0_dmem_rdata[31] ,
+    \u_riscv_top.core0_dmem_rdata[30] ,
+    \u_riscv_top.core0_dmem_rdata[29] ,
+    \u_riscv_top.core0_dmem_rdata[28] ,
+    \u_riscv_top.core0_dmem_rdata[27] ,
+    \u_riscv_top.core0_dmem_rdata[26] ,
+    \u_riscv_top.core0_dmem_rdata[25] ,
+    \u_riscv_top.core0_dmem_rdata[24] ,
+    \u_riscv_top.core0_dmem_rdata[23] ,
+    \u_riscv_top.core0_dmem_rdata[22] ,
+    \u_riscv_top.core0_dmem_rdata[21] ,
+    \u_riscv_top.core0_dmem_rdata[20] ,
+    \u_riscv_top.core0_dmem_rdata[19] ,
+    \u_riscv_top.core0_dmem_rdata[18] ,
+    \u_riscv_top.core0_dmem_rdata[17] ,
+    \u_riscv_top.core0_dmem_rdata[16] ,
+    \u_riscv_top.core0_dmem_rdata[15] ,
+    \u_riscv_top.core0_dmem_rdata[14] ,
+    \u_riscv_top.core0_dmem_rdata[13] ,
+    \u_riscv_top.core0_dmem_rdata[12] ,
+    \u_riscv_top.core0_dmem_rdata[11] ,
+    \u_riscv_top.core0_dmem_rdata[10] ,
+    \u_riscv_top.core0_dmem_rdata[9] ,
+    \u_riscv_top.core0_dmem_rdata[8] ,
+    \u_riscv_top.core0_dmem_rdata[7] ,
+    \u_riscv_top.core0_dmem_rdata[6] ,
+    \u_riscv_top.core0_dmem_rdata[5] ,
+    \u_riscv_top.core0_dmem_rdata[4] ,
+    \u_riscv_top.core0_dmem_rdata[3] ,
+    \u_riscv_top.core0_dmem_rdata[2] ,
+    \u_riscv_top.core0_dmem_rdata[1] ,
+    \u_riscv_top.core0_dmem_rdata[0] }),
+    .core0_dmem_resp({\u_riscv_top.core0_dmem_resp[1] ,
+    \u_riscv_top.core0_dmem_resp[0] }),
+    .core0_dmem_wdata({\u_riscv_top.core0_dmem_wdata[31] ,
+    \u_riscv_top.core0_dmem_wdata[30] ,
+    \u_riscv_top.core0_dmem_wdata[29] ,
+    \u_riscv_top.core0_dmem_wdata[28] ,
+    \u_riscv_top.core0_dmem_wdata[27] ,
+    \u_riscv_top.core0_dmem_wdata[26] ,
+    \u_riscv_top.core0_dmem_wdata[25] ,
+    \u_riscv_top.core0_dmem_wdata[24] ,
+    \u_riscv_top.core0_dmem_wdata[23] ,
+    \u_riscv_top.core0_dmem_wdata[22] ,
+    \u_riscv_top.core0_dmem_wdata[21] ,
+    \u_riscv_top.core0_dmem_wdata[20] ,
+    \u_riscv_top.core0_dmem_wdata[19] ,
+    \u_riscv_top.core0_dmem_wdata[18] ,
+    \u_riscv_top.core0_dmem_wdata[17] ,
+    \u_riscv_top.core0_dmem_wdata[16] ,
+    \u_riscv_top.core0_dmem_wdata[15] ,
+    \u_riscv_top.core0_dmem_wdata[14] ,
+    \u_riscv_top.core0_dmem_wdata[13] ,
+    \u_riscv_top.core0_dmem_wdata[12] ,
+    \u_riscv_top.core0_dmem_wdata[11] ,
+    \u_riscv_top.core0_dmem_wdata[10] ,
+    \u_riscv_top.core0_dmem_wdata[9] ,
+    \u_riscv_top.core0_dmem_wdata[8] ,
+    \u_riscv_top.core0_dmem_wdata[7] ,
+    \u_riscv_top.core0_dmem_wdata[6] ,
+    \u_riscv_top.core0_dmem_wdata[5] ,
+    \u_riscv_top.core0_dmem_wdata[4] ,
+    \u_riscv_top.core0_dmem_wdata[3] ,
+    \u_riscv_top.core0_dmem_wdata[2] ,
+    \u_riscv_top.core0_dmem_wdata[1] ,
+    \u_riscv_top.core0_dmem_wdata[0] }),
+    .core0_dmem_width({\u_riscv_top.core0_dmem_width[1] ,
+    \u_riscv_top.core0_dmem_width[0] }),
+    .core0_imem_addr({\u_riscv_top.core0_imem_addr[31] ,
+    \u_riscv_top.core0_imem_addr[30] ,
+    \u_riscv_top.core0_imem_addr[29] ,
+    \u_riscv_top.core0_imem_addr[28] ,
+    \u_riscv_top.core0_imem_addr[27] ,
+    \u_riscv_top.core0_imem_addr[26] ,
+    \u_riscv_top.core0_imem_addr[25] ,
+    \u_riscv_top.core0_imem_addr[24] ,
+    \u_riscv_top.core0_imem_addr[23] ,
+    \u_riscv_top.core0_imem_addr[22] ,
+    \u_riscv_top.core0_imem_addr[21] ,
+    \u_riscv_top.core0_imem_addr[20] ,
+    \u_riscv_top.core0_imem_addr[19] ,
+    \u_riscv_top.core0_imem_addr[18] ,
+    \u_riscv_top.core0_imem_addr[17] ,
+    \u_riscv_top.core0_imem_addr[16] ,
+    \u_riscv_top.core0_imem_addr[15] ,
+    \u_riscv_top.core0_imem_addr[14] ,
+    \u_riscv_top.core0_imem_addr[13] ,
+    \u_riscv_top.core0_imem_addr[12] ,
+    \u_riscv_top.core0_imem_addr[11] ,
+    \u_riscv_top.core0_imem_addr[10] ,
+    \u_riscv_top.core0_imem_addr[9] ,
+    \u_riscv_top.core0_imem_addr[8] ,
+    \u_riscv_top.core0_imem_addr[7] ,
+    \u_riscv_top.core0_imem_addr[6] ,
+    \u_riscv_top.core0_imem_addr[5] ,
+    \u_riscv_top.core0_imem_addr[4] ,
+    \u_riscv_top.core0_imem_addr[3] ,
+    \u_riscv_top.core0_imem_addr[2] ,
+    \u_riscv_top.core0_imem_addr[1] ,
+    \u_riscv_top.core0_imem_addr[0] }),
+    .core0_imem_bl({\u_riscv_top.core0_imem_bl[2] ,
+    \u_riscv_top.core0_imem_bl[1] ,
+    \u_riscv_top.core0_imem_bl[0] }),
+    .core0_imem_rdata({\u_riscv_top.core0_imem_rdata[31] ,
+    \u_riscv_top.core0_imem_rdata[30] ,
+    \u_riscv_top.core0_imem_rdata[29] ,
+    \u_riscv_top.core0_imem_rdata[28] ,
+    \u_riscv_top.core0_imem_rdata[27] ,
+    \u_riscv_top.core0_imem_rdata[26] ,
+    \u_riscv_top.core0_imem_rdata[25] ,
+    \u_riscv_top.core0_imem_rdata[24] ,
+    \u_riscv_top.core0_imem_rdata[23] ,
+    \u_riscv_top.core0_imem_rdata[22] ,
+    \u_riscv_top.core0_imem_rdata[21] ,
+    \u_riscv_top.core0_imem_rdata[20] ,
+    \u_riscv_top.core0_imem_rdata[19] ,
+    \u_riscv_top.core0_imem_rdata[18] ,
+    \u_riscv_top.core0_imem_rdata[17] ,
+    \u_riscv_top.core0_imem_rdata[16] ,
+    \u_riscv_top.core0_imem_rdata[15] ,
+    \u_riscv_top.core0_imem_rdata[14] ,
+    \u_riscv_top.core0_imem_rdata[13] ,
+    \u_riscv_top.core0_imem_rdata[12] ,
+    \u_riscv_top.core0_imem_rdata[11] ,
+    \u_riscv_top.core0_imem_rdata[10] ,
+    \u_riscv_top.core0_imem_rdata[9] ,
+    \u_riscv_top.core0_imem_rdata[8] ,
+    \u_riscv_top.core0_imem_rdata[7] ,
+    \u_riscv_top.core0_imem_rdata[6] ,
+    \u_riscv_top.core0_imem_rdata[5] ,
+    \u_riscv_top.core0_imem_rdata[4] ,
+    \u_riscv_top.core0_imem_rdata[3] ,
+    \u_riscv_top.core0_imem_rdata[2] ,
+    \u_riscv_top.core0_imem_rdata[1] ,
+    \u_riscv_top.core0_imem_rdata[0] }),
+    .core0_imem_resp({\u_riscv_top.core0_imem_resp[1] ,
+    \u_riscv_top.core0_imem_resp[0] }),
+    .core0_irq_lines({\u_riscv_top.core0_irq_lines[31] ,
+    \u_riscv_top.core0_irq_lines[30] ,
+    \u_riscv_top.core0_irq_lines[29] ,
+    \u_riscv_top.core0_irq_lines[28] ,
+    \u_riscv_top.core0_irq_lines[27] ,
+    \u_riscv_top.core0_irq_lines[26] ,
+    \u_riscv_top.core0_irq_lines[25] ,
+    \u_riscv_top.core0_irq_lines[24] ,
+    \u_riscv_top.core0_irq_lines[23] ,
+    \u_riscv_top.core0_irq_lines[22] ,
+    \u_riscv_top.core0_irq_lines[21] ,
+    \u_riscv_top.core0_irq_lines[20] ,
+    \u_riscv_top.core0_irq_lines[19] ,
+    \u_riscv_top.core0_irq_lines[18] ,
+    \u_riscv_top.core0_irq_lines[17] ,
+    \u_riscv_top.core0_irq_lines[16] ,
+    \u_riscv_top.core0_irq_lines[15] ,
+    \u_riscv_top.core0_irq_lines[14] ,
+    \u_riscv_top.core0_irq_lines[13] ,
+    \u_riscv_top.core0_irq_lines[12] ,
+    \u_riscv_top.core0_irq_lines[11] ,
+    \u_riscv_top.core0_irq_lines[10] ,
+    \u_riscv_top.core0_irq_lines[9] ,
+    \u_riscv_top.core0_irq_lines[8] ,
+    \u_riscv_top.core0_irq_lines[7] ,
+    \u_riscv_top.core0_irq_lines[6] ,
+    \u_riscv_top.core0_irq_lines[5] ,
+    \u_riscv_top.core0_irq_lines[4] ,
+    \u_riscv_top.core0_irq_lines[3] ,
+    \u_riscv_top.core0_irq_lines[2] ,
+    \u_riscv_top.core0_irq_lines[1] ,
+    \u_riscv_top.core0_irq_lines[0] }),
+    .core0_timer_val({\u_riscv_top.core0_timer_val[63] ,
+    \u_riscv_top.core0_timer_val[62] ,
+    \u_riscv_top.core0_timer_val[61] ,
+    \u_riscv_top.core0_timer_val[60] ,
+    \u_riscv_top.core0_timer_val[59] ,
+    \u_riscv_top.core0_timer_val[58] ,
+    \u_riscv_top.core0_timer_val[57] ,
+    \u_riscv_top.core0_timer_val[56] ,
+    \u_riscv_top.core0_timer_val[55] ,
+    \u_riscv_top.core0_timer_val[54] ,
+    \u_riscv_top.core0_timer_val[53] ,
+    \u_riscv_top.core0_timer_val[52] ,
+    \u_riscv_top.core0_timer_val[51] ,
+    \u_riscv_top.core0_timer_val[50] ,
+    \u_riscv_top.core0_timer_val[49] ,
+    \u_riscv_top.core0_timer_val[48] ,
+    \u_riscv_top.core0_timer_val[47] ,
+    \u_riscv_top.core0_timer_val[46] ,
+    \u_riscv_top.core0_timer_val[45] ,
+    \u_riscv_top.core0_timer_val[44] ,
+    \u_riscv_top.core0_timer_val[43] ,
+    \u_riscv_top.core0_timer_val[42] ,
+    \u_riscv_top.core0_timer_val[41] ,
+    \u_riscv_top.core0_timer_val[40] ,
+    \u_riscv_top.core0_timer_val[39] ,
+    \u_riscv_top.core0_timer_val[38] ,
+    \u_riscv_top.core0_timer_val[37] ,
+    \u_riscv_top.core0_timer_val[36] ,
+    \u_riscv_top.core0_timer_val[35] ,
+    \u_riscv_top.core0_timer_val[34] ,
+    \u_riscv_top.core0_timer_val[33] ,
+    \u_riscv_top.core0_timer_val[32] ,
+    \u_riscv_top.core0_timer_val[31] ,
+    \u_riscv_top.core0_timer_val[30] ,
+    \u_riscv_top.core0_timer_val[29] ,
+    \u_riscv_top.core0_timer_val[28] ,
+    \u_riscv_top.core0_timer_val[27] ,
+    \u_riscv_top.core0_timer_val[26] ,
+    \u_riscv_top.core0_timer_val[25] ,
+    \u_riscv_top.core0_timer_val[24] ,
+    \u_riscv_top.core0_timer_val[23] ,
+    \u_riscv_top.core0_timer_val[22] ,
+    \u_riscv_top.core0_timer_val[21] ,
+    \u_riscv_top.core0_timer_val[20] ,
+    \u_riscv_top.core0_timer_val[19] ,
+    \u_riscv_top.core0_timer_val[18] ,
+    \u_riscv_top.core0_timer_val[17] ,
+    \u_riscv_top.core0_timer_val[16] ,
+    \u_riscv_top.core0_timer_val[15] ,
+    \u_riscv_top.core0_timer_val[14] ,
+    \u_riscv_top.core0_timer_val[13] ,
+    \u_riscv_top.core0_timer_val[12] ,
+    \u_riscv_top.core0_timer_val[11] ,
+    \u_riscv_top.core0_timer_val[10] ,
+    \u_riscv_top.core0_timer_val[9] ,
+    \u_riscv_top.core0_timer_val[8] ,
+    \u_riscv_top.core0_timer_val[7] ,
+    \u_riscv_top.core0_timer_val[6] ,
+    \u_riscv_top.core0_timer_val[5] ,
+    \u_riscv_top.core0_timer_val[4] ,
+    \u_riscv_top.core0_timer_val[3] ,
+    \u_riscv_top.core0_timer_val[2] ,
+    \u_riscv_top.core0_timer_val[1] ,
+    \u_riscv_top.core0_timer_val[0] }),
+    .core0_uid({\u_riscv_top.core0_uid[1] ,
+    \u_riscv_top.core0_uid[0] }),
+    .core1_debug({\u_riscv_top.core1_debug[48] ,
+    \u_riscv_top.core1_debug[47] ,
+    \u_riscv_top.core1_debug[46] ,
+    \u_riscv_top.core1_debug[45] ,
+    \u_riscv_top.core1_debug[44] ,
+    \u_riscv_top.core1_debug[43] ,
+    \u_riscv_top.core1_debug[42] ,
+    \u_riscv_top.core1_debug[41] ,
+    \u_riscv_top.core1_debug[40] ,
+    \u_riscv_top.core1_debug[39] ,
+    \u_riscv_top.core1_debug[38] ,
+    \u_riscv_top.core1_debug[37] ,
+    \u_riscv_top.core1_debug[36] ,
+    \u_riscv_top.core1_debug[35] ,
+    \u_riscv_top.core1_debug[34] ,
+    \u_riscv_top.core1_debug[33] ,
+    \u_riscv_top.core1_debug[32] ,
+    \u_riscv_top.core1_debug[31] ,
+    \u_riscv_top.core1_debug[30] ,
+    \u_riscv_top.core1_debug[29] ,
+    \u_riscv_top.core1_debug[28] ,
+    \u_riscv_top.core1_debug[27] ,
+    \u_riscv_top.core1_debug[26] ,
+    \u_riscv_top.core1_debug[25] ,
+    \u_riscv_top.core1_debug[24] ,
+    \u_riscv_top.core1_debug[23] ,
+    \u_riscv_top.core1_debug[22] ,
+    \u_riscv_top.core1_debug[21] ,
+    \u_riscv_top.core1_debug[20] ,
+    \u_riscv_top.core1_debug[19] ,
+    \u_riscv_top.core1_debug[18] ,
+    \u_riscv_top.core1_debug[17] ,
+    \u_riscv_top.core1_debug[16] ,
+    \u_riscv_top.core1_debug[15] ,
+    \u_riscv_top.core1_debug[14] ,
+    \u_riscv_top.core1_debug[13] ,
+    \u_riscv_top.core1_debug[12] ,
+    \u_riscv_top.core1_debug[11] ,
+    \u_riscv_top.core1_debug[10] ,
+    \u_riscv_top.core1_debug[9] ,
+    \u_riscv_top.core1_debug[8] ,
+    \u_riscv_top.core1_debug[7] ,
+    \u_riscv_top.core1_debug[6] ,
+    \u_riscv_top.core1_debug[5] ,
+    \u_riscv_top.core1_debug[4] ,
+    \u_riscv_top.core1_debug[3] ,
+    \u_riscv_top.core1_debug[2] ,
+    \u_riscv_top.core1_debug[1] ,
+    \u_riscv_top.core1_debug[0] }),
+    .core1_dmem_addr({\u_riscv_top.core1_dmem_addr[31] ,
+    \u_riscv_top.core1_dmem_addr[30] ,
+    \u_riscv_top.core1_dmem_addr[29] ,
+    \u_riscv_top.core1_dmem_addr[28] ,
+    \u_riscv_top.core1_dmem_addr[27] ,
+    \u_riscv_top.core1_dmem_addr[26] ,
+    \u_riscv_top.core1_dmem_addr[25] ,
+    \u_riscv_top.core1_dmem_addr[24] ,
+    \u_riscv_top.core1_dmem_addr[23] ,
+    \u_riscv_top.core1_dmem_addr[22] ,
+    \u_riscv_top.core1_dmem_addr[21] ,
+    \u_riscv_top.core1_dmem_addr[20] ,
+    \u_riscv_top.core1_dmem_addr[19] ,
+    \u_riscv_top.core1_dmem_addr[18] ,
+    \u_riscv_top.core1_dmem_addr[17] ,
+    \u_riscv_top.core1_dmem_addr[16] ,
+    \u_riscv_top.core1_dmem_addr[15] ,
+    \u_riscv_top.core1_dmem_addr[14] ,
+    \u_riscv_top.core1_dmem_addr[13] ,
+    \u_riscv_top.core1_dmem_addr[12] ,
+    \u_riscv_top.core1_dmem_addr[11] ,
+    \u_riscv_top.core1_dmem_addr[10] ,
+    \u_riscv_top.core1_dmem_addr[9] ,
+    \u_riscv_top.core1_dmem_addr[8] ,
+    \u_riscv_top.core1_dmem_addr[7] ,
+    \u_riscv_top.core1_dmem_addr[6] ,
+    \u_riscv_top.core1_dmem_addr[5] ,
+    \u_riscv_top.core1_dmem_addr[4] ,
+    \u_riscv_top.core1_dmem_addr[3] ,
+    \u_riscv_top.core1_dmem_addr[2] ,
+    \u_riscv_top.core1_dmem_addr[1] ,
+    \u_riscv_top.core1_dmem_addr[0] }),
+    .core1_dmem_rdata({\u_riscv_top.core1_dmem_rdata[31] ,
+    \u_riscv_top.core1_dmem_rdata[30] ,
+    \u_riscv_top.core1_dmem_rdata[29] ,
+    \u_riscv_top.core1_dmem_rdata[28] ,
+    \u_riscv_top.core1_dmem_rdata[27] ,
+    \u_riscv_top.core1_dmem_rdata[26] ,
+    \u_riscv_top.core1_dmem_rdata[25] ,
+    \u_riscv_top.core1_dmem_rdata[24] ,
+    \u_riscv_top.core1_dmem_rdata[23] ,
+    \u_riscv_top.core1_dmem_rdata[22] ,
+    \u_riscv_top.core1_dmem_rdata[21] ,
+    \u_riscv_top.core1_dmem_rdata[20] ,
+    \u_riscv_top.core1_dmem_rdata[19] ,
+    \u_riscv_top.core1_dmem_rdata[18] ,
+    \u_riscv_top.core1_dmem_rdata[17] ,
+    \u_riscv_top.core1_dmem_rdata[16] ,
+    \u_riscv_top.core1_dmem_rdata[15] ,
+    \u_riscv_top.core1_dmem_rdata[14] ,
+    \u_riscv_top.core1_dmem_rdata[13] ,
+    \u_riscv_top.core1_dmem_rdata[12] ,
+    \u_riscv_top.core1_dmem_rdata[11] ,
+    \u_riscv_top.core1_dmem_rdata[10] ,
+    \u_riscv_top.core1_dmem_rdata[9] ,
+    \u_riscv_top.core1_dmem_rdata[8] ,
+    \u_riscv_top.core1_dmem_rdata[7] ,
+    \u_riscv_top.core1_dmem_rdata[6] ,
+    \u_riscv_top.core1_dmem_rdata[5] ,
+    \u_riscv_top.core1_dmem_rdata[4] ,
+    \u_riscv_top.core1_dmem_rdata[3] ,
+    \u_riscv_top.core1_dmem_rdata[2] ,
+    \u_riscv_top.core1_dmem_rdata[1] ,
+    \u_riscv_top.core1_dmem_rdata[0] }),
+    .core1_dmem_resp({\u_riscv_top.core1_dmem_resp[1] ,
+    \u_riscv_top.core1_dmem_resp[0] }),
+    .core1_dmem_wdata({\u_riscv_top.core1_dmem_wdata[31] ,
+    \u_riscv_top.core1_dmem_wdata[30] ,
+    \u_riscv_top.core1_dmem_wdata[29] ,
+    \u_riscv_top.core1_dmem_wdata[28] ,
+    \u_riscv_top.core1_dmem_wdata[27] ,
+    \u_riscv_top.core1_dmem_wdata[26] ,
+    \u_riscv_top.core1_dmem_wdata[25] ,
+    \u_riscv_top.core1_dmem_wdata[24] ,
+    \u_riscv_top.core1_dmem_wdata[23] ,
+    \u_riscv_top.core1_dmem_wdata[22] ,
+    \u_riscv_top.core1_dmem_wdata[21] ,
+    \u_riscv_top.core1_dmem_wdata[20] ,
+    \u_riscv_top.core1_dmem_wdata[19] ,
+    \u_riscv_top.core1_dmem_wdata[18] ,
+    \u_riscv_top.core1_dmem_wdata[17] ,
+    \u_riscv_top.core1_dmem_wdata[16] ,
+    \u_riscv_top.core1_dmem_wdata[15] ,
+    \u_riscv_top.core1_dmem_wdata[14] ,
+    \u_riscv_top.core1_dmem_wdata[13] ,
+    \u_riscv_top.core1_dmem_wdata[12] ,
+    \u_riscv_top.core1_dmem_wdata[11] ,
+    \u_riscv_top.core1_dmem_wdata[10] ,
+    \u_riscv_top.core1_dmem_wdata[9] ,
+    \u_riscv_top.core1_dmem_wdata[8] ,
+    \u_riscv_top.core1_dmem_wdata[7] ,
+    \u_riscv_top.core1_dmem_wdata[6] ,
+    \u_riscv_top.core1_dmem_wdata[5] ,
+    \u_riscv_top.core1_dmem_wdata[4] ,
+    \u_riscv_top.core1_dmem_wdata[3] ,
+    \u_riscv_top.core1_dmem_wdata[2] ,
+    \u_riscv_top.core1_dmem_wdata[1] ,
+    \u_riscv_top.core1_dmem_wdata[0] }),
+    .core1_dmem_width({\u_riscv_top.core1_dmem_width[1] ,
+    \u_riscv_top.core1_dmem_width[0] }),
+    .core1_imem_addr({\u_riscv_top.core1_imem_addr[31] ,
+    \u_riscv_top.core1_imem_addr[30] ,
+    \u_riscv_top.core1_imem_addr[29] ,
+    \u_riscv_top.core1_imem_addr[28] ,
+    \u_riscv_top.core1_imem_addr[27] ,
+    \u_riscv_top.core1_imem_addr[26] ,
+    \u_riscv_top.core1_imem_addr[25] ,
+    \u_riscv_top.core1_imem_addr[24] ,
+    \u_riscv_top.core1_imem_addr[23] ,
+    \u_riscv_top.core1_imem_addr[22] ,
+    \u_riscv_top.core1_imem_addr[21] ,
+    \u_riscv_top.core1_imem_addr[20] ,
+    \u_riscv_top.core1_imem_addr[19] ,
+    \u_riscv_top.core1_imem_addr[18] ,
+    \u_riscv_top.core1_imem_addr[17] ,
+    \u_riscv_top.core1_imem_addr[16] ,
+    \u_riscv_top.core1_imem_addr[15] ,
+    \u_riscv_top.core1_imem_addr[14] ,
+    \u_riscv_top.core1_imem_addr[13] ,
+    \u_riscv_top.core1_imem_addr[12] ,
+    \u_riscv_top.core1_imem_addr[11] ,
+    \u_riscv_top.core1_imem_addr[10] ,
+    \u_riscv_top.core1_imem_addr[9] ,
+    \u_riscv_top.core1_imem_addr[8] ,
+    \u_riscv_top.core1_imem_addr[7] ,
+    \u_riscv_top.core1_imem_addr[6] ,
+    \u_riscv_top.core1_imem_addr[5] ,
+    \u_riscv_top.core1_imem_addr[4] ,
+    \u_riscv_top.core1_imem_addr[3] ,
+    \u_riscv_top.core1_imem_addr[2] ,
+    \u_riscv_top.core1_imem_addr[1] ,
+    \u_riscv_top.core1_imem_addr[0] }),
+    .core1_imem_bl({\u_riscv_top.core1_imem_bl[2] ,
+    \u_riscv_top.core1_imem_bl[1] ,
+    \u_riscv_top.core1_imem_bl[0] }),
+    .core1_imem_rdata({\u_riscv_top.core1_imem_rdata[31] ,
+    \u_riscv_top.core1_imem_rdata[30] ,
+    \u_riscv_top.core1_imem_rdata[29] ,
+    \u_riscv_top.core1_imem_rdata[28] ,
+    \u_riscv_top.core1_imem_rdata[27] ,
+    \u_riscv_top.core1_imem_rdata[26] ,
+    \u_riscv_top.core1_imem_rdata[25] ,
+    \u_riscv_top.core1_imem_rdata[24] ,
+    \u_riscv_top.core1_imem_rdata[23] ,
+    \u_riscv_top.core1_imem_rdata[22] ,
+    \u_riscv_top.core1_imem_rdata[21] ,
+    \u_riscv_top.core1_imem_rdata[20] ,
+    \u_riscv_top.core1_imem_rdata[19] ,
+    \u_riscv_top.core1_imem_rdata[18] ,
+    \u_riscv_top.core1_imem_rdata[17] ,
+    \u_riscv_top.core1_imem_rdata[16] ,
+    \u_riscv_top.core1_imem_rdata[15] ,
+    \u_riscv_top.core1_imem_rdata[14] ,
+    \u_riscv_top.core1_imem_rdata[13] ,
+    \u_riscv_top.core1_imem_rdata[12] ,
+    \u_riscv_top.core1_imem_rdata[11] ,
+    \u_riscv_top.core1_imem_rdata[10] ,
+    \u_riscv_top.core1_imem_rdata[9] ,
+    \u_riscv_top.core1_imem_rdata[8] ,
+    \u_riscv_top.core1_imem_rdata[7] ,
+    \u_riscv_top.core1_imem_rdata[6] ,
+    \u_riscv_top.core1_imem_rdata[5] ,
+    \u_riscv_top.core1_imem_rdata[4] ,
+    \u_riscv_top.core1_imem_rdata[3] ,
+    \u_riscv_top.core1_imem_rdata[2] ,
+    \u_riscv_top.core1_imem_rdata[1] ,
+    \u_riscv_top.core1_imem_rdata[0] }),
+    .core1_imem_resp({\u_riscv_top.core1_imem_resp[1] ,
+    \u_riscv_top.core1_imem_resp[0] }),
+    .core1_irq_lines({\u_riscv_top.core1_irq_lines[31] ,
+    \u_riscv_top.core1_irq_lines[30] ,
+    \u_riscv_top.core1_irq_lines[29] ,
+    \u_riscv_top.core1_irq_lines[28] ,
+    \u_riscv_top.core1_irq_lines[27] ,
+    \u_riscv_top.core1_irq_lines[26] ,
+    \u_riscv_top.core1_irq_lines[25] ,
+    \u_riscv_top.core1_irq_lines[24] ,
+    \u_riscv_top.core1_irq_lines[23] ,
+    \u_riscv_top.core1_irq_lines[22] ,
+    \u_riscv_top.core1_irq_lines[21] ,
+    \u_riscv_top.core1_irq_lines[20] ,
+    \u_riscv_top.core1_irq_lines[19] ,
+    \u_riscv_top.core1_irq_lines[18] ,
+    \u_riscv_top.core1_irq_lines[17] ,
+    \u_riscv_top.core1_irq_lines[16] ,
+    \u_riscv_top.core1_irq_lines[15] ,
+    \u_riscv_top.core1_irq_lines[14] ,
+    \u_riscv_top.core1_irq_lines[13] ,
+    \u_riscv_top.core1_irq_lines[12] ,
+    \u_riscv_top.core1_irq_lines[11] ,
+    \u_riscv_top.core1_irq_lines[10] ,
+    \u_riscv_top.core1_irq_lines[9] ,
+    \u_riscv_top.core1_irq_lines[8] ,
+    \u_riscv_top.core1_irq_lines[7] ,
+    \u_riscv_top.core1_irq_lines[6] ,
+    \u_riscv_top.core1_irq_lines[5] ,
+    \u_riscv_top.core1_irq_lines[4] ,
+    \u_riscv_top.core1_irq_lines[3] ,
+    \u_riscv_top.core1_irq_lines[2] ,
+    \u_riscv_top.core1_irq_lines[1] ,
+    \u_riscv_top.core1_irq_lines[0] }),
+    .core1_timer_val({\u_riscv_top.core1_timer_val[63] ,
+    \u_riscv_top.core1_timer_val[62] ,
+    \u_riscv_top.core1_timer_val[61] ,
+    \u_riscv_top.core1_timer_val[60] ,
+    \u_riscv_top.core1_timer_val[59] ,
+    \u_riscv_top.core1_timer_val[58] ,
+    \u_riscv_top.core1_timer_val[57] ,
+    \u_riscv_top.core1_timer_val[56] ,
+    \u_riscv_top.core1_timer_val[55] ,
+    \u_riscv_top.core1_timer_val[54] ,
+    \u_riscv_top.core1_timer_val[53] ,
+    \u_riscv_top.core1_timer_val[52] ,
+    \u_riscv_top.core1_timer_val[51] ,
+    \u_riscv_top.core1_timer_val[50] ,
+    \u_riscv_top.core1_timer_val[49] ,
+    \u_riscv_top.core1_timer_val[48] ,
+    \u_riscv_top.core1_timer_val[47] ,
+    \u_riscv_top.core1_timer_val[46] ,
+    \u_riscv_top.core1_timer_val[45] ,
+    \u_riscv_top.core1_timer_val[44] ,
+    \u_riscv_top.core1_timer_val[43] ,
+    \u_riscv_top.core1_timer_val[42] ,
+    \u_riscv_top.core1_timer_val[41] ,
+    \u_riscv_top.core1_timer_val[40] ,
+    \u_riscv_top.core1_timer_val[39] ,
+    \u_riscv_top.core1_timer_val[38] ,
+    \u_riscv_top.core1_timer_val[37] ,
+    \u_riscv_top.core1_timer_val[36] ,
+    \u_riscv_top.core1_timer_val[35] ,
+    \u_riscv_top.core1_timer_val[34] ,
+    \u_riscv_top.core1_timer_val[33] ,
+    \u_riscv_top.core1_timer_val[32] ,
+    \u_riscv_top.core1_timer_val[31] ,
+    \u_riscv_top.core1_timer_val[30] ,
+    \u_riscv_top.core1_timer_val[29] ,
+    \u_riscv_top.core1_timer_val[28] ,
+    \u_riscv_top.core1_timer_val[27] ,
+    \u_riscv_top.core1_timer_val[26] ,
+    \u_riscv_top.core1_timer_val[25] ,
+    \u_riscv_top.core1_timer_val[24] ,
+    \u_riscv_top.core1_timer_val[23] ,
+    \u_riscv_top.core1_timer_val[22] ,
+    \u_riscv_top.core1_timer_val[21] ,
+    \u_riscv_top.core1_timer_val[20] ,
+    \u_riscv_top.core1_timer_val[19] ,
+    \u_riscv_top.core1_timer_val[18] ,
+    \u_riscv_top.core1_timer_val[17] ,
+    \u_riscv_top.core1_timer_val[16] ,
+    \u_riscv_top.core1_timer_val[15] ,
+    \u_riscv_top.core1_timer_val[14] ,
+    \u_riscv_top.core1_timer_val[13] ,
+    \u_riscv_top.core1_timer_val[12] ,
+    \u_riscv_top.core1_timer_val[11] ,
+    \u_riscv_top.core1_timer_val[10] ,
+    \u_riscv_top.core1_timer_val[9] ,
+    \u_riscv_top.core1_timer_val[8] ,
+    \u_riscv_top.core1_timer_val[7] ,
+    \u_riscv_top.core1_timer_val[6] ,
+    \u_riscv_top.core1_timer_val[5] ,
+    \u_riscv_top.core1_timer_val[4] ,
+    \u_riscv_top.core1_timer_val[3] ,
+    \u_riscv_top.core1_timer_val[2] ,
+    \u_riscv_top.core1_timer_val[1] ,
+    \u_riscv_top.core1_timer_val[0] }),
+    .core1_uid({\u_riscv_top.core1_uid[1] ,
+    \u_riscv_top.core1_uid[0] }),
+    .core2_debug({\u_riscv_top.core2_debug[48] ,
+    \u_riscv_top.core2_debug[47] ,
+    \u_riscv_top.core2_debug[46] ,
+    \u_riscv_top.core2_debug[45] ,
+    \u_riscv_top.core2_debug[44] ,
+    \u_riscv_top.core2_debug[43] ,
+    \u_riscv_top.core2_debug[42] ,
+    \u_riscv_top.core2_debug[41] ,
+    \u_riscv_top.core2_debug[40] ,
+    \u_riscv_top.core2_debug[39] ,
+    \u_riscv_top.core2_debug[38] ,
+    \u_riscv_top.core2_debug[37] ,
+    \u_riscv_top.core2_debug[36] ,
+    \u_riscv_top.core2_debug[35] ,
+    \u_riscv_top.core2_debug[34] ,
+    \u_riscv_top.core2_debug[33] ,
+    \u_riscv_top.core2_debug[32] ,
+    \u_riscv_top.core2_debug[31] ,
+    \u_riscv_top.core2_debug[30] ,
+    \u_riscv_top.core2_debug[29] ,
+    \u_riscv_top.core2_debug[28] ,
+    \u_riscv_top.core2_debug[27] ,
+    \u_riscv_top.core2_debug[26] ,
+    \u_riscv_top.core2_debug[25] ,
+    \u_riscv_top.core2_debug[24] ,
+    \u_riscv_top.core2_debug[23] ,
+    \u_riscv_top.core2_debug[22] ,
+    \u_riscv_top.core2_debug[21] ,
+    \u_riscv_top.core2_debug[20] ,
+    \u_riscv_top.core2_debug[19] ,
+    \u_riscv_top.core2_debug[18] ,
+    \u_riscv_top.core2_debug[17] ,
+    \u_riscv_top.core2_debug[16] ,
+    \u_riscv_top.core2_debug[15] ,
+    \u_riscv_top.core2_debug[14] ,
+    \u_riscv_top.core2_debug[13] ,
+    \u_riscv_top.core2_debug[12] ,
+    \u_riscv_top.core2_debug[11] ,
+    \u_riscv_top.core2_debug[10] ,
+    \u_riscv_top.core2_debug[9] ,
+    \u_riscv_top.core2_debug[8] ,
+    \u_riscv_top.core2_debug[7] ,
+    \u_riscv_top.core2_debug[6] ,
+    \u_riscv_top.core2_debug[5] ,
+    \u_riscv_top.core2_debug[4] ,
+    \u_riscv_top.core2_debug[3] ,
+    \u_riscv_top.core2_debug[2] ,
+    \u_riscv_top.core2_debug[1] ,
+    \u_riscv_top.core2_debug[0] }),
+    .core2_dmem_addr({\u_riscv_top.core2_dmem_addr[31] ,
+    \u_riscv_top.core2_dmem_addr[30] ,
+    \u_riscv_top.core2_dmem_addr[29] ,
+    \u_riscv_top.core2_dmem_addr[28] ,
+    \u_riscv_top.core2_dmem_addr[27] ,
+    \u_riscv_top.core2_dmem_addr[26] ,
+    \u_riscv_top.core2_dmem_addr[25] ,
+    \u_riscv_top.core2_dmem_addr[24] ,
+    \u_riscv_top.core2_dmem_addr[23] ,
+    \u_riscv_top.core2_dmem_addr[22] ,
+    \u_riscv_top.core2_dmem_addr[21] ,
+    \u_riscv_top.core2_dmem_addr[20] ,
+    \u_riscv_top.core2_dmem_addr[19] ,
+    \u_riscv_top.core2_dmem_addr[18] ,
+    \u_riscv_top.core2_dmem_addr[17] ,
+    \u_riscv_top.core2_dmem_addr[16] ,
+    \u_riscv_top.core2_dmem_addr[15] ,
+    \u_riscv_top.core2_dmem_addr[14] ,
+    \u_riscv_top.core2_dmem_addr[13] ,
+    \u_riscv_top.core2_dmem_addr[12] ,
+    \u_riscv_top.core2_dmem_addr[11] ,
+    \u_riscv_top.core2_dmem_addr[10] ,
+    \u_riscv_top.core2_dmem_addr[9] ,
+    \u_riscv_top.core2_dmem_addr[8] ,
+    \u_riscv_top.core2_dmem_addr[7] ,
+    \u_riscv_top.core2_dmem_addr[6] ,
+    \u_riscv_top.core2_dmem_addr[5] ,
+    \u_riscv_top.core2_dmem_addr[4] ,
+    \u_riscv_top.core2_dmem_addr[3] ,
+    \u_riscv_top.core2_dmem_addr[2] ,
+    \u_riscv_top.core2_dmem_addr[1] ,
+    \u_riscv_top.core2_dmem_addr[0] }),
+    .core2_dmem_rdata({\u_riscv_top.core2_dmem_rdata[31] ,
+    \u_riscv_top.core2_dmem_rdata[30] ,
+    \u_riscv_top.core2_dmem_rdata[29] ,
+    \u_riscv_top.core2_dmem_rdata[28] ,
+    \u_riscv_top.core2_dmem_rdata[27] ,
+    \u_riscv_top.core2_dmem_rdata[26] ,
+    \u_riscv_top.core2_dmem_rdata[25] ,
+    \u_riscv_top.core2_dmem_rdata[24] ,
+    \u_riscv_top.core2_dmem_rdata[23] ,
+    \u_riscv_top.core2_dmem_rdata[22] ,
+    \u_riscv_top.core2_dmem_rdata[21] ,
+    \u_riscv_top.core2_dmem_rdata[20] ,
+    \u_riscv_top.core2_dmem_rdata[19] ,
+    \u_riscv_top.core2_dmem_rdata[18] ,
+    \u_riscv_top.core2_dmem_rdata[17] ,
+    \u_riscv_top.core2_dmem_rdata[16] ,
+    \u_riscv_top.core2_dmem_rdata[15] ,
+    \u_riscv_top.core2_dmem_rdata[14] ,
+    \u_riscv_top.core2_dmem_rdata[13] ,
+    \u_riscv_top.core2_dmem_rdata[12] ,
+    \u_riscv_top.core2_dmem_rdata[11] ,
+    \u_riscv_top.core2_dmem_rdata[10] ,
+    \u_riscv_top.core2_dmem_rdata[9] ,
+    \u_riscv_top.core2_dmem_rdata[8] ,
+    \u_riscv_top.core2_dmem_rdata[7] ,
+    \u_riscv_top.core2_dmem_rdata[6] ,
+    \u_riscv_top.core2_dmem_rdata[5] ,
+    \u_riscv_top.core2_dmem_rdata[4] ,
+    \u_riscv_top.core2_dmem_rdata[3] ,
+    \u_riscv_top.core2_dmem_rdata[2] ,
+    \u_riscv_top.core2_dmem_rdata[1] ,
+    \u_riscv_top.core2_dmem_rdata[0] }),
+    .core2_dmem_resp({\u_riscv_top.core2_dmem_resp[1] ,
+    \u_riscv_top.core2_dmem_resp[0] }),
+    .core2_dmem_wdata({\u_riscv_top.core2_dmem_wdata[31] ,
+    \u_riscv_top.core2_dmem_wdata[30] ,
+    \u_riscv_top.core2_dmem_wdata[29] ,
+    \u_riscv_top.core2_dmem_wdata[28] ,
+    \u_riscv_top.core2_dmem_wdata[27] ,
+    \u_riscv_top.core2_dmem_wdata[26] ,
+    \u_riscv_top.core2_dmem_wdata[25] ,
+    \u_riscv_top.core2_dmem_wdata[24] ,
+    \u_riscv_top.core2_dmem_wdata[23] ,
+    \u_riscv_top.core2_dmem_wdata[22] ,
+    \u_riscv_top.core2_dmem_wdata[21] ,
+    \u_riscv_top.core2_dmem_wdata[20] ,
+    \u_riscv_top.core2_dmem_wdata[19] ,
+    \u_riscv_top.core2_dmem_wdata[18] ,
+    \u_riscv_top.core2_dmem_wdata[17] ,
+    \u_riscv_top.core2_dmem_wdata[16] ,
+    \u_riscv_top.core2_dmem_wdata[15] ,
+    \u_riscv_top.core2_dmem_wdata[14] ,
+    \u_riscv_top.core2_dmem_wdata[13] ,
+    \u_riscv_top.core2_dmem_wdata[12] ,
+    \u_riscv_top.core2_dmem_wdata[11] ,
+    \u_riscv_top.core2_dmem_wdata[10] ,
+    \u_riscv_top.core2_dmem_wdata[9] ,
+    \u_riscv_top.core2_dmem_wdata[8] ,
+    \u_riscv_top.core2_dmem_wdata[7] ,
+    \u_riscv_top.core2_dmem_wdata[6] ,
+    \u_riscv_top.core2_dmem_wdata[5] ,
+    \u_riscv_top.core2_dmem_wdata[4] ,
+    \u_riscv_top.core2_dmem_wdata[3] ,
+    \u_riscv_top.core2_dmem_wdata[2] ,
+    \u_riscv_top.core2_dmem_wdata[1] ,
+    \u_riscv_top.core2_dmem_wdata[0] }),
+    .core2_dmem_width({\u_riscv_top.core2_dmem_width[1] ,
+    \u_riscv_top.core2_dmem_width[0] }),
+    .core2_imem_addr({\u_riscv_top.core2_imem_addr[31] ,
+    \u_riscv_top.core2_imem_addr[30] ,
+    \u_riscv_top.core2_imem_addr[29] ,
+    \u_riscv_top.core2_imem_addr[28] ,
+    \u_riscv_top.core2_imem_addr[27] ,
+    \u_riscv_top.core2_imem_addr[26] ,
+    \u_riscv_top.core2_imem_addr[25] ,
+    \u_riscv_top.core2_imem_addr[24] ,
+    \u_riscv_top.core2_imem_addr[23] ,
+    \u_riscv_top.core2_imem_addr[22] ,
+    \u_riscv_top.core2_imem_addr[21] ,
+    \u_riscv_top.core2_imem_addr[20] ,
+    \u_riscv_top.core2_imem_addr[19] ,
+    \u_riscv_top.core2_imem_addr[18] ,
+    \u_riscv_top.core2_imem_addr[17] ,
+    \u_riscv_top.core2_imem_addr[16] ,
+    \u_riscv_top.core2_imem_addr[15] ,
+    \u_riscv_top.core2_imem_addr[14] ,
+    \u_riscv_top.core2_imem_addr[13] ,
+    \u_riscv_top.core2_imem_addr[12] ,
+    \u_riscv_top.core2_imem_addr[11] ,
+    \u_riscv_top.core2_imem_addr[10] ,
+    \u_riscv_top.core2_imem_addr[9] ,
+    \u_riscv_top.core2_imem_addr[8] ,
+    \u_riscv_top.core2_imem_addr[7] ,
+    \u_riscv_top.core2_imem_addr[6] ,
+    \u_riscv_top.core2_imem_addr[5] ,
+    \u_riscv_top.core2_imem_addr[4] ,
+    \u_riscv_top.core2_imem_addr[3] ,
+    \u_riscv_top.core2_imem_addr[2] ,
+    \u_riscv_top.core2_imem_addr[1] ,
+    \u_riscv_top.core2_imem_addr[0] }),
+    .core2_imem_bl({\u_riscv_top.core2_imem_bl[2] ,
+    \u_riscv_top.core2_imem_bl[1] ,
+    \u_riscv_top.core2_imem_bl[0] }),
+    .core2_imem_rdata({\u_riscv_top.core2_imem_rdata[31] ,
+    \u_riscv_top.core2_imem_rdata[30] ,
+    \u_riscv_top.core2_imem_rdata[29] ,
+    \u_riscv_top.core2_imem_rdata[28] ,
+    \u_riscv_top.core2_imem_rdata[27] ,
+    \u_riscv_top.core2_imem_rdata[26] ,
+    \u_riscv_top.core2_imem_rdata[25] ,
+    \u_riscv_top.core2_imem_rdata[24] ,
+    \u_riscv_top.core2_imem_rdata[23] ,
+    \u_riscv_top.core2_imem_rdata[22] ,
+    \u_riscv_top.core2_imem_rdata[21] ,
+    \u_riscv_top.core2_imem_rdata[20] ,
+    \u_riscv_top.core2_imem_rdata[19] ,
+    \u_riscv_top.core2_imem_rdata[18] ,
+    \u_riscv_top.core2_imem_rdata[17] ,
+    \u_riscv_top.core2_imem_rdata[16] ,
+    \u_riscv_top.core2_imem_rdata[15] ,
+    \u_riscv_top.core2_imem_rdata[14] ,
+    \u_riscv_top.core2_imem_rdata[13] ,
+    \u_riscv_top.core2_imem_rdata[12] ,
+    \u_riscv_top.core2_imem_rdata[11] ,
+    \u_riscv_top.core2_imem_rdata[10] ,
+    \u_riscv_top.core2_imem_rdata[9] ,
+    \u_riscv_top.core2_imem_rdata[8] ,
+    \u_riscv_top.core2_imem_rdata[7] ,
+    \u_riscv_top.core2_imem_rdata[6] ,
+    \u_riscv_top.core2_imem_rdata[5] ,
+    \u_riscv_top.core2_imem_rdata[4] ,
+    \u_riscv_top.core2_imem_rdata[3] ,
+    \u_riscv_top.core2_imem_rdata[2] ,
+    \u_riscv_top.core2_imem_rdata[1] ,
+    \u_riscv_top.core2_imem_rdata[0] }),
+    .core2_imem_resp({\u_riscv_top.core2_imem_resp[1] ,
+    \u_riscv_top.core2_imem_resp[0] }),
+    .core2_irq_lines({\u_riscv_top.core2_irq_lines[31] ,
+    \u_riscv_top.core2_irq_lines[30] ,
+    \u_riscv_top.core2_irq_lines[29] ,
+    \u_riscv_top.core2_irq_lines[28] ,
+    \u_riscv_top.core2_irq_lines[27] ,
+    \u_riscv_top.core2_irq_lines[26] ,
+    \u_riscv_top.core2_irq_lines[25] ,
+    \u_riscv_top.core2_irq_lines[24] ,
+    \u_riscv_top.core2_irq_lines[23] ,
+    \u_riscv_top.core2_irq_lines[22] ,
+    \u_riscv_top.core2_irq_lines[21] ,
+    \u_riscv_top.core2_irq_lines[20] ,
+    \u_riscv_top.core2_irq_lines[19] ,
+    \u_riscv_top.core2_irq_lines[18] ,
+    \u_riscv_top.core2_irq_lines[17] ,
+    \u_riscv_top.core2_irq_lines[16] ,
+    \u_riscv_top.core2_irq_lines[15] ,
+    \u_riscv_top.core2_irq_lines[14] ,
+    \u_riscv_top.core2_irq_lines[13] ,
+    \u_riscv_top.core2_irq_lines[12] ,
+    \u_riscv_top.core2_irq_lines[11] ,
+    \u_riscv_top.core2_irq_lines[10] ,
+    \u_riscv_top.core2_irq_lines[9] ,
+    \u_riscv_top.core2_irq_lines[8] ,
+    \u_riscv_top.core2_irq_lines[7] ,
+    \u_riscv_top.core2_irq_lines[6] ,
+    \u_riscv_top.core2_irq_lines[5] ,
+    \u_riscv_top.core2_irq_lines[4] ,
+    \u_riscv_top.core2_irq_lines[3] ,
+    \u_riscv_top.core2_irq_lines[2] ,
+    \u_riscv_top.core2_irq_lines[1] ,
+    \u_riscv_top.core2_irq_lines[0] }),
+    .core2_timer_val({\u_riscv_top.core2_timer_val[63] ,
+    \u_riscv_top.core2_timer_val[62] ,
+    \u_riscv_top.core2_timer_val[61] ,
+    \u_riscv_top.core2_timer_val[60] ,
+    \u_riscv_top.core2_timer_val[59] ,
+    \u_riscv_top.core2_timer_val[58] ,
+    \u_riscv_top.core2_timer_val[57] ,
+    \u_riscv_top.core2_timer_val[56] ,
+    \u_riscv_top.core2_timer_val[55] ,
+    \u_riscv_top.core2_timer_val[54] ,
+    \u_riscv_top.core2_timer_val[53] ,
+    \u_riscv_top.core2_timer_val[52] ,
+    \u_riscv_top.core2_timer_val[51] ,
+    \u_riscv_top.core2_timer_val[50] ,
+    \u_riscv_top.core2_timer_val[49] ,
+    \u_riscv_top.core2_timer_val[48] ,
+    \u_riscv_top.core2_timer_val[47] ,
+    \u_riscv_top.core2_timer_val[46] ,
+    \u_riscv_top.core2_timer_val[45] ,
+    \u_riscv_top.core2_timer_val[44] ,
+    \u_riscv_top.core2_timer_val[43] ,
+    \u_riscv_top.core2_timer_val[42] ,
+    \u_riscv_top.core2_timer_val[41] ,
+    \u_riscv_top.core2_timer_val[40] ,
+    \u_riscv_top.core2_timer_val[39] ,
+    \u_riscv_top.core2_timer_val[38] ,
+    \u_riscv_top.core2_timer_val[37] ,
+    \u_riscv_top.core2_timer_val[36] ,
+    \u_riscv_top.core2_timer_val[35] ,
+    \u_riscv_top.core2_timer_val[34] ,
+    \u_riscv_top.core2_timer_val[33] ,
+    \u_riscv_top.core2_timer_val[32] ,
+    \u_riscv_top.core2_timer_val[31] ,
+    \u_riscv_top.core2_timer_val[30] ,
+    \u_riscv_top.core2_timer_val[29] ,
+    \u_riscv_top.core2_timer_val[28] ,
+    \u_riscv_top.core2_timer_val[27] ,
+    \u_riscv_top.core2_timer_val[26] ,
+    \u_riscv_top.core2_timer_val[25] ,
+    \u_riscv_top.core2_timer_val[24] ,
+    \u_riscv_top.core2_timer_val[23] ,
+    \u_riscv_top.core2_timer_val[22] ,
+    \u_riscv_top.core2_timer_val[21] ,
+    \u_riscv_top.core2_timer_val[20] ,
+    \u_riscv_top.core2_timer_val[19] ,
+    \u_riscv_top.core2_timer_val[18] ,
+    \u_riscv_top.core2_timer_val[17] ,
+    \u_riscv_top.core2_timer_val[16] ,
+    \u_riscv_top.core2_timer_val[15] ,
+    \u_riscv_top.core2_timer_val[14] ,
+    \u_riscv_top.core2_timer_val[13] ,
+    \u_riscv_top.core2_timer_val[12] ,
+    \u_riscv_top.core2_timer_val[11] ,
+    \u_riscv_top.core2_timer_val[10] ,
+    \u_riscv_top.core2_timer_val[9] ,
+    \u_riscv_top.core2_timer_val[8] ,
+    \u_riscv_top.core2_timer_val[7] ,
+    \u_riscv_top.core2_timer_val[6] ,
+    \u_riscv_top.core2_timer_val[5] ,
+    \u_riscv_top.core2_timer_val[4] ,
+    \u_riscv_top.core2_timer_val[3] ,
+    \u_riscv_top.core2_timer_val[2] ,
+    \u_riscv_top.core2_timer_val[1] ,
+    \u_riscv_top.core2_timer_val[0] }),
+    .core2_uid({\u_riscv_top.core2_uid[1] ,
+    \u_riscv_top.core2_uid[0] }),
+    .core3_debug({\u_riscv_top.core3_debug[48] ,
+    \u_riscv_top.core3_debug[47] ,
+    \u_riscv_top.core3_debug[46] ,
+    \u_riscv_top.core3_debug[45] ,
+    \u_riscv_top.core3_debug[44] ,
+    \u_riscv_top.core3_debug[43] ,
+    \u_riscv_top.core3_debug[42] ,
+    \u_riscv_top.core3_debug[41] ,
+    \u_riscv_top.core3_debug[40] ,
+    \u_riscv_top.core3_debug[39] ,
+    \u_riscv_top.core3_debug[38] ,
+    \u_riscv_top.core3_debug[37] ,
+    \u_riscv_top.core3_debug[36] ,
+    \u_riscv_top.core3_debug[35] ,
+    \u_riscv_top.core3_debug[34] ,
+    \u_riscv_top.core3_debug[33] ,
+    \u_riscv_top.core3_debug[32] ,
+    \u_riscv_top.core3_debug[31] ,
+    \u_riscv_top.core3_debug[30] ,
+    \u_riscv_top.core3_debug[29] ,
+    \u_riscv_top.core3_debug[28] ,
+    \u_riscv_top.core3_debug[27] ,
+    \u_riscv_top.core3_debug[26] ,
+    \u_riscv_top.core3_debug[25] ,
+    \u_riscv_top.core3_debug[24] ,
+    \u_riscv_top.core3_debug[23] ,
+    \u_riscv_top.core3_debug[22] ,
+    \u_riscv_top.core3_debug[21] ,
+    \u_riscv_top.core3_debug[20] ,
+    \u_riscv_top.core3_debug[19] ,
+    \u_riscv_top.core3_debug[18] ,
+    \u_riscv_top.core3_debug[17] ,
+    \u_riscv_top.core3_debug[16] ,
+    \u_riscv_top.core3_debug[15] ,
+    \u_riscv_top.core3_debug[14] ,
+    \u_riscv_top.core3_debug[13] ,
+    \u_riscv_top.core3_debug[12] ,
+    \u_riscv_top.core3_debug[11] ,
+    \u_riscv_top.core3_debug[10] ,
+    \u_riscv_top.core3_debug[9] ,
+    \u_riscv_top.core3_debug[8] ,
+    \u_riscv_top.core3_debug[7] ,
+    \u_riscv_top.core3_debug[6] ,
+    \u_riscv_top.core3_debug[5] ,
+    \u_riscv_top.core3_debug[4] ,
+    \u_riscv_top.core3_debug[3] ,
+    \u_riscv_top.core3_debug[2] ,
+    \u_riscv_top.core3_debug[1] ,
+    \u_riscv_top.core3_debug[0] }),
+    .core3_dmem_addr({\u_riscv_top.core3_dmem_addr[31] ,
+    \u_riscv_top.core3_dmem_addr[30] ,
+    \u_riscv_top.core3_dmem_addr[29] ,
+    \u_riscv_top.core3_dmem_addr[28] ,
+    \u_riscv_top.core3_dmem_addr[27] ,
+    \u_riscv_top.core3_dmem_addr[26] ,
+    \u_riscv_top.core3_dmem_addr[25] ,
+    \u_riscv_top.core3_dmem_addr[24] ,
+    \u_riscv_top.core3_dmem_addr[23] ,
+    \u_riscv_top.core3_dmem_addr[22] ,
+    \u_riscv_top.core3_dmem_addr[21] ,
+    \u_riscv_top.core3_dmem_addr[20] ,
+    \u_riscv_top.core3_dmem_addr[19] ,
+    \u_riscv_top.core3_dmem_addr[18] ,
+    \u_riscv_top.core3_dmem_addr[17] ,
+    \u_riscv_top.core3_dmem_addr[16] ,
+    \u_riscv_top.core3_dmem_addr[15] ,
+    \u_riscv_top.core3_dmem_addr[14] ,
+    \u_riscv_top.core3_dmem_addr[13] ,
+    \u_riscv_top.core3_dmem_addr[12] ,
+    \u_riscv_top.core3_dmem_addr[11] ,
+    \u_riscv_top.core3_dmem_addr[10] ,
+    \u_riscv_top.core3_dmem_addr[9] ,
+    \u_riscv_top.core3_dmem_addr[8] ,
+    \u_riscv_top.core3_dmem_addr[7] ,
+    \u_riscv_top.core3_dmem_addr[6] ,
+    \u_riscv_top.core3_dmem_addr[5] ,
+    \u_riscv_top.core3_dmem_addr[4] ,
+    \u_riscv_top.core3_dmem_addr[3] ,
+    \u_riscv_top.core3_dmem_addr[2] ,
+    \u_riscv_top.core3_dmem_addr[1] ,
+    \u_riscv_top.core3_dmem_addr[0] }),
+    .core3_dmem_rdata({\u_riscv_top.core3_dmem_rdata[31] ,
+    \u_riscv_top.core3_dmem_rdata[30] ,
+    \u_riscv_top.core3_dmem_rdata[29] ,
+    \u_riscv_top.core3_dmem_rdata[28] ,
+    \u_riscv_top.core3_dmem_rdata[27] ,
+    \u_riscv_top.core3_dmem_rdata[26] ,
+    \u_riscv_top.core3_dmem_rdata[25] ,
+    \u_riscv_top.core3_dmem_rdata[24] ,
+    \u_riscv_top.core3_dmem_rdata[23] ,
+    \u_riscv_top.core3_dmem_rdata[22] ,
+    \u_riscv_top.core3_dmem_rdata[21] ,
+    \u_riscv_top.core3_dmem_rdata[20] ,
+    \u_riscv_top.core3_dmem_rdata[19] ,
+    \u_riscv_top.core3_dmem_rdata[18] ,
+    \u_riscv_top.core3_dmem_rdata[17] ,
+    \u_riscv_top.core3_dmem_rdata[16] ,
+    \u_riscv_top.core3_dmem_rdata[15] ,
+    \u_riscv_top.core3_dmem_rdata[14] ,
+    \u_riscv_top.core3_dmem_rdata[13] ,
+    \u_riscv_top.core3_dmem_rdata[12] ,
+    \u_riscv_top.core3_dmem_rdata[11] ,
+    \u_riscv_top.core3_dmem_rdata[10] ,
+    \u_riscv_top.core3_dmem_rdata[9] ,
+    \u_riscv_top.core3_dmem_rdata[8] ,
+    \u_riscv_top.core3_dmem_rdata[7] ,
+    \u_riscv_top.core3_dmem_rdata[6] ,
+    \u_riscv_top.core3_dmem_rdata[5] ,
+    \u_riscv_top.core3_dmem_rdata[4] ,
+    \u_riscv_top.core3_dmem_rdata[3] ,
+    \u_riscv_top.core3_dmem_rdata[2] ,
+    \u_riscv_top.core3_dmem_rdata[1] ,
+    \u_riscv_top.core3_dmem_rdata[0] }),
+    .core3_dmem_resp({\u_riscv_top.core3_dmem_resp[1] ,
+    \u_riscv_top.core3_dmem_resp[0] }),
+    .core3_dmem_wdata({\u_riscv_top.core3_dmem_wdata[31] ,
+    \u_riscv_top.core3_dmem_wdata[30] ,
+    \u_riscv_top.core3_dmem_wdata[29] ,
+    \u_riscv_top.core3_dmem_wdata[28] ,
+    \u_riscv_top.core3_dmem_wdata[27] ,
+    \u_riscv_top.core3_dmem_wdata[26] ,
+    \u_riscv_top.core3_dmem_wdata[25] ,
+    \u_riscv_top.core3_dmem_wdata[24] ,
+    \u_riscv_top.core3_dmem_wdata[23] ,
+    \u_riscv_top.core3_dmem_wdata[22] ,
+    \u_riscv_top.core3_dmem_wdata[21] ,
+    \u_riscv_top.core3_dmem_wdata[20] ,
+    \u_riscv_top.core3_dmem_wdata[19] ,
+    \u_riscv_top.core3_dmem_wdata[18] ,
+    \u_riscv_top.core3_dmem_wdata[17] ,
+    \u_riscv_top.core3_dmem_wdata[16] ,
+    \u_riscv_top.core3_dmem_wdata[15] ,
+    \u_riscv_top.core3_dmem_wdata[14] ,
+    \u_riscv_top.core3_dmem_wdata[13] ,
+    \u_riscv_top.core3_dmem_wdata[12] ,
+    \u_riscv_top.core3_dmem_wdata[11] ,
+    \u_riscv_top.core3_dmem_wdata[10] ,
+    \u_riscv_top.core3_dmem_wdata[9] ,
+    \u_riscv_top.core3_dmem_wdata[8] ,
+    \u_riscv_top.core3_dmem_wdata[7] ,
+    \u_riscv_top.core3_dmem_wdata[6] ,
+    \u_riscv_top.core3_dmem_wdata[5] ,
+    \u_riscv_top.core3_dmem_wdata[4] ,
+    \u_riscv_top.core3_dmem_wdata[3] ,
+    \u_riscv_top.core3_dmem_wdata[2] ,
+    \u_riscv_top.core3_dmem_wdata[1] ,
+    \u_riscv_top.core3_dmem_wdata[0] }),
+    .core3_dmem_width({\u_riscv_top.core3_dmem_width[1] ,
+    \u_riscv_top.core3_dmem_width[0] }),
+    .core3_imem_addr({\u_riscv_top.core3_imem_addr[31] ,
+    \u_riscv_top.core3_imem_addr[30] ,
+    \u_riscv_top.core3_imem_addr[29] ,
+    \u_riscv_top.core3_imem_addr[28] ,
+    \u_riscv_top.core3_imem_addr[27] ,
+    \u_riscv_top.core3_imem_addr[26] ,
+    \u_riscv_top.core3_imem_addr[25] ,
+    \u_riscv_top.core3_imem_addr[24] ,
+    \u_riscv_top.core3_imem_addr[23] ,
+    \u_riscv_top.core3_imem_addr[22] ,
+    \u_riscv_top.core3_imem_addr[21] ,
+    \u_riscv_top.core3_imem_addr[20] ,
+    \u_riscv_top.core3_imem_addr[19] ,
+    \u_riscv_top.core3_imem_addr[18] ,
+    \u_riscv_top.core3_imem_addr[17] ,
+    \u_riscv_top.core3_imem_addr[16] ,
+    \u_riscv_top.core3_imem_addr[15] ,
+    \u_riscv_top.core3_imem_addr[14] ,
+    \u_riscv_top.core3_imem_addr[13] ,
+    \u_riscv_top.core3_imem_addr[12] ,
+    \u_riscv_top.core3_imem_addr[11] ,
+    \u_riscv_top.core3_imem_addr[10] ,
+    \u_riscv_top.core3_imem_addr[9] ,
+    \u_riscv_top.core3_imem_addr[8] ,
+    \u_riscv_top.core3_imem_addr[7] ,
+    \u_riscv_top.core3_imem_addr[6] ,
+    \u_riscv_top.core3_imem_addr[5] ,
+    \u_riscv_top.core3_imem_addr[4] ,
+    \u_riscv_top.core3_imem_addr[3] ,
+    \u_riscv_top.core3_imem_addr[2] ,
+    \u_riscv_top.core3_imem_addr[1] ,
+    \u_riscv_top.core3_imem_addr[0] }),
+    .core3_imem_bl({\u_riscv_top.core3_imem_bl[2] ,
+    \u_riscv_top.core3_imem_bl[1] ,
+    \u_riscv_top.core3_imem_bl[0] }),
+    .core3_imem_rdata({\u_riscv_top.core3_imem_rdata[31] ,
+    \u_riscv_top.core3_imem_rdata[30] ,
+    \u_riscv_top.core3_imem_rdata[29] ,
+    \u_riscv_top.core3_imem_rdata[28] ,
+    \u_riscv_top.core3_imem_rdata[27] ,
+    \u_riscv_top.core3_imem_rdata[26] ,
+    \u_riscv_top.core3_imem_rdata[25] ,
+    \u_riscv_top.core3_imem_rdata[24] ,
+    \u_riscv_top.core3_imem_rdata[23] ,
+    \u_riscv_top.core3_imem_rdata[22] ,
+    \u_riscv_top.core3_imem_rdata[21] ,
+    \u_riscv_top.core3_imem_rdata[20] ,
+    \u_riscv_top.core3_imem_rdata[19] ,
+    \u_riscv_top.core3_imem_rdata[18] ,
+    \u_riscv_top.core3_imem_rdata[17] ,
+    \u_riscv_top.core3_imem_rdata[16] ,
+    \u_riscv_top.core3_imem_rdata[15] ,
+    \u_riscv_top.core3_imem_rdata[14] ,
+    \u_riscv_top.core3_imem_rdata[13] ,
+    \u_riscv_top.core3_imem_rdata[12] ,
+    \u_riscv_top.core3_imem_rdata[11] ,
+    \u_riscv_top.core3_imem_rdata[10] ,
+    \u_riscv_top.core3_imem_rdata[9] ,
+    \u_riscv_top.core3_imem_rdata[8] ,
+    \u_riscv_top.core3_imem_rdata[7] ,
+    \u_riscv_top.core3_imem_rdata[6] ,
+    \u_riscv_top.core3_imem_rdata[5] ,
+    \u_riscv_top.core3_imem_rdata[4] ,
+    \u_riscv_top.core3_imem_rdata[3] ,
+    \u_riscv_top.core3_imem_rdata[2] ,
+    \u_riscv_top.core3_imem_rdata[1] ,
+    \u_riscv_top.core3_imem_rdata[0] }),
+    .core3_imem_resp({\u_riscv_top.core3_imem_resp[1] ,
+    \u_riscv_top.core3_imem_resp[0] }),
+    .core3_irq_lines({\u_riscv_top.core3_irq_lines[31] ,
+    \u_riscv_top.core3_irq_lines[30] ,
+    \u_riscv_top.core3_irq_lines[29] ,
+    \u_riscv_top.core3_irq_lines[28] ,
+    \u_riscv_top.core3_irq_lines[27] ,
+    \u_riscv_top.core3_irq_lines[26] ,
+    \u_riscv_top.core3_irq_lines[25] ,
+    \u_riscv_top.core3_irq_lines[24] ,
+    \u_riscv_top.core3_irq_lines[23] ,
+    \u_riscv_top.core3_irq_lines[22] ,
+    \u_riscv_top.core3_irq_lines[21] ,
+    \u_riscv_top.core3_irq_lines[20] ,
+    \u_riscv_top.core3_irq_lines[19] ,
+    \u_riscv_top.core3_irq_lines[18] ,
+    \u_riscv_top.core3_irq_lines[17] ,
+    \u_riscv_top.core3_irq_lines[16] ,
+    \u_riscv_top.core3_irq_lines[15] ,
+    \u_riscv_top.core3_irq_lines[14] ,
+    \u_riscv_top.core3_irq_lines[13] ,
+    \u_riscv_top.core3_irq_lines[12] ,
+    \u_riscv_top.core3_irq_lines[11] ,
+    \u_riscv_top.core3_irq_lines[10] ,
+    \u_riscv_top.core3_irq_lines[9] ,
+    \u_riscv_top.core3_irq_lines[8] ,
+    \u_riscv_top.core3_irq_lines[7] ,
+    \u_riscv_top.core3_irq_lines[6] ,
+    \u_riscv_top.core3_irq_lines[5] ,
+    \u_riscv_top.core3_irq_lines[4] ,
+    \u_riscv_top.core3_irq_lines[3] ,
+    \u_riscv_top.core3_irq_lines[2] ,
+    \u_riscv_top.core3_irq_lines[1] ,
+    \u_riscv_top.core3_irq_lines[0] }),
+    .core3_timer_val({\u_riscv_top.core3_timer_val[63] ,
+    \u_riscv_top.core3_timer_val[62] ,
+    \u_riscv_top.core3_timer_val[61] ,
+    \u_riscv_top.core3_timer_val[60] ,
+    \u_riscv_top.core3_timer_val[59] ,
+    \u_riscv_top.core3_timer_val[58] ,
+    \u_riscv_top.core3_timer_val[57] ,
+    \u_riscv_top.core3_timer_val[56] ,
+    \u_riscv_top.core3_timer_val[55] ,
+    \u_riscv_top.core3_timer_val[54] ,
+    \u_riscv_top.core3_timer_val[53] ,
+    \u_riscv_top.core3_timer_val[52] ,
+    \u_riscv_top.core3_timer_val[51] ,
+    \u_riscv_top.core3_timer_val[50] ,
+    \u_riscv_top.core3_timer_val[49] ,
+    \u_riscv_top.core3_timer_val[48] ,
+    \u_riscv_top.core3_timer_val[47] ,
+    \u_riscv_top.core3_timer_val[46] ,
+    \u_riscv_top.core3_timer_val[45] ,
+    \u_riscv_top.core3_timer_val[44] ,
+    \u_riscv_top.core3_timer_val[43] ,
+    \u_riscv_top.core3_timer_val[42] ,
+    \u_riscv_top.core3_timer_val[41] ,
+    \u_riscv_top.core3_timer_val[40] ,
+    \u_riscv_top.core3_timer_val[39] ,
+    \u_riscv_top.core3_timer_val[38] ,
+    \u_riscv_top.core3_timer_val[37] ,
+    \u_riscv_top.core3_timer_val[36] ,
+    \u_riscv_top.core3_timer_val[35] ,
+    \u_riscv_top.core3_timer_val[34] ,
+    \u_riscv_top.core3_timer_val[33] ,
+    \u_riscv_top.core3_timer_val[32] ,
+    \u_riscv_top.core3_timer_val[31] ,
+    \u_riscv_top.core3_timer_val[30] ,
+    \u_riscv_top.core3_timer_val[29] ,
+    \u_riscv_top.core3_timer_val[28] ,
+    \u_riscv_top.core3_timer_val[27] ,
+    \u_riscv_top.core3_timer_val[26] ,
+    \u_riscv_top.core3_timer_val[25] ,
+    \u_riscv_top.core3_timer_val[24] ,
+    \u_riscv_top.core3_timer_val[23] ,
+    \u_riscv_top.core3_timer_val[22] ,
+    \u_riscv_top.core3_timer_val[21] ,
+    \u_riscv_top.core3_timer_val[20] ,
+    \u_riscv_top.core3_timer_val[19] ,
+    \u_riscv_top.core3_timer_val[18] ,
+    \u_riscv_top.core3_timer_val[17] ,
+    \u_riscv_top.core3_timer_val[16] ,
+    \u_riscv_top.core3_timer_val[15] ,
+    \u_riscv_top.core3_timer_val[14] ,
+    \u_riscv_top.core3_timer_val[13] ,
+    \u_riscv_top.core3_timer_val[12] ,
+    \u_riscv_top.core3_timer_val[11] ,
+    \u_riscv_top.core3_timer_val[10] ,
+    \u_riscv_top.core3_timer_val[9] ,
+    \u_riscv_top.core3_timer_val[8] ,
+    \u_riscv_top.core3_timer_val[7] ,
+    \u_riscv_top.core3_timer_val[6] ,
+    \u_riscv_top.core3_timer_val[5] ,
+    \u_riscv_top.core3_timer_val[4] ,
+    \u_riscv_top.core3_timer_val[3] ,
+    \u_riscv_top.core3_timer_val[2] ,
+    \u_riscv_top.core3_timer_val[1] ,
+    \u_riscv_top.core3_timer_val[0] }),
+    .core3_uid({\u_riscv_top.core3_uid[1] ,
+    \u_riscv_top.core3_uid[0] }),
+    .core_dcache_addr({\u_riscv_top.core_dcache_addr[31] ,
+    \u_riscv_top.core_dcache_addr[30] ,
+    \u_riscv_top.core_dcache_addr[29] ,
+    \u_riscv_top.core_dcache_addr[28] ,
+    \u_riscv_top.core_dcache_addr[27] ,
+    \u_riscv_top.core_dcache_addr[26] ,
+    \u_riscv_top.core_dcache_addr[25] ,
+    \u_riscv_top.core_dcache_addr[24] ,
+    \u_riscv_top.core_dcache_addr[23] ,
+    \u_riscv_top.core_dcache_addr[22] ,
+    \u_riscv_top.core_dcache_addr[21] ,
+    \u_riscv_top.core_dcache_addr[20] ,
+    \u_riscv_top.core_dcache_addr[19] ,
+    \u_riscv_top.core_dcache_addr[18] ,
+    \u_riscv_top.core_dcache_addr[17] ,
+    \u_riscv_top.core_dcache_addr[16] ,
+    \u_riscv_top.core_dcache_addr[15] ,
+    \u_riscv_top.core_dcache_addr[14] ,
+    \u_riscv_top.core_dcache_addr[13] ,
+    \u_riscv_top.core_dcache_addr[12] ,
+    \u_riscv_top.core_dcache_addr[11] ,
+    \u_riscv_top.core_dcache_addr[10] ,
+    \u_riscv_top.core_dcache_addr[9] ,
+    \u_riscv_top.core_dcache_addr[8] ,
+    \u_riscv_top.core_dcache_addr[7] ,
+    \u_riscv_top.core_dcache_addr[6] ,
+    \u_riscv_top.core_dcache_addr[5] ,
+    \u_riscv_top.core_dcache_addr[4] ,
+    \u_riscv_top.core_dcache_addr[3] ,
+    \u_riscv_top.core_dcache_addr[2] ,
+    \u_riscv_top.core_dcache_addr[1] ,
+    \u_riscv_top.core_dcache_addr[0] }),
+    .core_dcache_rdata({\u_riscv_top.core_dcache_rdata[31] ,
+    \u_riscv_top.core_dcache_rdata[30] ,
+    \u_riscv_top.core_dcache_rdata[29] ,
+    \u_riscv_top.core_dcache_rdata[28] ,
+    \u_riscv_top.core_dcache_rdata[27] ,
+    \u_riscv_top.core_dcache_rdata[26] ,
+    \u_riscv_top.core_dcache_rdata[25] ,
+    \u_riscv_top.core_dcache_rdata[24] ,
+    \u_riscv_top.core_dcache_rdata[23] ,
+    \u_riscv_top.core_dcache_rdata[22] ,
+    \u_riscv_top.core_dcache_rdata[21] ,
+    \u_riscv_top.core_dcache_rdata[20] ,
+    \u_riscv_top.core_dcache_rdata[19] ,
+    \u_riscv_top.core_dcache_rdata[18] ,
+    \u_riscv_top.core_dcache_rdata[17] ,
+    \u_riscv_top.core_dcache_rdata[16] ,
+    \u_riscv_top.core_dcache_rdata[15] ,
+    \u_riscv_top.core_dcache_rdata[14] ,
+    \u_riscv_top.core_dcache_rdata[13] ,
+    \u_riscv_top.core_dcache_rdata[12] ,
+    \u_riscv_top.core_dcache_rdata[11] ,
+    \u_riscv_top.core_dcache_rdata[10] ,
+    \u_riscv_top.core_dcache_rdata[9] ,
+    \u_riscv_top.core_dcache_rdata[8] ,
+    \u_riscv_top.core_dcache_rdata[7] ,
+    \u_riscv_top.core_dcache_rdata[6] ,
+    \u_riscv_top.core_dcache_rdata[5] ,
+    \u_riscv_top.core_dcache_rdata[4] ,
+    \u_riscv_top.core_dcache_rdata[3] ,
+    \u_riscv_top.core_dcache_rdata[2] ,
+    \u_riscv_top.core_dcache_rdata[1] ,
+    \u_riscv_top.core_dcache_rdata[0] }),
+    .core_dcache_resp({\u_riscv_top.core_dcache_resp[1] ,
+    \u_riscv_top.core_dcache_resp[0] }),
+    .core_dcache_wdata({\u_riscv_top.core_dcache_wdata[31] ,
+    \u_riscv_top.core_dcache_wdata[30] ,
+    \u_riscv_top.core_dcache_wdata[29] ,
+    \u_riscv_top.core_dcache_wdata[28] ,
+    \u_riscv_top.core_dcache_wdata[27] ,
+    \u_riscv_top.core_dcache_wdata[26] ,
+    \u_riscv_top.core_dcache_wdata[25] ,
+    \u_riscv_top.core_dcache_wdata[24] ,
+    \u_riscv_top.core_dcache_wdata[23] ,
+    \u_riscv_top.core_dcache_wdata[22] ,
+    \u_riscv_top.core_dcache_wdata[21] ,
+    \u_riscv_top.core_dcache_wdata[20] ,
+    \u_riscv_top.core_dcache_wdata[19] ,
+    \u_riscv_top.core_dcache_wdata[18] ,
+    \u_riscv_top.core_dcache_wdata[17] ,
+    \u_riscv_top.core_dcache_wdata[16] ,
+    \u_riscv_top.core_dcache_wdata[15] ,
+    \u_riscv_top.core_dcache_wdata[14] ,
+    \u_riscv_top.core_dcache_wdata[13] ,
+    \u_riscv_top.core_dcache_wdata[12] ,
+    \u_riscv_top.core_dcache_wdata[11] ,
+    \u_riscv_top.core_dcache_wdata[10] ,
+    \u_riscv_top.core_dcache_wdata[9] ,
+    \u_riscv_top.core_dcache_wdata[8] ,
+    \u_riscv_top.core_dcache_wdata[7] ,
+    \u_riscv_top.core_dcache_wdata[6] ,
+    \u_riscv_top.core_dcache_wdata[5] ,
+    \u_riscv_top.core_dcache_wdata[4] ,
+    \u_riscv_top.core_dcache_wdata[3] ,
+    \u_riscv_top.core_dcache_wdata[2] ,
+    \u_riscv_top.core_dcache_wdata[1] ,
+    \u_riscv_top.core_dcache_wdata[0] }),
+    .core_dcache_width({\u_riscv_top.core_dcache_width[1] ,
+    \u_riscv_top.core_dcache_width[0] }),
+    .core_debug_sel({\cfg_riscv_ctrl[9] ,
+    \cfg_riscv_ctrl[8] }),
+    .core_dmem_addr({\u_riscv_top.core_dmem_addr[31] ,
+    \u_riscv_top.core_dmem_addr[30] ,
+    \u_riscv_top.core_dmem_addr[29] ,
+    \u_riscv_top.core_dmem_addr[28] ,
+    \u_riscv_top.core_dmem_addr[27] ,
+    \u_riscv_top.core_dmem_addr[26] ,
+    \u_riscv_top.core_dmem_addr[25] ,
+    \u_riscv_top.core_dmem_addr[24] ,
+    \u_riscv_top.core_dmem_addr[23] ,
+    \u_riscv_top.core_dmem_addr[22] ,
+    \u_riscv_top.core_dmem_addr[21] ,
+    \u_riscv_top.core_dmem_addr[20] ,
+    \u_riscv_top.core_dmem_addr[19] ,
+    \u_riscv_top.core_dmem_addr[18] ,
+    \u_riscv_top.core_dmem_addr[17] ,
+    \u_riscv_top.core_dmem_addr[16] ,
+    \u_riscv_top.core_dmem_addr[15] ,
+    \u_riscv_top.core_dmem_addr[14] ,
+    \u_riscv_top.core_dmem_addr[13] ,
+    \u_riscv_top.core_dmem_addr[12] ,
+    \u_riscv_top.core_dmem_addr[11] ,
+    \u_riscv_top.core_dmem_addr[10] ,
+    \u_riscv_top.core_dmem_addr[9] ,
+    \u_riscv_top.core_dmem_addr[8] ,
+    \u_riscv_top.core_dmem_addr[7] ,
+    \u_riscv_top.core_dmem_addr[6] ,
+    \u_riscv_top.core_dmem_addr[5] ,
+    \u_riscv_top.core_dmem_addr[4] ,
+    \u_riscv_top.core_dmem_addr[3] ,
+    \u_riscv_top.core_dmem_addr[2] ,
+    \u_riscv_top.core_dmem_addr[1] ,
+    \u_riscv_top.core_dmem_addr[0] }),
+    .core_dmem_bl({\u_riscv_top.core_dmem_bl[2] ,
+    \u_riscv_top.core_dmem_bl[1] ,
+    \u_riscv_top.core_dmem_bl[0] }),
+    .core_dmem_rdata({\u_riscv_top.core_dmem_rdata[31] ,
+    \u_riscv_top.core_dmem_rdata[30] ,
+    \u_riscv_top.core_dmem_rdata[29] ,
+    \u_riscv_top.core_dmem_rdata[28] ,
+    \u_riscv_top.core_dmem_rdata[27] ,
+    \u_riscv_top.core_dmem_rdata[26] ,
+    \u_riscv_top.core_dmem_rdata[25] ,
+    \u_riscv_top.core_dmem_rdata[24] ,
+    \u_riscv_top.core_dmem_rdata[23] ,
+    \u_riscv_top.core_dmem_rdata[22] ,
+    \u_riscv_top.core_dmem_rdata[21] ,
+    \u_riscv_top.core_dmem_rdata[20] ,
+    \u_riscv_top.core_dmem_rdata[19] ,
+    \u_riscv_top.core_dmem_rdata[18] ,
+    \u_riscv_top.core_dmem_rdata[17] ,
+    \u_riscv_top.core_dmem_rdata[16] ,
+    \u_riscv_top.core_dmem_rdata[15] ,
+    \u_riscv_top.core_dmem_rdata[14] ,
+    \u_riscv_top.core_dmem_rdata[13] ,
+    \u_riscv_top.core_dmem_rdata[12] ,
+    \u_riscv_top.core_dmem_rdata[11] ,
+    \u_riscv_top.core_dmem_rdata[10] ,
+    \u_riscv_top.core_dmem_rdata[9] ,
+    \u_riscv_top.core_dmem_rdata[8] ,
+    \u_riscv_top.core_dmem_rdata[7] ,
+    \u_riscv_top.core_dmem_rdata[6] ,
+    \u_riscv_top.core_dmem_rdata[5] ,
+    \u_riscv_top.core_dmem_rdata[4] ,
+    \u_riscv_top.core_dmem_rdata[3] ,
+    \u_riscv_top.core_dmem_rdata[2] ,
+    \u_riscv_top.core_dmem_rdata[1] ,
+    \u_riscv_top.core_dmem_rdata[0] }),
+    .core_dmem_resp({\u_riscv_top.core_dmem_resp[1] ,
+    \u_riscv_top.core_dmem_resp[0] }),
+    .core_dmem_wdata({\u_riscv_top.core_dmem_wdata[31] ,
+    \u_riscv_top.core_dmem_wdata[30] ,
+    \u_riscv_top.core_dmem_wdata[29] ,
+    \u_riscv_top.core_dmem_wdata[28] ,
+    \u_riscv_top.core_dmem_wdata[27] ,
+    \u_riscv_top.core_dmem_wdata[26] ,
+    \u_riscv_top.core_dmem_wdata[25] ,
+    \u_riscv_top.core_dmem_wdata[24] ,
+    \u_riscv_top.core_dmem_wdata[23] ,
+    \u_riscv_top.core_dmem_wdata[22] ,
+    \u_riscv_top.core_dmem_wdata[21] ,
+    \u_riscv_top.core_dmem_wdata[20] ,
+    \u_riscv_top.core_dmem_wdata[19] ,
+    \u_riscv_top.core_dmem_wdata[18] ,
+    \u_riscv_top.core_dmem_wdata[17] ,
+    \u_riscv_top.core_dmem_wdata[16] ,
+    \u_riscv_top.core_dmem_wdata[15] ,
+    \u_riscv_top.core_dmem_wdata[14] ,
+    \u_riscv_top.core_dmem_wdata[13] ,
+    \u_riscv_top.core_dmem_wdata[12] ,
+    \u_riscv_top.core_dmem_wdata[11] ,
+    \u_riscv_top.core_dmem_wdata[10] ,
+    \u_riscv_top.core_dmem_wdata[9] ,
+    \u_riscv_top.core_dmem_wdata[8] ,
+    \u_riscv_top.core_dmem_wdata[7] ,
+    \u_riscv_top.core_dmem_wdata[6] ,
+    \u_riscv_top.core_dmem_wdata[5] ,
+    \u_riscv_top.core_dmem_wdata[4] ,
+    \u_riscv_top.core_dmem_wdata[3] ,
+    \u_riscv_top.core_dmem_wdata[2] ,
+    \u_riscv_top.core_dmem_wdata[1] ,
+    \u_riscv_top.core_dmem_wdata[0] }),
+    .core_dmem_width({\u_riscv_top.core_dmem_width[1] ,
+    \u_riscv_top.core_dmem_width[0] }),
+    .core_icache_addr({\u_riscv_top.core_icache_addr[31] ,
+    \u_riscv_top.core_icache_addr[30] ,
+    \u_riscv_top.core_icache_addr[29] ,
+    \u_riscv_top.core_icache_addr[28] ,
+    \u_riscv_top.core_icache_addr[27] ,
+    \u_riscv_top.core_icache_addr[26] ,
+    \u_riscv_top.core_icache_addr[25] ,
+    \u_riscv_top.core_icache_addr[24] ,
+    \u_riscv_top.core_icache_addr[23] ,
+    \u_riscv_top.core_icache_addr[22] ,
+    \u_riscv_top.core_icache_addr[21] ,
+    \u_riscv_top.core_icache_addr[20] ,
+    \u_riscv_top.core_icache_addr[19] ,
+    \u_riscv_top.core_icache_addr[18] ,
+    \u_riscv_top.core_icache_addr[17] ,
+    \u_riscv_top.core_icache_addr[16] ,
+    \u_riscv_top.core_icache_addr[15] ,
+    \u_riscv_top.core_icache_addr[14] ,
+    \u_riscv_top.core_icache_addr[13] ,
+    \u_riscv_top.core_icache_addr[12] ,
+    \u_riscv_top.core_icache_addr[11] ,
+    \u_riscv_top.core_icache_addr[10] ,
+    \u_riscv_top.core_icache_addr[9] ,
+    \u_riscv_top.core_icache_addr[8] ,
+    \u_riscv_top.core_icache_addr[7] ,
+    \u_riscv_top.core_icache_addr[6] ,
+    \u_riscv_top.core_icache_addr[5] ,
+    \u_riscv_top.core_icache_addr[4] ,
+    \u_riscv_top.core_icache_addr[3] ,
+    \u_riscv_top.core_icache_addr[2] ,
+    \u_riscv_top.core_icache_addr[1] ,
+    \u_riscv_top.core_icache_addr[0] }),
+    .core_icache_bl({\u_riscv_top.core_icache_bl[2] ,
+    \u_riscv_top.core_icache_bl[1] ,
+    \u_riscv_top.core_icache_bl[0] }),
+    .core_icache_rdata({\u_riscv_top.core_icache_rdata[31] ,
+    \u_riscv_top.core_icache_rdata[30] ,
+    \u_riscv_top.core_icache_rdata[29] ,
+    \u_riscv_top.core_icache_rdata[28] ,
+    \u_riscv_top.core_icache_rdata[27] ,
+    \u_riscv_top.core_icache_rdata[26] ,
+    \u_riscv_top.core_icache_rdata[25] ,
+    \u_riscv_top.core_icache_rdata[24] ,
+    \u_riscv_top.core_icache_rdata[23] ,
+    \u_riscv_top.core_icache_rdata[22] ,
+    \u_riscv_top.core_icache_rdata[21] ,
+    \u_riscv_top.core_icache_rdata[20] ,
+    \u_riscv_top.core_icache_rdata[19] ,
+    \u_riscv_top.core_icache_rdata[18] ,
+    \u_riscv_top.core_icache_rdata[17] ,
+    \u_riscv_top.core_icache_rdata[16] ,
+    \u_riscv_top.core_icache_rdata[15] ,
+    \u_riscv_top.core_icache_rdata[14] ,
+    \u_riscv_top.core_icache_rdata[13] ,
+    \u_riscv_top.core_icache_rdata[12] ,
+    \u_riscv_top.core_icache_rdata[11] ,
+    \u_riscv_top.core_icache_rdata[10] ,
+    \u_riscv_top.core_icache_rdata[9] ,
+    \u_riscv_top.core_icache_rdata[8] ,
+    \u_riscv_top.core_icache_rdata[7] ,
+    \u_riscv_top.core_icache_rdata[6] ,
+    \u_riscv_top.core_icache_rdata[5] ,
+    \u_riscv_top.core_icache_rdata[4] ,
+    \u_riscv_top.core_icache_rdata[3] ,
+    \u_riscv_top.core_icache_rdata[2] ,
+    \u_riscv_top.core_icache_rdata[1] ,
+    \u_riscv_top.core_icache_rdata[0] }),
+    .core_icache_resp({\u_riscv_top.core_icache_resp[1] ,
+    \u_riscv_top.core_icache_resp[0] }),
+    .core_icache_width({\u_riscv_top.core_icache_width[1] ,
+    \u_riscv_top.core_icache_width[0] }),
+    .core_irq_lines_i({\u_riscv_top.irq_lines[31] ,
+    \u_riscv_top.irq_lines[30] ,
+    \u_riscv_top.irq_lines[29] ,
+    \u_riscv_top.irq_lines[28] ,
+    \u_riscv_top.irq_lines[27] ,
+    \u_riscv_top.irq_lines[26] ,
+    \u_riscv_top.irq_lines[25] ,
+    \u_riscv_top.irq_lines[24] ,
+    \u_riscv_top.irq_lines[23] ,
+    \u_riscv_top.irq_lines[22] ,
+    \u_riscv_top.irq_lines[21] ,
+    \u_riscv_top.irq_lines[20] ,
+    \u_riscv_top.irq_lines[19] ,
+    \u_riscv_top.irq_lines[18] ,
+    \u_riscv_top.irq_lines[17] ,
+    \u_riscv_top.irq_lines[16] ,
+    \u_riscv_top.irq_lines[15] ,
+    \u_riscv_top.irq_lines[14] ,
+    \u_riscv_top.irq_lines[13] ,
+    \u_riscv_top.irq_lines[12] ,
+    \u_riscv_top.irq_lines[11] ,
+    \u_riscv_top.irq_lines[10] ,
+    \u_riscv_top.irq_lines[9] ,
+    \u_riscv_top.irq_lines[8] ,
+    \u_riscv_top.irq_lines[7] ,
+    \u_riscv_top.irq_lines[6] ,
+    \u_riscv_top.irq_lines[5] ,
+    \u_riscv_top.irq_lines[4] ,
+    \u_riscv_top.irq_lines[3] ,
+    \u_riscv_top.irq_lines[2] ,
+    \u_riscv_top.irq_lines[1] ,
+    \u_riscv_top.irq_lines[0] }),
+    .riscv_debug({la_data_out[63],
+    la_data_out[62],
+    la_data_out[61],
+    la_data_out[60],
+    la_data_out[59],
+    la_data_out[58],
+    la_data_out[57],
+    la_data_out[56],
+    la_data_out[55],
+    la_data_out[54],
+    la_data_out[53],
+    la_data_out[52],
+    la_data_out[51],
+    la_data_out[50],
+    la_data_out[49],
+    la_data_out[48],
+    la_data_out[47],
+    la_data_out[46],
+    la_data_out[45],
+    la_data_out[44],
+    la_data_out[43],
+    la_data_out[42],
+    la_data_out[41],
+    la_data_out[40],
+    la_data_out[39],
+    la_data_out[38],
+    la_data_out[37],
+    la_data_out[36],
+    la_data_out[35],
+    la_data_out[34],
+    la_data_out[33],
+    la_data_out[32],
+    la_data_out[31],
+    la_data_out[30],
+    la_data_out[29],
+    la_data_out[28],
+    la_data_out[27],
+    la_data_out[26],
+    la_data_out[25],
+    la_data_out[24],
+    la_data_out[23],
+    la_data_out[22],
+    la_data_out[21],
+    la_data_out[20],
+    la_data_out[19],
+    la_data_out[18],
+    la_data_out[17],
+    la_data_out[16],
+    la_data_out[15],
+    la_data_out[14],
+    la_data_out[13],
+    la_data_out[12],
+    la_data_out[11],
+    la_data_out[10],
+    la_data_out[9],
+    la_data_out[8],
+    la_data_out[7],
+    la_data_out[6],
+    la_data_out[5],
+    la_data_out[4],
+    la_data_out[3],
+    la_data_out[2],
+    la_data_out[1],
+    la_data_out[0]}),
+    .sram0_addr0({\u_riscv_top.sram0_addr0[8] ,
+    \u_riscv_top.sram0_addr0[7] ,
+    \u_riscv_top.sram0_addr0[6] ,
+    \u_riscv_top.sram0_addr0[5] ,
+    \u_riscv_top.sram0_addr0[4] ,
+    \u_riscv_top.sram0_addr0[3] ,
+    \u_riscv_top.sram0_addr0[2] ,
+    \u_riscv_top.sram0_addr0[1] ,
+    \u_riscv_top.sram0_addr0[0] }),
+    .sram0_addr1({\u_riscv_top.sram0_addr1[8] ,
+    \u_riscv_top.sram0_addr1[7] ,
+    \u_riscv_top.sram0_addr1[6] ,
+    \u_riscv_top.sram0_addr1[5] ,
+    \u_riscv_top.sram0_addr1[4] ,
+    \u_riscv_top.sram0_addr1[3] ,
+    \u_riscv_top.sram0_addr1[2] ,
+    \u_riscv_top.sram0_addr1[1] ,
+    \u_riscv_top.sram0_addr1[0] }),
+    .sram0_din0({\u_riscv_top.sram0_din0[31] ,
+    \u_riscv_top.sram0_din0[30] ,
+    \u_riscv_top.sram0_din0[29] ,
+    \u_riscv_top.sram0_din0[28] ,
+    \u_riscv_top.sram0_din0[27] ,
+    \u_riscv_top.sram0_din0[26] ,
+    \u_riscv_top.sram0_din0[25] ,
+    \u_riscv_top.sram0_din0[24] ,
+    \u_riscv_top.sram0_din0[23] ,
+    \u_riscv_top.sram0_din0[22] ,
+    \u_riscv_top.sram0_din0[21] ,
+    \u_riscv_top.sram0_din0[20] ,
+    \u_riscv_top.sram0_din0[19] ,
+    \u_riscv_top.sram0_din0[18] ,
+    \u_riscv_top.sram0_din0[17] ,
+    \u_riscv_top.sram0_din0[16] ,
+    \u_riscv_top.sram0_din0[15] ,
+    \u_riscv_top.sram0_din0[14] ,
+    \u_riscv_top.sram0_din0[13] ,
+    \u_riscv_top.sram0_din0[12] ,
+    \u_riscv_top.sram0_din0[11] ,
+    \u_riscv_top.sram0_din0[10] ,
+    \u_riscv_top.sram0_din0[9] ,
+    \u_riscv_top.sram0_din0[8] ,
+    \u_riscv_top.sram0_din0[7] ,
+    \u_riscv_top.sram0_din0[6] ,
+    \u_riscv_top.sram0_din0[5] ,
+    \u_riscv_top.sram0_din0[4] ,
+    \u_riscv_top.sram0_din0[3] ,
+    \u_riscv_top.sram0_din0[2] ,
+    \u_riscv_top.sram0_din0[1] ,
+    \u_riscv_top.sram0_din0[0] }),
+    .sram0_dout0({\u_riscv_top.sram0_dout0[31] ,
+    \u_riscv_top.sram0_dout0[30] ,
+    \u_riscv_top.sram0_dout0[29] ,
+    \u_riscv_top.sram0_dout0[28] ,
+    \u_riscv_top.sram0_dout0[27] ,
+    \u_riscv_top.sram0_dout0[26] ,
+    \u_riscv_top.sram0_dout0[25] ,
+    \u_riscv_top.sram0_dout0[24] ,
+    \u_riscv_top.sram0_dout0[23] ,
+    \u_riscv_top.sram0_dout0[22] ,
+    \u_riscv_top.sram0_dout0[21] ,
+    \u_riscv_top.sram0_dout0[20] ,
+    \u_riscv_top.sram0_dout0[19] ,
+    \u_riscv_top.sram0_dout0[18] ,
+    \u_riscv_top.sram0_dout0[17] ,
+    \u_riscv_top.sram0_dout0[16] ,
+    \u_riscv_top.sram0_dout0[15] ,
+    \u_riscv_top.sram0_dout0[14] ,
+    \u_riscv_top.sram0_dout0[13] ,
+    \u_riscv_top.sram0_dout0[12] ,
+    \u_riscv_top.sram0_dout0[11] ,
+    \u_riscv_top.sram0_dout0[10] ,
+    \u_riscv_top.sram0_dout0[9] ,
+    \u_riscv_top.sram0_dout0[8] ,
+    \u_riscv_top.sram0_dout0[7] ,
+    \u_riscv_top.sram0_dout0[6] ,
+    \u_riscv_top.sram0_dout0[5] ,
+    \u_riscv_top.sram0_dout0[4] ,
+    \u_riscv_top.sram0_dout0[3] ,
+    \u_riscv_top.sram0_dout0[2] ,
+    \u_riscv_top.sram0_dout0[1] ,
+    \u_riscv_top.sram0_dout0[0] }),
+    .sram0_dout1({\u_riscv_top.sram0_dout1[31] ,
+    \u_riscv_top.sram0_dout1[30] ,
+    \u_riscv_top.sram0_dout1[29] ,
+    \u_riscv_top.sram0_dout1[28] ,
+    \u_riscv_top.sram0_dout1[27] ,
+    \u_riscv_top.sram0_dout1[26] ,
+    \u_riscv_top.sram0_dout1[25] ,
+    \u_riscv_top.sram0_dout1[24] ,
+    \u_riscv_top.sram0_dout1[23] ,
+    \u_riscv_top.sram0_dout1[22] ,
+    \u_riscv_top.sram0_dout1[21] ,
+    \u_riscv_top.sram0_dout1[20] ,
+    \u_riscv_top.sram0_dout1[19] ,
+    \u_riscv_top.sram0_dout1[18] ,
+    \u_riscv_top.sram0_dout1[17] ,
+    \u_riscv_top.sram0_dout1[16] ,
+    \u_riscv_top.sram0_dout1[15] ,
+    \u_riscv_top.sram0_dout1[14] ,
+    \u_riscv_top.sram0_dout1[13] ,
+    \u_riscv_top.sram0_dout1[12] ,
+    \u_riscv_top.sram0_dout1[11] ,
+    \u_riscv_top.sram0_dout1[10] ,
+    \u_riscv_top.sram0_dout1[9] ,
+    \u_riscv_top.sram0_dout1[8] ,
+    \u_riscv_top.sram0_dout1[7] ,
+    \u_riscv_top.sram0_dout1[6] ,
+    \u_riscv_top.sram0_dout1[5] ,
+    \u_riscv_top.sram0_dout1[4] ,
+    \u_riscv_top.sram0_dout1[3] ,
+    \u_riscv_top.sram0_dout1[2] ,
+    \u_riscv_top.sram0_dout1[1] ,
+    \u_riscv_top.sram0_dout1[0] }),
+    .sram0_wmask0({\u_riscv_top.sram0_wmask0[3] ,
+    \u_riscv_top.sram0_wmask0[2] ,
+    \u_riscv_top.sram0_wmask0[1] ,
+    \u_riscv_top.sram0_wmask0[0] }));
+ ycr_intf \u_riscv_top.u_intf  (.cfg_bypass_dcache(\cfg_riscv_ctrl[11] ),
+    .cfg_bypass_icache(\cfg_riscv_ctrl[10] ),
+    .cfg_dcache_force_flush(\u_riscv_top.cfg_dcache_force_flush ),
+    .cfg_dcache_pfet_dis(\cfg_riscv_ctrl[6] ),
+    .cfg_icache_ntag_pfet_dis(\cfg_riscv_ctrl[5] ),
+    .cfg_icache_pfet_dis(\cfg_riscv_ctrl[4] ),
+    .core_clk(\u_riscv_top.core_clk_intf_skew ),
+    .core_clk_int(\u_riscv_top.core_clk_int[0] ),
+    .core_clk_skew(\u_riscv_top.core_clk_intf_skew ),
+    .core_dcache_cmd(\u_riscv_top.core_dcache_cmd ),
+    .core_dcache_req(\u_riscv_top.core_dcache_req ),
+    .core_dcache_req_ack(\u_riscv_top.core_dcache_req_ack ),
+    .core_dmem_cmd(\u_riscv_top.core_dmem_cmd ),
+    .core_dmem_req(\u_riscv_top.core_dmem_req ),
+    .core_dmem_req_ack(\u_riscv_top.core_dmem_req_ack ),
+    .core_icache_cmd(\u_riscv_top.core_icache_cmd ),
+    .core_icache_req(\u_riscv_top.core_icache_req ),
+    .core_icache_req_ack(\u_riscv_top.core_icache_req_ack ),
+    .cpu_intf_rst_n(\u_riscv_top.cpu_intf_rst_n ),
+    .dcache_mem_clk0(\u_riscv_top.dcache_mem_clk0 ),
+    .dcache_mem_clk1(\u_riscv_top.dcache_mem_clk1 ),
+    .dcache_mem_csb0(\u_riscv_top.dcache_mem_csb0 ),
+    .dcache_mem_csb1(\u_riscv_top.dcache_mem_csb1 ),
+    .dcache_mem_web0(\u_riscv_top.dcache_mem_web0 ),
+    .icache_mem_clk0(\u_riscv_top.icache_mem_clk0 ),
+    .icache_mem_clk1(\u_riscv_top.icache_mem_clk1 ),
+    .icache_mem_csb0(\u_riscv_top.icache_mem_csb0 ),
+    .icache_mem_csb1(\u_riscv_top.icache_mem_csb1 ),
+    .icache_mem_web0(\u_riscv_top.icache_mem_web0 ),
+    .pwrup_rst_n(\u_riscv_top.pwrup_rst_n ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .wb_clk(\u_riscv_top.wb_clk ),
+    .wb_dcache_ack_i(\u_riscv_top.wb_dcache_ack_i ),
+    .wb_dcache_bry_o(\u_riscv_top.wb_dcache_bry_o ),
+    .wb_dcache_cyc_o(\u_riscv_top.wb_dcache_cyc_o ),
+    .wb_dcache_err_i(\u_riscv_top.wb_dcache_err_i ),
+    .wb_dcache_lack_i(\u_riscv_top.wb_dcache_lack_i ),
+    .wb_dcache_stb_o(\u_riscv_top.wb_dcache_stb_o ),
+    .wb_dcache_we_o(\u_riscv_top.wb_dcache_we_o ),
+    .wb_icache_ack_i(\u_riscv_top.wb_icache_ack_i ),
+    .wb_icache_bry_o(\u_riscv_top.wb_icache_bry_o ),
+    .wb_icache_cyc_o(\u_riscv_top.wb_icache_cyc_o ),
+    .wb_icache_err_i(\u_riscv_top.wb_icache_err_i ),
+    .wb_icache_lack_i(\u_riscv_top.wb_icache_lack_i ),
+    .wb_icache_stb_o(\u_riscv_top.wb_icache_stb_o ),
+    .wb_icache_we_o(\u_riscv_top.wb_icache_we_o ),
+    .wb_rst_n(\u_riscv_top.pwrup_rst_n ),
+    .wbd_clk_int(\u_riscv_top.wbd_clk_int ),
+    .wbd_clk_skew(\u_riscv_top.wb_clk ),
+    .wbd_dmem_ack_i(\u_riscv_top.wbd_dmem_ack_i ),
+    .wbd_dmem_bry_o(\u_riscv_top.wbd_dmem_bry_o ),
+    .wbd_dmem_err_i(\u_riscv_top.wbd_dmem_err_i ),
+    .wbd_dmem_lack_i(\u_riscv_top.wbd_dmem_lack_i ),
+    .wbd_dmem_stb_o(\u_riscv_top.wbd_dmem_stb_o ),
+    .wbd_dmem_we_o(\u_riscv_top.wbd_dmem_we_o ),
+    .cfg_ccska({\u_riscv_top.cfg_ccska_riscv_intf[3] ,
+    \u_riscv_top.cfg_ccska_riscv_intf[2] ,
+    \u_riscv_top.cfg_ccska_riscv_intf[1] ,
+    \u_riscv_top.cfg_ccska_riscv_intf[0] }),
+    .cfg_sram_lphase({\cfg_riscv_ctrl[1] ,
+    \cfg_riscv_ctrl[0] }),
+    .cfg_wcska({\u_riscv_top.cfg_wcska_riscv_intf[3] ,
+    \u_riscv_top.cfg_wcska_riscv_intf[2] ,
+    \u_riscv_top.cfg_wcska_riscv_intf[1] ,
+    \u_riscv_top.cfg_wcska_riscv_intf[0] }),
+    .core_dcache_addr({\u_riscv_top.core_dcache_addr[31] ,
+    \u_riscv_top.core_dcache_addr[30] ,
+    \u_riscv_top.core_dcache_addr[29] ,
+    \u_riscv_top.core_dcache_addr[28] ,
+    \u_riscv_top.core_dcache_addr[27] ,
+    \u_riscv_top.core_dcache_addr[26] ,
+    \u_riscv_top.core_dcache_addr[25] ,
+    \u_riscv_top.core_dcache_addr[24] ,
+    \u_riscv_top.core_dcache_addr[23] ,
+    \u_riscv_top.core_dcache_addr[22] ,
+    \u_riscv_top.core_dcache_addr[21] ,
+    \u_riscv_top.core_dcache_addr[20] ,
+    \u_riscv_top.core_dcache_addr[19] ,
+    \u_riscv_top.core_dcache_addr[18] ,
+    \u_riscv_top.core_dcache_addr[17] ,
+    \u_riscv_top.core_dcache_addr[16] ,
+    \u_riscv_top.core_dcache_addr[15] ,
+    \u_riscv_top.core_dcache_addr[14] ,
+    \u_riscv_top.core_dcache_addr[13] ,
+    \u_riscv_top.core_dcache_addr[12] ,
+    \u_riscv_top.core_dcache_addr[11] ,
+    \u_riscv_top.core_dcache_addr[10] ,
+    \u_riscv_top.core_dcache_addr[9] ,
+    \u_riscv_top.core_dcache_addr[8] ,
+    \u_riscv_top.core_dcache_addr[7] ,
+    \u_riscv_top.core_dcache_addr[6] ,
+    \u_riscv_top.core_dcache_addr[5] ,
+    \u_riscv_top.core_dcache_addr[4] ,
+    \u_riscv_top.core_dcache_addr[3] ,
+    \u_riscv_top.core_dcache_addr[2] ,
+    \u_riscv_top.core_dcache_addr[1] ,
+    \u_riscv_top.core_dcache_addr[0] }),
+    .core_dcache_rdata({\u_riscv_top.core_dcache_rdata[31] ,
+    \u_riscv_top.core_dcache_rdata[30] ,
+    \u_riscv_top.core_dcache_rdata[29] ,
+    \u_riscv_top.core_dcache_rdata[28] ,
+    \u_riscv_top.core_dcache_rdata[27] ,
+    \u_riscv_top.core_dcache_rdata[26] ,
+    \u_riscv_top.core_dcache_rdata[25] ,
+    \u_riscv_top.core_dcache_rdata[24] ,
+    \u_riscv_top.core_dcache_rdata[23] ,
+    \u_riscv_top.core_dcache_rdata[22] ,
+    \u_riscv_top.core_dcache_rdata[21] ,
+    \u_riscv_top.core_dcache_rdata[20] ,
+    \u_riscv_top.core_dcache_rdata[19] ,
+    \u_riscv_top.core_dcache_rdata[18] ,
+    \u_riscv_top.core_dcache_rdata[17] ,
+    \u_riscv_top.core_dcache_rdata[16] ,
+    \u_riscv_top.core_dcache_rdata[15] ,
+    \u_riscv_top.core_dcache_rdata[14] ,
+    \u_riscv_top.core_dcache_rdata[13] ,
+    \u_riscv_top.core_dcache_rdata[12] ,
+    \u_riscv_top.core_dcache_rdata[11] ,
+    \u_riscv_top.core_dcache_rdata[10] ,
+    \u_riscv_top.core_dcache_rdata[9] ,
+    \u_riscv_top.core_dcache_rdata[8] ,
+    \u_riscv_top.core_dcache_rdata[7] ,
+    \u_riscv_top.core_dcache_rdata[6] ,
+    \u_riscv_top.core_dcache_rdata[5] ,
+    \u_riscv_top.core_dcache_rdata[4] ,
+    \u_riscv_top.core_dcache_rdata[3] ,
+    \u_riscv_top.core_dcache_rdata[2] ,
+    \u_riscv_top.core_dcache_rdata[1] ,
+    \u_riscv_top.core_dcache_rdata[0] }),
+    .core_dcache_resp({\u_riscv_top.core_dcache_resp[1] ,
+    \u_riscv_top.core_dcache_resp[0] }),
+    .core_dcache_wdata({\u_riscv_top.core_dcache_wdata[31] ,
+    \u_riscv_top.core_dcache_wdata[30] ,
+    \u_riscv_top.core_dcache_wdata[29] ,
+    \u_riscv_top.core_dcache_wdata[28] ,
+    \u_riscv_top.core_dcache_wdata[27] ,
+    \u_riscv_top.core_dcache_wdata[26] ,
+    \u_riscv_top.core_dcache_wdata[25] ,
+    \u_riscv_top.core_dcache_wdata[24] ,
+    \u_riscv_top.core_dcache_wdata[23] ,
+    \u_riscv_top.core_dcache_wdata[22] ,
+    \u_riscv_top.core_dcache_wdata[21] ,
+    \u_riscv_top.core_dcache_wdata[20] ,
+    \u_riscv_top.core_dcache_wdata[19] ,
+    \u_riscv_top.core_dcache_wdata[18] ,
+    \u_riscv_top.core_dcache_wdata[17] ,
+    \u_riscv_top.core_dcache_wdata[16] ,
+    \u_riscv_top.core_dcache_wdata[15] ,
+    \u_riscv_top.core_dcache_wdata[14] ,
+    \u_riscv_top.core_dcache_wdata[13] ,
+    \u_riscv_top.core_dcache_wdata[12] ,
+    \u_riscv_top.core_dcache_wdata[11] ,
+    \u_riscv_top.core_dcache_wdata[10] ,
+    \u_riscv_top.core_dcache_wdata[9] ,
+    \u_riscv_top.core_dcache_wdata[8] ,
+    \u_riscv_top.core_dcache_wdata[7] ,
+    \u_riscv_top.core_dcache_wdata[6] ,
+    \u_riscv_top.core_dcache_wdata[5] ,
+    \u_riscv_top.core_dcache_wdata[4] ,
+    \u_riscv_top.core_dcache_wdata[3] ,
+    \u_riscv_top.core_dcache_wdata[2] ,
+    \u_riscv_top.core_dcache_wdata[1] ,
+    \u_riscv_top.core_dcache_wdata[0] }),
+    .core_dcache_width({\u_riscv_top.core_dcache_width[1] ,
+    \u_riscv_top.core_dcache_width[0] }),
+    .core_dmem_addr({\u_riscv_top.core_dmem_addr[31] ,
+    \u_riscv_top.core_dmem_addr[30] ,
+    \u_riscv_top.core_dmem_addr[29] ,
+    \u_riscv_top.core_dmem_addr[28] ,
+    \u_riscv_top.core_dmem_addr[27] ,
+    \u_riscv_top.core_dmem_addr[26] ,
+    \u_riscv_top.core_dmem_addr[25] ,
+    \u_riscv_top.core_dmem_addr[24] ,
+    \u_riscv_top.core_dmem_addr[23] ,
+    \u_riscv_top.core_dmem_addr[22] ,
+    \u_riscv_top.core_dmem_addr[21] ,
+    \u_riscv_top.core_dmem_addr[20] ,
+    \u_riscv_top.core_dmem_addr[19] ,
+    \u_riscv_top.core_dmem_addr[18] ,
+    \u_riscv_top.core_dmem_addr[17] ,
+    \u_riscv_top.core_dmem_addr[16] ,
+    \u_riscv_top.core_dmem_addr[15] ,
+    \u_riscv_top.core_dmem_addr[14] ,
+    \u_riscv_top.core_dmem_addr[13] ,
+    \u_riscv_top.core_dmem_addr[12] ,
+    \u_riscv_top.core_dmem_addr[11] ,
+    \u_riscv_top.core_dmem_addr[10] ,
+    \u_riscv_top.core_dmem_addr[9] ,
+    \u_riscv_top.core_dmem_addr[8] ,
+    \u_riscv_top.core_dmem_addr[7] ,
+    \u_riscv_top.core_dmem_addr[6] ,
+    \u_riscv_top.core_dmem_addr[5] ,
+    \u_riscv_top.core_dmem_addr[4] ,
+    \u_riscv_top.core_dmem_addr[3] ,
+    \u_riscv_top.core_dmem_addr[2] ,
+    \u_riscv_top.core_dmem_addr[1] ,
+    \u_riscv_top.core_dmem_addr[0] }),
+    .core_dmem_bl({\u_riscv_top.core_dmem_bl[2] ,
+    \u_riscv_top.core_dmem_bl[1] ,
+    \u_riscv_top.core_dmem_bl[0] }),
+    .core_dmem_rdata({\u_riscv_top.core_dmem_rdata[31] ,
+    \u_riscv_top.core_dmem_rdata[30] ,
+    \u_riscv_top.core_dmem_rdata[29] ,
+    \u_riscv_top.core_dmem_rdata[28] ,
+    \u_riscv_top.core_dmem_rdata[27] ,
+    \u_riscv_top.core_dmem_rdata[26] ,
+    \u_riscv_top.core_dmem_rdata[25] ,
+    \u_riscv_top.core_dmem_rdata[24] ,
+    \u_riscv_top.core_dmem_rdata[23] ,
+    \u_riscv_top.core_dmem_rdata[22] ,
+    \u_riscv_top.core_dmem_rdata[21] ,
+    \u_riscv_top.core_dmem_rdata[20] ,
+    \u_riscv_top.core_dmem_rdata[19] ,
+    \u_riscv_top.core_dmem_rdata[18] ,
+    \u_riscv_top.core_dmem_rdata[17] ,
+    \u_riscv_top.core_dmem_rdata[16] ,
+    \u_riscv_top.core_dmem_rdata[15] ,
+    \u_riscv_top.core_dmem_rdata[14] ,
+    \u_riscv_top.core_dmem_rdata[13] ,
+    \u_riscv_top.core_dmem_rdata[12] ,
+    \u_riscv_top.core_dmem_rdata[11] ,
+    \u_riscv_top.core_dmem_rdata[10] ,
+    \u_riscv_top.core_dmem_rdata[9] ,
+    \u_riscv_top.core_dmem_rdata[8] ,
+    \u_riscv_top.core_dmem_rdata[7] ,
+    \u_riscv_top.core_dmem_rdata[6] ,
+    \u_riscv_top.core_dmem_rdata[5] ,
+    \u_riscv_top.core_dmem_rdata[4] ,
+    \u_riscv_top.core_dmem_rdata[3] ,
+    \u_riscv_top.core_dmem_rdata[2] ,
+    \u_riscv_top.core_dmem_rdata[1] ,
+    \u_riscv_top.core_dmem_rdata[0] }),
+    .core_dmem_resp({\u_riscv_top.core_dmem_resp[1] ,
+    \u_riscv_top.core_dmem_resp[0] }),
+    .core_dmem_wdata({\u_riscv_top.core_dmem_wdata[31] ,
+    \u_riscv_top.core_dmem_wdata[30] ,
+    \u_riscv_top.core_dmem_wdata[29] ,
+    \u_riscv_top.core_dmem_wdata[28] ,
+    \u_riscv_top.core_dmem_wdata[27] ,
+    \u_riscv_top.core_dmem_wdata[26] ,
+    \u_riscv_top.core_dmem_wdata[25] ,
+    \u_riscv_top.core_dmem_wdata[24] ,
+    \u_riscv_top.core_dmem_wdata[23] ,
+    \u_riscv_top.core_dmem_wdata[22] ,
+    \u_riscv_top.core_dmem_wdata[21] ,
+    \u_riscv_top.core_dmem_wdata[20] ,
+    \u_riscv_top.core_dmem_wdata[19] ,
+    \u_riscv_top.core_dmem_wdata[18] ,
+    \u_riscv_top.core_dmem_wdata[17] ,
+    \u_riscv_top.core_dmem_wdata[16] ,
+    \u_riscv_top.core_dmem_wdata[15] ,
+    \u_riscv_top.core_dmem_wdata[14] ,
+    \u_riscv_top.core_dmem_wdata[13] ,
+    \u_riscv_top.core_dmem_wdata[12] ,
+    \u_riscv_top.core_dmem_wdata[11] ,
+    \u_riscv_top.core_dmem_wdata[10] ,
+    \u_riscv_top.core_dmem_wdata[9] ,
+    \u_riscv_top.core_dmem_wdata[8] ,
+    \u_riscv_top.core_dmem_wdata[7] ,
+    \u_riscv_top.core_dmem_wdata[6] ,
+    \u_riscv_top.core_dmem_wdata[5] ,
+    \u_riscv_top.core_dmem_wdata[4] ,
+    \u_riscv_top.core_dmem_wdata[3] ,
+    \u_riscv_top.core_dmem_wdata[2] ,
+    \u_riscv_top.core_dmem_wdata[1] ,
+    \u_riscv_top.core_dmem_wdata[0] }),
+    .core_dmem_width({\u_riscv_top.core_dmem_width[1] ,
+    \u_riscv_top.core_dmem_width[0] }),
+    .core_icache_addr({\u_riscv_top.core_icache_addr[31] ,
+    \u_riscv_top.core_icache_addr[30] ,
+    \u_riscv_top.core_icache_addr[29] ,
+    \u_riscv_top.core_icache_addr[28] ,
+    \u_riscv_top.core_icache_addr[27] ,
+    \u_riscv_top.core_icache_addr[26] ,
+    \u_riscv_top.core_icache_addr[25] ,
+    \u_riscv_top.core_icache_addr[24] ,
+    \u_riscv_top.core_icache_addr[23] ,
+    \u_riscv_top.core_icache_addr[22] ,
+    \u_riscv_top.core_icache_addr[21] ,
+    \u_riscv_top.core_icache_addr[20] ,
+    \u_riscv_top.core_icache_addr[19] ,
+    \u_riscv_top.core_icache_addr[18] ,
+    \u_riscv_top.core_icache_addr[17] ,
+    \u_riscv_top.core_icache_addr[16] ,
+    \u_riscv_top.core_icache_addr[15] ,
+    \u_riscv_top.core_icache_addr[14] ,
+    \u_riscv_top.core_icache_addr[13] ,
+    \u_riscv_top.core_icache_addr[12] ,
+    \u_riscv_top.core_icache_addr[11] ,
+    \u_riscv_top.core_icache_addr[10] ,
+    \u_riscv_top.core_icache_addr[9] ,
+    \u_riscv_top.core_icache_addr[8] ,
+    \u_riscv_top.core_icache_addr[7] ,
+    \u_riscv_top.core_icache_addr[6] ,
+    \u_riscv_top.core_icache_addr[5] ,
+    \u_riscv_top.core_icache_addr[4] ,
+    \u_riscv_top.core_icache_addr[3] ,
+    \u_riscv_top.core_icache_addr[2] ,
+    \u_riscv_top.core_icache_addr[1] ,
+    \u_riscv_top.core_icache_addr[0] }),
+    .core_icache_bl({\u_riscv_top.core_icache_bl[2] ,
+    \u_riscv_top.core_icache_bl[1] ,
+    \u_riscv_top.core_icache_bl[0] }),
+    .core_icache_rdata({\u_riscv_top.core_icache_rdata[31] ,
+    \u_riscv_top.core_icache_rdata[30] ,
+    \u_riscv_top.core_icache_rdata[29] ,
+    \u_riscv_top.core_icache_rdata[28] ,
+    \u_riscv_top.core_icache_rdata[27] ,
+    \u_riscv_top.core_icache_rdata[26] ,
+    \u_riscv_top.core_icache_rdata[25] ,
+    \u_riscv_top.core_icache_rdata[24] ,
+    \u_riscv_top.core_icache_rdata[23] ,
+    \u_riscv_top.core_icache_rdata[22] ,
+    \u_riscv_top.core_icache_rdata[21] ,
+    \u_riscv_top.core_icache_rdata[20] ,
+    \u_riscv_top.core_icache_rdata[19] ,
+    \u_riscv_top.core_icache_rdata[18] ,
+    \u_riscv_top.core_icache_rdata[17] ,
+    \u_riscv_top.core_icache_rdata[16] ,
+    \u_riscv_top.core_icache_rdata[15] ,
+    \u_riscv_top.core_icache_rdata[14] ,
+    \u_riscv_top.core_icache_rdata[13] ,
+    \u_riscv_top.core_icache_rdata[12] ,
+    \u_riscv_top.core_icache_rdata[11] ,
+    \u_riscv_top.core_icache_rdata[10] ,
+    \u_riscv_top.core_icache_rdata[9] ,
+    \u_riscv_top.core_icache_rdata[8] ,
+    \u_riscv_top.core_icache_rdata[7] ,
+    \u_riscv_top.core_icache_rdata[6] ,
+    \u_riscv_top.core_icache_rdata[5] ,
+    \u_riscv_top.core_icache_rdata[4] ,
+    \u_riscv_top.core_icache_rdata[3] ,
+    \u_riscv_top.core_icache_rdata[2] ,
+    \u_riscv_top.core_icache_rdata[1] ,
+    \u_riscv_top.core_icache_rdata[0] }),
+    .core_icache_resp({\u_riscv_top.core_icache_resp[1] ,
+    \u_riscv_top.core_icache_resp[0] }),
+    .core_icache_width({\u_riscv_top.core_icache_width[1] ,
+    \u_riscv_top.core_icache_width[0] }),
+    .dcache_mem_addr0({\u_riscv_top.dcache_mem_addr0[8] ,
+    \u_riscv_top.dcache_mem_addr0[7] ,
+    \u_riscv_top.dcache_mem_addr0[6] ,
+    \u_riscv_top.dcache_mem_addr0[5] ,
+    \u_riscv_top.dcache_mem_addr0[4] ,
+    \u_riscv_top.dcache_mem_addr0[3] ,
+    \u_riscv_top.dcache_mem_addr0[2] ,
+    \u_riscv_top.dcache_mem_addr0[1] ,
+    \u_riscv_top.dcache_mem_addr0[0] }),
+    .dcache_mem_addr1({\u_riscv_top.dcache_mem_addr1[8] ,
+    \u_riscv_top.dcache_mem_addr1[7] ,
+    \u_riscv_top.dcache_mem_addr1[6] ,
+    \u_riscv_top.dcache_mem_addr1[5] ,
+    \u_riscv_top.dcache_mem_addr1[4] ,
+    \u_riscv_top.dcache_mem_addr1[3] ,
+    \u_riscv_top.dcache_mem_addr1[2] ,
+    \u_riscv_top.dcache_mem_addr1[1] ,
+    \u_riscv_top.dcache_mem_addr1[0] }),
+    .dcache_mem_din0({\u_riscv_top.dcache_mem_din0[31] ,
+    \u_riscv_top.dcache_mem_din0[30] ,
+    \u_riscv_top.dcache_mem_din0[29] ,
+    \u_riscv_top.dcache_mem_din0[28] ,
+    \u_riscv_top.dcache_mem_din0[27] ,
+    \u_riscv_top.dcache_mem_din0[26] ,
+    \u_riscv_top.dcache_mem_din0[25] ,
+    \u_riscv_top.dcache_mem_din0[24] ,
+    \u_riscv_top.dcache_mem_din0[23] ,
+    \u_riscv_top.dcache_mem_din0[22] ,
+    \u_riscv_top.dcache_mem_din0[21] ,
+    \u_riscv_top.dcache_mem_din0[20] ,
+    \u_riscv_top.dcache_mem_din0[19] ,
+    \u_riscv_top.dcache_mem_din0[18] ,
+    \u_riscv_top.dcache_mem_din0[17] ,
+    \u_riscv_top.dcache_mem_din0[16] ,
+    \u_riscv_top.dcache_mem_din0[15] ,
+    \u_riscv_top.dcache_mem_din0[14] ,
+    \u_riscv_top.dcache_mem_din0[13] ,
+    \u_riscv_top.dcache_mem_din0[12] ,
+    \u_riscv_top.dcache_mem_din0[11] ,
+    \u_riscv_top.dcache_mem_din0[10] ,
+    \u_riscv_top.dcache_mem_din0[9] ,
+    \u_riscv_top.dcache_mem_din0[8] ,
+    \u_riscv_top.dcache_mem_din0[7] ,
+    \u_riscv_top.dcache_mem_din0[6] ,
+    \u_riscv_top.dcache_mem_din0[5] ,
+    \u_riscv_top.dcache_mem_din0[4] ,
+    \u_riscv_top.dcache_mem_din0[3] ,
+    \u_riscv_top.dcache_mem_din0[2] ,
+    \u_riscv_top.dcache_mem_din0[1] ,
+    \u_riscv_top.dcache_mem_din0[0] }),
+    .dcache_mem_dout0({\u_riscv_top.dcache_mem_dout0[31] ,
+    \u_riscv_top.dcache_mem_dout0[30] ,
+    \u_riscv_top.dcache_mem_dout0[29] ,
+    \u_riscv_top.dcache_mem_dout0[28] ,
+    \u_riscv_top.dcache_mem_dout0[27] ,
+    \u_riscv_top.dcache_mem_dout0[26] ,
+    \u_riscv_top.dcache_mem_dout0[25] ,
+    \u_riscv_top.dcache_mem_dout0[24] ,
+    \u_riscv_top.dcache_mem_dout0[23] ,
+    \u_riscv_top.dcache_mem_dout0[22] ,
+    \u_riscv_top.dcache_mem_dout0[21] ,
+    \u_riscv_top.dcache_mem_dout0[20] ,
+    \u_riscv_top.dcache_mem_dout0[19] ,
+    \u_riscv_top.dcache_mem_dout0[18] ,
+    \u_riscv_top.dcache_mem_dout0[17] ,
+    \u_riscv_top.dcache_mem_dout0[16] ,
+    \u_riscv_top.dcache_mem_dout0[15] ,
+    \u_riscv_top.dcache_mem_dout0[14] ,
+    \u_riscv_top.dcache_mem_dout0[13] ,
+    \u_riscv_top.dcache_mem_dout0[12] ,
+    \u_riscv_top.dcache_mem_dout0[11] ,
+    \u_riscv_top.dcache_mem_dout0[10] ,
+    \u_riscv_top.dcache_mem_dout0[9] ,
+    \u_riscv_top.dcache_mem_dout0[8] ,
+    \u_riscv_top.dcache_mem_dout0[7] ,
+    \u_riscv_top.dcache_mem_dout0[6] ,
+    \u_riscv_top.dcache_mem_dout0[5] ,
+    \u_riscv_top.dcache_mem_dout0[4] ,
+    \u_riscv_top.dcache_mem_dout0[3] ,
+    \u_riscv_top.dcache_mem_dout0[2] ,
+    \u_riscv_top.dcache_mem_dout0[1] ,
+    \u_riscv_top.dcache_mem_dout0[0] }),
+    .dcache_mem_dout1({\u_riscv_top.dcache_mem_dout1[31] ,
+    \u_riscv_top.dcache_mem_dout1[30] ,
+    \u_riscv_top.dcache_mem_dout1[29] ,
+    \u_riscv_top.dcache_mem_dout1[28] ,
+    \u_riscv_top.dcache_mem_dout1[27] ,
+    \u_riscv_top.dcache_mem_dout1[26] ,
+    \u_riscv_top.dcache_mem_dout1[25] ,
+    \u_riscv_top.dcache_mem_dout1[24] ,
+    \u_riscv_top.dcache_mem_dout1[23] ,
+    \u_riscv_top.dcache_mem_dout1[22] ,
+    \u_riscv_top.dcache_mem_dout1[21] ,
+    \u_riscv_top.dcache_mem_dout1[20] ,
+    \u_riscv_top.dcache_mem_dout1[19] ,
+    \u_riscv_top.dcache_mem_dout1[18] ,
+    \u_riscv_top.dcache_mem_dout1[17] ,
+    \u_riscv_top.dcache_mem_dout1[16] ,
+    \u_riscv_top.dcache_mem_dout1[15] ,
+    \u_riscv_top.dcache_mem_dout1[14] ,
+    \u_riscv_top.dcache_mem_dout1[13] ,
+    \u_riscv_top.dcache_mem_dout1[12] ,
+    \u_riscv_top.dcache_mem_dout1[11] ,
+    \u_riscv_top.dcache_mem_dout1[10] ,
+    \u_riscv_top.dcache_mem_dout1[9] ,
+    \u_riscv_top.dcache_mem_dout1[8] ,
+    \u_riscv_top.dcache_mem_dout1[7] ,
+    \u_riscv_top.dcache_mem_dout1[6] ,
+    \u_riscv_top.dcache_mem_dout1[5] ,
+    \u_riscv_top.dcache_mem_dout1[4] ,
+    \u_riscv_top.dcache_mem_dout1[3] ,
+    \u_riscv_top.dcache_mem_dout1[2] ,
+    \u_riscv_top.dcache_mem_dout1[1] ,
+    \u_riscv_top.dcache_mem_dout1[0] }),
+    .dcache_mem_wmask0({\u_riscv_top.dcache_mem_wmask0[3] ,
+    \u_riscv_top.dcache_mem_wmask0[2] ,
+    \u_riscv_top.dcache_mem_wmask0[1] ,
+    \u_riscv_top.dcache_mem_wmask0[0] }),
+    .icache_mem_addr0({\u_riscv_top.icache_mem_addr0[8] ,
+    \u_riscv_top.icache_mem_addr0[7] ,
+    \u_riscv_top.icache_mem_addr0[6] ,
+    \u_riscv_top.icache_mem_addr0[5] ,
+    \u_riscv_top.icache_mem_addr0[4] ,
+    \u_riscv_top.icache_mem_addr0[3] ,
+    \u_riscv_top.icache_mem_addr0[2] ,
+    \u_riscv_top.icache_mem_addr0[1] ,
+    \u_riscv_top.icache_mem_addr0[0] }),
+    .icache_mem_addr1({\u_riscv_top.icache_mem_addr1[8] ,
+    \u_riscv_top.icache_mem_addr1[7] ,
+    \u_riscv_top.icache_mem_addr1[6] ,
+    \u_riscv_top.icache_mem_addr1[5] ,
+    \u_riscv_top.icache_mem_addr1[4] ,
+    \u_riscv_top.icache_mem_addr1[3] ,
+    \u_riscv_top.icache_mem_addr1[2] ,
+    \u_riscv_top.icache_mem_addr1[1] ,
+    \u_riscv_top.icache_mem_addr1[0] }),
+    .icache_mem_din0({\u_riscv_top.icache_mem_din0[31] ,
+    \u_riscv_top.icache_mem_din0[30] ,
+    \u_riscv_top.icache_mem_din0[29] ,
+    \u_riscv_top.icache_mem_din0[28] ,
+    \u_riscv_top.icache_mem_din0[27] ,
+    \u_riscv_top.icache_mem_din0[26] ,
+    \u_riscv_top.icache_mem_din0[25] ,
+    \u_riscv_top.icache_mem_din0[24] ,
+    \u_riscv_top.icache_mem_din0[23] ,
+    \u_riscv_top.icache_mem_din0[22] ,
+    \u_riscv_top.icache_mem_din0[21] ,
+    \u_riscv_top.icache_mem_din0[20] ,
+    \u_riscv_top.icache_mem_din0[19] ,
+    \u_riscv_top.icache_mem_din0[18] ,
+    \u_riscv_top.icache_mem_din0[17] ,
+    \u_riscv_top.icache_mem_din0[16] ,
+    \u_riscv_top.icache_mem_din0[15] ,
+    \u_riscv_top.icache_mem_din0[14] ,
+    \u_riscv_top.icache_mem_din0[13] ,
+    \u_riscv_top.icache_mem_din0[12] ,
+    \u_riscv_top.icache_mem_din0[11] ,
+    \u_riscv_top.icache_mem_din0[10] ,
+    \u_riscv_top.icache_mem_din0[9] ,
+    \u_riscv_top.icache_mem_din0[8] ,
+    \u_riscv_top.icache_mem_din0[7] ,
+    \u_riscv_top.icache_mem_din0[6] ,
+    \u_riscv_top.icache_mem_din0[5] ,
+    \u_riscv_top.icache_mem_din0[4] ,
+    \u_riscv_top.icache_mem_din0[3] ,
+    \u_riscv_top.icache_mem_din0[2] ,
+    \u_riscv_top.icache_mem_din0[1] ,
+    \u_riscv_top.icache_mem_din0[0] }),
+    .icache_mem_dout1({\u_riscv_top.icache_mem_dout1[31] ,
+    \u_riscv_top.icache_mem_dout1[30] ,
+    \u_riscv_top.icache_mem_dout1[29] ,
+    \u_riscv_top.icache_mem_dout1[28] ,
+    \u_riscv_top.icache_mem_dout1[27] ,
+    \u_riscv_top.icache_mem_dout1[26] ,
+    \u_riscv_top.icache_mem_dout1[25] ,
+    \u_riscv_top.icache_mem_dout1[24] ,
+    \u_riscv_top.icache_mem_dout1[23] ,
+    \u_riscv_top.icache_mem_dout1[22] ,
+    \u_riscv_top.icache_mem_dout1[21] ,
+    \u_riscv_top.icache_mem_dout1[20] ,
+    \u_riscv_top.icache_mem_dout1[19] ,
+    \u_riscv_top.icache_mem_dout1[18] ,
+    \u_riscv_top.icache_mem_dout1[17] ,
+    \u_riscv_top.icache_mem_dout1[16] ,
+    \u_riscv_top.icache_mem_dout1[15] ,
+    \u_riscv_top.icache_mem_dout1[14] ,
+    \u_riscv_top.icache_mem_dout1[13] ,
+    \u_riscv_top.icache_mem_dout1[12] ,
+    \u_riscv_top.icache_mem_dout1[11] ,
+    \u_riscv_top.icache_mem_dout1[10] ,
+    \u_riscv_top.icache_mem_dout1[9] ,
+    \u_riscv_top.icache_mem_dout1[8] ,
+    \u_riscv_top.icache_mem_dout1[7] ,
+    \u_riscv_top.icache_mem_dout1[6] ,
+    \u_riscv_top.icache_mem_dout1[5] ,
+    \u_riscv_top.icache_mem_dout1[4] ,
+    \u_riscv_top.icache_mem_dout1[3] ,
+    \u_riscv_top.icache_mem_dout1[2] ,
+    \u_riscv_top.icache_mem_dout1[1] ,
+    \u_riscv_top.icache_mem_dout1[0] }),
+    .icache_mem_wmask0({\u_riscv_top.icache_mem_wmask0[3] ,
+    \u_riscv_top.icache_mem_wmask0[2] ,
+    \u_riscv_top.icache_mem_wmask0[1] ,
+    \u_riscv_top.icache_mem_wmask0[0] }),
+    .wb_dcache_adr_o({\u_riscv_top.wb_dcache_adr_o[31] ,
+    \u_riscv_top.wb_dcache_adr_o[30] ,
+    \u_riscv_top.wb_dcache_adr_o[29] ,
+    \u_riscv_top.wb_dcache_adr_o[28] ,
+    \u_riscv_top.wb_dcache_adr_o[27] ,
+    \u_riscv_top.wb_dcache_adr_o[26] ,
+    \u_riscv_top.wb_dcache_adr_o[25] ,
+    \u_riscv_top.wb_dcache_adr_o[24] ,
+    \u_riscv_top.wb_dcache_adr_o[23] ,
+    \u_riscv_top.wb_dcache_adr_o[22] ,
+    \u_riscv_top.wb_dcache_adr_o[21] ,
+    \u_riscv_top.wb_dcache_adr_o[20] ,
+    \u_riscv_top.wb_dcache_adr_o[19] ,
+    \u_riscv_top.wb_dcache_adr_o[18] ,
+    \u_riscv_top.wb_dcache_adr_o[17] ,
+    \u_riscv_top.wb_dcache_adr_o[16] ,
+    \u_riscv_top.wb_dcache_adr_o[15] ,
+    \u_riscv_top.wb_dcache_adr_o[14] ,
+    \u_riscv_top.wb_dcache_adr_o[13] ,
+    \u_riscv_top.wb_dcache_adr_o[12] ,
+    \u_riscv_top.wb_dcache_adr_o[11] ,
+    \u_riscv_top.wb_dcache_adr_o[10] ,
+    \u_riscv_top.wb_dcache_adr_o[9] ,
+    \u_riscv_top.wb_dcache_adr_o[8] ,
+    \u_riscv_top.wb_dcache_adr_o[7] ,
+    \u_riscv_top.wb_dcache_adr_o[6] ,
+    \u_riscv_top.wb_dcache_adr_o[5] ,
+    \u_riscv_top.wb_dcache_adr_o[4] ,
+    \u_riscv_top.wb_dcache_adr_o[3] ,
+    \u_riscv_top.wb_dcache_adr_o[2] ,
+    \u_riscv_top.wb_dcache_adr_o[1] ,
+    \u_riscv_top.wb_dcache_adr_o[0] }),
+    .wb_dcache_bl_o({\u_riscv_top.wb_dcache_bl_o[9] ,
+    \u_riscv_top.wb_dcache_bl_o[8] ,
+    \u_riscv_top.wb_dcache_bl_o[7] ,
+    \u_riscv_top.wb_dcache_bl_o[6] ,
+    \u_riscv_top.wb_dcache_bl_o[5] ,
+    \u_riscv_top.wb_dcache_bl_o[4] ,
+    \u_riscv_top.wb_dcache_bl_o[3] ,
+    \u_riscv_top.wb_dcache_bl_o[2] ,
+    \u_riscv_top.wb_dcache_bl_o[1] ,
+    \u_riscv_top.wb_dcache_bl_o[0] }),
+    .wb_dcache_dat_i({\u_riscv_top.wb_dcache_dat_i[31] ,
+    \u_riscv_top.wb_dcache_dat_i[30] ,
+    \u_riscv_top.wb_dcache_dat_i[29] ,
+    \u_riscv_top.wb_dcache_dat_i[28] ,
+    \u_riscv_top.wb_dcache_dat_i[27] ,
+    \u_riscv_top.wb_dcache_dat_i[26] ,
+    \u_riscv_top.wb_dcache_dat_i[25] ,
+    \u_riscv_top.wb_dcache_dat_i[24] ,
+    \u_riscv_top.wb_dcache_dat_i[23] ,
+    \u_riscv_top.wb_dcache_dat_i[22] ,
+    \u_riscv_top.wb_dcache_dat_i[21] ,
+    \u_riscv_top.wb_dcache_dat_i[20] ,
+    \u_riscv_top.wb_dcache_dat_i[19] ,
+    \u_riscv_top.wb_dcache_dat_i[18] ,
+    \u_riscv_top.wb_dcache_dat_i[17] ,
+    \u_riscv_top.wb_dcache_dat_i[16] ,
+    \u_riscv_top.wb_dcache_dat_i[15] ,
+    \u_riscv_top.wb_dcache_dat_i[14] ,
+    \u_riscv_top.wb_dcache_dat_i[13] ,
+    \u_riscv_top.wb_dcache_dat_i[12] ,
+    \u_riscv_top.wb_dcache_dat_i[11] ,
+    \u_riscv_top.wb_dcache_dat_i[10] ,
+    \u_riscv_top.wb_dcache_dat_i[9] ,
+    \u_riscv_top.wb_dcache_dat_i[8] ,
+    \u_riscv_top.wb_dcache_dat_i[7] ,
+    \u_riscv_top.wb_dcache_dat_i[6] ,
+    \u_riscv_top.wb_dcache_dat_i[5] ,
+    \u_riscv_top.wb_dcache_dat_i[4] ,
+    \u_riscv_top.wb_dcache_dat_i[3] ,
+    \u_riscv_top.wb_dcache_dat_i[2] ,
+    \u_riscv_top.wb_dcache_dat_i[1] ,
+    \u_riscv_top.wb_dcache_dat_i[0] }),
+    .wb_dcache_dat_o({\u_riscv_top.wb_dcache_dat_o[31] ,
+    \u_riscv_top.wb_dcache_dat_o[30] ,
+    \u_riscv_top.wb_dcache_dat_o[29] ,
+    \u_riscv_top.wb_dcache_dat_o[28] ,
+    \u_riscv_top.wb_dcache_dat_o[27] ,
+    \u_riscv_top.wb_dcache_dat_o[26] ,
+    \u_riscv_top.wb_dcache_dat_o[25] ,
+    \u_riscv_top.wb_dcache_dat_o[24] ,
+    \u_riscv_top.wb_dcache_dat_o[23] ,
+    \u_riscv_top.wb_dcache_dat_o[22] ,
+    \u_riscv_top.wb_dcache_dat_o[21] ,
+    \u_riscv_top.wb_dcache_dat_o[20] ,
+    \u_riscv_top.wb_dcache_dat_o[19] ,
+    \u_riscv_top.wb_dcache_dat_o[18] ,
+    \u_riscv_top.wb_dcache_dat_o[17] ,
+    \u_riscv_top.wb_dcache_dat_o[16] ,
+    \u_riscv_top.wb_dcache_dat_o[15] ,
+    \u_riscv_top.wb_dcache_dat_o[14] ,
+    \u_riscv_top.wb_dcache_dat_o[13] ,
+    \u_riscv_top.wb_dcache_dat_o[12] ,
+    \u_riscv_top.wb_dcache_dat_o[11] ,
+    \u_riscv_top.wb_dcache_dat_o[10] ,
+    \u_riscv_top.wb_dcache_dat_o[9] ,
+    \u_riscv_top.wb_dcache_dat_o[8] ,
+    \u_riscv_top.wb_dcache_dat_o[7] ,
+    \u_riscv_top.wb_dcache_dat_o[6] ,
+    \u_riscv_top.wb_dcache_dat_o[5] ,
+    \u_riscv_top.wb_dcache_dat_o[4] ,
+    \u_riscv_top.wb_dcache_dat_o[3] ,
+    \u_riscv_top.wb_dcache_dat_o[2] ,
+    \u_riscv_top.wb_dcache_dat_o[1] ,
+    \u_riscv_top.wb_dcache_dat_o[0] }),
+    .wb_dcache_sel_o({\u_riscv_top.wb_dcache_sel_o[3] ,
+    \u_riscv_top.wb_dcache_sel_o[2] ,
+    \u_riscv_top.wb_dcache_sel_o[1] ,
+    \u_riscv_top.wb_dcache_sel_o[0] }),
+    .wb_icache_adr_o({\u_riscv_top.wb_icache_adr_o[31] ,
+    \u_riscv_top.wb_icache_adr_o[30] ,
+    \u_riscv_top.wb_icache_adr_o[29] ,
+    \u_riscv_top.wb_icache_adr_o[28] ,
+    \u_riscv_top.wb_icache_adr_o[27] ,
+    \u_riscv_top.wb_icache_adr_o[26] ,
+    \u_riscv_top.wb_icache_adr_o[25] ,
+    \u_riscv_top.wb_icache_adr_o[24] ,
+    \u_riscv_top.wb_icache_adr_o[23] ,
+    \u_riscv_top.wb_icache_adr_o[22] ,
+    \u_riscv_top.wb_icache_adr_o[21] ,
+    \u_riscv_top.wb_icache_adr_o[20] ,
+    \u_riscv_top.wb_icache_adr_o[19] ,
+    \u_riscv_top.wb_icache_adr_o[18] ,
+    \u_riscv_top.wb_icache_adr_o[17] ,
+    \u_riscv_top.wb_icache_adr_o[16] ,
+    \u_riscv_top.wb_icache_adr_o[15] ,
+    \u_riscv_top.wb_icache_adr_o[14] ,
+    \u_riscv_top.wb_icache_adr_o[13] ,
+    \u_riscv_top.wb_icache_adr_o[12] ,
+    \u_riscv_top.wb_icache_adr_o[11] ,
+    \u_riscv_top.wb_icache_adr_o[10] ,
+    \u_riscv_top.wb_icache_adr_o[9] ,
+    \u_riscv_top.wb_icache_adr_o[8] ,
+    \u_riscv_top.wb_icache_adr_o[7] ,
+    \u_riscv_top.wb_icache_adr_o[6] ,
+    \u_riscv_top.wb_icache_adr_o[5] ,
+    \u_riscv_top.wb_icache_adr_o[4] ,
+    \u_riscv_top.wb_icache_adr_o[3] ,
+    \u_riscv_top.wb_icache_adr_o[2] ,
+    \u_riscv_top.wb_icache_adr_o[1] ,
+    \u_riscv_top.wb_icache_adr_o[0] }),
+    .wb_icache_bl_o({\u_riscv_top.wb_icache_bl_o[9] ,
+    \u_riscv_top.wb_icache_bl_o[8] ,
+    \u_riscv_top.wb_icache_bl_o[7] ,
+    \u_riscv_top.wb_icache_bl_o[6] ,
+    \u_riscv_top.wb_icache_bl_o[5] ,
+    \u_riscv_top.wb_icache_bl_o[4] ,
+    \u_riscv_top.wb_icache_bl_o[3] ,
+    \u_riscv_top.wb_icache_bl_o[2] ,
+    \u_riscv_top.wb_icache_bl_o[1] ,
+    \u_riscv_top.wb_icache_bl_o[0] }),
+    .wb_icache_dat_i({\u_riscv_top.wb_icache_dat_i[31] ,
+    \u_riscv_top.wb_icache_dat_i[30] ,
+    \u_riscv_top.wb_icache_dat_i[29] ,
+    \u_riscv_top.wb_icache_dat_i[28] ,
+    \u_riscv_top.wb_icache_dat_i[27] ,
+    \u_riscv_top.wb_icache_dat_i[26] ,
+    \u_riscv_top.wb_icache_dat_i[25] ,
+    \u_riscv_top.wb_icache_dat_i[24] ,
+    \u_riscv_top.wb_icache_dat_i[23] ,
+    \u_riscv_top.wb_icache_dat_i[22] ,
+    \u_riscv_top.wb_icache_dat_i[21] ,
+    \u_riscv_top.wb_icache_dat_i[20] ,
+    \u_riscv_top.wb_icache_dat_i[19] ,
+    \u_riscv_top.wb_icache_dat_i[18] ,
+    \u_riscv_top.wb_icache_dat_i[17] ,
+    \u_riscv_top.wb_icache_dat_i[16] ,
+    \u_riscv_top.wb_icache_dat_i[15] ,
+    \u_riscv_top.wb_icache_dat_i[14] ,
+    \u_riscv_top.wb_icache_dat_i[13] ,
+    \u_riscv_top.wb_icache_dat_i[12] ,
+    \u_riscv_top.wb_icache_dat_i[11] ,
+    \u_riscv_top.wb_icache_dat_i[10] ,
+    \u_riscv_top.wb_icache_dat_i[9] ,
+    \u_riscv_top.wb_icache_dat_i[8] ,
+    \u_riscv_top.wb_icache_dat_i[7] ,
+    \u_riscv_top.wb_icache_dat_i[6] ,
+    \u_riscv_top.wb_icache_dat_i[5] ,
+    \u_riscv_top.wb_icache_dat_i[4] ,
+    \u_riscv_top.wb_icache_dat_i[3] ,
+    \u_riscv_top.wb_icache_dat_i[2] ,
+    \u_riscv_top.wb_icache_dat_i[1] ,
+    \u_riscv_top.wb_icache_dat_i[0] }),
+    .wb_icache_sel_o({\u_riscv_top.wb_icache_sel_o[3] ,
+    \u_riscv_top.wb_icache_sel_o[2] ,
+    \u_riscv_top.wb_icache_sel_o[1] ,
+    \u_riscv_top.wb_icache_sel_o[0] }),
+    .wbd_dmem_adr_o({\u_riscv_top.wbd_dmem_adr_o[31] ,
+    \u_riscv_top.wbd_dmem_adr_o[30] ,
+    \u_riscv_top.wbd_dmem_adr_o[29] ,
+    \u_riscv_top.wbd_dmem_adr_o[28] ,
+    \u_riscv_top.wbd_dmem_adr_o[27] ,
+    \u_riscv_top.wbd_dmem_adr_o[26] ,
+    \u_riscv_top.wbd_dmem_adr_o[25] ,
+    \u_riscv_top.wbd_dmem_adr_o[24] ,
+    \u_riscv_top.wbd_dmem_adr_o[23] ,
+    \u_riscv_top.wbd_dmem_adr_o[22] ,
+    \u_riscv_top.wbd_dmem_adr_o[21] ,
+    \u_riscv_top.wbd_dmem_adr_o[20] ,
+    \u_riscv_top.wbd_dmem_adr_o[19] ,
+    \u_riscv_top.wbd_dmem_adr_o[18] ,
+    \u_riscv_top.wbd_dmem_adr_o[17] ,
+    \u_riscv_top.wbd_dmem_adr_o[16] ,
+    \u_riscv_top.wbd_dmem_adr_o[15] ,
+    \u_riscv_top.wbd_dmem_adr_o[14] ,
+    \u_riscv_top.wbd_dmem_adr_o[13] ,
+    \u_riscv_top.wbd_dmem_adr_o[12] ,
+    \u_riscv_top.wbd_dmem_adr_o[11] ,
+    \u_riscv_top.wbd_dmem_adr_o[10] ,
+    \u_riscv_top.wbd_dmem_adr_o[9] ,
+    \u_riscv_top.wbd_dmem_adr_o[8] ,
+    \u_riscv_top.wbd_dmem_adr_o[7] ,
+    \u_riscv_top.wbd_dmem_adr_o[6] ,
+    \u_riscv_top.wbd_dmem_adr_o[5] ,
+    \u_riscv_top.wbd_dmem_adr_o[4] ,
+    \u_riscv_top.wbd_dmem_adr_o[3] ,
+    \u_riscv_top.wbd_dmem_adr_o[2] ,
+    \u_riscv_top.wbd_dmem_adr_o[1] ,
+    \u_riscv_top.wbd_dmem_adr_o[0] }),
+    .wbd_dmem_bl_o({\u_riscv_top.wbd_dmem_bl_o[2] ,
+    \u_riscv_top.wbd_dmem_bl_o[1] ,
+    \u_riscv_top.wbd_dmem_bl_o[0] }),
+    .wbd_dmem_dat_i({\u_riscv_top.wbd_dmem_dat_i[31] ,
+    \u_riscv_top.wbd_dmem_dat_i[30] ,
+    \u_riscv_top.wbd_dmem_dat_i[29] ,
+    \u_riscv_top.wbd_dmem_dat_i[28] ,
+    \u_riscv_top.wbd_dmem_dat_i[27] ,
+    \u_riscv_top.wbd_dmem_dat_i[26] ,
+    \u_riscv_top.wbd_dmem_dat_i[25] ,
+    \u_riscv_top.wbd_dmem_dat_i[24] ,
+    \u_riscv_top.wbd_dmem_dat_i[23] ,
+    \u_riscv_top.wbd_dmem_dat_i[22] ,
+    \u_riscv_top.wbd_dmem_dat_i[21] ,
+    \u_riscv_top.wbd_dmem_dat_i[20] ,
+    \u_riscv_top.wbd_dmem_dat_i[19] ,
+    \u_riscv_top.wbd_dmem_dat_i[18] ,
+    \u_riscv_top.wbd_dmem_dat_i[17] ,
+    \u_riscv_top.wbd_dmem_dat_i[16] ,
+    \u_riscv_top.wbd_dmem_dat_i[15] ,
+    \u_riscv_top.wbd_dmem_dat_i[14] ,
+    \u_riscv_top.wbd_dmem_dat_i[13] ,
+    \u_riscv_top.wbd_dmem_dat_i[12] ,
+    \u_riscv_top.wbd_dmem_dat_i[11] ,
+    \u_riscv_top.wbd_dmem_dat_i[10] ,
+    \u_riscv_top.wbd_dmem_dat_i[9] ,
+    \u_riscv_top.wbd_dmem_dat_i[8] ,
+    \u_riscv_top.wbd_dmem_dat_i[7] ,
+    \u_riscv_top.wbd_dmem_dat_i[6] ,
+    \u_riscv_top.wbd_dmem_dat_i[5] ,
+    \u_riscv_top.wbd_dmem_dat_i[4] ,
+    \u_riscv_top.wbd_dmem_dat_i[3] ,
+    \u_riscv_top.wbd_dmem_dat_i[2] ,
+    \u_riscv_top.wbd_dmem_dat_i[1] ,
+    \u_riscv_top.wbd_dmem_dat_i[0] }),
+    .wbd_dmem_dat_o({\u_riscv_top.wbd_dmem_dat_o[31] ,
+    \u_riscv_top.wbd_dmem_dat_o[30] ,
+    \u_riscv_top.wbd_dmem_dat_o[29] ,
+    \u_riscv_top.wbd_dmem_dat_o[28] ,
+    \u_riscv_top.wbd_dmem_dat_o[27] ,
+    \u_riscv_top.wbd_dmem_dat_o[26] ,
+    \u_riscv_top.wbd_dmem_dat_o[25] ,
+    \u_riscv_top.wbd_dmem_dat_o[24] ,
+    \u_riscv_top.wbd_dmem_dat_o[23] ,
+    \u_riscv_top.wbd_dmem_dat_o[22] ,
+    \u_riscv_top.wbd_dmem_dat_o[21] ,
+    \u_riscv_top.wbd_dmem_dat_o[20] ,
+    \u_riscv_top.wbd_dmem_dat_o[19] ,
+    \u_riscv_top.wbd_dmem_dat_o[18] ,
+    \u_riscv_top.wbd_dmem_dat_o[17] ,
+    \u_riscv_top.wbd_dmem_dat_o[16] ,
+    \u_riscv_top.wbd_dmem_dat_o[15] ,
+    \u_riscv_top.wbd_dmem_dat_o[14] ,
+    \u_riscv_top.wbd_dmem_dat_o[13] ,
+    \u_riscv_top.wbd_dmem_dat_o[12] ,
+    \u_riscv_top.wbd_dmem_dat_o[11] ,
+    \u_riscv_top.wbd_dmem_dat_o[10] ,
+    \u_riscv_top.wbd_dmem_dat_o[9] ,
+    \u_riscv_top.wbd_dmem_dat_o[8] ,
+    \u_riscv_top.wbd_dmem_dat_o[7] ,
+    \u_riscv_top.wbd_dmem_dat_o[6] ,
+    \u_riscv_top.wbd_dmem_dat_o[5] ,
+    \u_riscv_top.wbd_dmem_dat_o[4] ,
+    \u_riscv_top.wbd_dmem_dat_o[3] ,
+    \u_riscv_top.wbd_dmem_dat_o[2] ,
+    \u_riscv_top.wbd_dmem_dat_o[1] ,
+    \u_riscv_top.wbd_dmem_dat_o[0] }),
+    .wbd_dmem_sel_o({\u_riscv_top.wbd_dmem_sel_o[3] ,
+    \u_riscv_top.wbd_dmem_sel_o[2] ,
+    \u_riscv_top.wbd_dmem_sel_o[1] ,
+    \u_riscv_top.wbd_dmem_sel_o[0] }));
+ sky130_sram_2kbyte_1rw1r_32x512_8 u_tsram0_2kb (.csb0(\u_riscv_top.sram0_csb0 ),
+    .csb1(\u_riscv_top.sram0_csb1 ),
+    .web0(\u_riscv_top.sram0_web0 ),
+    .clk0(\u_riscv_top.sram0_clk0 ),
+    .clk1(\u_riscv_top.sram0_clk1 ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .addr0({\u_riscv_top.sram0_addr0[8] ,
+    \u_riscv_top.sram0_addr0[7] ,
+    \u_riscv_top.sram0_addr0[6] ,
+    \u_riscv_top.sram0_addr0[5] ,
+    \u_riscv_top.sram0_addr0[4] ,
+    \u_riscv_top.sram0_addr0[3] ,
+    \u_riscv_top.sram0_addr0[2] ,
+    \u_riscv_top.sram0_addr0[1] ,
+    \u_riscv_top.sram0_addr0[0] }),
+    .addr1({\u_riscv_top.sram0_addr1[8] ,
+    \u_riscv_top.sram0_addr1[7] ,
+    \u_riscv_top.sram0_addr1[6] ,
+    \u_riscv_top.sram0_addr1[5] ,
+    \u_riscv_top.sram0_addr1[4] ,
+    \u_riscv_top.sram0_addr1[3] ,
+    \u_riscv_top.sram0_addr1[2] ,
+    \u_riscv_top.sram0_addr1[1] ,
+    \u_riscv_top.sram0_addr1[0] }),
+    .din0({\u_riscv_top.sram0_din0[31] ,
+    \u_riscv_top.sram0_din0[30] ,
+    \u_riscv_top.sram0_din0[29] ,
+    \u_riscv_top.sram0_din0[28] ,
+    \u_riscv_top.sram0_din0[27] ,
+    \u_riscv_top.sram0_din0[26] ,
+    \u_riscv_top.sram0_din0[25] ,
+    \u_riscv_top.sram0_din0[24] ,
+    \u_riscv_top.sram0_din0[23] ,
+    \u_riscv_top.sram0_din0[22] ,
+    \u_riscv_top.sram0_din0[21] ,
+    \u_riscv_top.sram0_din0[20] ,
+    \u_riscv_top.sram0_din0[19] ,
+    \u_riscv_top.sram0_din0[18] ,
+    \u_riscv_top.sram0_din0[17] ,
+    \u_riscv_top.sram0_din0[16] ,
+    \u_riscv_top.sram0_din0[15] ,
+    \u_riscv_top.sram0_din0[14] ,
+    \u_riscv_top.sram0_din0[13] ,
+    \u_riscv_top.sram0_din0[12] ,
+    \u_riscv_top.sram0_din0[11] ,
+    \u_riscv_top.sram0_din0[10] ,
+    \u_riscv_top.sram0_din0[9] ,
+    \u_riscv_top.sram0_din0[8] ,
+    \u_riscv_top.sram0_din0[7] ,
+    \u_riscv_top.sram0_din0[6] ,
+    \u_riscv_top.sram0_din0[5] ,
+    \u_riscv_top.sram0_din0[4] ,
+    \u_riscv_top.sram0_din0[3] ,
+    \u_riscv_top.sram0_din0[2] ,
+    \u_riscv_top.sram0_din0[1] ,
+    \u_riscv_top.sram0_din0[0] }),
+    .dout0({\u_riscv_top.sram0_dout0[31] ,
+    \u_riscv_top.sram0_dout0[30] ,
+    \u_riscv_top.sram0_dout0[29] ,
+    \u_riscv_top.sram0_dout0[28] ,
+    \u_riscv_top.sram0_dout0[27] ,
+    \u_riscv_top.sram0_dout0[26] ,
+    \u_riscv_top.sram0_dout0[25] ,
+    \u_riscv_top.sram0_dout0[24] ,
+    \u_riscv_top.sram0_dout0[23] ,
+    \u_riscv_top.sram0_dout0[22] ,
+    \u_riscv_top.sram0_dout0[21] ,
+    \u_riscv_top.sram0_dout0[20] ,
+    \u_riscv_top.sram0_dout0[19] ,
+    \u_riscv_top.sram0_dout0[18] ,
+    \u_riscv_top.sram0_dout0[17] ,
+    \u_riscv_top.sram0_dout0[16] ,
+    \u_riscv_top.sram0_dout0[15] ,
+    \u_riscv_top.sram0_dout0[14] ,
+    \u_riscv_top.sram0_dout0[13] ,
+    \u_riscv_top.sram0_dout0[12] ,
+    \u_riscv_top.sram0_dout0[11] ,
+    \u_riscv_top.sram0_dout0[10] ,
+    \u_riscv_top.sram0_dout0[9] ,
+    \u_riscv_top.sram0_dout0[8] ,
+    \u_riscv_top.sram0_dout0[7] ,
+    \u_riscv_top.sram0_dout0[6] ,
+    \u_riscv_top.sram0_dout0[5] ,
+    \u_riscv_top.sram0_dout0[4] ,
+    \u_riscv_top.sram0_dout0[3] ,
+    \u_riscv_top.sram0_dout0[2] ,
+    \u_riscv_top.sram0_dout0[1] ,
+    \u_riscv_top.sram0_dout0[0] }),
+    .dout1({\u_riscv_top.sram0_dout1[31] ,
+    \u_riscv_top.sram0_dout1[30] ,
+    \u_riscv_top.sram0_dout1[29] ,
+    \u_riscv_top.sram0_dout1[28] ,
+    \u_riscv_top.sram0_dout1[27] ,
+    \u_riscv_top.sram0_dout1[26] ,
+    \u_riscv_top.sram0_dout1[25] ,
+    \u_riscv_top.sram0_dout1[24] ,
+    \u_riscv_top.sram0_dout1[23] ,
+    \u_riscv_top.sram0_dout1[22] ,
+    \u_riscv_top.sram0_dout1[21] ,
+    \u_riscv_top.sram0_dout1[20] ,
+    \u_riscv_top.sram0_dout1[19] ,
+    \u_riscv_top.sram0_dout1[18] ,
+    \u_riscv_top.sram0_dout1[17] ,
+    \u_riscv_top.sram0_dout1[16] ,
+    \u_riscv_top.sram0_dout1[15] ,
+    \u_riscv_top.sram0_dout1[14] ,
+    \u_riscv_top.sram0_dout1[13] ,
+    \u_riscv_top.sram0_dout1[12] ,
+    \u_riscv_top.sram0_dout1[11] ,
+    \u_riscv_top.sram0_dout1[10] ,
+    \u_riscv_top.sram0_dout1[9] ,
+    \u_riscv_top.sram0_dout1[8] ,
+    \u_riscv_top.sram0_dout1[7] ,
+    \u_riscv_top.sram0_dout1[6] ,
+    \u_riscv_top.sram0_dout1[5] ,
+    \u_riscv_top.sram0_dout1[4] ,
+    \u_riscv_top.sram0_dout1[3] ,
+    \u_riscv_top.sram0_dout1[2] ,
+    \u_riscv_top.sram0_dout1[1] ,
+    \u_riscv_top.sram0_dout1[0] }),
+    .wmask0({\u_riscv_top.sram0_wmask0[3] ,
+    \u_riscv_top.sram0_wmask0[2] ,
+    \u_riscv_top.sram0_wmask0[1] ,
+    \u_riscv_top.sram0_wmask0[0] }));
+ uart_i2c_usb_spi_top u_uart_i2c_usb_spi (.app_clk(wbd_clk_uart_skew),
+    .i2c_rstn(i2c_rst_n),
+    .i2cm_intr_o(i2cm_intr_o),
+    .reg_ack(wbd_uart_ack_i),
+    .reg_cs(wbd_uart_stb_o),
+    .reg_wr(wbd_uart_we_o),
+    .scl_pad_i(i2cm_clk_i),
+    .scl_pad_o(i2cm_clk_o),
+    .scl_pad_oen_o(i2cm_clk_oen),
+    .sda_pad_i(i2cm_data_i),
+    .sda_pad_o(i2cm_data_o),
+    .sda_padoen_o(i2cm_data_oen),
+    .spi_rstn(sspim_rst_n),
+    .sspim_sck(sspim_sck),
+    .sspim_si(sspim_si),
+    .sspim_so(sspim_so),
+    .usb_clk(usb_clk),
+    .usb_in_dn(usb_dn_i),
+    .usb_in_dp(usb_dp_i),
+    .usb_intr_o(usb_intr_o),
+    .usb_out_dn(usb_dn_o),
+    .usb_out_dp(usb_dp_o),
+    .usb_out_tx_oen(usb_oen),
+    .usb_rstn(usb_rst_n),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .wbd_clk_int(wbd_clk_uart_rp),
+    .wbd_clk_uart(wbd_clk_uart_skew),
+    .cfg_cska_uart({\cfg_wcska_uart_rp[3] ,
+    \cfg_wcska_uart_rp[2] ,
+    \cfg_wcska_uart_rp[1] ,
+    \cfg_wcska_uart_rp[0] }),
+    .reg_addr({\wbd_uart_adr_o[8] ,
+    \wbd_uart_adr_o[7] ,
+    \wbd_uart_adr_o[6] ,
+    \wbd_uart_adr_o[5] ,
+    \wbd_uart_adr_o[4] ,
+    \wbd_uart_adr_o[3] ,
+    \wbd_uart_adr_o[2] ,
+    \wbd_uart_adr_o[1] ,
+    \wbd_uart_adr_o[0] }),
+    .reg_be({\wbd_uart_sel_o[3] ,
+    \wbd_uart_sel_o[2] ,
+    \wbd_uart_sel_o[1] ,
+    \wbd_uart_sel_o[0] }),
+    .reg_rdata({\wbd_uart_dat_i[31] ,
+    \wbd_uart_dat_i[30] ,
+    \wbd_uart_dat_i[29] ,
+    \wbd_uart_dat_i[28] ,
+    \wbd_uart_dat_i[27] ,
+    \wbd_uart_dat_i[26] ,
+    \wbd_uart_dat_i[25] ,
+    \wbd_uart_dat_i[24] ,
+    \wbd_uart_dat_i[23] ,
+    \wbd_uart_dat_i[22] ,
+    \wbd_uart_dat_i[21] ,
+    \wbd_uart_dat_i[20] ,
+    \wbd_uart_dat_i[19] ,
+    \wbd_uart_dat_i[18] ,
+    \wbd_uart_dat_i[17] ,
+    \wbd_uart_dat_i[16] ,
+    \wbd_uart_dat_i[15] ,
+    \wbd_uart_dat_i[14] ,
+    \wbd_uart_dat_i[13] ,
+    \wbd_uart_dat_i[12] ,
+    \wbd_uart_dat_i[11] ,
+    \wbd_uart_dat_i[10] ,
+    \wbd_uart_dat_i[9] ,
+    \wbd_uart_dat_i[8] ,
+    \wbd_uart_dat_i[7] ,
+    \wbd_uart_dat_i[6] ,
+    \wbd_uart_dat_i[5] ,
+    \wbd_uart_dat_i[4] ,
+    \wbd_uart_dat_i[3] ,
+    \wbd_uart_dat_i[2] ,
+    \wbd_uart_dat_i[1] ,
+    \wbd_uart_dat_i[0] }),
+    .reg_wdata({\wbd_uart_dat_o[31] ,
+    \wbd_uart_dat_o[30] ,
+    \wbd_uart_dat_o[29] ,
+    \wbd_uart_dat_o[28] ,
+    \wbd_uart_dat_o[27] ,
+    \wbd_uart_dat_o[26] ,
+    \wbd_uart_dat_o[25] ,
+    \wbd_uart_dat_o[24] ,
+    \wbd_uart_dat_o[23] ,
+    \wbd_uart_dat_o[22] ,
+    \wbd_uart_dat_o[21] ,
+    \wbd_uart_dat_o[20] ,
+    \wbd_uart_dat_o[19] ,
+    \wbd_uart_dat_o[18] ,
+    \wbd_uart_dat_o[17] ,
+    \wbd_uart_dat_o[16] ,
+    \wbd_uart_dat_o[15] ,
+    \wbd_uart_dat_o[14] ,
+    \wbd_uart_dat_o[13] ,
+    \wbd_uart_dat_o[12] ,
+    \wbd_uart_dat_o[11] ,
+    \wbd_uart_dat_o[10] ,
+    \wbd_uart_dat_o[9] ,
+    \wbd_uart_dat_o[8] ,
+    \wbd_uart_dat_o[7] ,
+    \wbd_uart_dat_o[6] ,
+    \wbd_uart_dat_o[5] ,
+    \wbd_uart_dat_o[4] ,
+    \wbd_uart_dat_o[3] ,
+    \wbd_uart_dat_o[2] ,
+    \wbd_uart_dat_o[1] ,
+    \wbd_uart_dat_o[0] }),
+    .sspim_ssn({\sspim_ssn[3] ,
+    \sspim_ssn[2] ,
+    \sspim_ssn[1] ,
+    \sspim_ssn[0] }),
+    .uart_rstn({\uart_rst_n[1] ,
+    \uart_rst_n[0] }),
+    .uart_rxd({\uart_rxd[1] ,
+    \uart_rxd[0] }),
+    .uart_txd({\uart_txd[1] ,
+    \uart_txd[0] }));
+ wb_host u_wb_host (.cfg_strap_pad_ctrl(cfg_strap_pad_ctrl),
+    .cpu_clk(cpu_clk),
+    .e_reset_n(e_reset_n),
+    .int_pll_clock(\pll_clk_out[0] ),
+    .p_reset_n(p_reset_n),
+    .s_reset_n(s_reset_n),
+    .sclk(sspis_sck),
+    .sdin(sspis_si),
+    .sdout(sspis_so),
+    .ssn(sspis_ssn),
+    .uartm_rxd(uartm_rxd),
+    .uartm_txd(uartm_txd),
+    .user_clock1(wb_clk_i),
+    .user_clock2(user_clock2),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .wbd_clk_int(wbd_clk_int),
+    .wbd_clk_wh(wbd_clk_wh),
+    .wbd_int_rst_n(\u_riscv_top.pwrup_rst_n ),
+    .wbd_pll_rst_n(wbd_pll_rst_n),
+    .wbm_ack_o(wbs_ack_o),
+    .wbm_clk_i(wb_clk_i),
+    .wbm_cyc_i(wbs_cyc_i),
+    .wbm_rst_i(wb_rst_i),
+    .wbm_stb_i(wbs_stb_i),
+    .wbm_we_i(wbs_we_i),
+    .wbs_ack_i(wbd_int_ack_o),
+    .wbs_clk_i(wbd_clk_wh),
+    .wbs_clk_out(wbd_clk_int),
+    .wbs_cyc_o(wbd_int_cyc_i),
+    .wbs_err_i(wbd_int_err_o),
+    .wbs_stb_o(wbd_int_stb_i),
+    .wbs_we_o(wbd_int_we_i),
+    .xtal_clk(xtal_clk),
+    .cfg_clk_skew_ctrl1({\cfg_clk_skew_ctrl1[31] ,
+    \cfg_clk_skew_ctrl1[30] ,
+    \cfg_clk_skew_ctrl1[29] ,
+    \cfg_clk_skew_ctrl1[28] ,
+    \cfg_clk_skew_ctrl1[27] ,
+    \cfg_clk_skew_ctrl1[26] ,
+    \cfg_clk_skew_ctrl1[25] ,
+    \cfg_clk_skew_ctrl1[24] ,
+    \cfg_clk_skew_ctrl1[23] ,
+    \cfg_clk_skew_ctrl1[22] ,
+    \cfg_clk_skew_ctrl1[21] ,
+    \cfg_clk_skew_ctrl1[20] ,
+    \cfg_clk_skew_ctrl1[19] ,
+    \cfg_clk_skew_ctrl1[18] ,
+    \cfg_clk_skew_ctrl1[17] ,
+    \cfg_clk_skew_ctrl1[16] ,
+    \cfg_clk_skew_ctrl1[15] ,
+    \cfg_clk_skew_ctrl1[14] ,
+    \cfg_clk_skew_ctrl1[13] ,
+    \cfg_clk_skew_ctrl1[12] ,
+    \cfg_clk_skew_ctrl1[11] ,
+    \cfg_clk_skew_ctrl1[10] ,
+    \cfg_clk_skew_ctrl1[9] ,
+    \cfg_clk_skew_ctrl1[8] ,
+    \cfg_clk_skew_ctrl1[7] ,
+    \cfg_clk_skew_ctrl1[6] ,
+    \cfg_clk_skew_ctrl1[5] ,
+    \cfg_clk_skew_ctrl1[4] ,
+    \cfg_clk_skew_ctrl1[3] ,
+    \cfg_clk_skew_ctrl1[2] ,
+    \cfg_clk_skew_ctrl1[1] ,
+    \cfg_clk_skew_ctrl1[0] }),
+    .cfg_clk_skew_ctrl2({\cfg_clk_skew_ctrl2[31] ,
+    \cfg_clk_skew_ctrl2[30] ,
+    \cfg_clk_skew_ctrl2[29] ,
+    \cfg_clk_skew_ctrl2[28] ,
+    \cfg_clk_skew_ctrl2[27] ,
+    \cfg_clk_skew_ctrl2[26] ,
+    \cfg_clk_skew_ctrl2[25] ,
+    \cfg_clk_skew_ctrl2[24] ,
+    \cfg_clk_skew_ctrl2[23] ,
+    \cfg_clk_skew_ctrl2[22] ,
+    \cfg_clk_skew_ctrl2[21] ,
+    \cfg_clk_skew_ctrl2[20] ,
+    \cfg_clk_skew_ctrl2[19] ,
+    \cfg_clk_skew_ctrl2[18] ,
+    \cfg_clk_skew_ctrl2[17] ,
+    \cfg_clk_skew_ctrl2[16] ,
+    \cfg_clk_skew_ctrl2[15] ,
+    \cfg_clk_skew_ctrl2[14] ,
+    \cfg_clk_skew_ctrl2[13] ,
+    \cfg_clk_skew_ctrl2[12] ,
+    \cfg_clk_skew_ctrl2[11] ,
+    \cfg_clk_skew_ctrl2[10] ,
+    \cfg_clk_skew_ctrl2[9] ,
+    \cfg_clk_skew_ctrl2[8] ,
+    \cfg_clk_skew_ctrl2[7] ,
+    \cfg_clk_skew_ctrl2[6] ,
+    \cfg_clk_skew_ctrl2[5] ,
+    \cfg_clk_skew_ctrl2[4] ,
+    \cfg_clk_skew_ctrl2[3] ,
+    \cfg_clk_skew_ctrl2[2] ,
+    \cfg_clk_skew_ctrl2[1] ,
+    \cfg_clk_skew_ctrl2[0] }),
+    .cfg_cska_wh({\cfg_clk_skew_ctrl1[7] ,
+    \cfg_clk_skew_ctrl1[6] ,
+    \cfg_clk_skew_ctrl1[5] ,
+    \cfg_clk_skew_ctrl1[4] }),
+    .la_data_in({la_data_in[17],
+    la_data_in[16],
+    la_data_in[15],
+    la_data_in[14],
+    la_data_in[13],
+    la_data_in[12],
+    la_data_in[11],
+    la_data_in[10],
+    la_data_in[9],
+    la_data_in[8],
+    la_data_in[7],
+    la_data_in[6],
+    la_data_in[5],
+    la_data_in[4],
+    la_data_in[3],
+    la_data_in[2],
+    la_data_in[1],
+    la_data_in[0]}),
+    .strap_sticky({\strap_sticky_rp[31] ,
+    \strap_sticky_rp[30] ,
+    \strap_sticky_rp[29] ,
+    \strap_sticky_rp[28] ,
+    \strap_sticky_rp[27] ,
+    \strap_sticky_rp[26] ,
+    \strap_sticky_rp[25] ,
+    \strap_sticky_rp[24] ,
+    \strap_sticky_rp[23] ,
+    \strap_sticky_rp[22] ,
+    \strap_sticky_rp[21] ,
+    \strap_sticky_rp[20] ,
+    \strap_sticky_rp[19] ,
+    \strap_sticky_rp[18] ,
+    \strap_sticky_rp[17] ,
+    \strap_sticky_rp[16] ,
+    \strap_sticky_rp[15] ,
+    \strap_sticky_rp[14] ,
+    \strap_sticky_rp[13] ,
+    \strap_sticky_rp[12] ,
+    \strap_sticky_rp[11] ,
+    \strap_sticky_rp[10] ,
+    \strap_sticky_rp[9] ,
+    \strap_sticky_rp[8] ,
+    \strap_sticky_rp[7] ,
+    \strap_sticky_rp[6] ,
+    \strap_sticky_rp[5] ,
+    \strap_sticky_rp[4] ,
+    \strap_sticky_rp[3] ,
+    \strap_sticky_rp[2] ,
+    \strap_sticky_rp[1] ,
+    \strap_sticky_rp[0] }),
+    .strap_uartm({\strap_uartm_rp[1] ,
+    \strap_uartm_rp[0] }),
+    .system_strap({\system_strap[31] ,
+    \system_strap[30] ,
+    \system_strap[29] ,
+    \system_strap[28] ,
+    \system_strap[27] ,
+    \system_strap[26] ,
+    \system_strap[25] ,
+    \system_strap[24] ,
+    \system_strap[23] ,
+    \system_strap[22] ,
+    \system_strap[21] ,
+    \system_strap[20] ,
+    \system_strap[19] ,
+    \system_strap[18] ,
+    \system_strap[17] ,
+    \system_strap[16] ,
+    \system_strap[15] ,
+    \system_strap[14] ,
+    \system_strap[13] ,
+    \system_strap[12] ,
+    \system_strap[11] ,
+    \system_strap[10] ,
+    \system_strap[9] ,
+    \system_strap[8] ,
+    \system_strap[7] ,
+    \system_strap[6] ,
+    \system_strap[5] ,
+    \system_strap[4] ,
+    \system_strap[3] ,
+    \system_strap[2] ,
+    \system_strap[1] ,
+    \system_strap[0] }),
+    .wbm_adr_i({wbs_adr_i[31],
+    wbs_adr_i[30],
+    wbs_adr_i[29],
+    wbs_adr_i[28],
+    wbs_adr_i[27],
+    wbs_adr_i[26],
+    wbs_adr_i[25],
+    wbs_adr_i[24],
+    wbs_adr_i[23],
+    wbs_adr_i[22],
+    wbs_adr_i[21],
+    wbs_adr_i[20],
+    wbs_adr_i[19],
+    wbs_adr_i[18],
+    wbs_adr_i[17],
+    wbs_adr_i[16],
+    wbs_adr_i[15],
+    wbs_adr_i[14],
+    wbs_adr_i[13],
+    wbs_adr_i[12],
+    wbs_adr_i[11],
+    wbs_adr_i[10],
+    wbs_adr_i[9],
+    wbs_adr_i[8],
+    wbs_adr_i[7],
+    wbs_adr_i[6],
+    wbs_adr_i[5],
+    wbs_adr_i[4],
+    wbs_adr_i[3],
+    wbs_adr_i[2],
+    wbs_adr_i[1],
+    wbs_adr_i[0]}),
+    .wbm_dat_i({wbs_dat_i[31],
+    wbs_dat_i[30],
+    wbs_dat_i[29],
+    wbs_dat_i[28],
+    wbs_dat_i[27],
+    wbs_dat_i[26],
+    wbs_dat_i[25],
+    wbs_dat_i[24],
+    wbs_dat_i[23],
+    wbs_dat_i[22],
+    wbs_dat_i[21],
+    wbs_dat_i[20],
+    wbs_dat_i[19],
+    wbs_dat_i[18],
+    wbs_dat_i[17],
+    wbs_dat_i[16],
+    wbs_dat_i[15],
+    wbs_dat_i[14],
+    wbs_dat_i[13],
+    wbs_dat_i[12],
+    wbs_dat_i[11],
+    wbs_dat_i[10],
+    wbs_dat_i[9],
+    wbs_dat_i[8],
+    wbs_dat_i[7],
+    wbs_dat_i[6],
+    wbs_dat_i[5],
+    wbs_dat_i[4],
+    wbs_dat_i[3],
+    wbs_dat_i[2],
+    wbs_dat_i[1],
+    wbs_dat_i[0]}),
+    .wbm_dat_o({wbs_dat_o[31],
+    wbs_dat_o[30],
+    wbs_dat_o[29],
+    wbs_dat_o[28],
+    wbs_dat_o[27],
+    wbs_dat_o[26],
+    wbs_dat_o[25],
+    wbs_dat_o[24],
+    wbs_dat_o[23],
+    wbs_dat_o[22],
+    wbs_dat_o[21],
+    wbs_dat_o[20],
+    wbs_dat_o[19],
+    wbs_dat_o[18],
+    wbs_dat_o[17],
+    wbs_dat_o[16],
+    wbs_dat_o[15],
+    wbs_dat_o[14],
+    wbs_dat_o[13],
+    wbs_dat_o[12],
+    wbs_dat_o[11],
+    wbs_dat_o[10],
+    wbs_dat_o[9],
+    wbs_dat_o[8],
+    wbs_dat_o[7],
+    wbs_dat_o[6],
+    wbs_dat_o[5],
+    wbs_dat_o[4],
+    wbs_dat_o[3],
+    wbs_dat_o[2],
+    wbs_dat_o[1],
+    wbs_dat_o[0]}),
+    .wbm_sel_i({wbs_sel_i[3],
+    wbs_sel_i[2],
+    wbs_sel_i[1],
+    wbs_sel_i[0]}),
+    .wbs_adr_o({\wbd_int_adr_i[31] ,
+    \wbd_int_adr_i[30] ,
+    \wbd_int_adr_i[29] ,
+    \wbd_int_adr_i[28] ,
+    \wbd_int_adr_i[27] ,
+    \wbd_int_adr_i[26] ,
+    \wbd_int_adr_i[25] ,
+    \wbd_int_adr_i[24] ,
+    \wbd_int_adr_i[23] ,
+    \wbd_int_adr_i[22] ,
+    \wbd_int_adr_i[21] ,
+    \wbd_int_adr_i[20] ,
+    \wbd_int_adr_i[19] ,
+    \wbd_int_adr_i[18] ,
+    \wbd_int_adr_i[17] ,
+    \wbd_int_adr_i[16] ,
+    \wbd_int_adr_i[15] ,
+    \wbd_int_adr_i[14] ,
+    \wbd_int_adr_i[13] ,
+    \wbd_int_adr_i[12] ,
+    \wbd_int_adr_i[11] ,
+    \wbd_int_adr_i[10] ,
+    \wbd_int_adr_i[9] ,
+    \wbd_int_adr_i[8] ,
+    \wbd_int_adr_i[7] ,
+    \wbd_int_adr_i[6] ,
+    \wbd_int_adr_i[5] ,
+    \wbd_int_adr_i[4] ,
+    \wbd_int_adr_i[3] ,
+    \wbd_int_adr_i[2] ,
+    \wbd_int_adr_i[1] ,
+    \wbd_int_adr_i[0] }),
+    .wbs_dat_i({\wbd_int_dat_o[31] ,
+    \wbd_int_dat_o[30] ,
+    \wbd_int_dat_o[29] ,
+    \wbd_int_dat_o[28] ,
+    \wbd_int_dat_o[27] ,
+    \wbd_int_dat_o[26] ,
+    \wbd_int_dat_o[25] ,
+    \wbd_int_dat_o[24] ,
+    \wbd_int_dat_o[23] ,
+    \wbd_int_dat_o[22] ,
+    \wbd_int_dat_o[21] ,
+    \wbd_int_dat_o[20] ,
+    \wbd_int_dat_o[19] ,
+    \wbd_int_dat_o[18] ,
+    \wbd_int_dat_o[17] ,
+    \wbd_int_dat_o[16] ,
+    \wbd_int_dat_o[15] ,
+    \wbd_int_dat_o[14] ,
+    \wbd_int_dat_o[13] ,
+    \wbd_int_dat_o[12] ,
+    \wbd_int_dat_o[11] ,
+    \wbd_int_dat_o[10] ,
+    \wbd_int_dat_o[9] ,
+    \wbd_int_dat_o[8] ,
+    \wbd_int_dat_o[7] ,
+    \wbd_int_dat_o[6] ,
+    \wbd_int_dat_o[5] ,
+    \wbd_int_dat_o[4] ,
+    \wbd_int_dat_o[3] ,
+    \wbd_int_dat_o[2] ,
+    \wbd_int_dat_o[1] ,
+    \wbd_int_dat_o[0] }),
+    .wbs_dat_o({\wbd_int_dat_i[31] ,
+    \wbd_int_dat_i[30] ,
+    \wbd_int_dat_i[29] ,
+    \wbd_int_dat_i[28] ,
+    \wbd_int_dat_i[27] ,
+    \wbd_int_dat_i[26] ,
+    \wbd_int_dat_i[25] ,
+    \wbd_int_dat_i[24] ,
+    \wbd_int_dat_i[23] ,
+    \wbd_int_dat_i[22] ,
+    \wbd_int_dat_i[21] ,
+    \wbd_int_dat_i[20] ,
+    \wbd_int_dat_i[19] ,
+    \wbd_int_dat_i[18] ,
+    \wbd_int_dat_i[17] ,
+    \wbd_int_dat_i[16] ,
+    \wbd_int_dat_i[15] ,
+    \wbd_int_dat_i[14] ,
+    \wbd_int_dat_i[13] ,
+    \wbd_int_dat_i[12] ,
+    \wbd_int_dat_i[11] ,
+    \wbd_int_dat_i[10] ,
+    \wbd_int_dat_i[9] ,
+    \wbd_int_dat_i[8] ,
+    \wbd_int_dat_i[7] ,
+    \wbd_int_dat_i[6] ,
+    \wbd_int_dat_i[5] ,
+    \wbd_int_dat_i[4] ,
+    \wbd_int_dat_i[3] ,
+    \wbd_int_dat_i[2] ,
+    \wbd_int_dat_i[1] ,
+    \wbd_int_dat_i[0] }),
+    .wbs_sel_o({\wbd_int_sel_i[3] ,
+    \wbd_int_sel_i[2] ,
+    \wbd_int_sel_i[1] ,
+    \wbd_int_sel_i[0] }));
+endmodule
diff --git a/mpw_precheck/outputs/user_project_wrapper.magic.drc.mag b/mpw_precheck/outputs/user_project_wrapper.magic.drc.mag
new file mode 100644
index 0000000..0f19622
--- /dev/null
+++ b/mpw_precheck/outputs/user_project_wrapper.magic.drc.mag
@@ -0,0 +1,158619 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1670125470
+<< checkpaint >>
+rect -12658 -11586 596582 715522
+<< metal1 >>
+rect 71774 702992 71780 703044
+rect 71832 703032 71838 703044
+rect 72970 703032 72976 703044
+rect 71832 703004 72976 703032
+rect 71832 702992 71838 703004
+rect 72970 702992 72976 703004
+rect 73028 702992 73034 703044
+rect 201494 702992 201500 703044
+rect 201552 703032 201558 703044
+rect 202782 703032 202788 703044
+rect 201552 703004 202788 703032
+rect 201552 702992 201558 703004
+rect 202782 702992 202788 703004
+rect 202840 702992 202846 703044
+rect 331214 702992 331220 703044
+rect 331272 703032 331278 703044
+rect 332502 703032 332508 703044
+rect 331272 703004 332508 703032
+rect 331272 702992 331278 703004
+rect 332502 702992 332508 703004
+rect 332560 702992 332566 703044
+rect 89162 700340 89168 700392
+rect 89220 700380 89226 700392
+rect 352742 700380 352748 700392
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+rect 574542 -5702 590142 -5146
+rect 590698 -5702 590730 -5146
+rect -6806 -5734 590730 -5702
+rect -7766 -6106 591690 -6074
+rect -7766 -6662 -7734 -6106
+rect -7178 -6662 591102 -6106
+rect 591658 -6662 591690 -6106
+rect -7766 -6694 591690 -6662
+rect -8726 -7066 592650 -7034
+rect -8726 -7622 -8694 -7066
+rect -8138 -7622 592062 -7066
+rect 592618 -7622 592650 -7066
+rect -8726 -7654 592650 -7622
+use dac_top  u_4x8bit_dac
+timestamp 0
+transform 1 0 370000 0 1 500000
+box -800 2128 48000 110800
+use sky130_sram_2kbyte_1rw1r_32x512_8  u_dcache_2kb $PDK_PATH/libs.ref/sky130_sram_macros/maglef
+timestamp 1666464484
+transform 1 0 30000 0 1 26000
+box 0 0 136620 83308
+use sky130_sram_2kbyte_1rw1r_32x512_8  u_icache_2kb
+timestamp 1666464484
+transform 1 0 190000 0 1 26000
+box 0 0 136620 83308
+use wb_interconnect  u_intercon
+timestamp 0
+transform 1 0 370000 0 1 130000
+box 0 0 60000 357456
+use pinmux_top  u_pinmux
+timestamp 0
+transform 1 0 450000 0 1 400000
+box -800 -800 104800 180800
+use dg_pll  u_pll
+timestamp 0
+transform 1 0 500000 0 1 605600
+box 0 0 18000 20000
+use qspim_top  u_qspi_master
+timestamp 0
+transform 1 0 450000 0 1 90000
+box 0 0 90000 107760
+use ycr_core_top  u_riscv_top.i_core_top_0
+timestamp 0
+transform 1 0 15000 0 1 280000
+box 1066 144 108000 187728
+use ycr_core_top  u_riscv_top.i_core_top_1
+timestamp 0
+transform -1 0 348000 0 1 280000
+box 1066 144 108000 187728
+use ycr_core_top  u_riscv_top.i_core_top_2
+timestamp 0
+transform 1 0 15000 0 1 495000
+box 1066 144 108000 187728
+use ycr_core_top  u_riscv_top.i_core_top_3
+timestamp 0
+transform -1 0 348000 0 1 495000
+box 1066 144 108000 187728
+use ycr4_iconnect  u_riscv_top.u_connect
+timestamp 0
+transform 1 0 147000 0 1 280000
+box 0 0 80000 400000
+use ycr_intf  u_riscv_top.u_intf
+timestamp 0
+transform 1 0 190000 0 1 130000
+box 0 0 162000 128000
+use sky130_sram_2kbyte_1rw1r_32x512_8  u_tsram0_2kb
+timestamp 1666464484
+transform 1 0 30000 0 1 150000
+box 0 0 136620 83308
+use uart_i2c_usb_spi_top  u_uart_i2c_usb_spi
+timestamp 0
+transform 1 0 450000 0 1 220000
+box 0 0 104000 157808
+use wb_host  u_wb_host
+timestamp 0
+transform 1 0 350000 0 1 20000
+box -800 -800 80800 85800
+<< labels >>
+rlabel metal5 s -8726 242556 592650 243796 4 vccd1
+port 1 nsew
+rlabel metal4 s 587230 -2854 587850 706790 4 vccd2
+port 2 nsew
+rlabel metal5 s -8726 678556 592650 679796 4 vdda1
+port 3 nsew
+rlabel metal4 s 591070 -6694 591690 710630 4 vdda2
+port 4 nsew
+rlabel metal5 s -8726 494556 592650 495796 4 vssa1
+port 5 nsew
+rlabel metal4 s 592030 -7654 592650 711590 4 vssa2
+port 6 nsew
+rlabel metal5 s -8726 250556 592650 251796 4 vssd1
+port 7 nsew
+rlabel metal4 s 588190 -3814 588810 707750 4 vssd2
+port 8 nsew
+rlabel metal2 s 121670 701294 121670 701294 4 analog_io[15]
+port 9 nsew
+rlabel metal2 s 56810 699900 56810 699900 4 analog_io[16]
+port 10 nsew
+rlabel metal3 s 1878 697340 1878 697340 4 analog_io[17]
+port 11 nsew
+rlabel metal3 s 1832 645116 1832 645116 4 analog_io[18]
+port 12 nsew
+rlabel metal3 s 1878 384404 1878 384404 4 analog_io[23]
+port 13 nsew
+rlabel metal2 s 378948 105815 378948 105815 4 cfg_clk_skew_ctrl1\[0\]
+port 14 nsew
+rlabel metal2 s 377844 105883 377844 105883 4 cfg_clk_skew_ctrl1\[10\]
+port 15 nsew
+rlabel metal2 s 377660 105883 377660 105883 4 cfg_clk_skew_ctrl1\[11\]
+port 16 nsew
+rlabel metal2 s 377476 105883 377476 105883 4 cfg_clk_skew_ctrl1\[12\]
+port 17 nsew
+rlabel metal2 s 377292 105883 377292 105883 4 cfg_clk_skew_ctrl1\[13\]
+port 18 nsew
+rlabel metal2 s 377108 105883 377108 105883 4 cfg_clk_skew_ctrl1\[14\]
+port 19 nsew
+rlabel metal2 s 376924 105815 376924 105815 4 cfg_clk_skew_ctrl1\[15\]
+port 20 nsew
+rlabel metal2 s 376740 105883 376740 105883 4 cfg_clk_skew_ctrl1\[16\]
+port 21 nsew
+rlabel metal2 s 376556 105883 376556 105883 4 cfg_clk_skew_ctrl1\[17\]
+port 22 nsew
+rlabel metal2 s 376372 105815 376372 105815 4 cfg_clk_skew_ctrl1\[18\]
+port 23 nsew
+rlabel metal2 s 376188 105815 376188 105815 4 cfg_clk_skew_ctrl1\[19\]
+port 24 nsew
+rlabel metal2 s 378764 105815 378764 105815 4 cfg_clk_skew_ctrl1\[1\]
+port 25 nsew
+rlabel metal2 s 376004 105815 376004 105815 4 cfg_clk_skew_ctrl1\[20\]
+port 26 nsew
+rlabel metal2 s 375820 105815 375820 105815 4 cfg_clk_skew_ctrl1\[21\]
+port 27 nsew
+rlabel metal2 s 375636 105815 375636 105815 4 cfg_clk_skew_ctrl1\[22\]
+port 28 nsew
+rlabel metal2 s 375452 105883 375452 105883 4 cfg_clk_skew_ctrl1\[23\]
+port 29 nsew
+rlabel metal2 s 375268 105815 375268 105815 4 cfg_clk_skew_ctrl1\[24\]
+port 30 nsew
+rlabel metal2 s 375084 105815 375084 105815 4 cfg_clk_skew_ctrl1\[25\]
+port 31 nsew
+rlabel metal2 s 374900 105815 374900 105815 4 cfg_clk_skew_ctrl1\[26\]
+port 32 nsew
+rlabel metal2 s 374716 105815 374716 105815 4 cfg_clk_skew_ctrl1\[27\]
+port 33 nsew
+rlabel metal2 s 378580 105815 378580 105815 4 cfg_clk_skew_ctrl1\[2\]
+port 34 nsew
+rlabel metal2 s 378396 105815 378396 105815 4 cfg_clk_skew_ctrl1\[3\]
+port 35 nsew
+rlabel metal2 s 353464 105815 353464 105815 4 cfg_clk_skew_ctrl1\[4\]
+port 36 nsew
+rlabel metal2 s 353096 105815 353096 105815 4 cfg_clk_skew_ctrl1\[5\]
+port 37 nsew
+rlabel metal2 s 352728 105815 352728 105815 4 cfg_clk_skew_ctrl1\[6\]
+port 38 nsew
+rlabel metal2 s 352360 105815 352360 105815 4 cfg_clk_skew_ctrl1\[7\]
+port 39 nsew
+rlabel metal2 s 378212 105815 378212 105815 4 cfg_clk_skew_ctrl1\[8\]
+port 40 nsew
+rlabel metal2 s 378028 105815 378028 105815 4 cfg_clk_skew_ctrl1\[9\]
+port 41 nsew
+rlabel metal2 s 374532 105815 374532 105815 4 cfg_clk_skew_ctrl2\[0\]
+port 42 nsew
+rlabel metal2 s 372692 105883 372692 105883 4 cfg_clk_skew_ctrl2\[10\]
+port 43 nsew
+rlabel metal2 s 372508 105883 372508 105883 4 cfg_clk_skew_ctrl2\[11\]
+port 44 nsew
+rlabel metal2 s 372324 105883 372324 105883 4 cfg_clk_skew_ctrl2\[12\]
+port 45 nsew
+rlabel metal2 s 372140 105883 372140 105883 4 cfg_clk_skew_ctrl2\[13\]
+port 46 nsew
+rlabel metal2 s 371956 105883 371956 105883 4 cfg_clk_skew_ctrl2\[14\]
+port 47 nsew
+rlabel metal2 s 371772 105883 371772 105883 4 cfg_clk_skew_ctrl2\[15\]
+port 48 nsew
+rlabel metal2 s 371588 105815 371588 105815 4 cfg_clk_skew_ctrl2\[16\]
+port 49 nsew
+rlabel metal2 s 371404 105815 371404 105815 4 cfg_clk_skew_ctrl2\[17\]
+port 50 nsew
+rlabel metal2 s 371220 105815 371220 105815 4 cfg_clk_skew_ctrl2\[18\]
+port 51 nsew
+rlabel metal2 s 371036 105815 371036 105815 4 cfg_clk_skew_ctrl2\[19\]
+port 52 nsew
+rlabel metal2 s 374348 105815 374348 105815 4 cfg_clk_skew_ctrl2\[1\]
+port 53 nsew
+rlabel metal2 s 370852 105815 370852 105815 4 cfg_clk_skew_ctrl2\[20\]
+port 54 nsew
+rlabel metal2 s 370668 105815 370668 105815 4 cfg_clk_skew_ctrl2\[21\]
+port 55 nsew
+rlabel metal2 s 370484 105815 370484 105815 4 cfg_clk_skew_ctrl2\[22\]
+port 56 nsew
+rlabel metal2 s 370300 105815 370300 105815 4 cfg_clk_skew_ctrl2\[23\]
+port 57 nsew
+rlabel metal2 s 351440 105815 351440 105815 4 cfg_clk_skew_ctrl2\[24\]
+port 58 nsew
+rlabel metal2 s 351256 105815 351256 105815 4 cfg_clk_skew_ctrl2\[25\]
+port 59 nsew
+rlabel metal2 s 351072 105883 351072 105883 4 cfg_clk_skew_ctrl2\[26\]
+port 60 nsew
+rlabel metal2 s 350888 105815 350888 105815 4 cfg_clk_skew_ctrl2\[27\]
+port 61 nsew
+rlabel metal2 s 350704 105866 350704 105866 4 cfg_clk_skew_ctrl2\[28\]
+port 62 nsew
+rlabel metal2 s 350520 105832 350520 105832 4 cfg_clk_skew_ctrl2\[29\]
+port 63 nsew
+rlabel metal2 s 374164 105883 374164 105883 4 cfg_clk_skew_ctrl2\[2\]
+port 64 nsew
+rlabel metal2 s 350336 105815 350336 105815 4 cfg_clk_skew_ctrl2\[30\]
+port 65 nsew
+rlabel metal2 s 350014 105043 350014 105043 4 cfg_clk_skew_ctrl2\[31\]
+port 66 nsew
+rlabel metal2 s 373934 107389 373934 107389 4 cfg_clk_skew_ctrl2\[3\]
+port 67 nsew
+rlabel metal2 s 373796 105815 373796 105815 4 cfg_clk_skew_ctrl2\[4\]
+port 68 nsew
+rlabel metal2 s 373612 105815 373612 105815 4 cfg_clk_skew_ctrl2\[5\]
+port 69 nsew
+rlabel metal2 s 373428 105815 373428 105815 4 cfg_clk_skew_ctrl2\[6\]
+port 70 nsew
+rlabel metal2 s 373244 105883 373244 105883 4 cfg_clk_skew_ctrl2\[7\]
+port 71 nsew
+rlabel metal2 s 373060 105815 373060 105815 4 cfg_clk_skew_ctrl2\[8\]
+port 72 nsew
+rlabel metal2 s 372876 105883 372876 105883 4 cfg_clk_skew_ctrl2\[9\]
+port 73 nsew
+rlabel metal2 s 376142 611276 376142 611276 4 cfg_dac0_mux_sel\[0\]
+port 74 nsew
+rlabel metal2 s 376694 610453 376694 610453 4 cfg_dac0_mux_sel\[1\]
+port 75 nsew
+rlabel metal2 s 376878 611072 376878 611072 4 cfg_dac0_mux_sel\[2\]
+port 76 nsew
+rlabel metal2 s 377430 610045 377430 610045 4 cfg_dac0_mux_sel\[3\]
+port 77 nsew
+rlabel metal2 s 377798 610147 377798 610147 4 cfg_dac0_mux_sel\[4\]
+port 78 nsew
+rlabel metal2 s 377982 611106 377982 611106 4 cfg_dac0_mux_sel\[5\]
+port 79 nsew
+rlabel metal2 s 378534 610181 378534 610181 4 cfg_dac0_mux_sel\[6\]
+port 80 nsew
+rlabel metal2 s 378718 611140 378718 611140 4 cfg_dac0_mux_sel\[7\]
+port 81 nsew
+rlabel metal2 s 386262 610283 386262 610283 4 cfg_dac1_mux_sel\[0\]
+port 82 nsew
+rlabel metal2 s 386446 611174 386446 611174 4 cfg_dac1_mux_sel\[1\]
+port 83 nsew
+rlabel metal2 s 386998 610317 386998 610317 4 cfg_dac1_mux_sel\[2\]
+port 84 nsew
+rlabel metal2 s 387182 611208 387182 611208 4 cfg_dac1_mux_sel\[3\]
+port 85 nsew
+rlabel metal2 s 387550 611786 387550 611786 4 cfg_dac1_mux_sel\[4\]
+port 86 nsew
+rlabel metal2 s 387918 611752 387918 611752 4 cfg_dac1_mux_sel\[5\]
+port 87 nsew
+rlabel metal2 s 388286 612092 388286 612092 4 cfg_dac1_mux_sel\[6\]
+port 88 nsew
+rlabel metal2 s 388654 612024 388654 612024 4 cfg_dac1_mux_sel\[7\]
+port 89 nsew
+rlabel metal2 s 452870 582546 452870 582546 4 cfg_dac2_mux_sel\[0\]
+port 90 nsew
+rlabel metal2 s 396658 610589 396658 610589 4 cfg_dac2_mux_sel\[1\]
+port 91 nsew
+rlabel metal2 s 396842 612058 396842 612058 4 cfg_dac2_mux_sel\[2\]
+port 92 nsew
+rlabel metal2 s 397210 611922 397210 611922 4 cfg_dac2_mux_sel\[3\]
+port 93 nsew
+rlabel metal2 s 418968 584324 418968 584324 4 cfg_dac2_mux_sel\[4\]
+port 94 nsew
+rlabel metal2 s 422970 601494 422970 601494 4 cfg_dac2_mux_sel\[5\]
+port 95 nsew
+rlabel metal2 s 424442 599352 424442 599352 4 cfg_dac2_mux_sel\[6\]
+port 96 nsew
+rlabel metal2 s 424534 602140 424534 602140 4 cfg_dac2_mux_sel\[7\]
+port 97 nsew
+rlabel metal2 s 406134 611242 406134 611242 4 cfg_dac3_mux_sel\[0\]
+port 98 nsew
+rlabel metal2 s 451214 581492 451214 581492 4 cfg_dac3_mux_sel\[1\]
+port 99 nsew
+rlabel metal2 s 407054 610419 407054 610419 4 cfg_dac3_mux_sel\[2\]
+port 100 nsew
+rlabel metal2 s 450846 582206 450846 582206 4 cfg_dac3_mux_sel\[3\]
+port 101 nsew
+rlabel metal2 s 450662 580778 450662 580778 4 cfg_dac3_mux_sel\[4\]
+port 102 nsew
+rlabel metal2 s 450478 580812 450478 580812 4 cfg_dac3_mux_sel\[5\]
+port 103 nsew
+rlabel metal2 s 450294 581764 450294 581764 4 cfg_dac3_mux_sel\[6\]
+port 104 nsew
+rlabel metal2 s 449919 580652 449919 580652 4 cfg_dac3_mux_sel\[7\]
+port 105 nsew
+rlabel metal2 s 496110 582206 496110 582206 4 cfg_dc_trim\[0\]
+port 106 nsew
+rlabel metal2 s 502366 626916 502366 626916 4 cfg_dc_trim\[10\]
+port 107 nsew
+rlabel metal2 s 502182 626814 502182 626814 4 cfg_dc_trim\[11\]
+port 108 nsew
+rlabel metal2 s 501998 626780 501998 626780 4 cfg_dc_trim\[12\]
+port 109 nsew
+rlabel metal2 s 501814 626746 501814 626746 4 cfg_dc_trim\[13\]
+port 110 nsew
+rlabel metal2 s 501630 626100 501630 626100 4 cfg_dc_trim\[14\]
+port 111 nsew
+rlabel metal1 s 496110 587826 496110 587826 4 cfg_dc_trim\[15\]
+port 112 nsew
+rlabel metal2 s 501262 626066 501262 626066 4 cfg_dc_trim\[16\]
+port 113 nsew
+rlabel metal3 s 500388 625260 500388 625260 4 cfg_dc_trim\[17\]
+port 114 nsew
+rlabel metal2 s 500894 626746 500894 626746 4 cfg_dc_trim\[18\]
+port 115 nsew
+rlabel metal2 s 492614 581764 492614 581764 4 cfg_dc_trim\[19\]
+port 116 nsew
+rlabel metal1 s 496386 608770 496386 608770 4 cfg_dc_trim\[1\]
+port 117 nsew
+rlabel metal2 s 520582 596479 520582 596479 4 cfg_dc_trim\[20\]
+port 118 nsew
+rlabel metal2 s 518926 597023 518926 597023 4 cfg_dc_trim\[21\]
+port 119 nsew
+rlabel metal2 s 520398 597601 520398 597601 4 cfg_dc_trim\[22\]
+port 120 nsew
+rlabel metal1 s 517500 603126 517500 603126 4 cfg_dc_trim\[23\]
+port 121 nsew
+rlabel metal2 s 500250 586177 500250 586177 4 cfg_dc_trim\[24\]
+port 122 nsew
+rlabel metal2 s 504390 596496 504390 596496 4 cfg_dc_trim\[25\]
+port 123 nsew
+rlabel metal1 s 496800 608702 496800 608702 4 cfg_dc_trim\[2\]
+port 124 nsew
+rlabel metal1 s 496662 608634 496662 608634 4 cfg_dc_trim\[3\]
+port 125 nsew
+rlabel metal1 s 495880 603126 495880 603126 4 cfg_dc_trim\[4\]
+port 126 nsew
+rlabel metal1 s 495972 603194 495972 603194 4 cfg_dc_trim\[5\]
+port 127 nsew
+rlabel metal2 s 495006 582240 495006 582240 4 cfg_dc_trim\[6\]
+port 128 nsew
+rlabel metal2 s 499790 624835 499790 624835 4 cfg_dc_trim\[7\]
+port 129 nsew
+rlabel metal2 s 500342 625624 500342 625624 4 cfg_dc_trim\[8\]
+port 130 nsew
+rlabel metal2 s 500526 625658 500526 625658 4 cfg_dc_trim\[9\]
+port 131 nsew
+rlabel metal2 s 490038 581798 490038 581798 4 cfg_dco_mode
+port 132 nsew
+rlabel metal1 s 491280 587350 491280 587350 4 cfg_pll_enb
+port 133 nsew
+rlabel metal1 s 494132 607274 494132 607274 4 cfg_pll_fed_div\[0\]
+port 134 nsew
+rlabel metal2 s 491142 581696 491142 581696 4 cfg_pll_fed_div\[1\]
+port 135 nsew
+rlabel metal1 s 494086 604554 494086 604554 4 cfg_pll_fed_div\[2\]
+port 136 nsew
+rlabel metal1 s 491418 590614 491418 590614 4 cfg_pll_fed_div\[3\]
+port 137 nsew
+rlabel metal1 s 492660 604486 492660 604486 4 cfg_pll_fed_div\[4\]
+port 138 nsew
+rlabel metal3 s 352628 254388 352628 254388 4 cfg_riscv_ctrl\[0\]
+port 139 nsew
+rlabel metal2 s 153778 681656 153778 681656 4 cfg_riscv_ctrl\[10\]
+port 140 nsew
+rlabel metal1 s 447580 487186 447580 487186 4 cfg_riscv_ctrl\[11\]
+port 141 nsew
+rlabel metal3 s 352674 254116 352674 254116 4 cfg_riscv_ctrl\[1\]
+port 142 nsew
+rlabel metal1 s 405536 488614 405536 488614 4 cfg_riscv_ctrl\[2\]
+port 143 nsew
+rlabel metal1 s 405444 488682 405444 488682 4 cfg_riscv_ctrl\[3\]
+port 144 nsew
+rlabel metal3 s 352950 253300 352950 253300 4 cfg_riscv_ctrl\[4\]
+port 145 nsew
+rlabel metal3 s 352674 253572 352674 253572 4 cfg_riscv_ctrl\[5\]
+port 146 nsew
+rlabel metal3 s 352628 253844 352628 253844 4 cfg_riscv_ctrl\[6\]
+port 147 nsew
+rlabel metal2 s 445326 443768 445326 443768 4 cfg_riscv_ctrl\[8\]
+port 148 nsew
+rlabel metal2 s 445142 442816 445142 442816 4 cfg_riscv_ctrl\[9\]
+port 149 nsew
+rlabel metal2 s 427248 105883 427248 105883 4 cfg_strap_pad_ctrl
+port 150 nsew
+rlabel metal2 s 447166 418727 447166 418727 4 cfg_strap_pad_ctrl_rp
+port 151 nsew
+rlabel metal2 s 447258 450245 447258 450245 4 cfg_wcska_pinmux_rp\[0\]
+port 152 nsew
+rlabel metal2 s 447258 449497 447258 449497 4 cfg_wcska_pinmux_rp\[1\]
+port 153 nsew
+rlabel metal2 s 447166 449327 447166 449327 4 cfg_wcska_pinmux_rp\[2\]
+port 154 nsew
+rlabel metal2 s 447350 449259 447350 449259 4 cfg_wcska_pinmux_rp\[3\]
+port 155 nsew
+rlabel metal2 s 447166 130713 447166 130713 4 cfg_wcska_qspi_co_rp\[0\]
+port 156 nsew
+rlabel metal3 s 430184 130764 430184 130764 4 cfg_wcska_qspi_co_rp\[1\]
+port 157 nsew
+rlabel metal3 s 430138 130492 430138 130492 4 cfg_wcska_qspi_co_rp\[2\]
+port 158 nsew
+rlabel metal3 s 429916 129933 429916 129933 4 cfg_wcska_qspi_co_rp\[3\]
+port 159 nsew
+rlabel metal2 s 447166 132073 447166 132073 4 cfg_wcska_qspi_rp\[0\]
+port 160 nsew
+rlabel metal2 s 447258 131903 447258 131903 4 cfg_wcska_qspi_rp\[1\]
+port 161 nsew
+rlabel metal2 s 447350 131733 447350 131733 4 cfg_wcska_qspi_rp\[2\]
+port 162 nsew
+rlabel metal2 s 447166 131563 447166 131563 4 cfg_wcska_qspi_rp\[3\]
+port 163 nsew
+rlabel metal2 s 447258 261307 447258 261307 4 cfg_wcska_uart_rp\[0\]
+port 164 nsew
+rlabel metal2 s 447350 260457 447350 260457 4 cfg_wcska_uart_rp\[1\]
+port 165 nsew
+rlabel metal2 s 447258 260355 447258 260355 4 cfg_wcska_uart_rp\[2\]
+port 166 nsew
+rlabel metal3 s 447166 260253 447166 260253 4 cfg_wcska_uart_rp\[3\]
+port 167 nsew
+rlabel metal3 s 349194 40188 349194 40188 4 cpu_clk
+port 168 nsew
+rlabel metal3 s 447166 474181 447166 474181 4 cpu_clk_rp\[2\]
+port 169 nsew
+rlabel metal2 s 427432 105883 427432 105883 4 e_reset_n
+port 170 nsew
+rlabel metal2 s 447258 418625 447258 418625 4 e_reset_n_rp
+port 171 nsew
+rlabel metal2 s 450662 219990 450662 219990 4 i2c_rst_n
+port 172 nsew
+rlabel metal2 s 457470 398082 457470 398082 4 i2cm_clk_i
+port 173 nsew
+rlabel metal2 s 457286 398048 457286 398048 4 i2cm_clk_o
+port 174 nsew
+rlabel metal2 s 457654 389106 457654 389106 4 i2cm_clk_oen
+port 175 nsew
+rlabel metal2 s 458206 389038 458206 389038 4 i2cm_data_i
+port 176 nsew
+rlabel metal2 s 458022 396586 458022 396586 4 i2cm_data_o
+port 177 nsew
+rlabel metal1 s 506460 392598 506460 392598 4 i2cm_data_oen
+port 178 nsew
+rlabel metal1 s 507518 385662 507518 385662 4 i2cm_intr_o
+port 179 nsew
+rlabel metal3 s 582230 6596 582230 6596 4 io_in[0]
+port 180 nsew
+rlabel metal2 s 580198 457453 580198 457453 4 io_in[10]
+port 181 nsew
+rlabel metal3 s 581954 511292 581954 511292 4 io_in[11]
+port 182 nsew
+rlabel metal2 s 580198 563703 580198 563703 4 io_in[12]
+port 183 nsew
+rlabel metal2 s 580198 617185 580198 617185 4 io_in[13]
+port 184 nsew
+rlabel metal2 s 560970 567120 560970 567120 4 io_in[14]
+port 185 nsew
+rlabel metal2 s 559682 701940 559682 701940 4 io_in[15]
+port 186 nsew
+rlabel metal2 s 494362 703596 494362 703596 4 io_in[16]
+port 187 nsew
+rlabel metal2 s 429870 701294 429870 701294 4 io_in[17]
+port 188 nsew
+rlabel metal2 s 364366 666883 364366 666883 4 io_in[18]
+port 189 nsew
+rlabel metal2 s 299736 703596 299736 703596 4 io_in[19]
+port 190 nsew
+rlabel metal2 s 560970 244256 560970 244256 4 io_in[1]
+port 191 nsew
+rlabel metal2 s 234830 703596 234830 703596 4 io_in[20]
+port 192 nsew
+rlabel metal2 s 527850 639234 527850 639234 4 io_in[21]
+port 193 nsew
+rlabel metal2 s 530610 581747 530610 581747 4 io_in[22]
+port 194 nsew
+rlabel metal2 s 40204 703596 40204 703596 4 io_in[23]
+port 195 nsew
+rlabel metal3 s 1878 684284 1878 684284 4 io_in[24]
+port 196 nsew
+rlabel metal3 s 2062 632060 2062 632060 4 io_in[25]
+port 197 nsew
+rlabel metal3 s 1924 579972 1924 579972 4 io_in[26]
+port 198 nsew
+rlabel metal3 s 1648 527884 1648 527884 4 io_in[27]
+port 199 nsew
+rlabel metal2 s 156538 679490 156538 679490 4 io_in[28]
+port 200 nsew
+rlabel metal3 s 2016 423572 2016 423572 4 io_in[29]
+port 201 nsew
+rlabel metal2 s 565110 264588 565110 264588 4 io_in[2]
+port 202 nsew
+rlabel metal3 s 1878 371348 1878 371348 4 io_in[30]
+port 203 nsew
+rlabel metal3 s 1832 319260 1832 319260 4 io_in[31]
+port 204 nsew
+rlabel metal3 s -960 267052 480 267292 4 io_in[32]
+port 205 nsew
+rlabel metal3 s 1832 214948 1832 214948 4 io_in[33]
+port 206 nsew
+rlabel metal4 s 364964 389164 364964 389164 4 io_in[34]
+port 207 nsew
+rlabel metal2 s 472834 580091 472834 580091 4 io_in[35]
+port 208 nsew
+rlabel metal3 s 1970 71604 1970 71604 4 io_in[36]
+port 209 nsew
+rlabel metal3 s 1740 32436 1740 32436 4 io_in[37]
+port 210 nsew
+rlabel metal2 s 580106 126463 580106 126463 4 io_in[3]
+port 211 nsew
+rlabel metal2 s 580198 166413 580198 166413 4 io_in[4]
+port 212 nsew
+rlabel metal2 s 563822 326672 563822 326672 4 io_in[5]
+port 213 nsew
+rlabel metal3 s 580198 245565 580198 245565 4 io_in[6]
+port 214 nsew
+rlabel metal3 s 581264 298724 581264 298724 4 io_in[7]
+port 215 nsew
+rlabel metal2 s 580198 352563 580198 352563 4 io_in[8]
+port 216 nsew
+rlabel metal2 s 579830 405297 579830 405297 4 io_in[9]
+port 217 nsew
+rlabel metal3 s 579922 33099 579922 33099 4 io_oeb[0]
+port 218 nsew
+rlabel metal2 s 580198 484517 580198 484517 4 io_oeb[10]
+port 219 nsew
+rlabel metal2 s 579922 537319 579922 537319 4 io_oeb[11]
+port 220 nsew
+rlabel metal2 s 559590 525742 559590 525742 4 io_oeb[12]
+port 221 nsew
+rlabel metal2 s 580198 643569 580198 643569 4 io_oeb[13]
+port 222 nsew
+rlabel metal2 s 580198 697085 580198 697085 4 io_oeb[14]
+port 223 nsew
+rlabel metal2 s 527206 643358 527206 643358 4 io_oeb[15]
+port 224 nsew
+rlabel metal2 s 462346 649512 462346 649512 4 io_oeb[16]
+port 225 nsew
+rlabel metal2 s 519570 640288 519570 640288 4 io_oeb[17]
+port 226 nsew
+rlabel metal1 s 331890 703018 331890 703018 4 io_oeb[18]
+port 227 nsew
+rlabel metal2 s 527942 637670 527942 637670 4 io_oeb[19]
+port 228 nsew
+rlabel metal2 s 580198 73049 580198 73049 4 io_oeb[1]
+port 229 nsew
+rlabel metal1 s 366850 693430 366850 693430 4 io_oeb[20]
+port 230 nsew
+rlabel metal2 s 137172 703596 137172 703596 4 io_oeb[21]
+port 231 nsew
+rlabel metal2 s 520950 634049 520950 634049 4 io_oeb[22]
+port 232 nsew
+rlabel metal2 s 7452 703596 7452 703596 4 io_oeb[23]
+port 233 nsew
+rlabel metal3 s 2154 658172 2154 658172 4 io_oeb[24]
+port 234 nsew
+rlabel metal3 s 1924 606084 1924 606084 4 io_oeb[25]
+port 235 nsew
+rlabel metal3 s 2016 553860 2016 553860 4 io_oeb[26]
+port 236 nsew
+rlabel metal3 s 1786 501772 1786 501772 4 io_oeb[27]
+port 237 nsew
+rlabel metal3 s 2062 449548 2062 449548 4 io_oeb[28]
+port 238 nsew
+rlabel metal3 s 1924 397460 1924 397460 4 io_oeb[29]
+port 239 nsew
+rlabel metal2 s 561154 278766 561154 278766 4 io_oeb[2]
+port 240 nsew
+rlabel metal3 s 1970 345372 1970 345372 4 io_oeb[30]
+port 241 nsew
+rlabel metal3 s 1832 293148 1832 293148 4 io_oeb[31]
+port 242 nsew
+rlabel metal3 s 1924 241060 1924 241060 4 io_oeb[32]
+port 243 nsew
+rlabel metal3 s 1878 188836 1878 188836 4 io_oeb[33]
+port 244 nsew
+rlabel metal3 s 1924 136748 1924 136748 4 io_oeb[34]
+port 245 nsew
+rlabel metal3 s 1648 84660 1648 84660 4 io_oeb[35]
+port 246 nsew
+rlabel metal3 s 1878 45492 1878 45492 4 io_oeb[36]
+port 247 nsew
+rlabel metal3 s -960 6340 480 6580 4 io_oeb[37]
+port 248 nsew
+rlabel metal3 s 581908 152660 581908 152660 4 io_oeb[3]
+port 249 nsew
+rlabel metal2 s 580198 192831 580198 192831 4 io_oeb[4]
+port 250 nsew
+rlabel metal2 s 580198 232781 580198 232781 4 io_oeb[5]
+port 251 nsew
+rlabel metal3 s 581954 272204 581954 272204 4 io_oeb[6]
+port 252 nsew
+rlabel metal2 s 564006 446114 564006 446114 4 io_oeb[7]
+port 253 nsew
+rlabel metal2 s 561246 416806 561246 416806 4 io_oeb[8]
+port 254 nsew
+rlabel metal3 s 582046 431596 582046 431596 4 io_oeb[9]
+port 255 nsew
+rlabel metal2 s 579922 20213 579922 20213 4 io_out[0]
+port 256 nsew
+rlabel metal2 s 564190 468860 564190 468860 4 io_out[10]
+port 257 nsew
+rlabel metal3 s 580198 524467 580198 524467 4 io_out[11]
+port 258 nsew
+rlabel metal2 s 580198 577269 580198 577269 4 io_out[12]
+port 259 nsew
+rlabel metal2 s 580014 630751 580014 630751 4 io_out[13]
+port 260 nsew
+rlabel metal3 s 581908 683876 581908 683876 4 io_out[14]
+port 261 nsew
+rlabel metal2 s 543490 701974 543490 701974 4 io_out[15]
+port 262 nsew
+rlabel metal2 s 523710 641682 523710 641682 4 io_out[16]
+port 263 nsew
+rlabel metal2 s 413080 703596 413080 703596 4 io_out[17]
+port 264 nsew
+rlabel metal2 s 347806 668957 347806 668957 4 io_out[18]
+port 265 nsew
+rlabel metal1 s 408158 696286 408158 696286 4 io_out[19]
+port 266 nsew
+rlabel metal2 s 580198 60163 580198 60163 4 io_out[1]
+port 267 nsew
+rlabel metal2 s 219006 701260 219006 701260 4 io_out[20]
+port 268 nsew
+rlabel metal1 s 154698 699686 154698 699686 4 io_out[21]
+port 269 nsew
+rlabel metal2 s 352774 668610 352774 668610 4 io_out[22]
+port 270 nsew
+rlabel metal2 s 24334 701940 24334 701940 4 io_out[23]
+port 271 nsew
+rlabel metal2 s 3772 678300 3772 678300 4 io_out[24]
+port 272 nsew
+rlabel metal3 s 1970 619140 1970 619140 4 io_out[25]
+port 273 nsew
+rlabel metal3 s 1970 566916 1970 566916 4 io_out[26]
+port 274 nsew
+rlabel metal3 s 1832 514828 1832 514828 4 io_out[27]
+port 275 nsew
+rlabel metal3 s 1832 462604 1832 462604 4 io_out[28]
+port 276 nsew
+rlabel metal3 s 1970 410516 1970 410516 4 io_out[29]
+port 277 nsew
+rlabel metal3 s 581954 99484 581954 99484 4 io_out[2]
+port 278 nsew
+rlabel metal1 s 447718 583202 447718 583202 4 io_out[30]
+port 279 nsew
+rlabel metal3 s 1694 306204 1694 306204 4 io_out[31]
+port 280 nsew
+rlabel metal3 s 1740 254116 1740 254116 4 io_out[32]
+port 281 nsew
+rlabel metal3 s 1878 201892 1878 201892 4 io_out[33]
+port 282 nsew
+rlabel metal3 s 1878 149804 1878 149804 4 io_out[34]
+port 283 nsew
+rlabel metal3 s 1786 97580 1786 97580 4 io_out[35]
+port 284 nsew
+rlabel metal3 s 1924 58548 1924 58548 4 io_out[36]
+port 285 nsew
+rlabel metal3 s 1878 19380 1878 19380 4 io_out[37]
+port 286 nsew
+rlabel metal3 s 581218 139332 581218 139332 4 io_out[3]
+port 287 nsew
+rlabel metal2 s 580198 179265 580198 179265 4 io_out[4]
+port 288 nsew
+rlabel metal3 s 582000 219028 582000 219028 4 io_out[5]
+port 289 nsew
+rlabel metal2 s 559774 354790 559774 354790 4 io_out[6]
+port 290 nsew
+rlabel metal2 s 580198 312647 580198 312647 4 io_out[7]
+port 291 nsew
+rlabel metal2 s 580198 365381 580198 365381 4 io_out[8]
+port 292 nsew
+rlabel metal2 s 579738 418863 579738 418863 4 io_out[9]
+port 293 nsew
+rlabel metal2 s 447442 449157 447442 449157 4 irq_lines\[0\]
+port 294 nsew
+rlabel metal2 s 447442 446369 447442 446369 4 irq_lines\[10\]
+port 295 nsew
+rlabel metal2 s 447350 446165 447350 446165 4 irq_lines\[11\]
+port 296 nsew
+rlabel metal2 s 447350 445349 447350 445349 4 irq_lines\[12\]
+port 297 nsew
+rlabel metal3 s 447166 445315 447166 445315 4 irq_lines\[13\]
+port 298 nsew
+rlabel metal2 s 447258 445145 447258 445145 4 irq_lines\[14\]
+port 299 nsew
+rlabel metal2 s 447166 444907 447166 444907 4 irq_lines\[15\]
+port 300 nsew
+rlabel metal2 s 447442 444839 447442 444839 4 irq_lines\[16\]
+port 301 nsew
+rlabel metal2 s 447442 443955 447442 443955 4 irq_lines\[17\]
+port 302 nsew
+rlabel metal3 s 447166 443955 447166 443955 4 irq_lines\[18\]
+port 303 nsew
+rlabel metal3 s 447166 443717 447166 443717 4 irq_lines\[19\]
+port 304 nsew
+rlabel metal2 s 447258 448885 447258 448885 4 irq_lines\[1\]
+port 305 nsew
+rlabel metal2 s 447258 443615 447258 443615 4 irq_lines\[20\]
+port 306 nsew
+rlabel metal2 s 447350 443513 447350 443513 4 irq_lines\[21\]
+port 307 nsew
+rlabel metal2 s 447350 442595 447350 442595 4 irq_lines\[22\]
+port 308 nsew
+rlabel metal2 s 447258 442493 447258 442493 4 irq_lines\[23\]
+port 309 nsew
+rlabel metal2 s 447166 442425 447166 442425 4 irq_lines\[24\]
+port 310 nsew
+rlabel metal2 s 447166 442153 447166 442153 4 irq_lines\[25\]
+port 311 nsew
+rlabel metal2 s 447442 442119 447442 442119 4 irq_lines\[26\]
+port 312 nsew
+rlabel metal2 s 447166 441337 447166 441337 4 irq_lines\[27\]
+port 313 nsew
+rlabel metal2 s 447258 441133 447258 441133 4 irq_lines\[28\]
+port 314 nsew
+rlabel metal3 s 447166 440963 447166 440963 4 irq_lines\[29\]
+port 315 nsew
+rlabel metal2 s 447442 448069 447442 448069 4 irq_lines\[2\]
+port 316 nsew
+rlabel metal2 s 447350 440895 447350 440895 4 irq_lines\[30\]
+port 317 nsew
+rlabel metal2 s 447258 440657 447258 440657 4 irq_lines\[31\]
+port 318 nsew
+rlabel metal2 s 447166 447967 447166 447967 4 irq_lines\[3\]
+port 319 nsew
+rlabel metal2 s 447258 447865 447258 447865 4 irq_lines\[4\]
+port 320 nsew
+rlabel metal2 s 447350 447763 447350 447763 4 irq_lines\[5\]
+port 321 nsew
+rlabel metal2 s 447534 447661 447534 447661 4 irq_lines\[6\]
+port 322 nsew
+rlabel metal2 s 447534 446675 447534 446675 4 irq_lines\[7\]
+port 323 nsew
+rlabel metal2 s 447166 446607 447166 446607 4 irq_lines\[8\]
+port 324 nsew
+rlabel metal2 s 447258 446539 447258 446539 4 irq_lines\[9\]
+port 325 nsew
+rlabel metal2 s 125757 340 125757 340 4 la_data_in[0]
+port 326 nsew
+rlabel metal2 s 161322 1860 161322 1860 4 la_data_in[10]
+port 327 nsew
+rlabel metal2 s 164673 340 164673 340 4 la_data_in[11]
+port 328 nsew
+rlabel metal2 s 371910 14824 371910 14824 4 la_data_in[12]
+port 329 nsew
+rlabel metal2 s 171994 8456 171994 8456 4 la_data_in[13]
+port 330 nsew
+rlabel metal2 s 175490 7742 175490 7742 4 la_data_in[14]
+port 331 nsew
+rlabel metal2 s 178841 340 178841 340 4 la_data_in[15]
+port 332 nsew
+rlabel metal2 s 403029 18972 403029 18972 4 la_data_in[16]
+port 333 nsew
+rlabel metal2 s 403259 18972 403259 18972 4 la_data_in[17]
+port 334 nsew
+rlabel metal2 s 129161 340 129161 340 4 la_data_in[1]
+port 335 nsew
+rlabel metal2 s 132986 7606 132986 7606 4 la_data_in[2]
+port 336 nsew
+rlabel metal2 s 136482 1860 136482 1860 4 la_data_in[3]
+port 337 nsew
+rlabel metal2 s 139833 340 139833 340 4 la_data_in[4]
+port 338 nsew
+rlabel metal2 s 401005 18972 401005 18972 4 la_data_in[5]
+port 339 nsew
+rlabel metal2 s 401189 18972 401189 18972 4 la_data_in[6]
+port 340 nsew
+rlabel metal2 s 150650 2846 150650 2846 4 la_data_in[7]
+port 341 nsew
+rlabel metal2 s 154238 2880 154238 2880 4 la_data_in[8]
+port 342 nsew
+rlabel metal2 s 157826 2506 157826 2506 4 la_data_in[9]
+port 343 nsew
+rlabel metal1 s 218584 279854 218584 279854 4 la_data_out[0]
+port 344 nsew
+rlabel metal1 s 449880 3842 449880 3842 4 la_data_out[100]
+port 345 nsew
+rlabel metal1 s 449834 3774 449834 3774 4 la_data_out[101]
+port 346 nsew
+rlabel metal1 s 449834 3672 449834 3672 4 la_data_out[102]
+port 347 nsew
+rlabel metal1 s 449696 4114 449696 4114 4 la_data_out[103]
+port 348 nsew
+rlabel metal2 s 495689 340 495689 340 4 la_data_out[104]
+port 349 nsew
+rlabel metal2 s 499422 1962 499422 1962 4 la_data_out[105]
+port 350 nsew
+rlabel metal2 s 503010 2030 503010 2030 4 la_data_out[106]
+port 351 nsew
+rlabel metal2 s 506506 2064 506506 2064 4 la_data_out[107]
+port 352 nsew
+rlabel metal2 s 560786 200328 560786 200328 4 la_data_out[108]
+port 353 nsew
+rlabel metal2 s 513590 1843 513590 1843 4 la_data_out[109]
+port 354 nsew
+rlabel metal2 s 217120 272612 217120 272612 4 la_data_out[10]
+port 355 nsew
+rlabel metal2 s 562166 192100 562166 192100 4 la_data_out[110]
+port 356 nsew
+rlabel metal2 s 520766 2132 520766 2132 4 la_data_out[111]
+port 357 nsew
+rlabel metal2 s 524262 2200 524262 2200 4 la_data_out[112]
+port 358 nsew
+rlabel metal2 s 527850 2166 527850 2166 4 la_data_out[113]
+port 359 nsew
+rlabel metal2 s 557842 200702 557842 200702 4 la_data_out[114]
+port 360 nsew
+rlabel metal2 s 559406 200260 559406 200260 4 la_data_out[115]
+port 361 nsew
+rlabel metal2 s 538430 1826 538430 1826 4 la_data_out[116]
+port 362 nsew
+rlabel metal2 s 542018 1928 542018 1928 4 la_data_out[117]
+port 363 nsew
+rlabel metal2 s 545514 1894 545514 1894 4 la_data_out[118]
+port 364 nsew
+rlabel metal2 s 558026 191862 558026 191862 4 la_data_out[119]
+port 365 nsew
+rlabel metal2 s 217074 278589 217074 278589 4 la_data_out[11]
+port 366 nsew
+rlabel metal2 s 552690 1911 552690 1911 4 la_data_out[120]
+port 367 nsew
+rlabel metal2 s 556186 1911 556186 1911 4 la_data_out[121]
+port 368 nsew
+rlabel metal2 s 559491 340 559491 340 4 la_data_out[122]
+port 369 nsew
+rlabel metal2 s 563171 340 563171 340 4 la_data_out[123]
+port 370 nsew
+rlabel metal2 s 566858 1894 566858 1894 4 la_data_out[124]
+port 371 nsew
+rlabel metal2 s 570354 1758 570354 1758 4 la_data_out[125]
+port 372 nsew
+rlabel metal2 s 573942 1690 573942 1690 4 la_data_out[126]
+port 373 nsew
+rlabel metal2 s 577438 1894 577438 1894 4 la_data_out[127]
+port 374 nsew
+rlabel metal2 s 216890 279524 216890 279524 4 la_data_out[12]
+port 375 nsew
+rlabel metal2 s 173190 2047 173190 2047 4 la_data_out[13]
+port 376 nsew
+rlabel metal2 s 176686 129530 176686 129530 4 la_data_out[14]
+port 377 nsew
+rlabel metal1 s 216108 272238 216108 272238 4 la_data_out[15]
+port 378 nsew
+rlabel metal2 s 216154 279048 216154 279048 4 la_data_out[16]
+port 379 nsew
+rlabel metal2 s 215970 279184 215970 279184 4 la_data_out[17]
+port 380 nsew
+rlabel metal2 s 190854 2183 190854 2183 4 la_data_out[18]
+port 381 nsew
+rlabel metal2 s 194442 1792 194442 1792 4 la_data_out[19]
+port 382 nsew
+rlabel metal2 s 219006 274384 219006 274384 4 la_data_out[1]
+port 383 nsew
+rlabel metal2 s 197938 1826 197938 1826 4 la_data_out[20]
+port 384 nsew
+rlabel metal2 s 215234 278657 215234 278657 4 la_data_out[21]
+port 385 nsew
+rlabel metal2 s 215050 277977 215050 277977 4 la_data_out[22]
+port 386 nsew
+rlabel metal2 s 214866 277229 214866 277229 4 la_data_out[23]
+port 387 nsew
+rlabel metal2 s 211961 340 211961 340 4 la_data_out[24]
+port 388 nsew
+rlabel metal2 s 215694 2234 215694 2234 4 la_data_out[25]
+port 389 nsew
+rlabel metal2 s 219282 2200 219282 2200 4 la_data_out[26]
+port 390 nsew
+rlabel metal1 s 214268 272238 214268 272238 4 la_data_out[27]
+port 391 nsew
+rlabel metal2 s 195270 258740 195270 258740 4 la_data_out[28]
+port 392 nsew
+rlabel metal1 s 213394 272238 213394 272238 4 la_data_out[29]
+port 393 nsew
+rlabel metal2 s 134182 2047 134182 2047 4 la_data_out[2]
+port 394 nsew
+rlabel metal1 s 213118 272102 213118 272102 4 la_data_out[30]
+port 395 nsew
+rlabel metal2 s 237038 3186 237038 3186 4 la_data_out[31]
+port 396 nsew
+rlabel metal3 s 213003 278732 213003 278732 4 la_data_out[32]
+port 397 nsew
+rlabel metal3 s 212819 277916 212819 277916 4 la_data_out[33]
+port 398 nsew
+rlabel metal2 s 212842 271721 212842 271721 4 la_data_out[34]
+port 399 nsew
+rlabel metal1 s 212796 272238 212796 272238 4 la_data_out[35]
+port 400 nsew
+rlabel metal2 s 254702 3492 254702 3492 4 la_data_out[36]
+port 401 nsew
+rlabel metal2 s 212290 279592 212290 279592 4 la_data_out[37]
+port 402 nsew
+rlabel metal2 s 212106 278997 212106 278997 4 la_data_out[38]
+port 403 nsew
+rlabel metal1 s 211738 272238 211738 272238 4 la_data_out[39]
+port 404 nsew
+rlabel metal2 s 137678 2115 137678 2115 4 la_data_out[3]
+port 405 nsew
+rlabel metal2 s 180550 133858 180550 133858 4 la_data_out[40]
+port 406 nsew
+rlabel metal2 s 211646 268281 211646 268281 4 la_data_out[41]
+port 407 nsew
+rlabel metal2 s 180642 134164 180642 134164 4 la_data_out[42]
+port 408 nsew
+rlabel metal2 s 211278 271596 211278 271596 4 la_data_out[43]
+port 409 nsew
+rlabel metal2 s 211002 275257 211002 275257 4 la_data_out[44]
+port 410 nsew
+rlabel metal2 s 210910 273024 210910 273024 4 la_data_out[45]
+port 411 nsew
+rlabel metal1 s 210220 273258 210220 273258 4 la_data_out[46]
+port 412 nsew
+rlabel metal2 s 210312 273020 210312 273020 4 la_data_out[47]
+port 413 nsew
+rlabel metal1 s 210266 272238 210266 272238 4 la_data_out[48]
+port 414 nsew
+rlabel metal2 s 179262 138091 179262 138091 4 la_data_out[49]
+port 415 nsew
+rlabel metal2 s 140806 20418 140806 20418 4 la_data_out[4]
+port 416 nsew
+rlabel metal2 s 209898 278521 209898 278521 4 la_data_out[50]
+port 417 nsew
+rlabel metal2 s 179170 136901 179170 136901 4 la_data_out[51]
+port 418 nsew
+rlabel metal4 s 179124 138244 179124 138244 4 la_data_out[52]
+port 419 nsew
+rlabel metal2 s 314863 340 314863 340 4 la_data_out[53]
+port 420 nsew
+rlabel metal4 s 176548 138856 176548 138856 4 la_data_out[54]
+port 421 nsew
+rlabel metal3 s 251091 17204 251091 17204 4 la_data_out[55]
+port 422 nsew
+rlabel metal4 s 351900 141236 351900 141236 4 la_data_out[56]
+port 423 nsew
+rlabel metal2 s 329222 2047 329222 2047 4 la_data_out[57]
+port 424 nsew
+rlabel metal2 s 332718 2183 332718 2183 4 la_data_out[58]
+port 425 nsew
+rlabel metal2 s 327934 57477 327934 57477 4 la_data_out[59]
+port 426 nsew
+rlabel metal1 s 218546 272238 218546 272238 4 la_data_out[5]
+port 427 nsew
+rlabel metal2 s 327750 57511 327750 57511 4 la_data_out[60]
+port 428 nsew
+rlabel metal4 s 352084 130900 352084 130900 4 la_data_out[61]
+port 429 nsew
+rlabel metal2 s 346978 1724 346978 1724 4 la_data_out[62]
+port 430 nsew
+rlabel metal2 s 350474 1911 350474 1911 4 la_data_out[63]
+port 431 nsew
+rlabel metal2 s 354062 2098 354062 2098 4 la_data_out[64]
+port 432 nsew
+rlabel metal2 s 540178 89403 540178 89403 4 la_data_out[65]
+port 433 nsew
+rlabel metal2 s 540270 89505 540270 89505 4 la_data_out[66]
+port 434 nsew
+rlabel metal2 s 364642 3968 364642 3968 4 la_data_out[67]
+port 435 nsew
+rlabel metal2 s 368230 1894 368230 1894 4 la_data_out[68]
+port 436 nsew
+rlabel metal2 s 371726 1928 371726 1928 4 la_data_out[69]
+port 437 nsew
+rlabel metal2 s 217580 272340 217580 272340 4 la_data_out[6]
+port 438 nsew
+rlabel metal3 s 540584 91868 540584 91868 4 la_data_out[70]
+port 439 nsew
+rlabel metal1 s 539994 91698 539994 91698 4 la_data_out[71]
+port 440 nsew
+rlabel metal3 s 540216 92412 540216 92412 4 la_data_out[72]
+port 441 nsew
+rlabel metal2 s 385986 3288 385986 3288 4 la_data_out[73]
+port 442 nsew
+rlabel metal2 s 389482 3322 389482 3322 4 la_data_out[74]
+port 443 nsew
+rlabel metal2 s 393070 4002 393070 4002 4 la_data_out[75]
+port 444 nsew
+rlabel metal3 s 540538 93500 540538 93500 4 la_data_out[76]
+port 445 nsew
+rlabel metal1 s 539626 93738 539626 93738 4 la_data_out[77]
+port 446 nsew
+rlabel metal2 s 403650 2676 403650 2676 4 la_data_out[78]
+port 447 nsew
+rlabel metal2 s 407238 2710 407238 2710 4 la_data_out[79]
+port 448 nsew
+rlabel metal2 s 151846 2098 151846 2098 4 la_data_out[7]
+port 449 nsew
+rlabel metal3 s 540078 94588 540078 94588 4 la_data_out[80]
+port 450 nsew
+rlabel metal2 s 444314 4998 444314 4998 4 la_data_out[81]
+port 451 nsew
+rlabel metal3 s 541412 95132 541412 95132 4 la_data_out[82]
+port 452 nsew
+rlabel metal1 s 539948 95234 539948 95234 4 la_data_out[83]
+port 453 nsew
+rlabel metal3 s 541274 95676 541274 95676 4 la_data_out[84]
+port 454 nsew
+rlabel metal3 s 541458 95948 541458 95948 4 la_data_out[85]
+port 455 nsew
+rlabel metal3 s 540676 96220 540676 96220 4 la_data_out[86]
+port 456 nsew
+rlabel metal3 s 540814 96492 540814 96492 4 la_data_out[87]
+port 457 nsew
+rlabel metal3 s 540722 96764 540722 96764 4 la_data_out[88]
+port 458 nsew
+rlabel metal3 s 540170 97036 540170 97036 4 la_data_out[89]
+port 459 nsew
+rlabel metal2 s 216890 272119 216890 272119 4 la_data_out[8]
+port 460 nsew
+rlabel metal3 s 541366 97308 541366 97308 4 la_data_out[90]
+port 461 nsew
+rlabel metal2 s 449834 1962 449834 1962 4 la_data_out[91]
+port 462 nsew
+rlabel metal3 s 541642 97852 541642 97852 4 la_data_out[92]
+port 463 nsew
+rlabel metal3 s 540538 98124 540538 98124 4 la_data_out[93]
+port 464 nsew
+rlabel metal3 s 541596 98396 541596 98396 4 la_data_out[94]
+port 465 nsew
+rlabel metal3 s 541504 98668 541504 98668 4 la_data_out[95]
+port 466 nsew
+rlabel metal2 s 467498 2166 467498 2166 4 la_data_out[96]
+port 467 nsew
+rlabel metal2 s 448270 243066 448270 243066 4 la_data_out[97]
+port 468 nsew
+rlabel metal2 s 449558 200668 449558 200668 4 la_data_out[98]
+port 469 nsew
+rlabel metal1 s 449282 4046 449282 4046 4 la_data_out[99]
+port 470 nsew
+rlabel metal2 s 158746 20554 158746 20554 4 la_data_out[9]
+port 471 nsew
+rlabel metal2 s 427616 105883 427616 105883 4 p_reset_n
+port 472 nsew
+rlabel metal2 s 447442 417775 447442 417775 4 p_reset_n_rp
+port 473 nsew
+rlabel metal2 s 427800 105815 427800 105815 4 pll_clk_out\[0\]
+port 474 nsew
+rlabel metal2 s 499974 600916 499974 600916 4 pll_ref_clk
+port 475 nsew
+rlabel metal2 s 450011 90100 450011 90100 4 qspim_rst_n
+port 476 nsew
+rlabel metal1 s 522422 580516 522422 580516 4 sflash_di\[0\]
+port 477 nsew
+rlabel metal2 s 522606 580778 522606 580778 4 sflash_di\[1\]
+port 478 nsew
+rlabel metal2 s 522790 581764 522790 581764 4 sflash_di\[2\]
+port 479 nsew
+rlabel metal2 s 522974 581696 522974 581696 4 sflash_di\[3\]
+port 480 nsew
+rlabel metal2 s 521686 581730 521686 581730 4 sflash_do\[0\]
+port 481 nsew
+rlabel metal2 s 521870 581594 521870 581594 4 sflash_do\[1\]
+port 482 nsew
+rlabel metal1 s 522054 580482 522054 580482 4 sflash_do\[2\]
+port 483 nsew
+rlabel metal2 s 522238 581628 522238 581628 4 sflash_do\[3\]
+port 484 nsew
+rlabel metal2 s 519938 579717 519938 579717 4 sflash_oen\[0\]
+port 485 nsew
+rlabel metal1 s 519938 579836 519938 579836 4 sflash_oen\[1\]
+port 486 nsew
+rlabel metal2 s 520398 579860 520398 579860 4 sflash_oen\[2\]
+port 487 nsew
+rlabel metal1 s 520582 580448 520582 580448 4 sflash_oen\[3\]
+port 488 nsew
+rlabel metal2 s 521502 581526 521502 581526 4 sflash_sck
+port 489 nsew
+rlabel metal2 s 447166 439841 447166 439841 4 soft_irq
+port 490 nsew
+rlabel metal2 s 520766 581560 520766 581560 4 spi_csn\[0\]
+port 491 nsew
+rlabel metal2 s 520950 581662 520950 581662 4 spi_csn\[1\]
+port 492 nsew
+rlabel metal2 s 521134 579948 521134 579948 4 spi_csn\[2\]
+port 493 nsew
+rlabel metal2 s 521318 579622 521318 579622 4 spi_csn\[3\]
+port 494 nsew
+rlabel metal3 s 554752 224876 554752 224876 4 sspim_rst_n
+port 495 nsew
+rlabel metal2 s 458390 390398 458390 390398 4 sspim_sck
+port 496 nsew
+rlabel metal2 s 459494 390466 459494 390466 4 sspim_si
+port 497 nsew
+rlabel metal2 s 459310 390432 459310 390432 4 sspim_so
+port 498 nsew
+rlabel metal2 s 459126 391112 459126 391112 4 sspim_ssn\[0\]
+port 499 nsew
+rlabel metal2 s 458942 391214 458942 391214 4 sspim_ssn\[1\]
+port 500 nsew
+rlabel metal2 s 458758 391146 458758 391146 4 sspim_ssn\[2\]
+port 501 nsew
+rlabel metal2 s 458574 389072 458574 389072 4 sspim_ssn\[3\]
+port 502 nsew
+rlabel metal3 s 431702 80716 431702 80716 4 sspis_sck
+port 503 nsew
+rlabel metal2 s 461150 392472 461150 392472 4 sspis_si
+port 504 nsew
+rlabel metal2 s 461058 392269 461058 392269 4 sspis_so
+port 505 nsew
+rlabel metal2 s 432446 81141 432446 81141 4 sspis_ssn
+port 506 nsew
+rlabel metal2 s 447442 408901 447442 408901 4 strap_sticky\[0\]
+port 507 nsew
+rlabel metal2 s 432998 406181 432998 406181 4 strap_sticky\[10\]
+port 508 nsew
+rlabel metal2 s 432814 405297 432814 405297 4 strap_sticky\[11\]
+port 509 nsew
+rlabel metal2 s 433182 405195 433182 405195 4 strap_sticky\[12\]
+port 510 nsew
+rlabel metal3 s 433274 405093 433274 405093 4 strap_sticky\[13\]
+port 511 nsew
+rlabel metal2 s 433090 404991 433090 404991 4 strap_sticky\[14\]
+port 512 nsew
+rlabel metal2 s 432998 404889 432998 404889 4 strap_sticky\[15\]
+port 513 nsew
+rlabel metal2 s 432906 404005 432906 404005 4 strap_sticky\[16\]
+port 514 nsew
+rlabel metal2 s 433182 403835 433182 403835 4 strap_sticky\[17\]
+port 515 nsew
+rlabel metal2 s 433274 403767 433274 403767 4 strap_sticky\[18\]
+port 516 nsew
+rlabel metal2 s 433090 403665 433090 403665 4 strap_sticky\[19\]
+port 517 nsew
+rlabel metal2 s 433274 408187 433274 408187 4 strap_sticky\[1\]
+port 518 nsew
+rlabel metal2 s 433274 403393 433274 403393 4 strap_sticky\[20\]
+port 519 nsew
+rlabel metal2 s 433090 402611 433090 402611 4 strap_sticky\[21\]
+port 520 nsew
+rlabel metal2 s 433182 402509 433182 402509 4 strap_sticky\[22\]
+port 521 nsew
+rlabel metal2 s 433274 402441 433274 402441 4 strap_sticky\[23\]
+port 522 nsew
+rlabel metal2 s 433274 402169 433274 402169 4 strap_sticky\[24\]
+port 523 nsew
+rlabel metal2 s 432814 402135 432814 402135 4 strap_sticky\[25\]
+port 524 nsew
+rlabel metal2 s 432906 401217 432906 401217 4 strap_sticky\[26\]
+port 525 nsew
+rlabel metal2 s 433274 401183 433274 401183 4 strap_sticky\[27\]
+port 526 nsew
+rlabel metal2 s 433182 401081 433182 401081 4 strap_sticky\[28\]
+port 527 nsew
+rlabel metal2 s 433090 400877 433090 400877 4 strap_sticky\[29\]
+port 528 nsew
+rlabel metal2 s 433182 407983 433182 407983 4 strap_sticky\[2\]
+port 529 nsew
+rlabel metal2 s 432998 400707 432998 400707 4 strap_sticky\[30\]
+port 530 nsew
+rlabel metal2 s 433182 399823 433182 399823 4 strap_sticky\[31\]
+port 531 nsew
+rlabel metal3 s 433274 407813 433274 407813 4 strap_sticky\[3\]
+port 532 nsew
+rlabel metal2 s 433090 407745 433090 407745 4 strap_sticky\[4\]
+port 533 nsew
+rlabel metal2 s 432906 407507 432906 407507 4 strap_sticky\[5\]
+port 534 nsew
+rlabel metal2 s 432814 406793 432814 406793 4 strap_sticky\[6\]
+port 535 nsew
+rlabel metal2 s 433274 406623 433274 406623 4 strap_sticky\[7\]
+port 536 nsew
+rlabel metal2 s 432446 406555 432446 406555 4 strap_sticky\[8\]
+port 537 nsew
+rlabel metal2 s 433274 406283 433274 406283 4 strap_sticky\[9\]
+port 538 nsew
+rlabel metal1 s 422970 126378 422970 126378 4 strap_sticky_rp\[0\]
+port 539 nsew
+rlabel metal2 s 418968 105883 418968 105883 4 strap_sticky_rp\[10\]
+port 540 nsew
+rlabel metal2 s 418784 105883 418784 105883 4 strap_sticky_rp\[11\]
+port 541 nsew
+rlabel metal2 s 418600 105883 418600 105883 4 strap_sticky_rp\[12\]
+port 542 nsew
+rlabel metal2 s 418416 105815 418416 105815 4 strap_sticky_rp\[13\]
+port 543 nsew
+rlabel metal2 s 418232 105815 418232 105815 4 strap_sticky_rp\[14\]
+port 544 nsew
+rlabel metal2 s 418048 105815 418048 105815 4 strap_sticky_rp\[15\]
+port 545 nsew
+rlabel metal2 s 417864 105883 417864 105883 4 strap_sticky_rp\[16\]
+port 546 nsew
+rlabel metal2 s 417680 105883 417680 105883 4 strap_sticky_rp\[17\]
+port 547 nsew
+rlabel metal2 s 417496 105883 417496 105883 4 strap_sticky_rp\[18\]
+port 548 nsew
+rlabel metal2 s 417312 105883 417312 105883 4 strap_sticky_rp\[19\]
+port 549 nsew
+rlabel metal2 s 420624 105883 420624 105883 4 strap_sticky_rp\[1\]
+port 550 nsew
+rlabel metal2 s 417128 105883 417128 105883 4 strap_sticky_rp\[20\]
+port 551 nsew
+rlabel metal2 s 416944 105815 416944 105815 4 strap_sticky_rp\[21\]
+port 552 nsew
+rlabel metal2 s 416760 105883 416760 105883 4 strap_sticky_rp\[22\]
+port 553 nsew
+rlabel metal2 s 416576 105815 416576 105815 4 strap_sticky_rp\[23\]
+port 554 nsew
+rlabel metal2 s 416392 105815 416392 105815 4 strap_sticky_rp\[24\]
+port 555 nsew
+rlabel metal2 s 416208 105883 416208 105883 4 strap_sticky_rp\[25\]
+port 556 nsew
+rlabel metal2 s 416024 105883 416024 105883 4 strap_sticky_rp\[26\]
+port 557 nsew
+rlabel metal2 s 415840 105883 415840 105883 4 strap_sticky_rp\[27\]
+port 558 nsew
+rlabel metal2 s 415656 105815 415656 105815 4 strap_sticky_rp\[28\]
+port 559 nsew
+rlabel metal2 s 415472 105815 415472 105815 4 strap_sticky_rp\[29\]
+port 560 nsew
+rlabel metal2 s 420440 105815 420440 105815 4 strap_sticky_rp\[2\]
+port 561 nsew
+rlabel metal2 s 415288 105815 415288 105815 4 strap_sticky_rp\[30\]
+port 562 nsew
+rlabel metal2 s 415074 105740 415074 105740 4 strap_sticky_rp\[31\]
+port 563 nsew
+rlabel metal2 s 420256 105815 420256 105815 4 strap_sticky_rp\[3\]
+port 564 nsew
+rlabel metal2 s 420072 105815 420072 105815 4 strap_sticky_rp\[4\]
+port 565 nsew
+rlabel metal2 s 419888 105815 419888 105815 4 strap_sticky_rp\[5\]
+port 566 nsew
+rlabel metal2 s 419704 105815 419704 105815 4 strap_sticky_rp\[6\]
+port 567 nsew
+rlabel metal2 s 419520 105815 419520 105815 4 strap_sticky_rp\[7\]
+port 568 nsew
+rlabel metal2 s 419336 105883 419336 105883 4 strap_sticky_rp\[8\]
+port 569 nsew
+rlabel metal2 s 419152 105883 419152 105883 4 strap_sticky_rp\[9\]
+port 570 nsew
+rlabel metal2 s 447258 409241 447258 409241 4 strap_uartm\[0\]
+port 571 nsew
+rlabel metal2 s 447166 409003 447166 409003 4 strap_uartm\[1\]
+port 572 nsew
+rlabel metal2 s 422694 129074 422694 129074 4 strap_uartm_rp\[0\]
+port 573 nsew
+rlabel metal2 s 422510 129108 422510 129108 4 strap_uartm_rp\[1\]
+port 574 nsew
+rlabel metal2 s 427064 105815 427064 105815 4 system_strap\[0\]
+port 575 nsew
+rlabel metal2 s 425224 105815 425224 105815 4 system_strap\[10\]
+port 576 nsew
+rlabel metal2 s 424994 106471 424994 106471 4 system_strap\[11\]
+port 577 nsew
+rlabel metal2 s 424856 105815 424856 105815 4 system_strap\[12\]
+port 578 nsew
+rlabel metal2 s 424672 105815 424672 105815 4 system_strap\[13\]
+port 579 nsew
+rlabel metal2 s 424488 105815 424488 105815 4 system_strap\[14\]
+port 580 nsew
+rlabel metal2 s 424304 105883 424304 105883 4 system_strap\[15\]
+port 581 nsew
+rlabel metal2 s 424120 105883 424120 105883 4 system_strap\[16\]
+port 582 nsew
+rlabel metal2 s 423936 105815 423936 105815 4 system_strap\[17\]
+port 583 nsew
+rlabel metal2 s 423752 105815 423752 105815 4 system_strap\[18\]
+port 584 nsew
+rlabel metal2 s 423568 105883 423568 105883 4 system_strap\[19\]
+port 585 nsew
+rlabel metal2 s 426880 105815 426880 105815 4 system_strap\[1\]
+port 586 nsew
+rlabel metal2 s 423384 105815 423384 105815 4 system_strap\[20\]
+port 587 nsew
+rlabel metal2 s 423200 105815 423200 105815 4 system_strap\[21\]
+port 588 nsew
+rlabel metal2 s 423016 105815 423016 105815 4 system_strap\[22\]
+port 589 nsew
+rlabel metal2 s 422832 105815 422832 105815 4 system_strap\[23\]
+port 590 nsew
+rlabel metal2 s 422648 105815 422648 105815 4 system_strap\[24\]
+port 591 nsew
+rlabel metal2 s 422464 105815 422464 105815 4 system_strap\[25\]
+port 592 nsew
+rlabel metal2 s 423798 119146 423798 119146 4 system_strap\[26\]
+port 593 nsew
+rlabel metal1 s 423154 126514 423154 126514 4 system_strap\[27\]
+port 594 nsew
+rlabel metal1 s 422970 126446 422970 126446 4 system_strap\[28\]
+port 595 nsew
+rlabel metal2 s 423246 119486 423246 119486 4 system_strap\[29\]
+port 596 nsew
+rlabel metal2 s 426696 105815 426696 105815 4 system_strap\[2\]
+port 597 nsew
+rlabel metal2 s 423062 129040 423062 129040 4 system_strap\[30\]
+port 598 nsew
+rlabel metal1 s 423154 125834 423154 125834 4 system_strap\[31\]
+port 599 nsew
+rlabel metal2 s 426512 105815 426512 105815 4 system_strap\[3\]
+port 600 nsew
+rlabel metal2 s 426328 105883 426328 105883 4 system_strap\[4\]
+port 601 nsew
+rlabel metal2 s 426144 105883 426144 105883 4 system_strap\[5\]
+port 602 nsew
+rlabel metal2 s 425960 105883 425960 105883 4 system_strap\[6\]
+port 603 nsew
+rlabel metal2 s 425776 105815 425776 105815 4 system_strap\[7\]
+port 604 nsew
+rlabel metal2 s 425592 105815 425592 105815 4 system_strap\[8\]
+port 605 nsew
+rlabel metal2 s 425408 105815 425408 105815 4 system_strap\[9\]
+port 606 nsew
+rlabel metal2 s 447258 417707 447258 417707 4 system_strap_rp\[0\]
+port 607 nsew
+rlabel metal2 s 447258 414953 447258 414953 4 system_strap_rp\[10\]
+port 608 nsew
+rlabel metal3 s 447166 414885 447166 414885 4 system_strap_rp\[11\]
+port 609 nsew
+rlabel metal2 s 447166 414647 447166 414647 4 system_strap_rp\[12\]
+port 610 nsew
+rlabel metal2 s 447442 414647 447442 414647 4 system_strap_rp\[13\]
+port 611 nsew
+rlabel metal2 s 447350 414443 447350 414443 4 system_strap_rp\[14\]
+port 612 nsew
+rlabel metal2 s 447258 413559 447258 413559 4 system_strap_rp\[15\]
+port 613 nsew
+rlabel metal2 s 447166 413457 447166 413457 4 system_strap_rp\[16\]
+port 614 nsew
+rlabel metal3 s 447166 413253 447166 413253 4 system_strap_rp\[17\]
+port 615 nsew
+rlabel metal2 s 447350 413219 447350 413219 4 system_strap_rp\[18\]
+port 616 nsew
+rlabel metal2 s 447442 413117 447442 413117 4 system_strap_rp\[19\]
+port 617 nsew
+rlabel metal2 s 447166 417639 447166 417639 4 system_strap_rp\[1\]
+port 618 nsew
+rlabel metal2 s 447258 412233 447258 412233 4 system_strap_rp\[20\]
+port 619 nsew
+rlabel metal3 s 447166 412131 447166 412131 4 system_strap_rp\[21\]
+port 620 nsew
+rlabel metal3 s 447166 411893 447166 411893 4 system_strap_rp\[22\]
+port 621 nsew
+rlabel metal2 s 447442 411893 447442 411893 4 system_strap_rp\[23\]
+port 622 nsew
+rlabel metal2 s 447350 411655 447350 411655 4 system_strap_rp\[24\]
+port 623 nsew
+rlabel metal2 s 447258 410941 447258 410941 4 system_strap_rp\[25\]
+port 624 nsew
+rlabel metal3 s 447166 410771 447166 410771 4 system_strap_rp\[26\]
+port 625 nsew
+rlabel metal2 s 447258 410601 447258 410601 4 system_strap_rp\[27\]
+port 626 nsew
+rlabel metal2 s 447166 410431 447166 410431 4 system_strap_rp\[28\]
+port 627 nsew
+rlabel metal2 s 447350 410261 447350 410261 4 system_strap_rp\[29\]
+port 628 nsew
+rlabel metal2 s 447350 417469 447350 417469 4 system_strap_rp\[2\]
+port 629 nsew
+rlabel metal2 s 447166 409547 447166 409547 4 system_strap_rp\[30\]
+port 630 nsew
+rlabel metal2 s 447350 409343 447350 409343 4 system_strap_rp\[31\]
+port 631 nsew
+rlabel metal2 s 447166 417265 447166 417265 4 system_strap_rp\[3\]
+port 632 nsew
+rlabel metal2 s 447534 417265 447534 417265 4 system_strap_rp\[4\]
+port 633 nsew
+rlabel metal2 s 447258 416347 447258 416347 4 system_strap_rp\[5\]
+port 634 nsew
+rlabel metal3 s 447166 416245 447166 416245 4 system_strap_rp\[6\]
+port 635 nsew
+rlabel metal2 s 447350 416143 447350 416143 4 system_strap_rp\[7\]
+port 636 nsew
+rlabel metal2 s 447166 415905 447166 415905 4 system_strap_rp\[8\]
+port 637 nsew
+rlabel metal2 s 447258 415735 447258 415735 4 system_strap_rp\[9\]
+port 638 nsew
+rlabel metal2 s 216062 272170 216062 272170 4 u_riscv_top.cfg_ccska_riscv_core0\[0\]
+port 639 nsew
+rlabel metal2 s 215970 271103 215970 271103 4 u_riscv_top.cfg_ccska_riscv_core0\[1\]
+port 640 nsew
+rlabel metal2 s 367310 264197 367310 264197 4 u_riscv_top.cfg_ccska_riscv_core0\[2\]
+port 641 nsew
+rlabel metal3 s 369020 263364 369020 263364 4 u_riscv_top.cfg_ccska_riscv_core0\[3\]
+port 642 nsew
+rlabel metal2 s 367218 263279 367218 263279 4 u_riscv_top.cfg_ccska_riscv_core1\[0\]
+port 643 nsew
+rlabel metal2 s 367126 263177 367126 263177 4 u_riscv_top.cfg_ccska_riscv_core1\[1\]
+port 644 nsew
+rlabel metal2 s 367402 264095 367402 264095 4 u_riscv_top.cfg_ccska_riscv_core1\[2\]
+port 645 nsew
+rlabel metal2 s 367494 264027 367494 264027 4 u_riscv_top.cfg_ccska_riscv_core1\[3\]
+port 646 nsew
+rlabel metal3 s 368928 262004 368928 262004 4 u_riscv_top.cfg_ccska_riscv_core2\[0\]
+port 647 nsew
+rlabel metal2 s 194074 267172 194074 267172 4 u_riscv_top.cfg_ccska_riscv_core2\[1\]
+port 648 nsew
+rlabel metal2 s 367218 261817 367218 261817 4 u_riscv_top.cfg_ccska_riscv_core2\[2\]
+port 649 nsew
+rlabel metal2 s 367126 261647 367126 261647 4 u_riscv_top.cfg_ccska_riscv_core2\[3\]
+port 650 nsew
+rlabel metal2 s 238694 398837 238694 398837 4 u_riscv_top.cfg_ccska_riscv_core3\[0\]
+port 651 nsew
+rlabel metal2 s 367678 263245 367678 263245 4 u_riscv_top.cfg_ccska_riscv_core3\[1\]
+port 652 nsew
+rlabel metal2 s 238418 508929 238418 508929 4 u_riscv_top.cfg_ccska_riscv_core3\[2\]
+port 653 nsew
+rlabel metal2 s 367310 261477 367310 261477 4 u_riscv_top.cfg_ccska_riscv_core3\[3\]
+port 654 nsew
+rlabel metal2 s 230322 280653 230322 280653 4 u_riscv_top.cfg_ccska_riscv_icon\[0\]
+port 655 nsew
+rlabel metal2 s 367494 279531 367494 279531 4 u_riscv_top.cfg_ccska_riscv_icon\[1\]
+port 656 nsew
+rlabel metal2 s 367218 280177 367218 280177 4 u_riscv_top.cfg_ccska_riscv_icon\[2\]
+port 657 nsew
+rlabel metal2 s 367126 279769 367126 279769 4 u_riscv_top.cfg_ccska_riscv_icon\[3\]
+port 658 nsew
+rlabel metal3 s 352628 131036 352628 131036 4 u_riscv_top.cfg_ccska_riscv_intf\[0\]
+port 659 nsew
+rlabel metal3 s 352076 130764 352076 130764 4 u_riscv_top.cfg_ccska_riscv_intf\[1\]
+port 660 nsew
+rlabel metal3 s 352030 130492 352030 130492 4 u_riscv_top.cfg_ccska_riscv_intf\[2\]
+port 661 nsew
+rlabel metal3 s 351900 129933 351900 129933 4 u_riscv_top.cfg_ccska_riscv_intf\[3\]
+port 662 nsew
+rlabel metal2 s 249550 259342 249550 259342 4 u_riscv_top.cfg_dcache_force_flush
+port 663 nsew
+rlabel metal3 s 352674 140964 352674 140964 4 u_riscv_top.cfg_wcska_riscv_intf\[0\]
+port 664 nsew
+rlabel metal3 s 352720 140692 352720 140692 4 u_riscv_top.cfg_wcska_riscv_intf\[1\]
+port 665 nsew
+rlabel metal3 s 352674 140420 352674 140420 4 u_riscv_top.cfg_wcska_riscv_intf\[2\]
+port 666 nsew
+rlabel metal3 s 352628 140148 352628 140148 4 u_riscv_top.cfg_wcska_riscv_intf\[3\]
+port 667 nsew
+rlabel metal3 s 124100 320212 124100 320212 4 u_riscv_top.core0_clk
+port 668 nsew
+rlabel metal3 s 123686 393244 123686 393244 4 u_riscv_top.core0_debug\[0\]
+port 669 nsew
+rlabel metal3 s 124146 390524 124146 390524 4 u_riscv_top.core0_debug\[10\]
+port 670 nsew
+rlabel metal3 s 123640 390252 123640 390252 4 u_riscv_top.core0_debug\[11\]
+port 671 nsew
+rlabel metal3 s 124192 389980 124192 389980 4 u_riscv_top.core0_debug\[12\]
+port 672 nsew
+rlabel metal3 s 124192 389708 124192 389708 4 u_riscv_top.core0_debug\[13\]
+port 673 nsew
+rlabel metal3 s 123732 389436 123732 389436 4 u_riscv_top.core0_debug\[14\]
+port 674 nsew
+rlabel metal3 s 123824 389164 123824 389164 4 u_riscv_top.core0_debug\[15\]
+port 675 nsew
+rlabel metal3 s 124146 388892 124146 388892 4 u_riscv_top.core0_debug\[16\]
+port 676 nsew
+rlabel metal3 s 124192 388620 124192 388620 4 u_riscv_top.core0_debug\[17\]
+port 677 nsew
+rlabel metal3 s 124100 388348 124100 388348 4 u_riscv_top.core0_debug\[18\]
+port 678 nsew
+rlabel metal3 s 124192 388076 124192 388076 4 u_riscv_top.core0_debug\[19\]
+port 679 nsew
+rlabel metal3 s 124192 392972 124192 392972 4 u_riscv_top.core0_debug\[1\]
+port 680 nsew
+rlabel metal3 s 124146 387804 124146 387804 4 u_riscv_top.core0_debug\[20\]
+port 681 nsew
+rlabel metal3 s 124192 387532 124192 387532 4 u_riscv_top.core0_debug\[21\]
+port 682 nsew
+rlabel metal3 s 124100 387260 124100 387260 4 u_riscv_top.core0_debug\[22\]
+port 683 nsew
+rlabel metal3 s 124192 386988 124192 386988 4 u_riscv_top.core0_debug\[23\]
+port 684 nsew
+rlabel metal3 s 123732 386716 123732 386716 4 u_riscv_top.core0_debug\[24\]
+port 685 nsew
+rlabel metal3 s 123824 386444 123824 386444 4 u_riscv_top.core0_debug\[25\]
+port 686 nsew
+rlabel metal3 s 123640 386172 123640 386172 4 u_riscv_top.core0_debug\[26\]
+port 687 nsew
+rlabel metal3 s 124192 385900 124192 385900 4 u_riscv_top.core0_debug\[27\]
+port 688 nsew
+rlabel metal3 s 124146 385628 124146 385628 4 u_riscv_top.core0_debug\[28\]
+port 689 nsew
+rlabel metal3 s 124192 385356 124192 385356 4 u_riscv_top.core0_debug\[29\]
+port 690 nsew
+rlabel metal3 s 124100 392700 124100 392700 4 u_riscv_top.core0_debug\[2\]
+port 691 nsew
+rlabel metal3 s 123732 385084 123732 385084 4 u_riscv_top.core0_debug\[30\]
+port 692 nsew
+rlabel metal3 s 123640 384812 123640 384812 4 u_riscv_top.core0_debug\[31\]
+port 693 nsew
+rlabel metal3 s 124192 384540 124192 384540 4 u_riscv_top.core0_debug\[32\]
+port 694 nsew
+rlabel metal3 s 124100 384268 124100 384268 4 u_riscv_top.core0_debug\[33\]
+port 695 nsew
+rlabel metal3 s 124146 383996 124146 383996 4 u_riscv_top.core0_debug\[34\]
+port 696 nsew
+rlabel metal3 s 123778 383724 123778 383724 4 u_riscv_top.core0_debug\[35\]
+port 697 nsew
+rlabel metal3 s 124100 383452 124100 383452 4 u_riscv_top.core0_debug\[36\]
+port 698 nsew
+rlabel metal3 s 124146 383180 124146 383180 4 u_riscv_top.core0_debug\[37\]
+port 699 nsew
+rlabel metal3 s 124192 382908 124192 382908 4 u_riscv_top.core0_debug\[38\]
+port 700 nsew
+rlabel metal3 s 124054 382636 124054 382636 4 u_riscv_top.core0_debug\[39\]
+port 701 nsew
+rlabel metal3 s 124192 392428 124192 392428 4 u_riscv_top.core0_debug\[3\]
+port 702 nsew
+rlabel metal3 s 123732 382364 123732 382364 4 u_riscv_top.core0_debug\[40\]
+port 703 nsew
+rlabel metal3 s 124192 382092 124192 382092 4 u_riscv_top.core0_debug\[41\]
+port 704 nsew
+rlabel metal3 s 124100 381820 124100 381820 4 u_riscv_top.core0_debug\[42\]
+port 705 nsew
+rlabel metal3 s 124146 381548 124146 381548 4 u_riscv_top.core0_debug\[43\]
+port 706 nsew
+rlabel metal3 s 123640 381276 123640 381276 4 u_riscv_top.core0_debug\[44\]
+port 707 nsew
+rlabel metal3 s 124192 381004 124192 381004 4 u_riscv_top.core0_debug\[45\]
+port 708 nsew
+rlabel metal3 s 124146 380732 124146 380732 4 u_riscv_top.core0_debug\[46\]
+port 709 nsew
+rlabel metal3 s 124192 380460 124192 380460 4 u_riscv_top.core0_debug\[47\]
+port 710 nsew
+rlabel metal3 s 124192 380188 124192 380188 4 u_riscv_top.core0_debug\[48\]
+port 711 nsew
+rlabel metal3 s 123732 392156 123732 392156 4 u_riscv_top.core0_debug\[4\]
+port 712 nsew
+rlabel metal3 s 123824 391884 123824 391884 4 u_riscv_top.core0_debug\[5\]
+port 713 nsew
+rlabel metal3 s 124146 391612 124146 391612 4 u_riscv_top.core0_debug\[6\]
+port 714 nsew
+rlabel metal3 s 124192 391340 124192 391340 4 u_riscv_top.core0_debug\[7\]
+port 715 nsew
+rlabel metal3 s 124100 391068 124100 391068 4 u_riscv_top.core0_debug\[8\]
+port 716 nsew
+rlabel metal3 s 124054 390796 124054 390796 4 u_riscv_top.core0_debug\[9\]
+port 717 nsew
+rlabel metal3 s 124100 359924 124100 359924 4 u_riscv_top.core0_dmem_addr\[0\]
+port 718 nsew
+rlabel metal3 s 124146 357204 124146 357204 4 u_riscv_top.core0_dmem_addr\[10\]
+port 719 nsew
+rlabel metal3 s 124192 356932 124192 356932 4 u_riscv_top.core0_dmem_addr\[11\]
+port 720 nsew
+rlabel metal3 s 124146 356660 124146 356660 4 u_riscv_top.core0_dmem_addr\[12\]
+port 721 nsew
+rlabel metal3 s 124192 356388 124192 356388 4 u_riscv_top.core0_dmem_addr\[13\]
+port 722 nsew
+rlabel metal3 s 123732 356116 123732 356116 4 u_riscv_top.core0_dmem_addr\[14\]
+port 723 nsew
+rlabel metal3 s 124192 355844 124192 355844 4 u_riscv_top.core0_dmem_addr\[15\]
+port 724 nsew
+rlabel metal3 s 124146 355572 124146 355572 4 u_riscv_top.core0_dmem_addr\[16\]
+port 725 nsew
+rlabel metal3 s 124100 355300 124100 355300 4 u_riscv_top.core0_dmem_addr\[17\]
+port 726 nsew
+rlabel metal3 s 124192 355028 124192 355028 4 u_riscv_top.core0_dmem_addr\[18\]
+port 727 nsew
+rlabel metal3 s 123686 354756 123686 354756 4 u_riscv_top.core0_dmem_addr\[19\]
+port 728 nsew
+rlabel metal3 s 124192 359652 124192 359652 4 u_riscv_top.core0_dmem_addr\[1\]
+port 729 nsew
+rlabel metal3 s 124100 354484 124100 354484 4 u_riscv_top.core0_dmem_addr\[20\]
+port 730 nsew
+rlabel metal3 s 124192 354212 124192 354212 4 u_riscv_top.core0_dmem_addr\[21\]
+port 731 nsew
+rlabel metal3 s 124146 353940 124146 353940 4 u_riscv_top.core0_dmem_addr\[22\]
+port 732 nsew
+rlabel metal3 s 123640 353668 123640 353668 4 u_riscv_top.core0_dmem_addr\[23\]
+port 733 nsew
+rlabel metal3 s 124054 353396 124054 353396 4 u_riscv_top.core0_dmem_addr\[24\]
+port 734 nsew
+rlabel metal3 s 124146 353124 124146 353124 4 u_riscv_top.core0_dmem_addr\[25\]
+port 735 nsew
+rlabel metal3 s 124054 352852 124054 352852 4 u_riscv_top.core0_dmem_addr\[26\]
+port 736 nsew
+rlabel metal3 s 124192 352580 124192 352580 4 u_riscv_top.core0_dmem_addr\[27\]
+port 737 nsew
+rlabel metal3 s 123640 352308 123640 352308 4 u_riscv_top.core0_dmem_addr\[28\]
+port 738 nsew
+rlabel metal3 s 124100 352036 124100 352036 4 u_riscv_top.core0_dmem_addr\[29\]
+port 739 nsew
+rlabel metal3 s 124146 359380 124146 359380 4 u_riscv_top.core0_dmem_addr\[2\]
+port 740 nsew
+rlabel metal3 s 124192 351764 124192 351764 4 u_riscv_top.core0_dmem_addr\[30\]
+port 741 nsew
+rlabel metal3 s 124146 351492 124146 351492 4 u_riscv_top.core0_dmem_addr\[31\]
+port 742 nsew
+rlabel metal3 s 123640 359108 123640 359108 4 u_riscv_top.core0_dmem_addr\[3\]
+port 743 nsew
+rlabel metal3 s 123778 358836 123778 358836 4 u_riscv_top.core0_dmem_addr\[4\]
+port 744 nsew
+rlabel metal3 s 124146 358564 124146 358564 4 u_riscv_top.core0_dmem_addr\[5\]
+port 745 nsew
+rlabel metal3 s 124192 358292 124192 358292 4 u_riscv_top.core0_dmem_addr\[6\]
+port 746 nsew
+rlabel metal3 s 124192 358020 124192 358020 4 u_riscv_top.core0_dmem_addr\[7\]
+port 747 nsew
+rlabel metal3 s 124146 357748 124146 357748 4 u_riscv_top.core0_dmem_addr\[8\]
+port 748 nsew
+rlabel metal3 s 124100 357476 124100 357476 4 u_riscv_top.core0_dmem_addr\[9\]
+port 749 nsew
+rlabel metal3 s 123732 350676 123732 350676 4 u_riscv_top.core0_dmem_cmd
+port 750 nsew
+rlabel metal3 s 124146 377332 124146 377332 4 u_riscv_top.core0_dmem_rdata\[0\]
+port 751 nsew
+rlabel metal3 s 124146 374612 124146 374612 4 u_riscv_top.core0_dmem_rdata\[10\]
+port 752 nsew
+rlabel metal3 s 124192 374340 124192 374340 4 u_riscv_top.core0_dmem_rdata\[11\]
+port 753 nsew
+rlabel metal3 s 124100 374068 124100 374068 4 u_riscv_top.core0_dmem_rdata\[12\]
+port 754 nsew
+rlabel metal3 s 124100 373796 124100 373796 4 u_riscv_top.core0_dmem_rdata\[13\]
+port 755 nsew
+rlabel metal3 s 124192 373524 124192 373524 4 u_riscv_top.core0_dmem_rdata\[14\]
+port 756 nsew
+rlabel metal3 s 124146 373252 124146 373252 4 u_riscv_top.core0_dmem_rdata\[15\]
+port 757 nsew
+rlabel metal3 s 123640 372980 123640 372980 4 u_riscv_top.core0_dmem_rdata\[16\]
+port 758 nsew
+rlabel metal3 s 124054 372708 124054 372708 4 u_riscv_top.core0_dmem_rdata\[17\]
+port 759 nsew
+rlabel metal3 s 124146 372436 124146 372436 4 u_riscv_top.core0_dmem_rdata\[18\]
+port 760 nsew
+rlabel metal3 s 124192 372164 124192 372164 4 u_riscv_top.core0_dmem_rdata\[19\]
+port 761 nsew
+rlabel metal3 s 124100 377060 124100 377060 4 u_riscv_top.core0_dmem_rdata\[1\]
+port 762 nsew
+rlabel metal3 s 124192 371892 124192 371892 4 u_riscv_top.core0_dmem_rdata\[20\]
+port 763 nsew
+rlabel metal3 s 124146 371620 124146 371620 4 u_riscv_top.core0_dmem_rdata\[21\]
+port 764 nsew
+rlabel metal3 s 123732 371348 123732 371348 4 u_riscv_top.core0_dmem_rdata\[22\]
+port 765 nsew
+rlabel metal3 s 123732 371076 123732 371076 4 u_riscv_top.core0_dmem_rdata\[23\]
+port 766 nsew
+rlabel metal3 s 124146 370804 124146 370804 4 u_riscv_top.core0_dmem_rdata\[24\]
+port 767 nsew
+rlabel metal3 s 124192 370532 124192 370532 4 u_riscv_top.core0_dmem_rdata\[25\]
+port 768 nsew
+rlabel metal3 s 123640 370260 123640 370260 4 u_riscv_top.core0_dmem_rdata\[26\]
+port 769 nsew
+rlabel metal3 s 124100 369988 124100 369988 4 u_riscv_top.core0_dmem_rdata\[27\]
+port 770 nsew
+rlabel metal3 s 124100 369716 124100 369716 4 u_riscv_top.core0_dmem_rdata\[28\]
+port 771 nsew
+rlabel metal3 s 124192 369444 124192 369444 4 u_riscv_top.core0_dmem_rdata\[29\]
+port 772 nsew
+rlabel metal3 s 123824 376788 123824 376788 4 u_riscv_top.core0_dmem_rdata\[2\]
+port 773 nsew
+rlabel metal3 s 124146 369172 124146 369172 4 u_riscv_top.core0_dmem_rdata\[30\]
+port 774 nsew
+rlabel metal3 s 123594 368900 123594 368900 4 u_riscv_top.core0_dmem_rdata\[31\]
+port 775 nsew
+rlabel metal3 s 124192 376516 124192 376516 4 u_riscv_top.core0_dmem_rdata\[3\]
+port 776 nsew
+rlabel metal3 s 124146 376244 124146 376244 4 u_riscv_top.core0_dmem_rdata\[4\]
+port 777 nsew
+rlabel metal3 s 124192 375972 124192 375972 4 u_riscv_top.core0_dmem_rdata\[5\]
+port 778 nsew
+rlabel metal3 s 124100 375700 124100 375700 4 u_riscv_top.core0_dmem_rdata\[6\]
+port 779 nsew
+rlabel metal3 s 123732 375428 123732 375428 4 u_riscv_top.core0_dmem_rdata\[7\]
+port 780 nsew
+rlabel metal3 s 123640 375156 123640 375156 4 u_riscv_top.core0_dmem_rdata\[8\]
+port 781 nsew
+rlabel metal3 s 124192 374884 124192 374884 4 u_riscv_top.core0_dmem_rdata\[9\]
+port 782 nsew
+rlabel metal3 s 124146 350404 124146 350404 4 u_riscv_top.core0_dmem_req
+port 783 nsew
+rlabel metal3 s 124192 350132 124192 350132 4 u_riscv_top.core0_dmem_req_ack
+port 784 nsew
+rlabel metal3 s 123640 377876 123640 377876 4 u_riscv_top.core0_dmem_resp\[0\]
+port 785 nsew
+rlabel metal3 s 124192 377604 124192 377604 4 u_riscv_top.core0_dmem_resp\[1\]
+port 786 nsew
+rlabel metal3 s 124192 368628 124192 368628 4 u_riscv_top.core0_dmem_wdata\[0\]
+port 787 nsew
+rlabel metal3 s 124100 365908 124100 365908 4 u_riscv_top.core0_dmem_wdata\[10\]
+port 788 nsew
+rlabel metal3 s 123686 365636 123686 365636 4 u_riscv_top.core0_dmem_wdata\[11\]
+port 789 nsew
+rlabel metal3 s 124192 365364 124192 365364 4 u_riscv_top.core0_dmem_wdata\[12\]
+port 790 nsew
+rlabel metal3 s 124100 365092 124100 365092 4 u_riscv_top.core0_dmem_wdata\[13\]
+port 791 nsew
+rlabel metal3 s 124192 364820 124192 364820 4 u_riscv_top.core0_dmem_wdata\[14\]
+port 792 nsew
+rlabel metal3 s 124146 364548 124146 364548 4 u_riscv_top.core0_dmem_wdata\[15\]
+port 793 nsew
+rlabel metal3 s 123732 364276 123732 364276 4 u_riscv_top.core0_dmem_wdata\[16\]
+port 794 nsew
+rlabel metal3 s 124146 364004 124146 364004 4 u_riscv_top.core0_dmem_wdata\[17\]
+port 795 nsew
+rlabel metal3 s 124192 363732 124192 363732 4 u_riscv_top.core0_dmem_wdata\[18\]
+port 796 nsew
+rlabel metal3 s 124192 363460 124192 363460 4 u_riscv_top.core0_dmem_wdata\[19\]
+port 797 nsew
+rlabel metal3 s 124146 368356 124146 368356 4 u_riscv_top.core0_dmem_wdata\[1\]
+port 798 nsew
+rlabel metal3 s 124100 363188 124100 363188 4 u_riscv_top.core0_dmem_wdata\[20\]
+port 799 nsew
+rlabel metal3 s 124100 362916 124100 362916 4 u_riscv_top.core0_dmem_wdata\[21\]
+port 800 nsew
+rlabel metal3 s 124146 362644 124146 362644 4 u_riscv_top.core0_dmem_wdata\[22\]
+port 801 nsew
+rlabel metal3 s 124192 362372 124192 362372 4 u_riscv_top.core0_dmem_wdata\[23\]
+port 802 nsew
+rlabel metal3 s 124192 362100 124192 362100 4 u_riscv_top.core0_dmem_wdata\[24\]
+port 803 nsew
+rlabel metal3 s 123732 361828 123732 361828 4 u_riscv_top.core0_dmem_wdata\[25\]
+port 804 nsew
+rlabel metal3 s 124146 361556 124146 361556 4 u_riscv_top.core0_dmem_wdata\[26\]
+port 805 nsew
+rlabel metal3 s 124100 361284 124100 361284 4 u_riscv_top.core0_dmem_wdata\[27\]
+port 806 nsew
+rlabel metal3 s 124192 361012 124192 361012 4 u_riscv_top.core0_dmem_wdata\[28\]
+port 807 nsew
+rlabel metal3 s 124054 360740 124054 360740 4 u_riscv_top.core0_dmem_wdata\[29\]
+port 808 nsew
+rlabel metal3 s 124192 368084 124192 368084 4 u_riscv_top.core0_dmem_wdata\[2\]
+port 809 nsew
+rlabel metal3 s 123732 360468 123732 360468 4 u_riscv_top.core0_dmem_wdata\[30\]
+port 810 nsew
+rlabel metal3 s 123640 360196 123640 360196 4 u_riscv_top.core0_dmem_wdata\[31\]
+port 811 nsew
+rlabel metal3 s 124100 367812 124100 367812 4 u_riscv_top.core0_dmem_wdata\[3\]
+port 812 nsew
+rlabel metal3 s 123686 367540 123686 367540 4 u_riscv_top.core0_dmem_wdata\[4\]
+port 813 nsew
+rlabel metal3 s 124192 367268 124192 367268 4 u_riscv_top.core0_dmem_wdata\[5\]
+port 814 nsew
+rlabel metal3 s 124192 366996 124192 366996 4 u_riscv_top.core0_dmem_wdata\[6\]
+port 815 nsew
+rlabel metal3 s 124054 366724 124054 366724 4 u_riscv_top.core0_dmem_wdata\[7\]
+port 816 nsew
+rlabel metal3 s 124146 366452 124146 366452 4 u_riscv_top.core0_dmem_wdata\[8\]
+port 817 nsew
+rlabel metal3 s 124192 366180 124192 366180 4 u_riscv_top.core0_dmem_wdata\[9\]
+port 818 nsew
+rlabel metal3 s 124192 351220 124192 351220 4 u_riscv_top.core0_dmem_width\[0\]
+port 819 nsew
+rlabel metal3 s 124100 350948 124100 350948 4 u_riscv_top.core0_dmem_width\[1\]
+port 820 nsew
+rlabel metal3 s 123824 330276 123824 330276 4 u_riscv_top.core0_imem_addr\[0\]
+port 821 nsew
+rlabel metal3 s 124100 327556 124100 327556 4 u_riscv_top.core0_imem_addr\[10\]
+port 822 nsew
+rlabel metal3 s 123640 327284 123640 327284 4 u_riscv_top.core0_imem_addr\[11\]
+port 823 nsew
+rlabel metal3 s 123824 327012 123824 327012 4 u_riscv_top.core0_imem_addr\[12\]
+port 824 nsew
+rlabel metal3 s 124054 326740 124054 326740 4 u_riscv_top.core0_imem_addr\[13\]
+port 825 nsew
+rlabel metal3 s 124192 326468 124192 326468 4 u_riscv_top.core0_imem_addr\[14\]
+port 826 nsew
+rlabel metal3 s 124146 326196 124146 326196 4 u_riscv_top.core0_imem_addr\[15\]
+port 827 nsew
+rlabel metal3 s 124100 325924 124100 325924 4 u_riscv_top.core0_imem_addr\[16\]
+port 828 nsew
+rlabel metal3 s 124100 325652 124100 325652 4 u_riscv_top.core0_imem_addr\[17\]
+port 829 nsew
+rlabel metal3 s 124054 325380 124054 325380 4 u_riscv_top.core0_imem_addr\[18\]
+port 830 nsew
+rlabel metal3 s 124192 325108 124192 325108 4 u_riscv_top.core0_imem_addr\[19\]
+port 831 nsew
+rlabel metal3 s 124100 330004 124100 330004 4 u_riscv_top.core0_imem_addr\[1\]
+port 832 nsew
+rlabel metal3 s 124146 324836 124146 324836 4 u_riscv_top.core0_imem_addr\[20\]
+port 833 nsew
+rlabel metal3 s 123594 324564 123594 324564 4 u_riscv_top.core0_imem_addr\[21\]
+port 834 nsew
+rlabel metal3 s 123732 324292 123732 324292 4 u_riscv_top.core0_imem_addr\[22\]
+port 835 nsew
+rlabel metal3 s 124100 324020 124100 324020 4 u_riscv_top.core0_imem_addr\[23\]
+port 836 nsew
+rlabel metal3 s 124192 323748 124192 323748 4 u_riscv_top.core0_imem_addr\[24\]
+port 837 nsew
+rlabel metal3 s 124146 323476 124146 323476 4 u_riscv_top.core0_imem_addr\[25\]
+port 838 nsew
+rlabel metal3 s 124054 323204 124054 323204 4 u_riscv_top.core0_imem_addr\[26\]
+port 839 nsew
+rlabel metal3 s 123640 322932 123640 322932 4 u_riscv_top.core0_imem_addr\[27\]
+port 840 nsew
+rlabel metal3 s 124146 322660 124146 322660 4 u_riscv_top.core0_imem_addr\[28\]
+port 841 nsew
+rlabel metal3 s 124192 322388 124192 322388 4 u_riscv_top.core0_imem_addr\[29\]
+port 842 nsew
+rlabel metal3 s 124100 329732 124100 329732 4 u_riscv_top.core0_imem_addr\[2\]
+port 843 nsew
+rlabel metal3 s 124192 322116 124192 322116 4 u_riscv_top.core0_imem_addr\[30\]
+port 844 nsew
+rlabel metal3 s 124146 321844 124146 321844 4 u_riscv_top.core0_imem_addr\[31\]
+port 845 nsew
+rlabel metal3 s 123594 329460 123594 329460 4 u_riscv_top.core0_imem_addr\[3\]
+port 846 nsew
+rlabel metal3 s 124192 329188 124192 329188 4 u_riscv_top.core0_imem_addr\[4\]
+port 847 nsew
+rlabel metal3 s 124146 328916 124146 328916 4 u_riscv_top.core0_imem_addr\[5\]
+port 848 nsew
+rlabel metal3 s 123686 328644 123686 328644 4 u_riscv_top.core0_imem_addr\[6\]
+port 849 nsew
+rlabel metal3 s 124054 328372 124054 328372 4 u_riscv_top.core0_imem_addr\[7\]
+port 850 nsew
+rlabel metal3 s 124146 328100 124146 328100 4 u_riscv_top.core0_imem_addr\[8\]
+port 851 nsew
+rlabel metal3 s 124192 327828 124192 327828 4 u_riscv_top.core0_imem_addr\[9\]
+port 852 nsew
+rlabel metal3 s 124146 331092 124146 331092 4 u_riscv_top.core0_imem_bl\[0\]
+port 853 nsew
+rlabel metal3 s 124054 330820 124054 330820 4 u_riscv_top.core0_imem_bl\[1\]
+port 854 nsew
+rlabel metal3 s 124192 330548 124192 330548 4 u_riscv_top.core0_imem_bl\[2\]
+port 855 nsew
+rlabel metal3 s 124100 321572 124100 321572 4 u_riscv_top.core0_imem_cmd
+port 856 nsew
+rlabel metal3 s 124146 339796 124146 339796 4 u_riscv_top.core0_imem_rdata\[0\]
+port 857 nsew
+rlabel metal3 s 124192 337076 124192 337076 4 u_riscv_top.core0_imem_rdata\[10\]
+port 858 nsew
+rlabel metal3 s 123732 336804 123732 336804 4 u_riscv_top.core0_imem_rdata\[11\]
+port 859 nsew
+rlabel metal3 s 124146 336532 124146 336532 4 u_riscv_top.core0_imem_rdata\[12\]
+port 860 nsew
+rlabel metal3 s 124192 336260 124192 336260 4 u_riscv_top.core0_imem_rdata\[13\]
+port 861 nsew
+rlabel metal3 s 124192 335988 124192 335988 4 u_riscv_top.core0_imem_rdata\[14\]
+port 862 nsew
+rlabel metal3 s 124100 335716 124100 335716 4 u_riscv_top.core0_imem_rdata\[15\]
+port 863 nsew
+rlabel metal3 s 124054 335444 124054 335444 4 u_riscv_top.core0_imem_rdata\[16\]
+port 864 nsew
+rlabel metal3 s 124146 335172 124146 335172 4 u_riscv_top.core0_imem_rdata\[17\]
+port 865 nsew
+rlabel metal3 s 124192 334900 124192 334900 4 u_riscv_top.core0_imem_rdata\[18\]
+port 866 nsew
+rlabel metal3 s 124192 334628 124192 334628 4 u_riscv_top.core0_imem_rdata\[19\]
+port 867 nsew
+rlabel metal3 s 123778 339524 123778 339524 4 u_riscv_top.core0_imem_rdata\[1\]
+port 868 nsew
+rlabel metal3 s 124146 334356 124146 334356 4 u_riscv_top.core0_imem_rdata\[20\]
+port 869 nsew
+rlabel metal3 s 123732 334084 123732 334084 4 u_riscv_top.core0_imem_rdata\[21\]
+port 870 nsew
+rlabel metal3 s 124100 333812 124100 333812 4 u_riscv_top.core0_imem_rdata\[22\]
+port 871 nsew
+rlabel metal3 s 124054 333540 124054 333540 4 u_riscv_top.core0_imem_rdata\[23\]
+port 872 nsew
+rlabel metal3 s 124192 333268 124192 333268 4 u_riscv_top.core0_imem_rdata\[24\]
+port 873 nsew
+rlabel metal3 s 124146 332996 124146 332996 4 u_riscv_top.core0_imem_rdata\[25\]
+port 874 nsew
+rlabel metal3 s 123824 332724 123824 332724 4 u_riscv_top.core0_imem_rdata\[26\]
+port 875 nsew
+rlabel metal3 s 124100 332452 124100 332452 4 u_riscv_top.core0_imem_rdata\[27\]
+port 876 nsew
+rlabel metal3 s 124192 332180 124192 332180 4 u_riscv_top.core0_imem_rdata\[28\]
+port 877 nsew
+rlabel metal3 s 124192 331908 124192 331908 4 u_riscv_top.core0_imem_rdata\[29\]
+port 878 nsew
+rlabel metal3 s 124146 339252 124146 339252 4 u_riscv_top.core0_imem_rdata\[2\]
+port 879 nsew
+rlabel metal3 s 124146 331636 124146 331636 4 u_riscv_top.core0_imem_rdata\[30\]
+port 880 nsew
+rlabel metal3 s 123732 331364 123732 331364 4 u_riscv_top.core0_imem_rdata\[31\]
+port 881 nsew
+rlabel metal3 s 124192 338980 124192 338980 4 u_riscv_top.core0_imem_rdata\[3\]
+port 882 nsew
+rlabel metal3 s 124100 338708 124100 338708 4 u_riscv_top.core0_imem_rdata\[4\]
+port 883 nsew
+rlabel metal3 s 124146 338436 124146 338436 4 u_riscv_top.core0_imem_rdata\[5\]
+port 884 nsew
+rlabel metal3 s 124192 338164 124192 338164 4 u_riscv_top.core0_imem_rdata\[6\]
+port 885 nsew
+rlabel metal3 s 124192 337892 124192 337892 4 u_riscv_top.core0_imem_rdata\[7\]
+port 886 nsew
+rlabel metal3 s 124146 337620 124146 337620 4 u_riscv_top.core0_imem_rdata\[8\]
+port 887 nsew
+rlabel metal3 s 124100 337348 124100 337348 4 u_riscv_top.core0_imem_rdata\[9\]
+port 888 nsew
+rlabel metal3 s 123640 321300 123640 321300 4 u_riscv_top.core0_imem_req
+port 889 nsew
+rlabel metal3 s 124192 321028 124192 321028 4 u_riscv_top.core0_imem_req_ack
+port 890 nsew
+rlabel metal3 s 124192 340340 124192 340340 4 u_riscv_top.core0_imem_resp\[0\]
+port 891 nsew
+rlabel metal3 s 124192 340068 124192 340068 4 u_riscv_top.core0_imem_resp\[1\]
+port 892 nsew
+rlabel metal3 s 124146 426292 124146 426292 4 u_riscv_top.core0_irq_lines\[0\]
+port 893 nsew
+rlabel metal3 s 123732 423572 123732 423572 4 u_riscv_top.core0_irq_lines\[10\]
+port 894 nsew
+rlabel metal3 s 124100 423300 124100 423300 4 u_riscv_top.core0_irq_lines\[11\]
+port 895 nsew
+rlabel metal3 s 124192 423028 124192 423028 4 u_riscv_top.core0_irq_lines\[12\]
+port 896 nsew
+rlabel metal3 s 124146 422756 124146 422756 4 u_riscv_top.core0_irq_lines\[13\]
+port 897 nsew
+rlabel metal3 s 124054 422484 124054 422484 4 u_riscv_top.core0_irq_lines\[14\]
+port 898 nsew
+rlabel metal3 s 124054 422212 124054 422212 4 u_riscv_top.core0_irq_lines\[15\]
+port 899 nsew
+rlabel metal3 s 124146 421940 124146 421940 4 u_riscv_top.core0_irq_lines\[16\]
+port 900 nsew
+rlabel metal3 s 124192 421668 124192 421668 4 u_riscv_top.core0_irq_lines\[17\]
+port 901 nsew
+rlabel metal3 s 124100 421396 124100 421396 4 u_riscv_top.core0_irq_lines\[18\]
+port 902 nsew
+rlabel metal3 s 123824 421124 123824 421124 4 u_riscv_top.core0_irq_lines\[19\]
+port 903 nsew
+rlabel metal3 s 124192 426020 124192 426020 4 u_riscv_top.core0_irq_lines\[1\]
+port 904 nsew
+rlabel metal3 s 124146 420852 124146 420852 4 u_riscv_top.core0_irq_lines\[20\]
+port 905 nsew
+rlabel metal3 s 124100 420580 124100 420580 4 u_riscv_top.core0_irq_lines\[21\]
+port 906 nsew
+rlabel metal3 s 124192 420308 124192 420308 4 u_riscv_top.core0_irq_lines\[22\]
+port 907 nsew
+rlabel metal3 s 124192 420036 124192 420036 4 u_riscv_top.core0_irq_lines\[23\]
+port 908 nsew
+rlabel metal3 s 123732 419764 123732 419764 4 u_riscv_top.core0_irq_lines\[24\]
+port 909 nsew
+rlabel metal3 s 124192 419492 124192 419492 4 u_riscv_top.core0_irq_lines\[25\]
+port 910 nsew
+rlabel metal3 s 123640 419220 123640 419220 4 u_riscv_top.core0_irq_lines\[26\]
+port 911 nsew
+rlabel metal3 s 124192 418948 124192 418948 4 u_riscv_top.core0_irq_lines\[27\]
+port 912 nsew
+rlabel metal3 s 124192 418676 124192 418676 4 u_riscv_top.core0_irq_lines\[28\]
+port 913 nsew
+rlabel metal3 s 124146 418404 124146 418404 4 u_riscv_top.core0_irq_lines\[29\]
+port 914 nsew
+rlabel metal3 s 124192 425748 124192 425748 4 u_riscv_top.core0_irq_lines\[2\]
+port 915 nsew
+rlabel metal3 s 124146 418132 124146 418132 4 u_riscv_top.core0_irq_lines\[30\]
+port 916 nsew
+rlabel metal3 s 124192 417860 124192 417860 4 u_riscv_top.core0_irq_lines\[31\]
+port 917 nsew
+rlabel metal3 s 124146 425476 124146 425476 4 u_riscv_top.core0_irq_lines\[3\]
+port 918 nsew
+rlabel metal3 s 123778 425204 123778 425204 4 u_riscv_top.core0_irq_lines\[4\]
+port 919 nsew
+rlabel metal3 s 124100 424932 124100 424932 4 u_riscv_top.core0_irq_lines\[5\]
+port 920 nsew
+rlabel metal3 s 124146 424660 124146 424660 4 u_riscv_top.core0_irq_lines\[6\]
+port 921 nsew
+rlabel metal3 s 124192 424388 124192 424388 4 u_riscv_top.core0_irq_lines\[7\]
+port 922 nsew
+rlabel metal3 s 123686 424116 123686 424116 4 u_riscv_top.core0_irq_lines\[8\]
+port 923 nsew
+rlabel metal3 s 123778 423844 123778 423844 4 u_riscv_top.core0_irq_lines\[9\]
+port 924 nsew
+rlabel metal3 s 124192 426564 124192 426564 4 u_riscv_top.core0_soft_irq
+port 925 nsew
+rlabel metal3 s 124192 400180 124192 400180 4 u_riscv_top.core0_timer_irq
+port 926 nsew
+rlabel metal3 s 124100 417588 124100 417588 4 u_riscv_top.core0_timer_val\[0\]
+port 927 nsew
+rlabel metal3 s 124192 414868 124192 414868 4 u_riscv_top.core0_timer_val\[10\]
+port 928 nsew
+rlabel metal3 s 123594 414596 123594 414596 4 u_riscv_top.core0_timer_val\[11\]
+port 929 nsew
+rlabel metal3 s 123732 414324 123732 414324 4 u_riscv_top.core0_timer_val\[12\]
+port 930 nsew
+rlabel metal3 s 124100 414052 124100 414052 4 u_riscv_top.core0_timer_val\[13\]
+port 931 nsew
+rlabel metal3 s 124146 413780 124146 413780 4 u_riscv_top.core0_timer_val\[14\]
+port 932 nsew
+rlabel metal3 s 124192 413508 124192 413508 4 u_riscv_top.core0_timer_val\[15\]
+port 933 nsew
+rlabel metal3 s 124192 413236 124192 413236 4 u_riscv_top.core0_timer_val\[16\]
+port 934 nsew
+rlabel metal3 s 124100 412964 124100 412964 4 u_riscv_top.core0_timer_val\[17\]
+port 935 nsew
+rlabel metal3 s 124146 412692 124146 412692 4 u_riscv_top.core0_timer_val\[18\]
+port 936 nsew
+rlabel metal3 s 124192 412420 124192 412420 4 u_riscv_top.core0_timer_val\[19\]
+port 937 nsew
+rlabel metal3 s 124192 417316 124192 417316 4 u_riscv_top.core0_timer_val\[1\]
+port 938 nsew
+rlabel metal3 s 124146 412148 124146 412148 4 u_riscv_top.core0_timer_val\[20\]
+port 939 nsew
+rlabel metal3 s 124192 411876 124192 411876 4 u_riscv_top.core0_timer_val\[21\]
+port 940 nsew
+rlabel metal3 s 124100 411604 124100 411604 4 u_riscv_top.core0_timer_val\[22\]
+port 941 nsew
+rlabel metal3 s 123732 411332 123732 411332 4 u_riscv_top.core0_timer_val\[23\]
+port 942 nsew
+rlabel metal3 s 123640 411060 123640 411060 4 u_riscv_top.core0_timer_val\[24\]
+port 943 nsew
+rlabel metal3 s 124146 410788 124146 410788 4 u_riscv_top.core0_timer_val\[25\]
+port 944 nsew
+rlabel metal3 s 124192 410516 124192 410516 4 u_riscv_top.core0_timer_val\[26\]
+port 945 nsew
+rlabel metal3 s 124100 410244 124100 410244 4 u_riscv_top.core0_timer_val\[27\]
+port 946 nsew
+rlabel metal3 s 124054 409972 124054 409972 4 u_riscv_top.core0_timer_val\[28\]
+port 947 nsew
+rlabel metal3 s 124146 409700 124146 409700 4 u_riscv_top.core0_timer_val\[29\]
+port 948 nsew
+rlabel metal3 s 124054 417044 124054 417044 4 u_riscv_top.core0_timer_val\[2\]
+port 949 nsew
+rlabel metal3 s 124192 409428 124192 409428 4 u_riscv_top.core0_timer_val\[30\]
+port 950 nsew
+rlabel metal3 s 124100 409156 124100 409156 4 u_riscv_top.core0_timer_val\[31\]
+port 951 nsew
+rlabel metal3 s 124192 408884 124192 408884 4 u_riscv_top.core0_timer_val\[32\]
+port 952 nsew
+rlabel metal3 s 123732 408612 123732 408612 4 u_riscv_top.core0_timer_val\[33\]
+port 953 nsew
+rlabel metal3 s 124100 408340 124100 408340 4 u_riscv_top.core0_timer_val\[34\]
+port 954 nsew
+rlabel metal3 s 124192 408068 124192 408068 4 u_riscv_top.core0_timer_val\[35\]
+port 955 nsew
+rlabel metal3 s 124146 407796 124146 407796 4 u_riscv_top.core0_timer_val\[36\]
+port 956 nsew
+rlabel metal3 s 124192 407524 124192 407524 4 u_riscv_top.core0_timer_val\[37\]
+port 957 nsew
+rlabel metal3 s 123732 407252 123732 407252 4 u_riscv_top.core0_timer_val\[38\]
+port 958 nsew
+rlabel metal3 s 124146 406980 124146 406980 4 u_riscv_top.core0_timer_val\[39\]
+port 959 nsew
+rlabel metal3 s 123732 416772 123732 416772 4 u_riscv_top.core0_timer_val\[3\]
+port 960 nsew
+rlabel metal3 s 124192 406708 124192 406708 4 u_riscv_top.core0_timer_val\[40\]
+port 961 nsew
+rlabel metal3 s 124192 406436 124192 406436 4 u_riscv_top.core0_timer_val\[41\]
+port 962 nsew
+rlabel metal3 s 124100 406164 124100 406164 4 u_riscv_top.core0_timer_val\[42\]
+port 963 nsew
+rlabel metal3 s 123732 405892 123732 405892 4 u_riscv_top.core0_timer_val\[43\]
+port 964 nsew
+rlabel metal3 s 123732 405620 123732 405620 4 u_riscv_top.core0_timer_val\[44\]
+port 965 nsew
+rlabel metal3 s 124146 405348 124146 405348 4 u_riscv_top.core0_timer_val\[45\]
+port 966 nsew
+rlabel metal3 s 124192 405076 124192 405076 4 u_riscv_top.core0_timer_val\[46\]
+port 967 nsew
+rlabel metal3 s 124192 404804 124192 404804 4 u_riscv_top.core0_timer_val\[47\]
+port 968 nsew
+rlabel metal3 s 123686 404532 123686 404532 4 u_riscv_top.core0_timer_val\[48\]
+port 969 nsew
+rlabel metal3 s 124100 404260 124100 404260 4 u_riscv_top.core0_timer_val\[49\]
+port 970 nsew
+rlabel metal3 s 124146 416500 124146 416500 4 u_riscv_top.core0_timer_val\[4\]
+port 971 nsew
+rlabel metal3 s 124146 403988 124146 403988 4 u_riscv_top.core0_timer_val\[50\]
+port 972 nsew
+rlabel metal3 s 124192 403716 124192 403716 4 u_riscv_top.core0_timer_val\[51\]
+port 973 nsew
+rlabel metal3 s 124192 403444 124192 403444 4 u_riscv_top.core0_timer_val\[52\]
+port 974 nsew
+rlabel metal3 s 124100 403172 124100 403172 4 u_riscv_top.core0_timer_val\[53\]
+port 975 nsew
+rlabel metal3 s 124054 402900 124054 402900 4 u_riscv_top.core0_timer_val\[54\]
+port 976 nsew
+rlabel metal3 s 124100 402628 124100 402628 4 u_riscv_top.core0_timer_val\[55\]
+port 977 nsew
+rlabel metal3 s 124192 402356 124192 402356 4 u_riscv_top.core0_timer_val\[56\]
+port 978 nsew
+rlabel metal3 s 123640 402084 123640 402084 4 u_riscv_top.core0_timer_val\[57\]
+port 979 nsew
+rlabel metal3 s 124146 401812 124146 401812 4 u_riscv_top.core0_timer_val\[58\]
+port 980 nsew
+rlabel metal3 s 123686 401540 123686 401540 4 u_riscv_top.core0_timer_val\[59\]
+port 981 nsew
+rlabel metal3 s 124192 416228 124192 416228 4 u_riscv_top.core0_timer_val\[5\]
+port 982 nsew
+rlabel metal3 s 124192 401268 124192 401268 4 u_riscv_top.core0_timer_val\[60\]
+port 983 nsew
+rlabel metal3 s 124192 400996 124192 400996 4 u_riscv_top.core0_timer_val\[61\]
+port 984 nsew
+rlabel metal3 s 124100 400724 124100 400724 4 u_riscv_top.core0_timer_val\[62\]
+port 985 nsew
+rlabel metal3 s 124146 400452 124146 400452 4 u_riscv_top.core0_timer_val\[63\]
+port 986 nsew
+rlabel metal3 s 124100 415956 124100 415956 4 u_riscv_top.core0_timer_val\[6\]
+port 987 nsew
+rlabel metal3 s 123640 415684 123640 415684 4 u_riscv_top.core0_timer_val\[7\]
+port 988 nsew
+rlabel metal3 s 123778 415412 123778 415412 4 u_riscv_top.core0_timer_val\[8\]
+port 989 nsew
+rlabel metal3 s 124146 415140 124146 415140 4 u_riscv_top.core0_timer_val\[9\]
+port 990 nsew
+rlabel metal3 s 124146 320756 124146 320756 4 u_riscv_top.core0_uid\[0\]
+port 991 nsew
+rlabel metal3 s 123732 320484 123732 320484 4 u_riscv_top.core0_uid\[1\]
+port 992 nsew
+rlabel metal3 s 230414 320229 230414 320229 4 u_riscv_top.core1_clk
+port 993 nsew
+rlabel metal3 s 230414 393261 230414 393261 4 u_riscv_top.core1_debug\[0\]
+port 994 nsew
+rlabel metal3 s 230414 390507 230414 390507 4 u_riscv_top.core1_debug\[10\]
+port 995 nsew
+rlabel metal3 s 230414 390269 230414 390269 4 u_riscv_top.core1_debug\[11\]
+port 996 nsew
+rlabel metal3 s 230414 389997 230414 389997 4 u_riscv_top.core1_debug\[12\]
+port 997 nsew
+rlabel metal3 s 230414 389725 230414 389725 4 u_riscv_top.core1_debug\[13\]
+port 998 nsew
+rlabel metal3 s 230414 389453 230414 389453 4 u_riscv_top.core1_debug\[14\]
+port 999 nsew
+rlabel metal3 s 230414 389181 230414 389181 4 u_riscv_top.core1_debug\[15\]
+port 1000 nsew
+rlabel metal3 s 230414 388875 230414 388875 4 u_riscv_top.core1_debug\[16\]
+port 1001 nsew
+rlabel metal3 s 230414 388637 230414 388637 4 u_riscv_top.core1_debug\[17\]
+port 1002 nsew
+rlabel metal3 s 230414 388365 230414 388365 4 u_riscv_top.core1_debug\[18\]
+port 1003 nsew
+rlabel metal3 s 230414 388093 230414 388093 4 u_riscv_top.core1_debug\[19\]
+port 1004 nsew
+rlabel metal3 s 230414 392989 230414 392989 4 u_riscv_top.core1_debug\[1\]
+port 1005 nsew
+rlabel metal3 s 230414 387821 230414 387821 4 u_riscv_top.core1_debug\[20\]
+port 1006 nsew
+rlabel metal3 s 230414 387515 230414 387515 4 u_riscv_top.core1_debug\[21\]
+port 1007 nsew
+rlabel metal3 s 230414 387277 230414 387277 4 u_riscv_top.core1_debug\[22\]
+port 1008 nsew
+rlabel metal3 s 230414 387005 230414 387005 4 u_riscv_top.core1_debug\[23\]
+port 1009 nsew
+rlabel metal3 s 230414 386733 230414 386733 4 u_riscv_top.core1_debug\[24\]
+port 1010 nsew
+rlabel metal3 s 230414 386461 230414 386461 4 u_riscv_top.core1_debug\[25\]
+port 1011 nsew
+rlabel metal3 s 230414 386155 230414 386155 4 u_riscv_top.core1_debug\[26\]
+port 1012 nsew
+rlabel metal3 s 230414 385917 230414 385917 4 u_riscv_top.core1_debug\[27\]
+port 1013 nsew
+rlabel metal3 s 230414 385645 230414 385645 4 u_riscv_top.core1_debug\[28\]
+port 1014 nsew
+rlabel metal3 s 230414 385373 230414 385373 4 u_riscv_top.core1_debug\[29\]
+port 1015 nsew
+rlabel metal3 s 230414 392717 230414 392717 4 u_riscv_top.core1_debug\[2\]
+port 1016 nsew
+rlabel metal3 s 230414 385101 230414 385101 4 u_riscv_top.core1_debug\[30\]
+port 1017 nsew
+rlabel metal3 s 230414 384795 230414 384795 4 u_riscv_top.core1_debug\[31\]
+port 1018 nsew
+rlabel metal3 s 230414 384557 230414 384557 4 u_riscv_top.core1_debug\[32\]
+port 1019 nsew
+rlabel metal3 s 230414 384285 230414 384285 4 u_riscv_top.core1_debug\[33\]
+port 1020 nsew
+rlabel metal3 s 230414 384013 230414 384013 4 u_riscv_top.core1_debug\[34\]
+port 1021 nsew
+rlabel metal3 s 230414 383741 230414 383741 4 u_riscv_top.core1_debug\[35\]
+port 1022 nsew
+rlabel metal3 s 230414 383469 230414 383469 4 u_riscv_top.core1_debug\[36\]
+port 1023 nsew
+rlabel metal3 s 230414 383197 230414 383197 4 u_riscv_top.core1_debug\[37\]
+port 1024 nsew
+rlabel metal3 s 230414 382925 230414 382925 4 u_riscv_top.core1_debug\[38\]
+port 1025 nsew
+rlabel metal3 s 230414 382653 230414 382653 4 u_riscv_top.core1_debug\[39\]
+port 1026 nsew
+rlabel metal3 s 230414 392445 230414 392445 4 u_riscv_top.core1_debug\[3\]
+port 1027 nsew
+rlabel metal3 s 230414 382381 230414 382381 4 u_riscv_top.core1_debug\[40\]
+port 1028 nsew
+rlabel metal3 s 230414 382109 230414 382109 4 u_riscv_top.core1_debug\[41\]
+port 1029 nsew
+rlabel metal3 s 230414 381837 230414 381837 4 u_riscv_top.core1_debug\[42\]
+port 1030 nsew
+rlabel metal3 s 230414 381565 230414 381565 4 u_riscv_top.core1_debug\[43\]
+port 1031 nsew
+rlabel metal3 s 230414 381293 230414 381293 4 u_riscv_top.core1_debug\[44\]
+port 1032 nsew
+rlabel metal3 s 230414 381021 230414 381021 4 u_riscv_top.core1_debug\[45\]
+port 1033 nsew
+rlabel metal3 s 230414 380749 230414 380749 4 u_riscv_top.core1_debug\[46\]
+port 1034 nsew
+rlabel metal3 s 230414 380477 230414 380477 4 u_riscv_top.core1_debug\[47\]
+port 1035 nsew
+rlabel metal3 s 230414 380205 230414 380205 4 u_riscv_top.core1_debug\[48\]
+port 1036 nsew
+rlabel metal3 s 230414 392173 230414 392173 4 u_riscv_top.core1_debug\[4\]
+port 1037 nsew
+rlabel metal3 s 230414 391867 230414 391867 4 u_riscv_top.core1_debug\[5\]
+port 1038 nsew
+rlabel metal3 s 230414 391629 230414 391629 4 u_riscv_top.core1_debug\[6\]
+port 1039 nsew
+rlabel metal3 s 230414 391357 230414 391357 4 u_riscv_top.core1_debug\[7\]
+port 1040 nsew
+rlabel metal3 s 230414 391085 230414 391085 4 u_riscv_top.core1_debug\[8\]
+port 1041 nsew
+rlabel metal3 s 230414 390813 230414 390813 4 u_riscv_top.core1_debug\[9\]
+port 1042 nsew
+rlabel metal3 s 230414 359941 230414 359941 4 u_riscv_top.core1_dmem_addr\[0\]
+port 1043 nsew
+rlabel metal3 s 230414 357221 230414 357221 4 u_riscv_top.core1_dmem_addr\[10\]
+port 1044 nsew
+rlabel metal3 s 230414 356949 230414 356949 4 u_riscv_top.core1_dmem_addr\[11\]
+port 1045 nsew
+rlabel metal3 s 230414 356677 230414 356677 4 u_riscv_top.core1_dmem_addr\[12\]
+port 1046 nsew
+rlabel metal3 s 230414 356405 230414 356405 4 u_riscv_top.core1_dmem_addr\[13\]
+port 1047 nsew
+rlabel metal3 s 230414 356133 230414 356133 4 u_riscv_top.core1_dmem_addr\[14\]
+port 1048 nsew
+rlabel metal3 s 230414 355861 230414 355861 4 u_riscv_top.core1_dmem_addr\[15\]
+port 1049 nsew
+rlabel metal3 s 230414 355589 230414 355589 4 u_riscv_top.core1_dmem_addr\[16\]
+port 1050 nsew
+rlabel metal3 s 230414 355317 230414 355317 4 u_riscv_top.core1_dmem_addr\[17\]
+port 1051 nsew
+rlabel metal3 s 230414 355045 230414 355045 4 u_riscv_top.core1_dmem_addr\[18\]
+port 1052 nsew
+rlabel metal3 s 230414 354773 230414 354773 4 u_riscv_top.core1_dmem_addr\[19\]
+port 1053 nsew
+rlabel metal3 s 230414 359669 230414 359669 4 u_riscv_top.core1_dmem_addr\[1\]
+port 1054 nsew
+rlabel metal3 s 230414 354501 230414 354501 4 u_riscv_top.core1_dmem_addr\[20\]
+port 1055 nsew
+rlabel metal3 s 230414 354229 230414 354229 4 u_riscv_top.core1_dmem_addr\[21\]
+port 1056 nsew
+rlabel metal3 s 230414 353957 230414 353957 4 u_riscv_top.core1_dmem_addr\[22\]
+port 1057 nsew
+rlabel metal3 s 230414 353685 230414 353685 4 u_riscv_top.core1_dmem_addr\[23\]
+port 1058 nsew
+rlabel metal3 s 230414 353413 230414 353413 4 u_riscv_top.core1_dmem_addr\[24\]
+port 1059 nsew
+rlabel metal3 s 230414 353141 230414 353141 4 u_riscv_top.core1_dmem_addr\[25\]
+port 1060 nsew
+rlabel metal3 s 230414 352869 230414 352869 4 u_riscv_top.core1_dmem_addr\[26\]
+port 1061 nsew
+rlabel metal3 s 230414 352597 230414 352597 4 u_riscv_top.core1_dmem_addr\[27\]
+port 1062 nsew
+rlabel metal3 s 230414 352325 230414 352325 4 u_riscv_top.core1_dmem_addr\[28\]
+port 1063 nsew
+rlabel metal3 s 230414 352053 230414 352053 4 u_riscv_top.core1_dmem_addr\[29\]
+port 1064 nsew
+rlabel metal3 s 230414 359397 230414 359397 4 u_riscv_top.core1_dmem_addr\[2\]
+port 1065 nsew
+rlabel metal3 s 230414 351781 230414 351781 4 u_riscv_top.core1_dmem_addr\[30\]
+port 1066 nsew
+rlabel metal3 s 230414 351509 230414 351509 4 u_riscv_top.core1_dmem_addr\[31\]
+port 1067 nsew
+rlabel metal3 s 230414 359125 230414 359125 4 u_riscv_top.core1_dmem_addr\[3\]
+port 1068 nsew
+rlabel metal3 s 230414 358853 230414 358853 4 u_riscv_top.core1_dmem_addr\[4\]
+port 1069 nsew
+rlabel metal3 s 230414 358581 230414 358581 4 u_riscv_top.core1_dmem_addr\[5\]
+port 1070 nsew
+rlabel metal3 s 230414 358309 230414 358309 4 u_riscv_top.core1_dmem_addr\[6\]
+port 1071 nsew
+rlabel metal3 s 230414 358037 230414 358037 4 u_riscv_top.core1_dmem_addr\[7\]
+port 1072 nsew
+rlabel metal3 s 230414 357765 230414 357765 4 u_riscv_top.core1_dmem_addr\[8\]
+port 1073 nsew
+rlabel metal3 s 230414 357459 230414 357459 4 u_riscv_top.core1_dmem_addr\[9\]
+port 1074 nsew
+rlabel metal3 s 230414 350693 230414 350693 4 u_riscv_top.core1_dmem_cmd
+port 1075 nsew
+rlabel metal3 s 230414 377349 230414 377349 4 u_riscv_top.core1_dmem_rdata\[0\]
+port 1076 nsew
+rlabel metal3 s 230414 374629 230414 374629 4 u_riscv_top.core1_dmem_rdata\[10\]
+port 1077 nsew
+rlabel metal3 s 230414 374357 230414 374357 4 u_riscv_top.core1_dmem_rdata\[11\]
+port 1078 nsew
+rlabel metal3 s 230414 374051 230414 374051 4 u_riscv_top.core1_dmem_rdata\[12\]
+port 1079 nsew
+rlabel metal3 s 230414 373813 230414 373813 4 u_riscv_top.core1_dmem_rdata\[13\]
+port 1080 nsew
+rlabel metal3 s 230414 373541 230414 373541 4 u_riscv_top.core1_dmem_rdata\[14\]
+port 1081 nsew
+rlabel metal3 s 230414 373269 230414 373269 4 u_riscv_top.core1_dmem_rdata\[15\]
+port 1082 nsew
+rlabel metal3 s 230414 372963 230414 372963 4 u_riscv_top.core1_dmem_rdata\[16\]
+port 1083 nsew
+rlabel metal3 s 230414 372725 230414 372725 4 u_riscv_top.core1_dmem_rdata\[17\]
+port 1084 nsew
+rlabel metal3 s 230414 372453 230414 372453 4 u_riscv_top.core1_dmem_rdata\[18\]
+port 1085 nsew
+rlabel metal3 s 230414 372181 230414 372181 4 u_riscv_top.core1_dmem_rdata\[19\]
+port 1086 nsew
+rlabel metal3 s 230414 377077 230414 377077 4 u_riscv_top.core1_dmem_rdata\[1\]
+port 1087 nsew
+rlabel metal3 s 230414 371909 230414 371909 4 u_riscv_top.core1_dmem_rdata\[20\]
+port 1088 nsew
+rlabel metal3 s 230414 371603 230414 371603 4 u_riscv_top.core1_dmem_rdata\[21\]
+port 1089 nsew
+rlabel metal3 s 230414 371365 230414 371365 4 u_riscv_top.core1_dmem_rdata\[22\]
+port 1090 nsew
+rlabel metal3 s 230414 371093 230414 371093 4 u_riscv_top.core1_dmem_rdata\[23\]
+port 1091 nsew
+rlabel metal3 s 230414 370821 230414 370821 4 u_riscv_top.core1_dmem_rdata\[24\]
+port 1092 nsew
+rlabel metal3 s 230414 370549 230414 370549 4 u_riscv_top.core1_dmem_rdata\[25\]
+port 1093 nsew
+rlabel metal3 s 230414 370277 230414 370277 4 u_riscv_top.core1_dmem_rdata\[26\]
+port 1094 nsew
+rlabel metal3 s 230414 370005 230414 370005 4 u_riscv_top.core1_dmem_rdata\[27\]
+port 1095 nsew
+rlabel metal3 s 230414 369733 230414 369733 4 u_riscv_top.core1_dmem_rdata\[28\]
+port 1096 nsew
+rlabel metal3 s 230414 369461 230414 369461 4 u_riscv_top.core1_dmem_rdata\[29\]
+port 1097 nsew
+rlabel metal3 s 230414 376805 230414 376805 4 u_riscv_top.core1_dmem_rdata\[2\]
+port 1098 nsew
+rlabel metal3 s 230414 369189 230414 369189 4 u_riscv_top.core1_dmem_rdata\[30\]
+port 1099 nsew
+rlabel metal3 s 230414 368917 230414 368917 4 u_riscv_top.core1_dmem_rdata\[31\]
+port 1100 nsew
+rlabel metal3 s 230414 376533 230414 376533 4 u_riscv_top.core1_dmem_rdata\[3\]
+port 1101 nsew
+rlabel metal3 s 230414 376261 230414 376261 4 u_riscv_top.core1_dmem_rdata\[4\]
+port 1102 nsew
+rlabel metal3 s 230414 375989 230414 375989 4 u_riscv_top.core1_dmem_rdata\[5\]
+port 1103 nsew
+rlabel metal3 s 230414 375717 230414 375717 4 u_riscv_top.core1_dmem_rdata\[6\]
+port 1104 nsew
+rlabel metal3 s 230414 375445 230414 375445 4 u_riscv_top.core1_dmem_rdata\[7\]
+port 1105 nsew
+rlabel metal3 s 230414 375139 230414 375139 4 u_riscv_top.core1_dmem_rdata\[8\]
+port 1106 nsew
+rlabel metal3 s 230414 374867 230414 374867 4 u_riscv_top.core1_dmem_rdata\[9\]
+port 1107 nsew
+rlabel metal3 s 230414 350421 230414 350421 4 u_riscv_top.core1_dmem_req
+port 1108 nsew
+rlabel metal3 s 230414 350115 230414 350115 4 u_riscv_top.core1_dmem_req_ack
+port 1109 nsew
+rlabel metal3 s 230414 377893 230414 377893 4 u_riscv_top.core1_dmem_resp\[0\]
+port 1110 nsew
+rlabel metal3 s 230414 377621 230414 377621 4 u_riscv_top.core1_dmem_resp\[1\]
+port 1111 nsew
+rlabel metal3 s 230414 368645 230414 368645 4 u_riscv_top.core1_dmem_wdata\[0\]
+port 1112 nsew
+rlabel metal3 s 230414 365925 230414 365925 4 u_riscv_top.core1_dmem_wdata\[10\]
+port 1113 nsew
+rlabel metal3 s 230414 365619 230414 365619 4 u_riscv_top.core1_dmem_wdata\[11\]
+port 1114 nsew
+rlabel metal3 s 230414 365381 230414 365381 4 u_riscv_top.core1_dmem_wdata\[12\]
+port 1115 nsew
+rlabel metal3 s 230414 365109 230414 365109 4 u_riscv_top.core1_dmem_wdata\[13\]
+port 1116 nsew
+rlabel metal3 s 230414 364837 230414 364837 4 u_riscv_top.core1_dmem_wdata\[14\]
+port 1117 nsew
+rlabel metal3 s 230414 364565 230414 364565 4 u_riscv_top.core1_dmem_wdata\[15\]
+port 1118 nsew
+rlabel metal3 s 230414 364293 230414 364293 4 u_riscv_top.core1_dmem_wdata\[16\]
+port 1119 nsew
+rlabel metal3 s 230414 363987 230414 363987 4 u_riscv_top.core1_dmem_wdata\[17\]
+port 1120 nsew
+rlabel metal3 s 230414 363749 230414 363749 4 u_riscv_top.core1_dmem_wdata\[18\]
+port 1121 nsew
+rlabel metal3 s 230414 363477 230414 363477 4 u_riscv_top.core1_dmem_wdata\[19\]
+port 1122 nsew
+rlabel metal3 s 230414 368373 230414 368373 4 u_riscv_top.core1_dmem_wdata\[1\]
+port 1123 nsew
+rlabel metal3 s 230414 363205 230414 363205 4 u_riscv_top.core1_dmem_wdata\[20\]
+port 1124 nsew
+rlabel metal3 s 230414 362899 230414 362899 4 u_riscv_top.core1_dmem_wdata\[21\]
+port 1125 nsew
+rlabel metal3 s 230414 362661 230414 362661 4 u_riscv_top.core1_dmem_wdata\[22\]
+port 1126 nsew
+rlabel metal3 s 230414 362389 230414 362389 4 u_riscv_top.core1_dmem_wdata\[23\]
+port 1127 nsew
+rlabel metal3 s 230414 362117 230414 362117 4 u_riscv_top.core1_dmem_wdata\[24\]
+port 1128 nsew
+rlabel metal3 s 230414 361845 230414 361845 4 u_riscv_top.core1_dmem_wdata\[25\]
+port 1129 nsew
+rlabel metal3 s 230414 361539 230414 361539 4 u_riscv_top.core1_dmem_wdata\[26\]
+port 1130 nsew
+rlabel metal3 s 230414 361301 230414 361301 4 u_riscv_top.core1_dmem_wdata\[27\]
+port 1131 nsew
+rlabel metal3 s 230414 361029 230414 361029 4 u_riscv_top.core1_dmem_wdata\[28\]
+port 1132 nsew
+rlabel metal3 s 230414 360757 230414 360757 4 u_riscv_top.core1_dmem_wdata\[29\]
+port 1133 nsew
+rlabel metal3 s 230414 368101 230414 368101 4 u_riscv_top.core1_dmem_wdata\[2\]
+port 1134 nsew
+rlabel metal3 s 230414 360451 230414 360451 4 u_riscv_top.core1_dmem_wdata\[30\]
+port 1135 nsew
+rlabel metal3 s 230414 360213 230414 360213 4 u_riscv_top.core1_dmem_wdata\[31\]
+port 1136 nsew
+rlabel metal3 s 230414 367829 230414 367829 4 u_riscv_top.core1_dmem_wdata\[3\]
+port 1137 nsew
+rlabel metal3 s 230414 367557 230414 367557 4 u_riscv_top.core1_dmem_wdata\[4\]
+port 1138 nsew
+rlabel metal3 s 230414 367251 230414 367251 4 u_riscv_top.core1_dmem_wdata\[5\]
+port 1139 nsew
+rlabel metal3 s 230414 366979 230414 366979 4 u_riscv_top.core1_dmem_wdata\[6\]
+port 1140 nsew
+rlabel metal3 s 230414 366741 230414 366741 4 u_riscv_top.core1_dmem_wdata\[7\]
+port 1141 nsew
+rlabel metal3 s 230414 366469 230414 366469 4 u_riscv_top.core1_dmem_wdata\[8\]
+port 1142 nsew
+rlabel metal3 s 230414 366197 230414 366197 4 u_riscv_top.core1_dmem_wdata\[9\]
+port 1143 nsew
+rlabel metal3 s 230414 351203 230414 351203 4 u_riscv_top.core1_dmem_width\[0\]
+port 1144 nsew
+rlabel metal3 s 230414 350931 230414 350931 4 u_riscv_top.core1_dmem_width\[1\]
+port 1145 nsew
+rlabel metal3 s 230414 330293 230414 330293 4 u_riscv_top.core1_imem_addr\[0\]
+port 1146 nsew
+rlabel metal3 s 230414 327573 230414 327573 4 u_riscv_top.core1_imem_addr\[10\]
+port 1147 nsew
+rlabel metal3 s 230414 327267 230414 327267 4 u_riscv_top.core1_imem_addr\[11\]
+port 1148 nsew
+rlabel metal3 s 230414 327029 230414 327029 4 u_riscv_top.core1_imem_addr\[12\]
+port 1149 nsew
+rlabel metal3 s 230414 326723 230414 326723 4 u_riscv_top.core1_imem_addr\[13\]
+port 1150 nsew
+rlabel metal3 s 230414 326451 230414 326451 4 u_riscv_top.core1_imem_addr\[14\]
+port 1151 nsew
+rlabel metal3 s 230414 326213 230414 326213 4 u_riscv_top.core1_imem_addr\[15\]
+port 1152 nsew
+rlabel metal3 s 230414 325941 230414 325941 4 u_riscv_top.core1_imem_addr\[16\]
+port 1153 nsew
+rlabel metal3 s 230414 325635 230414 325635 4 u_riscv_top.core1_imem_addr\[17\]
+port 1154 nsew
+rlabel metal3 s 230414 325397 230414 325397 4 u_riscv_top.core1_imem_addr\[18\]
+port 1155 nsew
+rlabel metal3 s 230414 325125 230414 325125 4 u_riscv_top.core1_imem_addr\[19\]
+port 1156 nsew
+rlabel metal3 s 230414 329987 230414 329987 4 u_riscv_top.core1_imem_addr\[1\]
+port 1157 nsew
+rlabel metal3 s 230414 324853 230414 324853 4 u_riscv_top.core1_imem_addr\[20\]
+port 1158 nsew
+rlabel metal3 s 230414 324581 230414 324581 4 u_riscv_top.core1_imem_addr\[21\]
+port 1159 nsew
+rlabel metal3 s 230414 324275 230414 324275 4 u_riscv_top.core1_imem_addr\[22\]
+port 1160 nsew
+rlabel metal3 s 230414 324037 230414 324037 4 u_riscv_top.core1_imem_addr\[23\]
+port 1161 nsew
+rlabel metal3 s 230414 323765 230414 323765 4 u_riscv_top.core1_imem_addr\[24\]
+port 1162 nsew
+rlabel metal3 s 230414 323493 230414 323493 4 u_riscv_top.core1_imem_addr\[25\]
+port 1163 nsew
+rlabel metal3 s 230414 323187 230414 323187 4 u_riscv_top.core1_imem_addr\[26\]
+port 1164 nsew
+rlabel metal3 s 230414 322949 230414 322949 4 u_riscv_top.core1_imem_addr\[27\]
+port 1165 nsew
+rlabel metal3 s 230414 322677 230414 322677 4 u_riscv_top.core1_imem_addr\[28\]
+port 1166 nsew
+rlabel metal3 s 230414 322405 230414 322405 4 u_riscv_top.core1_imem_addr\[29\]
+port 1167 nsew
+rlabel metal3 s 230414 329749 230414 329749 4 u_riscv_top.core1_imem_addr\[2\]
+port 1168 nsew
+rlabel metal3 s 230414 322133 230414 322133 4 u_riscv_top.core1_imem_addr\[30\]
+port 1169 nsew
+rlabel metal3 s 230414 321827 230414 321827 4 u_riscv_top.core1_imem_addr\[31\]
+port 1170 nsew
+rlabel metal3 s 230414 329443 230414 329443 4 u_riscv_top.core1_imem_addr\[3\]
+port 1171 nsew
+rlabel metal3 s 230414 329171 230414 329171 4 u_riscv_top.core1_imem_addr\[4\]
+port 1172 nsew
+rlabel metal3 s 230414 328899 230414 328899 4 u_riscv_top.core1_imem_addr\[5\]
+port 1173 nsew
+rlabel metal3 s 230414 328627 230414 328627 4 u_riscv_top.core1_imem_addr\[6\]
+port 1174 nsew
+rlabel metal3 s 230414 328389 230414 328389 4 u_riscv_top.core1_imem_addr\[7\]
+port 1175 nsew
+rlabel metal3 s 230414 328117 230414 328117 4 u_riscv_top.core1_imem_addr\[8\]
+port 1176 nsew
+rlabel metal3 s 230414 327845 230414 327845 4 u_riscv_top.core1_imem_addr\[9\]
+port 1177 nsew
+rlabel metal3 s 230414 331075 230414 331075 4 u_riscv_top.core1_imem_bl\[0\]
+port 1178 nsew
+rlabel metal3 s 230414 330837 230414 330837 4 u_riscv_top.core1_imem_bl\[1\]
+port 1179 nsew
+rlabel metal3 s 230414 330565 230414 330565 4 u_riscv_top.core1_imem_bl\[2\]
+port 1180 nsew
+rlabel metal3 s 230414 321589 230414 321589 4 u_riscv_top.core1_imem_cmd
+port 1181 nsew
+rlabel metal3 s 230414 339813 230414 339813 4 u_riscv_top.core1_imem_rdata\[0\]
+port 1182 nsew
+rlabel metal3 s 230414 337093 230414 337093 4 u_riscv_top.core1_imem_rdata\[10\]
+port 1183 nsew
+rlabel metal3 s 230414 336821 230414 336821 4 u_riscv_top.core1_imem_rdata\[11\]
+port 1184 nsew
+rlabel metal3 s 230414 336549 230414 336549 4 u_riscv_top.core1_imem_rdata\[12\]
+port 1185 nsew
+rlabel metal3 s 230414 336277 230414 336277 4 u_riscv_top.core1_imem_rdata\[13\]
+port 1186 nsew
+rlabel metal3 s 230414 336005 230414 336005 4 u_riscv_top.core1_imem_rdata\[14\]
+port 1187 nsew
+rlabel metal3 s 230414 335699 230414 335699 4 u_riscv_top.core1_imem_rdata\[15\]
+port 1188 nsew
+rlabel metal3 s 230414 335461 230414 335461 4 u_riscv_top.core1_imem_rdata\[16\]
+port 1189 nsew
+rlabel metal3 s 230414 335189 230414 335189 4 u_riscv_top.core1_imem_rdata\[17\]
+port 1190 nsew
+rlabel metal3 s 230414 334917 230414 334917 4 u_riscv_top.core1_imem_rdata\[18\]
+port 1191 nsew
+rlabel metal3 s 230414 334645 230414 334645 4 u_riscv_top.core1_imem_rdata\[19\]
+port 1192 nsew
+rlabel metal3 s 230414 339541 230414 339541 4 u_riscv_top.core1_imem_rdata\[1\]
+port 1193 nsew
+rlabel metal3 s 230414 334373 230414 334373 4 u_riscv_top.core1_imem_rdata\[20\]
+port 1194 nsew
+rlabel metal3 s 230414 334101 230414 334101 4 u_riscv_top.core1_imem_rdata\[21\]
+port 1195 nsew
+rlabel metal3 s 230414 333829 230414 333829 4 u_riscv_top.core1_imem_rdata\[22\]
+port 1196 nsew
+rlabel metal3 s 230414 333557 230414 333557 4 u_riscv_top.core1_imem_rdata\[23\]
+port 1197 nsew
+rlabel metal3 s 230414 333285 230414 333285 4 u_riscv_top.core1_imem_rdata\[24\]
+port 1198 nsew
+rlabel metal3 s 230414 333013 230414 333013 4 u_riscv_top.core1_imem_rdata\[25\]
+port 1199 nsew
+rlabel metal3 s 230414 332741 230414 332741 4 u_riscv_top.core1_imem_rdata\[26\]
+port 1200 nsew
+rlabel metal3 s 230414 332469 230414 332469 4 u_riscv_top.core1_imem_rdata\[27\]
+port 1201 nsew
+rlabel metal3 s 230414 332197 230414 332197 4 u_riscv_top.core1_imem_rdata\[28\]
+port 1202 nsew
+rlabel metal3 s 230414 331925 230414 331925 4 u_riscv_top.core1_imem_rdata\[29\]
+port 1203 nsew
+rlabel metal3 s 230414 339269 230414 339269 4 u_riscv_top.core1_imem_rdata\[2\]
+port 1204 nsew
+rlabel metal3 s 230414 331653 230414 331653 4 u_riscv_top.core1_imem_rdata\[30\]
+port 1205 nsew
+rlabel metal3 s 230414 331381 230414 331381 4 u_riscv_top.core1_imem_rdata\[31\]
+port 1206 nsew
+rlabel metal3 s 230414 338997 230414 338997 4 u_riscv_top.core1_imem_rdata\[3\]
+port 1207 nsew
+rlabel metal3 s 230414 338725 230414 338725 4 u_riscv_top.core1_imem_rdata\[4\]
+port 1208 nsew
+rlabel metal3 s 230414 338453 230414 338453 4 u_riscv_top.core1_imem_rdata\[5\]
+port 1209 nsew
+rlabel metal3 s 230414 338181 230414 338181 4 u_riscv_top.core1_imem_rdata\[6\]
+port 1210 nsew
+rlabel metal3 s 230414 337909 230414 337909 4 u_riscv_top.core1_imem_rdata\[7\]
+port 1211 nsew
+rlabel metal3 s 230414 337637 230414 337637 4 u_riscv_top.core1_imem_rdata\[8\]
+port 1212 nsew
+rlabel metal3 s 230414 337365 230414 337365 4 u_riscv_top.core1_imem_rdata\[9\]
+port 1213 nsew
+rlabel metal3 s 230414 321317 230414 321317 4 u_riscv_top.core1_imem_req
+port 1214 nsew
+rlabel metal3 s 230414 321045 230414 321045 4 u_riscv_top.core1_imem_req_ack
+port 1215 nsew
+rlabel metal3 s 230414 340357 230414 340357 4 u_riscv_top.core1_imem_resp\[0\]
+port 1216 nsew
+rlabel metal3 s 230414 340085 230414 340085 4 u_riscv_top.core1_imem_resp\[1\]
+port 1217 nsew
+rlabel metal3 s 230414 426309 230414 426309 4 u_riscv_top.core1_irq_lines\[0\]
+port 1218 nsew
+rlabel metal3 s 230414 423555 230414 423555 4 u_riscv_top.core1_irq_lines\[10\]
+port 1219 nsew
+rlabel metal3 s 230414 423317 230414 423317 4 u_riscv_top.core1_irq_lines\[11\]
+port 1220 nsew
+rlabel metal3 s 230414 423045 230414 423045 4 u_riscv_top.core1_irq_lines\[12\]
+port 1221 nsew
+rlabel metal3 s 230414 422739 230414 422739 4 u_riscv_top.core1_irq_lines\[13\]
+port 1222 nsew
+rlabel metal3 s 230414 422501 230414 422501 4 u_riscv_top.core1_irq_lines\[14\]
+port 1223 nsew
+rlabel metal3 s 230414 422229 230414 422229 4 u_riscv_top.core1_irq_lines\[15\]
+port 1224 nsew
+rlabel metal3 s 230414 421923 230414 421923 4 u_riscv_top.core1_irq_lines\[16\]
+port 1225 nsew
+rlabel metal3 s 230414 421685 230414 421685 4 u_riscv_top.core1_irq_lines\[17\]
+port 1226 nsew
+rlabel metal3 s 230414 421413 230414 421413 4 u_riscv_top.core1_irq_lines\[18\]
+port 1227 nsew
+rlabel metal3 s 230414 421141 230414 421141 4 u_riscv_top.core1_irq_lines\[19\]
+port 1228 nsew
+rlabel metal3 s 230414 426037 230414 426037 4 u_riscv_top.core1_irq_lines\[1\]
+port 1229 nsew
+rlabel metal3 s 230414 420869 230414 420869 4 u_riscv_top.core1_irq_lines\[20\]
+port 1230 nsew
+rlabel metal3 s 230414 420597 230414 420597 4 u_riscv_top.core1_irq_lines\[21\]
+port 1231 nsew
+rlabel metal3 s 230414 420325 230414 420325 4 u_riscv_top.core1_irq_lines\[22\]
+port 1232 nsew
+rlabel metal3 s 230414 420053 230414 420053 4 u_riscv_top.core1_irq_lines\[23\]
+port 1233 nsew
+rlabel metal3 s 230414 419781 230414 419781 4 u_riscv_top.core1_irq_lines\[24\]
+port 1234 nsew
+rlabel metal3 s 230414 419475 230414 419475 4 u_riscv_top.core1_irq_lines\[25\]
+port 1235 nsew
+rlabel metal3 s 230414 419237 230414 419237 4 u_riscv_top.core1_irq_lines\[26\]
+port 1236 nsew
+rlabel metal3 s 230414 418965 230414 418965 4 u_riscv_top.core1_irq_lines\[27\]
+port 1237 nsew
+rlabel metal3 s 230414 418693 230414 418693 4 u_riscv_top.core1_irq_lines\[28\]
+port 1238 nsew
+rlabel metal3 s 230414 418421 230414 418421 4 u_riscv_top.core1_irq_lines\[29\]
+port 1239 nsew
+rlabel metal3 s 230414 425765 230414 425765 4 u_riscv_top.core1_irq_lines\[2\]
+port 1240 nsew
+rlabel metal3 s 230414 418115 230414 418115 4 u_riscv_top.core1_irq_lines\[30\]
+port 1241 nsew
+rlabel metal3 s 230414 417877 230414 417877 4 u_riscv_top.core1_irq_lines\[31\]
+port 1242 nsew
+rlabel metal3 s 230414 425493 230414 425493 4 u_riscv_top.core1_irq_lines\[3\]
+port 1243 nsew
+rlabel metal3 s 230414 425221 230414 425221 4 u_riscv_top.core1_irq_lines\[4\]
+port 1244 nsew
+rlabel metal3 s 230414 424949 230414 424949 4 u_riscv_top.core1_irq_lines\[5\]
+port 1245 nsew
+rlabel metal3 s 230414 424677 230414 424677 4 u_riscv_top.core1_irq_lines\[6\]
+port 1246 nsew
+rlabel metal3 s 230414 424405 230414 424405 4 u_riscv_top.core1_irq_lines\[7\]
+port 1247 nsew
+rlabel metal3 s 230414 424099 230414 424099 4 u_riscv_top.core1_irq_lines\[8\]
+port 1248 nsew
+rlabel metal3 s 230414 423861 230414 423861 4 u_riscv_top.core1_irq_lines\[9\]
+port 1249 nsew
+rlabel metal3 s 230414 426581 230414 426581 4 u_riscv_top.core1_soft_irq
+port 1250 nsew
+rlabel metal3 s 230414 400163 230414 400163 4 u_riscv_top.core1_timer_irq
+port 1251 nsew
+rlabel metal3 s 230414 417605 230414 417605 4 u_riscv_top.core1_timer_val\[0\]
+port 1252 nsew
+rlabel metal3 s 230414 414885 230414 414885 4 u_riscv_top.core1_timer_val\[10\]
+port 1253 nsew
+rlabel metal3 s 230414 414613 230414 414613 4 u_riscv_top.core1_timer_val\[11\]
+port 1254 nsew
+rlabel metal3 s 230414 414341 230414 414341 4 u_riscv_top.core1_timer_val\[12\]
+port 1255 nsew
+rlabel metal3 s 230414 414069 230414 414069 4 u_riscv_top.core1_timer_val\[13\]
+port 1256 nsew
+rlabel metal3 s 230414 413797 230414 413797 4 u_riscv_top.core1_timer_val\[14\]
+port 1257 nsew
+rlabel metal3 s 230414 413525 230414 413525 4 u_riscv_top.core1_timer_val\[15\]
+port 1258 nsew
+rlabel metal3 s 230414 413253 230414 413253 4 u_riscv_top.core1_timer_val\[16\]
+port 1259 nsew
+rlabel metal3 s 230414 412981 230414 412981 4 u_riscv_top.core1_timer_val\[17\]
+port 1260 nsew
+rlabel metal3 s 230414 412709 230414 412709 4 u_riscv_top.core1_timer_val\[18\]
+port 1261 nsew
+rlabel metal3 s 230414 412437 230414 412437 4 u_riscv_top.core1_timer_val\[19\]
+port 1262 nsew
+rlabel metal3 s 230414 417333 230414 417333 4 u_riscv_top.core1_timer_val\[1\]
+port 1263 nsew
+rlabel metal3 s 230414 412165 230414 412165 4 u_riscv_top.core1_timer_val\[20\]
+port 1264 nsew
+rlabel metal3 s 230414 411893 230414 411893 4 u_riscv_top.core1_timer_val\[21\]
+port 1265 nsew
+rlabel metal3 s 230414 411621 230414 411621 4 u_riscv_top.core1_timer_val\[22\]
+port 1266 nsew
+rlabel metal3 s 230414 411315 230414 411315 4 u_riscv_top.core1_timer_val\[23\]
+port 1267 nsew
+rlabel metal3 s 230414 411077 230414 411077 4 u_riscv_top.core1_timer_val\[24\]
+port 1268 nsew
+rlabel metal3 s 230414 410805 230414 410805 4 u_riscv_top.core1_timer_val\[25\]
+port 1269 nsew
+rlabel metal3 s 230414 410533 230414 410533 4 u_riscv_top.core1_timer_val\[26\]
+port 1270 nsew
+rlabel metal3 s 230414 410227 230414 410227 4 u_riscv_top.core1_timer_val\[27\]
+port 1271 nsew
+rlabel metal3 s 230414 409989 230414 409989 4 u_riscv_top.core1_timer_val\[28\]
+port 1272 nsew
+rlabel metal3 s 230414 409717 230414 409717 4 u_riscv_top.core1_timer_val\[29\]
+port 1273 nsew
+rlabel metal3 s 230414 417027 230414 417027 4 u_riscv_top.core1_timer_val\[2\]
+port 1274 nsew
+rlabel metal3 s 230414 409445 230414 409445 4 u_riscv_top.core1_timer_val\[30\]
+port 1275 nsew
+rlabel metal3 s 230414 409173 230414 409173 4 u_riscv_top.core1_timer_val\[31\]
+port 1276 nsew
+rlabel metal3 s 230414 408867 230414 408867 4 u_riscv_top.core1_timer_val\[32\]
+port 1277 nsew
+rlabel metal3 s 230414 408629 230414 408629 4 u_riscv_top.core1_timer_val\[33\]
+port 1278 nsew
+rlabel metal3 s 230414 408357 230414 408357 4 u_riscv_top.core1_timer_val\[34\]
+port 1279 nsew
+rlabel metal3 s 230414 408085 230414 408085 4 u_riscv_top.core1_timer_val\[35\]
+port 1280 nsew
+rlabel metal3 s 230414 407813 230414 407813 4 u_riscv_top.core1_timer_val\[36\]
+port 1281 nsew
+rlabel metal3 s 230414 407541 230414 407541 4 u_riscv_top.core1_timer_val\[37\]
+port 1282 nsew
+rlabel metal3 s 230414 407269 230414 407269 4 u_riscv_top.core1_timer_val\[38\]
+port 1283 nsew
+rlabel metal3 s 230414 406997 230414 406997 4 u_riscv_top.core1_timer_val\[39\]
+port 1284 nsew
+rlabel metal3 s 230414 416789 230414 416789 4 u_riscv_top.core1_timer_val\[3\]
+port 1285 nsew
+rlabel metal3 s 230414 406725 230414 406725 4 u_riscv_top.core1_timer_val\[40\]
+port 1286 nsew
+rlabel metal3 s 230414 406453 230414 406453 4 u_riscv_top.core1_timer_val\[41\]
+port 1287 nsew
+rlabel metal3 s 230414 406181 230414 406181 4 u_riscv_top.core1_timer_val\[42\]
+port 1288 nsew
+rlabel metal3 s 230414 405875 230414 405875 4 u_riscv_top.core1_timer_val\[43\]
+port 1289 nsew
+rlabel metal3 s 230414 405603 230414 405603 4 u_riscv_top.core1_timer_val\[44\]
+port 1290 nsew
+rlabel metal3 s 230414 405365 230414 405365 4 u_riscv_top.core1_timer_val\[45\]
+port 1291 nsew
+rlabel metal3 s 230414 405093 230414 405093 4 u_riscv_top.core1_timer_val\[46\]
+port 1292 nsew
+rlabel metal3 s 230414 404821 230414 404821 4 u_riscv_top.core1_timer_val\[47\]
+port 1293 nsew
+rlabel metal3 s 230414 404515 230414 404515 4 u_riscv_top.core1_timer_val\[48\]
+port 1294 nsew
+rlabel metal3 s 230414 404243 230414 404243 4 u_riscv_top.core1_timer_val\[49\]
+port 1295 nsew
+rlabel metal3 s 230414 416517 230414 416517 4 u_riscv_top.core1_timer_val\[4\]
+port 1296 nsew
+rlabel metal3 s 230414 404005 230414 404005 4 u_riscv_top.core1_timer_val\[50\]
+port 1297 nsew
+rlabel metal3 s 230414 403733 230414 403733 4 u_riscv_top.core1_timer_val\[51\]
+port 1298 nsew
+rlabel metal3 s 230414 403461 230414 403461 4 u_riscv_top.core1_timer_val\[52\]
+port 1299 nsew
+rlabel metal3 s 230414 403189 230414 403189 4 u_riscv_top.core1_timer_val\[53\]
+port 1300 nsew
+rlabel metal3 s 230414 402883 230414 402883 4 u_riscv_top.core1_timer_val\[54\]
+port 1301 nsew
+rlabel metal3 s 230414 402645 230414 402645 4 u_riscv_top.core1_timer_val\[55\]
+port 1302 nsew
+rlabel metal3 s 230414 402373 230414 402373 4 u_riscv_top.core1_timer_val\[56\]
+port 1303 nsew
+rlabel metal3 s 230414 402101 230414 402101 4 u_riscv_top.core1_timer_val\[57\]
+port 1304 nsew
+rlabel metal3 s 230414 401829 230414 401829 4 u_riscv_top.core1_timer_val\[58\]
+port 1305 nsew
+rlabel metal3 s 230414 401557 230414 401557 4 u_riscv_top.core1_timer_val\[59\]
+port 1306 nsew
+rlabel metal3 s 230414 416245 230414 416245 4 u_riscv_top.core1_timer_val\[5\]
+port 1307 nsew
+rlabel metal3 s 230414 401285 230414 401285 4 u_riscv_top.core1_timer_val\[60\]
+port 1308 nsew
+rlabel metal3 s 230414 401013 230414 401013 4 u_riscv_top.core1_timer_val\[61\]
+port 1309 nsew
+rlabel metal3 s 230414 400741 230414 400741 4 u_riscv_top.core1_timer_val\[62\]
+port 1310 nsew
+rlabel metal3 s 230414 400469 230414 400469 4 u_riscv_top.core1_timer_val\[63\]
+port 1311 nsew
+rlabel metal3 s 230414 415973 230414 415973 4 u_riscv_top.core1_timer_val\[6\]
+port 1312 nsew
+rlabel metal3 s 230414 415667 230414 415667 4 u_riscv_top.core1_timer_val\[7\]
+port 1313 nsew
+rlabel metal3 s 230414 415429 230414 415429 4 u_riscv_top.core1_timer_val\[8\]
+port 1314 nsew
+rlabel metal3 s 230414 415157 230414 415157 4 u_riscv_top.core1_timer_val\[9\]
+port 1315 nsew
+rlabel metal3 s 230414 320773 230414 320773 4 u_riscv_top.core1_uid\[0\]
+port 1316 nsew
+rlabel metal3 s 230414 320467 230414 320467 4 u_riscv_top.core1_uid\[1\]
+port 1317 nsew
+rlabel metal2 s 135194 532610 135194 532610 4 u_riscv_top.core2_clk
+port 1318 nsew
+rlabel metal2 s 133906 605846 133906 605846 4 u_riscv_top.core2_debug\[0\]
+port 1319 nsew
+rlabel metal2 s 135102 603194 135102 603194 4 u_riscv_top.core2_debug\[10\]
+port 1320 nsew
+rlabel metal2 s 136482 602378 136482 602378 4 u_riscv_top.core2_debug\[11\]
+port 1321 nsew
+rlabel metal2 s 135746 602412 135746 602412 4 u_riscv_top.core2_debug\[12\]
+port 1322 nsew
+rlabel metal2 s 136298 602344 136298 602344 4 u_riscv_top.core2_debug\[13\]
+port 1323 nsew
+rlabel metal2 s 136206 602242 136206 602242 4 u_riscv_top.core2_debug\[14\]
+port 1324 nsew
+rlabel metal2 s 134918 601834 134918 601834 4 u_riscv_top.core2_debug\[15\]
+port 1325 nsew
+rlabel metal2 s 136022 600984 136022 600984 4 u_riscv_top.core2_debug\[16\]
+port 1326 nsew
+rlabel metal2 s 136114 601018 136114 601018 4 u_riscv_top.core2_debug\[17\]
+port 1327 nsew
+rlabel metal2 s 135562 600950 135562 600950 4 u_riscv_top.core2_debug\[18\]
+port 1328 nsew
+rlabel metal2 s 135930 600814 135930 600814 4 u_riscv_top.core2_debug\[19\]
+port 1329 nsew
+rlabel metal2 s 136574 604996 136574 604996 4 u_riscv_top.core2_debug\[1\]
+port 1330 nsew
+rlabel metal2 s 135010 600440 135010 600440 4 u_riscv_top.core2_debug\[20\]
+port 1331 nsew
+rlabel metal3 s 124192 602548 124192 602548 4 u_riscv_top.core2_debug\[21\]
+port 1332 nsew
+rlabel metal3 s 123824 602276 123824 602276 4 u_riscv_top.core2_debug\[22\]
+port 1333 nsew
+rlabel metal3 s 124146 602004 124146 602004 4 u_riscv_top.core2_debug\[23\]
+port 1334 nsew
+rlabel metal3 s 124192 601732 124192 601732 4 u_riscv_top.core2_debug\[24\]
+port 1335 nsew
+rlabel metal2 s 134734 598978 134734 598978 4 u_riscv_top.core2_debug\[25\]
+port 1336 nsew
+rlabel metal3 s 124008 601188 124008 601188 4 u_riscv_top.core2_debug\[26\]
+port 1337 nsew
+rlabel metal3 s 123778 600916 123778 600916 4 u_riscv_top.core2_debug\[27\]
+port 1338 nsew
+rlabel metal3 s 123732 600644 123732 600644 4 u_riscv_top.core2_debug\[28\]
+port 1339 nsew
+rlabel metal3 s 124192 600372 124192 600372 4 u_riscv_top.core2_debug\[29\]
+port 1340 nsew
+rlabel metal2 s 134274 605166 134274 605166 4 u_riscv_top.core2_debug\[2\]
+port 1341 nsew
+rlabel metal2 s 134918 597516 134918 597516 4 u_riscv_top.core2_debug\[30\]
+port 1342 nsew
+rlabel metal2 s 135102 597584 135102 597584 4 u_riscv_top.core2_debug\[31\]
+port 1343 nsew
+rlabel metal2 s 136482 596870 136482 596870 4 u_riscv_top.core2_debug\[32\]
+port 1344 nsew
+rlabel metal2 s 136390 596836 136390 596836 4 u_riscv_top.core2_debug\[33\]
+port 1345 nsew
+rlabel metal2 s 135838 596836 135838 596836 4 u_riscv_top.core2_debug\[34\]
+port 1346 nsew
+rlabel metal2 s 134366 596122 134366 596122 4 u_riscv_top.core2_debug\[35\]
+port 1347 nsew
+rlabel metal2 s 134274 596224 134274 596224 4 u_riscv_top.core2_debug\[36\]
+port 1348 nsew
+rlabel metal3 s 124100 598196 124100 598196 4 u_riscv_top.core2_debug\[37\]
+port 1349 nsew
+rlabel metal3 s 124146 597924 124146 597924 4 u_riscv_top.core2_debug\[38\]
+port 1350 nsew
+rlabel metal3 s 124192 597652 124192 597652 4 u_riscv_top.core2_debug\[39\]
+port 1351 nsew
+rlabel metal2 s 134458 605166 134458 605166 4 u_riscv_top.core2_debug\[3\]
+port 1352 nsew
+rlabel metal2 s 134182 594864 134182 594864 4 u_riscv_top.core2_debug\[40\]
+port 1353 nsew
+rlabel metal2 s 133998 594864 133998 594864 4 u_riscv_top.core2_debug\[41\]
+port 1354 nsew
+rlabel metal2 s 136114 594082 136114 594082 4 u_riscv_top.core2_debug\[42\]
+port 1355 nsew
+rlabel metal2 s 136022 594014 136022 594014 4 u_riscv_top.core2_debug\[43\]
+port 1356 nsew
+rlabel metal2 s 135930 593946 135930 593946 4 u_riscv_top.core2_debug\[44\]
+port 1357 nsew
+rlabel metal2 s 135102 593470 135102 593470 4 u_riscv_top.core2_debug\[45\]
+port 1358 nsew
+rlabel metal2 s 135194 593470 135194 593470 4 u_riscv_top.core2_debug\[46\]
+port 1359 nsew
+rlabel metal2 s 135746 592756 135746 592756 4 u_riscv_top.core2_debug\[47\]
+port 1360 nsew
+rlabel metal2 s 136574 592688 136574 592688 4 u_riscv_top.core2_debug\[48\]
+port 1361 nsew
+rlabel metal2 s 134090 604486 134090 604486 4 u_riscv_top.core2_debug\[4\]
+port 1362 nsew
+rlabel metal2 s 133998 604554 133998 604554 4 u_riscv_top.core2_debug\[5\]
+port 1363 nsew
+rlabel metal3 s 123824 606628 123824 606628 4 u_riscv_top.core2_debug\[6\]
+port 1364 nsew
+rlabel metal3 s 124146 606356 124146 606356 4 u_riscv_top.core2_debug\[7\]
+port 1365 nsew
+rlabel metal2 s 136390 603738 136390 603738 4 u_riscv_top.core2_debug\[8\]
+port 1366 nsew
+rlabel metal2 s 135194 603194 135194 603194 4 u_riscv_top.core2_debug\[9\]
+port 1367 nsew
+rlabel metal2 s 135746 571982 135746 571982 4 u_riscv_top.core2_dmem_addr\[0\]
+port 1368 nsew
+rlabel metal2 s 134826 569942 134826 569942 4 u_riscv_top.core2_dmem_addr\[10\]
+port 1369 nsew
+rlabel metal2 s 136574 569194 136574 569194 4 u_riscv_top.core2_dmem_addr\[11\]
+port 1370 nsew
+rlabel metal2 s 135838 569194 135838 569194 4 u_riscv_top.core2_dmem_addr\[12\]
+port 1371 nsew
+rlabel metal2 s 135562 569194 135562 569194 4 u_riscv_top.core2_dmem_addr\[13\]
+port 1372 nsew
+rlabel metal2 s 134274 568616 134274 568616 4 u_riscv_top.core2_dmem_addr\[14\]
+port 1373 nsew
+rlabel metal2 s 134366 568684 134366 568684 4 u_riscv_top.core2_dmem_addr\[15\]
+port 1374 nsew
+rlabel metal2 s 136390 567868 136390 567868 4 u_riscv_top.core2_dmem_addr\[16\]
+port 1375 nsew
+rlabel metal2 s 136206 567766 136206 567766 4 u_riscv_top.core2_dmem_addr\[17\]
+port 1376 nsew
+rlabel metal2 s 136482 567766 136482 567766 4 u_riscv_top.core2_dmem_addr\[18\]
+port 1377 nsew
+rlabel metal2 s 133906 567256 133906 567256 4 u_riscv_top.core2_dmem_addr\[19\]
+port 1378 nsew
+rlabel metal2 s 136298 571982 136298 571982 4 u_riscv_top.core2_dmem_addr\[1\]
+port 1379 nsew
+rlabel metal2 s 133998 567324 133998 567324 4 u_riscv_top.core2_dmem_addr\[20\]
+port 1380 nsew
+rlabel metal2 s 136114 566440 136114 566440 4 u_riscv_top.core2_dmem_addr\[21\]
+port 1381 nsew
+rlabel metal2 s 136298 566406 136298 566406 4 u_riscv_top.core2_dmem_addr\[22\]
+port 1382 nsew
+rlabel metal2 s 136022 566372 136022 566372 4 u_riscv_top.core2_dmem_addr\[23\]
+port 1383 nsew
+rlabel metal2 s 134458 565896 134458 565896 4 u_riscv_top.core2_dmem_addr\[24\]
+port 1384 nsew
+rlabel metal2 s 134642 565896 134642 565896 4 u_riscv_top.core2_dmem_addr\[25\]
+port 1385 nsew
+rlabel metal3 s 145092 562836 145092 562836 4 u_riscv_top.core2_dmem_addr\[26\]
+port 1386 nsew
+rlabel metal3 s 145184 562564 145184 562564 4 u_riscv_top.core2_dmem_addr\[27\]
+port 1387 nsew
+rlabel metal3 s 145046 562292 145046 562292 4 u_riscv_top.core2_dmem_addr\[28\]
+port 1388 nsew
+rlabel metal2 s 134550 564502 134550 564502 4 u_riscv_top.core2_dmem_addr\[29\]
+port 1389 nsew
+rlabel metal2 s 135470 571948 135470 571948 4 u_riscv_top.core2_dmem_addr\[2\]
+port 1390 nsew
+rlabel metal2 s 134734 564400 134734 564400 4 u_riscv_top.core2_dmem_addr\[30\]
+port 1391 nsew
+rlabel metal3 s 124100 566508 124100 566508 4 u_riscv_top.core2_dmem_addr\[31\]
+port 1392 nsew
+rlabel metal3 s 124192 574124 124192 574124 4 u_riscv_top.core2_dmem_addr\[3\]
+port 1393 nsew
+rlabel metal2 s 135194 571370 135194 571370 4 u_riscv_top.core2_dmem_addr\[4\]
+port 1394 nsew
+rlabel metal2 s 134182 570656 134182 570656 4 u_riscv_top.core2_dmem_addr\[5\]
+port 1395 nsew
+rlabel metal2 s 134918 570758 134918 570758 4 u_riscv_top.core2_dmem_addr\[6\]
+port 1396 nsew
+rlabel metal2 s 134734 570520 134734 570520 4 u_riscv_top.core2_dmem_addr\[7\]
+port 1397 nsew
+rlabel metal2 s 135930 570452 135930 570452 4 u_riscv_top.core2_dmem_addr\[8\]
+port 1398 nsew
+rlabel metal2 s 135102 570044 135102 570044 4 u_riscv_top.core2_dmem_addr\[9\]
+port 1399 nsew
+rlabel metal2 s 134826 562938 134826 562938 4 u_riscv_top.core2_dmem_cmd
+port 1400 nsew
+rlabel metal3 s 124146 592348 124146 592348 4 u_riscv_top.core2_dmem_rdata\[0\]
+port 1401 nsew
+rlabel metal2 s 135654 587112 135654 587112 4 u_riscv_top.core2_dmem_rdata\[10\]
+port 1402 nsew
+rlabel metal2 s 136390 587112 136390 587112 4 u_riscv_top.core2_dmem_rdata\[11\]
+port 1403 nsew
+rlabel metal2 s 133906 586636 133906 586636 4 u_riscv_top.core2_dmem_rdata\[12\]
+port 1404 nsew
+rlabel metal2 s 134182 586534 134182 586534 4 u_riscv_top.core2_dmem_rdata\[13\]
+port 1405 nsew
+rlabel metal2 s 136114 585752 136114 585752 4 u_riscv_top.core2_dmem_rdata\[14\]
+port 1406 nsew
+rlabel metal2 s 135746 585718 135746 585718 4 u_riscv_top.core2_dmem_rdata\[15\]
+port 1407 nsew
+rlabel metal2 s 135838 585684 135838 585684 4 u_riscv_top.core2_dmem_rdata\[16\]
+port 1408 nsew
+rlabel metal2 s 134274 585174 134274 585174 4 u_riscv_top.core2_dmem_rdata\[17\]
+port 1409 nsew
+rlabel metal2 s 134366 585242 134366 585242 4 u_riscv_top.core2_dmem_rdata\[18\]
+port 1410 nsew
+rlabel metal2 s 136482 584426 136482 584426 4 u_riscv_top.core2_dmem_rdata\[19\]
+port 1411 nsew
+rlabel metal3 s 124192 592076 124192 592076 4 u_riscv_top.core2_dmem_rdata\[1\]
+port 1412 nsew
+rlabel metal2 s 136298 584358 136298 584358 4 u_riscv_top.core2_dmem_rdata\[20\]
+port 1413 nsew
+rlabel metal2 s 136022 584290 136022 584290 4 u_riscv_top.core2_dmem_rdata\[21\]
+port 1414 nsew
+rlabel metal2 s 133998 583882 133998 583882 4 u_riscv_top.core2_dmem_rdata\[22\]
+port 1415 nsew
+rlabel metal2 s 135194 583814 135194 583814 4 u_riscv_top.core2_dmem_rdata\[23\]
+port 1416 nsew
+rlabel metal2 s 136574 583066 136574 583066 4 u_riscv_top.core2_dmem_rdata\[24\]
+port 1417 nsew
+rlabel metal2 s 135562 583100 135562 583100 4 u_riscv_top.core2_dmem_rdata\[25\]
+port 1418 nsew
+rlabel metal3 s 124192 585276 124192 585276 4 u_riscv_top.core2_dmem_rdata\[26\]
+port 1419 nsew
+rlabel metal2 s 134918 582420 134918 582420 4 u_riscv_top.core2_dmem_rdata\[27\]
+port 1420 nsew
+rlabel metal2 s 134826 582352 134826 582352 4 u_riscv_top.core2_dmem_rdata\[28\]
+port 1421 nsew
+rlabel metal3 s 124146 584460 124146 584460 4 u_riscv_top.core2_dmem_rdata\[29\]
+port 1422 nsew
+rlabel metal2 s 135194 589356 135194 589356 4 u_riscv_top.core2_dmem_rdata\[2\]
+port 1423 nsew
+rlabel metal3 s 123778 584188 123778 584188 4 u_riscv_top.core2_dmem_rdata\[30\]
+port 1424 nsew
+rlabel metal3 s 124192 583916 124192 583916 4 u_riscv_top.core2_dmem_rdata\[31\]
+port 1425 nsew
+rlabel metal2 s 134918 589288 134918 589288 4 u_riscv_top.core2_dmem_rdata\[3\]
+port 1426 nsew
+rlabel metal2 s 135930 588540 135930 588540 4 u_riscv_top.core2_dmem_rdata\[4\]
+port 1427 nsew
+rlabel metal2 s 135562 588540 135562 588540 4 u_riscv_top.core2_dmem_rdata\[5\]
+port 1428 nsew
+rlabel metal3 s 145644 585684 145644 585684 4 u_riscv_top.core2_dmem_rdata\[6\]
+port 1429 nsew
+rlabel metal2 s 135194 586449 135194 586449 4 u_riscv_top.core2_dmem_rdata\[7\]
+port 1430 nsew
+rlabel metal2 s 134458 587996 134458 587996 4 u_riscv_top.core2_dmem_rdata\[8\]
+port 1431 nsew
+rlabel metal2 s 134550 587316 134550 587316 4 u_riscv_top.core2_dmem_rdata\[9\]
+port 1432 nsew
+rlabel metal2 s 135194 563040 135194 563040 4 u_riscv_top.core2_dmem_req
+port 1433 nsew
+rlabel metal2 s 136574 562326 136574 562326 4 u_riscv_top.core2_dmem_req_ack
+port 1434 nsew
+rlabel metal2 s 135470 589968 135470 589968 4 u_riscv_top.core2_dmem_resp\[0\]
+port 1435 nsew
+rlabel metal2 s 136482 589968 136482 589968 4 u_riscv_top.core2_dmem_resp\[1\]
+port 1436 nsew
+rlabel metal2 s 134090 581060 134090 581060 4 u_riscv_top.core2_dmem_wdata\[0\]
+port 1437 nsew
+rlabel metal2 s 134734 578374 134734 578374 4 u_riscv_top.core2_dmem_wdata\[10\]
+port 1438 nsew
+rlabel metal2 s 134918 578306 134918 578306 4 u_riscv_top.core2_dmem_wdata\[11\]
+port 1439 nsew
+rlabel metal3 s 124146 580380 124146 580380 4 u_riscv_top.core2_dmem_wdata\[12\]
+port 1440 nsew
+rlabel metal3 s 123732 580108 123732 580108 4 u_riscv_top.core2_dmem_wdata\[13\]
+port 1441 nsew
+rlabel metal3 s 124192 579836 124192 579836 4 u_riscv_top.core2_dmem_wdata\[14\]
+port 1442 nsew
+rlabel metal2 s 133906 576878 133906 576878 4 u_riscv_top.core2_dmem_wdata\[15\]
+port 1443 nsew
+rlabel metal2 s 134274 576810 134274 576810 4 u_riscv_top.core2_dmem_wdata\[16\]
+port 1444 nsew
+rlabel metal2 s 136574 576062 136574 576062 4 u_riscv_top.core2_dmem_wdata\[17\]
+port 1445 nsew
+rlabel metal2 s 136482 576062 136482 576062 4 u_riscv_top.core2_dmem_wdata\[18\]
+port 1446 nsew
+rlabel metal2 s 136206 576062 136206 576062 4 u_riscv_top.core2_dmem_wdata\[19\]
+port 1447 nsew
+rlabel metal2 s 135010 580958 135010 580958 4 u_riscv_top.core2_dmem_wdata\[1\]
+port 1448 nsew
+rlabel metal2 s 134090 575620 134090 575620 4 u_riscv_top.core2_dmem_wdata\[20\]
+port 1449 nsew
+rlabel metal2 s 134182 575552 134182 575552 4 u_riscv_top.core2_dmem_wdata\[21\]
+port 1450 nsew
+rlabel metal2 s 140070 574872 140070 574872 4 u_riscv_top.core2_dmem_wdata\[22\]
+port 1451 nsew
+rlabel metal2 s 139978 574804 139978 574804 4 u_riscv_top.core2_dmem_wdata\[23\]
+port 1452 nsew
+rlabel metal2 s 140162 574736 140162 574736 4 u_riscv_top.core2_dmem_wdata\[24\]
+port 1453 nsew
+rlabel metal2 s 139886 574668 139886 574668 4 u_riscv_top.core2_dmem_wdata\[25\]
+port 1454 nsew
+rlabel metal2 s 135102 574090 135102 574090 4 u_riscv_top.core2_dmem_wdata\[26\]
+port 1455 nsew
+rlabel metal3 s 123916 576300 123916 576300 4 u_riscv_top.core2_dmem_wdata\[27\]
+port 1456 nsew
+rlabel metal3 s 123824 576028 123824 576028 4 u_riscv_top.core2_dmem_wdata\[28\]
+port 1457 nsew
+rlabel metal3 s 124192 575756 124192 575756 4 u_riscv_top.core2_dmem_wdata\[29\]
+port 1458 nsew
+rlabel metal3 s 123870 583100 123870 583100 4 u_riscv_top.core2_dmem_wdata\[2\]
+port 1459 nsew
+rlabel metal3 s 124192 575484 124192 575484 4 u_riscv_top.core2_dmem_wdata\[30\]
+port 1460 nsew
+rlabel metal2 s 135010 572832 135010 572832 4 u_riscv_top.core2_dmem_wdata\[31\]
+port 1461 nsew
+rlabel metal3 s 124100 582828 124100 582828 4 u_riscv_top.core2_dmem_wdata\[3\]
+port 1462 nsew
+rlabel metal2 s 134550 580346 134550 580346 4 u_riscv_top.core2_dmem_wdata\[4\]
+port 1463 nsew
+rlabel metal2 s 135194 579632 135194 579632 4 u_riscv_top.core2_dmem_wdata\[5\]
+port 1464 nsew
+rlabel metal2 s 135102 579598 135102 579598 4 u_riscv_top.core2_dmem_wdata\[6\]
+port 1465 nsew
+rlabel metal2 s 136390 578884 136390 578884 4 u_riscv_top.core2_dmem_wdata\[7\]
+port 1466 nsew
+rlabel metal2 s 136298 578816 136298 578816 4 u_riscv_top.core2_dmem_wdata\[8\]
+port 1467 nsew
+rlabel metal2 s 135930 578850 135930 578850 4 u_riscv_top.core2_dmem_wdata\[9\]
+port 1468 nsew
+rlabel metal3 s 123732 566236 123732 566236 4 u_riscv_top.core2_dmem_width\[0\]
+port 1469 nsew
+rlabel metal3 s 124192 565964 124192 565964 4 u_riscv_top.core2_dmem_width\[1\]
+port 1470 nsew
+rlabel metal2 s 135930 542912 135930 542912 4 u_riscv_top.core2_imem_addr\[0\]
+port 1471 nsew
+rlabel metal2 s 135562 540158 135562 540158 4 u_riscv_top.core2_imem_addr\[10\]
+port 1472 nsew
+rlabel metal2 s 134366 539614 134366 539614 4 u_riscv_top.core2_imem_addr\[11\]
+port 1473 nsew
+rlabel metal2 s 134458 539682 134458 539682 4 u_riscv_top.core2_imem_addr\[12\]
+port 1474 nsew
+rlabel metal2 s 135838 538832 135838 538832 4 u_riscv_top.core2_imem_addr\[13\]
+port 1475 nsew
+rlabel metal2 s 136574 538832 136574 538832 4 u_riscv_top.core2_imem_addr\[14\]
+port 1476 nsew
+rlabel metal2 s 136206 538730 136206 538730 4 u_riscv_top.core2_imem_addr\[15\]
+port 1477 nsew
+rlabel metal2 s 134182 538322 134182 538322 4 u_riscv_top.core2_imem_addr\[16\]
+port 1478 nsew
+rlabel metal2 s 133906 538322 133906 538322 4 u_riscv_top.core2_imem_addr\[17\]
+port 1479 nsew
+rlabel metal2 s 136114 537506 136114 537506 4 u_riscv_top.core2_imem_addr\[18\]
+port 1480 nsew
+rlabel metal2 s 136298 537472 136298 537472 4 u_riscv_top.core2_imem_addr\[19\]
+port 1481 nsew
+rlabel metal2 s 135102 542470 135102 542470 4 u_riscv_top.core2_imem_addr\[1\]
+port 1482 nsew
+rlabel metal2 s 135930 537472 135930 537472 4 u_riscv_top.core2_imem_addr\[20\]
+port 1483 nsew
+rlabel metal2 s 136022 537438 136022 537438 4 u_riscv_top.core2_imem_addr\[21\]
+port 1484 nsew
+rlabel metal2 s 134090 536894 134090 536894 4 u_riscv_top.core2_imem_addr\[22\]
+port 1485 nsew
+rlabel metal2 s 136482 536078 136482 536078 4 u_riscv_top.core2_imem_addr\[23\]
+port 1486 nsew
+rlabel metal2 s 136390 536010 136390 536010 4 u_riscv_top.core2_imem_addr\[24\]
+port 1487 nsew
+rlabel metal2 s 134274 536282 134274 536282 4 u_riscv_top.core2_imem_addr\[25\]
+port 1488 nsew
+rlabel metal2 s 134642 536214 134642 536214 4 u_riscv_top.core2_imem_addr\[26\]
+port 1489 nsew
+rlabel metal2 s 135010 535500 135010 535500 4 u_riscv_top.core2_imem_addr\[27\]
+port 1490 nsew
+rlabel metal3 s 124100 537676 124100 537676 4 u_riscv_top.core2_imem_addr\[28\]
+port 1491 nsew
+rlabel metal3 s 123824 537404 123824 537404 4 u_riscv_top.core2_imem_addr\[29\]
+port 1492 nsew
+rlabel metal2 s 134642 542402 134642 542402 4 u_riscv_top.core2_imem_addr\[2\]
+port 1493 nsew
+rlabel metal3 s 124192 537132 124192 537132 4 u_riscv_top.core2_imem_addr\[30\]
+port 1494 nsew
+rlabel metal3 s 124146 536860 124146 536860 4 u_riscv_top.core2_imem_addr\[31\]
+port 1495 nsew
+rlabel metal2 s 136482 541654 136482 541654 4 u_riscv_top.core2_imem_addr\[3\]
+port 1496 nsew
+rlabel metal2 s 135378 541586 135378 541586 4 u_riscv_top.core2_imem_addr\[4\]
+port 1497 nsew
+rlabel metal3 s 124192 543932 124192 543932 4 u_riscv_top.core2_imem_addr\[5\]
+port 1498 nsew
+rlabel metal2 s 135194 541076 135194 541076 4 u_riscv_top.core2_imem_addr\[6\]
+port 1499 nsew
+rlabel metal2 s 134734 541008 134734 541008 4 u_riscv_top.core2_imem_addr\[7\]
+port 1500 nsew
+rlabel metal2 s 134826 540328 134826 540328 4 u_riscv_top.core2_imem_addr\[8\]
+port 1501 nsew
+rlabel metal2 s 134550 540328 134550 540328 4 u_riscv_top.core2_imem_addr\[9\]
+port 1502 nsew
+rlabel metal2 s 135010 543728 135010 543728 4 u_riscv_top.core2_imem_bl\[0\]
+port 1503 nsew
+rlabel metal3 s 124146 545836 124146 545836 4 u_riscv_top.core2_imem_bl\[1\]
+port 1504 nsew
+rlabel metal3 s 123732 545564 123732 545564 4 u_riscv_top.core2_imem_bl\[2\]
+port 1505 nsew
+rlabel metal2 s 135102 534140 135102 534140 4 u_riscv_top.core2_imem_cmd
+port 1506 nsew
+rlabel metal2 s 136114 552568 136114 552568 4 u_riscv_top.core2_imem_rdata\[0\]
+port 1507 nsew
+rlabel metal2 s 135930 549814 135930 549814 4 u_riscv_top.core2_imem_rdata\[10\]
+port 1508 nsew
+rlabel metal2 s 135010 549304 135010 549304 4 u_riscv_top.core2_imem_rdata\[11\]
+port 1509 nsew
+rlabel metal2 s 134826 549882 134826 549882 4 u_riscv_top.core2_imem_rdata\[12\]
+port 1510 nsew
+rlabel metal2 s 135746 548454 135746 548454 4 u_riscv_top.core2_imem_rdata\[13\]
+port 1511 nsew
+rlabel metal2 s 136298 550409 136298 550409 4 u_riscv_top.core2_imem_rdata\[14\]
+port 1512 nsew
+rlabel metal2 s 135838 548454 135838 548454 4 u_riscv_top.core2_imem_rdata\[15\]
+port 1513 nsew
+rlabel metal2 s 133998 547944 133998 547944 4 u_riscv_top.core2_imem_rdata\[16\]
+port 1514 nsew
+rlabel metal2 s 133906 547944 133906 547944 4 u_riscv_top.core2_imem_rdata\[17\]
+port 1515 nsew
+rlabel metal2 s 136298 547128 136298 547128 4 u_riscv_top.core2_imem_rdata\[18\]
+port 1516 nsew
+rlabel metal2 s 136574 547094 136574 547094 4 u_riscv_top.core2_imem_rdata\[19\]
+port 1517 nsew
+rlabel metal2 s 135194 552126 135194 552126 4 u_riscv_top.core2_imem_rdata\[1\]
+port 1518 nsew
+rlabel metal2 s 136022 547060 136022 547060 4 u_riscv_top.core2_imem_rdata\[20\]
+port 1519 nsew
+rlabel metal2 s 134182 546584 134182 546584 4 u_riscv_top.core2_imem_rdata\[21\]
+port 1520 nsew
+rlabel metal2 s 134366 546584 134366 546584 4 u_riscv_top.core2_imem_rdata\[22\]
+port 1521 nsew
+rlabel metal2 s 136206 545768 136206 545768 4 u_riscv_top.core2_imem_rdata\[23\]
+port 1522 nsew
+rlabel metal2 s 136390 545734 136390 545734 4 u_riscv_top.core2_imem_rdata\[24\]
+port 1523 nsew
+rlabel metal2 s 136114 545700 136114 545700 4 u_riscv_top.core2_imem_rdata\[25\]
+port 1524 nsew
+rlabel metal2 s 135194 545224 135194 545224 4 u_riscv_top.core2_imem_rdata\[26\]
+port 1525 nsew
+rlabel metal2 s 134826 545156 134826 545156 4 u_riscv_top.core2_imem_rdata\[27\]
+port 1526 nsew
+rlabel metal3 s 124146 547196 124146 547196 4 u_riscv_top.core2_imem_rdata\[28\]
+port 1527 nsew
+rlabel metal3 s 124054 546924 124054 546924 4 u_riscv_top.core2_imem_rdata\[29\]
+port 1528 nsew
+rlabel metal2 s 135654 551310 135654 551310 4 u_riscv_top.core2_imem_rdata\[2\]
+port 1529 nsew
+rlabel metal3 s 124192 546652 124192 546652 4 u_riscv_top.core2_imem_rdata\[30\]
+port 1530 nsew
+rlabel metal2 s 134918 543728 134918 543728 4 u_riscv_top.core2_imem_rdata\[31\]
+port 1531 nsew
+rlabel metal2 s 135470 551242 135470 551242 4 u_riscv_top.core2_imem_rdata\[3\]
+port 1532 nsew
+rlabel metal2 s 136206 551310 136206 551310 4 u_riscv_top.core2_imem_rdata\[4\]
+port 1533 nsew
+rlabel metal3 s 124192 553452 124192 553452 4 u_riscv_top.core2_imem_rdata\[5\]
+port 1534 nsew
+rlabel metal2 s 134918 550766 134918 550766 4 u_riscv_top.core2_imem_rdata\[6\]
+port 1535 nsew
+rlabel metal2 s 135102 550596 135102 550596 4 u_riscv_top.core2_imem_rdata\[7\]
+port 1536 nsew
+rlabel metal2 s 134550 550018 134550 550018 4 u_riscv_top.core2_imem_rdata\[8\]
+port 1537 nsew
+rlabel metal2 s 134642 550018 134642 550018 4 u_riscv_top.core2_imem_rdata\[9\]
+port 1538 nsew
+rlabel metal3 s 124100 536316 124100 536316 4 u_riscv_top.core2_imem_req
+port 1539 nsew
+rlabel metal3 s 124054 536044 124054 536044 4 u_riscv_top.core2_imem_req_ack
+port 1540 nsew
+rlabel metal2 s 136574 552602 136574 552602 4 u_riscv_top.core2_imem_resp\[0\]
+port 1541 nsew
+rlabel metal2 s 136482 552568 136482 552568 4 u_riscv_top.core2_imem_resp\[1\]
+port 1542 nsew
+rlabel metal2 s 135102 638996 135102 638996 4 u_riscv_top.core2_irq_lines\[0\]
+port 1543 nsew
+rlabel metal2 s 134550 636905 134550 636905 4 u_riscv_top.core2_irq_lines\[10\]
+port 1544 nsew
+rlabel metal2 s 136022 636718 136022 636718 4 u_riscv_top.core2_irq_lines\[11\]
+port 1545 nsew
+rlabel metal2 s 136298 636735 136298 636735 4 u_riscv_top.core2_irq_lines\[12\]
+port 1546 nsew
+rlabel metal2 s 135838 635426 135838 635426 4 u_riscv_top.core2_irq_lines\[13\]
+port 1547 nsew
+rlabel metal2 s 133906 634882 133906 634882 4 u_riscv_top.core2_irq_lines\[14\]
+port 1548 nsew
+rlabel metal2 s 134734 634916 134734 634916 4 u_riscv_top.core2_irq_lines\[15\]
+port 1549 nsew
+rlabel metal2 s 136114 634100 136114 634100 4 u_riscv_top.core2_irq_lines\[16\]
+port 1550 nsew
+rlabel metal2 s 135470 634100 135470 634100 4 u_riscv_top.core2_irq_lines\[17\]
+port 1551 nsew
+rlabel metal2 s 135654 634032 135654 634032 4 u_riscv_top.core2_irq_lines\[18\]
+port 1552 nsew
+rlabel metal2 s 133998 633522 133998 633522 4 u_riscv_top.core2_irq_lines\[19\]
+port 1553 nsew
+rlabel metal2 s 136574 638146 136574 638146 4 u_riscv_top.core2_irq_lines\[1\]
+port 1554 nsew
+rlabel metal2 s 134090 633454 134090 633454 4 u_riscv_top.core2_irq_lines\[20\]
+port 1555 nsew
+rlabel metal2 s 135562 632706 135562 632706 4 u_riscv_top.core2_irq_lines\[21\]
+port 1556 nsew
+rlabel metal2 s 136022 632672 136022 632672 4 u_riscv_top.core2_irq_lines\[22\]
+port 1557 nsew
+rlabel metal2 s 135746 632604 135746 632604 4 u_riscv_top.core2_irq_lines\[23\]
+port 1558 nsew
+rlabel metal2 s 135010 632196 135010 632196 4 u_riscv_top.core2_irq_lines\[24\]
+port 1559 nsew
+rlabel metal2 s 134918 632128 134918 632128 4 u_riscv_top.core2_irq_lines\[25\]
+port 1560 nsew
+rlabel metal3 s 124054 634236 124054 634236 4 u_riscv_top.core2_irq_lines\[26\]
+port 1561 nsew
+rlabel metal3 s 124146 633964 124146 633964 4 u_riscv_top.core2_irq_lines\[27\]
+port 1562 nsew
+rlabel metal2 s 136206 631448 136206 631448 4 u_riscv_top.core2_irq_lines\[28\]
+port 1563 nsew
+rlabel metal3 s 124192 633420 124192 633420 4 u_riscv_top.core2_irq_lines\[29\]
+port 1564 nsew
+rlabel metal2 s 136482 638248 136482 638248 4 u_riscv_top.core2_irq_lines\[2\]
+port 1565 nsew
+rlabel metal2 s 135102 630734 135102 630734 4 u_riscv_top.core2_irq_lines\[30\]
+port 1566 nsew
+rlabel metal3 s 123870 632876 123870 632876 4 u_riscv_top.core2_irq_lines\[31\]
+port 1567 nsew
+rlabel metal2 s 135930 638146 135930 638146 4 u_riscv_top.core2_irq_lines\[3\]
+port 1568 nsew
+rlabel metal2 s 135194 637568 135194 637568 4 u_riscv_top.core2_irq_lines\[4\]
+port 1569 nsew
+rlabel metal2 s 134458 637704 134458 637704 4 u_riscv_top.core2_irq_lines\[5\]
+port 1570 nsew
+rlabel metal2 s 136206 636718 136206 636718 4 u_riscv_top.core2_irq_lines\[6\]
+port 1571 nsew
+rlabel metal2 s 134274 637432 134274 637432 4 u_riscv_top.core2_irq_lines\[7\]
+port 1572 nsew
+rlabel metal2 s 134642 637517 134642 637517 4 u_riscv_top.core2_irq_lines\[8\]
+port 1573 nsew
+rlabel metal2 s 134366 636208 134366 636208 4 u_riscv_top.core2_irq_lines\[9\]
+port 1574 nsew
+rlabel metal2 s 134734 639064 134734 639064 4 u_riscv_top.core2_soft_irq
+port 1575 nsew
+rlabel metal2 s 134918 612646 134918 612646 4 u_riscv_top.core2_timer_irq
+port 1576 nsew
+rlabel metal2 s 136482 629986 136482 629986 4 u_riscv_top.core2_timer_val\[0\]
+port 1577 nsew
+rlabel metal2 s 135562 627096 135562 627096 4 u_riscv_top.core2_timer_val\[10\]
+port 1578 nsew
+rlabel metal2 s 135654 627096 135654 627096 4 u_riscv_top.core2_timer_val\[11\]
+port 1579 nsew
+rlabel metal2 s 136574 627096 136574 627096 4 u_riscv_top.core2_timer_val\[12\]
+port 1580 nsew
+rlabel metal2 s 134826 626586 134826 626586 4 u_riscv_top.core2_timer_val\[13\]
+port 1581 nsew
+rlabel metal2 s 135102 626586 135102 626586 4 u_riscv_top.core2_timer_val\[14\]
+port 1582 nsew
+rlabel metal3 s 145184 623492 145184 623492 4 u_riscv_top.core2_timer_val\[15\]
+port 1583 nsew
+rlabel metal3 s 145092 623220 145092 623220 4 u_riscv_top.core2_timer_val\[16\]
+port 1584 nsew
+rlabel metal3 s 145046 622948 145046 622948 4 u_riscv_top.core2_timer_val\[17\]
+port 1585 nsew
+rlabel metal2 s 134090 625192 134090 625192 4 u_riscv_top.core2_timer_val\[18\]
+port 1586 nsew
+rlabel metal2 s 134182 625158 134182 625158 4 u_riscv_top.core2_timer_val\[19\]
+port 1587 nsew
+rlabel metal2 s 136390 629850 136390 629850 4 u_riscv_top.core2_timer_val\[1\]
+port 1588 nsew
+rlabel metal2 s 136298 624478 136298 624478 4 u_riscv_top.core2_timer_val\[20\]
+port 1589 nsew
+rlabel metal2 s 136206 624410 136206 624410 4 u_riscv_top.core2_timer_val\[21\]
+port 1590 nsew
+rlabel metal2 s 136114 624342 136114 624342 4 u_riscv_top.core2_timer_val\[22\]
+port 1591 nsew
+rlabel metal2 s 134274 623900 134274 623900 4 u_riscv_top.core2_timer_val\[23\]
+port 1592 nsew
+rlabel metal2 s 134366 623832 134366 623832 4 u_riscv_top.core2_timer_val\[24\]
+port 1593 nsew
+rlabel metal2 s 136482 622982 136482 622982 4 u_riscv_top.core2_timer_val\[25\]
+port 1594 nsew
+rlabel metal2 s 136390 622982 136390 622982 4 u_riscv_top.core2_timer_val\[26\]
+port 1595 nsew
+rlabel metal2 s 135838 622982 135838 622982 4 u_riscv_top.core2_timer_val\[27\]
+port 1596 nsew
+rlabel metal2 s 135194 622438 135194 622438 4 u_riscv_top.core2_timer_val\[28\]
+port 1597 nsew
+rlabel metal2 s 134642 622506 134642 622506 4 u_riscv_top.core2_timer_val\[29\]
+port 1598 nsew
+rlabel metal2 s 136298 629816 136298 629816 4 u_riscv_top.core2_timer_val\[2\]
+port 1599 nsew
+rlabel metal2 s 135746 621656 135746 621656 4 u_riscv_top.core2_timer_val\[30\]
+port 1600 nsew
+rlabel metal2 s 135654 621588 135654 621588 4 u_riscv_top.core2_timer_val\[31\]
+port 1601 nsew
+rlabel metal2 s 135562 621622 135562 621622 4 u_riscv_top.core2_timer_val\[32\]
+port 1602 nsew
+rlabel metal2 s 134918 621146 134918 621146 4 u_riscv_top.core2_timer_val\[33\]
+port 1603 nsew
+rlabel metal2 s 134734 621078 134734 621078 4 u_riscv_top.core2_timer_val\[34\]
+port 1604 nsew
+rlabel metal3 s 124100 623084 124100 623084 4 u_riscv_top.core2_timer_val\[35\]
+port 1605 nsew
+rlabel metal3 s 124146 622812 124146 622812 4 u_riscv_top.core2_timer_val\[36\]
+port 1606 nsew
+rlabel metal3 s 124192 622540 124192 622540 4 u_riscv_top.core2_timer_val\[37\]
+port 1607 nsew
+rlabel metal2 s 135010 619752 135010 619752 4 u_riscv_top.core2_timer_val\[38\]
+port 1608 nsew
+rlabel metal2 s 134826 619684 134826 619684 4 u_riscv_top.core2_timer_val\[39\]
+port 1609 nsew
+rlabel metal2 s 135194 629238 135194 629238 4 u_riscv_top.core2_timer_val\[3\]
+port 1610 nsew
+rlabel metal3 s 124146 621724 124146 621724 4 u_riscv_top.core2_timer_val\[40\]
+port 1611 nsew
+rlabel metal3 s 123732 621452 123732 621452 4 u_riscv_top.core2_timer_val\[41\]
+port 1612 nsew
+rlabel metal3 s 124192 621180 124192 621180 4 u_riscv_top.core2_timer_val\[42\]
+port 1613 nsew
+rlabel metal2 s 135102 618324 135102 618324 4 u_riscv_top.core2_timer_val\[43\]
+port 1614 nsew
+rlabel metal2 s 135194 618324 135194 618324 4 u_riscv_top.core2_timer_val\[44\]
+port 1615 nsew
+rlabel metal2 s 136206 617508 136206 617508 4 u_riscv_top.core2_timer_val\[45\]
+port 1616 nsew
+rlabel metal2 s 136114 617440 136114 617440 4 u_riscv_top.core2_timer_val\[46\]
+port 1617 nsew
+rlabel metal2 s 136574 617474 136574 617474 4 u_riscv_top.core2_timer_val\[47\]
+port 1618 nsew
+rlabel metal2 s 134918 616930 134918 616930 4 u_riscv_top.core2_timer_val\[48\]
+port 1619 nsew
+rlabel metal2 s 134734 616998 134734 616998 4 u_riscv_top.core2_timer_val\[49\]
+port 1620 nsew
+rlabel metal2 s 135378 628524 135378 628524 4 u_riscv_top.core2_timer_val\[4\]
+port 1621 nsew
+rlabel metal2 s 135930 616114 135930 616114 4 u_riscv_top.core2_timer_val\[50\]
+port 1622 nsew
+rlabel metal2 s 136298 616148 136298 616148 4 u_riscv_top.core2_timer_val\[51\]
+port 1623 nsew
+rlabel metal2 s 136482 616080 136482 616080 4 u_riscv_top.core2_timer_val\[52\]
+port 1624 nsew
+rlabel metal2 s 134274 615570 134274 615570 4 u_riscv_top.core2_timer_val\[53\]
+port 1625 nsew
+rlabel metal2 s 134366 615570 134366 615570 4 u_riscv_top.core2_timer_val\[54\]
+port 1626 nsew
+rlabel metal2 s 136390 614720 136390 614720 4 u_riscv_top.core2_timer_val\[55\]
+port 1627 nsew
+rlabel metal2 s 135838 614754 135838 614754 4 u_riscv_top.core2_timer_val\[56\]
+port 1628 nsew
+rlabel metal2 s 135746 614686 135746 614686 4 u_riscv_top.core2_timer_val\[57\]
+port 1629 nsew
+rlabel metal2 s 134090 614244 134090 614244 4 u_riscv_top.core2_timer_val\[58\]
+port 1630 nsew
+rlabel metal2 s 134182 614176 134182 614176 4 u_riscv_top.core2_timer_val\[59\]
+port 1631 nsew
+rlabel metal2 s 135470 628524 135470 628524 4 u_riscv_top.core2_timer_val\[5\]
+port 1632 nsew
+rlabel metal3 s 123916 616284 123916 616284 4 u_riscv_top.core2_timer_val\[60\]
+port 1633 nsew
+rlabel metal2 s 136022 613462 136022 613462 4 u_riscv_top.core2_timer_val\[61\]
+port 1634 nsew
+rlabel metal3 s 124192 615740 124192 615740 4 u_riscv_top.core2_timer_val\[62\]
+port 1635 nsew
+rlabel metal2 s 135194 612680 135194 612680 4 u_riscv_top.core2_timer_val\[63\]
+port 1636 nsew
+rlabel metal2 s 135838 628524 135838 628524 4 u_riscv_top.core2_timer_val\[6\]
+port 1637 nsew
+rlabel metal3 s 124054 630700 124054 630700 4 u_riscv_top.core2_timer_val\[7\]
+port 1638 nsew
+rlabel metal2 s 135010 627980 135010 627980 4 u_riscv_top.core2_timer_val\[8\]
+port 1639 nsew
+rlabel metal3 s 144578 625107 144578 625107 4 u_riscv_top.core2_timer_val\[9\]
+port 1640 nsew
+rlabel metal3 s 124192 535772 124192 535772 4 u_riscv_top.core2_uid\[0\]
+port 1641 nsew
+rlabel metal3 s 124146 535500 124146 535500 4 u_riscv_top.core2_uid\[1\]
+port 1642 nsew
+rlabel metal2 s 229862 530451 229862 530451 4 u_riscv_top.core3_clk
+port 1643 nsew
+rlabel metal3 s 229862 603245 229862 603245 4 u_riscv_top.core3_debug\[0\]
+port 1644 nsew
+rlabel metal2 s 229862 600593 229862 600593 4 u_riscv_top.core3_debug\[10\]
+port 1645 nsew
+rlabel metal3 s 230414 600253 230414 600253 4 u_riscv_top.core3_debug\[11\]
+port 1646 nsew
+rlabel metal3 s 230414 599981 230414 599981 4 u_riscv_top.core3_debug\[12\]
+port 1647 nsew
+rlabel metal2 s 229494 599777 229494 599777 4 u_riscv_top.core3_debug\[13\]
+port 1648 nsew
+rlabel metal2 s 230230 599777 230230 599777 4 u_riscv_top.core3_debug\[14\]
+port 1649 nsew
+rlabel metal2 s 229678 599675 229678 599675 4 u_riscv_top.core3_debug\[15\]
+port 1650 nsew
+rlabel metal3 s 230414 598893 230414 598893 4 u_riscv_top.core3_debug\[16\]
+port 1651 nsew
+rlabel metal3 s 230414 598621 230414 598621 4 u_riscv_top.core3_debug\[17\]
+port 1652 nsew
+rlabel metal2 s 230046 598417 230046 598417 4 u_riscv_top.core3_debug\[18\]
+port 1653 nsew
+rlabel metal2 s 229494 598451 229494 598451 4 u_riscv_top.core3_debug\[19\]
+port 1654 nsew
+rlabel metal3 s 230414 602973 230414 602973 4 u_riscv_top.core3_debug\[1\]
+port 1655 nsew
+rlabel metal2 s 229678 598281 229678 598281 4 u_riscv_top.core3_debug\[20\]
+port 1656 nsew
+rlabel metal3 s 230414 597499 230414 597499 4 u_riscv_top.core3_debug\[21\]
+port 1657 nsew
+rlabel metal2 s 230414 597295 230414 597295 4 u_riscv_top.core3_debug\[22\]
+port 1658 nsew
+rlabel metal2 s 230414 597057 230414 597057 4 u_riscv_top.core3_debug\[23\]
+port 1659 nsew
+rlabel metal2 s 229862 597057 229862 597057 4 u_riscv_top.core3_debug\[24\]
+port 1660 nsew
+rlabel metal2 s 229862 596513 229862 596513 4 u_riscv_top.core3_debug\[25\]
+port 1661 nsew
+rlabel metal1 s 236026 600406 236026 600406 4 u_riscv_top.core3_debug\[26\]
+port 1662 nsew
+rlabel metal2 s 229494 595935 229494 595935 4 u_riscv_top.core3_debug\[27\]
+port 1663 nsew
+rlabel metal2 s 229862 595697 229862 595697 4 u_riscv_top.core3_debug\[28\]
+port 1664 nsew
+rlabel metal2 s 229494 595459 229494 595459 4 u_riscv_top.core3_debug\[29\]
+port 1665 nsew
+rlabel metal2 s 229586 602871 229586 602871 4 u_riscv_top.core3_debug\[2\]
+port 1666 nsew
+rlabel metal1 s 235612 599114 235612 599114 4 u_riscv_top.core3_debug\[30\]
+port 1667 nsew
+rlabel metal1 s 235612 599046 235612 599046 4 u_riscv_top.core3_debug\[31\]
+port 1668 nsew
+rlabel metal1 s 235934 598978 235934 598978 4 u_riscv_top.core3_debug\[32\]
+port 1669 nsew
+rlabel metal1 s 233956 599250 233956 599250 4 u_riscv_top.core3_debug\[33\]
+port 1670 nsew
+rlabel metal1 s 233956 599182 233956 599182 4 u_riscv_top.core3_debug\[34\]
+port 1671 nsew
+rlabel metal1 s 235658 597618 235658 597618 4 u_riscv_top.core3_debug\[35\]
+port 1672 nsew
+rlabel metal1 s 235888 597550 235888 597550 4 u_riscv_top.core3_debug\[36\]
+port 1673 nsew
+rlabel metal3 s 230414 593181 230414 593181 4 u_riscv_top.core3_debug\[37\]
+port 1674 nsew
+rlabel metal2 s 230046 593113 230046 593113 4 u_riscv_top.core3_debug\[38\]
+port 1675 nsew
+rlabel metal2 s 229678 592943 229678 592943 4 u_riscv_top.core3_debug\[39\]
+port 1676 nsew
+rlabel metal2 s 229678 602531 229678 602531 4 u_riscv_top.core3_debug\[3\]
+port 1677 nsew
+rlabel metal2 s 237774 596770 237774 596770 4 u_riscv_top.core3_debug\[40\]
+port 1678 nsew
+rlabel metal2 s 237498 596634 237498 596634 4 u_riscv_top.core3_debug\[41\]
+port 1679 nsew
+rlabel metal1 s 235796 596394 235796 596394 4 u_riscv_top.core3_debug\[42\]
+port 1680 nsew
+rlabel metal1 s 235704 596326 235704 596326 4 u_riscv_top.core3_debug\[43\]
+port 1681 nsew
+rlabel metal1 s 233496 596258 233496 596258 4 u_riscv_top.core3_debug\[44\]
+port 1682 nsew
+rlabel metal2 s 229862 591073 229862 591073 4 u_riscv_top.core3_debug\[45\]
+port 1683 nsew
+rlabel metal2 s 229402 591311 229402 591311 4 u_riscv_top.core3_debug\[46\]
+port 1684 nsew
+rlabel metal3 s 230414 590461 230414 590461 4 u_riscv_top.core3_debug\[47\]
+port 1685 nsew
+rlabel metal2 s 229862 590257 229862 590257 4 u_riscv_top.core3_debug\[48\]
+port 1686 nsew
+rlabel metal2 s 229678 602225 229678 602225 4 u_riscv_top.core3_debug\[4\]
+port 1687 nsew
+rlabel metal2 s 229678 601919 229678 601919 4 u_riscv_top.core3_debug\[5\]
+port 1688 nsew
+rlabel metal3 s 230414 601579 230414 601579 4 u_riscv_top.core3_debug\[6\]
+port 1689 nsew
+rlabel metal3 s 230414 601341 230414 601341 4 u_riscv_top.core3_debug\[7\]
+port 1690 nsew
+rlabel metal2 s 230414 601137 230414 601137 4 u_riscv_top.core3_debug\[8\]
+port 1691 nsew
+rlabel metal2 s 229862 601205 229862 601205 4 u_riscv_top.core3_debug\[9\]
+port 1692 nsew
+rlabel metal3 s 230414 569891 230414 569891 4 u_riscv_top.core3_dmem_addr\[0\]
+port 1693 nsew
+rlabel metal2 s 230138 567579 230138 567579 4 u_riscv_top.core3_dmem_addr\[10\]
+port 1694 nsew
+rlabel metal3 s 229494 566933 229494 566933 4 u_riscv_top.core3_dmem_addr\[11\]
+port 1695 nsew
+rlabel metal3 s 230414 566661 230414 566661 4 u_riscv_top.core3_dmem_addr\[12\]
+port 1696 nsew
+rlabel metal2 s 229678 566593 229678 566593 4 u_riscv_top.core3_dmem_addr\[13\]
+port 1697 nsew
+rlabel metal2 s 229586 566321 229586 566321 4 u_riscv_top.core3_dmem_addr\[14\]
+port 1698 nsew
+rlabel metal2 s 230414 566083 230414 566083 4 u_riscv_top.core3_dmem_addr\[15\]
+port 1699 nsew
+rlabel metal3 s 230414 565573 230414 565573 4 u_riscv_top.core3_dmem_addr\[16\]
+port 1700 nsew
+rlabel metal2 s 229494 565471 229494 565471 4 u_riscv_top.core3_dmem_addr\[17\]
+port 1701 nsew
+rlabel metal3 s 230414 565029 230414 565029 4 u_riscv_top.core3_dmem_addr\[18\]
+port 1702 nsew
+rlabel metal2 s 229494 564961 229494 564961 4 u_riscv_top.core3_dmem_addr\[19\]
+port 1703 nsew
+rlabel metal3 s 230414 569653 230414 569653 4 u_riscv_top.core3_dmem_addr\[1\]
+port 1704 nsew
+rlabel metal2 s 230046 564723 230046 564723 4 u_riscv_top.core3_dmem_addr\[20\]
+port 1705 nsew
+rlabel metal3 s 230414 564213 230414 564213 4 u_riscv_top.core3_dmem_addr\[21\]
+port 1706 nsew
+rlabel metal3 s 230414 563941 230414 563941 4 u_riscv_top.core3_dmem_addr\[22\]
+port 1707 nsew
+rlabel metal2 s 230230 563975 230230 563975 4 u_riscv_top.core3_dmem_addr\[23\]
+port 1708 nsew
+rlabel metal2 s 229494 563873 229494 563873 4 u_riscv_top.core3_dmem_addr\[24\]
+port 1709 nsew
+rlabel metal2 s 229586 563431 229586 563431 4 u_riscv_top.core3_dmem_addr\[25\]
+port 1710 nsew
+rlabel metal1 s 233680 567562 233680 567562 4 u_riscv_top.core3_dmem_addr\[26\]
+port 1711 nsew
+rlabel metal1 s 233680 567358 233680 567358 4 u_riscv_top.core3_dmem_addr\[27\]
+port 1712 nsew
+rlabel metal1 s 233680 567222 233680 567222 4 u_riscv_top.core3_dmem_addr\[28\]
+port 1713 nsew
+rlabel metal2 s 229954 562105 229954 562105 4 u_riscv_top.core3_dmem_addr\[29\]
+port 1714 nsew
+rlabel metal2 s 230414 569449 230414 569449 4 u_riscv_top.core3_dmem_addr\[2\]
+port 1715 nsew
+rlabel metal2 s 229862 562105 229862 562105 4 u_riscv_top.core3_dmem_addr\[30\]
+port 1716 nsew
+rlabel metal3 s 230414 561493 230414 561493 4 u_riscv_top.core3_dmem_addr\[31\]
+port 1717 nsew
+rlabel metal2 s 229494 569449 229494 569449 4 u_riscv_top.core3_dmem_addr\[3\]
+port 1718 nsew
+rlabel metal2 s 229862 569279 229862 569279 4 u_riscv_top.core3_dmem_addr\[4\]
+port 1719 nsew
+rlabel metal3 s 230414 568531 230414 568531 4 u_riscv_top.core3_dmem_addr\[5\]
+port 1720 nsew
+rlabel metal3 s 230414 568293 230414 568293 4 u_riscv_top.core3_dmem_addr\[6\]
+port 1721 nsew
+rlabel metal3 s 230230 568021 230230 568021 4 u_riscv_top.core3_dmem_addr\[7\]
+port 1722 nsew
+rlabel metal2 s 229862 567953 229862 567953 4 u_riscv_top.core3_dmem_addr\[8\]
+port 1723 nsew
+rlabel metal2 s 229494 567545 229494 567545 4 u_riscv_top.core3_dmem_addr\[9\]
+port 1724 nsew
+rlabel metal2 s 230046 561153 230046 561153 4 u_riscv_top.core3_dmem_cmd
+port 1725 nsew
+rlabel metal3 s 229678 587333 229678 587333 4 u_riscv_top.core3_dmem_rdata\[0\]
+port 1726 nsew
+rlabel metal2 s 229862 584817 229862 584817 4 u_riscv_top.core3_dmem_rdata\[10\]
+port 1727 nsew
+rlabel metal2 s 229678 584545 229678 584545 4 u_riscv_top.core3_dmem_rdata\[11\]
+port 1728 nsew
+rlabel metal2 s 230414 584511 230414 584511 4 u_riscv_top.core3_dmem_rdata\[12\]
+port 1729 nsew
+rlabel metal2 s 230046 584341 230046 584341 4 u_riscv_top.core3_dmem_rdata\[13\]
+port 1730 nsew
+rlabel metal3 s 230414 583525 230414 583525 4 u_riscv_top.core3_dmem_rdata\[14\]
+port 1731 nsew
+rlabel metal2 s 230138 583423 230138 583423 4 u_riscv_top.core3_dmem_rdata\[15\]
+port 1732 nsew
+rlabel metal2 s 230046 583117 230046 583117 4 u_riscv_top.core3_dmem_rdata\[16\]
+port 1733 nsew
+rlabel metal2 s 229678 583185 229678 583185 4 u_riscv_top.core3_dmem_rdata\[17\]
+port 1734 nsew
+rlabel metal2 s 229494 582675 229494 582675 4 u_riscv_top.core3_dmem_rdata\[18\]
+port 1735 nsew
+rlabel metal3 s 230414 582165 230414 582165 4 u_riscv_top.core3_dmem_rdata\[19\]
+port 1736 nsew
+rlabel metal2 s 230414 587129 230414 587129 4 u_riscv_top.core3_dmem_rdata\[1\]
+port 1737 nsew
+rlabel metal3 s 230414 581893 230414 581893 4 u_riscv_top.core3_dmem_rdata\[20\]
+port 1738 nsew
+rlabel metal3 s 230414 581621 230414 581621 4 u_riscv_top.core3_dmem_rdata\[21\]
+port 1739 nsew
+rlabel metal2 s 229770 581825 229770 581825 4 u_riscv_top.core3_dmem_rdata\[22\]
+port 1740 nsew
+rlabel metal2 s 229862 581655 229862 581655 4 u_riscv_top.core3_dmem_rdata\[23\]
+port 1741 nsew
+rlabel metal3 s 230414 580805 230414 580805 4 u_riscv_top.core3_dmem_rdata\[24\]
+port 1742 nsew
+rlabel metal2 s 230414 580601 230414 580601 4 u_riscv_top.core3_dmem_rdata\[25\]
+port 1743 nsew
+rlabel metal2 s 230046 580601 230046 580601 4 u_riscv_top.core3_dmem_rdata\[26\]
+port 1744 nsew
+rlabel metal2 s 230046 580057 230046 580057 4 u_riscv_top.core3_dmem_rdata\[27\]
+port 1745 nsew
+rlabel metal2 s 230046 579785 230046 579785 4 u_riscv_top.core3_dmem_rdata\[28\]
+port 1746 nsew
+rlabel metal3 s 230414 579445 230414 579445 4 u_riscv_top.core3_dmem_rdata\[29\]
+port 1747 nsew
+rlabel metal2 s 229862 587027 229862 587027 4 u_riscv_top.core3_dmem_rdata\[2\]
+port 1748 nsew
+rlabel metal2 s 230414 579241 230414 579241 4 u_riscv_top.core3_dmem_rdata\[30\]
+port 1749 nsew
+rlabel metal2 s 230046 579241 230046 579241 4 u_riscv_top.core3_dmem_rdata\[31\]
+port 1750 nsew
+rlabel metal3 s 229126 586517 229126 586517 4 u_riscv_top.core3_dmem_rdata\[3\]
+port 1751 nsew
+rlabel metal2 s 230414 586313 230414 586313 4 u_riscv_top.core3_dmem_rdata\[4\]
+port 1752 nsew
+rlabel metal2 s 230414 586041 230414 586041 4 u_riscv_top.core3_dmem_rdata\[5\]
+port 1753 nsew
+rlabel metal2 s 229862 585837 229862 585837 4 u_riscv_top.core3_dmem_rdata\[6\]
+port 1754 nsew
+rlabel metal2 s 229494 585565 229494 585565 4 u_riscv_top.core3_dmem_rdata\[7\]
+port 1755 nsew
+rlabel metal3 s 229862 585157 229862 585157 4 u_riscv_top.core3_dmem_rdata\[8\]
+port 1756 nsew
+rlabel metal2 s 229678 584987 229678 584987 4 u_riscv_top.core3_dmem_rdata\[9\]
+port 1757 nsew
+rlabel metal2 s 229494 560473 229494 560473 4 u_riscv_top.core3_dmem_req
+port 1758 nsew
+rlabel metal3 s 230414 560133 230414 560133 4 u_riscv_top.core3_dmem_req_ack
+port 1759 nsew
+rlabel metal3 s 230414 587843 230414 587843 4 u_riscv_top.core3_dmem_resp\[0\]
+port 1760 nsew
+rlabel metal3 s 230414 587605 230414 587605 4 u_riscv_top.core3_dmem_resp\[1\]
+port 1761 nsew
+rlabel metal2 s 229862 579071 229862 579071 4 u_riscv_top.core3_dmem_wdata\[0\]
+port 1762 nsew
+rlabel metal1 s 235934 579870 235934 579870 4 u_riscv_top.core3_dmem_wdata\[10\]
+port 1763 nsew
+rlabel metal1 s 235980 579802 235980 579802 4 u_riscv_top.core3_dmem_wdata\[11\]
+port 1764 nsew
+rlabel metal1 s 235980 579734 235980 579734 4 u_riscv_top.core3_dmem_wdata\[12\]
+port 1765 nsew
+rlabel metal1 s 235842 579666 235842 579666 4 u_riscv_top.core3_dmem_wdata\[13\]
+port 1766 nsew
+rlabel metal2 s 229494 575059 229494 575059 4 u_riscv_top.core3_dmem_wdata\[14\]
+port 1767 nsew
+rlabel metal2 s 230414 574617 230414 574617 4 u_riscv_top.core3_dmem_wdata\[15\]
+port 1768 nsew
+rlabel metal2 s 237682 578066 237682 578066 4 u_riscv_top.core3_dmem_wdata\[16\]
+port 1769 nsew
+rlabel metal3 s 230414 574005 230414 574005 4 u_riscv_top.core3_dmem_wdata\[17\]
+port 1770 nsew
+rlabel metal3 s 229678 573733 229678 573733 4 u_riscv_top.core3_dmem_wdata\[18\]
+port 1771 nsew
+rlabel metal2 s 229494 573631 229494 573631 4 u_riscv_top.core3_dmem_wdata\[19\]
+port 1772 nsew
+rlabel metal2 s 229862 578425 229862 578425 4 u_riscv_top.core3_dmem_wdata\[1\]
+port 1773 nsew
+rlabel metal1 s 235980 577082 235980 577082 4 u_riscv_top.core3_dmem_wdata\[20\]
+port 1774 nsew
+rlabel metal1 s 235796 577218 235796 577218 4 u_riscv_top.core3_dmem_wdata\[21\]
+port 1775 nsew
+rlabel metal1 s 233680 577286 233680 577286 4 u_riscv_top.core3_dmem_wdata\[22\]
+port 1776 nsew
+rlabel metal1 s 229678 576946 229678 576946 4 u_riscv_top.core3_dmem_wdata\[23\]
+port 1777 nsew
+rlabel metal1 s 233680 576946 233680 576946 4 u_riscv_top.core3_dmem_wdata\[24\]
+port 1778 nsew
+rlabel metal1 s 233588 576878 233588 576878 4 u_riscv_top.core3_dmem_wdata\[25\]
+port 1779 nsew
+rlabel metal2 s 229862 572101 229862 572101 4 u_riscv_top.core3_dmem_wdata\[26\]
+port 1780 nsew
+rlabel metal3 s 230414 571285 230414 571285 4 u_riscv_top.core3_dmem_wdata\[27\]
+port 1781 nsew
+rlabel metal2 s 230414 571081 230414 571081 4 u_riscv_top.core3_dmem_wdata\[28\]
+port 1782 nsew
+rlabel metal2 s 230414 570809 230414 570809 4 u_riscv_top.core3_dmem_wdata\[29\]
+port 1783 nsew
+rlabel metal2 s 230046 578119 230046 578119 4 u_riscv_top.core3_dmem_wdata\[2\]
+port 1784 nsew
+rlabel metal2 s 230046 570571 230046 570571 4 u_riscv_top.core3_dmem_wdata\[30\]
+port 1785 nsew
+rlabel metal2 s 229862 570707 229862 570707 4 u_riscv_top.core3_dmem_wdata\[31\]
+port 1786 nsew
+rlabel metal2 s 230322 580159 230322 580159 4 u_riscv_top.core3_dmem_wdata\[3\]
+port 1787 nsew
+rlabel metal2 s 230230 580057 230230 580057 4 u_riscv_top.core3_dmem_wdata\[4\]
+port 1788 nsew
+rlabel metal2 s 229678 577677 229678 577677 4 u_riscv_top.core3_dmem_wdata\[5\]
+port 1789 nsew
+rlabel metal2 s 229678 577065 229678 577065 4 u_riscv_top.core3_dmem_wdata\[6\]
+port 1790 nsew
+rlabel metal3 s 230414 576725 230414 576725 4 u_riscv_top.core3_dmem_wdata\[7\]
+port 1791 nsew
+rlabel metal3 s 230414 576453 230414 576453 4 u_riscv_top.core3_dmem_wdata\[8\]
+port 1792 nsew
+rlabel metal1 s 234048 581162 234048 581162 4 u_riscv_top.core3_dmem_wdata\[9\]
+port 1793 nsew
+rlabel metal2 s 229678 563567 229678 563567 4 u_riscv_top.core3_dmem_width\[0\]
+port 1794 nsew
+rlabel metal2 s 230322 563397 230322 563397 4 u_riscv_top.core3_dmem_width\[1\]
+port 1795 nsew
+rlabel metal3 s 229310 540277 229310 540277 4 u_riscv_top.core3_imem_addr\[0\]
+port 1796 nsew
+rlabel metal1 s 234094 540362 234094 540362 4 u_riscv_top.core3_imem_addr\[10\]
+port 1797 nsew
+rlabel metal2 s 230414 537659 230414 537659 4 u_riscv_top.core3_imem_addr\[11\]
+port 1798 nsew
+rlabel metal2 s 230414 537081 230414 537081 4 u_riscv_top.core3_imem_addr\[12\]
+port 1799 nsew
+rlabel metal1 s 235842 541042 235842 541042 4 u_riscv_top.core3_imem_addr\[13\]
+port 1800 nsew
+rlabel metal1 s 235566 541110 235566 541110 4 u_riscv_top.core3_imem_addr\[14\]
+port 1801 nsew
+rlabel metal2 s 234140 539716 234140 539716 4 u_riscv_top.core3_imem_addr\[15\]
+port 1802 nsew
+rlabel metal1 s 235888 539614 235888 539614 4 u_riscv_top.core3_imem_addr\[16\]
+port 1803 nsew
+rlabel metal2 s 230046 535721 230046 535721 4 u_riscv_top.core3_imem_addr\[17\]
+port 1804 nsew
+rlabel metal1 s 235474 539682 235474 539682 4 u_riscv_top.core3_imem_addr\[18\]
+port 1805 nsew
+rlabel metal2 s 229678 535177 229678 535177 4 u_riscv_top.core3_imem_addr\[19\]
+port 1806 nsew
+rlabel metal2 s 229862 540447 229862 540447 4 u_riscv_top.core3_imem_addr\[1\]
+port 1807 nsew
+rlabel metal2 s 229678 534905 229678 534905 4 u_riscv_top.core3_imem_addr\[20\]
+port 1808 nsew
+rlabel metal3 s 229678 534565 229678 534565 4 u_riscv_top.core3_imem_addr\[21\]
+port 1809 nsew
+rlabel metal2 s 229494 534803 229494 534803 4 u_riscv_top.core3_imem_addr\[22\]
+port 1810 nsew
+rlabel metal1 s 235934 538458 235934 538458 4 u_riscv_top.core3_imem_addr\[23\]
+port 1811 nsew
+rlabel metal1 s 235842 538526 235842 538526 4 u_riscv_top.core3_imem_addr\[24\]
+port 1812 nsew
+rlabel metal1 s 233864 538322 233864 538322 4 u_riscv_top.core3_imem_addr\[25\]
+port 1813 nsew
+rlabel metal1 s 233680 538254 233680 538254 4 u_riscv_top.core3_imem_addr\[26\]
+port 1814 nsew
+rlabel metal2 s 230046 533205 230046 533205 4 u_riscv_top.core3_imem_addr\[27\]
+port 1815 nsew
+rlabel metal2 s 229770 534837 229770 534837 4 u_riscv_top.core3_imem_addr\[28\]
+port 1816 nsew
+rlabel metal2 s 229862 534667 229862 534667 4 u_riscv_top.core3_imem_addr\[29\]
+port 1817 nsew
+rlabel metal2 s 230046 540277 230046 540277 4 u_riscv_top.core3_imem_addr\[2\]
+port 1818 nsew
+rlabel metal2 s 230322 534463 230322 534463 4 u_riscv_top.core3_imem_addr\[30\]
+port 1819 nsew
+rlabel metal2 s 230230 534361 230230 534361 4 u_riscv_top.core3_imem_addr\[31\]
+port 1820 nsew
+rlabel metal3 s 230414 539461 230414 539461 4 u_riscv_top.core3_imem_addr\[3\]
+port 1821 nsew
+rlabel metal3 s 229678 539189 229678 539189 4 u_riscv_top.core3_imem_addr\[4\]
+port 1822 nsew
+rlabel metal3 s 230414 538917 230414 538917 4 u_riscv_top.core3_imem_addr\[5\]
+port 1823 nsew
+rlabel metal2 s 229402 539087 229402 539087 4 u_riscv_top.core3_imem_addr\[6\]
+port 1824 nsew
+rlabel metal2 s 230046 538883 230046 538883 4 u_riscv_top.core3_imem_addr\[7\]
+port 1825 nsew
+rlabel metal1 s 235244 542674 235244 542674 4 u_riscv_top.core3_imem_addr\[8\]
+port 1826 nsew
+rlabel metal1 s 235244 542606 235244 542606 4 u_riscv_top.core3_imem_addr\[9\]
+port 1827 nsew
+rlabel metal2 s 230046 541535 230046 541535 4 u_riscv_top.core3_imem_bl\[0\]
+port 1828 nsew
+rlabel metal3 s 230414 540787 230414 540787 4 u_riscv_top.core3_imem_bl\[1\]
+port 1829 nsew
+rlabel metal3 s 230414 540549 230414 540549 4 u_riscv_top.core3_imem_bl\[2\]
+port 1830 nsew
+rlabel metal3 s 229310 531573 229310 531573 4 u_riscv_top.core3_imem_cmd
+port 1831 nsew
+rlabel metal2 s 229770 550171 229770 550171 4 u_riscv_top.core3_imem_rdata\[0\]
+port 1832 nsew
+rlabel metal2 s 229310 547281 229310 547281 4 u_riscv_top.core3_imem_rdata\[10\]
+port 1833 nsew
+rlabel metal2 s 230046 547009 230046 547009 4 u_riscv_top.core3_imem_rdata\[11\]
+port 1834 nsew
+rlabel metal2 s 229954 546635 229954 546635 4 u_riscv_top.core3_imem_rdata\[12\]
+port 1835 nsew
+rlabel metal3 s 230414 546261 230414 546261 4 u_riscv_top.core3_imem_rdata\[13\]
+port 1836 nsew
+rlabel metal3 s 230414 545989 230414 545989 4 u_riscv_top.core3_imem_rdata\[14\]
+port 1837 nsew
+rlabel metal2 s 230414 545785 230414 545785 4 u_riscv_top.core3_imem_rdata\[15\]
+port 1838 nsew
+rlabel metal2 s 230322 545887 230322 545887 4 u_riscv_top.core3_imem_rdata\[16\]
+port 1839 nsew
+rlabel metal2 s 230230 545649 230230 545649 4 u_riscv_top.core3_imem_rdata\[17\]
+port 1840 nsew
+rlabel metal3 s 230414 544901 230414 544901 4 u_riscv_top.core3_imem_rdata\[18\]
+port 1841 nsew
+rlabel metal2 s 229402 544833 229402 544833 4 u_riscv_top.core3_imem_rdata\[19\]
+port 1842 nsew
+rlabel metal2 s 229678 550001 229678 550001 4 u_riscv_top.core3_imem_rdata\[1\]
+port 1843 nsew
+rlabel metal2 s 230414 544425 230414 544425 4 u_riscv_top.core3_imem_rdata\[20\]
+port 1844 nsew
+rlabel metal2 s 229862 544391 229862 544391 4 u_riscv_top.core3_imem_rdata\[21\]
+port 1845 nsew
+rlabel metal2 s 229862 543881 229862 543881 4 u_riscv_top.core3_imem_rdata\[22\]
+port 1846 nsew
+rlabel metal1 s 233542 548182 233542 548182 4 u_riscv_top.core3_imem_rdata\[23\]
+port 1847 nsew
+rlabel metal1 s 233542 548046 233542 548046 4 u_riscv_top.core3_imem_rdata\[24\]
+port 1848 nsew
+rlabel metal1 s 233542 547910 233542 547910 4 u_riscv_top.core3_imem_rdata\[25\]
+port 1849 nsew
+rlabel metal2 s 229494 542793 229494 542793 4 u_riscv_top.core3_imem_rdata\[26\]
+port 1850 nsew
+rlabel metal2 s 230046 543065 230046 543065 4 u_riscv_top.core3_imem_rdata\[27\]
+port 1851 nsew
+rlabel metal2 s 230414 542215 230414 542215 4 u_riscv_top.core3_imem_rdata\[28\]
+port 1852 nsew
+rlabel metal2 s 230414 541977 230414 541977 4 u_riscv_top.core3_imem_rdata\[29\]
+port 1853 nsew
+rlabel metal3 s 230414 549219 230414 549219 4 u_riscv_top.core3_imem_rdata\[2\]
+port 1854 nsew
+rlabel metal2 s 230230 541977 230230 541977 4 u_riscv_top.core3_imem_rdata\[30\]
+port 1855 nsew
+rlabel metal2 s 229862 541773 229862 541773 4 u_riscv_top.core3_imem_rdata\[31\]
+port 1856 nsew
+rlabel metal3 s 230414 548981 230414 548981 4 u_riscv_top.core3_imem_rdata\[3\]
+port 1857 nsew
+rlabel metal2 s 229494 548777 229494 548777 4 u_riscv_top.core3_imem_rdata\[4\]
+port 1858 nsew
+rlabel metal2 s 229862 548471 229862 548471 4 u_riscv_top.core3_imem_rdata\[5\]
+port 1859 nsew
+rlabel metal2 s 229862 548233 229862 548233 4 u_riscv_top.core3_imem_rdata\[6\]
+port 1860 nsew
+rlabel metal2 s 230230 548403 230230 548403 4 u_riscv_top.core3_imem_rdata\[7\]
+port 1861 nsew
+rlabel metal2 s 229862 547732 229862 547732 4 u_riscv_top.core3_imem_rdata\[8\]
+port 1862 nsew
+rlabel metal1 s 234002 552194 234002 552194 4 u_riscv_top.core3_imem_rdata\[9\]
+port 1863 nsew
+rlabel metal3 s 230414 531267 230414 531267 4 u_riscv_top.core3_imem_req
+port 1864 nsew
+rlabel metal3 s 230414 531029 230414 531029 4 u_riscv_top.core3_imem_req_ack
+port 1865 nsew
+rlabel metal3 s 230414 550341 230414 550341 4 u_riscv_top.core3_imem_resp\[0\]
+port 1866 nsew
+rlabel metal2 s 230414 550137 230414 550137 4 u_riscv_top.core3_imem_resp\[1\]
+port 1867 nsew
+rlabel metal2 s 229678 636871 229678 636871 4 u_riscv_top.core3_irq_lines\[0\]
+port 1868 nsew
+rlabel metal1 s 236164 637670 236164 637670 4 u_riscv_top.core3_irq_lines\[10\]
+port 1869 nsew
+rlabel metal1 s 236118 637738 236118 637738 4 u_riscv_top.core3_irq_lines\[11\]
+port 1870 nsew
+rlabel metal1 s 235934 637602 235934 637602 4 u_riscv_top.core3_irq_lines\[12\]
+port 1871 nsew
+rlabel metal3 s 230046 632757 230046 632757 4 u_riscv_top.core3_irq_lines\[13\]
+port 1872 nsew
+rlabel metal1 s 236072 636242 236072 636242 4 u_riscv_top.core3_irq_lines\[14\]
+port 1873 nsew
+rlabel metal1 s 235888 636310 235888 636310 4 u_riscv_top.core3_irq_lines\[15\]
+port 1874 nsew
+rlabel metal3 s 230414 631941 230414 631941 4 u_riscv_top.core3_irq_lines\[16\]
+port 1875 nsew
+rlabel metal1 s 233910 636446 233910 636446 4 u_riscv_top.core3_irq_lines\[17\]
+port 1876 nsew
+rlabel metal1 s 233956 636378 233956 636378 4 u_riscv_top.core3_irq_lines\[18\]
+port 1877 nsew
+rlabel metal2 s 237590 635470 237590 635470 4 u_riscv_top.core3_irq_lines\[19\]
+port 1878 nsew
+rlabel metal2 s 229862 636089 229862 636089 4 u_riscv_top.core3_irq_lines\[1\]
+port 1879 nsew
+rlabel metal2 s 230322 631431 230322 631431 4 u_riscv_top.core3_irq_lines\[20\]
+port 1880 nsew
+rlabel metal3 s 230414 630581 230414 630581 4 u_riscv_top.core3_irq_lines\[21\]
+port 1881 nsew
+rlabel metal3 s 230230 630309 230230 630309 4 u_riscv_top.core3_irq_lines\[22\]
+port 1882 nsew
+rlabel metal3 s 230230 630037 230230 630037 4 u_riscv_top.core3_irq_lines\[23\]
+port 1883 nsew
+rlabel metal2 s 229678 630139 229678 630139 4 u_riscv_top.core3_irq_lines\[24\]
+port 1884 nsew
+rlabel metal2 s 230414 629969 230414 629969 4 u_riscv_top.core3_irq_lines\[25\]
+port 1885 nsew
+rlabel metal3 s 230414 629221 230414 629221 4 u_riscv_top.core3_irq_lines\[26\]
+port 1886 nsew
+rlabel metal3 s 230414 628949 230414 628949 4 u_riscv_top.core3_irq_lines\[27\]
+port 1887 nsew
+rlabel metal2 s 230230 628745 230230 628745 4 u_riscv_top.core3_irq_lines\[28\]
+port 1888 nsew
+rlabel metal2 s 229678 628779 229678 628779 4 u_riscv_top.core3_irq_lines\[29\]
+port 1889 nsew
+rlabel metal3 s 230322 635749 230322 635749 4 u_riscv_top.core3_irq_lines\[2\]
+port 1890 nsew
+rlabel metal2 s 229862 628269 229862 628269 4 u_riscv_top.core3_irq_lines\[30\]
+port 1891 nsew
+rlabel metal3 s 230414 627861 230414 627861 4 u_riscv_top.core3_irq_lines\[31\]
+port 1892 nsew
+rlabel metal2 s 229954 635749 229954 635749 4 u_riscv_top.core3_irq_lines\[3\]
+port 1893 nsew
+rlabel metal2 s 229678 635647 229678 635647 4 u_riscv_top.core3_irq_lines\[4\]
+port 1894 nsew
+rlabel metal2 s 229678 635001 229678 635001 4 u_riscv_top.core3_irq_lines\[5\]
+port 1895 nsew
+rlabel metal3 s 230414 634661 230414 634661 4 u_riscv_top.core3_irq_lines\[6\]
+port 1896 nsew
+rlabel metal3 s 229678 634389 229678 634389 4 u_riscv_top.core3_irq_lines\[7\]
+port 1897 nsew
+rlabel metal2 s 230046 634287 230046 634287 4 u_riscv_top.core3_irq_lines\[8\]
+port 1898 nsew
+rlabel metal1 s 234278 634950 234278 634950 4 u_riscv_top.core3_irq_lines\[9\]
+port 1899 nsew
+rlabel metal2 s 229862 637041 229862 637041 4 u_riscv_top.core3_soft_irq
+port 1900 nsew
+rlabel metal2 s 230046 610623 230046 610623 4 u_riscv_top.core3_timer_irq
+port 1901 nsew
+rlabel metal3 s 230414 627589 230414 627589 4 u_riscv_top.core3_timer_val\[0\]
+port 1902 nsew
+rlabel metal2 s 230230 624937 230230 624937 4 u_riscv_top.core3_timer_val\[10\]
+port 1903 nsew
+rlabel metal2 s 229862 624733 229862 624733 4 u_riscv_top.core3_timer_val\[11\]
+port 1904 nsew
+rlabel metal2 s 230414 624393 230414 624393 4 u_riscv_top.core3_timer_val\[12\]
+port 1905 nsew
+rlabel metal2 s 229586 624325 229586 624325 4 u_riscv_top.core3_timer_val\[13\]
+port 1906 nsew
+rlabel metal3 s 229678 623781 229678 623781 4 u_riscv_top.core3_timer_val\[14\]
+port 1907 nsew
+rlabel metal3 s 230414 623509 230414 623509 4 u_riscv_top.core3_timer_val\[15\]
+port 1908 nsew
+rlabel metal2 s 230230 623305 230230 623305 4 u_riscv_top.core3_timer_val\[16\]
+port 1909 nsew
+rlabel metal3 s 229310 622965 229310 622965 4 u_riscv_top.core3_timer_val\[17\]
+port 1910 nsew
+rlabel metal2 s 229862 622999 229862 622999 4 u_riscv_top.core3_timer_val\[18\]
+port 1911 nsew
+rlabel metal2 s 229954 622999 229954 622999 4 u_riscv_top.core3_timer_val\[19\]
+port 1912 nsew
+rlabel metal3 s 230414 627317 230414 627317 4 u_riscv_top.core3_timer_val\[1\]
+port 1913 nsew
+rlabel metal2 s 230414 622183 230414 622183 4 u_riscv_top.core3_timer_val\[20\]
+port 1914 nsew
+rlabel metal2 s 229862 621945 229862 621945 4 u_riscv_top.core3_timer_val\[21\]
+port 1915 nsew
+rlabel metal3 s 229678 621605 229678 621605 4 u_riscv_top.core3_timer_val\[22\]
+port 1916 nsew
+rlabel metal3 s 229678 621333 229678 621333 4 u_riscv_top.core3_timer_val\[23\]
+port 1917 nsew
+rlabel metal2 s 230230 621095 230230 621095 4 u_riscv_top.core3_timer_val\[24\]
+port 1918 nsew
+rlabel metal3 s 230414 620789 230414 620789 4 u_riscv_top.core3_timer_val\[25\]
+port 1919 nsew
+rlabel metal3 s 230414 620517 230414 620517 4 u_riscv_top.core3_timer_val\[26\]
+port 1920 nsew
+rlabel metal3 s 230414 620245 230414 620245 4 u_riscv_top.core3_timer_val\[27\]
+port 1921 nsew
+rlabel metal2 s 229862 620449 229862 620449 4 u_riscv_top.core3_timer_val\[28\]
+port 1922 nsew
+rlabel metal2 s 229494 619769 229494 619769 4 u_riscv_top.core3_timer_val\[29\]
+port 1923 nsew
+rlabel metal2 s 229862 627419 229862 627419 4 u_riscv_top.core3_timer_val\[2\]
+port 1924 nsew
+rlabel metal3 s 230414 619429 230414 619429 4 u_riscv_top.core3_timer_val\[30\]
+port 1925 nsew
+rlabel metal2 s 230414 619225 230414 619225 4 u_riscv_top.core3_timer_val\[31\]
+port 1926 nsew
+rlabel metal2 s 229678 619225 229678 619225 4 u_riscv_top.core3_timer_val\[32\]
+port 1927 nsew
+rlabel metal2 s 230230 618885 230230 618885 4 u_riscv_top.core3_timer_val\[33\]
+port 1928 nsew
+rlabel metal2 s 229678 618545 229678 618545 4 u_riscv_top.core3_timer_val\[34\]
+port 1929 nsew
+rlabel metal2 s 230322 620313 230322 620313 4 u_riscv_top.core3_timer_val\[35\]
+port 1930 nsew
+rlabel metal2 s 230138 620211 230138 620211 4 u_riscv_top.core3_timer_val\[36\]
+port 1931 nsew
+rlabel metal2 s 230046 620109 230046 620109 4 u_riscv_top.core3_timer_val\[37\]
+port 1932 nsew
+rlabel metal3 s 229310 617253 229310 617253 4 u_riscv_top.core3_timer_val\[38\]
+port 1933 nsew
+rlabel metal2 s 229862 617389 229862 617389 4 u_riscv_top.core3_timer_val\[39\]
+port 1934 nsew
+rlabel metal2 s 230046 627249 230046 627249 4 u_riscv_top.core3_timer_val\[3\]
+port 1935 nsew
+rlabel metal2 s 229954 618953 229954 618953 4 u_riscv_top.core3_timer_val\[40\]
+port 1936 nsew
+rlabel metal2 s 229586 618851 229586 618851 4 u_riscv_top.core3_timer_val\[41\]
+port 1937 nsew
+rlabel metal2 s 229862 616233 229862 616233 4 u_riscv_top.core3_timer_val\[42\]
+port 1938 nsew
+rlabel metal2 s 229862 615961 229862 615961 4 u_riscv_top.core3_timer_val\[43\]
+port 1939 nsew
+rlabel metal2 s 230230 616029 230230 616029 4 u_riscv_top.core3_timer_val\[44\]
+port 1940 nsew
+rlabel metal3 s 230414 615349 230414 615349 4 u_riscv_top.core3_timer_val\[45\]
+port 1941 nsew
+rlabel metal3 s 230414 615077 230414 615077 4 u_riscv_top.core3_timer_val\[46\]
+port 1942 nsew
+rlabel metal2 s 230414 614873 230414 614873 4 u_riscv_top.core3_timer_val\[47\]
+port 1943 nsew
+rlabel metal3 s 230414 614533 230414 614533 4 u_riscv_top.core3_timer_val\[48\]
+port 1944 nsew
+rlabel metal2 s 230230 614465 230230 614465 4 u_riscv_top.core3_timer_val\[49\]
+port 1945 nsew
+rlabel metal2 s 230322 628609 230322 628609 4 u_riscv_top.core3_timer_val\[4\]
+port 1946 nsew
+rlabel metal1 s 235842 618358 235842 618358 4 u_riscv_top.core3_timer_val\[50\]
+port 1947 nsew
+rlabel metal1 s 235888 618290 235888 618290 4 u_riscv_top.core3_timer_val\[51\]
+port 1948 nsew
+rlabel metal3 s 230414 613445 230414 613445 4 u_riscv_top.core3_timer_val\[52\]
+port 1949 nsew
+rlabel metal1 s 235658 616930 235658 616930 4 u_riscv_top.core3_timer_val\[53\]
+port 1950 nsew
+rlabel metal1 s 235566 616862 235566 616862 4 u_riscv_top.core3_timer_val\[54\]
+port 1951 nsew
+rlabel metal1 s 233726 617134 233726 617134 4 u_riscv_top.core3_timer_val\[55\]
+port 1952 nsew
+rlabel metal1 s 233818 616998 233818 616998 4 u_riscv_top.core3_timer_val\[56\]
+port 1953 nsew
+rlabel metal1 s 233726 617066 233726 617066 4 u_riscv_top.core3_timer_val\[57\]
+port 1954 nsew
+rlabel metal1 s 235934 616182 235934 616182 4 u_riscv_top.core3_timer_val\[58\]
+port 1955 nsew
+rlabel metal1 s 235934 615978 235934 615978 4 u_riscv_top.core3_timer_val\[59\]
+port 1956 nsew
+rlabel metal2 s 230138 628507 230138 628507 4 u_riscv_top.core3_timer_val\[5\]
+port 1957 nsew
+rlabel metal1 s 235796 615910 235796 615910 4 u_riscv_top.core3_timer_val\[60\]
+port 1958 nsew
+rlabel metal1 s 233588 615774 233588 615774 4 u_riscv_top.core3_timer_val\[61\]
+port 1959 nsew
+rlabel metal1 s 233634 615638 233634 615638 4 u_riscv_top.core3_timer_val\[62\]
+port 1960 nsew
+rlabel metal2 s 229862 610861 229862 610861 4 u_riscv_top.core3_timer_val\[63\]
+port 1961 nsew
+rlabel metal2 s 229954 628405 229954 628405 4 u_riscv_top.core3_timer_val\[6\]
+port 1962 nsew
+rlabel metal2 s 229770 628303 229770 628303 4 u_riscv_top.core3_timer_val\[7\]
+port 1963 nsew
+rlabel metal2 s 229678 625957 229678 625957 4 u_riscv_top.core3_timer_val\[8\]
+port 1964 nsew
+rlabel metal3 s 230414 625107 230414 625107 4 u_riscv_top.core3_timer_val\[9\]
+port 1965 nsew
+rlabel metal3 s 229678 530757 229678 530757 4 u_riscv_top.core3_uid\[0\]
+port 1966 nsew
+rlabel metal2 s 229494 530553 229494 530553 4 u_riscv_top.core3_uid\[1\]
+port 1967 nsew
+rlabel metal3 s 122268 317356 122268 317356 4 u_riscv_top.core_clk_core0_skew
+port 1968 nsew
+rlabel metal3 s 240212 317356 240212 317356 4 u_riscv_top.core_clk_core1_skew
+port 1969 nsew
+rlabel metal3 s 122268 532372 122268 532372 4 u_riscv_top.core_clk_core2_skew
+port 1970 nsew
+rlabel metal3 s 240212 532372 240212 532372 4 u_riscv_top.core_clk_core3_skew
+port 1971 nsew
+rlabel metal3 s 226412 281724 226412 281724 4 u_riscv_top.core_clk_icon_skew
+port 1972 nsew
+rlabel metal3 s 352628 131308 352628 131308 4 u_riscv_top.core_clk_int\[0\]
+port 1973 nsew
+rlabel metal2 s 230414 280755 230414 280755 4 u_riscv_top.core_clk_int\[1\]
+port 1974 nsew
+rlabel metal3 s 351348 131716 351348 131716 4 u_riscv_top.core_clk_intf_skew
+port 1975 nsew
+rlabel metal2 s 216706 259716 216706 259716 4 u_riscv_top.core_dcache_addr\[0\]
+port 1976 nsew
+rlabel metal2 s 214866 265462 214866 265462 4 u_riscv_top.core_dcache_addr\[10\]
+port 1977 nsew
+rlabel metal2 s 171810 278953 171810 278953 4 u_riscv_top.core_dcache_addr\[11\]
+port 1978 nsew
+rlabel metal2 s 171626 277380 171626 277380 4 u_riscv_top.core_dcache_addr\[12\]
+port 1979 nsew
+rlabel metal2 s 214314 258934 214314 258934 4 u_riscv_top.core_dcache_addr\[13\]
+port 1980 nsew
+rlabel metal1 s 171304 279378 171304 279378 4 u_riscv_top.core_dcache_addr\[14\]
+port 1981 nsew
+rlabel metal2 s 213946 260396 213946 260396 4 u_riscv_top.core_dcache_addr\[15\]
+port 1982 nsew
+rlabel metal2 s 213670 271645 213670 271645 4 u_riscv_top.core_dcache_addr\[16\]
+port 1983 nsew
+rlabel metal2 s 213578 260566 213578 260566 4 u_riscv_top.core_dcache_addr\[17\]
+port 1984 nsew
+rlabel metal2 s 213394 260634 213394 260634 4 u_riscv_top.core_dcache_addr\[18\]
+port 1985 nsew
+rlabel metal2 s 213210 257999 213210 257999 4 u_riscv_top.core_dcache_addr\[19\]
+port 1986 nsew
+rlabel metal2 s 216522 260600 216522 260600 4 u_riscv_top.core_dcache_addr\[1\]
+port 1987 nsew
+rlabel metal2 s 213026 260702 213026 260702 4 u_riscv_top.core_dcache_addr\[20\]
+port 1988 nsew
+rlabel metal2 s 212842 259988 212842 259988 4 u_riscv_top.core_dcache_addr\[21\]
+port 1989 nsew
+rlabel metal2 s 212658 259835 212658 259835 4 u_riscv_top.core_dcache_addr\[22\]
+port 1990 nsew
+rlabel metal2 s 211094 261766 211094 261766 4 u_riscv_top.core_dcache_addr\[23\]
+port 1991 nsew
+rlabel metal2 s 212290 259002 212290 259002 4 u_riscv_top.core_dcache_addr\[24\]
+port 1992 nsew
+rlabel metal2 s 212106 257999 212106 257999 4 u_riscv_top.core_dcache_addr\[25\]
+port 1993 nsew
+rlabel metal2 s 211922 260226 211922 260226 4 u_riscv_top.core_dcache_addr\[26\]
+port 1994 nsew
+rlabel metal2 s 212198 272257 212198 272257 4 u_riscv_top.core_dcache_addr\[27\]
+port 1995 nsew
+rlabel metal2 s 211554 259954 211554 259954 4 u_riscv_top.core_dcache_addr\[28\]
+port 1996 nsew
+rlabel metal2 s 211370 257999 211370 257999 4 u_riscv_top.core_dcache_addr\[29\]
+port 1997 nsew
+rlabel metal2 s 173328 277380 173328 277380 4 u_riscv_top.core_dcache_addr\[2\]
+port 1998 nsew
+rlabel metal2 s 211186 261076 211186 261076 4 u_riscv_top.core_dcache_addr\[30\]
+port 1999 nsew
+rlabel metal2 s 211002 259682 211002 259682 4 u_riscv_top.core_dcache_addr\[31\]
+port 2000 nsew
+rlabel metal2 s 173144 277380 173144 277380 4 u_riscv_top.core_dcache_addr\[3\]
+port 2001 nsew
+rlabel metal2 s 215970 261042 215970 261042 4 u_riscv_top.core_dcache_addr\[4\]
+port 2002 nsew
+rlabel metal2 s 172776 277380 172776 277380 4 u_riscv_top.core_dcache_addr\[5\]
+port 2003 nsew
+rlabel metal2 s 215602 261314 215602 261314 4 u_riscv_top.core_dcache_addr\[6\]
+port 2004 nsew
+rlabel metal2 s 215418 261127 215418 261127 4 u_riscv_top.core_dcache_addr\[7\]
+port 2005 nsew
+rlabel metal2 s 215234 261246 215234 261246 4 u_riscv_top.core_dcache_addr\[8\]
+port 2006 nsew
+rlabel metal2 s 172040 277380 172040 277380 4 u_riscv_top.core_dcache_addr\[9\]
+port 2007 nsew
+rlabel metal2 s 210450 261280 210450 261280 4 u_riscv_top.core_dcache_cmd
+port 2008 nsew
+rlabel metal1 s 206724 261698 206724 261698 4 u_riscv_top.core_dcache_rdata\[0\]
+port 2009 nsew
+rlabel metal2 s 183632 277380 183632 277380 4 u_riscv_top.core_dcache_rdata\[10\]
+port 2010 nsew
+rlabel metal2 s 226458 261059 226458 261059 4 u_riscv_top.core_dcache_rdata\[11\]
+port 2011 nsew
+rlabel metal2 s 210634 272476 210634 272476 4 u_riscv_top.core_dcache_rdata\[12\]
+port 2012 nsew
+rlabel metal1 s 204148 262990 204148 262990 4 u_riscv_top.core_dcache_rdata\[13\]
+port 2013 nsew
+rlabel metal2 s 213210 269756 213210 269756 4 u_riscv_top.core_dcache_rdata\[14\]
+port 2014 nsew
+rlabel metal2 s 225722 261790 225722 261790 4 u_riscv_top.core_dcache_rdata\[15\]
+port 2015 nsew
+rlabel metal2 s 182528 277380 182528 277380 4 u_riscv_top.core_dcache_rdata\[16\]
+port 2016 nsew
+rlabel metal2 s 225354 262096 225354 262096 4 u_riscv_top.core_dcache_rdata\[17\]
+port 2017 nsew
+rlabel metal1 s 182436 276250 182436 276250 4 u_riscv_top.core_dcache_rdata\[18\]
+port 2018 nsew
+rlabel metal2 s 224986 261739 224986 261739 4 u_riscv_top.core_dcache_rdata\[19\]
+port 2019 nsew
+rlabel metal2 s 185150 277380 185150 277380 4 u_riscv_top.core_dcache_rdata\[1\]
+port 2020 nsew
+rlabel metal2 s 224802 261960 224802 261960 4 u_riscv_top.core_dcache_rdata\[20\]
+port 2021 nsew
+rlabel metal2 s 181608 277380 181608 277380 4 u_riscv_top.core_dcache_rdata\[21\]
+port 2022 nsew
+rlabel metal2 s 224434 261756 224434 261756 4 u_riscv_top.core_dcache_rdata\[22\]
+port 2023 nsew
+rlabel metal2 s 224250 261858 224250 261858 4 u_riscv_top.core_dcache_rdata\[23\]
+port 2024 nsew
+rlabel metal2 s 181056 277380 181056 277380 4 u_riscv_top.core_dcache_rdata\[24\]
+port 2025 nsew
+rlabel metal2 s 223882 262028 223882 262028 4 u_riscv_top.core_dcache_rdata\[25\]
+port 2026 nsew
+rlabel metal2 s 180734 279456 180734 279456 4 u_riscv_top.core_dcache_rdata\[26\]
+port 2027 nsew
+rlabel metal1 s 201526 261834 201526 261834 4 u_riscv_top.core_dcache_rdata\[27\]
+port 2028 nsew
+rlabel metal1 s 201480 261766 201480 261766 4 u_riscv_top.core_dcache_rdata\[28\]
+port 2029 nsew
+rlabel metal1 s 201434 263126 201434 263126 4 u_riscv_top.core_dcache_rdata\[29\]
+port 2030 nsew
+rlabel metal1 s 207644 272306 207644 272306 4 u_riscv_top.core_dcache_rdata\[2\]
+port 2031 nsew
+rlabel metal2 s 179952 277380 179952 277380 4 u_riscv_top.core_dcache_rdata\[30\]
+port 2032 nsew
+rlabel metal2 s 222778 262436 222778 262436 4 u_riscv_top.core_dcache_rdata\[31\]
+port 2033 nsew
+rlabel metal2 s 227930 262572 227930 262572 4 u_riscv_top.core_dcache_rdata\[3\]
+port 2034 nsew
+rlabel metal2 s 227746 262487 227746 262487 4 u_riscv_top.core_dcache_rdata\[4\]
+port 2035 nsew
+rlabel metal2 s 227562 262708 227562 262708 4 u_riscv_top.core_dcache_rdata\[5\]
+port 2036 nsew
+rlabel metal2 s 227378 262640 227378 262640 4 u_riscv_top.core_dcache_rdata\[6\]
+port 2037 nsew
+rlabel metal2 s 227194 262810 227194 262810 4 u_riscv_top.core_dcache_rdata\[7\]
+port 2038 nsew
+rlabel metal2 s 227010 262538 227010 262538 4 u_riscv_top.core_dcache_rdata\[8\]
+port 2039 nsew
+rlabel metal2 s 183908 277380 183908 277380 4 u_riscv_top.core_dcache_rdata\[9\]
+port 2040 nsew
+rlabel metal2 s 210266 262402 210266 262402 4 u_riscv_top.core_dcache_req
+port 2041 nsew
+rlabel metal2 s 210082 258696 210082 258696 4 u_riscv_top.core_dcache_req_ack
+port 2042 nsew
+rlabel metal1 s 185610 277882 185610 277882 4 u_riscv_top.core_dcache_resp\[0\]
+port 2043 nsew
+rlabel metal2 s 228666 262606 228666 262606 4 u_riscv_top.core_dcache_resp\[1\]
+port 2044 nsew
+rlabel metal2 s 222594 261926 222594 261926 4 u_riscv_top.core_dcache_wdata\[0\]
+port 2045 nsew
+rlabel metal2 s 220754 262504 220754 262504 4 u_riscv_top.core_dcache_wdata\[10\]
+port 2046 nsew
+rlabel metal2 s 177606 278538 177606 278538 4 u_riscv_top.core_dcache_wdata\[11\]
+port 2047 nsew
+rlabel metal2 s 177422 279490 177422 279490 4 u_riscv_top.core_dcache_wdata\[12\]
+port 2048 nsew
+rlabel metal2 s 220202 265326 220202 265326 4 u_riscv_top.core_dcache_wdata\[13\]
+port 2049 nsew
+rlabel metal2 s 220018 263354 220018 263354 4 u_riscv_top.core_dcache_wdata\[14\]
+port 2050 nsew
+rlabel metal2 s 219834 257999 219834 257999 4 u_riscv_top.core_dcache_wdata\[15\]
+port 2051 nsew
+rlabel metal2 s 219650 263456 219650 263456 4 u_riscv_top.core_dcache_wdata\[16\]
+port 2052 nsew
+rlabel metal2 s 219466 263167 219466 263167 4 u_riscv_top.core_dcache_wdata\[17\]
+port 2053 nsew
+rlabel metal2 s 176364 277380 176364 277380 4 u_riscv_top.core_dcache_wdata\[18\]
+port 2054 nsew
+rlabel metal2 s 219098 263422 219098 263422 4 u_riscv_top.core_dcache_wdata\[19\]
+port 2055 nsew
+rlabel metal2 s 222686 268041 222686 268041 4 u_riscv_top.core_dcache_wdata\[1\]
+port 2056 nsew
+rlabel metal2 s 218914 257999 218914 257999 4 u_riscv_top.core_dcache_wdata\[20\]
+port 2057 nsew
+rlabel metal1 s 218408 262854 218408 262854 4 u_riscv_top.core_dcache_wdata\[21\]
+port 2058 nsew
+rlabel metal2 s 175628 277380 175628 277380 4 u_riscv_top.core_dcache_wdata\[22\]
+port 2059 nsew
+rlabel metal2 s 218362 263252 218362 263252 4 u_riscv_top.core_dcache_wdata\[23\]
+port 2060 nsew
+rlabel metal2 s 218178 263235 218178 263235 4 u_riscv_top.core_dcache_wdata\[24\]
+port 2061 nsew
+rlabel metal2 s 215326 262752 215326 262752 4 u_riscv_top.core_dcache_wdata\[25\]
+port 2062 nsew
+rlabel metal2 s 217810 261722 217810 261722 4 u_riscv_top.core_dcache_wdata\[26\]
+port 2063 nsew
+rlabel metal2 s 174616 277380 174616 277380 4 u_riscv_top.core_dcache_wdata\[27\]
+port 2064 nsew
+rlabel metal2 s 217442 263082 217442 263082 4 u_riscv_top.core_dcache_wdata\[28\]
+port 2065 nsew
+rlabel metal2 s 213486 262854 213486 262854 4 u_riscv_top.core_dcache_wdata\[29\]
+port 2066 nsew
+rlabel metal2 s 222226 263915 222226 263915 4 u_riscv_top.core_dcache_wdata\[2\]
+port 2067 nsew
+rlabel metal2 s 174156 277380 174156 277380 4 u_riscv_top.core_dcache_wdata\[30\]
+port 2068 nsew
+rlabel metal2 s 216890 260668 216890 260668 4 u_riscv_top.core_dcache_wdata\[31\]
+port 2069 nsew
+rlabel metal2 s 222042 263796 222042 263796 4 u_riscv_top.core_dcache_wdata\[3\]
+port 2070 nsew
+rlabel metal2 s 221858 264204 221858 264204 4 u_riscv_top.core_dcache_wdata\[4\]
+port 2071 nsew
+rlabel metal2 s 221674 263966 221674 263966 4 u_riscv_top.core_dcache_wdata\[5\]
+port 2072 nsew
+rlabel metal2 s 221490 264170 221490 264170 4 u_riscv_top.core_dcache_wdata\[6\]
+port 2073 nsew
+rlabel metal2 s 221306 264068 221306 264068 4 u_riscv_top.core_dcache_wdata\[7\]
+port 2074 nsew
+rlabel metal2 s 221122 263762 221122 263762 4 u_riscv_top.core_dcache_wdata\[8\]
+port 2075 nsew
+rlabel metal2 s 220938 263983 220938 263983 4 u_riscv_top.core_dcache_wdata\[9\]
+port 2076 nsew
+rlabel metal2 s 210818 266142 210818 266142 4 u_riscv_top.core_dcache_width\[0\]
+port 2077 nsew
+rlabel metal2 s 210634 264136 210634 264136 4 u_riscv_top.core_dcache_width\[1\]
+port 2078 nsew
+rlabel metal2 s 194166 273619 194166 273619 4 u_riscv_top.core_dmem_addr\[0\]
+port 2079 nsew
+rlabel metal1 s 192556 269722 192556 269722 4 u_riscv_top.core_dmem_addr\[10\]
+port 2080 nsew
+rlabel metal2 s 192142 273823 192142 273823 4 u_riscv_top.core_dmem_addr\[11\]
+port 2081 nsew
+rlabel metal2 s 192050 270990 192050 270990 4 u_riscv_top.core_dmem_addr\[12\]
+port 2082 nsew
+rlabel metal1 s 192096 272510 192096 272510 4 u_riscv_top.core_dmem_addr\[13\]
+port 2083 nsew
+rlabel metal2 s 191544 272612 191544 272612 4 u_riscv_top.core_dmem_addr\[14\]
+port 2084 nsew
+rlabel metal2 s 191314 271388 191314 271388 4 u_riscv_top.core_dmem_addr\[15\]
+port 2085 nsew
+rlabel metal1 s 193384 271558 193384 271558 4 u_riscv_top.core_dmem_addr\[16\]
+port 2086 nsew
+rlabel metal1 s 191452 270742 191452 270742 4 u_riscv_top.core_dmem_addr\[17\]
+port 2087 nsew
+rlabel metal1 s 193430 271014 193430 271014 4 u_riscv_top.core_dmem_addr\[18\]
+port 2088 nsew
+rlabel metal1 s 193292 271218 193292 271218 4 u_riscv_top.core_dmem_addr\[19\]
+port 2089 nsew
+rlabel metal2 s 194074 278776 194074 278776 4 u_riscv_top.core_dmem_addr\[1\]
+port 2090 nsew
+rlabel metal1 s 190762 271558 190762 271558 4 u_riscv_top.core_dmem_addr\[20\]
+port 2091 nsew
+rlabel metal1 s 233588 262922 233588 262922 4 u_riscv_top.core_dmem_addr\[21\]
+port 2092 nsew
+rlabel metal2 s 233174 264782 233174 264782 4 u_riscv_top.core_dmem_addr\[22\]
+port 2093 nsew
+rlabel metal2 s 232990 264612 232990 264612 4 u_riscv_top.core_dmem_addr\[23\]
+port 2094 nsew
+rlabel metal2 s 232806 264680 232806 264680 4 u_riscv_top.core_dmem_addr\[24\]
+port 2095 nsew
+rlabel metal2 s 195270 271592 195270 271592 4 u_riscv_top.core_dmem_addr\[25\]
+port 2096 nsew
+rlabel metal2 s 232438 264510 232438 264510 4 u_riscv_top.core_dmem_addr\[26\]
+port 2097 nsew
+rlabel metal1 s 232484 262854 232484 262854 4 u_riscv_top.core_dmem_addr\[27\]
+port 2098 nsew
+rlabel metal1 s 195270 270878 195270 270878 4 u_riscv_top.core_dmem_addr\[28\]
+port 2099 nsew
+rlabel metal2 s 231886 268352 231886 268352 4 u_riscv_top.core_dmem_addr\[29\]
+port 2100 nsew
+rlabel metal1 s 193798 273258 193798 273258 4 u_riscv_top.core_dmem_addr\[2\]
+port 2101 nsew
+rlabel metal2 s 231702 263184 231702 263184 4 u_riscv_top.core_dmem_addr\[30\]
+port 2102 nsew
+rlabel metal2 s 231518 262470 231518 262470 4 u_riscv_top.core_dmem_addr\[31\]
+port 2103 nsew
+rlabel metal1 s 194580 278698 194580 278698 4 u_riscv_top.core_dmem_addr\[3\]
+port 2104 nsew
+rlabel metal2 s 193522 276600 193522 276600 4 u_riscv_top.core_dmem_addr\[4\]
+port 2105 nsew
+rlabel metal2 s 193338 276362 193338 276362 4 u_riscv_top.core_dmem_addr\[5\]
+port 2106 nsew
+rlabel metal4 s 193131 278732 193131 278732 4 u_riscv_top.core_dmem_addr\[6\]
+port 2107 nsew
+rlabel metal2 s 192970 276634 192970 276634 4 u_riscv_top.core_dmem_addr\[7\]
+port 2108 nsew
+rlabel metal2 s 192878 274911 192878 274911 4 u_riscv_top.core_dmem_addr\[8\]
+port 2109 nsew
+rlabel metal2 s 192602 276566 192602 276566 4 u_riscv_top.core_dmem_addr\[9\]
+port 2110 nsew
+rlabel metal2 s 230966 265394 230966 265394 4 u_riscv_top.core_dmem_bl\[0\]
+port 2111 nsew
+rlabel metal2 s 230782 265360 230782 265360 4 u_riscv_top.core_dmem_bl\[1\]
+port 2112 nsew
+rlabel metal2 s 230598 265411 230598 265411 4 u_riscv_top.core_dmem_bl\[2\]
+port 2113 nsew
+rlabel metal2 s 230414 265258 230414 265258 4 u_riscv_top.core_dmem_cmd
+port 2114 nsew
+rlabel metal2 s 248998 260294 248998 260294 4 u_riscv_top.core_dmem_rdata\[0\]
+port 2115 nsew
+rlabel metal3 s 228298 270164 228298 270164 4 u_riscv_top.core_dmem_rdata\[10\]
+port 2116 nsew
+rlabel metal1 s 206540 271966 206540 271966 4 u_riscv_top.core_dmem_rdata\[11\]
+port 2117 nsew
+rlabel metal2 s 209346 270810 209346 270810 4 u_riscv_top.core_dmem_rdata\[12\]
+port 2118 nsew
+rlabel metal1 s 208150 273666 208150 273666 4 u_riscv_top.core_dmem_rdata\[13\]
+port 2119 nsew
+rlabel metal2 s 210496 272612 210496 272612 4 u_riscv_top.core_dmem_rdata\[14\]
+port 2120 nsew
+rlabel metal1 s 207552 272034 207552 272034 4 u_riscv_top.core_dmem_rdata\[15\]
+port 2121 nsew
+rlabel metal1 s 206678 272102 206678 272102 4 u_riscv_top.core_dmem_rdata\[16\]
+port 2122 nsew
+rlabel metal2 s 245870 259274 245870 259274 4 u_riscv_top.core_dmem_rdata\[17\]
+port 2123 nsew
+rlabel metal2 s 245686 266023 245686 266023 4 u_riscv_top.core_dmem_rdata\[18\]
+port 2124 nsew
+rlabel metal2 s 245502 266244 245502 266244 4 u_riscv_top.core_dmem_rdata\[19\]
+port 2125 nsew
+rlabel metal2 s 248814 259308 248814 259308 4 u_riscv_top.core_dmem_rdata\[1\]
+port 2126 nsew
+rlabel metal2 s 245318 259376 245318 259376 4 u_riscv_top.core_dmem_rdata\[20\]
+port 2127 nsew
+rlabel metal2 s 245134 265938 245134 265938 4 u_riscv_top.core_dmem_rdata\[21\]
+port 2128 nsew
+rlabel metal2 s 244950 266108 244950 266108 4 u_riscv_top.core_dmem_rdata\[22\]
+port 2129 nsew
+rlabel metal2 s 244766 266006 244766 266006 4 u_riscv_top.core_dmem_rdata\[23\]
+port 2130 nsew
+rlabel metal2 s 244582 266074 244582 266074 4 u_riscv_top.core_dmem_rdata\[24\]
+port 2131 nsew
+rlabel metal1 s 244628 262922 244628 262922 4 u_riscv_top.core_dmem_rdata\[25\]
+port 2132 nsew
+rlabel metal2 s 201250 277110 201250 277110 4 u_riscv_top.core_dmem_rdata\[26\]
+port 2133 nsew
+rlabel metal2 s 201066 277246 201066 277246 4 u_riscv_top.core_dmem_rdata\[27\]
+port 2134 nsew
+rlabel metal2 s 203366 273836 203366 273836 4 u_riscv_top.core_dmem_rdata\[28\]
+port 2135 nsew
+rlabel metal2 s 206356 272612 206356 272612 4 u_riscv_top.core_dmem_rdata\[29\]
+port 2136 nsew
+rlabel metal2 s 248630 261008 248630 261008 4 u_riscv_top.core_dmem_rdata\[2\]
+port 2137 nsew
+rlabel metal1 s 214590 275026 214590 275026 4 u_riscv_top.core_dmem_rdata\[30\]
+port 2138 nsew
+rlabel metal2 s 200330 277960 200330 277960 4 u_riscv_top.core_dmem_rdata\[31\]
+port 2139 nsew
+rlabel metal2 s 248446 260447 248446 260447 4 u_riscv_top.core_dmem_rdata\[3\]
+port 2140 nsew
+rlabel metal1 s 206586 272918 206586 272918 4 u_riscv_top.core_dmem_rdata\[4\]
+port 2141 nsew
+rlabel metal1 s 226596 269790 226596 269790 4 u_riscv_top.core_dmem_rdata\[5\]
+port 2142 nsew
+rlabel metal2 s 247894 267536 247894 267536 4 u_riscv_top.core_dmem_rdata\[6\]
+port 2143 nsew
+rlabel metal2 s 247710 259172 247710 259172 4 u_riscv_top.core_dmem_rdata\[7\]
+port 2144 nsew
+rlabel metal2 s 204332 272612 204332 272612 4 u_riscv_top.core_dmem_rdata\[8\]
+port 2145 nsew
+rlabel metal1 s 232668 260678 232668 260678 4 u_riscv_top.core_dmem_rdata\[9\]
+port 2146 nsew
+rlabel metal2 s 216982 272986 216982 272986 4 u_riscv_top.core_dmem_req
+port 2147 nsew
+rlabel metal2 s 230046 266822 230046 266822 4 u_riscv_top.core_dmem_req_ack
+port 2148 nsew
+rlabel metal2 s 249366 259070 249366 259070 4 u_riscv_top.core_dmem_resp\[0\]
+port 2149 nsew
+rlabel metal2 s 249182 259036 249182 259036 4 u_riscv_top.core_dmem_resp\[1\]
+port 2150 nsew
+rlabel metal2 s 200146 277756 200146 277756 4 u_riscv_top.core_dmem_wdata\[0\]
+port 2151 nsew
+rlabel metal2 s 198214 275689 198214 275689 4 u_riscv_top.core_dmem_wdata\[10\]
+port 2152 nsew
+rlabel metal2 s 198122 277858 198122 277858 4 u_riscv_top.core_dmem_wdata\[11\]
+port 2153 nsew
+rlabel metal2 s 197938 278028 197938 278028 4 u_riscv_top.core_dmem_wdata\[12\]
+port 2154 nsew
+rlabel metal2 s 197754 277790 197754 277790 4 u_riscv_top.core_dmem_wdata\[13\]
+port 2155 nsew
+rlabel metal2 s 197570 277994 197570 277994 4 u_riscv_top.core_dmem_wdata\[14\]
+port 2156 nsew
+rlabel metal2 s 201434 277542 201434 277542 4 u_riscv_top.core_dmem_wdata\[15\]
+port 2157 nsew
+rlabel metal2 s 197202 277773 197202 277773 4 u_riscv_top.core_dmem_wdata\[16\]
+port 2158 nsew
+rlabel metal2 s 196926 276080 196926 276080 4 u_riscv_top.core_dmem_wdata\[17\]
+port 2159 nsew
+rlabel metal2 s 196834 277926 196834 277926 4 u_riscv_top.core_dmem_wdata\[18\]
+port 2160 nsew
+rlabel metal2 s 196650 277654 196650 277654 4 u_riscv_top.core_dmem_wdata\[19\]
+port 2161 nsew
+rlabel metal2 s 202170 267720 202170 267720 4 u_riscv_top.core_dmem_wdata\[1\]
+port 2162 nsew
+rlabel metal2 s 196466 277909 196466 277909 4 u_riscv_top.core_dmem_wdata\[20\]
+port 2163 nsew
+rlabel metal1 s 234278 260712 234278 260712 4 u_riscv_top.core_dmem_wdata\[21\]
+port 2164 nsew
+rlabel metal1 s 198490 273598 198490 273598 4 u_riscv_top.core_dmem_wdata\[22\]
+port 2165 nsew
+rlabel metal2 s 195914 278368 195914 278368 4 u_riscv_top.core_dmem_wdata\[23\]
+port 2166 nsew
+rlabel metal2 s 195730 278470 195730 278470 4 u_riscv_top.core_dmem_wdata\[24\]
+port 2167 nsew
+rlabel metal2 s 195546 278572 195546 278572 4 u_riscv_top.core_dmem_wdata\[25\]
+port 2168 nsew
+rlabel metal2 s 195362 278504 195362 278504 4 u_riscv_top.core_dmem_wdata\[26\]
+port 2169 nsew
+rlabel metal2 s 195178 278708 195178 278708 4 u_riscv_top.core_dmem_wdata\[27\]
+port 2170 nsew
+rlabel metal2 s 194994 278334 194994 278334 4 u_riscv_top.core_dmem_wdata\[28\]
+port 2171 nsew
+rlabel metal2 s 194810 277076 194810 277076 4 u_riscv_top.core_dmem_wdata\[29\]
+port 2172 nsew
+rlabel metal2 s 199778 278674 199778 278674 4 u_riscv_top.core_dmem_wdata\[2\]
+port 2173 nsew
+rlabel metal2 s 194626 276804 194626 276804 4 u_riscv_top.core_dmem_wdata\[30\]
+port 2174 nsew
+rlabel metal2 s 194442 278385 194442 278385 4 u_riscv_top.core_dmem_wdata\[31\]
+port 2175 nsew
+rlabel metal2 s 199594 278640 199594 278640 4 u_riscv_top.core_dmem_wdata\[3\]
+port 2176 nsew
+rlabel metal2 s 202262 264180 202262 264180 4 u_riscv_top.core_dmem_wdata\[4\]
+port 2177 nsew
+rlabel metal2 s 199088 276658 199088 276658 4 u_riscv_top.core_dmem_wdata\[5\]
+port 2178 nsew
+rlabel metal1 s 212152 263534 212152 263534 4 u_riscv_top.core_dmem_wdata\[6\]
+port 2179 nsew
+rlabel metal2 s 198858 270208 198858 270208 4 u_riscv_top.core_dmem_wdata\[7\]
+port 2180 nsew
+rlabel metal2 s 200744 267720 200744 267720 4 u_riscv_top.core_dmem_wdata\[8\]
+port 2181 nsew
+rlabel metal2 s 198490 279116 198490 279116 4 u_riscv_top.core_dmem_wdata\[9\]
+port 2182 nsew
+rlabel metal2 s 231334 258900 231334 258900 4 u_riscv_top.core_dmem_width\[0\]
+port 2183 nsew
+rlabel metal2 s 231150 259223 231150 259223 4 u_riscv_top.core_dmem_width\[1\]
+port 2184 nsew
+rlabel metal2 s 153410 277756 153410 277756 4 u_riscv_top.core_icache_addr\[0\]
+port 2185 nsew
+rlabel metal2 s 194534 258900 194534 258900 4 u_riscv_top.core_icache_addr\[10\]
+port 2186 nsew
+rlabel metal2 s 152030 275298 152030 275298 4 u_riscv_top.core_icache_addr\[11\]
+port 2187 nsew
+rlabel metal2 s 193798 273462 193798 273462 4 u_riscv_top.core_icache_addr\[12\]
+port 2188 nsew
+rlabel metal2 s 193982 264000 193982 264000 4 u_riscv_top.core_icache_addr\[13\]
+port 2189 nsew
+rlabel metal1 s 194028 262786 194028 262786 4 u_riscv_top.core_icache_addr\[14\]
+port 2190 nsew
+rlabel metal2 s 193614 266720 193614 266720 4 u_riscv_top.core_icache_addr\[15\]
+port 2191 nsew
+rlabel metal2 s 193430 266652 193430 266652 4 u_riscv_top.core_icache_addr\[16\]
+port 2192 nsew
+rlabel metal1 s 192924 260814 192924 260814 4 u_riscv_top.core_icache_addr\[17\]
+port 2193 nsew
+rlabel metal2 s 192694 274686 192694 274686 4 u_riscv_top.core_icache_addr\[18\]
+port 2194 nsew
+rlabel metal2 s 193062 274329 193062 274329 4 u_riscv_top.core_icache_addr\[19\]
+port 2195 nsew
+rlabel metal2 s 153318 269471 153318 269471 4 u_riscv_top.core_icache_addr\[1\]
+port 2196 nsew
+rlabel metal2 s 192694 263898 192694 263898 4 u_riscv_top.core_icache_addr\[20\]
+port 2197 nsew
+rlabel metal2 s 192510 257999 192510 257999 4 u_riscv_top.core_icache_addr\[21\]
+port 2198 nsew
+rlabel metal1 s 192740 262650 192740 262650 4 u_riscv_top.core_icache_addr\[22\]
+port 2199 nsew
+rlabel metal1 s 192464 262786 192464 262786 4 u_riscv_top.core_icache_addr\[23\]
+port 2200 nsew
+rlabel metal2 s 191958 265190 191958 265190 4 u_riscv_top.core_icache_addr\[24\]
+port 2201 nsew
+rlabel metal2 s 191774 267502 191774 267502 4 u_riscv_top.core_icache_addr\[25\]
+port 2202 nsew
+rlabel metal2 s 191590 264816 191590 264816 4 u_riscv_top.core_icache_addr\[26\]
+port 2203 nsew
+rlabel metal2 s 191406 264306 191406 264306 4 u_riscv_top.core_icache_addr\[27\]
+port 2204 nsew
+rlabel metal2 s 191222 257999 191222 257999 4 u_riscv_top.core_icache_addr\[28\]
+port 2205 nsew
+rlabel metal1 s 191360 262786 191360 262786 4 u_riscv_top.core_icache_addr\[29\]
+port 2206 nsew
+rlabel metal2 s 153042 277484 153042 277484 4 u_riscv_top.core_icache_addr\[2\]
+port 2207 nsew
+rlabel metal2 s 190854 264714 190854 264714 4 u_riscv_top.core_icache_addr\[30\]
+port 2208 nsew
+rlabel metal1 s 190670 257958 190670 257958 4 u_riscv_top.core_icache_addr\[31\]
+port 2209 nsew
+rlabel metal2 s 194902 273972 194902 273972 4 u_riscv_top.core_icache_addr\[3\]
+port 2210 nsew
+rlabel metal2 s 195730 272578 195730 272578 4 u_riscv_top.core_icache_addr\[4\]
+port 2211 nsew
+rlabel metal2 s 195638 272544 195638 272544 4 u_riscv_top.core_icache_addr\[5\]
+port 2212 nsew
+rlabel metal2 s 195546 272561 195546 272561 4 u_riscv_top.core_icache_addr\[6\]
+port 2213 nsew
+rlabel metal2 s 195086 273564 195086 273564 4 u_riscv_top.core_icache_addr\[7\]
+port 2214 nsew
+rlabel metal2 s 151938 270854 151938 270854 4 u_riscv_top.core_icache_addr\[8\]
+port 2215 nsew
+rlabel metal2 s 155618 275196 155618 275196 4 u_riscv_top.core_icache_addr\[9\]
+port 2216 nsew
+rlabel metal1 s 154928 278630 154928 278630 4 u_riscv_top.core_icache_bl\[0\]
+port 2217 nsew
+rlabel metal1 s 154744 278426 154744 278426 4 u_riscv_top.core_icache_bl\[1\]
+port 2218 nsew
+rlabel metal1 s 154422 278698 154422 278698 4 u_riscv_top.core_icache_bl\[2\]
+port 2219 nsew
+rlabel metal2 s 190486 258016 190486 258016 4 u_riscv_top.core_icache_cmd
+port 2220 nsew
+rlabel metal2 s 160218 277586 160218 277586 4 u_riscv_top.core_icache_rdata\[0\]
+port 2221 nsew
+rlabel metal2 s 158378 276770 158378 276770 4 u_riscv_top.core_icache_rdata\[10\]
+port 2222 nsew
+rlabel metal2 s 158194 276498 158194 276498 4 u_riscv_top.core_icache_rdata\[11\]
+port 2223 nsew
+rlabel metal2 s 158010 278606 158010 278606 4 u_riscv_top.core_icache_rdata\[12\]
+port 2224 nsew
+rlabel metal1 s 158838 278698 158838 278698 4 u_riscv_top.core_icache_rdata\[13\]
+port 2225 nsew
+rlabel metal1 s 158608 277882 158608 277882 4 u_riscv_top.core_icache_rdata\[14\]
+port 2226 nsew
+rlabel metal2 s 157458 277246 157458 277246 4 u_riscv_top.core_icache_rdata\[15\]
+port 2227 nsew
+rlabel metal2 s 157228 278732 157228 278732 4 u_riscv_top.core_icache_rdata\[16\]
+port 2228 nsew
+rlabel metal2 s 157090 275444 157090 275444 4 u_riscv_top.core_icache_rdata\[17\]
+port 2229 nsew
+rlabel metal2 s 156906 277314 156906 277314 4 u_riscv_top.core_icache_rdata\[18\]
+port 2230 nsew
+rlabel metal2 s 156722 275478 156722 275478 4 u_riscv_top.core_icache_rdata\[19\]
+port 2231 nsew
+rlabel metal2 s 160034 278300 160034 278300 4 u_riscv_top.core_icache_rdata\[1\]
+port 2232 nsew
+rlabel metal2 s 156538 273744 156538 273744 4 u_riscv_top.core_icache_rdata\[20\]
+port 2233 nsew
+rlabel metal2 s 195362 271779 195362 271779 4 u_riscv_top.core_icache_rdata\[21\]
+port 2234 nsew
+rlabel metal2 s 156170 275512 156170 275512 4 u_riscv_top.core_icache_rdata\[22\]
+port 2235 nsew
+rlabel metal1 s 159942 278664 159942 278664 4 u_riscv_top.core_icache_rdata\[23\]
+port 2236 nsew
+rlabel metal1 s 155204 272306 155204 272306 4 u_riscv_top.core_icache_rdata\[24\]
+port 2237 nsew
+rlabel metal1 s 160034 278596 160034 278596 4 u_riscv_top.core_icache_rdata\[25\]
+port 2238 nsew
+rlabel metal1 s 155112 267750 155112 267750 4 u_riscv_top.core_icache_rdata\[26\]
+port 2239 nsew
+rlabel metal2 s 160126 278324 160126 278324 4 u_riscv_top.core_icache_rdata\[27\]
+port 2240 nsew
+rlabel metal2 s 154836 269620 154836 269620 4 u_riscv_top.core_icache_rdata\[28\]
+port 2241 nsew
+rlabel metal2 s 160678 278290 160678 278290 4 u_riscv_top.core_icache_rdata\[29\]
+port 2242 nsew
+rlabel metal1 s 160494 278460 160494 278460 4 u_riscv_top.core_icache_rdata\[2\]
+port 2243 nsew
+rlabel metal2 s 154790 273564 154790 273564 4 u_riscv_top.core_icache_rdata\[30\]
+port 2244 nsew
+rlabel metal2 s 154514 274424 154514 274424 4 u_riscv_top.core_icache_rdata\[31\]
+port 2245 nsew
+rlabel metal2 s 159666 279150 159666 279150 4 u_riscv_top.core_icache_rdata\[3\]
+port 2246 nsew
+rlabel metal2 s 159482 274458 159482 274458 4 u_riscv_top.core_icache_rdata\[4\]
+port 2247 nsew
+rlabel metal2 s 159298 279218 159298 279218 4 u_riscv_top.core_icache_rdata\[5\]
+port 2248 nsew
+rlabel metal2 s 158792 272748 158792 272748 4 u_riscv_top.core_icache_rdata\[6\]
+port 2249 nsew
+rlabel metal2 s 158930 279184 158930 279184 4 u_riscv_top.core_icache_rdata\[7\]
+port 2250 nsew
+rlabel metal1 s 158884 272986 158884 272986 4 u_riscv_top.core_icache_rdata\[8\]
+port 2251 nsew
+rlabel metal2 s 158562 279048 158562 279048 4 u_riscv_top.core_icache_rdata\[9\]
+port 2252 nsew
+rlabel metal1 s 147016 272578 147016 272578 4 u_riscv_top.core_icache_req
+port 2253 nsew
+rlabel metal2 s 190065 257788 190065 257788 4 u_riscv_top.core_icache_req_ack
+port 2254 nsew
+rlabel metal2 s 160586 279082 160586 279082 4 u_riscv_top.core_icache_resp\[0\]
+port 2255 nsew
+rlabel metal2 s 160402 275410 160402 275410 4 u_riscv_top.core_icache_resp\[1\]
+port 2256 nsew
+rlabel metal2 s 160770 277984 160770 277984 4 u_riscv_top.core_icache_width\[0\]
+port 2257 nsew
+rlabel metal1 s 153686 272374 153686 272374 4 u_riscv_top.core_icache_width\[1\]
+port 2258 nsew
+rlabel metal1 s 172454 279888 172454 279888 4 u_riscv_top.cpu_core_rst_n\[0\]
+port 2259 nsew
+rlabel metal2 s 238510 457181 238510 457181 4 u_riscv_top.cpu_core_rst_n\[1\]
+port 2260 nsew
+rlabel metal3 s 237889 533324 237889 533324 4 u_riscv_top.cpu_core_rst_n\[2\]
+port 2261 nsew
+rlabel metal2 s 238510 565437 238510 565437 4 u_riscv_top.cpu_core_rst_n\[3\]
+port 2262 nsew
+rlabel metal2 s 153594 681214 153594 681214 4 u_riscv_top.cpu_intf_rst_n
+port 2263 nsew
+rlabel metal4 s 46086 25788 46086 25788 4 u_riscv_top.dcache_mem_addr0\[0\]
+port 2264 nsew
+rlabel metal4 s 47174 25788 47174 25788 4 u_riscv_top.dcache_mem_addr0\[1\]
+port 2265 nsew
+rlabel metal3 s 29345 54196 29345 54196 4 u_riscv_top.dcache_mem_addr0\[2\]
+port 2266 nsew
+rlabel metal3 s 29391 55964 29391 55964 4 u_riscv_top.dcache_mem_addr0\[3\]
+port 2267 nsew
+rlabel metal3 s 29299 57052 29299 57052 4 u_riscv_top.dcache_mem_addr0\[4\]
+port 2268 nsew
+rlabel metal3 s 29529 58820 29529 58820 4 u_riscv_top.dcache_mem_addr0\[5\]
+port 2269 nsew
+rlabel metal3 s 28701 59772 28701 59772 4 u_riscv_top.dcache_mem_addr0\[6\]
+port 2270 nsew
+rlabel metal3 s 29253 61948 29253 61948 4 u_riscv_top.dcache_mem_addr0\[7\]
+port 2271 nsew
+rlabel metal3 s 29575 62900 29575 62900 4 u_riscv_top.dcache_mem_addr0\[8\]
+port 2272 nsew
+rlabel metal1 s 185702 172618 185702 172618 4 u_riscv_top.dcache_mem_addr1\[0\]
+port 2273 nsew
+rlabel metal2 s 180458 158950 180458 158950 4 u_riscv_top.dcache_mem_addr1\[1\]
+port 2274 nsew
+rlabel metal3 s 166903 45350 166903 45350 4 u_riscv_top.dcache_mem_addr1\[2\]
+port 2275 nsew
+rlabel metal2 s 176410 107644 176410 107644 4 u_riscv_top.dcache_mem_addr1\[3\]
+port 2276 nsew
+rlabel metal2 s 180274 106998 180274 106998 4 u_riscv_top.dcache_mem_addr1\[4\]
+port 2277 nsew
+rlabel metal2 s 176226 106386 176226 106386 4 u_riscv_top.dcache_mem_addr1\[5\]
+port 2278 nsew
+rlabel metal3 s 166903 39638 166903 39638 4 u_riscv_top.dcache_mem_addr1\[6\]
+port 2279 nsew
+rlabel metal4 s 153254 25924 153254 25924 4 u_riscv_top.dcache_mem_addr1\[7\]
+port 2280 nsew
+rlabel metal4 s 153390 25788 153390 25788 4 u_riscv_top.dcache_mem_addr1\[8\]
+port 2281 nsew
+rlabel metal3 s 28793 34340 28793 34340 4 u_riscv_top.dcache_mem_clk0
+port 2282 nsew
+rlabel metal4 s 160870 109526 160870 109526 4 u_riscv_top.dcache_mem_clk1
+port 2283 nsew
+rlabel metal2 s 135930 124610 135930 124610 4 u_riscv_top.dcache_mem_csb0
+port 2284 nsew
+rlabel metal2 s 178618 138040 178618 138040 4 u_riscv_top.dcache_mem_csb1
+port 2285 nsew
+rlabel metal4 s 53158 25788 53158 25788 4 u_riscv_top.dcache_mem_din0\[0\]
+port 2286 nsew
+rlabel metal4 s 64582 25788 64582 25788 4 u_riscv_top.dcache_mem_din0\[10\]
+port 2287 nsew
+rlabel metal2 s 176502 80104 176502 80104 4 u_riscv_top.dcache_mem_din0\[11\]
+port 2288 nsew
+rlabel metal2 s 79350 23834 79350 23834 4 u_riscv_top.dcache_mem_din0\[12\]
+port 2289 nsew
+rlabel metal2 s 178894 81821 178894 81821 4 u_riscv_top.dcache_mem_din0\[13\]
+port 2290 nsew
+rlabel metal4 s 69478 25788 69478 25788 4 u_riscv_top.dcache_mem_din0\[14\]
+port 2291 nsew
+rlabel metal2 s 174938 81566 174938 81566 4 u_riscv_top.dcache_mem_din0\[15\]
+port 2292 nsew
+rlabel metal4 s 71790 25788 71790 25788 4 u_riscv_top.dcache_mem_din0\[16\]
+port 2293 nsew
+rlabel metal2 s 173374 80716 173374 80716 4 u_riscv_top.dcache_mem_din0\[17\]
+port 2294 nsew
+rlabel metal2 s 173282 81362 173282 81362 4 u_riscv_top.dcache_mem_din0\[18\]
+port 2295 nsew
+rlabel metal4 s 75326 25788 75326 25788 4 u_riscv_top.dcache_mem_din0\[19\]
+port 2296 nsew
+rlabel metal2 s 175030 78625 175030 78625 4 u_riscv_top.dcache_mem_din0\[1\]
+port 2297 nsew
+rlabel metal4 s 76414 25788 76414 25788 4 u_riscv_top.dcache_mem_din0\[20\]
+port 2298 nsew
+rlabel metal4 s 77638 25856 77638 25856 4 u_riscv_top.dcache_mem_din0\[21\]
+port 2299 nsew
+rlabel metal4 s 78726 25856 78726 25856 4 u_riscv_top.dcache_mem_din0\[22\]
+port 2300 nsew
+rlabel metal4 s 79814 25924 79814 25924 4 u_riscv_top.dcache_mem_din0\[23\]
+port 2301 nsew
+rlabel metal4 s 81174 25924 81174 25924 4 u_riscv_top.dcache_mem_din0\[24\]
+port 2302 nsew
+rlabel metal4 s 82262 25856 82262 25856 4 u_riscv_top.dcache_mem_din0\[25\]
+port 2303 nsew
+rlabel metal4 s 83350 25856 83350 25856 4 u_riscv_top.dcache_mem_din0\[26\]
+port 2304 nsew
+rlabel metal4 s 84438 25856 84438 25856 4 u_riscv_top.dcache_mem_din0\[27\]
+port 2305 nsew
+rlabel metal4 s 85798 25788 85798 25788 4 u_riscv_top.dcache_mem_din0\[28\]
+port 2306 nsew
+rlabel metal4 s 87022 25788 87022 25788 4 u_riscv_top.dcache_mem_din0\[29\]
+port 2307 nsew
+rlabel metal4 s 55470 25788 55470 25788 4 u_riscv_top.dcache_mem_din0\[2\]
+port 2308 nsew
+rlabel metal2 s 171902 82008 171902 82008 4 u_riscv_top.dcache_mem_din0\[30\]
+port 2309 nsew
+rlabel metal2 s 174754 82076 174754 82076 4 u_riscv_top.dcache_mem_din0\[31\]
+port 2310 nsew
+rlabel metal4 s 56558 25788 56558 25788 4 u_riscv_top.dcache_mem_din0\[3\]
+port 2311 nsew
+rlabel metal4 s 57646 25788 57646 25788 4 u_riscv_top.dcache_mem_din0\[4\]
+port 2312 nsew
+rlabel metal4 s 58734 25788 58734 25788 4 u_riscv_top.dcache_mem_din0\[5\]
+port 2313 nsew
+rlabel metal4 s 60094 25788 60094 25788 4 u_riscv_top.dcache_mem_din0\[6\]
+port 2314 nsew
+rlabel metal4 s 61318 25788 61318 25788 4 u_riscv_top.dcache_mem_din0\[7\]
+port 2315 nsew
+rlabel metal4 s 62406 25788 62406 25788 4 u_riscv_top.dcache_mem_din0\[8\]
+port 2316 nsew
+rlabel metal4 s 63494 25856 63494 25856 4 u_riscv_top.dcache_mem_din0\[9\]
+port 2317 nsew
+rlabel metal4 s 58326 25788 58326 25788 4 u_riscv_top.dcache_mem_dout0\[0\]
+port 2318 nsew
+rlabel metal4 s 83622 25788 83622 25788 4 u_riscv_top.dcache_mem_dout0\[10\]
+port 2319 nsew
+rlabel metal2 s 176318 89046 176318 89046 4 u_riscv_top.dcache_mem_dout0\[11\]
+port 2320 nsew
+rlabel metal4 s 88518 25788 88518 25788 4 u_riscv_top.dcache_mem_dout0\[12\]
+port 2321 nsew
+rlabel metal4 s 171948 87720 171948 87720 4 u_riscv_top.dcache_mem_dout0\[13\]
+port 2322 nsew
+rlabel metal4 s 93550 25788 93550 25788 4 u_riscv_top.dcache_mem_dout0\[14\]
+port 2323 nsew
+rlabel metal4 s 95998 25788 95998 25788 4 u_riscv_top.dcache_mem_dout0\[15\]
+port 2324 nsew
+rlabel metal4 s 98310 25788 98310 25788 4 u_riscv_top.dcache_mem_dout0\[16\]
+port 2325 nsew
+rlabel metal4 s 101030 25788 101030 25788 4 u_riscv_top.dcache_mem_dout0\[17\]
+port 2326 nsew
+rlabel metal4 s 103478 25788 103478 25788 4 u_riscv_top.dcache_mem_dout0\[18\]
+port 2327 nsew
+rlabel metal4 s 105926 25788 105926 25788 4 u_riscv_top.dcache_mem_dout0\[19\]
+port 2328 nsew
+rlabel metal4 s 60774 25788 60774 25788 4 u_riscv_top.dcache_mem_dout0\[1\]
+port 2329 nsew
+rlabel metal2 s 177330 88944 177330 88944 4 u_riscv_top.dcache_mem_dout0\[20\]
+port 2330 nsew
+rlabel metal4 s 110958 25788 110958 25788 4 u_riscv_top.dcache_mem_dout0\[21\]
+port 2331 nsew
+rlabel metal4 s 113542 25788 113542 25788 4 u_riscv_top.dcache_mem_dout0\[22\]
+port 2332 nsew
+rlabel metal4 s 115990 25788 115990 25788 4 u_riscv_top.dcache_mem_dout0\[23\]
+port 2333 nsew
+rlabel metal4 s 118574 25788 118574 25788 4 u_riscv_top.dcache_mem_dout0\[24\]
+port 2334 nsew
+rlabel metal4 s 121022 25788 121022 25788 4 u_riscv_top.dcache_mem_dout0\[25\]
+port 2335 nsew
+rlabel metal4 s 123470 25788 123470 25788 4 u_riscv_top.dcache_mem_dout0\[26\]
+port 2336 nsew
+rlabel metal2 s 176134 91630 176134 91630 4 u_riscv_top.dcache_mem_dout0\[27\]
+port 2337 nsew
+rlabel metal4 s 128502 25788 128502 25788 4 u_riscv_top.dcache_mem_dout0\[28\]
+port 2338 nsew
+rlabel metal2 s 178710 90168 178710 90168 4 u_riscv_top.dcache_mem_dout0\[29\]
+port 2339 nsew
+rlabel metal4 s 63630 25788 63630 25788 4 u_riscv_top.dcache_mem_dout0\[2\]
+port 2340 nsew
+rlabel metal4 s 133398 25788 133398 25788 4 u_riscv_top.dcache_mem_dout0\[30\]
+port 2341 nsew
+rlabel metal4 s 135982 25788 135982 25788 4 u_riscv_top.dcache_mem_dout0\[31\]
+port 2342 nsew
+rlabel metal4 s 66078 25788 66078 25788 4 u_riscv_top.dcache_mem_dout0\[3\]
+port 2343 nsew
+rlabel metal4 s 68526 25788 68526 25788 4 u_riscv_top.dcache_mem_dout0\[4\]
+port 2344 nsew
+rlabel metal4 s 172132 85612 172132 85612 4 u_riscv_top.dcache_mem_dout0\[5\]
+port 2345 nsew
+rlabel metal4 s 73558 25788 73558 25788 4 u_riscv_top.dcache_mem_dout0\[6\]
+port 2346 nsew
+rlabel metal4 s 76006 25856 76006 25856 4 u_riscv_top.dcache_mem_dout0\[7\]
+port 2347 nsew
+rlabel metal4 s 78318 25788 78318 25788 4 u_riscv_top.dcache_mem_dout0\[8\]
+port 2348 nsew
+rlabel metal4 s 81038 25788 81038 25788 4 u_riscv_top.dcache_mem_dout0\[9\]
+port 2349 nsew
+rlabel metal4 s 58734 109526 58734 109526 4 u_riscv_top.dcache_mem_dout1\[0\]
+port 2350 nsew
+rlabel metal4 s 83622 109526 83622 109526 4 u_riscv_top.dcache_mem_dout1\[10\]
+port 2351 nsew
+rlabel metal4 s 86206 109526 86206 109526 4 u_riscv_top.dcache_mem_dout1\[11\]
+port 2352 nsew
+rlabel metal1 s 130364 116722 130364 116722 4 u_riscv_top.dcache_mem_dout1\[12\]
+port 2353 nsew
+rlabel metal2 s 180366 152966 180366 152966 4 u_riscv_top.dcache_mem_dout1\[13\]
+port 2354 nsew
+rlabel metal4 s 93686 109526 93686 109526 4 u_riscv_top.dcache_mem_dout1\[14\]
+port 2355 nsew
+rlabel metal4 s 96134 109526 96134 109526 4 u_riscv_top.dcache_mem_dout1\[15\]
+port 2356 nsew
+rlabel metal4 s 98582 109526 98582 109526 4 u_riscv_top.dcache_mem_dout1\[16\]
+port 2357 nsew
+rlabel metal4 s 101030 109526 101030 109526 4 u_riscv_top.dcache_mem_dout1\[17\]
+port 2358 nsew
+rlabel metal2 s 172454 152252 172454 152252 4 u_riscv_top.dcache_mem_dout1\[18\]
+port 2359 nsew
+rlabel metal2 s 172086 149430 172086 149430 4 u_riscv_top.dcache_mem_dout1\[19\]
+port 2360 nsew
+rlabel metal4 s 61046 109526 61046 109526 4 u_riscv_top.dcache_mem_dout1\[1\]
+port 2361 nsew
+rlabel metal1 s 139932 116790 139932 116790 4 u_riscv_top.dcache_mem_dout1\[20\]
+port 2362 nsew
+rlabel metal2 s 177790 154326 177790 154326 4 u_riscv_top.dcache_mem_dout1\[21\]
+port 2363 nsew
+rlabel metal4 s 113542 109526 113542 109526 4 u_riscv_top.dcache_mem_dout1\[22\]
+port 2364 nsew
+rlabel metal4 s 115990 109526 115990 109526 4 u_riscv_top.dcache_mem_dout1\[23\]
+port 2365 nsew
+rlabel metal4 s 118438 109526 118438 109526 4 u_riscv_top.dcache_mem_dout1\[24\]
+port 2366 nsew
+rlabel metal4 s 121022 109526 121022 109526 4 u_riscv_top.dcache_mem_dout1\[25\]
+port 2367 nsew
+rlabel metal4 s 123606 109526 123606 109526 4 u_riscv_top.dcache_mem_dout1\[26\]
+port 2368 nsew
+rlabel metal2 s 172362 152286 172362 152286 4 u_riscv_top.dcache_mem_dout1\[27\]
+port 2369 nsew
+rlabel metal4 s 128502 109526 128502 109526 4 u_riscv_top.dcache_mem_dout1\[28\]
+port 2370 nsew
+rlabel metal2 s 172178 153000 172178 153000 4 u_riscv_top.dcache_mem_dout1\[29\]
+port 2371 nsew
+rlabel metal4 s 63494 109526 63494 109526 4 u_riscv_top.dcache_mem_dout1\[2\]
+port 2372 nsew
+rlabel metal4 s 133398 109526 133398 109526 4 u_riscv_top.dcache_mem_dout1\[30\]
+port 2373 nsew
+rlabel metal4 s 136118 109526 136118 109526 4 u_riscv_top.dcache_mem_dout1\[31\]
+port 2374 nsew
+rlabel metal2 s 171626 148750 171626 148750 4 u_riscv_top.dcache_mem_dout1\[3\]
+port 2375 nsew
+rlabel metal4 s 68526 109526 68526 109526 4 u_riscv_top.dcache_mem_dout1\[4\]
+port 2376 nsew
+rlabel metal2 s 177698 149464 177698 149464 4 u_riscv_top.dcache_mem_dout1\[5\]
+port 2377 nsew
+rlabel metal2 s 172914 136204 172914 136204 4 u_riscv_top.dcache_mem_dout1\[6\]
+port 2378 nsew
+rlabel metal4 s 76142 109526 76142 109526 4 u_riscv_top.dcache_mem_dout1\[7\]
+port 2379 nsew
+rlabel metal4 s 78590 109526 78590 109526 4 u_riscv_top.dcache_mem_dout1\[8\]
+port 2380 nsew
+rlabel metal4 s 81174 109526 81174 109526 4 u_riscv_top.dcache_mem_dout1\[9\]
+port 2381 nsew
+rlabel metal3 s 29437 35972 29437 35972 4 u_riscv_top.dcache_mem_web0
+port 2382 nsew
+rlabel metal4 s 48262 25788 48262 25788 4 u_riscv_top.dcache_mem_wmask0\[0\]
+port 2383 nsew
+rlabel metal4 s 49622 25788 49622 25788 4 u_riscv_top.dcache_mem_wmask0\[1\]
+port 2384 nsew
+rlabel metal4 s 172316 79492 172316 79492 4 u_riscv_top.dcache_mem_wmask0\[2\]
+port 2385 nsew
+rlabel metal4 s 51798 25788 51798 25788 4 u_riscv_top.dcache_mem_wmask0\[3\]
+port 2386 nsew
+rlabel metal2 s 190670 120302 190670 120302 4 u_riscv_top.icache_mem_addr0\[0\]
+port 2387 nsew
+rlabel metal2 s 190854 120540 190854 120540 4 u_riscv_top.icache_mem_addr0\[1\]
+port 2388 nsew
+rlabel metal2 s 191038 120506 191038 120506 4 u_riscv_top.icache_mem_addr0\[2\]
+port 2389 nsew
+rlabel metal2 s 191222 120472 191222 120472 4 u_riscv_top.icache_mem_addr0\[3\]
+port 2390 nsew
+rlabel metal2 s 191406 120948 191406 120948 4 u_riscv_top.icache_mem_addr0\[4\]
+port 2391 nsew
+rlabel metal2 s 191590 128802 191590 128802 4 u_riscv_top.icache_mem_addr0\[5\]
+port 2392 nsew
+rlabel metal2 s 191774 129074 191774 129074 4 u_riscv_top.icache_mem_addr0\[6\]
+port 2393 nsew
+rlabel metal2 s 191958 126456 191958 126456 4 u_riscv_top.icache_mem_addr0\[7\]
+port 2394 nsew
+rlabel metal2 s 192142 129108 192142 129108 4 u_riscv_top.icache_mem_addr0\[8\]
+port 2395 nsew
+rlabel metal2 s 213762 128156 213762 128156 4 u_riscv_top.icache_mem_addr1\[0\]
+port 2396 nsew
+rlabel metal2 s 215234 125222 215234 125222 4 u_riscv_top.icache_mem_addr1\[1\]
+port 2397 nsew
+rlabel metal3 s 326914 45350 326914 45350 4 u_riscv_top.icache_mem_addr1\[2\]
+port 2398 nsew
+rlabel metal3 s 326945 43724 326945 43724 4 u_riscv_top.icache_mem_addr1\[3\]
+port 2399 nsew
+rlabel metal3 s 326868 42358 326868 42358 4 u_riscv_top.icache_mem_addr1\[4\]
+port 2400 nsew
+rlabel metal3 s 327681 40868 327681 40868 4 u_riscv_top.icache_mem_addr1\[5\]
+port 2401 nsew
+rlabel metal3 s 327635 39644 327635 39644 4 u_riscv_top.icache_mem_addr1\[6\]
+port 2402 nsew
+rlabel metal4 s 313254 25856 313254 25856 4 u_riscv_top.icache_mem_addr1\[7\]
+port 2403 nsew
+rlabel metal4 s 313390 25788 313390 25788 4 u_riscv_top.icache_mem_addr1\[8\]
+port 2404 nsew
+rlabel metal3 s 189735 34334 189735 34334 4 u_riscv_top.icache_mem_clk0
+port 2405 nsew
+rlabel metal2 s 210151 129812 210151 129812 4 u_riscv_top.icache_mem_clk1
+port 2406 nsew
+rlabel metal1 s 189060 63546 189060 63546 4 u_riscv_top.icache_mem_csb0
+port 2407 nsew
+rlabel metal1 s 214590 127126 214590 127126 4 u_riscv_top.icache_mem_csb1
+port 2408 nsew
+rlabel metal4 s 213158 25788 213158 25788 4 u_riscv_top.icache_mem_din0\[0\]
+port 2409 nsew
+rlabel metal2 s 194902 120778 194902 120778 4 u_riscv_top.icache_mem_din0\[10\]
+port 2410 nsew
+rlabel metal2 s 180366 67116 180366 67116 4 u_riscv_top.icache_mem_din0\[11\]
+port 2411 nsew
+rlabel metal2 s 195270 120744 195270 120744 4 u_riscv_top.icache_mem_din0\[12\]
+port 2412 nsew
+rlabel metal2 s 195454 120812 195454 120812 4 u_riscv_top.icache_mem_din0\[13\]
+port 2413 nsew
+rlabel metal4 s 229478 25788 229478 25788 4 u_riscv_top.icache_mem_din0\[14\]
+port 2414 nsew
+rlabel metal4 s 230702 25788 230702 25788 4 u_riscv_top.icache_mem_din0\[15\]
+port 2415 nsew
+rlabel metal4 s 231790 25788 231790 25788 4 u_riscv_top.icache_mem_din0\[16\]
+port 2416 nsew
+rlabel metal4 s 232878 25788 232878 25788 4 u_riscv_top.icache_mem_din0\[17\]
+port 2417 nsew
+rlabel metal4 s 233966 25788 233966 25788 4 u_riscv_top.icache_mem_din0\[18\]
+port 2418 nsew
+rlabel metal4 s 235326 25788 235326 25788 4 u_riscv_top.icache_mem_din0\[19\]
+port 2419 nsew
+rlabel metal4 s 214246 25788 214246 25788 4 u_riscv_top.icache_mem_din0\[1\]
+port 2420 nsew
+rlabel metal4 s 236414 25788 236414 25788 4 u_riscv_top.icache_mem_din0\[20\]
+port 2421 nsew
+rlabel metal4 s 237638 25788 237638 25788 4 u_riscv_top.icache_mem_din0\[21\]
+port 2422 nsew
+rlabel metal4 s 238726 25788 238726 25788 4 u_riscv_top.icache_mem_din0\[22\]
+port 2423 nsew
+rlabel metal2 s 172362 69666 172362 69666 4 u_riscv_top.icache_mem_din0\[23\]
+port 2424 nsew
+rlabel metal2 s 173742 69564 173742 69564 4 u_riscv_top.icache_mem_din0\[24\]
+port 2425 nsew
+rlabel metal2 s 175766 69394 175766 69394 4 u_riscv_top.icache_mem_din0\[25\]
+port 2426 nsew
+rlabel metal2 s 172178 69360 172178 69360 4 u_riscv_top.icache_mem_din0\[26\]
+port 2427 nsew
+rlabel metal2 s 173650 69496 173650 69496 4 u_riscv_top.icache_mem_din0\[27\]
+port 2428 nsew
+rlabel metal2 s 179998 69411 179998 69411 4 u_riscv_top.icache_mem_din0\[28\]
+port 2429 nsew
+rlabel metal2 s 198398 122053 198398 122053 4 u_riscv_top.icache_mem_din0\[29\]
+port 2430 nsew
+rlabel metal4 s 215470 25924 215470 25924 4 u_riscv_top.icache_mem_din0\[2\]
+port 2431 nsew
+rlabel metal2 s 175122 69632 175122 69632 4 u_riscv_top.icache_mem_din0\[30\]
+port 2432 nsew
+rlabel metal4 s 249198 25788 249198 25788 4 u_riscv_top.icache_mem_din0\[31\]
+port 2433 nsew
+rlabel metal4 s 216558 25924 216558 25924 4 u_riscv_top.icache_mem_din0\[3\]
+port 2434 nsew
+rlabel metal4 s 217646 25924 217646 25924 4 u_riscv_top.icache_mem_din0\[4\]
+port 2435 nsew
+rlabel metal4 s 218734 25924 218734 25924 4 u_riscv_top.icache_mem_din0\[5\]
+port 2436 nsew
+rlabel metal2 s 172454 69292 172454 69292 4 u_riscv_top.icache_mem_din0\[6\]
+port 2437 nsew
+rlabel metal2 s 177974 69088 177974 69088 4 u_riscv_top.icache_mem_din0\[7\]
+port 2438 nsew
+rlabel metal2 s 175858 68986 175858 68986 4 u_riscv_top.icache_mem_din0\[8\]
+port 2439 nsew
+rlabel metal2 s 178986 67048 178986 67048 4 u_riscv_top.icache_mem_din0\[9\]
+port 2440 nsew
+rlabel metal4 s 218734 109526 218734 109526 4 u_riscv_top.icache_mem_dout1\[0\]
+port 2441 nsew
+rlabel metal1 s 232438 119510 232438 119510 4 u_riscv_top.icache_mem_dout1\[10\]
+port 2442 nsew
+rlabel metal1 s 233910 122230 233910 122230 4 u_riscv_top.icache_mem_dout1\[11\]
+port 2443 nsew
+rlabel metal4 s 248518 109526 248518 109526 4 u_riscv_top.icache_mem_dout1\[12\]
+port 2444 nsew
+rlabel metal4 s 250966 109526 250966 109526 4 u_riscv_top.icache_mem_dout1\[13\]
+port 2445 nsew
+rlabel metal4 s 253686 109526 253686 109526 4 u_riscv_top.icache_mem_dout1\[14\]
+port 2446 nsew
+rlabel metal4 s 256134 109526 256134 109526 4 u_riscv_top.icache_mem_dout1\[15\]
+port 2447 nsew
+rlabel metal1 s 240580 120870 240580 120870 4 u_riscv_top.icache_mem_dout1\[16\]
+port 2448 nsew
+rlabel metal1 s 242052 118014 242052 118014 4 u_riscv_top.icache_mem_dout1\[17\]
+port 2449 nsew
+rlabel metal1 s 243524 113934 243524 113934 4 u_riscv_top.icache_mem_dout1\[18\]
+port 2450 nsew
+rlabel metal1 s 244306 119442 244306 119442 4 u_riscv_top.icache_mem_dout1\[19\]
+port 2451 nsew
+rlabel metal4 s 221046 109526 221046 109526 4 u_riscv_top.icache_mem_dout1\[1\]
+port 2452 nsew
+rlabel metal4 s 268646 109526 268646 109526 4 u_riscv_top.icache_mem_dout1\[20\]
+port 2453 nsew
+rlabel metal4 s 271094 109526 271094 109526 4 u_riscv_top.icache_mem_dout1\[21\]
+port 2454 nsew
+rlabel metal4 s 273542 109526 273542 109526 4 u_riscv_top.icache_mem_dout1\[22\]
+port 2455 nsew
+rlabel metal4 s 275990 109526 275990 109526 4 u_riscv_top.icache_mem_dout1\[23\]
+port 2456 nsew
+rlabel metal2 s 224526 127476 224526 127476 4 u_riscv_top.icache_mem_dout1\[24\]
+port 2457 nsew
+rlabel metal2 s 224710 129074 224710 129074 4 u_riscv_top.icache_mem_dout1\[25\]
+port 2458 nsew
+rlabel metal1 s 253920 120802 253920 120802 4 u_riscv_top.icache_mem_dout1\[26\]
+port 2459 nsew
+rlabel metal2 s 225078 129040 225078 129040 4 u_riscv_top.icache_mem_dout1\[27\]
+port 2460 nsew
+rlabel metal2 s 249090 120428 249090 120428 4 u_riscv_top.icache_mem_dout1\[28\]
+port 2461 nsew
+rlabel metal4 s 291086 109526 291086 109526 4 u_riscv_top.icache_mem_dout1\[29\]
+port 2462 nsew
+rlabel metal4 s 223494 109526 223494 109526 4 u_riscv_top.icache_mem_dout1\[2\]
+port 2463 nsew
+rlabel metal2 s 250470 120462 250470 120462 4 u_riscv_top.icache_mem_dout1\[30\]
+port 2464 nsew
+rlabel metal4 s 296118 109526 296118 109526 4 u_riscv_top.icache_mem_dout1\[31\]
+port 2465 nsew
+rlabel metal4 s 226214 109526 226214 109526 4 u_riscv_top.icache_mem_dout1\[3\]
+port 2466 nsew
+rlabel metal4 s 228526 109526 228526 109526 4 u_riscv_top.icache_mem_dout1\[4\]
+port 2467 nsew
+rlabel metal4 s 231110 109526 231110 109526 4 u_riscv_top.icache_mem_dout1\[5\]
+port 2468 nsew
+rlabel metal4 s 233558 109526 233558 109526 4 u_riscv_top.icache_mem_dout1\[6\]
+port 2469 nsew
+rlabel metal4 s 236142 109526 236142 109526 4 u_riscv_top.icache_mem_dout1\[7\]
+port 2470 nsew
+rlabel metal4 s 238590 109526 238590 109526 4 u_riscv_top.icache_mem_dout1\[8\]
+port 2471 nsew
+rlabel metal2 s 221766 129108 221766 129108 4 u_riscv_top.icache_mem_dout1\[9\]
+port 2472 nsew
+rlabel metal2 s 190486 128768 190486 128768 4 u_riscv_top.icache_mem_web0
+port 2473 nsew
+rlabel metal2 s 192326 122070 192326 122070 4 u_riscv_top.icache_mem_wmask0\[0\]
+port 2474 nsew
+rlabel metal2 s 192510 122172 192510 122172 4 u_riscv_top.icache_mem_wmask0\[1\]
+port 2475 nsew
+rlabel metal4 s 210574 25788 210574 25788 4 u_riscv_top.icache_mem_wmask0\[2\]
+port 2476 nsew
+rlabel metal4 s 211798 25788 211798 25788 4 u_riscv_top.icache_mem_wmask0\[3\]
+port 2477 nsew
+rlabel metal2 s 152858 681928 152858 681928 4 u_riscv_top.irq_lines\[0\]
+port 2478 nsew
+rlabel metal2 s 352682 570078 352682 570078 4 u_riscv_top.irq_lines\[10\]
+port 2479 nsew
+rlabel metal2 s 348634 570146 348634 570146 4 u_riscv_top.irq_lines\[11\]
+port 2480 nsew
+rlabel metal2 s 351210 570146 351210 570146 4 u_riscv_top.irq_lines\[12\]
+port 2481 nsew
+rlabel metal1 s 366114 455362 366114 455362 4 u_riscv_top.irq_lines\[13\]
+port 2482 nsew
+rlabel metal2 s 235290 575858 235290 575858 4 u_riscv_top.irq_lines\[14\]
+port 2483 nsew
+rlabel metal2 s 367218 454971 367218 454971 4 u_riscv_top.irq_lines\[15\]
+port 2484 nsew
+rlabel metal2 s 232530 575280 232530 575280 4 u_riscv_top.irq_lines\[16\]
+port 2485 nsew
+rlabel metal3 s 368882 454172 368882 454172 4 u_riscv_top.irq_lines\[17\]
+port 2486 nsew
+rlabel metal2 s 348450 568854 348450 568854 4 u_riscv_top.irq_lines\[18\]
+port 2487 nsew
+rlabel metal3 s 369112 453628 369112 453628 4 u_riscv_top.irq_lines\[19\]
+port 2488 nsew
+rlabel metal2 s 152674 681894 152674 681894 4 u_riscv_top.irq_lines\[1\]
+port 2489 nsew
+rlabel metal3 s 369204 453356 369204 453356 4 u_riscv_top.irq_lines\[20\]
+port 2490 nsew
+rlabel metal2 s 367310 453509 367310 453509 4 u_riscv_top.irq_lines\[21\]
+port 2491 nsew
+rlabel metal3 s 368928 452812 368928 452812 4 u_riscv_top.irq_lines\[22\]
+port 2492 nsew
+rlabel metal3 s 367218 452523 367218 452523 4 u_riscv_top.irq_lines\[23\]
+port 2493 nsew
+rlabel metal2 s 367126 452353 367126 452353 4 u_riscv_top.irq_lines\[24\]
+port 2494 nsew
+rlabel metal2 s 352590 568718 352590 568718 4 u_riscv_top.irq_lines\[25\]
+port 2495 nsew
+rlabel metal3 s 369158 451724 369158 451724 4 u_riscv_top.irq_lines\[26\]
+port 2496 nsew
+rlabel metal3 s 369066 451452 369066 451452 4 u_riscv_top.irq_lines\[27\]
+port 2497 nsew
+rlabel metal2 s 156262 679694 156262 679694 4 u_riscv_top.irq_lines\[28\]
+port 2498 nsew
+rlabel metal3 s 368905 450908 368905 450908 4 u_riscv_top.irq_lines\[29\]
+port 2499 nsew
+rlabel metal2 s 152490 682472 152490 682472 4 u_riscv_top.irq_lines\[2\]
+port 2500 nsew
+rlabel metal3 s 368813 450636 368813 450636 4 u_riscv_top.irq_lines\[30\]
+port 2501 nsew
+rlabel metal3 s 369181 450364 369181 450364 4 u_riscv_top.irq_lines\[31\]
+port 2502 nsew
+rlabel metal2 s 152306 682438 152306 682438 4 u_riscv_top.irq_lines\[3\]
+port 2503 nsew
+rlabel metal2 s 152122 682608 152122 682608 4 u_riscv_top.irq_lines\[4\]
+port 2504 nsew
+rlabel metal2 s 151938 681180 151938 681180 4 u_riscv_top.irq_lines\[5\]
+port 2505 nsew
+rlabel metal2 s 349830 571574 349830 571574 4 u_riscv_top.irq_lines\[6\]
+port 2506 nsew
+rlabel metal2 s 367310 457419 367310 457419 4 u_riscv_top.irq_lines\[7\]
+port 2507 nsew
+rlabel metal2 s 367218 456671 367218 456671 4 u_riscv_top.irq_lines\[8\]
+port 2508 nsew
+rlabel metal2 s 233910 575892 233910 575892 4 u_riscv_top.irq_lines\[9\]
+port 2509 nsew
+rlabel metal2 s 153410 680160 153410 680160 4 u_riscv_top.pwrup_rst_n
+port 2510 nsew
+rlabel metal2 s 153226 682914 153226 682914 4 u_riscv_top.rtc_clk
+port 2511 nsew
+rlabel metal2 s 153042 680908 153042 680908 4 u_riscv_top.soft_irq
+port 2512 nsew
+rlabel metal2 s 140806 280568 140806 280568 4 u_riscv_top.sram0_addr0\[0\]
+port 2513 nsew
+rlabel metal2 s 140898 280466 140898 280466 4 u_riscv_top.sram0_addr0\[1\]
+port 2514 nsew
+rlabel metal3 s 28359 178228 28359 178228 4 u_riscv_top.sram0_addr0\[2\]
+port 2515 nsew
+rlabel metal3 s 28313 179996 28313 179996 4 u_riscv_top.sram0_addr0\[3\]
+port 2516 nsew
+rlabel metal1 s 76866 235314 76866 235314 4 u_riscv_top.sram0_addr0\[4\]
+port 2517 nsew
+rlabel metal1 s 76774 235382 76774 235382 4 u_riscv_top.sram0_addr0\[5\]
+port 2518 nsew
+rlabel metal1 s 77510 235246 77510 235246 4 u_riscv_top.sram0_addr0\[6\]
+port 2519 nsew
+rlabel metal1 s 77602 236810 77602 236810 4 u_riscv_top.sram0_addr0\[7\]
+port 2520 nsew
+rlabel metal2 s 134550 258536 134550 258536 4 u_riscv_top.sram0_addr0\[8\]
+port 2521 nsew
+rlabel metal1 s 147338 235790 147338 235790 4 u_riscv_top.sram0_addr1\[0\]
+port 2522 nsew
+rlabel metal1 s 146694 235858 146694 235858 4 u_riscv_top.sram0_addr1\[1\]
+port 2523 nsew
+rlabel metal1 s 157366 233886 157366 233886 4 u_riscv_top.sram0_addr1\[2\]
+port 2524 nsew
+rlabel metal1 s 157550 235314 157550 235314 4 u_riscv_top.sram0_addr1\[3\]
+port 2525 nsew
+rlabel metal1 s 157734 234022 157734 234022 4 u_riscv_top.sram0_addr1\[4\]
+port 2526 nsew
+rlabel metal1 s 157550 233954 157550 233954 4 u_riscv_top.sram0_addr1\[5\]
+port 2527 nsew
+rlabel metal1 s 157642 234090 157642 234090 4 u_riscv_top.sram0_addr1\[6\]
+port 2528 nsew
+rlabel metal4 s 153254 149804 153254 149804 4 u_riscv_top.sram0_addr1\[7\]
+port 2529 nsew
+rlabel metal2 s 141358 268736 141358 268736 4 u_riscv_top.sram0_addr1\[8\]
+port 2530 nsew
+rlabel metal3 s 28451 158372 28451 158372 4 u_riscv_top.sram0_clk0
+port 2531 nsew
+rlabel metal3 s 160126 235909 160126 235909 4 u_riscv_top.sram0_clk1
+port 2532 nsew
+rlabel metal3 s 28405 158100 28405 158100 4 u_riscv_top.sram0_csb0
+port 2533 nsew
+rlabel metal3 s 166903 229190 166903 229190 4 u_riscv_top.sram0_csb1
+port 2534 nsew
+rlabel metal4 s 141220 285668 141220 285668 4 u_riscv_top.sram0_din0\[0\]
+port 2535 nsew
+rlabel metal3 s 146725 290292 146725 290292 4 u_riscv_top.sram0_din0\[10\]
+port 2536 nsew
+rlabel metal4 s 146901 290020 146901 290020 4 u_riscv_top.sram0_din0\[11\]
+port 2537 nsew
+rlabel metal3 s 146081 289748 146081 289748 4 u_riscv_top.sram0_din0\[12\]
+port 2538 nsew
+rlabel metal3 s 146173 289476 146173 289476 4 u_riscv_top.sram0_din0\[13\]
+port 2539 nsew
+rlabel metal3 s 146656 289204 146656 289204 4 u_riscv_top.sram0_din0\[14\]
+port 2540 nsew
+rlabel metal2 s 141910 282081 141910 282081 4 u_riscv_top.sram0_din0\[15\]
+port 2541 nsew
+rlabel metal2 s 141818 282030 141818 282030 4 u_riscv_top.sram0_din0\[16\]
+port 2542 nsew
+rlabel metal3 s 145161 288388 145161 288388 4 u_riscv_top.sram0_din0\[17\]
+port 2543 nsew
+rlabel metal2 s 142002 281180 142002 281180 4 u_riscv_top.sram0_din0\[18\]
+port 2544 nsew
+rlabel metal3 s 145230 287844 145230 287844 4 u_riscv_top.sram0_din0\[19\]
+port 2545 nsew
+rlabel metal4 s 141036 285736 141036 285736 4 u_riscv_top.sram0_din0\[1\]
+port 2546 nsew
+rlabel metal3 s 145092 287572 145092 287572 4 u_riscv_top.sram0_din0\[20\]
+port 2547 nsew
+rlabel metal2 s 141726 281384 141726 281384 4 u_riscv_top.sram0_din0\[21\]
+port 2548 nsew
+rlabel metal3 s 145046 287028 145046 287028 4 u_riscv_top.sram0_din0\[22\]
+port 2549 nsew
+rlabel metal2 s 146970 275132 146970 275132 4 u_riscv_top.sram0_din0\[23\]
+port 2550 nsew
+rlabel metal4 s 81259 147628 81259 147628 4 u_riscv_top.sram0_din0\[24\]
+port 2551 nsew
+rlabel metal3 s 160425 276692 160425 276692 4 u_riscv_top.sram0_din0\[25\]
+port 2552 nsew
+rlabel metal4 s 83467 147628 83467 147628 4 u_riscv_top.sram0_din0\[26\]
+port 2553 nsew
+rlabel metal3 s 145460 285668 145460 285668 4 u_riscv_top.sram0_din0\[27\]
+port 2554 nsew
+rlabel metal2 s 144808 280092 144808 280092 4 u_riscv_top.sram0_din0\[28\]
+port 2555 nsew
+rlabel metal4 s 87147 147628 87147 147628 4 u_riscv_top.sram0_din0\[29\]
+port 2556 nsew
+rlabel metal2 s 141450 284648 141450 284648 4 u_riscv_top.sram0_din0\[2\]
+port 2557 nsew
+rlabel metal1 s 143566 284342 143566 284342 4 u_riscv_top.sram0_din0\[30\]
+port 2558 nsew
+rlabel metal4 s 89171 147628 89171 147628 4 u_riscv_top.sram0_din0\[31\]
+port 2559 nsew
+rlabel metal2 s 139242 284818 139242 284818 4 u_riscv_top.sram0_din0\[3\]
+port 2560 nsew
+rlabel metal2 s 138966 285022 138966 285022 4 u_riscv_top.sram0_din0\[4\]
+port 2561 nsew
+rlabel metal2 s 139058 284784 139058 284784 4 u_riscv_top.sram0_din0\[5\]
+port 2562 nsew
+rlabel metal2 s 139150 284920 139150 284920 4 u_riscv_top.sram0_din0\[6\]
+port 2563 nsew
+rlabel metal3 s 61295 147628 61295 147628 4 u_riscv_top.sram0_din0\[7\]
+port 2564 nsew
+rlabel metal2 s 138598 284444 138598 284444 4 u_riscv_top.sram0_din0\[8\]
+port 2565 nsew
+rlabel metal3 s 145805 290564 145805 290564 4 u_riscv_top.sram0_din0\[9\]
+port 2566 nsew
+rlabel metal2 s 138874 289646 138874 289646 4 u_riscv_top.sram0_dout0\[0\]
+port 2567 nsew
+rlabel metal2 s 143750 274928 143750 274928 4 u_riscv_top.sram0_dout0\[10\]
+port 2568 nsew
+rlabel metal1 s 144164 283866 144164 283866 4 u_riscv_top.sram0_dout0\[11\]
+port 2569 nsew
+rlabel metal4 s 88619 147628 88619 147628 4 u_riscv_top.sram0_dout0\[12\]
+port 2570 nsew
+rlabel metal2 s 141266 283288 141266 283288 4 u_riscv_top.sram0_dout0\[13\]
+port 2571 nsew
+rlabel metal1 s 145360 272646 145360 272646 4 u_riscv_top.sram0_dout0\[14\]
+port 2572 nsew
+rlabel metal4 s 95998 149872 95998 149872 4 u_riscv_top.sram0_dout0\[15\]
+port 2573 nsew
+rlabel metal4 s 98310 149940 98310 149940 4 u_riscv_top.sram0_dout0\[16\]
+port 2574 nsew
+rlabel metal4 s 101030 149872 101030 149872 4 u_riscv_top.sram0_dout0\[17\]
+port 2575 nsew
+rlabel metal4 s 103478 149872 103478 149872 4 u_riscv_top.sram0_dout0\[18\]
+port 2576 nsew
+rlabel metal2 s 140254 282914 140254 282914 4 u_riscv_top.sram0_dout0\[19\]
+port 2577 nsew
+rlabel metal4 s 60789 147628 60789 147628 4 u_riscv_top.sram0_dout0\[1\]
+port 2578 nsew
+rlabel metal1 s 144624 287062 144624 287062 4 u_riscv_top.sram0_dout0\[20\]
+port 2579 nsew
+rlabel metal2 s 139978 279242 139978 279242 4 u_riscv_top.sram0_dout0\[21\]
+port 2580 nsew
+rlabel metal4 s 113542 149668 113542 149668 4 u_riscv_top.sram0_dout0\[22\]
+port 2581 nsew
+rlabel metal4 s 115990 149668 115990 149668 4 u_riscv_top.sram0_dout0\[23\]
+port 2582 nsew
+rlabel metal4 s 118574 149668 118574 149668 4 u_riscv_top.sram0_dout0\[24\]
+port 2583 nsew
+rlabel metal4 s 121022 149668 121022 149668 4 u_riscv_top.sram0_dout0\[25\]
+port 2584 nsew
+rlabel metal3 s 146840 294644 146840 294644 4 u_riscv_top.sram0_dout0\[26\]
+port 2585 nsew
+rlabel metal2 s 139334 282030 139334 282030 4 u_riscv_top.sram0_dout0\[27\]
+port 2586 nsew
+rlabel metal3 s 145276 294100 145276 294100 4 u_riscv_top.sram0_dout0\[28\]
+port 2587 nsew
+rlabel metal1 s 143566 292638 143566 292638 4 u_riscv_top.sram0_dout0\[29\]
+port 2588 nsew
+rlabel metal4 s 135884 288320 135884 288320 4 u_riscv_top.sram0_dout0\[2\]
+port 2589 nsew
+rlabel metal4 s 133398 149668 133398 149668 4 u_riscv_top.sram0_dout0\[30\]
+port 2590 nsew
+rlabel metal4 s 135982 149668 135982 149668 4 u_riscv_top.sram0_dout0\[31\]
+port 2591 nsew
+rlabel metal4 s 144808 287040 144808 287040 4 u_riscv_top.sram0_dout0\[3\]
+port 2592 nsew
+rlabel metal3 s 145253 300628 145253 300628 4 u_riscv_top.sram0_dout0\[4\]
+port 2593 nsew
+rlabel metal2 s 133170 289102 133170 289102 4 u_riscv_top.sram0_dout0\[5\]
+port 2594 nsew
+rlabel metal2 s 136298 284801 136298 284801 4 u_riscv_top.sram0_dout0\[6\]
+port 2595 nsew
+rlabel metal3 s 76475 147628 76475 147628 4 u_riscv_top.sram0_dout0\[7\]
+port 2596 nsew
+rlabel metal2 s 136390 284750 136390 284750 4 u_riscv_top.sram0_dout0\[8\]
+port 2597 nsew
+rlabel metal4 s 81075 147084 81075 147084 4 u_riscv_top.sram0_dout0\[9\]
+port 2598 nsew
+rlabel metal3 s 59041 235212 59041 235212 4 u_riscv_top.sram0_dout1\[0\]
+port 2599 nsew
+rlabel metal3 s 83881 235892 83881 235892 4 u_riscv_top.sram0_dout1\[10\]
+port 2600 nsew
+rlabel metal2 s 135930 277168 135930 277168 4 u_riscv_top.sram0_dout1\[11\]
+port 2601 nsew
+rlabel metal3 s 89125 235892 89125 235892 4 u_riscv_top.sram0_dout1\[12\]
+port 2602 nsew
+rlabel metal2 s 136114 279276 136114 279276 4 u_riscv_top.sram0_dout1\[13\]
+port 2603 nsew
+rlabel metal4 s 93771 235212 93771 235212 4 u_riscv_top.sram0_dout1\[14\]
+port 2604 nsew
+rlabel metal3 s 96347 235892 96347 235892 4 u_riscv_top.sram0_dout1\[15\]
+port 2605 nsew
+rlabel metal3 s 98923 235212 98923 235212 4 u_riscv_top.sram0_dout1\[16\]
+port 2606 nsew
+rlabel metal3 s 101591 235892 101591 235892 4 u_riscv_top.sram0_dout1\[17\]
+port 2607 nsew
+rlabel metal3 s 104259 235892 104259 235892 4 u_riscv_top.sram0_dout1\[18\]
+port 2608 nsew
+rlabel metal3 s 106007 235212 106007 235212 4 u_riscv_top.sram0_dout1\[19\]
+port 2609 nsew
+rlabel metal3 s 61525 235892 61525 235892 4 u_riscv_top.sram0_dout1\[1\]
+port 2610 nsew
+rlabel metal2 s 137770 279276 137770 279276 4 u_riscv_top.sram0_dout1\[20\]
+port 2611 nsew
+rlabel metal2 s 137678 279276 137678 279276 4 u_riscv_top.sram0_dout1\[21\]
+port 2612 nsew
+rlabel metal3 s 114057 235212 114057 235212 4 u_riscv_top.sram0_dout1\[22\]
+port 2613 nsew
+rlabel metal3 s 116633 235892 116633 235892 4 u_riscv_top.sram0_dout1\[23\]
+port 2614 nsew
+rlabel metal3 s 118519 235212 118519 235212 4 u_riscv_top.sram0_dout1\[24\]
+port 2615 nsew
+rlabel metal3 s 121187 235892 121187 235892 4 u_riscv_top.sram0_dout1\[25\]
+port 2616 nsew
+rlabel metal3 s 123855 235892 123855 235892 4 u_riscv_top.sram0_dout1\[26\]
+port 2617 nsew
+rlabel metal3 s 126523 235212 126523 235212 4 u_riscv_top.sram0_dout1\[27\]
+port 2618 nsew
+rlabel metal2 s 137402 270572 137402 270572 4 u_riscv_top.sram0_dout1\[28\]
+port 2619 nsew
+rlabel metal2 s 133262 298656 133262 298656 4 u_riscv_top.sram0_dout1\[29\]
+port 2620 nsew
+rlabel metal3 s 64193 235892 64193 235892 4 u_riscv_top.sram0_dout1\[2\]
+port 2621 nsew
+rlabel metal1 s 135654 235858 135654 235858 4 u_riscv_top.sram0_dout1\[30\]
+port 2622 nsew
+rlabel metal3 s 136321 235892 136321 235892 4 u_riscv_top.sram0_dout1\[31\]
+port 2623 nsew
+rlabel metal2 s 137586 281962 137586 281962 4 u_riscv_top.sram0_dout1\[3\]
+port 2624 nsew
+rlabel metal3 s 68747 235892 68747 235892 4 u_riscv_top.sram0_dout1\[4\]
+port 2625 nsew
+rlabel metal3 s 71415 235892 71415 235892 4 u_riscv_top.sram0_dout1\[5\]
+port 2626 nsew
+rlabel metal3 s 73991 235212 73991 235212 4 u_riscv_top.sram0_dout1\[6\]
+port 2627 nsew
+rlabel metal2 s 77234 235637 77234 235637 4 u_riscv_top.sram0_dout1\[7\]
+port 2628 nsew
+rlabel metal4 s 78637 235212 78637 235212 4 u_riscv_top.sram0_dout1\[8\]
+port 2629 nsew
+rlabel metal2 s 81374 235807 81374 235807 4 u_riscv_top.sram0_dout1\[9\]
+port 2630 nsew
+rlabel metal3 s 28819 160004 28819 160004 4 u_riscv_top.sram0_web0
+port 2631 nsew
+rlabel metal2 s 24610 212007 24610 212007 4 u_riscv_top.sram0_wmask0\[0\]
+port 2632 nsew
+rlabel metal2 s 24702 212092 24702 212092 4 u_riscv_top.sram0_wmask0\[1\]
+port 2633 nsew
+rlabel metal2 s 24794 211208 24794 211208 4 u_riscv_top.sram0_wmask0\[2\]
+port 2634 nsew
+rlabel metal2 s 24518 211922 24518 211922 4 u_riscv_top.sram0_wmask0\[3\]
+port 2635 nsew
+rlabel metal3 s 351348 141644 351348 141644 4 u_riscv_top.wb_clk
+port 2636 nsew
+rlabel metal3 s 352720 221204 352720 221204 4 u_riscv_top.wb_dcache_ack_i
+port 2637 nsew
+rlabel metal3 s 352628 199444 352628 199444 4 u_riscv_top.wb_dcache_adr_o\[0\]
+port 2638 nsew
+rlabel metal3 s 352628 196724 352628 196724 4 u_riscv_top.wb_dcache_adr_o\[10\]
+port 2639 nsew
+rlabel metal3 s 352766 196452 352766 196452 4 u_riscv_top.wb_dcache_adr_o\[11\]
+port 2640 nsew
+rlabel metal3 s 352674 196180 352674 196180 4 u_riscv_top.wb_dcache_adr_o\[12\]
+port 2641 nsew
+rlabel metal3 s 352720 195908 352720 195908 4 u_riscv_top.wb_dcache_adr_o\[13\]
+port 2642 nsew
+rlabel metal3 s 352674 195636 352674 195636 4 u_riscv_top.wb_dcache_adr_o\[14\]
+port 2643 nsew
+rlabel metal3 s 352628 195364 352628 195364 4 u_riscv_top.wb_dcache_adr_o\[15\]
+port 2644 nsew
+rlabel metal3 s 352628 195092 352628 195092 4 u_riscv_top.wb_dcache_adr_o\[16\]
+port 2645 nsew
+rlabel metal3 s 352766 194820 352766 194820 4 u_riscv_top.wb_dcache_adr_o\[17\]
+port 2646 nsew
+rlabel metal3 s 352720 194548 352720 194548 4 u_riscv_top.wb_dcache_adr_o\[18\]
+port 2647 nsew
+rlabel metal3 s 352674 194276 352674 194276 4 u_riscv_top.wb_dcache_adr_o\[19\]
+port 2648 nsew
+rlabel metal3 s 352720 199172 352720 199172 4 u_riscv_top.wb_dcache_adr_o\[1\]
+port 2649 nsew
+rlabel metal3 s 352628 194004 352628 194004 4 u_riscv_top.wb_dcache_adr_o\[20\]
+port 2650 nsew
+rlabel metal3 s 352628 193732 352628 193732 4 u_riscv_top.wb_dcache_adr_o\[21\]
+port 2651 nsew
+rlabel metal3 s 352674 193460 352674 193460 4 u_riscv_top.wb_dcache_adr_o\[22\]
+port 2652 nsew
+rlabel metal3 s 352674 193188 352674 193188 4 u_riscv_top.wb_dcache_adr_o\[23\]
+port 2653 nsew
+rlabel metal3 s 352766 192916 352766 192916 4 u_riscv_top.wb_dcache_adr_o\[24\]
+port 2654 nsew
+rlabel metal3 s 352628 192644 352628 192644 4 u_riscv_top.wb_dcache_adr_o\[25\]
+port 2655 nsew
+rlabel metal3 s 352812 192372 352812 192372 4 u_riscv_top.wb_dcache_adr_o\[26\]
+port 2656 nsew
+rlabel metal3 s 352628 192100 352628 192100 4 u_riscv_top.wb_dcache_adr_o\[27\]
+port 2657 nsew
+rlabel metal3 s 352720 191828 352720 191828 4 u_riscv_top.wb_dcache_adr_o\[28\]
+port 2658 nsew
+rlabel metal3 s 352628 191556 352628 191556 4 u_riscv_top.wb_dcache_adr_o\[29\]
+port 2659 nsew
+rlabel metal3 s 352674 198900 352674 198900 4 u_riscv_top.wb_dcache_adr_o\[2\]
+port 2660 nsew
+rlabel metal3 s 352674 191284 352674 191284 4 u_riscv_top.wb_dcache_adr_o\[30\]
+port 2661 nsew
+rlabel metal3 s 352720 191012 352720 191012 4 u_riscv_top.wb_dcache_adr_o\[31\]
+port 2662 nsew
+rlabel metal3 s 352720 198628 352720 198628 4 u_riscv_top.wb_dcache_adr_o\[3\]
+port 2663 nsew
+rlabel metal3 s 352628 198356 352628 198356 4 u_riscv_top.wb_dcache_adr_o\[4\]
+port 2664 nsew
+rlabel metal3 s 352674 198084 352674 198084 4 u_riscv_top.wb_dcache_adr_o\[5\]
+port 2665 nsew
+rlabel metal3 s 352628 197812 352628 197812 4 u_riscv_top.wb_dcache_adr_o\[6\]
+port 2666 nsew
+rlabel metal3 s 352674 197540 352674 197540 4 u_riscv_top.wb_dcache_adr_o\[7\]
+port 2667 nsew
+rlabel metal3 s 352720 197268 352720 197268 4 u_riscv_top.wb_dcache_adr_o\[8\]
+port 2668 nsew
+rlabel metal3 s 352628 196996 352628 196996 4 u_riscv_top.wb_dcache_adr_o\[9\]
+port 2669 nsew
+rlabel metal3 s 352628 203252 352628 203252 4 u_riscv_top.wb_dcache_bl_o\[0\]
+port 2670 nsew
+rlabel metal3 s 352766 202980 352766 202980 4 u_riscv_top.wb_dcache_bl_o\[1\]
+port 2671 nsew
+rlabel metal3 s 352628 202708 352628 202708 4 u_riscv_top.wb_dcache_bl_o\[2\]
+port 2672 nsew
+rlabel metal3 s 352720 202436 352720 202436 4 u_riscv_top.wb_dcache_bl_o\[3\]
+port 2673 nsew
+rlabel metal3 s 352674 202164 352674 202164 4 u_riscv_top.wb_dcache_bl_o\[4\]
+port 2674 nsew
+rlabel metal3 s 352766 201892 352766 201892 4 u_riscv_top.wb_dcache_bl_o\[5\]
+port 2675 nsew
+rlabel metal3 s 352628 201620 352628 201620 4 u_riscv_top.wb_dcache_bl_o\[6\]
+port 2676 nsew
+rlabel metal3 s 352812 201348 352812 201348 4 u_riscv_top.wb_dcache_bl_o\[7\]
+port 2677 nsew
+rlabel metal3 s 352674 201076 352674 201076 4 u_riscv_top.wb_dcache_bl_o\[8\]
+port 2678 nsew
+rlabel metal3 s 352628 200804 352628 200804 4 u_riscv_top.wb_dcache_bl_o\[9\]
+port 2679 nsew
+rlabel metal3 s 352720 203524 352720 203524 4 u_riscv_top.wb_dcache_bry_o
+port 2680 nsew
+rlabel metal3 s 352674 220932 352674 220932 4 u_riscv_top.wb_dcache_dat_i\[0\]
+port 2681 nsew
+rlabel metal3 s 352766 218212 352766 218212 4 u_riscv_top.wb_dcache_dat_i\[10\]
+port 2682 nsew
+rlabel metal3 s 352628 217940 352628 217940 4 u_riscv_top.wb_dcache_dat_i\[11\]
+port 2683 nsew
+rlabel metal3 s 352720 217668 352720 217668 4 u_riscv_top.wb_dcache_dat_i\[12\]
+port 2684 nsew
+rlabel metal3 s 352628 217396 352628 217396 4 u_riscv_top.wb_dcache_dat_i\[13\]
+port 2685 nsew
+rlabel metal3 s 352674 217124 352674 217124 4 u_riscv_top.wb_dcache_dat_i\[14\]
+port 2686 nsew
+rlabel metal3 s 352766 216852 352766 216852 4 u_riscv_top.wb_dcache_dat_i\[15\]
+port 2687 nsew
+rlabel metal3 s 352766 216580 352766 216580 4 u_riscv_top.wb_dcache_dat_i\[16\]
+port 2688 nsew
+rlabel metal3 s 352628 216308 352628 216308 4 u_riscv_top.wb_dcache_dat_i\[17\]
+port 2689 nsew
+rlabel metal3 s 352674 216036 352674 216036 4 u_riscv_top.wb_dcache_dat_i\[18\]
+port 2690 nsew
+rlabel metal3 s 352720 215764 352720 215764 4 u_riscv_top.wb_dcache_dat_i\[19\]
+port 2691 nsew
+rlabel metal3 s 352628 220660 352628 220660 4 u_riscv_top.wb_dcache_dat_i\[1\]
+port 2692 nsew
+rlabel metal3 s 352628 215492 352628 215492 4 u_riscv_top.wb_dcache_dat_i\[20\]
+port 2693 nsew
+rlabel metal3 s 352628 215220 352628 215220 4 u_riscv_top.wb_dcache_dat_i\[21\]
+port 2694 nsew
+rlabel metal3 s 352720 214948 352720 214948 4 u_riscv_top.wb_dcache_dat_i\[22\]
+port 2695 nsew
+rlabel metal3 s 352628 214676 352628 214676 4 u_riscv_top.wb_dcache_dat_i\[23\]
+port 2696 nsew
+rlabel metal3 s 352674 214404 352674 214404 4 u_riscv_top.wb_dcache_dat_i\[24\]
+port 2697 nsew
+rlabel metal3 s 352766 214132 352766 214132 4 u_riscv_top.wb_dcache_dat_i\[25\]
+port 2698 nsew
+rlabel metal3 s 352766 213860 352766 213860 4 u_riscv_top.wb_dcache_dat_i\[26\]
+port 2699 nsew
+rlabel metal3 s 352628 213588 352628 213588 4 u_riscv_top.wb_dcache_dat_i\[27\]
+port 2700 nsew
+rlabel metal3 s 352628 213316 352628 213316 4 u_riscv_top.wb_dcache_dat_i\[28\]
+port 2701 nsew
+rlabel metal3 s 352674 213044 352674 213044 4 u_riscv_top.wb_dcache_dat_i\[29\]
+port 2702 nsew
+rlabel metal3 s 352766 220388 352766 220388 4 u_riscv_top.wb_dcache_dat_i\[2\]
+port 2703 nsew
+rlabel metal3 s 352720 212772 352720 212772 4 u_riscv_top.wb_dcache_dat_i\[30\]
+port 2704 nsew
+rlabel metal3 s 352628 212500 352628 212500 4 u_riscv_top.wb_dcache_dat_i\[31\]
+port 2705 nsew
+rlabel metal3 s 352674 220116 352674 220116 4 u_riscv_top.wb_dcache_dat_i\[3\]
+port 2706 nsew
+rlabel metal3 s 352628 219844 352628 219844 4 u_riscv_top.wb_dcache_dat_i\[4\]
+port 2707 nsew
+rlabel metal3 s 352720 219572 352720 219572 4 u_riscv_top.wb_dcache_dat_i\[5\]
+port 2708 nsew
+rlabel metal3 s 352628 219300 352628 219300 4 u_riscv_top.wb_dcache_dat_i\[6\]
+port 2709 nsew
+rlabel metal3 s 352720 219028 352720 219028 4 u_riscv_top.wb_dcache_dat_i\[7\]
+port 2710 nsew
+rlabel metal3 s 352674 218756 352674 218756 4 u_riscv_top.wb_dcache_dat_i\[8\]
+port 2711 nsew
+rlabel metal3 s 352628 218484 352628 218484 4 u_riscv_top.wb_dcache_dat_i\[9\]
+port 2712 nsew
+rlabel metal3 s 352720 212228 352720 212228 4 u_riscv_top.wb_dcache_dat_o\[0\]
+port 2713 nsew
+rlabel metal3 s 352674 209508 352674 209508 4 u_riscv_top.wb_dcache_dat_o\[10\]
+port 2714 nsew
+rlabel metal3 s 352628 209236 352628 209236 4 u_riscv_top.wb_dcache_dat_o\[11\]
+port 2715 nsew
+rlabel metal3 s 352766 208964 352766 208964 4 u_riscv_top.wb_dcache_dat_o\[12\]
+port 2716 nsew
+rlabel metal3 s 352674 208692 352674 208692 4 u_riscv_top.wb_dcache_dat_o\[13\]
+port 2717 nsew
+rlabel metal3 s 352720 208420 352720 208420 4 u_riscv_top.wb_dcache_dat_o\[14\]
+port 2718 nsew
+rlabel metal3 s 352674 208148 352674 208148 4 u_riscv_top.wb_dcache_dat_o\[15\]
+port 2719 nsew
+rlabel metal3 s 352628 207876 352628 207876 4 u_riscv_top.wb_dcache_dat_o\[16\]
+port 2720 nsew
+rlabel metal3 s 352766 207604 352766 207604 4 u_riscv_top.wb_dcache_dat_o\[17\]
+port 2721 nsew
+rlabel metal3 s 352720 207332 352720 207332 4 u_riscv_top.wb_dcache_dat_o\[18\]
+port 2722 nsew
+rlabel metal3 s 352674 207060 352674 207060 4 u_riscv_top.wb_dcache_dat_o\[19\]
+port 2723 nsew
+rlabel metal3 s 352674 211956 352674 211956 4 u_riscv_top.wb_dcache_dat_o\[1\]
+port 2724 nsew
+rlabel metal3 s 352720 206788 352720 206788 4 u_riscv_top.wb_dcache_dat_o\[20\]
+port 2725 nsew
+rlabel metal3 s 352628 206516 352628 206516 4 u_riscv_top.wb_dcache_dat_o\[21\]
+port 2726 nsew
+rlabel metal3 s 352628 206244 352628 206244 4 u_riscv_top.wb_dcache_dat_o\[22\]
+port 2727 nsew
+rlabel metal3 s 352674 205972 352674 205972 4 u_riscv_top.wb_dcache_dat_o\[23\]
+port 2728 nsew
+rlabel metal3 s 352766 205700 352766 205700 4 u_riscv_top.wb_dcache_dat_o\[24\]
+port 2729 nsew
+rlabel metal3 s 352628 205428 352628 205428 4 u_riscv_top.wb_dcache_dat_o\[25\]
+port 2730 nsew
+rlabel metal3 s 352674 205156 352674 205156 4 u_riscv_top.wb_dcache_dat_o\[26\]
+port 2731 nsew
+rlabel metal3 s 352628 204884 352628 204884 4 u_riscv_top.wb_dcache_dat_o\[27\]
+port 2732 nsew
+rlabel metal3 s 352720 204612 352720 204612 4 u_riscv_top.wb_dcache_dat_o\[28\]
+port 2733 nsew
+rlabel metal3 s 352766 204340 352766 204340 4 u_riscv_top.wb_dcache_dat_o\[29\]
+port 2734 nsew
+rlabel metal3 s 352628 211684 352628 211684 4 u_riscv_top.wb_dcache_dat_o\[2\]
+port 2735 nsew
+rlabel metal3 s 352628 204068 352628 204068 4 u_riscv_top.wb_dcache_dat_o\[30\]
+port 2736 nsew
+rlabel metal3 s 352674 203796 352674 203796 4 u_riscv_top.wb_dcache_dat_o\[31\]
+port 2737 nsew
+rlabel metal3 s 352766 211412 352766 211412 4 u_riscv_top.wb_dcache_dat_o\[3\]
+port 2738 nsew
+rlabel metal3 s 352812 211140 352812 211140 4 u_riscv_top.wb_dcache_dat_o\[4\]
+port 2739 nsew
+rlabel metal3 s 352766 210868 352766 210868 4 u_riscv_top.wb_dcache_dat_o\[5\]
+port 2740 nsew
+rlabel metal3 s 352628 210596 352628 210596 4 u_riscv_top.wb_dcache_dat_o\[6\]
+port 2741 nsew
+rlabel metal3 s 352720 210324 352720 210324 4 u_riscv_top.wb_dcache_dat_o\[7\]
+port 2742 nsew
+rlabel metal3 s 352812 210052 352812 210052 4 u_riscv_top.wb_dcache_dat_o\[8\]
+port 2743 nsew
+rlabel metal3 s 352674 209780 352674 209780 4 u_riscv_top.wb_dcache_dat_o\[9\]
+port 2744 nsew
+rlabel metal3 s 352628 221748 352628 221748 4 u_riscv_top.wb_dcache_err_i
+port 2745 nsew
+rlabel metal3 s 352628 221476 352628 221476 4 u_riscv_top.wb_dcache_lack_i
+port 2746 nsew
+rlabel metal3 s 352766 200532 352766 200532 4 u_riscv_top.wb_dcache_sel_o\[0\]
+port 2747 nsew
+rlabel metal3 s 352720 200260 352720 200260 4 u_riscv_top.wb_dcache_sel_o\[1\]
+port 2748 nsew
+rlabel metal3 s 352628 199988 352628 199988 4 u_riscv_top.wb_dcache_sel_o\[2\]
+port 2749 nsew
+rlabel metal3 s 352674 199716 352674 199716 4 u_riscv_top.wb_dcache_sel_o\[3\]
+port 2750 nsew
+rlabel metal3 s 352628 190196 352628 190196 4 u_riscv_top.wb_dcache_stb_o
+port 2751 nsew
+rlabel metal3 s 352628 190740 352628 190740 4 u_riscv_top.wb_dcache_we_o
+port 2752 nsew
+rlabel metal3 s 352628 252484 352628 252484 4 u_riscv_top.wb_icache_ack_i
+port 2753 nsew
+rlabel metal3 s 352628 239428 352628 239428 4 u_riscv_top.wb_icache_adr_o\[0\]
+port 2754 nsew
+rlabel metal3 s 352628 236708 352628 236708 4 u_riscv_top.wb_icache_adr_o\[10\]
+port 2755 nsew
+rlabel metal3 s 352674 236436 352674 236436 4 u_riscv_top.wb_icache_adr_o\[11\]
+port 2756 nsew
+rlabel metal3 s 352720 236164 352720 236164 4 u_riscv_top.wb_icache_adr_o\[12\]
+port 2757 nsew
+rlabel metal3 s 352766 235892 352766 235892 4 u_riscv_top.wb_icache_adr_o\[13\]
+port 2758 nsew
+rlabel metal3 s 352674 235620 352674 235620 4 u_riscv_top.wb_icache_adr_o\[14\]
+port 2759 nsew
+rlabel metal3 s 352628 235348 352628 235348 4 u_riscv_top.wb_icache_adr_o\[15\]
+port 2760 nsew
+rlabel metal3 s 352720 235076 352720 235076 4 u_riscv_top.wb_icache_adr_o\[16\]
+port 2761 nsew
+rlabel metal3 s 352674 234804 352674 234804 4 u_riscv_top.wb_icache_adr_o\[17\]
+port 2762 nsew
+rlabel metal3 s 352720 234532 352720 234532 4 u_riscv_top.wb_icache_adr_o\[18\]
+port 2763 nsew
+rlabel metal3 s 352628 234260 352628 234260 4 u_riscv_top.wb_icache_adr_o\[19\]
+port 2764 nsew
+rlabel metal3 s 352674 239156 352674 239156 4 u_riscv_top.wb_icache_adr_o\[1\]
+port 2765 nsew
+rlabel metal3 s 352628 233988 352628 233988 4 u_riscv_top.wb_icache_adr_o\[20\]
+port 2766 nsew
+rlabel metal3 s 352674 233716 352674 233716 4 u_riscv_top.wb_icache_adr_o\[21\]
+port 2767 nsew
+rlabel metal3 s 352766 233444 352766 233444 4 u_riscv_top.wb_icache_adr_o\[22\]
+port 2768 nsew
+rlabel metal3 s 352720 233172 352720 233172 4 u_riscv_top.wb_icache_adr_o\[23\]
+port 2769 nsew
+rlabel metal3 s 352766 232900 352766 232900 4 u_riscv_top.wb_icache_adr_o\[24\]
+port 2770 nsew
+rlabel metal3 s 352628 232628 352628 232628 4 u_riscv_top.wb_icache_adr_o\[25\]
+port 2771 nsew
+rlabel metal3 s 352674 232356 352674 232356 4 u_riscv_top.wb_icache_adr_o\[26\]
+port 2772 nsew
+rlabel metal3 s 352812 232084 352812 232084 4 u_riscv_top.wb_icache_adr_o\[27\]
+port 2773 nsew
+rlabel metal3 s 352766 231812 352766 231812 4 u_riscv_top.wb_icache_adr_o\[28\]
+port 2774 nsew
+rlabel metal3 s 352720 231540 352720 231540 4 u_riscv_top.wb_icache_adr_o\[29\]
+port 2775 nsew
+rlabel metal3 s 352766 238884 352766 238884 4 u_riscv_top.wb_icache_adr_o\[2\]
+port 2776 nsew
+rlabel metal3 s 352628 231268 352628 231268 4 u_riscv_top.wb_icache_adr_o\[30\]
+port 2777 nsew
+rlabel metal3 s 352674 230996 352674 230996 4 u_riscv_top.wb_icache_adr_o\[31\]
+port 2778 nsew
+rlabel metal3 s 352720 238612 352720 238612 4 u_riscv_top.wb_icache_adr_o\[3\]
+port 2779 nsew
+rlabel metal3 s 352628 238340 352628 238340 4 u_riscv_top.wb_icache_adr_o\[4\]
+port 2780 nsew
+rlabel metal3 s 352628 238068 352628 238068 4 u_riscv_top.wb_icache_adr_o\[5\]
+port 2781 nsew
+rlabel metal3 s 352674 237796 352674 237796 4 u_riscv_top.wb_icache_adr_o\[6\]
+port 2782 nsew
+rlabel metal3 s 352766 237524 352766 237524 4 u_riscv_top.wb_icache_adr_o\[7\]
+port 2783 nsew
+rlabel metal3 s 352766 237252 352766 237252 4 u_riscv_top.wb_icache_adr_o\[8\]
+port 2784 nsew
+rlabel metal3 s 352628 236980 352628 236980 4 u_riscv_top.wb_icache_adr_o\[9\]
+port 2785 nsew
+rlabel metal3 s 352812 243236 352812 243236 4 u_riscv_top.wb_icache_bl_o\[0\]
+port 2786 nsew
+rlabel metal3 s 352766 242964 352766 242964 4 u_riscv_top.wb_icache_bl_o\[1\]
+port 2787 nsew
+rlabel metal3 s 352720 242692 352720 242692 4 u_riscv_top.wb_icache_bl_o\[2\]
+port 2788 nsew
+rlabel metal3 s 352628 242420 352628 242420 4 u_riscv_top.wb_icache_bl_o\[3\]
+port 2789 nsew
+rlabel metal3 s 352766 242148 352766 242148 4 u_riscv_top.wb_icache_bl_o\[4\]
+port 2790 nsew
+rlabel metal3 s 352674 241876 352674 241876 4 u_riscv_top.wb_icache_bl_o\[5\]
+port 2791 nsew
+rlabel metal3 s 352628 241604 352628 241604 4 u_riscv_top.wb_icache_bl_o\[6\]
+port 2792 nsew
+rlabel metal3 s 352812 241332 352812 241332 4 u_riscv_top.wb_icache_bl_o\[7\]
+port 2793 nsew
+rlabel metal3 s 352628 241060 352628 241060 4 u_riscv_top.wb_icache_bl_o\[8\]
+port 2794 nsew
+rlabel metal3 s 352674 240788 352674 240788 4 u_riscv_top.wb_icache_bl_o\[9\]
+port 2795 nsew
+rlabel metal3 s 352628 243508 352628 243508 4 u_riscv_top.wb_icache_bry_o
+port 2796 nsew
+rlabel metal3 s 352674 252212 352674 252212 4 u_riscv_top.wb_icache_dat_i\[0\]
+port 2797 nsew
+rlabel metal3 s 352674 249492 352674 249492 4 u_riscv_top.wb_icache_dat_i\[10\]
+port 2798 nsew
+rlabel metal3 s 352628 249220 352628 249220 4 u_riscv_top.wb_icache_dat_i\[11\]
+port 2799 nsew
+rlabel metal3 s 352720 248948 352720 248948 4 u_riscv_top.wb_icache_dat_i\[12\]
+port 2800 nsew
+rlabel metal3 s 352628 248676 352628 248676 4 u_riscv_top.wb_icache_dat_i\[13\]
+port 2801 nsew
+rlabel metal3 s 352674 248404 352674 248404 4 u_riscv_top.wb_icache_dat_i\[14\]
+port 2802 nsew
+rlabel metal3 s 352766 248132 352766 248132 4 u_riscv_top.wb_icache_dat_i\[15\]
+port 2803 nsew
+rlabel metal3 s 352628 247860 352628 247860 4 u_riscv_top.wb_icache_dat_i\[16\]
+port 2804 nsew
+rlabel metal3 s 352720 247588 352720 247588 4 u_riscv_top.wb_icache_dat_i\[17\]
+port 2805 nsew
+rlabel metal3 s 352812 247316 352812 247316 4 u_riscv_top.wb_icache_dat_i\[18\]
+port 2806 nsew
+rlabel metal3 s 352674 247044 352674 247044 4 u_riscv_top.wb_icache_dat_i\[19\]
+port 2807 nsew
+rlabel metal3 s 352628 251940 352628 251940 4 u_riscv_top.wb_icache_dat_i\[1\]
+port 2808 nsew
+rlabel metal3 s 352674 246772 352674 246772 4 u_riscv_top.wb_icache_dat_i\[20\]
+port 2809 nsew
+rlabel metal3 s 352628 246500 352628 246500 4 u_riscv_top.wb_icache_dat_i\[21\]
+port 2810 nsew
+rlabel metal3 s 352628 246228 352628 246228 4 u_riscv_top.wb_icache_dat_i\[22\]
+port 2811 nsew
+rlabel metal3 s 352674 245956 352674 245956 4 u_riscv_top.wb_icache_dat_i\[23\]
+port 2812 nsew
+rlabel metal3 s 352720 245684 352720 245684 4 u_riscv_top.wb_icache_dat_i\[24\]
+port 2813 nsew
+rlabel metal3 s 352674 245412 352674 245412 4 u_riscv_top.wb_icache_dat_i\[25\]
+port 2814 nsew
+rlabel metal3 s 352628 245140 352628 245140 4 u_riscv_top.wb_icache_dat_i\[26\]
+port 2815 nsew
+rlabel metal3 s 352812 244868 352812 244868 4 u_riscv_top.wb_icache_dat_i\[27\]
+port 2816 nsew
+rlabel metal3 s 352766 244596 352766 244596 4 u_riscv_top.wb_icache_dat_i\[28\]
+port 2817 nsew
+rlabel metal3 s 352720 244324 352720 244324 4 u_riscv_top.wb_icache_dat_i\[29\]
+port 2818 nsew
+rlabel metal3 s 352766 251668 352766 251668 4 u_riscv_top.wb_icache_dat_i\[2\]
+port 2819 nsew
+rlabel metal3 s 352720 244052 352720 244052 4 u_riscv_top.wb_icache_dat_i\[30\]
+port 2820 nsew
+rlabel metal3 s 352674 243780 352674 243780 4 u_riscv_top.wb_icache_dat_i\[31\]
+port 2821 nsew
+rlabel metal3 s 352720 251396 352720 251396 4 u_riscv_top.wb_icache_dat_i\[3\]
+port 2822 nsew
+rlabel metal3 s 352766 251124 352766 251124 4 u_riscv_top.wb_icache_dat_i\[4\]
+port 2823 nsew
+rlabel metal3 s 352628 250852 352628 250852 4 u_riscv_top.wb_icache_dat_i\[5\]
+port 2824 nsew
+rlabel metal3 s 352674 250580 352674 250580 4 u_riscv_top.wb_icache_dat_i\[6\]
+port 2825 nsew
+rlabel metal3 s 352628 250308 352628 250308 4 u_riscv_top.wb_icache_dat_i\[7\]
+port 2826 nsew
+rlabel metal3 s 352720 250036 352720 250036 4 u_riscv_top.wb_icache_dat_i\[8\]
+port 2827 nsew
+rlabel metal3 s 352766 249764 352766 249764 4 u_riscv_top.wb_icache_dat_i\[9\]
+port 2828 nsew
+rlabel metal3 s 352628 253028 352628 253028 4 u_riscv_top.wb_icache_err_i
+port 2829 nsew
+rlabel metal3 s 352674 252756 352674 252756 4 u_riscv_top.wb_icache_lack_i
+port 2830 nsew
+rlabel metal3 s 352720 240516 352720 240516 4 u_riscv_top.wb_icache_sel_o\[0\]
+port 2831 nsew
+rlabel metal3 s 352766 240244 352766 240244 4 u_riscv_top.wb_icache_sel_o\[1\]
+port 2832 nsew
+rlabel metal3 s 352628 239972 352628 239972 4 u_riscv_top.wb_icache_sel_o\[2\]
+port 2833 nsew
+rlabel metal3 s 352720 239700 352720 239700 4 u_riscv_top.wb_icache_sel_o\[3\]
+port 2834 nsew
+rlabel metal3 s 352628 230180 352628 230180 4 u_riscv_top.wb_icache_stb_o
+port 2835 nsew
+rlabel metal3 s 352628 230724 352628 230724 4 u_riscv_top.wb_icache_we_o
+port 2836 nsew
+rlabel metal3 s 352628 141236 352628 141236 4 u_riscv_top.wbd_clk_int
+port 2837 nsew
+rlabel metal3 s 352674 179588 352674 179588 4 u_riscv_top.wbd_dmem_ack_i
+port 2838 nsew
+rlabel metal3 s 352628 159460 352628 159460 4 u_riscv_top.wbd_dmem_adr_o\[0\]
+port 2839 nsew
+rlabel metal3 s 352628 156740 352628 156740 4 u_riscv_top.wbd_dmem_adr_o\[10\]
+port 2840 nsew
+rlabel metal3 s 352674 156468 352674 156468 4 u_riscv_top.wbd_dmem_adr_o\[11\]
+port 2841 nsew
+rlabel metal3 s 352766 156196 352766 156196 4 u_riscv_top.wbd_dmem_adr_o\[12\]
+port 2842 nsew
+rlabel metal3 s 352766 155924 352766 155924 4 u_riscv_top.wbd_dmem_adr_o\[13\]
+port 2843 nsew
+rlabel metal3 s 352628 155652 352628 155652 4 u_riscv_top.wbd_dmem_adr_o\[14\]
+port 2844 nsew
+rlabel metal3 s 352674 155380 352674 155380 4 u_riscv_top.wbd_dmem_adr_o\[15\]
+port 2845 nsew
+rlabel metal3 s 352720 155108 352720 155108 4 u_riscv_top.wbd_dmem_adr_o\[16\]
+port 2846 nsew
+rlabel metal3 s 352628 154836 352628 154836 4 u_riscv_top.wbd_dmem_adr_o\[17\]
+port 2847 nsew
+rlabel metal3 s 352674 154564 352674 154564 4 u_riscv_top.wbd_dmem_adr_o\[18\]
+port 2848 nsew
+rlabel metal3 s 352720 154292 352720 154292 4 u_riscv_top.wbd_dmem_adr_o\[19\]
+port 2849 nsew
+rlabel metal3 s 352674 159188 352674 159188 4 u_riscv_top.wbd_dmem_adr_o\[1\]
+port 2850 nsew
+rlabel metal3 s 352628 154020 352628 154020 4 u_riscv_top.wbd_dmem_adr_o\[20\]
+port 2851 nsew
+rlabel metal3 s 352766 153748 352766 153748 4 u_riscv_top.wbd_dmem_adr_o\[21\]
+port 2852 nsew
+rlabel metal3 s 352674 153476 352674 153476 4 u_riscv_top.wbd_dmem_adr_o\[22\]
+port 2853 nsew
+rlabel metal3 s 352628 153204 352628 153204 4 u_riscv_top.wbd_dmem_adr_o\[23\]
+port 2854 nsew
+rlabel metal3 s 352628 152932 352628 152932 4 u_riscv_top.wbd_dmem_adr_o\[24\]
+port 2855 nsew
+rlabel metal3 s 352674 152660 352674 152660 4 u_riscv_top.wbd_dmem_adr_o\[25\]
+port 2856 nsew
+rlabel metal3 s 352766 152388 352766 152388 4 u_riscv_top.wbd_dmem_adr_o\[26\]
+port 2857 nsew
+rlabel metal3 s 352720 152116 352720 152116 4 u_riscv_top.wbd_dmem_adr_o\[27\]
+port 2858 nsew
+rlabel metal3 s 352628 151844 352628 151844 4 u_riscv_top.wbd_dmem_adr_o\[28\]
+port 2859 nsew
+rlabel metal3 s 352720 151572 352720 151572 4 u_riscv_top.wbd_dmem_adr_o\[29\]
+port 2860 nsew
+rlabel metal3 s 352720 158916 352720 158916 4 u_riscv_top.wbd_dmem_adr_o\[2\]
+port 2861 nsew
+rlabel metal3 s 352628 151300 352628 151300 4 u_riscv_top.wbd_dmem_adr_o\[30\]
+port 2862 nsew
+rlabel metal3 s 352628 151028 352628 151028 4 u_riscv_top.wbd_dmem_adr_o\[31\]
+port 2863 nsew
+rlabel metal3 s 352812 158644 352812 158644 4 u_riscv_top.wbd_dmem_adr_o\[3\]
+port 2864 nsew
+rlabel metal3 s 352766 158372 352766 158372 4 u_riscv_top.wbd_dmem_adr_o\[4\]
+port 2865 nsew
+rlabel metal3 s 352628 158100 352628 158100 4 u_riscv_top.wbd_dmem_adr_o\[5\]
+port 2866 nsew
+rlabel metal3 s 352674 157828 352674 157828 4 u_riscv_top.wbd_dmem_adr_o\[6\]
+port 2867 nsew
+rlabel metal3 s 352720 157556 352720 157556 4 u_riscv_top.wbd_dmem_adr_o\[7\]
+port 2868 nsew
+rlabel metal3 s 352720 157284 352720 157284 4 u_riscv_top.wbd_dmem_adr_o\[8\]
+port 2869 nsew
+rlabel metal3 s 352674 157012 352674 157012 4 u_riscv_top.wbd_dmem_adr_o\[9\]
+port 2870 nsew
+rlabel metal3 s 352766 161364 352766 161364 4 u_riscv_top.wbd_dmem_bl_o\[0\]
+port 2871 nsew
+rlabel metal3 s 352720 161092 352720 161092 4 u_riscv_top.wbd_dmem_bl_o\[1\]
+port 2872 nsew
+rlabel metal3 s 352628 160820 352628 160820 4 u_riscv_top.wbd_dmem_bl_o\[2\]
+port 2873 nsew
+rlabel metal3 s 352720 161636 352720 161636 4 u_riscv_top.wbd_dmem_bry_o
+port 2874 nsew
+rlabel metal3 s 352766 179044 352766 179044 4 u_riscv_top.wbd_dmem_dat_i\[0\]
+port 2875 nsew
+rlabel metal3 s 352674 176324 352674 176324 4 u_riscv_top.wbd_dmem_dat_i\[10\]
+port 2876 nsew
+rlabel metal3 s 352628 176052 352628 176052 4 u_riscv_top.wbd_dmem_dat_i\[11\]
+port 2877 nsew
+rlabel metal3 s 352720 175780 352720 175780 4 u_riscv_top.wbd_dmem_dat_i\[12\]
+port 2878 nsew
+rlabel metal3 s 352766 175508 352766 175508 4 u_riscv_top.wbd_dmem_dat_i\[13\]
+port 2879 nsew
+rlabel metal3 s 352812 175236 352812 175236 4 u_riscv_top.wbd_dmem_dat_i\[14\]
+port 2880 nsew
+rlabel metal3 s 352720 174964 352720 174964 4 u_riscv_top.wbd_dmem_dat_i\[15\]
+port 2881 nsew
+rlabel metal3 s 352628 174692 352628 174692 4 u_riscv_top.wbd_dmem_dat_i\[16\]
+port 2882 nsew
+rlabel metal3 s 352674 174420 352674 174420 4 u_riscv_top.wbd_dmem_dat_i\[17\]
+port 2883 nsew
+rlabel metal3 s 352766 174148 352766 174148 4 u_riscv_top.wbd_dmem_dat_i\[18\]
+port 2884 nsew
+rlabel metal3 s 352674 173876 352674 173876 4 u_riscv_top.wbd_dmem_dat_i\[19\]
+port 2885 nsew
+rlabel metal3 s 352628 178772 352628 178772 4 u_riscv_top.wbd_dmem_dat_i\[1\]
+port 2886 nsew
+rlabel metal3 s 352628 173604 352628 173604 4 u_riscv_top.wbd_dmem_dat_i\[20\]
+port 2887 nsew
+rlabel metal3 s 352628 173332 352628 173332 4 u_riscv_top.wbd_dmem_dat_i\[21\]
+port 2888 nsew
+rlabel metal3 s 352628 173060 352628 173060 4 u_riscv_top.wbd_dmem_dat_i\[22\]
+port 2889 nsew
+rlabel metal3 s 352720 172788 352720 172788 4 u_riscv_top.wbd_dmem_dat_i\[23\]
+port 2890 nsew
+rlabel metal3 s 352674 172516 352674 172516 4 u_riscv_top.wbd_dmem_dat_i\[24\]
+port 2891 nsew
+rlabel metal3 s 352766 172244 352766 172244 4 u_riscv_top.wbd_dmem_dat_i\[25\]
+port 2892 nsew
+rlabel metal3 s 352628 171972 352628 171972 4 u_riscv_top.wbd_dmem_dat_i\[26\]
+port 2893 nsew
+rlabel metal3 s 352720 171700 352720 171700 4 u_riscv_top.wbd_dmem_dat_i\[27\]
+port 2894 nsew
+rlabel metal3 s 352812 171428 352812 171428 4 u_riscv_top.wbd_dmem_dat_i\[28\]
+port 2895 nsew
+rlabel metal3 s 352674 171156 352674 171156 4 u_riscv_top.wbd_dmem_dat_i\[29\]
+port 2896 nsew
+rlabel metal3 s 352674 178500 352674 178500 4 u_riscv_top.wbd_dmem_dat_i\[2\]
+port 2897 nsew
+rlabel metal3 s 352720 170884 352720 170884 4 u_riscv_top.wbd_dmem_dat_i\[30\]
+port 2898 nsew
+rlabel metal3 s 352628 170612 352628 170612 4 u_riscv_top.wbd_dmem_dat_i\[31\]
+port 2899 nsew
+rlabel metal3 s 352812 178228 352812 178228 4 u_riscv_top.wbd_dmem_dat_i\[3\]
+port 2900 nsew
+rlabel metal3 s 352720 177956 352720 177956 4 u_riscv_top.wbd_dmem_dat_i\[4\]
+port 2901 nsew
+rlabel metal3 s 352628 177684 352628 177684 4 u_riscv_top.wbd_dmem_dat_i\[5\]
+port 2902 nsew
+rlabel metal3 s 352628 177412 352628 177412 4 u_riscv_top.wbd_dmem_dat_i\[6\]
+port 2903 nsew
+rlabel metal3 s 352674 177140 352674 177140 4 u_riscv_top.wbd_dmem_dat_i\[7\]
+port 2904 nsew
+rlabel metal3 s 352628 176868 352628 176868 4 u_riscv_top.wbd_dmem_dat_i\[8\]
+port 2905 nsew
+rlabel metal3 s 352628 176596 352628 176596 4 u_riscv_top.wbd_dmem_dat_i\[9\]
+port 2906 nsew
+rlabel metal3 s 352674 170340 352674 170340 4 u_riscv_top.wbd_dmem_dat_o\[0\]
+port 2907 nsew
+rlabel metal3 s 352674 167620 352674 167620 4 u_riscv_top.wbd_dmem_dat_o\[10\]
+port 2908 nsew
+rlabel metal3 s 352628 167348 352628 167348 4 u_riscv_top.wbd_dmem_dat_o\[11\]
+port 2909 nsew
+rlabel metal3 s 352720 167076 352720 167076 4 u_riscv_top.wbd_dmem_dat_o\[12\]
+port 2910 nsew
+rlabel metal3 s 352766 166804 352766 166804 4 u_riscv_top.wbd_dmem_dat_o\[13\]
+port 2911 nsew
+rlabel metal3 s 352628 166532 352628 166532 4 u_riscv_top.wbd_dmem_dat_o\[14\]
+port 2912 nsew
+rlabel metal3 s 352674 166260 352674 166260 4 u_riscv_top.wbd_dmem_dat_o\[15\]
+port 2913 nsew
+rlabel metal3 s 352812 165988 352812 165988 4 u_riscv_top.wbd_dmem_dat_o\[16\]
+port 2914 nsew
+rlabel metal3 s 352720 165716 352720 165716 4 u_riscv_top.wbd_dmem_dat_o\[17\]
+port 2915 nsew
+rlabel metal3 s 352766 165444 352766 165444 4 u_riscv_top.wbd_dmem_dat_o\[18\]
+port 2916 nsew
+rlabel metal3 s 352628 165172 352628 165172 4 u_riscv_top.wbd_dmem_dat_o\[19\]
+port 2917 nsew
+rlabel metal3 s 352628 170068 352628 170068 4 u_riscv_top.wbd_dmem_dat_o\[1\]
+port 2918 nsew
+rlabel metal3 s 352674 164900 352674 164900 4 u_riscv_top.wbd_dmem_dat_o\[20\]
+port 2919 nsew
+rlabel metal3 s 352628 164628 352628 164628 4 u_riscv_top.wbd_dmem_dat_o\[21\]
+port 2920 nsew
+rlabel metal3 s 352720 164356 352720 164356 4 u_riscv_top.wbd_dmem_dat_o\[22\]
+port 2921 nsew
+rlabel metal3 s 352628 164084 352628 164084 4 u_riscv_top.wbd_dmem_dat_o\[23\]
+port 2922 nsew
+rlabel metal3 s 352674 163812 352674 163812 4 u_riscv_top.wbd_dmem_dat_o\[24\]
+port 2923 nsew
+rlabel metal3 s 352628 163540 352628 163540 4 u_riscv_top.wbd_dmem_dat_o\[25\]
+port 2924 nsew
+rlabel metal3 s 352720 163268 352720 163268 4 u_riscv_top.wbd_dmem_dat_o\[26\]
+port 2925 nsew
+rlabel metal3 s 352766 162996 352766 162996 4 u_riscv_top.wbd_dmem_dat_o\[27\]
+port 2926 nsew
+rlabel metal3 s 352812 162724 352812 162724 4 u_riscv_top.wbd_dmem_dat_o\[28\]
+port 2927 nsew
+rlabel metal3 s 352628 162452 352628 162452 4 u_riscv_top.wbd_dmem_dat_o\[29\]
+port 2928 nsew
+rlabel metal3 s 352766 169796 352766 169796 4 u_riscv_top.wbd_dmem_dat_o\[2\]
+port 2929 nsew
+rlabel metal3 s 352674 162180 352674 162180 4 u_riscv_top.wbd_dmem_dat_o\[30\]
+port 2930 nsew
+rlabel metal3 s 352766 161908 352766 161908 4 u_riscv_top.wbd_dmem_dat_o\[31\]
+port 2931 nsew
+rlabel metal3 s 352720 169524 352720 169524 4 u_riscv_top.wbd_dmem_dat_o\[3\]
+port 2932 nsew
+rlabel metal3 s 352628 169252 352628 169252 4 u_riscv_top.wbd_dmem_dat_o\[4\]
+port 2933 nsew
+rlabel metal3 s 352674 168980 352674 168980 4 u_riscv_top.wbd_dmem_dat_o\[5\]
+port 2934 nsew
+rlabel metal3 s 352628 168708 352628 168708 4 u_riscv_top.wbd_dmem_dat_o\[6\]
+port 2935 nsew
+rlabel metal3 s 352766 168436 352766 168436 4 u_riscv_top.wbd_dmem_dat_o\[7\]
+port 2936 nsew
+rlabel metal3 s 352674 168164 352674 168164 4 u_riscv_top.wbd_dmem_dat_o\[8\]
+port 2937 nsew
+rlabel metal3 s 352628 167892 352628 167892 4 u_riscv_top.wbd_dmem_dat_o\[9\]
+port 2938 nsew
+rlabel metal3 s 352628 179860 352628 179860 4 u_riscv_top.wbd_dmem_err_i
+port 2939 nsew
+rlabel metal3 s 352720 179316 352720 179316 4 u_riscv_top.wbd_dmem_lack_i
+port 2940 nsew
+rlabel metal3 s 352674 160548 352674 160548 4 u_riscv_top.wbd_dmem_sel_o\[0\]
+port 2941 nsew
+rlabel metal3 s 352812 160276 352812 160276 4 u_riscv_top.wbd_dmem_sel_o\[1\]
+port 2942 nsew
+rlabel metal3 s 352674 160004 352674 160004 4 u_riscv_top.wbd_dmem_sel_o\[2\]
+port 2943 nsew
+rlabel metal3 s 352628 159732 352628 159732 4 u_riscv_top.wbd_dmem_sel_o\[3\]
+port 2944 nsew
+rlabel metal3 s 352628 150212 352628 150212 4 u_riscv_top.wbd_dmem_stb_o
+port 2945 nsew
+rlabel metal3 s 352674 150756 352674 150756 4 u_riscv_top.wbd_dmem_we_o
+port 2946 nsew
+rlabel metal2 s 450478 219837 450478 219837 4 uart_rst_n\[0\]
+port 2947 nsew
+rlabel metal2 s 450294 219922 450294 219922 4 uart_rst_n\[1\]
+port 2948 nsew
+rlabel metal2 s 457102 390364 457102 390364 4 uart_rxd\[0\]
+port 2949 nsew
+rlabel metal3 s 555120 222428 555120 222428 4 uart_rxd\[1\]
+port 2950 nsew
+rlabel metal2 s 456918 391180 456918 391180 4 uart_txd\[0\]
+port 2951 nsew
+rlabel metal3 s 555212 222700 555212 222700 4 uart_txd\[1\]
+port 2952 nsew
+rlabel metal2 s 443670 235586 443670 235586 4 uartm_rxd
+port 2953 nsew
+rlabel metal2 s 432814 80495 432814 80495 4 uartm_txd
+port 2954 nsew
+rlabel metal3 s 449949 220660 449949 220660 4 usb_clk
+port 2955 nsew
+rlabel metal3 s 555258 223244 555258 223244 4 usb_dn_i
+port 2956 nsew
+rlabel metal3 s 554108 223788 554108 223788 4 usb_dn_o
+port 2957 nsew
+rlabel metal1 s 505126 384438 505126 384438 4 usb_dp_i
+port 2958 nsew
+rlabel metal1 s 504804 384370 504804 384370 4 usb_dp_o
+port 2959 nsew
+rlabel metal1 s 507702 384506 507702 384506 4 usb_intr_o
+port 2960 nsew
+rlabel metal1 s 505632 384302 505632 384302 4 usb_oen
+port 2961 nsew
+rlabel metal1 s 448960 217974 448960 217974 4 usb_rst_n
+port 2962 nsew
+rlabel metal2 s 349938 19244 349938 19244 4 user_clock2
+port 2963 nsew
+rlabel metal2 s 581026 1928 581026 1928 4 user_irq[0]
+port 2964 nsew
+rlabel metal2 s 582222 3254 582222 3254 4 user_irq[1]
+port 2965 nsew
+rlabel metal2 s 582912 16560 582912 16560 4 user_irq[2]
+port 2966 nsew
+rlabel metal2 s 598 1588 598 1588 4 wb_clk_i
+port 2967 nsew
+rlabel metal2 s 1702 1962 1702 1962 4 wb_rst_i
+port 2968 nsew
+rlabel metal2 s 383686 130009 383686 130009 4 wbd_clk_int
+port 2969 nsew
+rlabel metal2 s 447166 450415 447166 450415 4 wbd_clk_pinmux_rp
+port 2970 nsew
+rlabel metal3 s 449972 450636 449972 450636 4 wbd_clk_pinmux_skew
+port 2971 nsew
+rlabel metal2 s 447442 132073 447442 132073 4 wbd_clk_qspi_rp
+port 2972 nsew
+rlabel metal3 s 450156 132804 450156 132804 4 wbd_clk_spi
+port 2973 nsew
+rlabel metal2 s 447166 261409 447166 261409 4 wbd_clk_uart_rp
+port 2974 nsew
+rlabel metal3 s 450156 261732 450156 261732 4 wbd_clk_uart_skew
+port 2975 nsew
+rlabel metal2 s 379684 105815 379684 105815 4 wbd_clk_wh
+port 2976 nsew
+rlabel metal2 s 384192 130009 384192 130009 4 wbd_clk_wi_skew
+port 2977 nsew
+rlabel metal2 s 447258 474011 447258 474011 4 wbd_glbl_ack_i
+port 2978 nsew
+rlabel metal2 s 447166 455039 447166 455039 4 wbd_glbl_adr_o\[0\]
+port 2979 nsew
+rlabel metal3 s 447166 454835 447166 454835 4 wbd_glbl_adr_o\[1\]
+port 2980 nsew
+rlabel metal2 s 447166 454631 447166 454631 4 wbd_glbl_adr_o\[2\]
+port 2981 nsew
+rlabel metal2 s 447258 454529 447258 454529 4 wbd_glbl_adr_o\[3\]
+port 2982 nsew
+rlabel metal2 s 447350 454529 447350 454529 4 wbd_glbl_adr_o\[4\]
+port 2983 nsew
+rlabel metal2 s 447258 453577 447258 453577 4 wbd_glbl_adr_o\[5\]
+port 2984 nsew
+rlabel metal3 s 447166 453509 447166 453509 4 wbd_glbl_adr_o\[6\]
+port 2985 nsew
+rlabel metal2 s 447166 453271 447166 453271 4 wbd_glbl_adr_o\[7\]
+port 2986 nsew
+rlabel metal2 s 447442 453271 447442 453271 4 wbd_glbl_adr_o\[8\]
+port 2987 nsew
+rlabel metal2 s 447350 453067 447350 453067 4 wbd_glbl_adr_o\[9\]
+port 2988 nsew
+rlabel metal2 s 447166 473841 447166 473841 4 wbd_glbl_dat_i\[0\]
+port 2989 nsew
+rlabel metal2 s 447442 471223 447442 471223 4 wbd_glbl_dat_i\[10\]
+port 2990 nsew
+rlabel metal2 s 447534 471053 447534 471053 4 wbd_glbl_dat_i\[11\]
+port 2991 nsew
+rlabel metal2 s 447350 470135 447350 470135 4 wbd_glbl_dat_i\[12\]
+port 2992 nsew
+rlabel metal2 s 447258 469965 447258 469965 4 wbd_glbl_dat_i\[13\]
+port 2993 nsew
+rlabel metal2 s 447166 469897 447166 469897 4 wbd_glbl_dat_i\[14\]
+port 2994 nsew
+rlabel metal2 s 447534 469829 447534 469829 4 wbd_glbl_dat_i\[15\]
+port 2995 nsew
+rlabel metal2 s 447442 469659 447442 469659 4 wbd_glbl_dat_i\[16\]
+port 2996 nsew
+rlabel metal2 s 447442 468741 447442 468741 4 wbd_glbl_dat_i\[17\]
+port 2997 nsew
+rlabel metal2 s 447166 468639 447166 468639 4 wbd_glbl_dat_i\[18\]
+port 2998 nsew
+rlabel metal2 s 447258 468571 447258 468571 4 wbd_glbl_dat_i\[19\]
+port 2999 nsew
+rlabel metal2 s 447350 473671 447350 473671 4 wbd_glbl_dat_i\[1\]
+port 3000 nsew
+rlabel metal2 s 447534 468469 447534 468469 4 wbd_glbl_dat_i\[20\]
+port 3001 nsew
+rlabel metal2 s 447350 468265 447350 468265 4 wbd_glbl_dat_i\[21\]
+port 3002 nsew
+rlabel metal2 s 447258 467483 447258 467483 4 wbd_glbl_dat_i\[22\]
+port 3003 nsew
+rlabel metal3 s 447166 467381 447166 467381 4 wbd_glbl_dat_i\[23\]
+port 3004 nsew
+rlabel metal2 s 447166 467177 447166 467177 4 wbd_glbl_dat_i\[24\]
+port 3005 nsew
+rlabel metal2 s 447258 467007 447258 467007 4 wbd_glbl_dat_i\[25\]
+port 3006 nsew
+rlabel metal2 s 447350 466837 447350 466837 4 wbd_glbl_dat_i\[26\]
+port 3007 nsew
+rlabel metal2 s 447534 465987 447534 465987 4 wbd_glbl_dat_i\[27\]
+port 3008 nsew
+rlabel metal2 s 447166 465885 447166 465885 4 wbd_glbl_dat_i\[28\]
+port 3009 nsew
+rlabel metal2 s 447258 465851 447258 465851 4 wbd_glbl_dat_i\[29\]
+port 3010 nsew
+rlabel metal2 s 447258 472923 447258 472923 4 wbd_glbl_dat_i\[2\]
+port 3011 nsew
+rlabel metal2 s 447350 465647 447350 465647 4 wbd_glbl_dat_i\[30\]
+port 3012 nsew
+rlabel metal2 s 447442 465545 447442 465545 4 wbd_glbl_dat_i\[31\]
+port 3013 nsew
+rlabel metal2 s 447166 472753 447166 472753 4 wbd_glbl_dat_i\[3\]
+port 3014 nsew
+rlabel metal2 s 447350 472685 447350 472685 4 wbd_glbl_dat_i\[4\]
+port 3015 nsew
+rlabel metal2 s 447442 472583 447442 472583 4 wbd_glbl_dat_i\[5\]
+port 3016 nsew
+rlabel metal2 s 447258 472311 447258 472311 4 wbd_glbl_dat_i\[6\]
+port 3017 nsew
+rlabel metal2 s 447350 471495 447350 471495 4 wbd_glbl_dat_i\[7\]
+port 3018 nsew
+rlabel metal3 s 447166 471427 447166 471427 4 wbd_glbl_dat_i\[8\]
+port 3019 nsew
+rlabel metal2 s 447258 471257 447258 471257 4 wbd_glbl_dat_i\[9\]
+port 3020 nsew
+rlabel metal2 s 447350 464661 447350 464661 4 wbd_glbl_dat_o\[0\]
+port 3021 nsew
+rlabel metal2 s 447166 461975 447166 461975 4 wbd_glbl_dat_o\[10\]
+port 3022 nsew
+rlabel metal2 s 447350 461805 447350 461805 4 wbd_glbl_dat_o\[11\]
+port 3023 nsew
+rlabel metal2 s 447258 461737 447258 461737 4 wbd_glbl_dat_o\[12\]
+port 3024 nsew
+rlabel metal2 s 447442 461635 447442 461635 4 wbd_glbl_dat_o\[13\]
+port 3025 nsew
+rlabel metal2 s 447166 461363 447166 461363 4 wbd_glbl_dat_o\[14\]
+port 3026 nsew
+rlabel metal2 s 447166 460615 447166 460615 4 wbd_glbl_dat_o\[15\]
+port 3027 nsew
+rlabel metal2 s 447350 460377 447350 460377 4 wbd_glbl_dat_o\[16\]
+port 3028 nsew
+rlabel metal3 s 447166 460275 447166 460275 4 wbd_glbl_dat_o\[17\]
+port 3029 nsew
+rlabel metal2 s 447442 460241 447442 460241 4 wbd_glbl_dat_o\[18\]
+port 3030 nsew
+rlabel metal2 s 447258 460037 447258 460037 4 wbd_glbl_dat_o\[19\]
+port 3031 nsew
+rlabel metal2 s 447442 464491 447442 464491 4 wbd_glbl_dat_o\[1\]
+port 3032 nsew
+rlabel metal2 s 447350 459187 447350 459187 4 wbd_glbl_dat_o\[20\]
+port 3033 nsew
+rlabel metal2 s 447166 459153 447166 459153 4 wbd_glbl_dat_o\[21\]
+port 3034 nsew
+rlabel metal2 s 447166 458881 447166 458881 4 wbd_glbl_dat_o\[22\]
+port 3035 nsew
+rlabel metal2 s 447258 458813 447258 458813 4 wbd_glbl_dat_o\[23\]
+port 3036 nsew
+rlabel metal2 s 447442 458711 447442 458711 4 wbd_glbl_dat_o\[24\]
+port 3037 nsew
+rlabel metal2 s 447166 457895 447166 457895 4 wbd_glbl_dat_o\[25\]
+port 3038 nsew
+rlabel metal2 s 447350 457657 447350 457657 4 wbd_glbl_dat_o\[26\]
+port 3039 nsew
+rlabel metal3 s 447166 457555 447166 457555 4 wbd_glbl_dat_o\[27\]
+port 3040 nsew
+rlabel metal2 s 447442 457521 447442 457521 4 wbd_glbl_dat_o\[28\]
+port 3041 nsew
+rlabel metal2 s 447258 457317 447258 457317 4 wbd_glbl_dat_o\[29\]
+port 3042 nsew
+rlabel metal2 s 447166 464457 447166 464457 4 wbd_glbl_dat_o\[2\]
+port 3043 nsew
+rlabel metal2 s 447166 456535 447166 456535 4 wbd_glbl_dat_o\[30\]
+port 3044 nsew
+rlabel metal2 s 447350 456297 447350 456297 4 wbd_glbl_dat_o\[31\]
+port 3045 nsew
+rlabel metal2 s 447258 464287 447258 464287 4 wbd_glbl_dat_o\[3\]
+port 3046 nsew
+rlabel metal2 s 447534 464219 447534 464219 4 wbd_glbl_dat_o\[4\]
+port 3047 nsew
+rlabel metal2 s 447258 463335 447258 463335 4 wbd_glbl_dat_o\[5\]
+port 3048 nsew
+rlabel metal2 s 447166 463233 447166 463233 4 wbd_glbl_dat_o\[6\]
+port 3049 nsew
+rlabel metal3 s 447166 463029 447166 463029 4 wbd_glbl_dat_o\[7\]
+port 3050 nsew
+rlabel metal2 s 447258 462859 447258 462859 4 wbd_glbl_dat_o\[8\]
+port 3051 nsew
+rlabel metal2 s 447350 462859 447350 462859 4 wbd_glbl_dat_o\[9\]
+port 3052 nsew
+rlabel metal3 s 447166 456195 447166 456195 4 wbd_glbl_sel_o\[0\]
+port 3053 nsew
+rlabel metal2 s 447258 456093 447258 456093 4 wbd_glbl_sel_o\[1\]
+port 3054 nsew
+rlabel metal2 s 447166 455855 447166 455855 4 wbd_glbl_sel_o\[2\]
+port 3055 nsew
+rlabel metal2 s 447258 455141 447258 455141 4 wbd_glbl_sel_o\[3\]
+port 3056 nsew
+rlabel metal2 s 447166 452013 447166 452013 4 wbd_glbl_stb_o
+port 3057 nsew
+rlabel metal2 s 447258 452183 447258 452183 4 wbd_glbl_we_o
+port 3058 nsew
+rlabel metal2 s 408848 105883 408848 105883 4 wbd_int_ack_o
+port 3059 nsew
+rlabel metal2 s 396152 105883 396152 105883 4 wbd_int_adr_i\[0\]
+port 3060 nsew
+rlabel metal2 s 394312 105883 394312 105883 4 wbd_int_adr_i\[10\]
+port 3061 nsew
+rlabel metal2 s 394128 105883 394128 105883 4 wbd_int_adr_i\[11\]
+port 3062 nsew
+rlabel metal2 s 393944 105883 393944 105883 4 wbd_int_adr_i\[12\]
+port 3063 nsew
+rlabel metal2 s 393760 105866 393760 105866 4 wbd_int_adr_i\[13\]
+port 3064 nsew
+rlabel metal2 s 393576 105883 393576 105883 4 wbd_int_adr_i\[14\]
+port 3065 nsew
+rlabel metal2 s 393392 105883 393392 105883 4 wbd_int_adr_i\[15\]
+port 3066 nsew
+rlabel metal2 s 393208 105883 393208 105883 4 wbd_int_adr_i\[16\]
+port 3067 nsew
+rlabel metal2 s 393024 105883 393024 105883 4 wbd_int_adr_i\[17\]
+port 3068 nsew
+rlabel metal2 s 392840 105883 392840 105883 4 wbd_int_adr_i\[18\]
+port 3069 nsew
+rlabel metal2 s 392656 105883 392656 105883 4 wbd_int_adr_i\[19\]
+port 3070 nsew
+rlabel metal2 s 395968 105883 395968 105883 4 wbd_int_adr_i\[1\]
+port 3071 nsew
+rlabel metal2 s 392472 105866 392472 105866 4 wbd_int_adr_i\[20\]
+port 3072 nsew
+rlabel metal2 s 392288 105883 392288 105883 4 wbd_int_adr_i\[21\]
+port 3073 nsew
+rlabel metal2 s 392104 105883 392104 105883 4 wbd_int_adr_i\[22\]
+port 3074 nsew
+rlabel metal2 s 391920 105883 391920 105883 4 wbd_int_adr_i\[23\]
+port 3075 nsew
+rlabel metal2 s 391736 105883 391736 105883 4 wbd_int_adr_i\[24\]
+port 3076 nsew
+rlabel metal2 s 391552 105883 391552 105883 4 wbd_int_adr_i\[25\]
+port 3077 nsew
+rlabel metal2 s 391368 105883 391368 105883 4 wbd_int_adr_i\[26\]
+port 3078 nsew
+rlabel metal2 s 391184 105883 391184 105883 4 wbd_int_adr_i\[27\]
+port 3079 nsew
+rlabel metal2 s 391000 105883 391000 105883 4 wbd_int_adr_i\[28\]
+port 3080 nsew
+rlabel metal2 s 390816 105883 390816 105883 4 wbd_int_adr_i\[29\]
+port 3081 nsew
+rlabel metal2 s 395784 105883 395784 105883 4 wbd_int_adr_i\[2\]
+port 3082 nsew
+rlabel metal2 s 390632 105883 390632 105883 4 wbd_int_adr_i\[30\]
+port 3083 nsew
+rlabel metal2 s 390448 105883 390448 105883 4 wbd_int_adr_i\[31\]
+port 3084 nsew
+rlabel metal2 s 395600 105883 395600 105883 4 wbd_int_adr_i\[3\]
+port 3085 nsew
+rlabel metal2 s 395416 105883 395416 105883 4 wbd_int_adr_i\[4\]
+port 3086 nsew
+rlabel metal2 s 395232 105883 395232 105883 4 wbd_int_adr_i\[5\]
+port 3087 nsew
+rlabel metal2 s 395048 105866 395048 105866 4 wbd_int_adr_i\[6\]
+port 3088 nsew
+rlabel metal2 s 394864 105866 394864 105866 4 wbd_int_adr_i\[7\]
+port 3089 nsew
+rlabel metal2 s 394680 105883 394680 105883 4 wbd_int_adr_i\[8\]
+port 3090 nsew
+rlabel metal2 s 394496 105883 394496 105883 4 wbd_int_adr_i\[9\]
+port 3091 nsew
+rlabel metal2 s 409292 105740 409292 105740 4 wbd_int_cyc_i
+port 3092 nsew
+rlabel metal2 s 402776 105883 402776 105883 4 wbd_int_dat_i\[0\]
+port 3093 nsew
+rlabel metal2 s 400936 105883 400936 105883 4 wbd_int_dat_i\[10\]
+port 3094 nsew
+rlabel metal2 s 400752 105883 400752 105883 4 wbd_int_dat_i\[11\]
+port 3095 nsew
+rlabel metal2 s 400568 105883 400568 105883 4 wbd_int_dat_i\[12\]
+port 3096 nsew
+rlabel metal2 s 400384 105883 400384 105883 4 wbd_int_dat_i\[13\]
+port 3097 nsew
+rlabel metal2 s 400200 105883 400200 105883 4 wbd_int_dat_i\[14\]
+port 3098 nsew
+rlabel metal2 s 400016 105883 400016 105883 4 wbd_int_dat_i\[15\]
+port 3099 nsew
+rlabel metal2 s 399832 105883 399832 105883 4 wbd_int_dat_i\[16\]
+port 3100 nsew
+rlabel metal2 s 399648 105883 399648 105883 4 wbd_int_dat_i\[17\]
+port 3101 nsew
+rlabel metal2 s 399464 105883 399464 105883 4 wbd_int_dat_i\[18\]
+port 3102 nsew
+rlabel metal2 s 399280 105883 399280 105883 4 wbd_int_dat_i\[19\]
+port 3103 nsew
+rlabel metal2 s 402592 105883 402592 105883 4 wbd_int_dat_i\[1\]
+port 3104 nsew
+rlabel metal2 s 399096 105883 399096 105883 4 wbd_int_dat_i\[20\]
+port 3105 nsew
+rlabel metal2 s 398912 105883 398912 105883 4 wbd_int_dat_i\[21\]
+port 3106 nsew
+rlabel metal2 s 398728 105883 398728 105883 4 wbd_int_dat_i\[22\]
+port 3107 nsew
+rlabel metal2 s 398544 105883 398544 105883 4 wbd_int_dat_i\[23\]
+port 3108 nsew
+rlabel metal2 s 398360 105883 398360 105883 4 wbd_int_dat_i\[24\]
+port 3109 nsew
+rlabel metal2 s 398176 105883 398176 105883 4 wbd_int_dat_i\[25\]
+port 3110 nsew
+rlabel metal2 s 397992 105883 397992 105883 4 wbd_int_dat_i\[26\]
+port 3111 nsew
+rlabel metal2 s 397808 105883 397808 105883 4 wbd_int_dat_i\[27\]
+port 3112 nsew
+rlabel metal2 s 397624 105866 397624 105866 4 wbd_int_dat_i\[28\]
+port 3113 nsew
+rlabel metal2 s 397440 105883 397440 105883 4 wbd_int_dat_i\[29\]
+port 3114 nsew
+rlabel metal2 s 402408 105883 402408 105883 4 wbd_int_dat_i\[2\]
+port 3115 nsew
+rlabel metal2 s 397256 105883 397256 105883 4 wbd_int_dat_i\[30\]
+port 3116 nsew
+rlabel metal2 s 397072 105883 397072 105883 4 wbd_int_dat_i\[31\]
+port 3117 nsew
+rlabel metal2 s 402224 105883 402224 105883 4 wbd_int_dat_i\[3\]
+port 3118 nsew
+rlabel metal2 s 402040 105866 402040 105866 4 wbd_int_dat_i\[4\]
+port 3119 nsew
+rlabel metal2 s 401856 105883 401856 105883 4 wbd_int_dat_i\[5\]
+port 3120 nsew
+rlabel metal2 s 401672 105883 401672 105883 4 wbd_int_dat_i\[6\]
+port 3121 nsew
+rlabel metal2 s 401488 105883 401488 105883 4 wbd_int_dat_i\[7\]
+port 3122 nsew
+rlabel metal2 s 401304 105883 401304 105883 4 wbd_int_dat_i\[8\]
+port 3123 nsew
+rlabel metal2 s 401120 105883 401120 105883 4 wbd_int_dat_i\[9\]
+port 3124 nsew
+rlabel metal2 s 408664 105883 408664 105883 4 wbd_int_dat_o\[0\]
+port 3125 nsew
+rlabel metal2 s 406824 105883 406824 105883 4 wbd_int_dat_o\[10\]
+port 3126 nsew
+rlabel metal2 s 406640 105883 406640 105883 4 wbd_int_dat_o\[11\]
+port 3127 nsew
+rlabel metal2 s 406456 105883 406456 105883 4 wbd_int_dat_o\[12\]
+port 3128 nsew
+rlabel metal2 s 406272 105883 406272 105883 4 wbd_int_dat_o\[13\]
+port 3129 nsew
+rlabel metal2 s 406088 105883 406088 105883 4 wbd_int_dat_o\[14\]
+port 3130 nsew
+rlabel metal2 s 405904 105883 405904 105883 4 wbd_int_dat_o\[15\]
+port 3131 nsew
+rlabel metal2 s 405720 105883 405720 105883 4 wbd_int_dat_o\[16\]
+port 3132 nsew
+rlabel metal2 s 405536 105883 405536 105883 4 wbd_int_dat_o\[17\]
+port 3133 nsew
+rlabel metal2 s 405352 105883 405352 105883 4 wbd_int_dat_o\[18\]
+port 3134 nsew
+rlabel metal2 s 405168 105883 405168 105883 4 wbd_int_dat_o\[19\]
+port 3135 nsew
+rlabel metal2 s 408480 105883 408480 105883 4 wbd_int_dat_o\[1\]
+port 3136 nsew
+rlabel metal2 s 404984 105883 404984 105883 4 wbd_int_dat_o\[20\]
+port 3137 nsew
+rlabel metal2 s 404800 105883 404800 105883 4 wbd_int_dat_o\[21\]
+port 3138 nsew
+rlabel metal2 s 404616 105883 404616 105883 4 wbd_int_dat_o\[22\]
+port 3139 nsew
+rlabel metal2 s 404432 105883 404432 105883 4 wbd_int_dat_o\[23\]
+port 3140 nsew
+rlabel metal2 s 404248 105883 404248 105883 4 wbd_int_dat_o\[24\]
+port 3141 nsew
+rlabel metal2 s 404064 105883 404064 105883 4 wbd_int_dat_o\[25\]
+port 3142 nsew
+rlabel metal2 s 403880 105883 403880 105883 4 wbd_int_dat_o\[26\]
+port 3143 nsew
+rlabel metal2 s 403696 105883 403696 105883 4 wbd_int_dat_o\[27\]
+port 3144 nsew
+rlabel metal2 s 403512 105866 403512 105866 4 wbd_int_dat_o\[28\]
+port 3145 nsew
+rlabel metal2 s 403328 105883 403328 105883 4 wbd_int_dat_o\[29\]
+port 3146 nsew
+rlabel metal2 s 408296 105883 408296 105883 4 wbd_int_dat_o\[2\]
+port 3147 nsew
+rlabel metal2 s 403144 105883 403144 105883 4 wbd_int_dat_o\[30\]
+port 3148 nsew
+rlabel metal2 s 403006 128972 403006 128972 4 wbd_int_dat_o\[31\]
+port 3149 nsew
+rlabel metal2 s 408112 105883 408112 105883 4 wbd_int_dat_o\[3\]
+port 3150 nsew
+rlabel metal2 s 407928 105883 407928 105883 4 wbd_int_dat_o\[4\]
+port 3151 nsew
+rlabel metal2 s 407744 105883 407744 105883 4 wbd_int_dat_o\[5\]
+port 3152 nsew
+rlabel metal2 s 407560 105883 407560 105883 4 wbd_int_dat_o\[6\]
+port 3153 nsew
+rlabel metal2 s 407376 105883 407376 105883 4 wbd_int_dat_o\[7\]
+port 3154 nsew
+rlabel metal2 s 407192 105883 407192 105883 4 wbd_int_dat_o\[8\]
+port 3155 nsew
+rlabel metal2 s 407008 105883 407008 105883 4 wbd_int_dat_o\[9\]
+port 3156 nsew
+rlabel metal2 s 409032 105883 409032 105883 4 wbd_int_err_o
+port 3157 nsew
+rlabel metal2 s 396888 105883 396888 105883 4 wbd_int_sel_i\[0\]
+port 3158 nsew
+rlabel metal2 s 396704 105883 396704 105883 4 wbd_int_sel_i\[1\]
+port 3159 nsew
+rlabel metal2 s 396520 105883 396520 105883 4 wbd_int_sel_i\[2\]
+port 3160 nsew
+rlabel metal2 s 396336 105883 396336 105883 4 wbd_int_sel_i\[3\]
+port 3161 nsew
+rlabel metal2 s 390080 105883 390080 105883 4 wbd_int_stb_i
+port 3162 nsew
+rlabel metal2 s 390264 105883 390264 105883 4 wbd_int_we_i
+port 3163 nsew
+rlabel metal2 s 500158 604700 500158 604700 4 wbd_pll_rst_n
+port 3164 nsew
+rlabel metal2 s 447258 181203 447258 181203 4 wbd_spim_ack_i
+port 3165 nsew
+rlabel metal2 s 447350 159341 447350 159341 4 wbd_spim_adr_o\[0\]
+port 3166 nsew
+rlabel metal2 s 447166 156553 447166 156553 4 wbd_spim_adr_o\[10\]
+port 3167 nsew
+rlabel metal2 s 447350 156451 447350 156451 4 wbd_spim_adr_o\[11\]
+port 3168 nsew
+rlabel metal2 s 447258 155669 447258 155669 4 wbd_spim_adr_o\[12\]
+port 3169 nsew
+rlabel metal2 s 447350 155465 447350 155465 4 wbd_spim_adr_o\[13\]
+port 3170 nsew
+rlabel metal3 s 447166 155363 447166 155363 4 wbd_spim_adr_o\[14\]
+port 3171 nsew
+rlabel metal2 s 447442 155329 447442 155329 4 wbd_spim_adr_o\[15\]
+port 3172 nsew
+rlabel metal2 s 447534 155159 447534 155159 4 wbd_spim_adr_o\[16\]
+port 3173 nsew
+rlabel metal2 s 447166 154887 447166 154887 4 wbd_spim_adr_o\[17\]
+port 3174 nsew
+rlabel metal2 s 447258 154207 447258 154207 4 wbd_spim_adr_o\[18\]
+port 3175 nsew
+rlabel metal3 s 447166 154037 447166 154037 4 wbd_spim_adr_o\[19\]
+port 3176 nsew
+rlabel metal2 s 447166 159137 447166 159137 4 wbd_spim_adr_o\[1\]
+port 3177 nsew
+rlabel metal2 s 447258 153867 447258 153867 4 wbd_spim_adr_o\[20\]
+port 3178 nsew
+rlabel metal2 s 447166 153697 447166 153697 4 wbd_spim_adr_o\[21\]
+port 3179 nsew
+rlabel metal2 s 447350 153527 447350 153527 4 wbd_spim_adr_o\[22\]
+port 3180 nsew
+rlabel metal2 s 447258 152847 447258 152847 4 wbd_spim_adr_o\[23\]
+port 3181 nsew
+rlabel metal3 s 447166 152677 447166 152677 4 wbd_spim_adr_o\[24\]
+port 3182 nsew
+rlabel metal2 s 447166 152439 447166 152439 4 wbd_spim_adr_o\[25\]
+port 3183 nsew
+rlabel metal2 s 447258 152371 447258 152371 4 wbd_spim_adr_o\[26\]
+port 3184 nsew
+rlabel metal2 s 447350 152201 447350 152201 4 wbd_spim_adr_o\[27\]
+port 3185 nsew
+rlabel metal2 s 447166 151453 447166 151453 4 wbd_spim_adr_o\[28\]
+port 3186 nsew
+rlabel metal2 s 447258 151215 447258 151215 4 wbd_spim_adr_o\[29\]
+port 3187 nsew
+rlabel metal2 s 447442 158321 447442 158321 4 wbd_spim_adr_o\[2\]
+port 3188 nsew
+rlabel metal3 s 447166 151045 447166 151045 4 wbd_spim_adr_o\[30\]
+port 3189 nsew
+rlabel metal2 s 447350 150977 447350 150977 4 wbd_spim_adr_o\[31\]
+port 3190 nsew
+rlabel metal2 s 447258 158287 447258 158287 4 wbd_spim_adr_o\[3\]
+port 3191 nsew
+rlabel metal3 s 447166 158117 447166 158117 4 wbd_spim_adr_o\[4\]
+port 3192 nsew
+rlabel metal2 s 447350 158049 447350 158049 4 wbd_spim_adr_o\[5\]
+port 3193 nsew
+rlabel metal2 s 447258 157811 447258 157811 4 wbd_spim_adr_o\[6\]
+port 3194 nsew
+rlabel metal2 s 447350 157063 447350 157063 4 wbd_spim_adr_o\[7\]
+port 3195 nsew
+rlabel metal2 s 447258 156893 447258 156893 4 wbd_spim_adr_o\[8\]
+port 3196 nsew
+rlabel metal2 s 447166 156825 447166 156825 4 wbd_spim_adr_o\[9\]
+port 3197 nsew
+rlabel metal2 s 447442 163353 447442 163353 4 wbd_spim_bl_o\[0\]
+port 3198 nsew
+rlabel metal2 s 447350 162469 447350 162469 4 wbd_spim_bl_o\[1\]
+port 3199 nsew
+rlabel metal2 s 447166 162367 447166 162367 4 wbd_spim_bl_o\[2\]
+port 3200 nsew
+rlabel metal2 s 447258 162299 447258 162299 4 wbd_spim_bl_o\[3\]
+port 3201 nsew
+rlabel metal2 s 447166 162027 447166 162027 4 wbd_spim_bl_o\[4\]
+port 3202 nsew
+rlabel metal2 s 447442 161993 447442 161993 4 wbd_spim_bl_o\[5\]
+port 3203 nsew
+rlabel metal2 s 447258 161177 447258 161177 4 wbd_spim_bl_o\[6\]
+port 3204 nsew
+rlabel metal2 s 447350 160939 447350 160939 4 wbd_spim_bl_o\[7\]
+port 3205 nsew
+rlabel metal2 s 447166 160871 447166 160871 4 wbd_spim_bl_o\[8\]
+port 3206 nsew
+rlabel metal2 s 447258 160701 447258 160701 4 wbd_spim_bl_o\[9\]
+port 3207 nsew
+rlabel metal2 s 447350 163455 447350 163455 4 wbd_spim_bry_o
+port 3208 nsew
+rlabel metal2 s 447166 180523 447166 180523 4 wbd_spim_dat_i\[0\]
+port 3209 nsew
+rlabel metal2 s 447442 177667 447442 177667 4 wbd_spim_dat_i\[10\]
+port 3210 nsew
+rlabel metal2 s 447166 177633 447166 177633 4 wbd_spim_dat_i\[11\]
+port 3211 nsew
+rlabel metal2 s 447258 177463 447258 177463 4 wbd_spim_dat_i\[12\]
+port 3212 nsew
+rlabel metal2 s 447166 177225 447166 177225 4 wbd_spim_dat_i\[13\]
+port 3213 nsew
+rlabel metal2 s 447350 177157 447350 177157 4 wbd_spim_dat_i\[14\]
+port 3214 nsew
+rlabel metal2 s 447258 176341 447258 176341 4 wbd_spim_dat_i\[15\]
+port 3215 nsew
+rlabel metal2 s 447166 176273 447166 176273 4 wbd_spim_dat_i\[16\]
+port 3216 nsew
+rlabel metal3 s 447166 176035 447166 176035 4 wbd_spim_dat_i\[17\]
+port 3217 nsew
+rlabel metal2 s 447258 175865 447258 175865 4 wbd_spim_dat_i\[18\]
+port 3218 nsew
+rlabel metal2 s 447350 175831 447350 175831 4 wbd_spim_dat_i\[19\]
+port 3219 nsew
+rlabel metal2 s 447350 180285 447350 180285 4 wbd_spim_dat_i\[1\]
+port 3220 nsew
+rlabel metal2 s 447350 174981 447350 174981 4 wbd_spim_dat_i\[20\]
+port 3221 nsew
+rlabel metal2 s 447166 174879 447166 174879 4 wbd_spim_dat_i\[21\]
+port 3222 nsew
+rlabel metal2 s 447258 174607 447258 174607 4 wbd_spim_dat_i\[22\]
+port 3223 nsew
+rlabel metal2 s 447166 174505 447166 174505 4 wbd_spim_dat_i\[23\]
+port 3224 nsew
+rlabel metal2 s 447442 174403 447442 174403 4 wbd_spim_dat_i\[24\]
+port 3225 nsew
+rlabel metal2 s 447534 173519 447534 173519 4 wbd_spim_dat_i\[25\]
+port 3226 nsew
+rlabel metal2 s 447258 173485 447258 173485 4 wbd_spim_dat_i\[26\]
+port 3227 nsew
+rlabel metal2 s 447166 173417 447166 173417 4 wbd_spim_dat_i\[27\]
+port 3228 nsew
+rlabel metal2 s 447350 173179 447350 173179 4 wbd_spim_dat_i\[28\]
+port 3229 nsew
+rlabel metal2 s 447442 173111 447442 173111 4 wbd_spim_dat_i\[29\]
+port 3230 nsew
+rlabel metal2 s 447258 180217 447258 180217 4 wbd_spim_dat_i\[2\]
+port 3231 nsew
+rlabel metal2 s 447166 172873 447166 172873 4 wbd_spim_dat_i\[30\]
+port 3232 nsew
+rlabel metal2 s 447258 172091 447258 172091 4 wbd_spim_dat_i\[31\]
+port 3233 nsew
+rlabel metal2 s 447442 180047 447442 180047 4 wbd_spim_dat_i\[3\]
+port 3234 nsew
+rlabel metal2 s 447166 179843 447166 179843 4 wbd_spim_dat_i\[4\]
+port 3235 nsew
+rlabel metal2 s 447442 178993 447442 178993 4 wbd_spim_dat_i\[5\]
+port 3236 nsew
+rlabel metal2 s 447166 178993 447166 178993 4 wbd_spim_dat_i\[6\]
+port 3237 nsew
+rlabel metal3 s 447166 178789 447166 178789 4 wbd_spim_dat_i\[7\]
+port 3238 nsew
+rlabel metal2 s 447350 178687 447350 178687 4 wbd_spim_dat_i\[8\]
+port 3239 nsew
+rlabel metal2 s 447258 178483 447258 178483 4 wbd_spim_dat_i\[9\]
+port 3240 nsew
+rlabel metal2 s 447166 172023 447166 172023 4 wbd_spim_dat_o\[0\]
+port 3241 nsew
+rlabel metal2 s 447166 169167 447166 169167 4 wbd_spim_dat_o\[10\]
+port 3242 nsew
+rlabel metal2 s 447442 169133 447442 169133 4 wbd_spim_dat_o\[11\]
+port 3243 nsew
+rlabel metal2 s 447350 168929 447350 168929 4 wbd_spim_dat_o\[12\]
+port 3244 nsew
+rlabel metal2 s 447258 168725 447258 168725 4 wbd_spim_dat_o\[13\]
+port 3245 nsew
+rlabel metal2 s 447258 168045 447258 168045 4 wbd_spim_dat_o\[14\]
+port 3246 nsew
+rlabel metal3 s 447166 167875 447166 167875 4 wbd_spim_dat_o\[15\]
+port 3247 nsew
+rlabel metal2 s 447166 167671 447166 167671 4 wbd_spim_dat_o\[16\]
+port 3248 nsew
+rlabel metal2 s 447258 167501 447258 167501 4 wbd_spim_dat_o\[17\]
+port 3249 nsew
+rlabel metal2 s 447350 167433 447350 167433 4 wbd_spim_dat_o\[18\]
+port 3250 nsew
+rlabel metal2 s 447258 166685 447258 166685 4 wbd_spim_dat_o\[19\]
+port 3251 nsew
+rlabel metal2 s 447350 171853 447350 171853 4 wbd_spim_dat_o\[1\]
+port 3252 nsew
+rlabel metal3 s 447166 166515 447166 166515 4 wbd_spim_dat_o\[20\]
+port 3253 nsew
+rlabel metal3 s 447166 166277 447166 166277 4 wbd_spim_dat_o\[21\]
+port 3254 nsew
+rlabel metal2 s 447258 166209 447258 166209 4 wbd_spim_dat_o\[22\]
+port 3255 nsew
+rlabel metal2 s 447350 166039 447350 166039 4 wbd_spim_dat_o\[23\]
+port 3256 nsew
+rlabel metal2 s 447258 165223 447258 165223 4 wbd_spim_dat_o\[24\]
+port 3257 nsew
+rlabel metal2 s 447534 165019 447534 165019 4 wbd_spim_dat_o\[25\]
+port 3258 nsew
+rlabel metal2 s 447166 165019 447166 165019 4 wbd_spim_dat_o\[26\]
+port 3259 nsew
+rlabel metal2 s 447442 164849 447442 164849 4 wbd_spim_dat_o\[27\]
+port 3260 nsew
+rlabel metal2 s 447350 164645 447350 164645 4 wbd_spim_dat_o\[28\]
+port 3261 nsew
+rlabel metal2 s 447166 163931 447166 163931 4 wbd_spim_dat_o\[29\]
+port 3262 nsew
+rlabel metal2 s 447166 171649 447166 171649 4 wbd_spim_dat_o\[2\]
+port 3263 nsew
+rlabel metal2 s 447258 163693 447258 163693 4 wbd_spim_dat_o\[30\]
+port 3264 nsew
+rlabel metal3 s 447166 163523 447166 163523 4 wbd_spim_dat_o\[31\]
+port 3265 nsew
+rlabel metal2 s 447258 171479 447258 171479 4 wbd_spim_dat_o\[3\]
+port 3266 nsew
+rlabel metal2 s 447350 170663 447350 170663 4 wbd_spim_dat_o\[4\]
+port 3267 nsew
+rlabel metal3 s 447166 170595 447166 170595 4 wbd_spim_dat_o\[5\]
+port 3268 nsew
+rlabel metal2 s 447258 170425 447258 170425 4 wbd_spim_dat_o\[6\]
+port 3269 nsew
+rlabel metal2 s 447442 170357 447442 170357 4 wbd_spim_dat_o\[7\]
+port 3270 nsew
+rlabel metal2 s 447166 170085 447166 170085 4 wbd_spim_dat_o\[8\]
+port 3271 nsew
+rlabel metal2 s 447258 169371 447258 169371 4 wbd_spim_dat_o\[9\]
+port 3272 nsew
+rlabel metal2 s 447166 181373 447166 181373 4 wbd_spim_lack_i
+port 3273 nsew
+rlabel metal2 s 447166 160497 447166 160497 4 wbd_spim_sel_o\[0\]
+port 3274 nsew
+rlabel metal2 s 447258 159783 447258 159783 4 wbd_spim_sel_o\[1\]
+port 3275 nsew
+rlabel metal2 s 447442 159579 447442 159579 4 wbd_spim_sel_o\[2\]
+port 3276 nsew
+rlabel metal2 s 447166 159545 447166 159545 4 wbd_spim_sel_o\[3\]
+port 3277 nsew
+rlabel metal2 s 447166 149957 447166 149957 4 wbd_spim_stb_o
+port 3278 nsew
+rlabel metal2 s 447442 150875 447442 150875 4 wbd_spim_we_o
+port 3279 nsew
+rlabel metal2 s 447166 301665 447166 301665 4 wbd_uart_ack_i
+port 3280 nsew
+rlabel metal2 s 447166 282897 447166 282897 4 wbd_uart_adr_o\[0\]
+port 3281 nsew
+rlabel metal2 s 447442 282421 447442 282421 4 wbd_uart_adr_o\[1\]
+port 3282 nsew
+rlabel metal2 s 447166 282353 447166 282353 4 wbd_uart_adr_o\[2\]
+port 3283 nsew
+rlabel metal2 s 447350 282251 447350 282251 4 wbd_uart_adr_o\[3\]
+port 3284 nsew
+rlabel metal2 s 447258 282047 447258 282047 4 wbd_uart_adr_o\[4\]
+port 3285 nsew
+rlabel metal2 s 447166 281537 447166 281537 4 wbd_uart_adr_o\[5\]
+port 3286 nsew
+rlabel metal2 s 447350 281061 447350 281061 4 wbd_uart_adr_o\[6\]
+port 3287 nsew
+rlabel metal2 s 447166 280959 447166 280959 4 wbd_uart_adr_o\[7\]
+port 3288 nsew
+rlabel metal2 s 447258 280857 447258 280857 4 wbd_uart_adr_o\[8\]
+port 3289 nsew
+rlabel metal2 s 447258 301495 447258 301495 4 wbd_uart_dat_i\[0\]
+port 3290 nsew
+rlabel metal3 s 447166 298741 447166 298741 4 wbd_uart_dat_i\[10\]
+port 3291 nsew
+rlabel metal2 s 447258 298639 447258 298639 4 wbd_uart_dat_i\[11\]
+port 3292 nsew
+rlabel metal2 s 447166 298129 447166 298129 4 wbd_uart_dat_i\[12\]
+port 3293 nsew
+rlabel metal2 s 447166 297721 447166 297721 4 wbd_uart_dat_i\[13\]
+port 3294 nsew
+rlabel metal2 s 447350 297517 447350 297517 4 wbd_uart_dat_i\[14\]
+port 3295 nsew
+rlabel metal2 s 447442 297483 447442 297483 4 wbd_uart_dat_i\[15\]
+port 3296 nsew
+rlabel metal2 s 447258 297279 447258 297279 4 wbd_uart_dat_i\[16\]
+port 3297 nsew
+rlabel metal3 s 448692 296820 448692 296820 4 wbd_uart_dat_i\[17\]
+port 3298 nsew
+rlabel metal2 s 447258 296327 447258 296327 4 wbd_uart_dat_i\[18\]
+port 3299 nsew
+rlabel metal2 s 447534 296123 447534 296123 4 wbd_uart_dat_i\[19\]
+port 3300 nsew
+rlabel metal2 s 447166 301325 447166 301325 4 wbd_uart_dat_i\[1\]
+port 3301 nsew
+rlabel metal2 s 447166 296123 447166 296123 4 wbd_uart_dat_i\[20\]
+port 3302 nsew
+rlabel metal2 s 447442 295953 447442 295953 4 wbd_uart_dat_i\[21\]
+port 3303 nsew
+rlabel metal2 s 447350 295749 447350 295749 4 wbd_uart_dat_i\[22\]
+port 3304 nsew
+rlabel metal2 s 447442 294899 447442 294899 4 wbd_uart_dat_i\[23\]
+port 3305 nsew
+rlabel metal3 s 447166 294899 447166 294899 4 wbd_uart_dat_i\[24\]
+port 3306 nsew
+rlabel metal2 s 447166 294695 447166 294695 4 wbd_uart_dat_i\[25\]
+port 3307 nsew
+rlabel metal2 s 447258 294525 447258 294525 4 wbd_uart_dat_i\[26\]
+port 3308 nsew
+rlabel metal2 s 447350 294457 447350 294457 4 wbd_uart_dat_i\[27\]
+port 3309 nsew
+rlabel metal2 s 447166 293607 447166 293607 4 wbd_uart_dat_i\[28\]
+port 3310 nsew
+rlabel metal2 s 447258 293437 447258 293437 4 wbd_uart_dat_i\[29\]
+port 3311 nsew
+rlabel metal2 s 447166 300849 447166 300849 4 wbd_uart_dat_i\[2\]
+port 3312 nsew
+rlabel metal2 s 447350 293403 447350 293403 4 wbd_uart_dat_i\[30\]
+port 3313 nsew
+rlabel metal2 s 447442 293233 447442 293233 4 wbd_uart_dat_i\[31\]
+port 3314 nsew
+rlabel metal2 s 447258 300441 447258 300441 4 wbd_uart_dat_i\[3\]
+port 3315 nsew
+rlabel metal3 s 447166 300339 447166 300339 4 wbd_uart_dat_i\[4\]
+port 3316 nsew
+rlabel metal3 s 447166 300101 447166 300101 4 wbd_uart_dat_i\[5\]
+port 3317 nsew
+rlabel metal2 s 447350 299999 447350 299999 4 wbd_uart_dat_i\[6\]
+port 3318 nsew
+rlabel metal2 s 447166 299489 447166 299489 4 wbd_uart_dat_i\[7\]
+port 3319 nsew
+rlabel metal2 s 447258 299115 447258 299115 4 wbd_uart_dat_i\[8\]
+port 3320 nsew
+rlabel metal2 s 447166 298945 447166 298945 4 wbd_uart_dat_i\[9\]
+port 3321 nsew
+rlabel metal2 s 447166 292995 447166 292995 4 wbd_uart_dat_o\[0\]
+port 3322 nsew
+rlabel metal2 s 447166 290275 447166 290275 4 wbd_uart_dat_o\[10\]
+port 3323 nsew
+rlabel metal2 s 447442 289425 447442 289425 4 wbd_uart_dat_o\[11\]
+port 3324 nsew
+rlabel metal2 s 447166 289425 447166 289425 4 wbd_uart_dat_o\[12\]
+port 3325 nsew
+rlabel metal2 s 447258 289255 447258 289255 4 wbd_uart_dat_o\[13\]
+port 3326 nsew
+rlabel metal2 s 447166 289051 447166 289051 4 wbd_uart_dat_o\[14\]
+port 3327 nsew
+rlabel metal2 s 447350 288949 447350 288949 4 wbd_uart_dat_o\[15\]
+port 3328 nsew
+rlabel metal2 s 447258 288133 447258 288133 4 wbd_uart_dat_o\[16\]
+port 3329 nsew
+rlabel metal2 s 447350 287963 447350 287963 4 wbd_uart_dat_o\[17\]
+port 3330 nsew
+rlabel metal2 s 447166 287895 447166 287895 4 wbd_uart_dat_o\[18\]
+port 3331 nsew
+rlabel metal2 s 447166 287623 447166 287623 4 wbd_uart_dat_o\[19\]
+port 3332 nsew
+rlabel metal2 s 447534 292179 447534 292179 4 wbd_uart_dat_o\[1\]
+port 3333 nsew
+rlabel metal2 s 447258 287521 447258 287521 4 wbd_uart_dat_o\[20\]
+port 3334 nsew
+rlabel metal2 s 447442 286671 447442 286671 4 wbd_uart_dat_o\[21\]
+port 3335 nsew
+rlabel metal2 s 447258 286637 447258 286637 4 wbd_uart_dat_o\[22\]
+port 3336 nsew
+rlabel metal3 s 447166 286467 447166 286467 4 wbd_uart_dat_o\[23\]
+port 3337 nsew
+rlabel metal2 s 447258 286297 447258 286297 4 wbd_uart_dat_o\[24\]
+port 3338 nsew
+rlabel metal2 s 447350 286263 447350 286263 4 wbd_uart_dat_o\[25\]
+port 3339 nsew
+rlabel metal3 s 447166 285651 447166 285651 4 wbd_uart_dat_o\[26\]
+port 3340 nsew
+rlabel metal2 s 447350 285209 447350 285209 4 wbd_uart_dat_o\[27\]
+port 3341 nsew
+rlabel metal3 s 447166 285141 447166 285141 4 wbd_uart_dat_o\[28\]
+port 3342 nsew
+rlabel metal2 s 447258 284971 447258 284971 4 wbd_uart_dat_o\[29\]
+port 3343 nsew
+rlabel metal2 s 447350 292009 447350 292009 4 wbd_uart_dat_o\[2\]
+port 3344 nsew
+rlabel metal2 s 447166 284767 447166 284767 4 wbd_uart_dat_o\[30\]
+port 3345 nsew
+rlabel metal3 s 447166 284291 447166 284291 4 wbd_uart_dat_o\[31\]
+port 3346 nsew
+rlabel metal2 s 447166 291975 447166 291975 4 wbd_uart_dat_o\[3\]
+port 3347 nsew
+rlabel metal2 s 447442 291873 447442 291873 4 wbd_uart_dat_o\[4\]
+port 3348 nsew
+rlabel metal2 s 447258 291669 447258 291669 4 wbd_uart_dat_o\[5\]
+port 3349 nsew
+rlabel metal2 s 447442 290785 447442 290785 4 wbd_uart_dat_o\[6\]
+port 3350 nsew
+rlabel metal2 s 447166 290751 447166 290751 4 wbd_uart_dat_o\[7\]
+port 3351 nsew
+rlabel metal2 s 447258 290649 447258 290649 4 wbd_uart_dat_o\[8\]
+port 3352 nsew
+rlabel metal2 s 447350 290445 447350 290445 4 wbd_uart_dat_o\[9\]
+port 3353 nsew
+rlabel metal2 s 447258 283883 447258 283883 4 wbd_uart_sel_o\[0\]
+port 3354 nsew
+rlabel metal3 s 447166 283781 447166 283781 4 wbd_uart_sel_o\[1\]
+port 3355 nsew
+rlabel metal2 s 447166 283577 447166 283577 4 wbd_uart_sel_o\[2\]
+port 3356 nsew
+rlabel metal2 s 447258 283407 447258 283407 4 wbd_uart_sel_o\[3\]
+port 3357 nsew
+rlabel metal2 s 447166 280177 447166 280177 4 wbd_uart_stb_o
+port 3358 nsew
+rlabel metal2 s 447442 280755 447442 280755 4 wbd_uart_we_o
+port 3359 nsew
+rlabel metal2 s 350911 18972 350911 18972 4 wbs_ack_o
+port 3360 nsew
+rlabel metal2 s 351601 18972 351601 18972 4 wbs_adr_i[0]
+port 3361 nsew
+rlabel metal2 s 353326 14518 353326 14518 4 wbs_adr_i[10]
+port 3362 nsew
+rlabel metal2 s 352590 11152 352590 11152 4 wbs_adr_i[11]
+port 3363 nsew
+rlabel metal2 s 358961 18972 358961 18972 4 wbs_adr_i[12]
+port 3364 nsew
+rlabel metal2 s 58466 7504 58466 7504 4 wbs_adr_i[13]
+port 3365 nsew
+rlabel metal2 s 62054 3254 62054 3254 4 wbs_adr_i[14]
+port 3366 nsew
+rlabel metal2 s 65550 3288 65550 3288 4 wbs_adr_i[15]
+port 3367 nsew
+rlabel metal2 s 69138 3322 69138 3322 4 wbs_adr_i[16]
+port 3368 nsew
+rlabel metal1 s 358248 16898 358248 16898 4 wbs_adr_i[17]
+port 3369 nsew
+rlabel metal2 s 76222 2064 76222 2064 4 wbs_adr_i[18]
+port 3370 nsew
+rlabel metal2 s 79481 340 79481 340 4 wbs_adr_i[19]
+port 3371 nsew
+rlabel metal2 s 352084 17884 352084 17884 4 wbs_adr_i[1]
+port 3372 nsew
+rlabel metal2 s 83306 2744 83306 2744 4 wbs_adr_i[20]
+port 3373 nsew
+rlabel metal2 s 86894 3356 86894 3356 4 wbs_adr_i[21]
+port 3374 nsew
+rlabel metal2 s 364481 18972 364481 18972 4 wbs_adr_i[22]
+port 3375 nsew
+rlabel metal2 s 365033 18972 365033 18972 4 wbs_adr_i[23]
+port 3376 nsew
+rlabel metal2 s 365585 18972 365585 18972 4 wbs_adr_i[24]
+port 3377 nsew
+rlabel metal2 s 100917 340 100917 340 4 wbs_adr_i[25]
+port 3378 nsew
+rlabel metal2 s 366689 18972 366689 18972 4 wbs_adr_i[26]
+port 3379 nsew
+rlabel metal2 s 367287 18972 367287 18972 4 wbs_adr_i[27]
+port 3380 nsew
+rlabel metal2 s 367793 18972 367793 18972 4 wbs_adr_i[28]
+port 3381 nsew
+rlabel metal2 s 368345 18972 368345 18972 4 wbs_adr_i[29]
+port 3382 nsew
+rlabel metal1 s 352590 17714 352590 17714 4 wbs_adr_i[2]
+port 3383 nsew
+rlabel metal2 s 368897 18972 368897 18972 4 wbs_adr_i[30]
+port 3384 nsew
+rlabel metal2 s 369449 18972 369449 18972 4 wbs_adr_i[31]
+port 3385 nsew
+rlabel metal2 s 353809 18972 353809 18972 4 wbs_adr_i[3]
+port 3386 nsew
+rlabel metal2 s 354545 18972 354545 18972 4 wbs_adr_i[4]
+port 3387 nsew
+rlabel metal2 s 355143 18972 355143 18972 4 wbs_adr_i[5]
+port 3388 nsew
+rlabel metal2 s 355649 18972 355649 18972 4 wbs_adr_i[6]
+port 3389 nsew
+rlabel metal2 s 36977 340 36977 340 4 wbs_adr_i[7]
+port 3390 nsew
+rlabel metal2 s 40473 340 40473 340 4 wbs_adr_i[8]
+port 3391 nsew
+rlabel metal2 s 44298 2676 44298 2676 4 wbs_adr_i[9]
+port 3392 nsew
+rlabel metal1 s 350911 18870 350911 18870 4 wbs_cyc_i
+port 3393 nsew
+rlabel metal2 s 351785 18972 351785 18972 4 wbs_dat_i[0]
+port 3394 nsew
+rlabel metal2 s 48753 340 48753 340 4 wbs_dat_i[10]
+port 3395 nsew
+rlabel metal2 s 358593 18972 358593 18972 4 wbs_dat_i[11]
+port 3396 nsew
+rlabel metal2 s 56074 7470 56074 7470 4 wbs_dat_i[12]
+port 3397 nsew
+rlabel metal2 s 59517 340 59517 340 4 wbs_dat_i[13]
+port 3398 nsew
+rlabel metal2 s 63250 4682 63250 4682 4 wbs_dat_i[14]
+port 3399 nsew
+rlabel metal1 s 360571 18870 360571 18870 4 wbs_dat_i[15]
+port 3400 nsew
+rlabel metal2 s 361353 18972 361353 18972 4 wbs_dat_i[16]
+port 3401 nsew
+rlabel metal2 s 73830 2030 73830 2030 4 wbs_dat_i[17]
+port 3402 nsew
+rlabel metal2 s 77418 4818 77418 4818 4 wbs_dat_i[18]
+port 3403 nsew
+rlabel metal2 s 80914 4784 80914 4784 4 wbs_dat_i[19]
+port 3404 nsew
+rlabel metal2 s 352429 18972 352429 18972 4 wbs_dat_i[1]
+port 3405 nsew
+rlabel metal1 s 362986 18972 362986 18972 4 wbs_dat_i[20]
+port 3406 nsew
+rlabel metal2 s 87998 2778 87998 2778 4 wbs_dat_i[21]
+port 3407 nsew
+rlabel metal2 s 364711 18972 364711 18972 4 wbs_dat_i[22]
+port 3408 nsew
+rlabel metal2 s 95174 3390 95174 3390 4 wbs_dat_i[23]
+port 3409 nsew
+rlabel metal2 s 365815 18972 365815 18972 4 wbs_dat_i[24]
+port 3410 nsew
+rlabel metal2 s 366298 17799 366298 17799 4 wbs_dat_i[25]
+port 3411 nsew
+rlabel metal2 s 366873 18972 366873 18972 4 wbs_dat_i[26]
+port 3412 nsew
+rlabel metal2 s 367471 18972 367471 18972 4 wbs_dat_i[27]
+port 3413 nsew
+rlabel metal2 s 367977 18972 367977 18972 4 wbs_dat_i[28]
+port 3414 nsew
+rlabel metal2 s 368529 18972 368529 18972 4 wbs_dat_i[29]
+port 3415 nsew
+rlabel metal2 s 18117 340 18117 340 4 wbs_dat_i[2]
+port 3416 nsew
+rlabel metal2 s 119922 1860 119922 1860 4 wbs_dat_i[30]
+port 3417 nsew
+rlabel metal2 s 369633 18972 369633 18972 4 wbs_dat_i[31]
+port 3418 nsew
+rlabel metal2 s 22809 340 22809 340 4 wbs_dat_i[3]
+port 3419 nsew
+rlabel metal2 s 354821 18972 354821 18972 4 wbs_dat_i[4]
+port 3420 nsew
+rlabel metal2 s 31089 340 31089 340 4 wbs_dat_i[5]
+port 3421 nsew
+rlabel metal2 s 34677 340 34677 340 4 wbs_dat_i[6]
+port 3422 nsew
+rlabel metal2 s 38410 2642 38410 2642 4 wbs_dat_i[7]
+port 3423 nsew
+rlabel metal2 s 41906 5532 41906 5532 4 wbs_dat_i[8]
+port 3424 nsew
+rlabel metal2 s 45494 4138 45494 4138 4 wbs_dat_i[9]
+port 3425 nsew
+rlabel metal2 s 351969 18972 351969 18972 4 wbs_dat_o[0]
+port 3426 nsew
+rlabel metal2 s 50186 3339 50186 3339 4 wbs_dat_o[10]
+port 3427 nsew
+rlabel metal1 s 358202 17306 358202 17306 4 wbs_dat_o[11]
+port 3428 nsew
+rlabel metal2 s 57033 340 57033 340 4 wbs_dat_o[12]
+port 3429 nsew
+rlabel metal2 s 60858 1248 60858 1248 4 wbs_dat_o[13]
+port 3430 nsew
+rlabel metal2 s 64354 1911 64354 1911 4 wbs_dat_o[14]
+port 3431 nsew
+rlabel metal2 s 67942 1282 67942 1282 4 wbs_dat_o[15]
+port 3432 nsew
+rlabel metal2 s 361514 18547 361514 18547 4 wbs_dat_o[16]
+port 3433 nsew
+rlabel metal2 s 75026 8218 75026 8218 4 wbs_dat_o[17]
+port 3434 nsew
+rlabel metal2 s 78377 340 78377 340 4 wbs_dat_o[18]
+port 3435 nsew
+rlabel metal2 s 81873 340 81873 340 4 wbs_dat_o[19]
+port 3436 nsew
+rlabel metal2 s 352544 17884 352544 17884 4 wbs_dat_o[1]
+port 3437 nsew
+rlabel metal2 s 363722 18649 363722 18649 4 wbs_dat_o[20]
+port 3438 nsew
+rlabel metal2 s 89194 1316 89194 1316 4 wbs_dat_o[21]
+port 3439 nsew
+rlabel metal2 s 364826 18615 364826 18615 4 wbs_dat_o[22]
+port 3440 nsew
+rlabel metal2 s 96041 340 96041 340 4 wbs_dat_o[23]
+port 3441 nsew
+rlabel metal2 s 99866 1350 99866 1350 4 wbs_dat_o[24]
+port 3442 nsew
+rlabel metal2 s 103362 2914 103362 2914 4 wbs_dat_o[25]
+port 3443 nsew
+rlabel metal2 s 367034 18649 367034 18649 4 wbs_dat_o[26]
+port 3444 nsew
+rlabel metal2 s 367609 18972 367609 18972 4 wbs_dat_o[27]
+port 3445 nsew
+rlabel metal2 s 368138 18377 368138 18377 4 wbs_dat_o[28]
+port 3446 nsew
+rlabel metal2 s 117622 2030 117622 2030 4 wbs_dat_o[29]
+port 3447 nsew
+rlabel metal2 s 349278 17544 349278 17544 4 wbs_dat_o[2]
+port 3448 nsew
+rlabel metal2 s 121118 2064 121118 2064 4 wbs_dat_o[30]
+port 3449 nsew
+rlabel metal2 s 369794 18309 369794 18309 4 wbs_dat_o[31]
+port 3450 nsew
+rlabel metal2 s 24242 2642 24242 2642 4 wbs_dat_o[3]
+port 3451 nsew
+rlabel metal2 s 28743 340 28743 340 4 wbs_dat_o[4]
+port 3452 nsew
+rlabel metal2 s 32430 1894 32430 1894 4 wbs_dat_o[5]
+port 3453 nsew
+rlabel metal2 s 36018 4750 36018 4750 4 wbs_dat_o[6]
+port 3454 nsew
+rlabel metal2 s 39606 1928 39606 1928 4 wbs_dat_o[7]
+port 3455 nsew
+rlabel metal2 s 43102 3288 43102 3288 4 wbs_dat_o[8]
+port 3456 nsew
+rlabel metal2 s 46690 1962 46690 1962 4 wbs_dat_o[9]
+port 3457 nsew
+rlabel metal2 s 352222 18207 352222 18207 4 wbs_sel_i[0]
+port 3458 nsew
+rlabel metal3 s 348772 3536 348772 3536 4 wbs_sel_i[1]
+port 3459 nsew
+rlabel metal2 s 20654 3254 20654 3254 4 wbs_sel_i[2]
+port 3460 nsew
+rlabel metal2 s 25346 1979 25346 1979 4 wbs_sel_i[3]
+port 3461 nsew
+rlabel metal2 s 5290 1911 5290 1911 4 wbs_stb_i
+port 3462 nsew
+rlabel metal2 s 6486 1843 6486 1843 4 wbs_we_i
+port 3463 nsew
+rlabel metal2 s 427984 105815 427984 105815 4 xtal_clk
+port 3464 nsew
+flabel metal3 s 583520 285276 584960 285516 0 FreeSans 1200 0 0 0 analog_io[0]
+port 3465 nsew
+flabel metal2 s 446098 703520 446210 704960 0 FreeSans 560 90 0 0 analog_io[10]
+port 3466 nsew
+flabel metal2 s 381146 703520 381258 704960 0 FreeSans 560 90 0 0 analog_io[11]
+port 3467 nsew
+flabel metal2 s 316286 703520 316398 704960 0 FreeSans 560 90 0 0 analog_io[12]
+port 3468 nsew
+flabel metal2 s 251426 703520 251538 704960 0 FreeSans 560 90 0 0 analog_io[13]
+port 3469 nsew
+flabel metal2 s 186474 703520 186586 704960 0 FreeSans 560 90 0 0 analog_io[14]
+port 3470 nsew
+flabel metal2 s 121614 703520 121726 704960 0 FreeSans 560 90 0 0 analog_io[15]
+port 9 nsew
+flabel metal2 s 56754 703520 56866 704960 0 FreeSans 560 90 0 0 analog_io[16]
+port 10 nsew
+flabel metal3 s -960 697220 480 697460 0 FreeSans 1200 0 0 0 analog_io[17]
+port 11 nsew
+flabel metal3 s -960 644996 480 645236 0 FreeSans 1200 0 0 0 analog_io[18]
+port 12 nsew
+flabel metal3 s -960 592908 480 593148 0 FreeSans 1200 0 0 0 analog_io[19]
+port 3471 nsew
+flabel metal3 s 583520 338452 584960 338692 0 FreeSans 1200 0 0 0 analog_io[1]
+port 3472 nsew
+flabel metal3 s -960 540684 480 540924 0 FreeSans 1200 0 0 0 analog_io[20]
+port 3473 nsew
+flabel metal3 s -960 488596 480 488836 0 FreeSans 1200 0 0 0 analog_io[21]
+port 3474 nsew
+flabel metal3 s -960 436508 480 436748 0 FreeSans 1200 0 0 0 analog_io[22]
+port 3475 nsew
+flabel metal3 s -960 384284 480 384524 0 FreeSans 1200 0 0 0 analog_io[23]
+port 13 nsew
+flabel metal3 s -960 332196 480 332436 0 FreeSans 1200 0 0 0 analog_io[24]
+port 3476 nsew
+flabel metal3 s -960 279972 480 280212 0 FreeSans 1200 0 0 0 analog_io[25]
+port 3477 nsew
+flabel metal3 s -960 227884 480 228124 0 FreeSans 1200 0 0 0 analog_io[26]
+port 3478 nsew
+flabel metal3 s -960 175796 480 176036 0 FreeSans 1200 0 0 0 analog_io[27]
+port 3479 nsew
+flabel metal3 s -960 123572 480 123812 0 FreeSans 1200 0 0 0 analog_io[28]
+port 3480 nsew
+flabel metal3 s 583520 391628 584960 391868 0 FreeSans 1200 0 0 0 analog_io[2]
+port 3481 nsew
+flabel metal3 s 583520 444668 584960 444908 0 FreeSans 1200 0 0 0 analog_io[3]
+port 3482 nsew
+flabel metal3 s 583520 497844 584960 498084 0 FreeSans 1200 0 0 0 analog_io[4]
+port 3483 nsew
+flabel metal3 s 583520 551020 584960 551260 0 FreeSans 1200 0 0 0 analog_io[5]
+port 3484 nsew
+flabel metal3 s 583520 604060 584960 604300 0 FreeSans 1200 0 0 0 analog_io[6]
+port 3485 nsew
+flabel metal3 s 583520 657236 584960 657476 0 FreeSans 1200 0 0 0 analog_io[7]
+port 3486 nsew
+flabel metal2 s 575818 703520 575930 704960 0 FreeSans 560 90 0 0 analog_io[8]
+port 3487 nsew
+flabel metal2 s 510958 703520 511070 704960 0 FreeSans 560 90 0 0 analog_io[9]
+port 3488 nsew
+flabel metal3 s 583520 6476 584960 6716 0 FreeSans 1200 0 0 0 io_in[0]
+port 180 nsew
+flabel metal3 s 583520 457996 584960 458236 0 FreeSans 1200 0 0 0 io_in[10]
+port 181 nsew
+flabel metal3 s 583520 511172 584960 511412 0 FreeSans 1200 0 0 0 io_in[11]
+port 182 nsew
+flabel metal3 s 583520 564212 584960 564452 0 FreeSans 1200 0 0 0 io_in[12]
+port 183 nsew
+flabel metal3 s 583520 617388 584960 617628 0 FreeSans 1200 0 0 0 io_in[13]
+port 184 nsew
+flabel metal3 s 583520 670564 584960 670804 0 FreeSans 1200 0 0 0 io_in[14]
+port 185 nsew
+flabel metal2 s 559626 703520 559738 704960 0 FreeSans 560 90 0 0 io_in[15]
+port 186 nsew
+flabel metal2 s 494766 703520 494878 704960 0 FreeSans 560 90 0 0 io_in[16]
+port 187 nsew
+flabel metal2 s 429814 703520 429926 704960 0 FreeSans 560 90 0 0 io_in[17]
+port 188 nsew
+flabel metal2 s 364954 703520 365066 704960 0 FreeSans 560 90 0 0 io_in[18]
+port 189 nsew
+flabel metal2 s 300094 703520 300206 704960 0 FreeSans 560 90 0 0 io_in[19]
+port 190 nsew
+flabel metal3 s 583520 46188 584960 46428 0 FreeSans 1200 0 0 0 io_in[1]
+port 191 nsew
+flabel metal2 s 235142 703520 235254 704960 0 FreeSans 560 90 0 0 io_in[20]
+port 192 nsew
+flabel metal2 s 170282 703520 170394 704960 0 FreeSans 560 90 0 0 io_in[21]
+port 193 nsew
+flabel metal2 s 105422 703520 105534 704960 0 FreeSans 560 90 0 0 io_in[22]
+port 194 nsew
+flabel metal2 s 40470 703520 40582 704960 0 FreeSans 560 90 0 0 io_in[23]
+port 195 nsew
+flabel metal3 s -960 684164 480 684404 0 FreeSans 1200 0 0 0 io_in[24]
+port 196 nsew
+flabel metal3 s -960 631940 480 632180 0 FreeSans 1200 0 0 0 io_in[25]
+port 197 nsew
+flabel metal3 s -960 579852 480 580092 0 FreeSans 1200 0 0 0 io_in[26]
+port 198 nsew
+flabel metal3 s -960 527764 480 528004 0 FreeSans 1200 0 0 0 io_in[27]
+port 199 nsew
+flabel metal3 s -960 475540 480 475780 0 FreeSans 1200 0 0 0 io_in[28]
+port 200 nsew
+flabel metal3 s -960 423452 480 423692 0 FreeSans 1200 0 0 0 io_in[29]
+port 201 nsew
+flabel metal3 s 583520 86036 584960 86276 0 FreeSans 1200 0 0 0 io_in[2]
+port 202 nsew
+flabel metal3 s -960 371228 480 371468 0 FreeSans 1200 0 0 0 io_in[30]
+port 203 nsew
+flabel metal3 s -960 319140 480 319380 0 FreeSans 1200 0 0 0 io_in[31]
+port 204 nsew
+flabel metal3 s -240 267172 -240 267172 0 FreeSans 1200 0 0 0 io_in[32]
+port 205 nsew
+flabel metal3 s -960 214828 480 215068 0 FreeSans 1200 0 0 0 io_in[33]
+port 206 nsew
+flabel metal3 s -960 162740 480 162980 0 FreeSans 1200 0 0 0 io_in[34]
+port 207 nsew
+flabel metal3 s -960 110516 480 110756 0 FreeSans 1200 0 0 0 io_in[35]
+port 208 nsew
+flabel metal3 s -960 71484 480 71724 0 FreeSans 1200 0 0 0 io_in[36]
+port 209 nsew
+flabel metal3 s -960 32316 480 32556 0 FreeSans 1200 0 0 0 io_in[37]
+port 210 nsew
+flabel metal3 s 583520 125884 584960 126124 0 FreeSans 1200 0 0 0 io_in[3]
+port 211 nsew
+flabel metal3 s 583520 165732 584960 165972 0 FreeSans 1200 0 0 0 io_in[4]
+port 212 nsew
+flabel metal3 s 583520 205580 584960 205820 0 FreeSans 1200 0 0 0 io_in[5]
+port 213 nsew
+flabel metal3 s 583520 245428 584960 245668 0 FreeSans 1200 0 0 0 io_in[6]
+port 214 nsew
+flabel metal3 s 583520 298604 584960 298844 0 FreeSans 1200 0 0 0 io_in[7]
+port 215 nsew
+flabel metal3 s 583520 351780 584960 352020 0 FreeSans 1200 0 0 0 io_in[8]
+port 216 nsew
+flabel metal3 s 583520 404820 584960 405060 0 FreeSans 1200 0 0 0 io_in[9]
+port 217 nsew
+flabel metal3 s 583520 32996 584960 33236 0 FreeSans 1200 0 0 0 io_oeb[0]
+port 218 nsew
+flabel metal3 s 583520 484516 584960 484756 0 FreeSans 1200 0 0 0 io_oeb[10]
+port 219 nsew
+flabel metal3 s 583520 537692 584960 537932 0 FreeSans 1200 0 0 0 io_oeb[11]
+port 220 nsew
+flabel metal3 s 583520 590868 584960 591108 0 FreeSans 1200 0 0 0 io_oeb[12]
+port 221 nsew
+flabel metal3 s 583520 643908 584960 644148 0 FreeSans 1200 0 0 0 io_oeb[13]
+port 222 nsew
+flabel metal3 s 583520 697084 584960 697324 0 FreeSans 1200 0 0 0 io_oeb[14]
+port 223 nsew
+flabel metal2 s 527150 703520 527262 704960 0 FreeSans 560 90 0 0 io_oeb[15]
+port 224 nsew
+flabel metal2 s 462290 703520 462402 704960 0 FreeSans 560 90 0 0 io_oeb[16]
+port 225 nsew
+flabel metal2 s 397430 703520 397542 704960 0 FreeSans 560 90 0 0 io_oeb[17]
+port 226 nsew
+flabel metal2 s 332478 703520 332590 704960 0 FreeSans 560 90 0 0 io_oeb[18]
+port 227 nsew
+flabel metal2 s 267618 703520 267730 704960 0 FreeSans 560 90 0 0 io_oeb[19]
+port 228 nsew
+flabel metal3 s 583520 72844 584960 73084 0 FreeSans 1200 0 0 0 io_oeb[1]
+port 229 nsew
+flabel metal2 s 202758 703520 202870 704960 0 FreeSans 560 90 0 0 io_oeb[20]
+port 230 nsew
+flabel metal2 s 137806 703520 137918 704960 0 FreeSans 560 90 0 0 io_oeb[21]
+port 231 nsew
+flabel metal2 s 72946 703520 73058 704960 0 FreeSans 560 90 0 0 io_oeb[22]
+port 232 nsew
+flabel metal2 s 8086 703520 8198 704960 0 FreeSans 560 90 0 0 io_oeb[23]
+port 233 nsew
+flabel metal3 s -960 658052 480 658292 0 FreeSans 1200 0 0 0 io_oeb[24]
+port 234 nsew
+flabel metal3 s -960 605964 480 606204 0 FreeSans 1200 0 0 0 io_oeb[25]
+port 235 nsew
+flabel metal3 s -960 553740 480 553980 0 FreeSans 1200 0 0 0 io_oeb[26]
+port 236 nsew
+flabel metal3 s -960 501652 480 501892 0 FreeSans 1200 0 0 0 io_oeb[27]
+port 237 nsew
+flabel metal3 s -960 449428 480 449668 0 FreeSans 1200 0 0 0 io_oeb[28]
+port 238 nsew
+flabel metal3 s -960 397340 480 397580 0 FreeSans 1200 0 0 0 io_oeb[29]
+port 239 nsew
+flabel metal3 s 583520 112692 584960 112932 0 FreeSans 1200 0 0 0 io_oeb[2]
+port 240 nsew
+flabel metal3 s -960 345252 480 345492 0 FreeSans 1200 0 0 0 io_oeb[30]
+port 241 nsew
+flabel metal3 s -960 293028 480 293268 0 FreeSans 1200 0 0 0 io_oeb[31]
+port 242 nsew
+flabel metal3 s -960 240940 480 241180 0 FreeSans 1200 0 0 0 io_oeb[32]
+port 243 nsew
+flabel metal3 s -960 188716 480 188956 0 FreeSans 1200 0 0 0 io_oeb[33]
+port 244 nsew
+flabel metal3 s -960 136628 480 136868 0 FreeSans 1200 0 0 0 io_oeb[34]
+port 245 nsew
+flabel metal3 s -960 84540 480 84780 0 FreeSans 1200 0 0 0 io_oeb[35]
+port 246 nsew
+flabel metal3 s -960 45372 480 45612 0 FreeSans 1200 0 0 0 io_oeb[36]
+port 247 nsew
+flabel metal3 s -240 6460 -240 6460 0 FreeSans 1200 0 0 0 io_oeb[37]
+port 248 nsew
+flabel metal3 s 583520 152540 584960 152780 0 FreeSans 1200 0 0 0 io_oeb[3]
+port 249 nsew
+flabel metal3 s 583520 192388 584960 192628 0 FreeSans 1200 0 0 0 io_oeb[4]
+port 250 nsew
+flabel metal3 s 583520 232236 584960 232476 0 FreeSans 1200 0 0 0 io_oeb[5]
+port 251 nsew
+flabel metal3 s 583520 272084 584960 272324 0 FreeSans 1200 0 0 0 io_oeb[6]
+port 252 nsew
+flabel metal3 s 583520 325124 584960 325364 0 FreeSans 1200 0 0 0 io_oeb[7]
+port 253 nsew
+flabel metal3 s 583520 378300 584960 378540 0 FreeSans 1200 0 0 0 io_oeb[8]
+port 254 nsew
+flabel metal3 s 583520 431476 584960 431716 0 FreeSans 1200 0 0 0 io_oeb[9]
+port 255 nsew
+flabel metal3 s 583520 19668 584960 19908 0 FreeSans 1200 0 0 0 io_out[0]
+port 256 nsew
+flabel metal3 s 583520 471324 584960 471564 0 FreeSans 1200 0 0 0 io_out[10]
+port 257 nsew
+flabel metal3 s 583520 524364 584960 524604 0 FreeSans 1200 0 0 0 io_out[11]
+port 258 nsew
+flabel metal3 s 583520 577540 584960 577780 0 FreeSans 1200 0 0 0 io_out[12]
+port 259 nsew
+flabel metal3 s 583520 630716 584960 630956 0 FreeSans 1200 0 0 0 io_out[13]
+port 260 nsew
+flabel metal3 s 583520 683756 584960 683996 0 FreeSans 1200 0 0 0 io_out[14]
+port 261 nsew
+flabel metal2 s 543434 703520 543546 704960 0 FreeSans 560 90 0 0 io_out[15]
+port 262 nsew
+flabel metal2 s 478482 703520 478594 704960 0 FreeSans 560 90 0 0 io_out[16]
+port 263 nsew
+flabel metal2 s 413622 703520 413734 704960 0 FreeSans 560 90 0 0 io_out[17]
+port 264 nsew
+flabel metal2 s 348762 703520 348874 704960 0 FreeSans 560 90 0 0 io_out[18]
+port 265 nsew
+flabel metal2 s 283810 703520 283922 704960 0 FreeSans 560 90 0 0 io_out[19]
+port 266 nsew
+flabel metal3 s 583520 59516 584960 59756 0 FreeSans 1200 0 0 0 io_out[1]
+port 267 nsew
+flabel metal2 s 218950 703520 219062 704960 0 FreeSans 560 90 0 0 io_out[20]
+port 268 nsew
+flabel metal2 s 154090 703520 154202 704960 0 FreeSans 560 90 0 0 io_out[21]
+port 269 nsew
+flabel metal2 s 89138 703520 89250 704960 0 FreeSans 560 90 0 0 io_out[22]
+port 270 nsew
+flabel metal2 s 24278 703520 24390 704960 0 FreeSans 560 90 0 0 io_out[23]
+port 271 nsew
+flabel metal3 s -960 671108 480 671348 0 FreeSans 1200 0 0 0 io_out[24]
+port 272 nsew
+flabel metal3 s -960 619020 480 619260 0 FreeSans 1200 0 0 0 io_out[25]
+port 273 nsew
+flabel metal3 s -960 566796 480 567036 0 FreeSans 1200 0 0 0 io_out[26]
+port 274 nsew
+flabel metal3 s -960 514708 480 514948 0 FreeSans 1200 0 0 0 io_out[27]
+port 275 nsew
+flabel metal3 s -960 462484 480 462724 0 FreeSans 1200 0 0 0 io_out[28]
+port 276 nsew
+flabel metal3 s -960 410396 480 410636 0 FreeSans 1200 0 0 0 io_out[29]
+port 277 nsew
+flabel metal3 s 583520 99364 584960 99604 0 FreeSans 1200 0 0 0 io_out[2]
+port 278 nsew
+flabel metal3 s -960 358308 480 358548 0 FreeSans 1200 0 0 0 io_out[30]
+port 279 nsew
+flabel metal3 s -960 306084 480 306324 0 FreeSans 1200 0 0 0 io_out[31]
+port 280 nsew
+flabel metal3 s -960 253996 480 254236 0 FreeSans 1200 0 0 0 io_out[32]
+port 281 nsew
+flabel metal3 s -960 201772 480 202012 0 FreeSans 1200 0 0 0 io_out[33]
+port 282 nsew
+flabel metal3 s -960 149684 480 149924 0 FreeSans 1200 0 0 0 io_out[34]
+port 283 nsew
+flabel metal3 s -960 97460 480 97700 0 FreeSans 1200 0 0 0 io_out[35]
+port 284 nsew
+flabel metal3 s -960 58428 480 58668 0 FreeSans 1200 0 0 0 io_out[36]
+port 285 nsew
+flabel metal3 s -960 19260 480 19500 0 FreeSans 1200 0 0 0 io_out[37]
+port 286 nsew
+flabel metal3 s 583520 139212 584960 139452 0 FreeSans 1200 0 0 0 io_out[3]
+port 287 nsew
+flabel metal3 s 583520 179060 584960 179300 0 FreeSans 1200 0 0 0 io_out[4]
+port 288 nsew
+flabel metal3 s 583520 218908 584960 219148 0 FreeSans 1200 0 0 0 io_out[5]
+port 289 nsew
+flabel metal3 s 583520 258756 584960 258996 0 FreeSans 1200 0 0 0 io_out[6]
+port 290 nsew
+flabel metal3 s 583520 311932 584960 312172 0 FreeSans 1200 0 0 0 io_out[7]
+port 291 nsew
+flabel metal3 s 583520 364972 584960 365212 0 FreeSans 1200 0 0 0 io_out[8]
+port 292 nsew
+flabel metal3 s 583520 418148 584960 418388 0 FreeSans 1200 0 0 0 io_out[9]
+port 293 nsew
+flabel metal2 s 125846 -960 125958 480 0 FreeSans 560 90 0 0 la_data_in[0]
+port 326 nsew
+flabel metal2 s 480506 -960 480618 480 0 FreeSans 560 90 0 0 la_data_in[100]
+port 3489 nsew
+flabel metal2 s 484002 -960 484114 480 0 FreeSans 560 90 0 0 la_data_in[101]
+port 3490 nsew
+flabel metal2 s 487590 -960 487702 480 0 FreeSans 560 90 0 0 la_data_in[102]
+port 3491 nsew
+flabel metal2 s 491086 -960 491198 480 0 FreeSans 560 90 0 0 la_data_in[103]
+port 3492 nsew
+flabel metal2 s 494674 -960 494786 480 0 FreeSans 560 90 0 0 la_data_in[104]
+port 3493 nsew
+flabel metal2 s 498170 -960 498282 480 0 FreeSans 560 90 0 0 la_data_in[105]
+port 3494 nsew
+flabel metal2 s 501758 -960 501870 480 0 FreeSans 560 90 0 0 la_data_in[106]
+port 3495 nsew
+flabel metal2 s 505346 -960 505458 480 0 FreeSans 560 90 0 0 la_data_in[107]
+port 3496 nsew
+flabel metal2 s 508842 -960 508954 480 0 FreeSans 560 90 0 0 la_data_in[108]
+port 3497 nsew
+flabel metal2 s 512430 -960 512542 480 0 FreeSans 560 90 0 0 la_data_in[109]
+port 3498 nsew
+flabel metal2 s 161266 -960 161378 480 0 FreeSans 560 90 0 0 la_data_in[10]
+port 327 nsew
+flabel metal2 s 515926 -960 516038 480 0 FreeSans 560 90 0 0 la_data_in[110]
+port 3499 nsew
+flabel metal2 s 519514 -960 519626 480 0 FreeSans 560 90 0 0 la_data_in[111]
+port 3500 nsew
+flabel metal2 s 523010 -960 523122 480 0 FreeSans 560 90 0 0 la_data_in[112]
+port 3501 nsew
+flabel metal2 s 526598 -960 526710 480 0 FreeSans 560 90 0 0 la_data_in[113]
+port 3502 nsew
+flabel metal2 s 530094 -960 530206 480 0 FreeSans 560 90 0 0 la_data_in[114]
+port 3503 nsew
+flabel metal2 s 533682 -960 533794 480 0 FreeSans 560 90 0 0 la_data_in[115]
+port 3504 nsew
+flabel metal2 s 537178 -960 537290 480 0 FreeSans 560 90 0 0 la_data_in[116]
+port 3505 nsew
+flabel metal2 s 540766 -960 540878 480 0 FreeSans 560 90 0 0 la_data_in[117]
+port 3506 nsew
+flabel metal2 s 544354 -960 544466 480 0 FreeSans 560 90 0 0 la_data_in[118]
+port 3507 nsew
+flabel metal2 s 547850 -960 547962 480 0 FreeSans 560 90 0 0 la_data_in[119]
+port 3508 nsew
+flabel metal2 s 164854 -960 164966 480 0 FreeSans 560 90 0 0 la_data_in[11]
+port 328 nsew
+flabel metal2 s 551438 -960 551550 480 0 FreeSans 560 90 0 0 la_data_in[120]
+port 3509 nsew
+flabel metal2 s 554934 -960 555046 480 0 FreeSans 560 90 0 0 la_data_in[121]
+port 3510 nsew
+flabel metal2 s 558522 -960 558634 480 0 FreeSans 560 90 0 0 la_data_in[122]
+port 3511 nsew
+flabel metal2 s 562018 -960 562130 480 0 FreeSans 560 90 0 0 la_data_in[123]
+port 3512 nsew
+flabel metal2 s 565606 -960 565718 480 0 FreeSans 560 90 0 0 la_data_in[124]
+port 3513 nsew
+flabel metal2 s 569102 -960 569214 480 0 FreeSans 560 90 0 0 la_data_in[125]
+port 3514 nsew
+flabel metal2 s 572690 -960 572802 480 0 FreeSans 560 90 0 0 la_data_in[126]
+port 3515 nsew
+flabel metal2 s 576278 -960 576390 480 0 FreeSans 560 90 0 0 la_data_in[127]
+port 3516 nsew
+flabel metal2 s 168350 -960 168462 480 0 FreeSans 560 90 0 0 la_data_in[12]
+port 329 nsew
+flabel metal2 s 171938 -960 172050 480 0 FreeSans 560 90 0 0 la_data_in[13]
+port 330 nsew
+flabel metal2 s 175434 -960 175546 480 0 FreeSans 560 90 0 0 la_data_in[14]
+port 331 nsew
+flabel metal2 s 179022 -960 179134 480 0 FreeSans 560 90 0 0 la_data_in[15]
+port 332 nsew
+flabel metal2 s 182518 -960 182630 480 0 FreeSans 560 90 0 0 la_data_in[16]
+port 333 nsew
+flabel metal2 s 186106 -960 186218 480 0 FreeSans 560 90 0 0 la_data_in[17]
+port 334 nsew
+flabel metal2 s 189694 -960 189806 480 0 FreeSans 560 90 0 0 la_data_in[18]
+port 3517 nsew
+flabel metal2 s 193190 -960 193302 480 0 FreeSans 560 90 0 0 la_data_in[19]
+port 3518 nsew
+flabel metal2 s 129342 -960 129454 480 0 FreeSans 560 90 0 0 la_data_in[1]
+port 335 nsew
+flabel metal2 s 196778 -960 196890 480 0 FreeSans 560 90 0 0 la_data_in[20]
+port 3519 nsew
+flabel metal2 s 200274 -960 200386 480 0 FreeSans 560 90 0 0 la_data_in[21]
+port 3520 nsew
+flabel metal2 s 203862 -960 203974 480 0 FreeSans 560 90 0 0 la_data_in[22]
+port 3521 nsew
+flabel metal2 s 207358 -960 207470 480 0 FreeSans 560 90 0 0 la_data_in[23]
+port 3522 nsew
+flabel metal2 s 210946 -960 211058 480 0 FreeSans 560 90 0 0 la_data_in[24]
+port 3523 nsew
+flabel metal2 s 214442 -960 214554 480 0 FreeSans 560 90 0 0 la_data_in[25]
+port 3524 nsew
+flabel metal2 s 218030 -960 218142 480 0 FreeSans 560 90 0 0 la_data_in[26]
+port 3525 nsew
+flabel metal2 s 221526 -960 221638 480 0 FreeSans 560 90 0 0 la_data_in[27]
+port 3526 nsew
+flabel metal2 s 225114 -960 225226 480 0 FreeSans 560 90 0 0 la_data_in[28]
+port 3527 nsew
+flabel metal2 s 228702 -960 228814 480 0 FreeSans 560 90 0 0 la_data_in[29]
+port 3528 nsew
+flabel metal2 s 132930 -960 133042 480 0 FreeSans 560 90 0 0 la_data_in[2]
+port 336 nsew
+flabel metal2 s 232198 -960 232310 480 0 FreeSans 560 90 0 0 la_data_in[30]
+port 3529 nsew
+flabel metal2 s 235786 -960 235898 480 0 FreeSans 560 90 0 0 la_data_in[31]
+port 3530 nsew
+flabel metal2 s 239282 -960 239394 480 0 FreeSans 560 90 0 0 la_data_in[32]
+port 3531 nsew
+flabel metal2 s 242870 -960 242982 480 0 FreeSans 560 90 0 0 la_data_in[33]
+port 3532 nsew
+flabel metal2 s 246366 -960 246478 480 0 FreeSans 560 90 0 0 la_data_in[34]
+port 3533 nsew
+flabel metal2 s 249954 -960 250066 480 0 FreeSans 560 90 0 0 la_data_in[35]
+port 3534 nsew
+flabel metal2 s 253450 -960 253562 480 0 FreeSans 560 90 0 0 la_data_in[36]
+port 3535 nsew
+flabel metal2 s 257038 -960 257150 480 0 FreeSans 560 90 0 0 la_data_in[37]
+port 3536 nsew
+flabel metal2 s 260626 -960 260738 480 0 FreeSans 560 90 0 0 la_data_in[38]
+port 3537 nsew
+flabel metal2 s 264122 -960 264234 480 0 FreeSans 560 90 0 0 la_data_in[39]
+port 3538 nsew
+flabel metal2 s 136426 -960 136538 480 0 FreeSans 560 90 0 0 la_data_in[3]
+port 337 nsew
+flabel metal2 s 267710 -960 267822 480 0 FreeSans 560 90 0 0 la_data_in[40]
+port 3539 nsew
+flabel metal2 s 271206 -960 271318 480 0 FreeSans 560 90 0 0 la_data_in[41]
+port 3540 nsew
+flabel metal2 s 274794 -960 274906 480 0 FreeSans 560 90 0 0 la_data_in[42]
+port 3541 nsew
+flabel metal2 s 278290 -960 278402 480 0 FreeSans 560 90 0 0 la_data_in[43]
+port 3542 nsew
+flabel metal2 s 281878 -960 281990 480 0 FreeSans 560 90 0 0 la_data_in[44]
+port 3543 nsew
+flabel metal2 s 285374 -960 285486 480 0 FreeSans 560 90 0 0 la_data_in[45]
+port 3544 nsew
+flabel metal2 s 288962 -960 289074 480 0 FreeSans 560 90 0 0 la_data_in[46]
+port 3545 nsew
+flabel metal2 s 292550 -960 292662 480 0 FreeSans 560 90 0 0 la_data_in[47]
+port 3546 nsew
+flabel metal2 s 296046 -960 296158 480 0 FreeSans 560 90 0 0 la_data_in[48]
+port 3547 nsew
+flabel metal2 s 299634 -960 299746 480 0 FreeSans 560 90 0 0 la_data_in[49]
+port 3548 nsew
+flabel metal2 s 140014 -960 140126 480 0 FreeSans 560 90 0 0 la_data_in[4]
+port 338 nsew
+flabel metal2 s 303130 -960 303242 480 0 FreeSans 560 90 0 0 la_data_in[50]
+port 3549 nsew
+flabel metal2 s 306718 -960 306830 480 0 FreeSans 560 90 0 0 la_data_in[51]
+port 3550 nsew
+flabel metal2 s 310214 -960 310326 480 0 FreeSans 560 90 0 0 la_data_in[52]
+port 3551 nsew
+flabel metal2 s 313802 -960 313914 480 0 FreeSans 560 90 0 0 la_data_in[53]
+port 3552 nsew
+flabel metal2 s 317298 -960 317410 480 0 FreeSans 560 90 0 0 la_data_in[54]
+port 3553 nsew
+flabel metal2 s 320886 -960 320998 480 0 FreeSans 560 90 0 0 la_data_in[55]
+port 3554 nsew
+flabel metal2 s 324382 -960 324494 480 0 FreeSans 560 90 0 0 la_data_in[56]
+port 3555 nsew
+flabel metal2 s 327970 -960 328082 480 0 FreeSans 560 90 0 0 la_data_in[57]
+port 3556 nsew
+flabel metal2 s 331558 -960 331670 480 0 FreeSans 560 90 0 0 la_data_in[58]
+port 3557 nsew
+flabel metal2 s 335054 -960 335166 480 0 FreeSans 560 90 0 0 la_data_in[59]
+port 3558 nsew
+flabel metal2 s 143510 -960 143622 480 0 FreeSans 560 90 0 0 la_data_in[5]
+port 339 nsew
+flabel metal2 s 338642 -960 338754 480 0 FreeSans 560 90 0 0 la_data_in[60]
+port 3559 nsew
+flabel metal2 s 342138 -960 342250 480 0 FreeSans 560 90 0 0 la_data_in[61]
+port 3560 nsew
+flabel metal2 s 345726 -960 345838 480 0 FreeSans 560 90 0 0 la_data_in[62]
+port 3561 nsew
+flabel metal2 s 349222 -960 349334 480 0 FreeSans 560 90 0 0 la_data_in[63]
+port 3562 nsew
+flabel metal2 s 352810 -960 352922 480 0 FreeSans 560 90 0 0 la_data_in[64]
+port 3563 nsew
+flabel metal2 s 356306 -960 356418 480 0 FreeSans 560 90 0 0 la_data_in[65]
+port 3564 nsew
+flabel metal2 s 359894 -960 360006 480 0 FreeSans 560 90 0 0 la_data_in[66]
+port 3565 nsew
+flabel metal2 s 363482 -960 363594 480 0 FreeSans 560 90 0 0 la_data_in[67]
+port 3566 nsew
+flabel metal2 s 366978 -960 367090 480 0 FreeSans 560 90 0 0 la_data_in[68]
+port 3567 nsew
+flabel metal2 s 370566 -960 370678 480 0 FreeSans 560 90 0 0 la_data_in[69]
+port 3568 nsew
+flabel metal2 s 147098 -960 147210 480 0 FreeSans 560 90 0 0 la_data_in[6]
+port 340 nsew
+flabel metal2 s 374062 -960 374174 480 0 FreeSans 560 90 0 0 la_data_in[70]
+port 3569 nsew
+flabel metal2 s 377650 -960 377762 480 0 FreeSans 560 90 0 0 la_data_in[71]
+port 3570 nsew
+flabel metal2 s 381146 -960 381258 480 0 FreeSans 560 90 0 0 la_data_in[72]
+port 3571 nsew
+flabel metal2 s 384734 -960 384846 480 0 FreeSans 560 90 0 0 la_data_in[73]
+port 3572 nsew
+flabel metal2 s 388230 -960 388342 480 0 FreeSans 560 90 0 0 la_data_in[74]
+port 3573 nsew
+flabel metal2 s 391818 -960 391930 480 0 FreeSans 560 90 0 0 la_data_in[75]
+port 3574 nsew
+flabel metal2 s 395314 -960 395426 480 0 FreeSans 560 90 0 0 la_data_in[76]
+port 3575 nsew
+flabel metal2 s 398902 -960 399014 480 0 FreeSans 560 90 0 0 la_data_in[77]
+port 3576 nsew
+flabel metal2 s 402490 -960 402602 480 0 FreeSans 560 90 0 0 la_data_in[78]
+port 3577 nsew
+flabel metal2 s 405986 -960 406098 480 0 FreeSans 560 90 0 0 la_data_in[79]
+port 3578 nsew
+flabel metal2 s 150594 -960 150706 480 0 FreeSans 560 90 0 0 la_data_in[7]
+port 341 nsew
+flabel metal2 s 409574 -960 409686 480 0 FreeSans 560 90 0 0 la_data_in[80]
+port 3579 nsew
+flabel metal2 s 413070 -960 413182 480 0 FreeSans 560 90 0 0 la_data_in[81]
+port 3580 nsew
+flabel metal2 s 416658 -960 416770 480 0 FreeSans 560 90 0 0 la_data_in[82]
+port 3581 nsew
+flabel metal2 s 420154 -960 420266 480 0 FreeSans 560 90 0 0 la_data_in[83]
+port 3582 nsew
+flabel metal2 s 423742 -960 423854 480 0 FreeSans 560 90 0 0 la_data_in[84]
+port 3583 nsew
+flabel metal2 s 427238 -960 427350 480 0 FreeSans 560 90 0 0 la_data_in[85]
+port 3584 nsew
+flabel metal2 s 430826 -960 430938 480 0 FreeSans 560 90 0 0 la_data_in[86]
+port 3585 nsew
+flabel metal2 s 434414 -960 434526 480 0 FreeSans 560 90 0 0 la_data_in[87]
+port 3586 nsew
+flabel metal2 s 437910 -960 438022 480 0 FreeSans 560 90 0 0 la_data_in[88]
+port 3587 nsew
+flabel metal2 s 441498 -960 441610 480 0 FreeSans 560 90 0 0 la_data_in[89]
+port 3588 nsew
+flabel metal2 s 154182 -960 154294 480 0 FreeSans 560 90 0 0 la_data_in[8]
+port 342 nsew
+flabel metal2 s 444994 -960 445106 480 0 FreeSans 560 90 0 0 la_data_in[90]
+port 3589 nsew
+flabel metal2 s 448582 -960 448694 480 0 FreeSans 560 90 0 0 la_data_in[91]
+port 3590 nsew
+flabel metal2 s 452078 -960 452190 480 0 FreeSans 560 90 0 0 la_data_in[92]
+port 3591 nsew
+flabel metal2 s 455666 -960 455778 480 0 FreeSans 560 90 0 0 la_data_in[93]
+port 3592 nsew
+flabel metal2 s 459162 -960 459274 480 0 FreeSans 560 90 0 0 la_data_in[94]
+port 3593 nsew
+flabel metal2 s 462750 -960 462862 480 0 FreeSans 560 90 0 0 la_data_in[95]
+port 3594 nsew
+flabel metal2 s 466246 -960 466358 480 0 FreeSans 560 90 0 0 la_data_in[96]
+port 3595 nsew
+flabel metal2 s 469834 -960 469946 480 0 FreeSans 560 90 0 0 la_data_in[97]
+port 3596 nsew
+flabel metal2 s 473422 -960 473534 480 0 FreeSans 560 90 0 0 la_data_in[98]
+port 3597 nsew
+flabel metal2 s 476918 -960 477030 480 0 FreeSans 560 90 0 0 la_data_in[99]
+port 3598 nsew
+flabel metal2 s 157770 -960 157882 480 0 FreeSans 560 90 0 0 la_data_in[9]
+port 343 nsew
+flabel metal2 s 126950 -960 127062 480 0 FreeSans 560 90 0 0 la_data_out[0]
+port 344 nsew
+flabel metal2 s 481702 -960 481814 480 0 FreeSans 560 90 0 0 la_data_out[100]
+port 345 nsew
+flabel metal2 s 485198 -960 485310 480 0 FreeSans 560 90 0 0 la_data_out[101]
+port 346 nsew
+flabel metal2 s 488786 -960 488898 480 0 FreeSans 560 90 0 0 la_data_out[102]
+port 347 nsew
+flabel metal2 s 492282 -960 492394 480 0 FreeSans 560 90 0 0 la_data_out[103]
+port 348 nsew
+flabel metal2 s 495870 -960 495982 480 0 FreeSans 560 90 0 0 la_data_out[104]
+port 349 nsew
+flabel metal2 s 499366 -960 499478 480 0 FreeSans 560 90 0 0 la_data_out[105]
+port 350 nsew
+flabel metal2 s 502954 -960 503066 480 0 FreeSans 560 90 0 0 la_data_out[106]
+port 351 nsew
+flabel metal2 s 506450 -960 506562 480 0 FreeSans 560 90 0 0 la_data_out[107]
+port 352 nsew
+flabel metal2 s 510038 -960 510150 480 0 FreeSans 560 90 0 0 la_data_out[108]
+port 353 nsew
+flabel metal2 s 513534 -960 513646 480 0 FreeSans 560 90 0 0 la_data_out[109]
+port 354 nsew
+flabel metal2 s 162462 -960 162574 480 0 FreeSans 560 90 0 0 la_data_out[10]
+port 355 nsew
+flabel metal2 s 517122 -960 517234 480 0 FreeSans 560 90 0 0 la_data_out[110]
+port 356 nsew
+flabel metal2 s 520710 -960 520822 480 0 FreeSans 560 90 0 0 la_data_out[111]
+port 357 nsew
+flabel metal2 s 524206 -960 524318 480 0 FreeSans 560 90 0 0 la_data_out[112]
+port 358 nsew
+flabel metal2 s 527794 -960 527906 480 0 FreeSans 560 90 0 0 la_data_out[113]
+port 359 nsew
+flabel metal2 s 531290 -960 531402 480 0 FreeSans 560 90 0 0 la_data_out[114]
+port 360 nsew
+flabel metal2 s 534878 -960 534990 480 0 FreeSans 560 90 0 0 la_data_out[115]
+port 361 nsew
+flabel metal2 s 538374 -960 538486 480 0 FreeSans 560 90 0 0 la_data_out[116]
+port 362 nsew
+flabel metal2 s 541962 -960 542074 480 0 FreeSans 560 90 0 0 la_data_out[117]
+port 363 nsew
+flabel metal2 s 545458 -960 545570 480 0 FreeSans 560 90 0 0 la_data_out[118]
+port 364 nsew
+flabel metal2 s 549046 -960 549158 480 0 FreeSans 560 90 0 0 la_data_out[119]
+port 365 nsew
+flabel metal2 s 166050 -960 166162 480 0 FreeSans 560 90 0 0 la_data_out[11]
+port 366 nsew
+flabel metal2 s 552634 -960 552746 480 0 FreeSans 560 90 0 0 la_data_out[120]
+port 367 nsew
+flabel metal2 s 556130 -960 556242 480 0 FreeSans 560 90 0 0 la_data_out[121]
+port 368 nsew
+flabel metal2 s 559718 -960 559830 480 0 FreeSans 560 90 0 0 la_data_out[122]
+port 369 nsew
+flabel metal2 s 563214 -960 563326 480 0 FreeSans 560 90 0 0 la_data_out[123]
+port 370 nsew
+flabel metal2 s 566802 -960 566914 480 0 FreeSans 560 90 0 0 la_data_out[124]
+port 371 nsew
+flabel metal2 s 570298 -960 570410 480 0 FreeSans 560 90 0 0 la_data_out[125]
+port 372 nsew
+flabel metal2 s 573886 -960 573998 480 0 FreeSans 560 90 0 0 la_data_out[126]
+port 373 nsew
+flabel metal2 s 577382 -960 577494 480 0 FreeSans 560 90 0 0 la_data_out[127]
+port 374 nsew
+flabel metal2 s 169546 -960 169658 480 0 FreeSans 560 90 0 0 la_data_out[12]
+port 375 nsew
+flabel metal2 s 173134 -960 173246 480 0 FreeSans 560 90 0 0 la_data_out[13]
+port 376 nsew
+flabel metal2 s 176630 -960 176742 480 0 FreeSans 560 90 0 0 la_data_out[14]
+port 377 nsew
+flabel metal2 s 180218 -960 180330 480 0 FreeSans 560 90 0 0 la_data_out[15]
+port 378 nsew
+flabel metal2 s 183714 -960 183826 480 0 FreeSans 560 90 0 0 la_data_out[16]
+port 379 nsew
+flabel metal2 s 187302 -960 187414 480 0 FreeSans 560 90 0 0 la_data_out[17]
+port 380 nsew
+flabel metal2 s 190798 -960 190910 480 0 FreeSans 560 90 0 0 la_data_out[18]
+port 381 nsew
+flabel metal2 s 194386 -960 194498 480 0 FreeSans 560 90 0 0 la_data_out[19]
+port 382 nsew
+flabel metal2 s 130538 -960 130650 480 0 FreeSans 560 90 0 0 la_data_out[1]
+port 383 nsew
+flabel metal2 s 197882 -960 197994 480 0 FreeSans 560 90 0 0 la_data_out[20]
+port 384 nsew
+flabel metal2 s 201470 -960 201582 480 0 FreeSans 560 90 0 0 la_data_out[21]
+port 385 nsew
+flabel metal2 s 205058 -960 205170 480 0 FreeSans 560 90 0 0 la_data_out[22]
+port 386 nsew
+flabel metal2 s 208554 -960 208666 480 0 FreeSans 560 90 0 0 la_data_out[23]
+port 387 nsew
+flabel metal2 s 212142 -960 212254 480 0 FreeSans 560 90 0 0 la_data_out[24]
+port 388 nsew
+flabel metal2 s 215638 -960 215750 480 0 FreeSans 560 90 0 0 la_data_out[25]
+port 389 nsew
+flabel metal2 s 219226 -960 219338 480 0 FreeSans 560 90 0 0 la_data_out[26]
+port 390 nsew
+flabel metal2 s 222722 -960 222834 480 0 FreeSans 560 90 0 0 la_data_out[27]
+port 391 nsew
+flabel metal2 s 226310 -960 226422 480 0 FreeSans 560 90 0 0 la_data_out[28]
+port 392 nsew
+flabel metal2 s 229806 -960 229918 480 0 FreeSans 560 90 0 0 la_data_out[29]
+port 393 nsew
+flabel metal2 s 134126 -960 134238 480 0 FreeSans 560 90 0 0 la_data_out[2]
+port 394 nsew
+flabel metal2 s 233394 -960 233506 480 0 FreeSans 560 90 0 0 la_data_out[30]
+port 395 nsew
+flabel metal2 s 236982 -960 237094 480 0 FreeSans 560 90 0 0 la_data_out[31]
+port 396 nsew
+flabel metal2 s 240478 -960 240590 480 0 FreeSans 560 90 0 0 la_data_out[32]
+port 397 nsew
+flabel metal2 s 244066 -960 244178 480 0 FreeSans 560 90 0 0 la_data_out[33]
+port 398 nsew
+flabel metal2 s 247562 -960 247674 480 0 FreeSans 560 90 0 0 la_data_out[34]
+port 399 nsew
+flabel metal2 s 251150 -960 251262 480 0 FreeSans 560 90 0 0 la_data_out[35]
+port 400 nsew
+flabel metal2 s 254646 -960 254758 480 0 FreeSans 560 90 0 0 la_data_out[36]
+port 401 nsew
+flabel metal2 s 258234 -960 258346 480 0 FreeSans 560 90 0 0 la_data_out[37]
+port 402 nsew
+flabel metal2 s 261730 -960 261842 480 0 FreeSans 560 90 0 0 la_data_out[38]
+port 403 nsew
+flabel metal2 s 265318 -960 265430 480 0 FreeSans 560 90 0 0 la_data_out[39]
+port 404 nsew
+flabel metal2 s 137622 -960 137734 480 0 FreeSans 560 90 0 0 la_data_out[3]
+port 405 nsew
+flabel metal2 s 268814 -960 268926 480 0 FreeSans 560 90 0 0 la_data_out[40]
+port 406 nsew
+flabel metal2 s 272402 -960 272514 480 0 FreeSans 560 90 0 0 la_data_out[41]
+port 407 nsew
+flabel metal2 s 275990 -960 276102 480 0 FreeSans 560 90 0 0 la_data_out[42]
+port 408 nsew
+flabel metal2 s 279486 -960 279598 480 0 FreeSans 560 90 0 0 la_data_out[43]
+port 409 nsew
+flabel metal2 s 283074 -960 283186 480 0 FreeSans 560 90 0 0 la_data_out[44]
+port 410 nsew
+flabel metal2 s 286570 -960 286682 480 0 FreeSans 560 90 0 0 la_data_out[45]
+port 411 nsew
+flabel metal2 s 290158 -960 290270 480 0 FreeSans 560 90 0 0 la_data_out[46]
+port 412 nsew
+flabel metal2 s 293654 -960 293766 480 0 FreeSans 560 90 0 0 la_data_out[47]
+port 413 nsew
+flabel metal2 s 297242 -960 297354 480 0 FreeSans 560 90 0 0 la_data_out[48]
+port 414 nsew
+flabel metal2 s 300738 -960 300850 480 0 FreeSans 560 90 0 0 la_data_out[49]
+port 415 nsew
+flabel metal2 s 141210 -960 141322 480 0 FreeSans 560 90 0 0 la_data_out[4]
+port 416 nsew
+flabel metal2 s 304326 -960 304438 480 0 FreeSans 560 90 0 0 la_data_out[50]
+port 417 nsew
+flabel metal2 s 307914 -960 308026 480 0 FreeSans 560 90 0 0 la_data_out[51]
+port 418 nsew
+flabel metal2 s 311410 -960 311522 480 0 FreeSans 560 90 0 0 la_data_out[52]
+port 419 nsew
+flabel metal2 s 314998 -960 315110 480 0 FreeSans 560 90 0 0 la_data_out[53]
+port 420 nsew
+flabel metal2 s 318494 -960 318606 480 0 FreeSans 560 90 0 0 la_data_out[54]
+port 421 nsew
+flabel metal2 s 322082 -960 322194 480 0 FreeSans 560 90 0 0 la_data_out[55]
+port 422 nsew
+flabel metal2 s 325578 -960 325690 480 0 FreeSans 560 90 0 0 la_data_out[56]
+port 423 nsew
+flabel metal2 s 329166 -960 329278 480 0 FreeSans 560 90 0 0 la_data_out[57]
+port 424 nsew
+flabel metal2 s 332662 -960 332774 480 0 FreeSans 560 90 0 0 la_data_out[58]
+port 425 nsew
+flabel metal2 s 336250 -960 336362 480 0 FreeSans 560 90 0 0 la_data_out[59]
+port 426 nsew
+flabel metal2 s 144706 -960 144818 480 0 FreeSans 560 90 0 0 la_data_out[5]
+port 427 nsew
+flabel metal2 s 339838 -960 339950 480 0 FreeSans 560 90 0 0 la_data_out[60]
+port 428 nsew
+flabel metal2 s 343334 -960 343446 480 0 FreeSans 560 90 0 0 la_data_out[61]
+port 429 nsew
+flabel metal2 s 346922 -960 347034 480 0 FreeSans 560 90 0 0 la_data_out[62]
+port 430 nsew
+flabel metal2 s 350418 -960 350530 480 0 FreeSans 560 90 0 0 la_data_out[63]
+port 431 nsew
+flabel metal2 s 354006 -960 354118 480 0 FreeSans 560 90 0 0 la_data_out[64]
+port 432 nsew
+flabel metal2 s 357502 -960 357614 480 0 FreeSans 560 90 0 0 la_data_out[65]
+port 433 nsew
+flabel metal2 s 361090 -960 361202 480 0 FreeSans 560 90 0 0 la_data_out[66]
+port 434 nsew
+flabel metal2 s 364586 -960 364698 480 0 FreeSans 560 90 0 0 la_data_out[67]
+port 435 nsew
+flabel metal2 s 368174 -960 368286 480 0 FreeSans 560 90 0 0 la_data_out[68]
+port 436 nsew
+flabel metal2 s 371670 -960 371782 480 0 FreeSans 560 90 0 0 la_data_out[69]
+port 437 nsew
+flabel metal2 s 148294 -960 148406 480 0 FreeSans 560 90 0 0 la_data_out[6]
+port 438 nsew
+flabel metal2 s 375258 -960 375370 480 0 FreeSans 560 90 0 0 la_data_out[70]
+port 439 nsew
+flabel metal2 s 378846 -960 378958 480 0 FreeSans 560 90 0 0 la_data_out[71]
+port 440 nsew
+flabel metal2 s 382342 -960 382454 480 0 FreeSans 560 90 0 0 la_data_out[72]
+port 441 nsew
+flabel metal2 s 385930 -960 386042 480 0 FreeSans 560 90 0 0 la_data_out[73]
+port 442 nsew
+flabel metal2 s 389426 -960 389538 480 0 FreeSans 560 90 0 0 la_data_out[74]
+port 443 nsew
+flabel metal2 s 393014 -960 393126 480 0 FreeSans 560 90 0 0 la_data_out[75]
+port 444 nsew
+flabel metal2 s 396510 -960 396622 480 0 FreeSans 560 90 0 0 la_data_out[76]
+port 445 nsew
+flabel metal2 s 400098 -960 400210 480 0 FreeSans 560 90 0 0 la_data_out[77]
+port 446 nsew
+flabel metal2 s 403594 -960 403706 480 0 FreeSans 560 90 0 0 la_data_out[78]
+port 447 nsew
+flabel metal2 s 407182 -960 407294 480 0 FreeSans 560 90 0 0 la_data_out[79]
+port 448 nsew
+flabel metal2 s 151790 -960 151902 480 0 FreeSans 560 90 0 0 la_data_out[7]
+port 449 nsew
+flabel metal2 s 410770 -960 410882 480 0 FreeSans 560 90 0 0 la_data_out[80]
+port 450 nsew
+flabel metal2 s 414266 -960 414378 480 0 FreeSans 560 90 0 0 la_data_out[81]
+port 451 nsew
+flabel metal2 s 417854 -960 417966 480 0 FreeSans 560 90 0 0 la_data_out[82]
+port 452 nsew
+flabel metal2 s 421350 -960 421462 480 0 FreeSans 560 90 0 0 la_data_out[83]
+port 453 nsew
+flabel metal2 s 424938 -960 425050 480 0 FreeSans 560 90 0 0 la_data_out[84]
+port 454 nsew
+flabel metal2 s 428434 -960 428546 480 0 FreeSans 560 90 0 0 la_data_out[85]
+port 455 nsew
+flabel metal2 s 432022 -960 432134 480 0 FreeSans 560 90 0 0 la_data_out[86]
+port 456 nsew
+flabel metal2 s 435518 -960 435630 480 0 FreeSans 560 90 0 0 la_data_out[87]
+port 457 nsew
+flabel metal2 s 439106 -960 439218 480 0 FreeSans 560 90 0 0 la_data_out[88]
+port 458 nsew
+flabel metal2 s 442602 -960 442714 480 0 FreeSans 560 90 0 0 la_data_out[89]
+port 459 nsew
+flabel metal2 s 155378 -960 155490 480 0 FreeSans 560 90 0 0 la_data_out[8]
+port 460 nsew
+flabel metal2 s 446190 -960 446302 480 0 FreeSans 560 90 0 0 la_data_out[90]
+port 461 nsew
+flabel metal2 s 449778 -960 449890 480 0 FreeSans 560 90 0 0 la_data_out[91]
+port 462 nsew
+flabel metal2 s 453274 -960 453386 480 0 FreeSans 560 90 0 0 la_data_out[92]
+port 463 nsew
+flabel metal2 s 456862 -960 456974 480 0 FreeSans 560 90 0 0 la_data_out[93]
+port 464 nsew
+flabel metal2 s 460358 -960 460470 480 0 FreeSans 560 90 0 0 la_data_out[94]
+port 465 nsew
+flabel metal2 s 463946 -960 464058 480 0 FreeSans 560 90 0 0 la_data_out[95]
+port 466 nsew
+flabel metal2 s 467442 -960 467554 480 0 FreeSans 560 90 0 0 la_data_out[96]
+port 467 nsew
+flabel metal2 s 471030 -960 471142 480 0 FreeSans 560 90 0 0 la_data_out[97]
+port 468 nsew
+flabel metal2 s 474526 -960 474638 480 0 FreeSans 560 90 0 0 la_data_out[98]
+port 469 nsew
+flabel metal2 s 478114 -960 478226 480 0 FreeSans 560 90 0 0 la_data_out[99]
+port 470 nsew
+flabel metal2 s 158874 -960 158986 480 0 FreeSans 560 90 0 0 la_data_out[9]
+port 471 nsew
+flabel metal2 s 128146 -960 128258 480 0 FreeSans 560 90 0 0 la_oenb[0]
+port 3599 nsew
+flabel metal2 s 482806 -960 482918 480 0 FreeSans 560 90 0 0 la_oenb[100]
+port 3600 nsew
+flabel metal2 s 486394 -960 486506 480 0 FreeSans 560 90 0 0 la_oenb[101]
+port 3601 nsew
+flabel metal2 s 489890 -960 490002 480 0 FreeSans 560 90 0 0 la_oenb[102]
+port 3602 nsew
+flabel metal2 s 493478 -960 493590 480 0 FreeSans 560 90 0 0 la_oenb[103]
+port 3603 nsew
+flabel metal2 s 497066 -960 497178 480 0 FreeSans 560 90 0 0 la_oenb[104]
+port 3604 nsew
+flabel metal2 s 500562 -960 500674 480 0 FreeSans 560 90 0 0 la_oenb[105]
+port 3605 nsew
+flabel metal2 s 504150 -960 504262 480 0 FreeSans 560 90 0 0 la_oenb[106]
+port 3606 nsew
+flabel metal2 s 507646 -960 507758 480 0 FreeSans 560 90 0 0 la_oenb[107]
+port 3607 nsew
+flabel metal2 s 511234 -960 511346 480 0 FreeSans 560 90 0 0 la_oenb[108]
+port 3608 nsew
+flabel metal2 s 514730 -960 514842 480 0 FreeSans 560 90 0 0 la_oenb[109]
+port 3609 nsew
+flabel metal2 s 163658 -960 163770 480 0 FreeSans 560 90 0 0 la_oenb[10]
+port 3610 nsew
+flabel metal2 s 518318 -960 518430 480 0 FreeSans 560 90 0 0 la_oenb[110]
+port 3611 nsew
+flabel metal2 s 521814 -960 521926 480 0 FreeSans 560 90 0 0 la_oenb[111]
+port 3612 nsew
+flabel metal2 s 525402 -960 525514 480 0 FreeSans 560 90 0 0 la_oenb[112]
+port 3613 nsew
+flabel metal2 s 528990 -960 529102 480 0 FreeSans 560 90 0 0 la_oenb[113]
+port 3614 nsew
+flabel metal2 s 532486 -960 532598 480 0 FreeSans 560 90 0 0 la_oenb[114]
+port 3615 nsew
+flabel metal2 s 536074 -960 536186 480 0 FreeSans 560 90 0 0 la_oenb[115]
+port 3616 nsew
+flabel metal2 s 539570 -960 539682 480 0 FreeSans 560 90 0 0 la_oenb[116]
+port 3617 nsew
+flabel metal2 s 543158 -960 543270 480 0 FreeSans 560 90 0 0 la_oenb[117]
+port 3618 nsew
+flabel metal2 s 546654 -960 546766 480 0 FreeSans 560 90 0 0 la_oenb[118]
+port 3619 nsew
+flabel metal2 s 550242 -960 550354 480 0 FreeSans 560 90 0 0 la_oenb[119]
+port 3620 nsew
+flabel metal2 s 167154 -960 167266 480 0 FreeSans 560 90 0 0 la_oenb[11]
+port 3621 nsew
+flabel metal2 s 553738 -960 553850 480 0 FreeSans 560 90 0 0 la_oenb[120]
+port 3622 nsew
+flabel metal2 s 557326 -960 557438 480 0 FreeSans 560 90 0 0 la_oenb[121]
+port 3623 nsew
+flabel metal2 s 560822 -960 560934 480 0 FreeSans 560 90 0 0 la_oenb[122]
+port 3624 nsew
+flabel metal2 s 564410 -960 564522 480 0 FreeSans 560 90 0 0 la_oenb[123]
+port 3625 nsew
+flabel metal2 s 567998 -960 568110 480 0 FreeSans 560 90 0 0 la_oenb[124]
+port 3626 nsew
+flabel metal2 s 571494 -960 571606 480 0 FreeSans 560 90 0 0 la_oenb[125]
+port 3627 nsew
+flabel metal2 s 575082 -960 575194 480 0 FreeSans 560 90 0 0 la_oenb[126]
+port 3628 nsew
+flabel metal2 s 578578 -960 578690 480 0 FreeSans 560 90 0 0 la_oenb[127]
+port 3629 nsew
+flabel metal2 s 170742 -960 170854 480 0 FreeSans 560 90 0 0 la_oenb[12]
+port 3630 nsew
+flabel metal2 s 174238 -960 174350 480 0 FreeSans 560 90 0 0 la_oenb[13]
+port 3631 nsew
+flabel metal2 s 177826 -960 177938 480 0 FreeSans 560 90 0 0 la_oenb[14]
+port 3632 nsew
+flabel metal2 s 181414 -960 181526 480 0 FreeSans 560 90 0 0 la_oenb[15]
+port 3633 nsew
+flabel metal2 s 184910 -960 185022 480 0 FreeSans 560 90 0 0 la_oenb[16]
+port 3634 nsew
+flabel metal2 s 188498 -960 188610 480 0 FreeSans 560 90 0 0 la_oenb[17]
+port 3635 nsew
+flabel metal2 s 191994 -960 192106 480 0 FreeSans 560 90 0 0 la_oenb[18]
+port 3636 nsew
+flabel metal2 s 195582 -960 195694 480 0 FreeSans 560 90 0 0 la_oenb[19]
+port 3637 nsew
+flabel metal2 s 131734 -960 131846 480 0 FreeSans 560 90 0 0 la_oenb[1]
+port 3638 nsew
+flabel metal2 s 199078 -960 199190 480 0 FreeSans 560 90 0 0 la_oenb[20]
+port 3639 nsew
+flabel metal2 s 202666 -960 202778 480 0 FreeSans 560 90 0 0 la_oenb[21]
+port 3640 nsew
+flabel metal2 s 206162 -960 206274 480 0 FreeSans 560 90 0 0 la_oenb[22]
+port 3641 nsew
+flabel metal2 s 209750 -960 209862 480 0 FreeSans 560 90 0 0 la_oenb[23]
+port 3642 nsew
+flabel metal2 s 213338 -960 213450 480 0 FreeSans 560 90 0 0 la_oenb[24]
+port 3643 nsew
+flabel metal2 s 216834 -960 216946 480 0 FreeSans 560 90 0 0 la_oenb[25]
+port 3644 nsew
+flabel metal2 s 220422 -960 220534 480 0 FreeSans 560 90 0 0 la_oenb[26]
+port 3645 nsew
+flabel metal2 s 223918 -960 224030 480 0 FreeSans 560 90 0 0 la_oenb[27]
+port 3646 nsew
+flabel metal2 s 227506 -960 227618 480 0 FreeSans 560 90 0 0 la_oenb[28]
+port 3647 nsew
+flabel metal2 s 231002 -960 231114 480 0 FreeSans 560 90 0 0 la_oenb[29]
+port 3648 nsew
+flabel metal2 s 135230 -960 135342 480 0 FreeSans 560 90 0 0 la_oenb[2]
+port 3649 nsew
+flabel metal2 s 234590 -960 234702 480 0 FreeSans 560 90 0 0 la_oenb[30]
+port 3650 nsew
+flabel metal2 s 238086 -960 238198 480 0 FreeSans 560 90 0 0 la_oenb[31]
+port 3651 nsew
+flabel metal2 s 241674 -960 241786 480 0 FreeSans 560 90 0 0 la_oenb[32]
+port 3652 nsew
+flabel metal2 s 245170 -960 245282 480 0 FreeSans 560 90 0 0 la_oenb[33]
+port 3653 nsew
+flabel metal2 s 248758 -960 248870 480 0 FreeSans 560 90 0 0 la_oenb[34]
+port 3654 nsew
+flabel metal2 s 252346 -960 252458 480 0 FreeSans 560 90 0 0 la_oenb[35]
+port 3655 nsew
+flabel metal2 s 255842 -960 255954 480 0 FreeSans 560 90 0 0 la_oenb[36]
+port 3656 nsew
+flabel metal2 s 259430 -960 259542 480 0 FreeSans 560 90 0 0 la_oenb[37]
+port 3657 nsew
+flabel metal2 s 262926 -960 263038 480 0 FreeSans 560 90 0 0 la_oenb[38]
+port 3658 nsew
+flabel metal2 s 266514 -960 266626 480 0 FreeSans 560 90 0 0 la_oenb[39]
+port 3659 nsew
+flabel metal2 s 138818 -960 138930 480 0 FreeSans 560 90 0 0 la_oenb[3]
+port 3660 nsew
+flabel metal2 s 270010 -960 270122 480 0 FreeSans 560 90 0 0 la_oenb[40]
+port 3661 nsew
+flabel metal2 s 273598 -960 273710 480 0 FreeSans 560 90 0 0 la_oenb[41]
+port 3662 nsew
+flabel metal2 s 277094 -960 277206 480 0 FreeSans 560 90 0 0 la_oenb[42]
+port 3663 nsew
+flabel metal2 s 280682 -960 280794 480 0 FreeSans 560 90 0 0 la_oenb[43]
+port 3664 nsew
+flabel metal2 s 284270 -960 284382 480 0 FreeSans 560 90 0 0 la_oenb[44]
+port 3665 nsew
+flabel metal2 s 287766 -960 287878 480 0 FreeSans 560 90 0 0 la_oenb[45]
+port 3666 nsew
+flabel metal2 s 291354 -960 291466 480 0 FreeSans 560 90 0 0 la_oenb[46]
+port 3667 nsew
+flabel metal2 s 294850 -960 294962 480 0 FreeSans 560 90 0 0 la_oenb[47]
+port 3668 nsew
+flabel metal2 s 298438 -960 298550 480 0 FreeSans 560 90 0 0 la_oenb[48]
+port 3669 nsew
+flabel metal2 s 301934 -960 302046 480 0 FreeSans 560 90 0 0 la_oenb[49]
+port 3670 nsew
+flabel metal2 s 142406 -960 142518 480 0 FreeSans 560 90 0 0 la_oenb[4]
+port 3671 nsew
+flabel metal2 s 305522 -960 305634 480 0 FreeSans 560 90 0 0 la_oenb[50]
+port 3672 nsew
+flabel metal2 s 309018 -960 309130 480 0 FreeSans 560 90 0 0 la_oenb[51]
+port 3673 nsew
+flabel metal2 s 312606 -960 312718 480 0 FreeSans 560 90 0 0 la_oenb[52]
+port 3674 nsew
+flabel metal2 s 316194 -960 316306 480 0 FreeSans 560 90 0 0 la_oenb[53]
+port 3675 nsew
+flabel metal2 s 319690 -960 319802 480 0 FreeSans 560 90 0 0 la_oenb[54]
+port 3676 nsew
+flabel metal2 s 323278 -960 323390 480 0 FreeSans 560 90 0 0 la_oenb[55]
+port 3677 nsew
+flabel metal2 s 326774 -960 326886 480 0 FreeSans 560 90 0 0 la_oenb[56]
+port 3678 nsew
+flabel metal2 s 330362 -960 330474 480 0 FreeSans 560 90 0 0 la_oenb[57]
+port 3679 nsew
+flabel metal2 s 333858 -960 333970 480 0 FreeSans 560 90 0 0 la_oenb[58]
+port 3680 nsew
+flabel metal2 s 337446 -960 337558 480 0 FreeSans 560 90 0 0 la_oenb[59]
+port 3681 nsew
+flabel metal2 s 145902 -960 146014 480 0 FreeSans 560 90 0 0 la_oenb[5]
+port 3682 nsew
+flabel metal2 s 340942 -960 341054 480 0 FreeSans 560 90 0 0 la_oenb[60]
+port 3683 nsew
+flabel metal2 s 344530 -960 344642 480 0 FreeSans 560 90 0 0 la_oenb[61]
+port 3684 nsew
+flabel metal2 s 348026 -960 348138 480 0 FreeSans 560 90 0 0 la_oenb[62]
+port 3685 nsew
+flabel metal2 s 351614 -960 351726 480 0 FreeSans 560 90 0 0 la_oenb[63]
+port 3686 nsew
+flabel metal2 s 355202 -960 355314 480 0 FreeSans 560 90 0 0 la_oenb[64]
+port 3687 nsew
+flabel metal2 s 358698 -960 358810 480 0 FreeSans 560 90 0 0 la_oenb[65]
+port 3688 nsew
+flabel metal2 s 362286 -960 362398 480 0 FreeSans 560 90 0 0 la_oenb[66]
+port 3689 nsew
+flabel metal2 s 365782 -960 365894 480 0 FreeSans 560 90 0 0 la_oenb[67]
+port 3690 nsew
+flabel metal2 s 369370 -960 369482 480 0 FreeSans 560 90 0 0 la_oenb[68]
+port 3691 nsew
+flabel metal2 s 372866 -960 372978 480 0 FreeSans 560 90 0 0 la_oenb[69]
+port 3692 nsew
+flabel metal2 s 149490 -960 149602 480 0 FreeSans 560 90 0 0 la_oenb[6]
+port 3693 nsew
+flabel metal2 s 376454 -960 376566 480 0 FreeSans 560 90 0 0 la_oenb[70]
+port 3694 nsew
+flabel metal2 s 379950 -960 380062 480 0 FreeSans 560 90 0 0 la_oenb[71]
+port 3695 nsew
+flabel metal2 s 383538 -960 383650 480 0 FreeSans 560 90 0 0 la_oenb[72]
+port 3696 nsew
+flabel metal2 s 387126 -960 387238 480 0 FreeSans 560 90 0 0 la_oenb[73]
+port 3697 nsew
+flabel metal2 s 390622 -960 390734 480 0 FreeSans 560 90 0 0 la_oenb[74]
+port 3698 nsew
+flabel metal2 s 394210 -960 394322 480 0 FreeSans 560 90 0 0 la_oenb[75]
+port 3699 nsew
+flabel metal2 s 397706 -960 397818 480 0 FreeSans 560 90 0 0 la_oenb[76]
+port 3700 nsew
+flabel metal2 s 401294 -960 401406 480 0 FreeSans 560 90 0 0 la_oenb[77]
+port 3701 nsew
+flabel metal2 s 404790 -960 404902 480 0 FreeSans 560 90 0 0 la_oenb[78]
+port 3702 nsew
+flabel metal2 s 408378 -960 408490 480 0 FreeSans 560 90 0 0 la_oenb[79]
+port 3703 nsew
+flabel metal2 s 152986 -960 153098 480 0 FreeSans 560 90 0 0 la_oenb[7]
+port 3704 nsew
+flabel metal2 s 411874 -960 411986 480 0 FreeSans 560 90 0 0 la_oenb[80]
+port 3705 nsew
+flabel metal2 s 415462 -960 415574 480 0 FreeSans 560 90 0 0 la_oenb[81]
+port 3706 nsew
+flabel metal2 s 418958 -960 419070 480 0 FreeSans 560 90 0 0 la_oenb[82]
+port 3707 nsew
+flabel metal2 s 422546 -960 422658 480 0 FreeSans 560 90 0 0 la_oenb[83]
+port 3708 nsew
+flabel metal2 s 426134 -960 426246 480 0 FreeSans 560 90 0 0 la_oenb[84]
+port 3709 nsew
+flabel metal2 s 429630 -960 429742 480 0 FreeSans 560 90 0 0 la_oenb[85]
+port 3710 nsew
+flabel metal2 s 433218 -960 433330 480 0 FreeSans 560 90 0 0 la_oenb[86]
+port 3711 nsew
+flabel metal2 s 436714 -960 436826 480 0 FreeSans 560 90 0 0 la_oenb[87]
+port 3712 nsew
+flabel metal2 s 440302 -960 440414 480 0 FreeSans 560 90 0 0 la_oenb[88]
+port 3713 nsew
+flabel metal2 s 443798 -960 443910 480 0 FreeSans 560 90 0 0 la_oenb[89]
+port 3714 nsew
+flabel metal2 s 156574 -960 156686 480 0 FreeSans 560 90 0 0 la_oenb[8]
+port 3715 nsew
+flabel metal2 s 447386 -960 447498 480 0 FreeSans 560 90 0 0 la_oenb[90]
+port 3716 nsew
+flabel metal2 s 450882 -960 450994 480 0 FreeSans 560 90 0 0 la_oenb[91]
+port 3717 nsew
+flabel metal2 s 454470 -960 454582 480 0 FreeSans 560 90 0 0 la_oenb[92]
+port 3718 nsew
+flabel metal2 s 458058 -960 458170 480 0 FreeSans 560 90 0 0 la_oenb[93]
+port 3719 nsew
+flabel metal2 s 461554 -960 461666 480 0 FreeSans 560 90 0 0 la_oenb[94]
+port 3720 nsew
+flabel metal2 s 465142 -960 465254 480 0 FreeSans 560 90 0 0 la_oenb[95]
+port 3721 nsew
+flabel metal2 s 468638 -960 468750 480 0 FreeSans 560 90 0 0 la_oenb[96]
+port 3722 nsew
+flabel metal2 s 472226 -960 472338 480 0 FreeSans 560 90 0 0 la_oenb[97]
+port 3723 nsew
+flabel metal2 s 475722 -960 475834 480 0 FreeSans 560 90 0 0 la_oenb[98]
+port 3724 nsew
+flabel metal2 s 479310 -960 479422 480 0 FreeSans 560 90 0 0 la_oenb[99]
+port 3725 nsew
+flabel metal2 s 160070 -960 160182 480 0 FreeSans 560 90 0 0 la_oenb[9]
+port 3726 nsew
+flabel metal2 s 579774 -960 579886 480 0 FreeSans 560 90 0 0 user_clock2
+port 2963 nsew
+flabel metal2 s 580970 -960 581082 480 0 FreeSans 560 90 0 0 user_irq[0]
+port 2964 nsew
+flabel metal2 s 582166 -960 582278 480 0 FreeSans 560 90 0 0 user_irq[1]
+port 2965 nsew
+flabel metal2 s 583362 -960 583474 480 0 FreeSans 560 90 0 0 user_irq[2]
+port 2966 nsew
+flabel metal4 s -2006 -934 -1386 704870 0 FreeSans 4800 90 0 0 vccd1
+port 1 nsew
+flabel metal5 s -2006 -934 585930 -314 0 FreeSans 3200 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -2006 704250 585930 704870 0 FreeSans 3200 0 0 0 vccd1
+port 1 nsew
+flabel metal4 s 585310 -934 585930 704870 0 FreeSans 4800 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 1484 -7654 2724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 17484 -7654 18724 280048 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 17484 684808 18724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 33484 -7654 34724 24064 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 33484 111244 34724 148064 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 33484 235244 34724 281375 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 33484 683481 34724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 49484 -7654 50724 23940 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 49484 111244 50724 147940 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 49484 235244 50724 280048 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 49484 684808 50724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 65484 -7654 66724 23940 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 65484 111368 66724 147940 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 65484 235368 66724 281375 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 65484 683481 66724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 81484 -7654 82724 23940 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 81484 111244 82724 147940 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 81484 235244 82724 281375 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 81484 683481 82724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 97484 -7654 98724 23940 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 97484 111368 98724 147940 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 97484 235368 98724 280048 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 97484 684808 98724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 113484 -7654 114724 23940 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 113484 111368 114724 147940 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 113484 235368 114724 281375 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 113484 683481 114724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 129484 -7654 130724 24064 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 129484 111244 130724 148064 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 129484 235244 130724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 145484 -7654 146724 24064 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 145484 111244 146724 148064 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 145484 235244 146724 278655 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 145484 679961 146724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 161484 -7654 162724 24064 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 161484 111244 162724 148064 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 161484 235244 162724 278655 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 161484 679961 162724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 177484 -7654 178724 278655 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 177484 679961 178724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 193484 -7654 194724 24064 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 193484 258777 194724 278655 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 193484 679961 194724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 209484 -7654 210724 23940 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 209484 258777 210724 278655 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 209484 679961 210724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 225484 -7654 226724 23940 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 225484 258777 226724 278655 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 225484 679961 226724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 241484 -7654 242724 23940 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 241484 258777 242724 281375 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 241484 683481 242724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 257484 -7654 258724 24064 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 257484 258777 258724 281375 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 257484 683481 258724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 273484 -7654 274724 24064 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 273484 258777 274724 280048 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 273484 684808 274724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 289484 -7654 290724 24064 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 289484 258777 290724 281375 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 289484 683481 290724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 305484 -7654 306724 24064 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 305484 258777 306724 281375 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 305484 683481 306724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 321484 -7654 322724 24064 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 321484 258777 322724 281375 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 321484 683481 322724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 337484 -7654 338724 128111 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 337484 258777 338724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 353484 -7654 354724 20048 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 353484 104816 354724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 369484 -7654 370724 130287 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 369484 484673 370724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 385484 -7654 386724 130287 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 385484 484673 386724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 401484 -7654 402724 130287 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 401484 484673 402724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 417484 -7654 418724 130287 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 417484 484673 418724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 433484 -7654 434724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 449484 -7654 450724 91375 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 449484 195113 450724 220287 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 449484 579369 450724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 465484 -7654 466724 91375 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 465484 195113 466724 220287 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 465484 579369 466724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 481484 -7654 482724 91375 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 481484 195113 482724 220287 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 481484 579369 482724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 497484 -7654 498724 91375 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 497484 195113 498724 220287 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 497484 579369 498724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 513484 -7654 514724 90048 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 513484 579472 514724 605648 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 513484 625136 514724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 529484 -7654 530724 220287 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 529484 579369 530724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 545484 -7654 546724 220287 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 545484 579369 546724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 561484 -7654 562724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 577484 -7654 578724 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 2556 592650 3796 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 18556 592650 19796 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 34556 592650 35796 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 50556 592650 51796 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 66556 592650 67796 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 82556 592650 83796 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 98556 592650 99796 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 114556 592650 115796 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 130556 592650 131796 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 146556 592650 147796 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 162556 592650 163796 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 178556 592650 179796 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 194556 592650 195796 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 210556 592650 211796 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 226556 592650 227796 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
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+port 1 nsew
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+port 1 nsew
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+port 1 nsew
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+port 1 nsew
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+port 1 nsew
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+port 1 nsew
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+port 1 nsew
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+port 1 nsew
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+port 1 nsew
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+port 1 nsew
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+port 1 nsew
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+port 1 nsew
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+port 1 nsew
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+port 1 nsew
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+port 1 nsew
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+port 1 nsew
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+port 1 nsew
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+port 1 nsew
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+port 1 nsew
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+port 1 nsew
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+port 1 nsew
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+port 1 nsew
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+port 1 nsew
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+port 1 nsew
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+port 1 nsew
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+port 1 nsew
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+port 1 nsew
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+port 1 nsew
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+port 1 nsew
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+port 2 nsew
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+port 2 nsew
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+port 2 nsew
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+port 2 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 3 nsew
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+port 5 nsew
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+port 5 nsew
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+port 7 nsew
+flabel metal4 s 281484 -7654 282724 24064 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 281484 468481 282724 496375 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 281484 683481 282724 711590 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 297484 -7654 298724 24064 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 297484 468481 298724 496375 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 297484 683481 298724 711590 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 313484 -7654 314724 23940 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 313484 469808 314724 495048 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 313484 684808 314724 711590 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 329484 -7654 330724 128111 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 329484 468481 330724 496375 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 329484 683481 330724 711590 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 345484 -7654 346724 128111 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 345484 258777 346724 711590 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 361484 -7654 362724 711590 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 377484 -7654 378724 130287 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 377484 484673 378724 711590 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 393484 -7654 394724 20048 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 393484 104816 394724 130048 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 393484 489536 394724 711590 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 409484 -7654 410724 130287 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 409484 484673 410724 711590 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 425484 -7654 426724 130287 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 425484 484673 426724 711590 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 441484 -7654 442724 711590 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 457484 -7654 458724 91375 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 457484 195113 458724 220287 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 457484 377745 458724 398383 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 457484 579369 458724 711590 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 473484 -7654 474724 90048 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 473484 199840 474724 220048 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 473484 579472 474724 711590 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 489484 -7654 490724 91375 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 489484 195113 490724 220287 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 489484 377745 490724 398383 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 489484 579369 490724 711590 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 505484 -7654 506724 91375 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 505484 195113 506724 220287 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 505484 377745 506724 398383 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 505484 579369 506724 605648 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 505484 625136 506724 711590 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 521484 -7654 522724 91375 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 521484 195113 522724 220287 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 521484 377745 522724 398383 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 521484 579369 522724 711590 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 537484 -7654 538724 220287 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 537484 377745 538724 398383 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 537484 579369 538724 711590 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 553484 -7654 554724 220287 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 553484 377745 554724 398383 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 553484 579369 554724 711590 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal4 s 569484 -7654 570724 711590 0 FreeSans 9600 90 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 10556 592650 11796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 26556 592650 27796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 42556 592650 43796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 58556 592650 59796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 74556 592650 75796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 90556 592650 91796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 106556 592650 107796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 122556 592650 123796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 138556 592650 139796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 154556 592650 155796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 170556 592650 171796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 186556 592650 187796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 202556 592650 203796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 218556 592650 219796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 234556 592650 235796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s 291962 251176 291962 251176 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 266556 592650 267796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 282556 592650 283796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 298556 592650 299796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 314556 592650 315796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 330556 592650 331796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 346556 592650 347796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 362556 592650 363796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 378556 592650 379796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 394556 592650 395796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 410556 592650 411796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 426556 592650 427796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 442556 592650 443796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 458556 592650 459796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 474556 592650 475796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 490556 592650 491796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 506556 592650 507796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 522556 592650 523796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 538556 592650 539796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 554556 592650 555796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 570556 592650 571796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 586556 592650 587796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 602556 592650 603796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 618556 592650 619796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 634556 592650 635796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 650556 592650 651796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 666556 592650 667796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 682556 592650 683796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 698556 592650 699796 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal4 s -4886 -3814 -4266 707750 0 FreeSans 4800 90 0 0 vssd2
+port 8 nsew
+flabel metal5 s -4886 -3814 588810 -3194 0 FreeSans 3200 0 0 0 vssd2
+port 8 nsew
+flabel metal5 s -4886 707130 588810 707750 0 FreeSans 3200 0 0 0 vssd2
+port 8 nsew
+flabel metal4 s 588500 351968 588500 351968 0 FreeSans 4800 90 0 0 vssd2
+port 8 nsew
+flabel metal2 s 542 -960 654 480 0 FreeSans 560 90 0 0 wb_clk_i
+port 2967 nsew
+flabel metal2 s 1646 -960 1758 480 0 FreeSans 560 90 0 0 wb_rst_i
+port 2968 nsew
+flabel metal2 s 2842 -960 2954 480 0 FreeSans 560 90 0 0 wbs_ack_o
+port 3360 nsew
+flabel metal2 s 7626 -960 7738 480 0 FreeSans 560 90 0 0 wbs_adr_i[0]
+port 3361 nsew
+flabel metal2 s 47830 -960 47942 480 0 FreeSans 560 90 0 0 wbs_adr_i[10]
+port 3362 nsew
+flabel metal2 s 51326 -960 51438 480 0 FreeSans 560 90 0 0 wbs_adr_i[11]
+port 3363 nsew
+flabel metal2 s 54914 -960 55026 480 0 FreeSans 560 90 0 0 wbs_adr_i[12]
+port 3364 nsew
+flabel metal2 s 58410 -960 58522 480 0 FreeSans 560 90 0 0 wbs_adr_i[13]
+port 3365 nsew
+flabel metal2 s 61998 -960 62110 480 0 FreeSans 560 90 0 0 wbs_adr_i[14]
+port 3366 nsew
+flabel metal2 s 65494 -960 65606 480 0 FreeSans 560 90 0 0 wbs_adr_i[15]
+port 3367 nsew
+flabel metal2 s 69082 -960 69194 480 0 FreeSans 560 90 0 0 wbs_adr_i[16]
+port 3368 nsew
+flabel metal2 s 72578 -960 72690 480 0 FreeSans 560 90 0 0 wbs_adr_i[17]
+port 3369 nsew
+flabel metal2 s 76166 -960 76278 480 0 FreeSans 560 90 0 0 wbs_adr_i[18]
+port 3370 nsew
+flabel metal2 s 79662 -960 79774 480 0 FreeSans 560 90 0 0 wbs_adr_i[19]
+port 3371 nsew
+flabel metal2 s 12318 -960 12430 480 0 FreeSans 560 90 0 0 wbs_adr_i[1]
+port 3372 nsew
+flabel metal2 s 83250 -960 83362 480 0 FreeSans 560 90 0 0 wbs_adr_i[20]
+port 3373 nsew
+flabel metal2 s 86838 -960 86950 480 0 FreeSans 560 90 0 0 wbs_adr_i[21]
+port 3374 nsew
+flabel metal2 s 90334 -960 90446 480 0 FreeSans 560 90 0 0 wbs_adr_i[22]
+port 3375 nsew
+flabel metal2 s 93922 -960 94034 480 0 FreeSans 560 90 0 0 wbs_adr_i[23]
+port 3376 nsew
+flabel metal2 s 97418 -960 97530 480 0 FreeSans 560 90 0 0 wbs_adr_i[24]
+port 3377 nsew
+flabel metal2 s 101006 -960 101118 480 0 FreeSans 560 90 0 0 wbs_adr_i[25]
+port 3378 nsew
+flabel metal2 s 104502 -960 104614 480 0 FreeSans 560 90 0 0 wbs_adr_i[26]
+port 3379 nsew
+flabel metal2 s 108090 -960 108202 480 0 FreeSans 560 90 0 0 wbs_adr_i[27]
+port 3380 nsew
+flabel metal2 s 111586 -960 111698 480 0 FreeSans 560 90 0 0 wbs_adr_i[28]
+port 3381 nsew
+flabel metal2 s 115174 -960 115286 480 0 FreeSans 560 90 0 0 wbs_adr_i[29]
+port 3382 nsew
+flabel metal2 s 17010 -960 17122 480 0 FreeSans 560 90 0 0 wbs_adr_i[2]
+port 3383 nsew
+flabel metal2 s 118762 -960 118874 480 0 FreeSans 560 90 0 0 wbs_adr_i[30]
+port 3384 nsew
+flabel metal2 s 122258 -960 122370 480 0 FreeSans 560 90 0 0 wbs_adr_i[31]
+port 3385 nsew
+flabel metal2 s 21794 -960 21906 480 0 FreeSans 560 90 0 0 wbs_adr_i[3]
+port 3386 nsew
+flabel metal2 s 26486 -960 26598 480 0 FreeSans 560 90 0 0 wbs_adr_i[4]
+port 3387 nsew
+flabel metal2 s 30074 -960 30186 480 0 FreeSans 560 90 0 0 wbs_adr_i[5]
+port 3388 nsew
+flabel metal2 s 33570 -960 33682 480 0 FreeSans 560 90 0 0 wbs_adr_i[6]
+port 3389 nsew
+flabel metal2 s 37158 -960 37270 480 0 FreeSans 560 90 0 0 wbs_adr_i[7]
+port 3390 nsew
+flabel metal2 s 40654 -960 40766 480 0 FreeSans 560 90 0 0 wbs_adr_i[8]
+port 3391 nsew
+flabel metal2 s 44242 -960 44354 480 0 FreeSans 560 90 0 0 wbs_adr_i[9]
+port 3392 nsew
+flabel metal2 s 4038 -960 4150 480 0 FreeSans 560 90 0 0 wbs_cyc_i
+port 3393 nsew
+flabel metal2 s 8730 -960 8842 480 0 FreeSans 560 90 0 0 wbs_dat_i[0]
+port 3394 nsew
+flabel metal2 s 48934 -960 49046 480 0 FreeSans 560 90 0 0 wbs_dat_i[10]
+port 3395 nsew
+flabel metal2 s 52522 -960 52634 480 0 FreeSans 560 90 0 0 wbs_dat_i[11]
+port 3396 nsew
+flabel metal2 s 56018 -960 56130 480 0 FreeSans 560 90 0 0 wbs_dat_i[12]
+port 3397 nsew
+flabel metal2 s 59606 -960 59718 480 0 FreeSans 560 90 0 0 wbs_dat_i[13]
+port 3398 nsew
+flabel metal2 s 63194 -960 63306 480 0 FreeSans 560 90 0 0 wbs_dat_i[14]
+port 3399 nsew
+flabel metal2 s 66690 -960 66802 480 0 FreeSans 560 90 0 0 wbs_dat_i[15]
+port 3400 nsew
+flabel metal2 s 70278 -960 70390 480 0 FreeSans 560 90 0 0 wbs_dat_i[16]
+port 3401 nsew
+flabel metal2 s 73774 -960 73886 480 0 FreeSans 560 90 0 0 wbs_dat_i[17]
+port 3402 nsew
+flabel metal2 s 77362 -960 77474 480 0 FreeSans 560 90 0 0 wbs_dat_i[18]
+port 3403 nsew
+flabel metal2 s 80858 -960 80970 480 0 FreeSans 560 90 0 0 wbs_dat_i[19]
+port 3404 nsew
+flabel metal2 s 13514 -960 13626 480 0 FreeSans 560 90 0 0 wbs_dat_i[1]
+port 3405 nsew
+flabel metal2 s 84446 -960 84558 480 0 FreeSans 560 90 0 0 wbs_dat_i[20]
+port 3406 nsew
+flabel metal2 s 87942 -960 88054 480 0 FreeSans 560 90 0 0 wbs_dat_i[21]
+port 3407 nsew
+flabel metal2 s 91530 -960 91642 480 0 FreeSans 560 90 0 0 wbs_dat_i[22]
+port 3408 nsew
+flabel metal2 s 95118 -960 95230 480 0 FreeSans 560 90 0 0 wbs_dat_i[23]
+port 3409 nsew
+flabel metal2 s 98614 -960 98726 480 0 FreeSans 560 90 0 0 wbs_dat_i[24]
+port 3410 nsew
+flabel metal2 s 102202 -960 102314 480 0 FreeSans 560 90 0 0 wbs_dat_i[25]
+port 3411 nsew
+flabel metal2 s 105698 -960 105810 480 0 FreeSans 560 90 0 0 wbs_dat_i[26]
+port 3412 nsew
+flabel metal2 s 109286 -960 109398 480 0 FreeSans 560 90 0 0 wbs_dat_i[27]
+port 3413 nsew
+flabel metal2 s 112782 -960 112894 480 0 FreeSans 560 90 0 0 wbs_dat_i[28]
+port 3414 nsew
+flabel metal2 s 116370 -960 116482 480 0 FreeSans 560 90 0 0 wbs_dat_i[29]
+port 3415 nsew
+flabel metal2 s 18206 -960 18318 480 0 FreeSans 560 90 0 0 wbs_dat_i[2]
+port 3416 nsew
+flabel metal2 s 119866 -960 119978 480 0 FreeSans 560 90 0 0 wbs_dat_i[30]
+port 3417 nsew
+flabel metal2 s 123454 -960 123566 480 0 FreeSans 560 90 0 0 wbs_dat_i[31]
+port 3418 nsew
+flabel metal2 s 22990 -960 23102 480 0 FreeSans 560 90 0 0 wbs_dat_i[3]
+port 3419 nsew
+flabel metal2 s 27682 -960 27794 480 0 FreeSans 560 90 0 0 wbs_dat_i[4]
+port 3420 nsew
+flabel metal2 s 31270 -960 31382 480 0 FreeSans 560 90 0 0 wbs_dat_i[5]
+port 3421 nsew
+flabel metal2 s 34766 -960 34878 480 0 FreeSans 560 90 0 0 wbs_dat_i[6]
+port 3422 nsew
+flabel metal2 s 38354 -960 38466 480 0 FreeSans 560 90 0 0 wbs_dat_i[7]
+port 3423 nsew
+flabel metal2 s 41850 -960 41962 480 0 FreeSans 560 90 0 0 wbs_dat_i[8]
+port 3424 nsew
+flabel metal2 s 45438 -960 45550 480 0 FreeSans 560 90 0 0 wbs_dat_i[9]
+port 3425 nsew
+flabel metal2 s 9926 -960 10038 480 0 FreeSans 560 90 0 0 wbs_dat_o[0]
+port 3426 nsew
+flabel metal2 s 50130 -960 50242 480 0 FreeSans 560 90 0 0 wbs_dat_o[10]
+port 3427 nsew
+flabel metal2 s 53718 -960 53830 480 0 FreeSans 560 90 0 0 wbs_dat_o[11]
+port 3428 nsew
+flabel metal2 s 57214 -960 57326 480 0 FreeSans 560 90 0 0 wbs_dat_o[12]
+port 3429 nsew
+flabel metal2 s 60802 -960 60914 480 0 FreeSans 560 90 0 0 wbs_dat_o[13]
+port 3430 nsew
+flabel metal2 s 64298 -960 64410 480 0 FreeSans 560 90 0 0 wbs_dat_o[14]
+port 3431 nsew
+flabel metal2 s 67886 -960 67998 480 0 FreeSans 560 90 0 0 wbs_dat_o[15]
+port 3432 nsew
+flabel metal2 s 71474 -960 71586 480 0 FreeSans 560 90 0 0 wbs_dat_o[16]
+port 3433 nsew
+flabel metal2 s 74970 -960 75082 480 0 FreeSans 560 90 0 0 wbs_dat_o[17]
+port 3434 nsew
+flabel metal2 s 78558 -960 78670 480 0 FreeSans 560 90 0 0 wbs_dat_o[18]
+port 3435 nsew
+flabel metal2 s 82054 -960 82166 480 0 FreeSans 560 90 0 0 wbs_dat_o[19]
+port 3436 nsew
+flabel metal2 s 14710 -960 14822 480 0 FreeSans 560 90 0 0 wbs_dat_o[1]
+port 3437 nsew
+flabel metal2 s 85642 -960 85754 480 0 FreeSans 560 90 0 0 wbs_dat_o[20]
+port 3438 nsew
+flabel metal2 s 89138 -960 89250 480 0 FreeSans 560 90 0 0 wbs_dat_o[21]
+port 3439 nsew
+flabel metal2 s 92726 -960 92838 480 0 FreeSans 560 90 0 0 wbs_dat_o[22]
+port 3440 nsew
+flabel metal2 s 96222 -960 96334 480 0 FreeSans 560 90 0 0 wbs_dat_o[23]
+port 3441 nsew
+flabel metal2 s 99810 -960 99922 480 0 FreeSans 560 90 0 0 wbs_dat_o[24]
+port 3442 nsew
+flabel metal2 s 103306 -960 103418 480 0 FreeSans 560 90 0 0 wbs_dat_o[25]
+port 3443 nsew
+flabel metal2 s 106894 -960 107006 480 0 FreeSans 560 90 0 0 wbs_dat_o[26]
+port 3444 nsew
+flabel metal2 s 110482 -960 110594 480 0 FreeSans 560 90 0 0 wbs_dat_o[27]
+port 3445 nsew
+flabel metal2 s 113978 -960 114090 480 0 FreeSans 560 90 0 0 wbs_dat_o[28]
+port 3446 nsew
+flabel metal2 s 117566 -960 117678 480 0 FreeSans 560 90 0 0 wbs_dat_o[29]
+port 3447 nsew
+flabel metal2 s 19402 -960 19514 480 0 FreeSans 560 90 0 0 wbs_dat_o[2]
+port 3448 nsew
+flabel metal2 s 121062 -960 121174 480 0 FreeSans 560 90 0 0 wbs_dat_o[30]
+port 3449 nsew
+flabel metal2 s 124650 -960 124762 480 0 FreeSans 560 90 0 0 wbs_dat_o[31]
+port 3450 nsew
+flabel metal2 s 24186 -960 24298 480 0 FreeSans 560 90 0 0 wbs_dat_o[3]
+port 3451 nsew
+flabel metal2 s 28878 -960 28990 480 0 FreeSans 560 90 0 0 wbs_dat_o[4]
+port 3452 nsew
+flabel metal2 s 32374 -960 32486 480 0 FreeSans 560 90 0 0 wbs_dat_o[5]
+port 3453 nsew
+flabel metal2 s 35962 -960 36074 480 0 FreeSans 560 90 0 0 wbs_dat_o[6]
+port 3454 nsew
+flabel metal2 s 39550 -960 39662 480 0 FreeSans 560 90 0 0 wbs_dat_o[7]
+port 3455 nsew
+flabel metal2 s 43046 -960 43158 480 0 FreeSans 560 90 0 0 wbs_dat_o[8]
+port 3456 nsew
+flabel metal2 s 46634 -960 46746 480 0 FreeSans 560 90 0 0 wbs_dat_o[9]
+port 3457 nsew
+flabel metal2 s 11122 -960 11234 480 0 FreeSans 560 90 0 0 wbs_sel_i[0]
+port 3458 nsew
+flabel metal2 s 15906 -960 16018 480 0 FreeSans 560 90 0 0 wbs_sel_i[1]
+port 3459 nsew
+flabel metal2 s 20598 -960 20710 480 0 FreeSans 560 90 0 0 wbs_sel_i[2]
+port 3460 nsew
+flabel metal2 s 25290 -960 25402 480 0 FreeSans 560 90 0 0 wbs_sel_i[3]
+port 3461 nsew
+flabel metal2 s 5234 -960 5346 480 0 FreeSans 560 90 0 0 wbs_stb_i
+port 3462 nsew
+flabel metal2 s 6430 -960 6542 480 0 FreeSans 560 90 0 0 wbs_we_i
+port 3463 nsew
+<< properties >>
+string FIXED_BBOX 0 0 584000 704000
+<< end >>
diff --git a/mpw_precheck/outputs/user_project_wrapper.xor.gds b/mpw_precheck/outputs/user_project_wrapper.xor.gds
new file mode 100644
index 0000000..f5f1a25
--- /dev/null
+++ b/mpw_precheck/outputs/user_project_wrapper.xor.gds
Binary files differ
diff --git a/mpw_precheck/outputs/user_project_wrapper_empty_erased.gds b/mpw_precheck/outputs/user_project_wrapper_empty_erased.gds
new file mode 100644
index 0000000..d742057
--- /dev/null
+++ b/mpw_precheck/outputs/user_project_wrapper_empty_erased.gds
Binary files differ
diff --git a/mpw_precheck/outputs/user_project_wrapper_erased.gds b/mpw_precheck/outputs/user_project_wrapper_erased.gds
new file mode 100644
index 0000000..79dda41
--- /dev/null
+++ b/mpw_precheck/outputs/user_project_wrapper_erased.gds
Binary files differ
diff --git a/mpw_precheck/outputs/user_project_wrapper_no_zero_areas.gds.gz b/mpw_precheck/outputs/user_project_wrapper_no_zero_areas.gds.gz
new file mode 100644
index 0000000..bf63502
--- /dev/null
+++ b/mpw_precheck/outputs/user_project_wrapper_no_zero_areas.gds.gz
Binary files differ
diff --git a/signoff/.gitignore b/signoff/.gitignore
new file mode 100644
index 0000000..6407046
--- /dev/null
+++ b/signoff/.gitignore
@@ -0,0 +1 @@
+cdrcpost/*
diff --git a/signoff/assigned_slot b/signoff/assigned_slot
new file mode 100644
index 0000000..be145ca
--- /dev/null
+++ b/signoff/assigned_slot
@@ -0,0 +1 @@
+005
diff --git a/signoff/caravel_layout.png b/signoff/caravel_layout.png
new file mode 100644
index 0000000..ef7386e
--- /dev/null
+++ b/signoff/caravel_layout.png
Binary files differ
diff --git a/tapeout/logs/compose.log b/tapeout/logs/compose.log
new file mode 100644
index 0000000..4055af8
--- /dev/null
+++ b/tapeout/logs/compose.log
@@ -0,0 +1,1800 @@
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/compose.tcl" from command line.
+caravel: 10000 rects
+caravel: 20000 rects
+caravel: 30000 rects
+caravel: 40000 rects
+caravel: 50000 rects
+caravel: 60000 rects
+caravel: 70000 rects
+caravel: 80000 rects
+caravel
+Scaled magic input cell advSeal_6um_gen geometry by factor of 2
+Writing final GDS. . . 
+Scaled magic input cell seal_ring_corner_abstract geometry by factor of 2
+Scaled magic input cell caravel_motto geometry by factor of 2
+Scaled magic input cell font_22 geometry by factor of 24
+Scaled magic input cell font_73 geometry by factor of 24
+Scaled magic input cell font_43 geometry by factor of 24
+Scaled magic input cell font_49 geometry by factor of 24
+Scaled magic input cell font_65 geometry by factor of 24
+Scaled magic input cell font_68 geometry by factor of 24
+Scaled magic input cell font_54 geometry by factor of 24
+Scaled magic input cell font_67 geometry by factor of 24
+Scaled magic input cell font_6E geometry by factor of 24
+Scaled magic input cell font_69 geometry by factor of 24
+Scaled magic input cell font_6C geometry by factor of 24
+Scaled magic input cell font_61 geometry by factor of 24
+Scaled magic input cell font_53 geometry by factor of 24
+Scaled magic input cell font_79 geometry by factor of 24
+Scaled magic input cell font_76 geometry by factor of 24
+Scaled magic input cell font_74 geometry by factor of 24
+Scaled magic input cell font_72 geometry by factor of 24
+Scaled magic input cell font_70 geometry by factor of 24
+Scaled magic input cell font_66 geometry by factor of 24
+Scaled magic input cell font_63 geometry by factor of 24
+Scaled magic input cell font_62 geometry by factor of 24
+Scaled magic input cell font_57 geometry by factor of 24
+Scaled magic input cell font_56 geometry by factor of 24
+Scaled magic input cell font_50 geometry by factor of 24
+Scaled magic input cell font_47 geometry by factor of 24
+Scaled magic input cell font_44 geometry by factor of 24
+Scaled magic input cell font_35 geometry by factor of 24
+Scaled magic input cell font_32 geometry by factor of 24
+Scaled magic input cell font_30 geometry by factor of 24
+Scaled magic input cell font_29 geometry by factor of 24
+Scaled magic input cell font_28 geometry by factor of 24
+Scaled magic input cell font_20 geometry by factor of 24
+Scaled magic input cell font_6F geometry by factor of 24
+Scaled magic input cell font_6B geometry by factor of 24
+Scaled magic input cell font_4F geometry by factor of 24
+Scaled magic input cell font_4B geometry by factor of 24
+Scaled magic input cell font_2D geometry by factor of 24
+Scaled magic input cell open_source geometry by factor of 2
+Scaled magic input cell user_id_textblock geometry by factor of 2
+Scaled magic input cell alpha_0 geometry by factor of 2
+Scaled magic input cell user_project_wrapper geometry by factor of 2
+user_project_wrapper: 10000 rects
+user_project_wrapper: 20000 rects
+user_project_wrapper: 30000 rects
+user_project_wrapper: 40000 rects
+user_project_wrapper: 50000 rects
+Processing timestamp mismatches: sky130_ef_sc_hd__decap_12, sky130_fd_sc_hd__buf_8, sky130_fd_sc_hd__tapvpwrvgnd_1, sky130_ef_io__com_bus_slice_10um, sky130_ef_io__com_bus_slice_20um, sky130_ef_io__com_bus_slice_1um, sky130_ef_io__com_bus_slice_5um, sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um, sky130_ef_io__disconnect_vdda_slice_5um, sky130_ef_io__vccd_lvc_clamped_pad, sky130_ef_io__vddio_hvc_clamped_pad, sky130_ef_io__vssd_lvc_clamped_pad, sky130_ef_io__vssio_hvc_clamped_pad, sky130_ef_io__gpiov2_pad_wrapped, sky130_fd_io__top_xres4v2, sky130_ef_io__corner_pad, sky130_ef_io__vccd_lvc_clamped3_pad, sky130_ef_io__vdda_hvc_clamped_pad, sky130_ef_io__vssa_hvc_clamped_pad, sky130_ef_io__vssd_lvc_clamped3_pad, gpio_control_power_routing, gpio_control_power_routing_right, gpio_control_power_routing_top, mgmt_protect, spare_logic_block, user_id_programming, simple_por, digital_pll, housekeeping, gpio_defaults_block, gpio_control_block, buff_flash_clkrst, caravel_clocking, xres_buf, seal_ring_corner_abstract.
+   Generating output for cell advSeal_6um_gen
+Reading "sealring_slots".
+Reading "seal_ring_slots_array".
+Reading "sr_polygon00011".
+Reading "sr_polygon00039".
+Reading "sr_polygon00035".
+Reading "sr_polygon00015".
+Reading "sr_polygon00007".
+Reading "sr_polygon00001".
+Reading "sr_polygon00002".
+Reading "sr_polygon00003".
+Reading "sr_polygon00004".
+Reading "sr_polygon00005".
+Reading "sr_polygon00006".
+Reading "nikon_sealring_shape".
+Reading "sr_polygon00019".
+Reading "sr_polygon00023".
+Reading "sr_polygon00027".
+Reading "sr_polygon00031".
+Reading "sr_polygon00036".
+Reading "sr_polygon00032".
+Reading "sr_polygon00016".
+Reading "sr_polygon00020".
+Reading "sr_polygon00024".
+Reading "sr_polygon00028".
+Reading "seal_ring_corner".
+Reading "advSeal_6um_gen".
+   Generating output for cell caravel_00088bca_fill_pattern
+Reading "caravel_00088bca_fill_pattern_0_0".
+Reading "caravel_00088bca_fill_pattern_1_0".
+Reading "caravel_00088bca_fill_pattern_0_1".
+Reading "caravel_00088bca_fill_pattern_1_1".
+Reading "caravel_00088bca_fill_pattern_2_0".
+Reading "caravel_00088bca_fill_pattern_2_1".
+Reading "caravel_00088bca_fill_pattern_3_0".
+Reading "caravel_00088bca_fill_pattern_3_1".
+Reading "caravel_00088bca_fill_pattern_4_0".
+Reading "caravel_00088bca_fill_pattern_4_1".
+Reading "caravel_00088bca_fill_pattern_5_0".
+Reading "caravel_00088bca_fill_pattern_5_1".
+Reading "caravel_00088bca_fill_pattern_0_2".
+Reading "caravel_00088bca_fill_pattern_1_2".
+Reading "caravel_00088bca_fill_pattern_2_2".
+Reading "caravel_00088bca_fill_pattern_3_2".
+Reading "caravel_00088bca_fill_pattern_4_2".
+Reading "caravel_00088bca_fill_pattern_5_2".
+Reading "caravel_00088bca_fill_pattern_0_3".
+Reading "caravel_00088bca_fill_pattern_1_3".
+Reading "caravel_00088bca_fill_pattern_2_3".
+Reading "caravel_00088bca_fill_pattern_3_3".
+Reading "caravel_00088bca_fill_pattern_4_3".
+Reading "caravel_00088bca_fill_pattern_5_3".
+Reading "caravel_00088bca_fill_pattern_0_4".
+Reading "caravel_00088bca_fill_pattern_1_4".
+Reading "caravel_00088bca_fill_pattern_2_4".
+Reading "caravel_00088bca_fill_pattern_3_4".
+Reading "caravel_00088bca_fill_pattern_4_4".
+Reading "caravel_00088bca_fill_pattern_5_4".
+Reading "caravel_00088bca_fill_pattern_0_5".
+Reading "caravel_00088bca_fill_pattern_1_5".
+Reading "caravel_00088bca_fill_pattern_2_5".
+Reading "caravel_00088bca_fill_pattern_3_5".
+Reading "caravel_00088bca_fill_pattern_4_5".
+Reading "caravel_00088bca_fill_pattern_5_5".
+Reading "caravel_00088bca_fill_pattern_0_6".
+Reading "caravel_00088bca_fill_pattern_1_6".
+Reading "caravel_00088bca_fill_pattern_2_6".
+Reading "caravel_00088bca_fill_pattern_3_6".
+Reading "caravel_00088bca_fill_pattern_4_6".
+Reading "caravel_00088bca_fill_pattern_5_6".
+Reading "caravel_00088bca_fill_pattern_0_7".
+Reading "caravel_00088bca_fill_pattern_1_7".
+Reading "caravel_00088bca_fill_pattern_2_7".
+Reading "caravel_00088bca_fill_pattern_3_7".
+Reading "caravel_00088bca_fill_pattern_4_7".
+Reading "caravel_00088bca_fill_pattern_5_7".
+Reading "caravel_00088bca_fill_pattern".
+   Generating output for cell caravel
+Reading "caravel_logo".
+Reading "font_22".
+Reading "font_73".
+Reading "font_43".
+Reading "font_49".
+Reading "font_65".
+Reading "font_68".
+Reading "font_54".
+Reading "font_67".
+Reading "font_6E".
+Reading "font_69".
+Reading "font_6C".
+Reading "font_61".
+Reading "font_53".
+Reading "caravel_motto".
+Reading "font_79".
+Reading "font_76".
+Reading "font_74".
+Reading "font_72".
+Reading "font_70".
+Reading "font_66".
+Reading "font_63".
+Reading "font_62".
+Reading "font_57".
+Reading "font_56".
+Reading "font_50".
+Reading "font_47".
+Reading "font_44".
+Reading "font_35".
+Reading "font_32".
+Reading "font_30".
+Reading "font_29".
+Reading "font_28".
+Reading "font_20".
+Reading "font_6F".
+Reading "font_6B".
+Reading "font_4F".
+Reading "font_4B".
+Reading "font_2D".
+Reading "copyright_block".
+Reading "open_source".
+Reading "sky130_fd_sc_hvl__decap_8".
+Reading "sky130_fd_sc_hvl__decap_4".
+Reading "sky130_fd_sc_hvl__diode_2".
+Reading "sky130_fd_sc_hvl__fill_1".
+Reading "sky130_fd_sc_hvl__fill_2".
+Reading "sky130_fd_sc_hvl__lsbufhv2lv_1".
+Reading "xres_buf".
+Reading "alpha_8".
+Reading "alpha_B".
+Reading "alpha_C".
+Reading "alpha_A".
+Reading "alpha_0".
+Reading "user_id_textblock".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "gpio_defaults_block_1803".
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__nand3b_1".
+Reading "sky130_fd_sc_hd__nand4bb_1".
+Reading "sky130_fd_sc_hd__o2111ai_2".
+Reading "sky130_fd_sc_hd__o31ai_2".
+Reading "sky130_fd_sc_hd__o2bb2ai_1".
+Reading "sky130_fd_sc_hd__a41oi_1".
+Reading "sky130_fd_sc_hd__o211ai_4".
+Reading "sky130_fd_sc_hd__nor3b_2".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__o2111ai_1".
+Reading "sky130_fd_sc_hd__nand3_1".
+Reading "sky130_fd_sc_hd__a31o_1".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "sky130_fd_sc_hd__nand2b_1".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__a2bb2o_1".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__nor3_2".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__nor4_1".
+Reading "sky130_fd_sc_hd__o31ai_1".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__dfstp_1".
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__dfrtn_1".
+Reading "sky130_fd_sc_hd__dfstp_2".
+Reading "sky130_fd_sc_hd__dfrtp_1".
+Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__o21a_2".
+Reading "sky130_fd_sc_hd__nand2b_2".
+Reading "sky130_fd_sc_hd__o21ai_2".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__dfrtp_2".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__clkinv_2".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_ef_sc_hd__decap_12".
+Reading "caravel_clocking".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "buff_flash_clkrst".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__macro_sparecell".
+Reading "sky130_fd_sc_hd__dfbbn_2".
+Reading "sky130_fd_sc_hd__or2_0".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__and2_0".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "sky130_fd_sc_hd__and2b_2".
+Reading "sky130_fd_sc_hd__and3b_2".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__buf_16".
+Reading "gpio_logic_high".
+Reading "gpio_control_block".
+Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__a21bo_1".
+Reading "sky130_fd_sc_hd__o2bb2a_1".
+Reading "sky130_fd_sc_hd__a221o_2".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__o21ba_1".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__and4bb_1".
+Reading "sky130_fd_sc_hd__and4bb_2".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__a311o_1".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__o221a_1".
+Reading "sky130_fd_sc_hd__a2111o_1".
+Reading "sky130_fd_sc_hd__nor4_2".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__nor4_4".
+Reading "sky130_fd_sc_hd__a2111o_2".
+Reading "sky130_fd_sc_hd__nand2b_4".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__a21boi_1".
+Reading "sky130_fd_sc_hd__nand4_1".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__o211a_1".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__nand4b_1".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__a41o_1".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__a311oi_2".
+Reading "sky130_fd_sc_hd__o41a_1".
+Reading "sky130_fd_sc_hd__nor3b_1".
+Reading "sky130_fd_sc_hd__a2111oi_1".
+Reading "sky130_fd_sc_hd__nand4b_4".
+Reading "sky130_fd_sc_hd__a31oi_4".
+Reading "sky130_fd_sc_hd__and4b_4".
+Reading "sky130_fd_sc_hd__nand3b_4".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__xor2_1".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__o221a_4".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "sky130_fd_sc_hd__o31a_4".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__a221oi_1".
+Reading "sky130_fd_sc_hd__a221o_4".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__inv_6".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__nand4_2".
+Reading "sky130_fd_sc_hd__and4b_2".
+Reading "sky130_fd_sc_hd__xnor2_2".
+Reading "sky130_fd_sc_hd__a21oi_2".
+Reading "sky130_fd_sc_hd__a211o_2".
+Reading "sky130_fd_sc_hd__and3_2".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__o31a_2".
+Reading "sky130_fd_sc_hd__nand3_2".
+Reading "sky130_fd_sc_hd__a21o_2".
+Reading "sky130_fd_sc_hd__a22o_2".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__and2b_4".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__and3b_4".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "housekeeping".
+Reading "sky130_fd_sc_hd__einvp_1".
+Reading "sky130_fd_sc_hd__clkinv_1".
+Reading "sky130_fd_sc_hd__einvn_4".
+Reading "sky130_fd_sc_hd__einvn_8".
+Reading "sky130_fd_sc_hd__einvp_2".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__a32o_2".
+Reading "sky130_fd_sc_hd__o2111a_2".
+Reading "sky130_fd_sc_hd__o22a_2".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__nand3b_2".
+Reading "sky130_fd_sc_hd__a21boi_2".
+Reading "sky130_fd_sc_hd__xor2_2".
+Reading "sky130_fd_sc_hd__o2bb2a_2".
+Reading "sky130_fd_sc_hd__nand4b_2".
+Reading "sky130_fd_sc_hd__o21ba_2".
+Reading "sky130_fd_sc_hd__o32a_2".
+Reading "sky130_fd_sc_hd__clkinv_8".
+Reading "digital_pll".
+Reading "user_id_programming".
+Reading "NJ_sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ".
+Reading "NJ_sky130_fd_pr__pfet_g5v0d10v5_3YBPVB".
+Reading "NJ_sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC".
+Reading "NJ_sky130_fd_pr__nfet_g5v0d10v5_TGFUGS".
+Reading "NJ_sky130_fd_pr__pfet_g5v0d10v5_YUHPBG".
+Reading "NJ_sky130_fd_pr__pfet_g5v0d10v5_YEUEBV".
+Reading "NJ_sky130_fd_pr__nfet_g5v0d10v5_PKVMTM".
+Reading "NJ_sky130_fd_pr__pfet_g5v0d10v5_YUHPXE".
+Reading "NJ_sky130_fd_sc_hvl__schmittbuf_1".
+Reading "NJ_sky130_fd_sc_hvl__buf_8".
+Reading "NJ_sky130_fd_sc_hvl__inv_8".
+Reading "NJ_sky130_fd_sc_hvl__fill_4".
+Reading "NJ_sky130_fd_pr__cap_mim_m3_1_WRT4AW".
+Reading "NJ_sky130_fd_pr__cap_mim_m3_2_W5U4AW".
+Reading "NJ_sky130_fd_pr__res_xhigh_po_0p69_S5N9F3".
+Reading "simple_por".
+Reading "EY_sky130_fd_sc_hd__decap_3".
+Reading "EY_sky130_ef_sc_hd__decap_12".
+Reading "EY_sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "EY_sky130_fd_sc_hd__fill_1".
+Reading "EY_sky130_fd_sc_hd__decap_4".
+Reading "EY_sky130_fd_sc_hd__decap_6".
+Reading "EY_sky130_fd_sc_hd__fill_2".
+Reading "EY_sky130_fd_sc_hd__decap_8".
+Reading "EY_sky130_fd_sc_hd__diode_2".
+Reading "EY_sky130_fd_sc_hd__clkbuf_16".
+Reading "EY_sky130_fd_sc_hd__o211a_1".
+Reading "EY_sky130_fd_sc_hd__dfxtp_2".
+Reading "EY_sky130_fd_sc_hd__o21a_1".
+Reading "EY_sky130_fd_sc_hd__mux2_1".
+Reading "EY_sky130_fd_sc_hd__or2_1".
+Reading "EY_sky130_fd_sc_hd__dfxtp_1".
+Reading "EY_sky130_fd_sc_hd__a22o_1".
+Reading "EY_sky130_fd_sc_hd__a21o_2".
+Reading "EY_sky130_fd_sc_hd__a21o_1".
+Reading "EY_sky130_fd_sc_hd__a22o_4".
+Reading "EY_sky130_fd_sc_hd__buf_8".
+Reading "EY_sky130_fd_sc_hd__o21a_2".
+Reading "EY_sky130_fd_sc_hd__mux2_2".
+Reading "EY_sky130_fd_sc_hd__buf_4".
+Reading "EY_sky130_fd_sc_hd__clkbuf_8".
+Reading "EY_sky130_fd_sc_hd__buf_6".
+Reading "EY_sky130_fd_sc_hd__dfxtp_4".
+Reading "EY_sky130_fd_sc_hd__buf_2".
+Reading "EY_sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "EY_sky130_fd_sc_hd__o21ai_1".
+Reading "EY_sky130_fd_sc_hd__mux4_1".
+Reading "EY_sky130_fd_sc_hd__buf_12".
+Reading "EY_sky130_fd_sc_hd__mux4_2".
+Reading "EY_sky130_fd_sc_hd__inv_2".
+Reading "EY_sky130_fd_sc_hd__and3_2".
+Reading "EY_sky130_fd_sc_hd__nand2_1".
+Reading "EY_sky130_fd_sc_hd__a2bb2o_1".
+Reading "EY_sky130_fd_sc_hd__or3b_1".
+Reading "EY_sky130_fd_sc_hd__o32a_1".
+Reading "EY_sky130_fd_sc_hd__a2bb2o_2".
+Reading "EY_sky130_fd_sc_hd__o311a_1".
+Reading "EY_sky130_fd_sc_hd__o221a_1".
+Reading "EY_sky130_fd_sc_hd__o31a_1".
+Reading "EY_sky130_fd_sc_hd__o211a_2".
+Reading "EY_sky130_fd_sc_hd__and3_1".
+Reading "EY_sky130_fd_sc_hd__a211oi_1".
+Reading "EY_sky130_fd_sc_hd__and4_4".
+Reading "EY_sky130_fd_sc_hd__and4_1".
+Reading "EY_sky130_fd_sc_hd__clkbuf_4".
+Reading "EY_sky130_fd_sc_hd__and3b_1".
+Reading "EY_sky130_fd_sc_hd__a211o_4".
+Reading "EY_sky130_fd_sc_hd__a211o_1".
+Reading "EY_sky130_fd_sc_hd__o21ba_1".
+Reading "EY_sky130_fd_sc_hd__a21oi_1".
+Reading "EY_sky130_fd_sc_hd__nor2_1".
+Reading "EY_sky130_fd_sc_hd__nand2_8".
+Reading "EY_sky130_fd_sc_hd__a311o_1".
+Reading "EY_sky130_fd_sc_hd__nor2_2".
+Reading "EY_sky130_fd_sc_hd__a41o_1".
+Reading "EY_sky130_fd_sc_hd__nor3_2".
+Reading "EY_sky130_fd_sc_hd__or4bb_4".
+Reading "EY_sky130_fd_sc_hd__nor3_1".
+Reading "EY_sky130_fd_sc_hd__or4b_4".
+Reading "EY_sky130_fd_sc_hd__or3b_4".
+Reading "EY_sky130_fd_sc_hd__a31o_1".
+Reading "EY_sky130_fd_sc_hd__a211o_2".
+Reading "EY_sky130_fd_sc_hd__or2_2".
+Reading "EY_sky130_fd_sc_hd__a31o_2".
+Reading "EY_sky130_fd_sc_hd__a221o_1".
+Reading "EY_sky130_fd_sc_hd__and4b_4".
+Reading "EY_sky130_fd_sc_hd__and3_4".
+Reading "EY_sky130_fd_sc_hd__mux2_8".
+Reading "EY_sky130_fd_sc_hd__o21ai_2".
+Reading "EY_sky130_fd_sc_hd__and4b_1".
+Reading "EY_sky130_fd_sc_hd__or4b_1".
+Reading "EY_sky130_fd_sc_hd__o211a_4".
+Reading "EY_sky130_fd_sc_hd__a32o_1".
+Reading "EY_sky130_fd_sc_hd__a21boi_1".
+Reading "EY_sky130_fd_sc_hd__o41ai_4".
+Reading "EY_sky130_fd_sc_hd__o31a_2".
+Reading "EY_sky130_fd_sc_hd__nand2_4".
+Reading "EY_sky130_fd_sc_hd__a31oi_4".
+Reading "EY_sky130_fd_sc_hd__and4_2".
+Reading "EY_sky130_fd_sc_hd__nand3_4".
+Reading "EY_sky130_fd_sc_hd__and4b_2".
+Reading "EY_sky130_fd_sc_hd__o41a_4".
+Reading "EY_sky130_fd_sc_hd__and4bb_2".
+Reading "EY_sky130_fd_sc_hd__clkinv_2".
+Reading "EY_sky130_fd_sc_hd__and2b_2".
+Reading "EY_sky130_fd_sc_hd__or4bb_1".
+Reading "EY_sky130_fd_sc_hd__a21oi_2".
+Reading "EY_sky130_fd_sc_hd__a221oi_1".
+Reading "EY_sky130_fd_sc_hd__a31oi_1".
+Reading "EY_sky130_fd_sc_hd__xor2_4".
+Reading "EY_sky130_fd_sc_hd__clkbuf_1".
+Reading "EY_sky130_fd_sc_hd__nand3b_4".
+Reading "EY_sky130_fd_sc_hd__nand2_2".
+Reading "EY_sky130_fd_sc_hd__xnor2_1".
+Reading "EY_sky130_fd_sc_hd__and2_1".
+Reading "EY_sky130_fd_sc_hd__nor2_4".
+Reading "EY_sky130_fd_sc_hd__nand4_4".
+Reading "EY_sky130_fd_sc_hd__a32o_2".
+Reading "EY_sky130_fd_sc_hd__nor4_1".
+Reading "EY_sky130_fd_sc_hd__nand4_1".
+Reading "EY_sky130_fd_sc_hd__xor2_1".
+Reading "EY_sky130_fd_sc_hd__and4bb_4".
+Reading "EY_sky130_fd_sc_hd__a41o_2".
+Reading "EY_sky130_fd_sc_hd__o2bb2a_1".
+Reading "EY_sky130_fd_sc_hd__xnor2_2".
+Reading "EY_sky130_fd_sc_hd__xor2_2".
+Reading "EY_sky130_fd_sc_hd__or2_4".
+Reading "EY_sky130_fd_sc_hd__a2111oi_2".
+Reading "EY_sky130_fd_sc_hd__nor4_4".
+Reading "EY_sky130_fd_sc_hd__mux2_4".
+Reading "EY_sky130_fd_sc_hd__and2b_1".
+Reading "EY_sky130_fd_sc_hd__and2_2".
+Reading "EY_sky130_fd_sc_hd__nor4b_1".
+Reading "EY_sky130_fd_sc_hd__o2111ai_4".
+Reading "EY_sky130_fd_sc_hd__nor4_2".
+Reading "EY_sky130_fd_sc_hd__nand3b_2".
+Reading "EY_sky130_fd_sc_hd__nand3_1".
+Reading "EY_sky130_fd_sc_hd__nand2b_2".
+Reading "EY_sky130_fd_sc_hd__o31ai_1".
+Reading "EY_sky130_fd_sc_hd__o41a_1".
+Reading "EY_sky130_fd_sc_hd__a21bo_1".
+Reading "EY_sky130_fd_sc_hd__o41ai_1".
+Reading "EY_sky130_fd_sc_hd__nand3b_1".
+Reading "EY_sky130_fd_sc_hd__o2111a_1".
+Reading "EY_sky130_fd_sc_hd__o21a_4".
+Reading "EY_sky130_fd_sc_hd__o22a_1".
+Reading "EY_sky130_fd_sc_hd__or3b_2".
+Reading "EY_sky130_fd_sc_hd__nand2b_1".
+Reading "EY_sky130_fd_sc_hd__nor4b_4".
+Reading "EY_sky130_fd_sc_hd__o21bai_1".
+Reading "EY_sky130_fd_sc_hd__nor3_4".
+Reading "EY_sky130_fd_sc_hd__o41a_2".
+Reading "EY_sky130_fd_sc_hd__or4b_2".
+Reading "EY_sky130_fd_sc_hd__a221o_4".
+Reading "EY_sky130_fd_sc_hd__a2111oi_1".
+Reading "EY_sky130_fd_sc_hd__o31a_4".
+Reading "EY_sky130_fd_sc_hd__nor2_8".
+Reading "EY_sky130_fd_sc_hd__clkinv_4".
+Reading "EY_sky130_fd_sc_hd__a221o_2".
+Reading "EY_sky130_fd_sc_hd__o21ai_4".
+Reading "EY_sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "EY_sky130_fd_sc_hd__clkbuf_2".
+Reading "EY_sky130_fd_sc_hd__a31o_4".
+Reading "EY_sky130_fd_sc_hd__ebufn_4".
+Reading "EY_sky130_fd_sc_hd__dlxtp_1".
+Reading "EY_sky130_fd_sc_hd__dlclkp_1".
+Reading "EY_sky130_fd_sc_hd__conb_1".
+Reading "EY_sky130_fd_sc_hd__inv_1".
+Reading "EY_sky130_fd_sc_hd__nor4b_2".
+Reading "EY_sky130_fd_sc_hd__and3b_2".
+Reading "EY_sky130_fd_sc_hd__nor3b_2".
+Reading "EY_RAM256".
+Reading "EY_sky130_fd_sc_hd__a21o_4".
+Reading "EY_sky130_fd_sc_hd__o2111a_4".
+Reading "EY_sky130_fd_sc_hd__a22o_2".
+Reading "EY_sky130_fd_sc_hd__o211ai_4".
+Reading "EY_sky130_fd_sc_hd__o22ai_4".
+Reading "EY_sky130_fd_sc_hd__a221oi_4".
+Reading "EY_sky130_fd_sc_hd__and2b_4".
+Reading "EY_sky130_fd_sc_hd__and3b_4".
+Reading "EY_sky130_fd_sc_hd__and4bb_1".
+Reading "EY_sky130_fd_sc_hd__a21oi_4".
+Reading "EY_sky130_fd_sc_hd__o22ai_1".
+Reading "EY_sky130_fd_sc_hd__inv_4".
+Reading "EY_sky130_fd_sc_hd__a311o_2".
+Reading "EY_sky130_fd_sc_hd__a2111o_1".
+Reading "EY_sky130_fd_sc_hd__o311a_4".
+Reading "EY_sky130_fd_sc_hd__o2111ai_1".
+Reading "EY_sky130_fd_sc_hd__clkinv_8".
+Reading "EY_sky130_fd_sc_hd__nand3_2".
+Reading "EY_sky130_fd_sc_hd__a22oi_1".
+Reading "EY_sky130_fd_sc_hd__nand4b_4".
+Reading "EY_sky130_fd_sc_hd__o221ai_4".
+Reading "EY_sky130_fd_sc_hd__nand4_2".
+Reading "EY_sky130_fd_sc_hd__inv_6".
+Reading "EY_sky130_fd_sc_hd__o2bb2ai_1".
+Reading "EY_sky130_fd_sc_hd__a311oi_4".
+Reading "EY_sky130_fd_sc_hd__o32ai_4".
+Reading "EY_sky130_fd_sc_hd__o211ai_1".
+Reading "EY_sky130_fd_sc_hd__nand4b_1".
+Reading "EY_sky130_fd_sc_hd__o211ai_2".
+Reading "EY_sky130_fd_sc_hd__a22oi_4".
+Reading "EY_sky130_fd_sc_hd__and2_4".
+Reading "EY_sky130_fd_sc_hd__a211oi_4".
+Reading "EY_sky130_fd_sc_hd__nor3b_4".
+Reading "EY_sky130_fd_sc_hd__o22a_2".
+Reading "EY_sky130_fd_sc_hd__a2111oi_4".
+Reading "EY_sky130_fd_sc_hd__nand2b_4".
+Reading "EY_sky130_fd_sc_hd__a2bb2o_4".
+Reading "EY_sky130_fd_sc_hd__o2bb2a_2".
+Reading "EY_sky130_fd_sc_hd__o2111ai_2".
+Reading "EY_sky130_fd_sc_hd__a22oi_2".
+Reading "EY_sky130_fd_sc_hd__nor3b_1".
+Reading "EY_sky130_fd_sc_hd__o2bb2a_4".
+Reading "EY_sky130_fd_sc_hd__o21bai_4".
+Reading "EY_sky130_fd_sc_hd__o311ai_1".
+Reading "EY_sky130_fd_sc_hd__a32oi_2".
+Reading "EY_sky130_fd_sc_hd__o2bb2ai_2".
+Reading "EY_sky130_fd_sc_hd__o311ai_4".
+Reading "EY_sky130_fd_sc_hd__o2bb2ai_4".
+Reading "EY_sky130_fd_sc_hd__o31ai_4".
+Reading "EY_sky130_fd_sc_hd__o221a_2".
+Reading "EY_sky130_fd_sc_hd__o2111a_2".
+Reading "EY_sky130_fd_sc_hd__a31oi_2".
+Reading "EY_sky130_fd_sc_hd__o311a_2".
+Reading "EY_sky130_fd_sc_hd__o22a_4".
+Reading "EY_sky130_fd_sc_hd__a32oi_4".
+Reading "EY_sky130_fd_sc_hd__a211oi_2".
+Reading "EY_sky130_fd_sc_hd__o31ai_2".
+Reading "EY_sky130_fd_sc_hd__o221ai_1".
+Reading "EY_sky130_fd_sc_hd__clkinv_16".
+Reading "EY_sky130_fd_sc_hd__or4bb_2".
+Reading "EY_sky130_fd_sc_hd__a221oi_2".
+Reading "EY_sky130_fd_sc_hd__inv_8".
+Reading "EY_sky130_fd_sc_hd__a311oi_2".
+Reading "EY_sky130_fd_sc_hd__a311oi_1".
+Reading "EY_sky130_fd_sc_hd__o311ai_2".
+Reading "EY_sky130_fd_sc_hd__a32oi_1".
+Reading "EY_sky130_fd_sc_hd__a2bb2oi_2".
+Reading "EY_sky130_fd_sc_hd__a2bb2oi_1".
+Reading "EY_sky130_fd_sc_hd__a2bb2oi_4".
+Reading "EY_sky130_fd_sc_hd__xnor2_4".
+Reading "EY_sky130_fd_sc_hd__inv_12".
+Reading "EY_sky130_fd_sc_hd__a2111o_4".
+Reading "EY_sky130_fd_sc_hd__a32o_4".
+Reading "EY_sky130_fd_sc_hd__o21ba_2".
+Reading "EY_sky130_fd_sc_hd__a41oi_2".
+Reading "EY_sky130_fd_sc_hd__o22ai_2".
+Reading "EY_sky130_fd_sc_hd__o21bai_2".
+Reading "EY_sky130_fd_sc_hd__a41oi_4".
+Reading "EY_sky130_fd_sc_hd__a41o_4".
+Reading "EY_sky130_fd_sc_hd__a311o_4".
+Reading "EY_sky130_fd_sc_hd__o32ai_1".
+Reading "EY_sky130_fd_sc_hd__a21boi_4".
+Reading "EY_sky130_fd_sc_hd__o32ai_2".
+Reading "EY_sky130_fd_sc_hd__a21bo_2".
+Reading "EY_RAM128".
+Reading "mgmt_core_wrapper".
+Reading "gpio_defaults_block_0403".
+Reading "gpio_defaults_block_1800".
+Reading "sky130_fd_sc_hd__inv_8".
+Reading "sky130_fd_sc_hd__dfbbp_1".
+Reading "spare_logic_block".
+Reading "sky130_fd_sc_hd__bufbuf_8".
+Reading "sky130_fd_sc_hvl__conb_1".
+Reading "mgmt_protect_hv".
+Reading "mprj_logic_high".
+Reading "mprj2_logic_high".
+Reading "sky130_fd_sc_hd__inv_12".
+Reading "mgmt_protect".
+Reading "gpio_defaults_block_0801".
+Reading "gpio_control_power_routing_top".
+Reading "gpio_control_power_routing_right".
+Reading "gpio_control_power_routing".
+Reading "caravel_power_routing".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_39".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_19".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_14".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_13".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_7".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_38".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_33".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_32".
+Reading "M3_sky130_fd_bd_sram__openram_dff".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_row_addr_dff".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_wmask_dff".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_cr_3".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_col_addr_dff".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_data_dff".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_16".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_29".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_28".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_11".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_360_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_12".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_1".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dli".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sli_dactive".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_1".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w1_680_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w1_680_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_3".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w0_740_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w1_260_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_2".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_0".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m7_w1_680_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m7_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_4".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_1".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_0".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pand2_1".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m24_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m24_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_14".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m8_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m8_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_13".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_12".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_11".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_0".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_3".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_17".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_delay_chain".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m18_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m18_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_16".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_5".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dactive".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pnand3".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pand3_0".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m22_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m22_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_15".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_4".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pand3".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m42_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m42_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_10".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m15_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m15_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_9".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m5_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_8".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w1_260_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_7".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_2".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_rw".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_cr_5".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array_0".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m41_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m41_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_20".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m14_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m14_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_19".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w1_680_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_18".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_6".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_r".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_cr_4".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_20".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_17".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_0".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pand2_0".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4_0".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_15".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w7_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w7_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec_0".
+Reading "M3_sky130_fd_bd_sram__openram_dp_nand2_dec".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec_0".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver_array".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec".
+Reading "M3_sky130_fd_bd_sram__openram_dp_nand3_dec".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_and3_dec".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode3x8".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_decoder".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_port_address_0".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_port_address".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_27".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_26".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_25".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_24".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w2_880_sli_dli".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_0".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array_0".
+Reading "M3_sky130_fd_bd_sram__openram_sense_amp".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_sense_amp_array".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_23".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_21".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_22".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w0_550_sli_dli".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_1".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array_0".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_port_data_0".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pnand2".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pand2".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_write_mask_and_array".
+Reading "M3_sky130_fd_bd_sram__openram_write_driver".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_write_driver_array".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_0".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_port_data".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_9".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_8".
+Reading "M3_sky130_fd_bd_sram__openram_dp_cell_cap_row".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array_0".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array".
+Reading "M3_sky130_fd_bd_sram__openram_dp_cell_cap_col".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array_0".
+Reading "M3_sky130_fd_bd_sram__openram_dp_cell_dummy".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_dummy_array".
+Reading "M3_sky130_fd_bd_sram__openram_dp_cell_replica".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_replica_column_0".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_replica_column".
+Reading "M3_sky130_fd_bd_sram__openram_dp_cell".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_bitcell_array".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_replica_bitcell_array".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_bank".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8".
+Reading "M3_sky130_fd_sc_hd__o32a_2".
+Reading "M3_sky130_fd_sc_hd__o21ai_2".
+Reading "M3_sky130_ef_sc_hd__decap_12".
+Reading "M3_sky130_fd_sc_hd__o221a_2".
+Reading "M3_sky130_fd_sc_hd__o2bb2a_2".
+Reading "M3_sky130_fd_sc_hd__a221o_2".
+Reading "M3_sky130_fd_sc_hd__buf_2".
+Reading "M3_sky130_fd_sc_hd__and4b_2".
+Reading "M3_sky130_fd_sc_hd__nand2_2".
+Reading "M3_sky130_fd_sc_hd__a31oi_2".
+Reading "M3_sky130_fd_sc_hd__or4_2".
+Reading "M3_sky130_fd_sc_hd__or3b_2".
+Reading "M3_sky130_fd_sc_hd__or3_2".
+Reading "M3_sky130_fd_sc_hd__and2b_2".
+Reading "M3_sky130_fd_sc_hd__a31o_2".
+Reading "M3_sky130_fd_sc_hd__xor2_2".
+Reading "M3_sky130_fd_sc_hd__nor2_2".
+Reading "M3_sky130_fd_sc_hd__a22o_2".
+Reading "M3_sky130_fd_sc_hd__o21a_2".
+Reading "M3_sky130_fd_sc_hd__a21oi_2".
+Reading "M3_sky130_fd_sc_hd__nand2b_2".
+Reading "M3_sky130_fd_sc_hd__o211a_2".
+Reading "M3_sky130_fd_sc_hd__a21o_2".
+Reading "M3_sky130_fd_sc_hd__o22a_2".
+Reading "M3_sky130_fd_sc_hd__nand3b_2".
+Reading "M3_sky130_fd_sc_hd__and4_2".
+Reading "M3_sky130_fd_sc_hd__a311o_2".
+Reading "M3_sky130_fd_sc_hd__clkbuf_2".
+Reading "M3_sky130_fd_sc_hd__a211o_2".
+Reading "M3_sky130_fd_sc_hd__decap_6".
+Reading "M3_sky130_fd_sc_hd__clkinv_2".
+Reading "M3_sky130_fd_sc_hd__and3_2".
+Reading "M3_sky130_fd_sc_hd__a32o_2".
+Reading "M3_sky130_fd_sc_hd__mux2_1".
+Reading "M3_sky130_fd_sc_hd__xnor2_2".
+Reading "M3_sky130_fd_sc_hd__and2_2".
+Reading "M3_sky130_fd_sc_hd__dfrtp_2".
+Reading "M3_sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "M3_sky130_fd_sc_hd__inv_2".
+Reading "M3_sky130_fd_sc_hd__conb_1".
+Reading "M3_sky130_fd_sc_hd__or2_2".
+Reading "M3_sky130_fd_sc_hd__decap_8".
+Reading "M3_sky130_fd_sc_hd__fill_1".
+Reading "M3_sky130_fd_sc_hd__fill_2".
+Reading "M3_sky130_fd_sc_hd__decap_4".
+Reading "M3_sky130_fd_sc_hd__decap_3".
+Reading "M3_sky130_fd_sc_hd__clkbuf_1".
+Reading "M3_sky130_fd_sc_hd__a2bb2o_2".
+Reading "M3_sky130_fd_sc_hd__a22oi_1".
+Reading "M3_sky130_fd_sc_hd__and4bb_4".
+Reading "M3_sky130_fd_sc_hd__o211ai_4".
+Reading "M3_sky130_fd_sc_hd__nand4_1".
+Reading "M3_sky130_fd_sc_hd__a21bo_2".
+Reading "M3_sky130_fd_sc_hd__nor4b_4".
+Reading "M3_sky130_fd_sc_hd__o2111a_1".
+Reading "M3_sky130_fd_sc_hd__o41a_1".
+Reading "M3_sky130_fd_sc_hd__a21o_4".
+Reading "M3_sky130_fd_sc_hd__o22ai_1".
+Reading "M3_sky130_fd_sc_hd__a31oi_1".
+Reading "M3_sky130_fd_sc_hd__a41o_1".
+Reading "M3_sky130_fd_sc_hd__o32a_4".
+Reading "M3_sky130_fd_sc_hd__a22oi_2".
+Reading "M3_sky130_fd_sc_hd__nor4_1".
+Reading "M3_sky130_fd_sc_hd__and4b_1".
+Reading "M3_sky130_fd_sc_hd__nand3_4".
+Reading "M3_sky130_fd_sc_hd__a311o_1".
+Reading "M3_sky130_fd_sc_hd__o211ai_2".
+Reading "M3_sky130_fd_sc_hd__o31ai_4".
+Reading "M3_sky130_fd_sc_hd__and3_4".
+Reading "M3_sky130_fd_sc_hd__dfstp_4".
+Reading "M3_sky130_fd_sc_hd__a31o_4".
+Reading "M3_sky130_fd_sc_hd__xor2_1".
+Reading "M3_sky130_fd_sc_hd__a21boi_1".
+Reading "M3_sky130_fd_sc_hd__dfstp_2".
+Reading "M3_sky130_fd_sc_hd__nand2_8".
+Reading "M3_sky130_fd_sc_hd__and3b_1".
+Reading "M3_sky130_fd_sc_hd__buf_12".
+Reading "M3_sky130_fd_sc_hd__o22ai_4".
+Reading "M3_sky130_fd_sc_hd__inv_4".
+Reading "M3_sky130_fd_sc_hd__o2111ai_4".
+Reading "M3_sky130_fd_sc_hd__clkinv_4".
+Reading "M3_sky130_fd_sc_hd__a21bo_1".
+Reading "M3_sky130_fd_sc_hd__xnor2_1".
+Reading "M3_sky130_fd_sc_hd__o211a_1".
+Reading "M3_sky130_fd_sc_hd__and2_4".
+Reading "M3_sky130_fd_sc_hd__a21oi_4".
+Reading "M3_sky130_fd_sc_hd__o22ai_2".
+Reading "M3_sky130_fd_sc_hd__a2111o_1".
+Reading "M3_sky130_fd_sc_hd__nor2_8".
+Reading "M3_sky130_fd_sc_hd__o21ba_1".
+Reading "M3_sky130_fd_sc_hd__or2_4".
+Reading "M3_sky130_fd_sc_hd__o221a_1".
+Reading "M3_sky130_fd_sc_hd__o31a_2".
+Reading "M3_sky130_fd_sc_hd__a22oi_4".
+Reading "M3_sky130_fd_sc_hd__dfxtp_4".
+Reading "M3_sky130_fd_sc_hd__o311a_1".
+Reading "M3_sky130_fd_sc_hd__mux4_2".
+Reading "M3_sky130_fd_sc_hd__a32o_1".
+Reading "M3_sky130_fd_sc_hd__or3b_1".
+Reading "M3_sky130_fd_sc_hd__a22o_4".
+Reading "M3_sky130_fd_sc_hd__a211oi_4".
+Reading "M3_sky130_fd_sc_hd__a221oi_1".
+Reading "M3_sky130_fd_sc_hd__a221oi_4".
+Reading "M3_sky130_fd_sc_hd__o311a_2".
+Reading "M3_sky130_fd_sc_hd__o31a_1".
+Reading "M3_sky130_fd_sc_hd__a31o_1".
+Reading "M3_sky130_fd_sc_hd__dfxtp_2".
+Reading "M3_sky130_fd_sc_hd__a21oi_1".
+Reading "M3_sky130_fd_sc_hd__a211o_4".
+Reading "M3_sky130_fd_sc_hd__buf_8".
+Reading "M3_sky130_fd_sc_hd__dfrtp_4".
+Reading "M3_sky130_fd_sc_hd__nor2_4".
+Reading "M3_sky130_fd_sc_hd__a211o_1".
+Reading "M3_sky130_fd_sc_hd__o2bb2a_1".
+Reading "M3_sky130_fd_sc_hd__o22a_1".
+Reading "M3_sky130_fd_sc_hd__mux2_2".
+Reading "M3_sky130_fd_sc_hd__o21ai_1".
+Reading "M3_sky130_fd_sc_hd__o21ai_4".
+Reading "M3_sky130_fd_sc_hd__a211oi_1".
+Reading "M3_sky130_fd_sc_hd__mux4_1".
+Reading "M3_sky130_fd_sc_hd__and4bb_1".
+Reading "M3_sky130_fd_sc_hd__mux2_4".
+Reading "M3_sky130_fd_sc_hd__and2_1".
+Reading "M3_sky130_fd_sc_hd__or4_4".
+Reading "M3_sky130_fd_sc_hd__or3_1".
+Reading "M3_sky130_fd_sc_hd__nand2_4".
+Reading "M3_sky130_fd_sc_hd__or4b_4".
+Reading "M3_sky130_fd_sc_hd__or3_4".
+Reading "M3_sky130_fd_sc_hd__nor3_1".
+Reading "M3_sky130_fd_sc_hd__a22o_1".
+Reading "M3_sky130_fd_sc_hd__or2_1".
+Reading "M3_sky130_fd_sc_hd__and4_1".
+Reading "M3_sky130_fd_sc_hd__nand2_1".
+Reading "M3_sky130_fd_sc_hd__a21o_1".
+Reading "M3_sky130_fd_sc_hd__and2b_1".
+Reading "M3_sky130_fd_sc_hd__or4b_1".
+Reading "M3_sky130_fd_sc_hd__nor4_4".
+Reading "M3_sky130_fd_sc_hd__nand3_1".
+Reading "M3_sky130_fd_sc_hd__nor3_4".
+Reading "M3_sky130_fd_sc_hd__and3_1".
+Reading "M3_sky130_fd_sc_hd__a2bb2o_1".
+Reading "M3_sky130_fd_sc_hd__dfstp_1".
+Reading "M3_sky130_fd_sc_hd__dfxtp_1".
+Reading "M3_sky130_fd_sc_hd__or4_1".
+Reading "M3_sky130_fd_sc_hd__o21a_1".
+Reading "M3_sky130_fd_sc_hd__a221o_1".
+Reading "M3_sky130_fd_sc_hd__clkbuf_16".
+Reading "M3_sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "M3_sky130_fd_sc_hd__nor2_1".
+Reading "M3_sky130_fd_sc_hd__dfrtp_1".
+Reading "M3_sky130_fd_sc_hd__clkbuf_4".
+Reading "M3_sky130_fd_sc_hd__diode_2".
+Reading "M3_sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "M3_sky130_fd_sc_hd__clkbuf_8".
+Reading "M3_sky130_fd_sc_hd__buf_4".
+Reading "M3_sky130_fd_sc_hd__buf_6".
+Reading "M3_sky130_fd_sc_hd__o31ai_1".
+Reading "M3_sky130_fd_sc_hd__nand2b_1".
+Reading "M3_sky130_fd_sc_hd__a311oi_1".
+Reading "M3_sky130_fd_sc_hd__nand2b_4".
+Reading "M3_sky130_fd_sc_hd__or4bb_1".
+Reading "M3_sky130_fd_sc_hd__o32a_1".
+Reading "M3_sky130_fd_sc_hd__o21bai_1".
+Reading "M3_sky130_fd_sc_hd__nor3_2".
+Reading "M3_sky130_fd_sc_hd__nand4b_1".
+Reading "M3_sky130_fd_sc_hd__xor2_4".
+Reading "M3_sky130_fd_sc_hd__o21ba_2".
+Reading "M3_sky130_fd_sc_hd__a2111o_2".
+Reading "M3_sky130_fd_sc_hd__or3b_4".
+Reading "M3_sky130_fd_sc_hd__a31oi_4".
+Reading "M3_sky130_fd_sc_hd__nand3b_1".
+Reading "M3_sky130_fd_sc_hd__nor4b_2".
+Reading "M3_sky130_fd_sc_hd__a41o_2".
+Reading "M3_sky130_fd_sc_hd__nor3b_4".
+Reading "M3_sky130_fd_sc_hd__a2111o_4".
+Reading "M3_sky130_fd_sc_hd__a2111oi_4".
+Reading "M3_sky130_fd_sc_hd__o32ai_1".
+Reading "M3_sky130_fd_sc_hd__and4bb_2".
+Reading "M3_sky130_fd_sc_hd__or4b_2".
+Reading "M3_sky130_fd_sc_hd__nor3b_1".
+Reading "M3_sky130_fd_sc_hd__nor4_2".
+Reading "M3_sky130_fd_sc_hd__a311oi_4".
+Reading "M3_sky130_fd_sc_hd__o21bai_2".
+Reading "M3_sky130_fd_sc_hd__nor3b_2".
+Reading "M3_sky130_fd_sc_hd__a311oi_2".
+Reading "M3_sky130_fd_sc_hd__and3b_4".
+Reading "M3_sky130_fd_sc_hd__a2bb2o_4".
+Reading "M3_sky130_fd_sc_hd__a21bo_4".
+Reading "M3_sky130_fd_sc_hd__xnor2_4".
+Reading "M3_sky130_fd_sc_hd__o311ai_4".
+Reading "M3_sky130_fd_sc_hd__o2bb2a_4".
+Reading "M3_sky130_fd_sc_hd__o211a_4".
+Reading "M3_sky130_fd_sc_hd__and2b_4".
+Reading "M3_sky130_fd_sc_hd__o21bai_4".
+Reading "M3_sky130_fd_sc_hd__nand3b_4".
+Reading "M3_sky130_fd_sc_hd__o2111ai_1".
+Reading "M3_sky130_fd_sc_hd__nand4_4".
+Reading "M3_sky130_fd_sc_hd__o221ai_2".
+Reading "M3_sky130_fd_sc_hd__o211ai_1".
+Reading "M3_sky130_fd_sc_hd__o2bb2ai_4".
+Reading "M3_sky130_fd_sc_hd__o22a_4".
+Reading "M3_sky130_fd_sc_hd__nor4b_1".
+Reading "M3_sky130_fd_sc_hd__o2111a_2".
+Reading "M3_ycr_core_top".
+Reading "M3_sky130_fd_sc_hd__and3b_2".
+Reading "M3_sky130_fd_sc_hd__nand4_2".
+Reading "M3_sky130_fd_sc_hd__o31ai_2".
+Reading "M3_sky130_fd_sc_hd__nand3_2".
+Reading "M3_sky130_fd_sc_hd__or2b_1".
+Reading "M3_sky130_fd_sc_hd__o2bb2ai_2".
+Reading "M3_sky130_fd_sc_hd__or2b_2".
+Reading "M3_sky130_fd_sc_hd__and4_4".
+Reading "M3_sky130_fd_sc_hd__a221o_4".
+Reading "M3_sky130_fd_sc_hd__or4bb_4".
+Reading "M3_sky130_fd_sc_hd__or2b_4".
+Reading "M3_sky130_fd_sc_hd__o41ai_4".
+Reading "M3_sky130_fd_sc_hd__a21boi_4".
+Reading "M3_sky130_fd_sc_hd__o221ai_1".
+Reading "M3_sky130_fd_sc_hd__o31a_4".
+Reading "M3_sky130_fd_sc_hd__buf_1".
+Reading "M3_sky130_fd_sc_hd__dlygate4sd1_1".
+Reading "M3_sky130_fd_sc_hd__mux2_8".
+Reading "M3_ycr4_iconnect".
+Reading "M3_sky130_fd_sc_hd__a2111oi_2".
+Reading "M3_sky130_fd_sc_hd__a2111oi_1".
+Reading "M3_sky130_fd_sc_hd__o2bb2ai_1".
+Reading "M3_sky130_fd_sc_hd__o41a_4".
+Reading "M3_sky130_fd_sc_hd__nand4b_4".
+Reading "M3_sky130_fd_sc_hd__a32o_4".
+Reading "M3_sky130_fd_sc_hd__or4bb_2".
+Reading "M3_ycr_intf".
+Reading "M3_switchn".
+Reading "M3_resistor".
+Reading "M3_resistor_3xh".
+Reading "M3_switch2".
+Reading "M3_switch2n".
+Reading "M3_2bit_DAC".
+Reading "M3_resistor_h".
+Reading "M3_3bit_DAC".
+Reading "M3_4bit_DAC".
+Reading "M3_5bit_DAC".
+Reading "M3_6bit_DAC".
+Reading "M3_7bit_DAC".
+Reading "M3_8bit_DAC".
+Reading "M3_2x8bit_DAC".
+Reading "M3_4x8bit_DAC".
+Reading "M3_dac_top".
+Reading "M3_sky130_fd_sc_hd__einvn_8".
+Reading "M3_sky130_fd_sc_hd__clkinv_1".
+Reading "M3_sky130_fd_sc_hd__einvp_2".
+Reading "M3_sky130_fd_sc_hd__einvn_2".
+Reading "M3_sky130_fd_sc_hd__a21boi_2".
+Reading "M3_sky130_fd_sc_hd__clkinv_8".
+Reading "M3_sky130_fd_sc_hd__einvp_1".
+Reading "M3_dg_pll".
+Reading "M3_sky130_fd_sc_hd__a41oi_4".
+Reading "M3_sky130_fd_sc_hd__o21a_4".
+Reading "M3_sky130_fd_sc_hd__o311a_4".
+Reading "M3_sky130_fd_sc_hd__o221a_4".
+Reading "M3_sky130_fd_sc_hd__a41o_4".
+Reading "M3_wb_interconnect".
+Reading "M3_sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "M3_sky130_fd_sc_hd__o41a_2".
+Reading "M3_sky130_fd_sc_hd__a211oi_2".
+Reading "M3_sky130_fd_sc_hd__clkdlybuf4s50_1".
+Reading "M3_qspim_top".
+Reading "M3_sky130_fd_sc_hd__dlclkp_1".
+Reading "M3_sky130_fd_sc_hd__dlclkp_4".
+Reading "M3_sky130_fd_sc_hd__a32oi_4".
+Reading "M3_sky130_fd_sc_hd__o311ai_2".
+Reading "M3_sky130_fd_sc_hd__o2111ai_2".
+Reading "M3_wb_host".
+Reading "M3_sky130_fd_sc_hd__and4b_4".
+Reading "M3_sky130_fd_sc_hd__nor2b_2".
+Reading "M3_sky130_fd_sc_hd__nor2b_1".
+Reading "M3_uart_i2c_usb_spi_top".
+Reading "M3_sky130_fd_sc_hd__dlxtn_1".
+Reading "M3_sky130_fd_sc_hd__dlxtn_2".
+Reading "M3_sky130_fd_sc_hd__nand4b_2".
+Reading "M3_sky130_fd_sc_hd__a32oi_1".
+Reading "M3_pinmux_top".
+Reading "user_project_wrapper".
+Reading "sky130_ef_io__com_bus_slice_20um".
+Reading "sky130_fd_io__corner_bus_overlay".
+Reading "sky130_ef_io__corner_pad".
+Reading "sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um".
+Reading "sky130_ef_io__com_bus_slice_1um".
+Reading "sky130_ef_io__com_bus_slice_5um".
+Reading "sky130_ef_io__com_bus_slice_10um".
+Reading "sky130_fd_pr__hvdfl1sd__example_5595914180851".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808664".
+Reading "sky130_fd_io__sio_clamp_pcap_4x5".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808680".
+Reading "sky130_fd_io__esd_rcclamp_nfetcap".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808336".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808666".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808665".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808678".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808679".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808677".
+Reading "sky130_fd_pr__via_pol1__example_5595914180839".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808667".
+Reading "sky130_fd_pr__hvdftpl1s__example_55959141808671".
+Reading "sky130_fd_pr__hvdftpl1s2__example_55959141808672".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808673".
+Reading "sky130_fd_pr__dfl1__example_55959141808663".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808660".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808670".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808668".
+Reading "sky130_fd_pr__hvdftpl1s__example_55959141808675".
+Reading "sky130_fd_pr__hvdftpl1s2__example_55959141808676".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808674".
+Reading "sky130_fd_pr__dfl1__example_55959141808662".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808661".
+Reading "sky130_fd_pr__via_l1m1__example_559591418084".
+Reading "sky130_fd_pr__genrivetdlring__example_559591418082".
+Reading "sky130_fd_pr__gendlring__example_559591418081".
+Reading "sky130_fd_pr__padplhp__example_559591418080".
+Reading "sky130_fd_io__pad_esd".
+Reading "sky130_fd_io__com_bus_slice".
+Reading "sky130_fd_io__com_bus_hookup".
+Reading "sky130_fd_io__com_busses_esd".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808669".
+Reading "sky130_fd_io__top_ground_hvc_wpad".
+Reading "sky130_fd_io__overlay_vssa_hvc".
+Reading "sky130_ef_io__hvc_vdda_overlay".
+Reading "sky130_ef_io__vssa_hvc_clamped_pad".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808719".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808767".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808765".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808764".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808720".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808718".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808717".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808716".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808243".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808723".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808722".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180890".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808721".
+Reading "sky130_fd_io__xres_inv_hysv2".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180838".
+Reading "sky130_fd_io__tk_tie_r_out_esd".
+Reading "sky130_fd_io__res250_sub_small".
+Reading "sky130_fd_io__res250only_small".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808264".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180858".
+Reading "sky130_fd_pr__via_pol1__example_5595914180833".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180864".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808715".
+Reading "sky130_fd_pr__res_bent_po__example_5595914180863".
+Reading "sky130_fd_pr__res_bent_po__example_5595914180862".
+Reading "sky130_fd_io__tk_em1s_cdns_55959141808288".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180859".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808289".
+Reading "sky130_fd_io__com_res_weak_v2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808274".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808728".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808727".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808726".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808725".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808724".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808554".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808553".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808552".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808551".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808402".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808350".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808261".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808260".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808259".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808400".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808372".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808326".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808290".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808128".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808127".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180897".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180819".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808555".
+Reading "sky130_fd_pr__via_pol1__example_55959141808147".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808157".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808156".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808155".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808154".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808153".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808152".
+Reading "sky130_fd_pr__tpl1__example_55959141808151".
+Reading "sky130_fd_pr__tpl1__example_55959141808150".
+Reading "sky130_fd_pr__tpl1__example_55959141808149".
+Reading "sky130_fd_pr__tpl1__example_55959141808148".
+Reading "sky130_fd_pr__dfl1__example_55959141808158".
+Reading "sky130_fd_io__signal_5_sym_hv_local_5term".
+Reading "sky130_fd_io__gpio_buf_localesdv2".
+Reading "sky130_fd_pr__via_pol1__example_559591418083".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808137".
+Reading "sky130_fd_pr__dfl1sd__example_559591418086".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808371".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808370".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808369".
+Reading "sky130_fd_io__hvsbt_inv_x1".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808316".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808421".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808385".
+Reading "sky130_fd_pr__dfl1sd__example_559591418088".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808422".
+Reading "sky130_fd_io__hvsbt_inv_x2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808612".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808616".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808615".
+Reading "sky130_fd_io__hvsbt_inv_x4".
+Reading "sky130_fd_pr__hvdfm1sd__example_5595914180848".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180849".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808766".
+Reading "sky130_fd_pr__via_m2m3__example_55959141808714".
+Reading "sky130_fd_pr__via_pol1_centered__example_559591418081".
+Reading "sky130_fd_io__tk_em2s_cdns_55959141808652".
+Reading "sky130_fd_io__tk_em2o_cdns_55959141808653".
+Reading "sky130_fd_pr__via_l1m1_centered__example_5595914180812".
+Reading "sky130_fd_pr__via_l1m1_centered__example_5595914180811".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418086".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418084".
+Reading "sky130_fd_pr__hvdftpm1s2__example_55959141808659".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808658".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808657".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808202".
+Reading "sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2".
+Reading "sky130_fd_io__gpio_pudrvr_strong_axres4v2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808273".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808740".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808739".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808738".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808737".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808736".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808735".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808734".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808733".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808732".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808731".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808730".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808752".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808751".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808750".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808749".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808748".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808747".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808746".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808745".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808744".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808743".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808742".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808741".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808324".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808270".
+Reading "sky130_fd_pr__dfl1__example_55959141808187".
+Reading "sky130_fd_pr__res_generic_nd__example_55959141808755".
+Reading "sky130_fd_pr__res_generic_nd__example_55959141808754".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808338".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808337".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808763".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808700".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808559".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808762".
+Reading "sky130_fd_pr__dfl1__example_55959141808729".
+Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808758".
+Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808757".
+Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808756".
+Reading "sky130_fd_io__xres_tk_p_em1c_cdns_55959141808761".
+Reading "sky130_fd_io__xres_tk_p_em1c_cdns_55959141808760".
+Reading "sky130_fd_io__xres_tk_p_em1c_cdns_55959141808759".
+Reading "sky130_fd_io__xres_p_em1c_cdns_55959141808753".
+Reading "sky130_fd_io__xres2v2_rcfilter_lpfv2".
+Reading "sky130_fd_io__tk_em1o_cdns_5595914180860".
+Reading "sky130_fd_pr__res_bent_po__example_5595914180861".
+Reading "sky130_fd_io__com_res_weak_bentbigres".
+Reading "sky130_fd_io__com_res_weak".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180857".
+Reading "sky130_fd_pr__hvdftpm1s2__example_55959141808649".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808651".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808650".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808648".
+Reading "sky130_fd_pr__hvdftpl1s__example_55959141808646".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808647".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808645".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808378".
+Reading "sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2".
+Reading "sky130_fd_io__gpio_pddrvr_strong_xres4v2".
+Reading "sky130_fd_io__top_gpio_pad".
+Reading "sky130_fd_io__com_busses".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808768".
+Reading "sky130_fd_pr__res_bent_nd__example_55959141808769".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808787".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808786".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808782".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808785".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808449".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808784".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808452".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808783".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808781".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808780".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808779".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808233".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180827".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808778".
+Reading "sky130_fd_pr__hvdfm1sd__example_5595914180835".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808777".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808776".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808775".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808242".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808774".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180829".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808773".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808237".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808772".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808771".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808770".
+Reading "sky130_fd_io__tap_1".
+Reading "sky130_fd_io__inv_1".
+Reading "sky130_fd_pr__pfet_01v8__example_559591418085".
+Reading "sky130_fd_pr__nfet_01v8__example_559591418089".
+Reading "sky130_fd_pr__nfet_01v8__example_559591418087".
+Reading "sky130_fd_io__hvsbt_nand2".
+Reading "sky130_fd_io__xres4v2_in_buf".
+Reading "sky130_fd_io__top_xres4v2".
+Reading "sky130_fd_sc_hd__fill_4".
+Reading "sky130_fd_sc_hd__fill_8".
+Reading "constant_block".
+Reading "sky130_fd_io__res75only_small".
+Reading "sky130_fd_io__com_bus_slice_m4".
+Reading "sky130_fd_io__overlay_gpiov2_m4".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808420".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808419".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808418".
+Reading "sky130_fd_io__hvsbt_nor".
+Reading "sky130_fd_io__hvsbt_nand2v2".
+Reading "sky130_fd_io__gpiov2_ictl_logic".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808190".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808611".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180811".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808549".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808548".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808191".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808189".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808517".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808518".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808610".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808609".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180815".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180816".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808608".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808604".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808533".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808529".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180884".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808230".
+Reading "sky130_fd_io__gpiov2_in_buf".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808537".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808106".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808481".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808607".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808504".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808600".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808550".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808528".
+Reading "sky130_fd_io__gpiov2_ipath_hvls".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808595".
+Reading "sky130_fd_pr__nfet_01v8__example_5595914180825".
+Reading "sky130_fd_io__gpiov2_inbuf_lvinv_x1".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180812".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808599".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808598".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808597".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808596".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808547".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808546".
+Reading "sky130_fd_io__gpiov2_ipath_lvls".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808606".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180875".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808605".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808540".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808603".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808602".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808601".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808535".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808527".
+Reading "sky130_fd_io__gpiov2_vcchib_in_buf".
+Reading "sky130_fd_io__gpiov2_ibuf_se".
+Reading "sky130_fd_io__gpiov2_buf_localesd".
+Reading "sky130_fd_io__gpiov2_ipath".
+Reading "sky130_fd_io__tk_em2s_cdns_55959141808438".
+Reading "sky130_fd_io__tk_em2o_cdns_55959141808439".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180882".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180881".
+Reading "sky130_fd_io__tk_em1o_cdns_5595914180880".
+Reading "sky130_fd_io__tk_em1o_cdns_5595914180879".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808430".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180823".
+Reading "sky130_fd_pr__pfet_01v8__example_5595914180822".
+Reading "sky130_fd_pr__pfet_01v8__example_5595914180813".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808624".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808510".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808623".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808622".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808621".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808620".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808619".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808618".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808116".
+Reading "sky130_fd_io__com_ctl_lsv2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808394".
+Reading "sky130_fd_pr__via_pol1__example_55959141808298".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808440".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180878".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808434".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808435".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808433".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808432".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808102".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808431".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808115".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808429".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808428".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808100".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808140".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808427".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808426".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808280".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808425".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808424".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808423".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808306".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808383".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808382".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808380".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808379".
+Reading "sky130_fd_io__com_ctl_ls_v2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808617".
+Reading "sky130_fd_io__com_ctl_ls_en_1_v2".
+Reading "sky130_fd_io__com_ctl_ls_1v2".
+Reading "sky130_fd_io__gpiov2_ctl_lsbank".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808614".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808613".
+Reading "sky130_fd_io__hvsbt_inv_x8v2".
+Reading "sky130_fd_io__hvsbt_inv_x8".
+Reading "sky130_fd_io__com_ctl_ls".
+Reading "sky130_fd_io__com_ctl_hldv2".
+Reading "sky130_fd_io__gpiov2_ctl".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808178".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808591".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808594".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808593".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808488".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808592".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808586".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808122".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808123".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808477".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808476".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808475".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808589".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808570".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808569".
+Reading "sky130_fd_io__gpiov2_amux_ctl_lshv2hv".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808588".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808587".
+Reading "sky130_fd_io__gpiov2_amux_ctl_lshv2hv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808590".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808460".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808468".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808467".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808466".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808465".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808464".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808463".
+Reading "sky130_fd_io__gpiov2_amux_ctl_ls".
+Reading "sky130_fd_io__gpiov2_amux_ctl_inv_1".
+Reading "sky130_fd_io__gpiov2_amux_ls".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808573".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808572".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808579".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808578".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808577".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808576".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808566".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180868".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180869".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808565".
+Reading "sky130_fd_io__gpiov2_amx_pucsd_inv".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808441".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808571".
+Reading "sky130_fd_io__gpiov2_amx_inv4".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808567".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808568".
+Reading "sky130_fd_io__gpiov2_amux_drvr_lshv2hv".
+Reading "sky130_fd_io__gpiov2_amux_drvr_lshv2hv2".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808581".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808580".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808278".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808462".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808583".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808582".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808498".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808497".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808496".
+Reading "sky130_fd_io__gpiov2_amux_drvr_ls".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808574".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808575".
+Reading "sky130_fd_io__amx_inv1".
+Reading "sky130_fd_io__gpiov2_amux_drvr".
+Reading "sky130_fd_io__xor2_1".
+Reading "sky130_fd_io__nor2_1".
+Reading "sky130_fd_io__nand2_1".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808200".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808457".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808451".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808450".
+Reading "sky130_fd_pr__hvdfl1sd__example_5595914180894".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808584".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808455".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808447".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808445".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808248".
+Reading "sky130_fd_io__gpiov2_amux_nand5".
+Reading "sky130_fd_pr__dfm1sd__example_55959141808258".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808585".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808446".
+Reading "sky130_fd_io__gpiov2_amux_nand4".
+Reading "sky130_fd_io__gpiov2_amux_decoder".
+Reading "sky130_fd_io__gpiov2_amux_ctl_logic".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808563".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808564".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808562".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808251".
+Reading "sky130_fd_pr__dfm1sd2__example_55959141808561".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808560".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808558".
+Reading "sky130_fd_io__amux_switch_1v2b".
+Reading "sky130_fd_io__gpiov2_amux".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808416".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808417".
+Reading "sky130_fd_io__hvsbt_xorv2".
+Reading "sky130_fd_io__hvsbt_xor".
+Reading "sky130_fd_io__com_ctl_ls_octl".
+Reading "sky130_fd_io__gpiov2_octl".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808267".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808266".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808642".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808184".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808141".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808643".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808183".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808139".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808636".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808635".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808634".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808633".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808632".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808630".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808638".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808637".
+Reading "sky130_fd_io__gpiov2_pdpredrvr_strong_nr3".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808629".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808628".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808627".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808626".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808354".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808631".
+Reading "sky130_fd_io__gpiov2_pdpredrvr_strong_nr2".
+Reading "sky130_fd_pr__nfet_01v8__example_5595914180888".
+Reading "sky130_fd_io__gpiov2_octl_mux".
+Reading "sky130_fd_pr__via_pol1__example_55959141808322".
+Reading "sky130_fd_pr__via_pol1__example_55959141808321".
+Reading "sky130_fd_pr__via_pol1__example_55959141808320".
+Reading "sky130_fd_pr__via_pol1__example_55959141808294".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808325".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808323".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808291".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808641".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808640".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808639".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808348".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808347".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808194".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808346".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808345".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808344".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808343".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808334".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808333".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808332".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808331".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808330".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808329".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808304".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808134".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808328".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808327".
+Reading "sky130_fd_io__com_pdpredrvr_pbiasv2".
+Reading "sky130_fd_io__gpiov2_pdpredrvr_strong".
+Reading "sky130_fd_pr__via_pol1__example_55959141808272".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808271".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808143".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808142".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808101".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808144".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_5595914180899".
+Reading "sky130_fd_pr__via_pol1__example_55959141808275".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808276".
+Reading "sky130_fd_pr__res_generic_po__example_55959141808286".
+Reading "sky130_fd_pr__res_generic_po__example_55959141808285".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808284".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808283".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808644".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808287".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808282".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808281".
+Reading "sky130_fd_io__gpiov2_pupredrvr_strong_nd2_a".
+Reading "sky130_fd_io__gpiov2_pupredrvr_strong_nd2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808297".
+Reading "sky130_fd_pr__via_pol1__example_55959141808296".
+Reading "sky130_fd_pr__via_pol1__example_55959141808295".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808293".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808292".
+Reading "sky130_fd_pr__tpl1__example_55959141808300".
+Reading "sky130_fd_pr__tpl1__example_55959141808299".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808319".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808318".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808317".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808315".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808314".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808313".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808312".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808311".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808310".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808309".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808308".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808307".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808305".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808303".
+Reading "sky130_fd_io__tk_em1s_cdns_55959141808301".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808302".
+Reading "sky130_fd_io__feascom_pupredrvr_nbiasv2".
+Reading "sky130_fd_io__gpio_pupredrvr_strongv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808361".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808360".
+Reading "sky130_fd_io__feas_com_pupredrvr_weak".
+Reading "sky130_fd_pr__via_pol1__example_5595914180854".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808363".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808362".
+Reading "sky130_fd_io__com_pupredrvr_strong_slowv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808366".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808365".
+Reading "sky130_fd_io__com_pdpredrvr_weakv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808364".
+Reading "sky130_fd_io__com_pdpredrvr_strong_slowv2".
+Reading "sky130_fd_io__gpiov2_obpredrvr".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808368".
+Reading "sky130_fd_pr__tpl1__example_55959141808625".
+Reading "sky130_fd_pr__via_pol1__example_55959141808373".
+Reading "sky130_fd_pr__tpl1__example_55959141808374".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808393".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808392".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808391".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808390".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808389".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808388".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808387".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808386".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808384".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808381".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808377".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808376".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808375".
+Reading "sky130_fd_io__gpio_dat_lsv2".
+Reading "sky130_fd_io__gpio_dat_ls_1v2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808398".
+Reading "sky130_fd_pr__via_pol1__example_55959141808397".
+Reading "sky130_fd_pr__via_pol1__example_55959141808396".
+Reading "sky130_fd_pr__via_pol1__example_55959141808395".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808401".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808399".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808269".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808410".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808409".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808408".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808407".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808406".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808405".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808404".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808403".
+Reading "sky130_fd_io__com_cclat".
+Reading "sky130_fd_io__com_opath_datoev2".
+Reading "sky130_fd_io__gpiov2_octl_dat".
+Reading "sky130_fd_pr__via_pol1_centered__example_559591418080".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180832".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180856".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180855".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180853".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180852".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418083".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418082".
+Reading "sky130_fd_io__nfet_con_diff_wo_abt_270v2".
+Reading "sky130_fd_io__gpiov2_pddrvr_strong".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418085".
+Reading "sky130_fd_io__pfet_con_diff_wo_abt_270v2".
+Reading "sky130_fd_io__gpio_pudrvr_strongv2".
+Reading "sky130_fd_pr__nfet_01v8__example_5595914180850".
+Reading "sky130_fd_io__gpio_pddrvr_weakv2".
+Reading "sky130_fd_io__gpio_pddrvr_strong_slowv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808656".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808655".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808654".
+Reading "sky130_fd_io__com_pudrvr_weakv2".
+Reading "sky130_fd_io__com_pudrvr_strong_slowv2".
+Reading "sky130_fd_io__gpio_odrvr_subv2".
+Reading "sky130_fd_io__gpio_odrvrv2".
+Reading "sky130_fd_io__gpio_opathv2".
+Reading "sky130_fd_io__top_gpiov2".
+Reading "sky130_fd_io__overlay_gpiov2".
+Reading "sky130_ef_io__gpiov2_pad".
+Reading "sky130_ef_io__gpiov2_pad_wrapped".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808691".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808687".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808684".
+Reading "sky130_fd_pr__tpl1__example_55959141808686".
+Reading "sky130_fd_pr__tpl1__example_55959141808685".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808683".
+Reading "sky130_fd_io__gnd2gnd_strap".
+Reading "sky130_fd_io__gnd2gnd_tap".
+Reading "sky130_fd_io__gnd2gnd_diff".
+Reading "sky130_fd_io__gnd2gnd_sub_dnwl".
+Reading "sky130_fd_io__gnd2gnd_120x2_lv_isosub".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808690".
+Reading "sky130_fd_pr__dftpl1s2__example_55959141808702".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808705".
+Reading "sky130_fd_pr__dfl1__example_55959141808682".
+Reading "sky130_fd_pr__dftpl1s2__example_55959141808694".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808693".
+Reading "sky130_fd_pr__dfl1__example_55959141808681".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808688".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808699".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808698".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808697".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808696".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808695".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808704".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808703".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808701".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808689".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808692".
+Reading "sky130_fd_io__top_ground_lvc_wpad".
+Reading "sky130_fd_io__overlay_vssd_lvc".
+Reading "sky130_ef_io__lvc_vccdx_overlay".
+Reading "sky130_ef_io__vssd_lvc_clamped_pad".
+Reading "sky130_fd_io__overlay_vssio_hvc".
+Reading "sky130_ef_io__hvc_vssio_overlay".
+Reading "sky130_ef_io__vssio_hvc_clamped_pad".
+Reading "sky130_fd_io__hvc_clampv2".
+Reading "sky130_fd_io__top_power_hvc_wpadv2".
+Reading "sky130_fd_io__overlay_vdda_hvc".
+Reading "sky130_ef_io__vdda_hvc_clamped_pad".
+Reading "sky130_fd_io__top_power_lvc_wpad".
+Reading "sky130_fd_io__overlay_vccd_lvc".
+Reading "sky130_ef_io__vccd_lvc_clamped_pad".
+Reading "sky130_ef_io__disconnect_vdda_slice_5um".
+Reading "sky130_fd_io__overlay_vddio_hvc".
+Reading "sky130_ef_io__hvc_vddio_overlay".
+Reading "sky130_ef_io__vddio_hvc_clamped_pad".
+Reading "chip_io_gpio_connects".
+Reading "sky130_ef_io__lvc_vccdy_overlay".
+Reading "sky130_ef_io__vssd_lvc_clamped3_pad".
+Reading "sky130_ef_io__vccd_lvc_clamped3_pad".
+Reading "chip_io".
+Reading "gpio_signal_buffering".
+Reading "caravel".
+   Generating output for cell caravel_00088bca
+Ended: 12/04/2022 06:41:34
diff --git a/tapeout/logs/fill_final.log b/tapeout/logs/fill_final.log
new file mode 100644
index 0000000..fb3c539
--- /dev/null
+++ b/tapeout/logs/fill_final.log
@@ -0,0 +1,114 @@
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_final.tcl" from command line.
+CIF output style is now "wafflefill(tiled)"
+Writing final GDS
+   Generating output for cell caravel_00088bca_fill_pattern_0_0
+Reading "caravel_00088bca_fill_pattern_0_0".
+   Generating output for cell caravel_00088bca_fill_pattern_1_0
+Reading "caravel_00088bca_fill_pattern_1_0".
+   Generating output for cell caravel_00088bca_fill_pattern_0_1
+Reading "caravel_00088bca_fill_pattern_0_1".
+   Generating output for cell caravel_00088bca_fill_pattern_1_1
+Reading "caravel_00088bca_fill_pattern_1_1".
+   Generating output for cell caravel_00088bca_fill_pattern_2_0
+Reading "caravel_00088bca_fill_pattern_2_0".
+   Generating output for cell caravel_00088bca_fill_pattern_2_1
+Reading "caravel_00088bca_fill_pattern_2_1".
+   Generating output for cell caravel_00088bca_fill_pattern_3_0
+Reading "caravel_00088bca_fill_pattern_3_0".
+   Generating output for cell caravel_00088bca_fill_pattern_3_1
+Reading "caravel_00088bca_fill_pattern_3_1".
+   Generating output for cell caravel_00088bca_fill_pattern_4_0
+Reading "caravel_00088bca_fill_pattern_4_0".
+   Generating output for cell caravel_00088bca_fill_pattern_4_1
+Reading "caravel_00088bca_fill_pattern_4_1".
+   Generating output for cell caravel_00088bca_fill_pattern_5_0
+Reading "caravel_00088bca_fill_pattern_5_0".
+   Generating output for cell caravel_00088bca_fill_pattern_5_1
+Reading "caravel_00088bca_fill_pattern_5_1".
+   Generating output for cell caravel_00088bca_fill_pattern_0_2
+Reading "caravel_00088bca_fill_pattern_0_2".
+   Generating output for cell caravel_00088bca_fill_pattern_1_2
+Reading "caravel_00088bca_fill_pattern_1_2".
+   Generating output for cell caravel_00088bca_fill_pattern_2_2
+Reading "caravel_00088bca_fill_pattern_2_2".
+   Generating output for cell caravel_00088bca_fill_pattern_3_2
+Reading "caravel_00088bca_fill_pattern_3_2".
+   Generating output for cell caravel_00088bca_fill_pattern_4_2
+Reading "caravel_00088bca_fill_pattern_4_2".
+   Generating output for cell caravel_00088bca_fill_pattern_5_2
+Reading "caravel_00088bca_fill_pattern_5_2".
+   Generating output for cell caravel_00088bca_fill_pattern_0_3
+Reading "caravel_00088bca_fill_pattern_0_3".
+   Generating output for cell caravel_00088bca_fill_pattern_1_3
+Reading "caravel_00088bca_fill_pattern_1_3".
+   Generating output for cell caravel_00088bca_fill_pattern_2_3
+Reading "caravel_00088bca_fill_pattern_2_3".
+   Generating output for cell caravel_00088bca_fill_pattern_3_3
+Reading "caravel_00088bca_fill_pattern_3_3".
+   Generating output for cell caravel_00088bca_fill_pattern_4_3
+Reading "caravel_00088bca_fill_pattern_4_3".
+   Generating output for cell caravel_00088bca_fill_pattern_5_3
+Reading "caravel_00088bca_fill_pattern_5_3".
+   Generating output for cell caravel_00088bca_fill_pattern_0_4
+Reading "caravel_00088bca_fill_pattern_0_4".
+   Generating output for cell caravel_00088bca_fill_pattern_1_4
+Reading "caravel_00088bca_fill_pattern_1_4".
+   Generating output for cell caravel_00088bca_fill_pattern_2_4
+Reading "caravel_00088bca_fill_pattern_2_4".
+   Generating output for cell caravel_00088bca_fill_pattern_3_4
+Reading "caravel_00088bca_fill_pattern_3_4".
+   Generating output for cell caravel_00088bca_fill_pattern_4_4
+Reading "caravel_00088bca_fill_pattern_4_4".
+   Generating output for cell caravel_00088bca_fill_pattern_5_4
+Reading "caravel_00088bca_fill_pattern_5_4".
+   Generating output for cell caravel_00088bca_fill_pattern_0_5
+Reading "caravel_00088bca_fill_pattern_0_5".
+   Generating output for cell caravel_00088bca_fill_pattern_1_5
+Reading "caravel_00088bca_fill_pattern_1_5".
+   Generating output for cell caravel_00088bca_fill_pattern_2_5
+Reading "caravel_00088bca_fill_pattern_2_5".
+   Generating output for cell caravel_00088bca_fill_pattern_3_5
+Reading "caravel_00088bca_fill_pattern_3_5".
+   Generating output for cell caravel_00088bca_fill_pattern_4_5
+Reading "caravel_00088bca_fill_pattern_4_5".
+   Generating output for cell caravel_00088bca_fill_pattern_5_5
+Reading "caravel_00088bca_fill_pattern_5_5".
+   Generating output for cell caravel_00088bca_fill_pattern_0_6
+Reading "caravel_00088bca_fill_pattern_0_6".
+   Generating output for cell caravel_00088bca_fill_pattern_1_6
+Reading "caravel_00088bca_fill_pattern_1_6".
+   Generating output for cell caravel_00088bca_fill_pattern_2_6
+Reading "caravel_00088bca_fill_pattern_2_6".
+   Generating output for cell caravel_00088bca_fill_pattern_3_6
+Reading "caravel_00088bca_fill_pattern_3_6".
+   Generating output for cell caravel_00088bca_fill_pattern_4_6
+Reading "caravel_00088bca_fill_pattern_4_6".
+   Generating output for cell caravel_00088bca_fill_pattern_5_6
+Reading "caravel_00088bca_fill_pattern_5_6".
+   Generating output for cell caravel_00088bca_fill_pattern_0_7
+Reading "caravel_00088bca_fill_pattern_0_7".
+   Generating output for cell caravel_00088bca_fill_pattern_1_7
+Reading "caravel_00088bca_fill_pattern_1_7".
+   Generating output for cell caravel_00088bca_fill_pattern_2_7
+Reading "caravel_00088bca_fill_pattern_2_7".
+   Generating output for cell caravel_00088bca_fill_pattern_3_7
+Reading "caravel_00088bca_fill_pattern_3_7".
+   Generating output for cell caravel_00088bca_fill_pattern_4_7
+Reading "caravel_00088bca_fill_pattern_4_7".
+   Generating output for cell caravel_00088bca_fill_pattern_5_7
+Reading "caravel_00088bca_fill_pattern_5_7".
+   Generating output for cell caravel_00088bca_fill_pattern
+Ended: 12/04/2022 06:40:19
diff --git a/tapeout/logs/fill_initial.log b/tapeout/logs/fill_initial.log
new file mode 100644
index 0000000..dc77d59
--- /dev/null
+++ b/tapeout/logs/fill_initial.log
@@ -0,0 +1,1895 @@
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill.tcl" from command line.
+Started: 12/04/2022 05:41:18
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: caravel
+Reading "caravel_logo".
+Reading "font_22".
+Reading "font_73".
+Reading "font_43".
+Reading "font_49".
+Reading "font_65".
+Reading "font_68".
+Reading "font_54".
+Reading "font_67".
+Reading "font_6E".
+Reading "font_69".
+Reading "font_6C".
+Reading "font_61".
+Reading "font_53".
+Reading "caravel_motto".
+Reading "font_79".
+Reading "font_76".
+Reading "font_74".
+Reading "font_72".
+Reading "font_70".
+Reading "font_66".
+Reading "font_63".
+Reading "font_62".
+Reading "font_57".
+Reading "font_56".
+Reading "font_50".
+Reading "font_47".
+Reading "font_44".
+Reading "font_35".
+Reading "font_32".
+Reading "font_30".
+Reading "font_29".
+Reading "font_28".
+Reading "font_20".
+Reading "font_6F".
+Reading "font_6B".
+Reading "font_4F".
+Reading "font_4B".
+Reading "font_2D".
+Reading "copyright_block".
+Reading "open_source".
+Reading "sky130_fd_sc_hvl__decap_8".
+CIF file read warning: CIF style sky130(vendor): units rescaled by factor of 5 / 1
+Reading "sky130_fd_sc_hvl__decap_4".
+Reading "sky130_fd_sc_hvl__diode_2".
+Reading "sky130_fd_sc_hvl__fill_1".
+Reading "sky130_fd_sc_hvl__fill_2".
+Reading "sky130_fd_sc_hvl__lsbufhv2lv_1".
+Reading "xres_buf".
+Reading "alpha_8".
+Reading "alpha_B".
+Reading "alpha_C".
+Reading "alpha_A".
+Reading "alpha_0".
+Reading "user_id_textblock".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "gpio_defaults_block_1803".
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__nand3b_1".
+Reading "sky130_fd_sc_hd__nand4bb_1".
+Reading "sky130_fd_sc_hd__o2111ai_2".
+Reading "sky130_fd_sc_hd__o31ai_2".
+Reading "sky130_fd_sc_hd__o2bb2ai_1".
+Reading "sky130_fd_sc_hd__a41oi_1".
+Reading "sky130_fd_sc_hd__o211ai_4".
+Reading "sky130_fd_sc_hd__nor3b_2".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__o2111ai_1".
+Reading "sky130_fd_sc_hd__nand3_1".
+Reading "sky130_fd_sc_hd__a31o_1".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "sky130_fd_sc_hd__nand2b_1".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__a2bb2o_1".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__nor3_2".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__nor4_1".
+Reading "sky130_fd_sc_hd__o31ai_1".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__dfstp_1".
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__dfrtn_1".
+Reading "sky130_fd_sc_hd__dfstp_2".
+Reading "sky130_fd_sc_hd__dfrtp_1".
+Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__o21a_2".
+Reading "sky130_fd_sc_hd__nand2b_2".
+Reading "sky130_fd_sc_hd__o21ai_2".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__dfrtp_2".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__clkinv_2".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_ef_sc_hd__decap_12".
+Reading "caravel_clocking".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "buff_flash_clkrst".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__macro_sparecell".
+Reading "sky130_fd_sc_hd__dfbbn_2".
+Reading "sky130_fd_sc_hd__or2_0".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__and2_0".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "sky130_fd_sc_hd__and2b_2".
+Reading "sky130_fd_sc_hd__and3b_2".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__buf_16".
+Reading "gpio_logic_high".
+Reading "gpio_control_block".
+Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__a21bo_1".
+Reading "sky130_fd_sc_hd__o2bb2a_1".
+Reading "sky130_fd_sc_hd__a221o_2".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__o21ba_1".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__and4bb_1".
+Reading "sky130_fd_sc_hd__and4bb_2".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__a311o_1".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__o221a_1".
+Reading "sky130_fd_sc_hd__a2111o_1".
+Reading "sky130_fd_sc_hd__nor4_2".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__nor4_4".
+Reading "sky130_fd_sc_hd__a2111o_2".
+Reading "sky130_fd_sc_hd__nand2b_4".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__a21boi_1".
+Reading "sky130_fd_sc_hd__nand4_1".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__o211a_1".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__nand4b_1".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__a41o_1".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__a311oi_2".
+Reading "sky130_fd_sc_hd__o41a_1".
+Reading "sky130_fd_sc_hd__nor3b_1".
+Reading "sky130_fd_sc_hd__a2111oi_1".
+CIF file read warning: Input off lambda grid by 2/5; snapped to grid.
+Reading "sky130_fd_sc_hd__nand4b_4".
+Reading "sky130_fd_sc_hd__a31oi_4".
+Reading "sky130_fd_sc_hd__and4b_4".
+Reading "sky130_fd_sc_hd__nand3b_4".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__xor2_1".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__o221a_4".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "sky130_fd_sc_hd__o31a_4".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__a221oi_1".
+Reading "sky130_fd_sc_hd__a221o_4".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__inv_6".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__nand4_2".
+Reading "sky130_fd_sc_hd__and4b_2".
+Reading "sky130_fd_sc_hd__xnor2_2".
+Reading "sky130_fd_sc_hd__a21oi_2".
+Reading "sky130_fd_sc_hd__a211o_2".
+Reading "sky130_fd_sc_hd__and3_2".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__o31a_2".
+Reading "sky130_fd_sc_hd__nand3_2".
+Reading "sky130_fd_sc_hd__a21o_2".
+Reading "sky130_fd_sc_hd__a22o_2".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__and2b_4".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__and3b_4".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "housekeeping".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+Reading "sky130_fd_sc_hd__einvp_1".
+Reading "sky130_fd_sc_hd__clkinv_1".
+Reading "sky130_fd_sc_hd__einvn_4".
+Reading "sky130_fd_sc_hd__einvn_8".
+Reading "sky130_fd_sc_hd__einvp_2".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__a32o_2".
+Reading "sky130_fd_sc_hd__o2111a_2".
+Reading "sky130_fd_sc_hd__o22a_2".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__nand3b_2".
+Reading "sky130_fd_sc_hd__a21boi_2".
+Reading "sky130_fd_sc_hd__xor2_2".
+Reading "sky130_fd_sc_hd__o2bb2a_2".
+Reading "sky130_fd_sc_hd__nand4b_2".
+Reading "sky130_fd_sc_hd__o21ba_2".
+Reading "sky130_fd_sc_hd__o32a_2".
+Reading "sky130_fd_sc_hd__clkinv_8".
+Reading "digital_pll".
+Reading "user_id_programming".
+Reading "NJ_sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ".
+Reading "NJ_sky130_fd_pr__pfet_g5v0d10v5_3YBPVB".
+Reading "NJ_sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC".
+Reading "NJ_sky130_fd_pr__nfet_g5v0d10v5_TGFUGS".
+Reading "NJ_sky130_fd_pr__pfet_g5v0d10v5_YUHPBG".
+Reading "NJ_sky130_fd_pr__pfet_g5v0d10v5_YEUEBV".
+Reading "NJ_sky130_fd_pr__nfet_g5v0d10v5_PKVMTM".
+Reading "NJ_sky130_fd_pr__pfet_g5v0d10v5_YUHPXE".
+Reading "NJ_sky130_fd_sc_hvl__schmittbuf_1".
+Reading "NJ_sky130_fd_sc_hvl__buf_8".
+Reading "NJ_sky130_fd_sc_hvl__inv_8".
+Reading "NJ_sky130_fd_sc_hvl__fill_4".
+Reading "NJ_sky130_fd_pr__cap_mim_m3_1_WRT4AW".
+Reading "NJ_sky130_fd_pr__cap_mim_m3_2_W5U4AW".
+Reading "NJ_sky130_fd_pr__res_xhigh_po_0p69_S5N9F3".
+Reading "simple_por".
+Reading "EY_sky130_fd_sc_hd__decap_3".
+Reading "EY_sky130_ef_sc_hd__decap_12".
+Reading "EY_sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "EY_sky130_fd_sc_hd__fill_1".
+Reading "EY_sky130_fd_sc_hd__decap_4".
+Reading "EY_sky130_fd_sc_hd__decap_6".
+Reading "EY_sky130_fd_sc_hd__fill_2".
+Reading "EY_sky130_fd_sc_hd__decap_8".
+Reading "EY_sky130_fd_sc_hd__diode_2".
+Reading "EY_sky130_fd_sc_hd__clkbuf_16".
+Reading "EY_sky130_fd_sc_hd__o211a_1".
+Reading "EY_sky130_fd_sc_hd__dfxtp_2".
+Reading "EY_sky130_fd_sc_hd__o21a_1".
+Reading "EY_sky130_fd_sc_hd__mux2_1".
+Reading "EY_sky130_fd_sc_hd__or2_1".
+Reading "EY_sky130_fd_sc_hd__dfxtp_1".
+Reading "EY_sky130_fd_sc_hd__a22o_1".
+Reading "EY_sky130_fd_sc_hd__a21o_2".
+Reading "EY_sky130_fd_sc_hd__a21o_1".
+Reading "EY_sky130_fd_sc_hd__a22o_4".
+Reading "EY_sky130_fd_sc_hd__buf_8".
+Reading "EY_sky130_fd_sc_hd__o21a_2".
+Reading "EY_sky130_fd_sc_hd__mux2_2".
+Reading "EY_sky130_fd_sc_hd__buf_4".
+Reading "EY_sky130_fd_sc_hd__clkbuf_8".
+Reading "EY_sky130_fd_sc_hd__buf_6".
+Reading "EY_sky130_fd_sc_hd__dfxtp_4".
+Reading "EY_sky130_fd_sc_hd__buf_2".
+Reading "EY_sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "EY_sky130_fd_sc_hd__o21ai_1".
+Reading "EY_sky130_fd_sc_hd__mux4_1".
+Reading "EY_sky130_fd_sc_hd__buf_12".
+Reading "EY_sky130_fd_sc_hd__mux4_2".
+Reading "EY_sky130_fd_sc_hd__inv_2".
+Reading "EY_sky130_fd_sc_hd__and3_2".
+Reading "EY_sky130_fd_sc_hd__nand2_1".
+Reading "EY_sky130_fd_sc_hd__a2bb2o_1".
+Reading "EY_sky130_fd_sc_hd__or3b_1".
+Reading "EY_sky130_fd_sc_hd__o32a_1".
+Reading "EY_sky130_fd_sc_hd__a2bb2o_2".
+Reading "EY_sky130_fd_sc_hd__o311a_1".
+Reading "EY_sky130_fd_sc_hd__o221a_1".
+Reading "EY_sky130_fd_sc_hd__o31a_1".
+Reading "EY_sky130_fd_sc_hd__o211a_2".
+Reading "EY_sky130_fd_sc_hd__and3_1".
+Reading "EY_sky130_fd_sc_hd__a211oi_1".
+Reading "EY_sky130_fd_sc_hd__and4_4".
+Reading "EY_sky130_fd_sc_hd__and4_1".
+Reading "EY_sky130_fd_sc_hd__clkbuf_4".
+Reading "EY_sky130_fd_sc_hd__and3b_1".
+Reading "EY_sky130_fd_sc_hd__a211o_4".
+Reading "EY_sky130_fd_sc_hd__a211o_1".
+Reading "EY_sky130_fd_sc_hd__o21ba_1".
+Reading "EY_sky130_fd_sc_hd__a21oi_1".
+Reading "EY_sky130_fd_sc_hd__nor2_1".
+Reading "EY_sky130_fd_sc_hd__nand2_8".
+Reading "EY_sky130_fd_sc_hd__a311o_1".
+Reading "EY_sky130_fd_sc_hd__nor2_2".
+Reading "EY_sky130_fd_sc_hd__a41o_1".
+Reading "EY_sky130_fd_sc_hd__nor3_2".
+Reading "EY_sky130_fd_sc_hd__or4bb_4".
+Reading "EY_sky130_fd_sc_hd__nor3_1".
+Reading "EY_sky130_fd_sc_hd__or4b_4".
+Reading "EY_sky130_fd_sc_hd__or3b_4".
+Reading "EY_sky130_fd_sc_hd__a31o_1".
+Reading "EY_sky130_fd_sc_hd__a211o_2".
+Reading "EY_sky130_fd_sc_hd__or2_2".
+Reading "EY_sky130_fd_sc_hd__a31o_2".
+Reading "EY_sky130_fd_sc_hd__a221o_1".
+Reading "EY_sky130_fd_sc_hd__and4b_4".
+Reading "EY_sky130_fd_sc_hd__and3_4".
+Reading "EY_sky130_fd_sc_hd__mux2_8".
+Reading "EY_sky130_fd_sc_hd__o21ai_2".
+Reading "EY_sky130_fd_sc_hd__and4b_1".
+Reading "EY_sky130_fd_sc_hd__or4b_1".
+Reading "EY_sky130_fd_sc_hd__o211a_4".
+Reading "EY_sky130_fd_sc_hd__a32o_1".
+Reading "EY_sky130_fd_sc_hd__a21boi_1".
+Reading "EY_sky130_fd_sc_hd__o41ai_4".
+Reading "EY_sky130_fd_sc_hd__o31a_2".
+Reading "EY_sky130_fd_sc_hd__nand2_4".
+Reading "EY_sky130_fd_sc_hd__a31oi_4".
+Reading "EY_sky130_fd_sc_hd__and4_2".
+Reading "EY_sky130_fd_sc_hd__nand3_4".
+Reading "EY_sky130_fd_sc_hd__and4b_2".
+Reading "EY_sky130_fd_sc_hd__o41a_4".
+Reading "EY_sky130_fd_sc_hd__and4bb_2".
+Reading "EY_sky130_fd_sc_hd__clkinv_2".
+Reading "EY_sky130_fd_sc_hd__and2b_2".
+Reading "EY_sky130_fd_sc_hd__or4bb_1".
+Reading "EY_sky130_fd_sc_hd__a21oi_2".
+Reading "EY_sky130_fd_sc_hd__a221oi_1".
+Reading "EY_sky130_fd_sc_hd__a31oi_1".
+Reading "EY_sky130_fd_sc_hd__xor2_4".
+Reading "EY_sky130_fd_sc_hd__clkbuf_1".
+Reading "EY_sky130_fd_sc_hd__nand3b_4".
+Reading "EY_sky130_fd_sc_hd__nand2_2".
+Reading "EY_sky130_fd_sc_hd__xnor2_1".
+Reading "EY_sky130_fd_sc_hd__and2_1".
+Reading "EY_sky130_fd_sc_hd__nor2_4".
+Reading "EY_sky130_fd_sc_hd__nand4_4".
+Reading "EY_sky130_fd_sc_hd__a32o_2".
+Reading "EY_sky130_fd_sc_hd__nor4_1".
+Reading "EY_sky130_fd_sc_hd__nand4_1".
+Reading "EY_sky130_fd_sc_hd__xor2_1".
+Reading "EY_sky130_fd_sc_hd__and4bb_4".
+Reading "EY_sky130_fd_sc_hd__a41o_2".
+Reading "EY_sky130_fd_sc_hd__o2bb2a_1".
+Reading "EY_sky130_fd_sc_hd__xnor2_2".
+Reading "EY_sky130_fd_sc_hd__xor2_2".
+Reading "EY_sky130_fd_sc_hd__or2_4".
+Reading "EY_sky130_fd_sc_hd__a2111oi_2".
+Reading "EY_sky130_fd_sc_hd__nor4_4".
+Reading "EY_sky130_fd_sc_hd__mux2_4".
+Reading "EY_sky130_fd_sc_hd__and2b_1".
+Reading "EY_sky130_fd_sc_hd__and2_2".
+Reading "EY_sky130_fd_sc_hd__nor4b_1".
+Reading "EY_sky130_fd_sc_hd__o2111ai_4".
+Reading "EY_sky130_fd_sc_hd__nor4_2".
+Reading "EY_sky130_fd_sc_hd__nand3b_2".
+Reading "EY_sky130_fd_sc_hd__nand3_1".
+Reading "EY_sky130_fd_sc_hd__nand2b_2".
+Reading "EY_sky130_fd_sc_hd__o31ai_1".
+Reading "EY_sky130_fd_sc_hd__o41a_1".
+Reading "EY_sky130_fd_sc_hd__a21bo_1".
+Reading "EY_sky130_fd_sc_hd__o41ai_1".
+Reading "EY_sky130_fd_sc_hd__nand3b_1".
+Reading "EY_sky130_fd_sc_hd__o2111a_1".
+Reading "EY_sky130_fd_sc_hd__o21a_4".
+Reading "EY_sky130_fd_sc_hd__o22a_1".
+Reading "EY_sky130_fd_sc_hd__or3b_2".
+Reading "EY_sky130_fd_sc_hd__nand2b_1".
+Reading "EY_sky130_fd_sc_hd__nor4b_4".
+Reading "EY_sky130_fd_sc_hd__o21bai_1".
+Reading "EY_sky130_fd_sc_hd__nor3_4".
+Reading "EY_sky130_fd_sc_hd__o41a_2".
+Reading "EY_sky130_fd_sc_hd__or4b_2".
+Reading "EY_sky130_fd_sc_hd__a221o_4".
+Reading "EY_sky130_fd_sc_hd__a2111oi_1".
+Reading "EY_sky130_fd_sc_hd__o31a_4".
+Reading "EY_sky130_fd_sc_hd__nor2_8".
+Reading "EY_sky130_fd_sc_hd__clkinv_4".
+Reading "EY_sky130_fd_sc_hd__a221o_2".
+Reading "EY_sky130_fd_sc_hd__o21ai_4".
+Reading "EY_sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "EY_sky130_fd_sc_hd__clkbuf_2".
+Reading "EY_sky130_fd_sc_hd__a31o_4".
+Reading "EY_sky130_fd_sc_hd__ebufn_4".
+Reading "EY_sky130_fd_sc_hd__dlxtp_1".
+Reading "EY_sky130_fd_sc_hd__dlclkp_1".
+Reading "EY_sky130_fd_sc_hd__conb_1".
+Reading "EY_sky130_fd_sc_hd__inv_1".
+Reading "EY_sky130_fd_sc_hd__nor4b_2".
+Reading "EY_sky130_fd_sc_hd__and3b_2".
+Reading "EY_sky130_fd_sc_hd__nor3b_2".
+Reading "EY_RAM256".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+Reading "EY_sky130_fd_sc_hd__a21o_4".
+Reading "EY_sky130_fd_sc_hd__o2111a_4".
+Reading "EY_sky130_fd_sc_hd__a22o_2".
+Reading "EY_sky130_fd_sc_hd__o211ai_4".
+Reading "EY_sky130_fd_sc_hd__o22ai_4".
+Reading "EY_sky130_fd_sc_hd__a221oi_4".
+Reading "EY_sky130_fd_sc_hd__and2b_4".
+Reading "EY_sky130_fd_sc_hd__and3b_4".
+Reading "EY_sky130_fd_sc_hd__and4bb_1".
+Reading "EY_sky130_fd_sc_hd__a21oi_4".
+Reading "EY_sky130_fd_sc_hd__o22ai_1".
+Reading "EY_sky130_fd_sc_hd__inv_4".
+Reading "EY_sky130_fd_sc_hd__a311o_2".
+Reading "EY_sky130_fd_sc_hd__a2111o_1".
+Reading "EY_sky130_fd_sc_hd__o311a_4".
+Reading "EY_sky130_fd_sc_hd__o2111ai_1".
+Reading "EY_sky130_fd_sc_hd__clkinv_8".
+Reading "EY_sky130_fd_sc_hd__nand3_2".
+Reading "EY_sky130_fd_sc_hd__a22oi_1".
+Reading "EY_sky130_fd_sc_hd__nand4b_4".
+Reading "EY_sky130_fd_sc_hd__o221ai_4".
+Reading "EY_sky130_fd_sc_hd__nand4_2".
+Reading "EY_sky130_fd_sc_hd__inv_6".
+Reading "EY_sky130_fd_sc_hd__o2bb2ai_1".
+Reading "EY_sky130_fd_sc_hd__a311oi_4".
+Reading "EY_sky130_fd_sc_hd__o32ai_4".
+Reading "EY_sky130_fd_sc_hd__o211ai_1".
+Reading "EY_sky130_fd_sc_hd__nand4b_1".
+Reading "EY_sky130_fd_sc_hd__o211ai_2".
+Reading "EY_sky130_fd_sc_hd__a22oi_4".
+Reading "EY_sky130_fd_sc_hd__and2_4".
+Reading "EY_sky130_fd_sc_hd__a211oi_4".
+Reading "EY_sky130_fd_sc_hd__nor3b_4".
+Reading "EY_sky130_fd_sc_hd__o22a_2".
+Reading "EY_sky130_fd_sc_hd__a2111oi_4".
+Reading "EY_sky130_fd_sc_hd__nand2b_4".
+Reading "EY_sky130_fd_sc_hd__a2bb2o_4".
+Reading "EY_sky130_fd_sc_hd__o2bb2a_2".
+Reading "EY_sky130_fd_sc_hd__o2111ai_2".
+Reading "EY_sky130_fd_sc_hd__a22oi_2".
+Reading "EY_sky130_fd_sc_hd__nor3b_1".
+Reading "EY_sky130_fd_sc_hd__o2bb2a_4".
+Reading "EY_sky130_fd_sc_hd__o21bai_4".
+Reading "EY_sky130_fd_sc_hd__o311ai_1".
+Reading "EY_sky130_fd_sc_hd__a32oi_2".
+Reading "EY_sky130_fd_sc_hd__o2bb2ai_2".
+Reading "EY_sky130_fd_sc_hd__o311ai_4".
+Reading "EY_sky130_fd_sc_hd__o2bb2ai_4".
+Reading "EY_sky130_fd_sc_hd__o31ai_4".
+Reading "EY_sky130_fd_sc_hd__o221a_2".
+Reading "EY_sky130_fd_sc_hd__o2111a_2".
+Reading "EY_sky130_fd_sc_hd__a31oi_2".
+Reading "EY_sky130_fd_sc_hd__o311a_2".
+Reading "EY_sky130_fd_sc_hd__o22a_4".
+Reading "EY_sky130_fd_sc_hd__a32oi_4".
+Reading "EY_sky130_fd_sc_hd__a211oi_2".
+Reading "EY_sky130_fd_sc_hd__o31ai_2".
+Reading "EY_sky130_fd_sc_hd__o221ai_1".
+Reading "EY_sky130_fd_sc_hd__clkinv_16".
+Reading "EY_sky130_fd_sc_hd__or4bb_2".
+Reading "EY_sky130_fd_sc_hd__a221oi_2".
+Reading "EY_sky130_fd_sc_hd__inv_8".
+Reading "EY_sky130_fd_sc_hd__a311oi_2".
+Reading "EY_sky130_fd_sc_hd__a311oi_1".
+Reading "EY_sky130_fd_sc_hd__o311ai_2".
+Reading "EY_sky130_fd_sc_hd__a32oi_1".
+Reading "EY_sky130_fd_sc_hd__a2bb2oi_2".
+Reading "EY_sky130_fd_sc_hd__a2bb2oi_1".
+Reading "EY_sky130_fd_sc_hd__a2bb2oi_4".
+Reading "EY_sky130_fd_sc_hd__xnor2_4".
+Reading "EY_sky130_fd_sc_hd__inv_12".
+Reading "EY_sky130_fd_sc_hd__a2111o_4".
+Reading "EY_sky130_fd_sc_hd__a32o_4".
+Reading "EY_sky130_fd_sc_hd__o21ba_2".
+Reading "EY_sky130_fd_sc_hd__a41oi_2".
+Reading "EY_sky130_fd_sc_hd__o22ai_2".
+Reading "EY_sky130_fd_sc_hd__o21bai_2".
+Reading "EY_sky130_fd_sc_hd__a41oi_4".
+Reading "EY_sky130_fd_sc_hd__a41o_4".
+Reading "EY_sky130_fd_sc_hd__a311o_4".
+Reading "EY_sky130_fd_sc_hd__o32ai_1".
+Reading "EY_sky130_fd_sc_hd__a21boi_4".
+Reading "EY_sky130_fd_sc_hd__o32ai_2".
+Reading "EY_sky130_fd_sc_hd__a21bo_2".
+Reading "EY_RAM128".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+Reading "mgmt_core_wrapper".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+    75000 uses
+    80000 uses
+    85000 uses
+    90000 uses
+    95000 uses
+    100000 uses
+    105000 uses
+    110000 uses
+    115000 uses
+    120000 uses
+    125000 uses
+    130000 uses
+    135000 uses
+    140000 uses
+    145000 uses
+    150000 uses
+    155000 uses
+    160000 uses
+    165000 uses
+    170000 uses
+    175000 uses
+    180000 uses
+    185000 uses
+    190000 uses
+    195000 uses
+    200000 uses
+    205000 uses
+    210000 uses
+    215000 uses
+    220000 uses
+Reading "gpio_defaults_block_0403".
+Reading "gpio_defaults_block_1800".
+Reading "sky130_fd_sc_hd__inv_8".
+Reading "sky130_fd_sc_hd__dfbbp_1".
+Reading "spare_logic_block".
+Reading "sky130_fd_sc_hd__bufbuf_8".
+Reading "sky130_fd_sc_hvl__conb_1".
+Reading "mgmt_protect_hv".
+Reading "mprj_logic_high".
+Reading "mprj2_logic_high".
+Reading "sky130_fd_sc_hd__inv_12".
+Reading "mgmt_protect".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+Reading "gpio_defaults_block_0801".
+Reading "gpio_control_power_routing_top".
+Reading "gpio_control_power_routing_right".
+Reading "gpio_control_power_routing".
+Reading "caravel_power_routing".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_39".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_19".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_14".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_13".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_7".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_38".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_33".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_32".
+Reading "M3_sky130_fd_bd_sram__openram_dff".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_row_addr_dff".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_wmask_dff".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_cr_3".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_col_addr_dff".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_data_dff".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_16".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_29".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_28".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_11".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_360_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_12".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_1".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dli".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sli_dactive".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_1".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w1_680_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w1_680_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_3".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w0_740_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w1_260_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_2".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_0".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m7_w1_680_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m7_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_4".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_1".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_0".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pand2_1".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m24_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m24_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_14".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m8_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m8_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_13".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_12".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_11".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_0".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_3".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_17".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_delay_chain".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m18_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m18_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_16".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_5".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dactive".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pnand3".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pand3_0".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m22_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m22_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_15".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_4".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pand3".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m42_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m42_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_10".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m15_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m15_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_9".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m5_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_8".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w1_260_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_7".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_2".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_rw".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_cr_5".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array_0".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m41_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m41_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_20".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m14_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m14_w2_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_19".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w1_680_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_18".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_6".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_r".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_cr_4".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_20".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_17".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_0".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pand2_0".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4_0".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_15".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w7_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w7_000_sli_dli_da_p".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec_0".
+Reading "M3_sky130_fd_bd_sram__openram_dp_nand2_dec".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec_0".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver_array".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec".
+Reading "M3_sky130_fd_bd_sram__openram_dp_nand3_dec".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_and3_dec".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode3x8".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_decoder".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_port_address_0".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_port_address".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_27".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_26".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_25".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_24".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w2_880_sli_dli".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_0".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array_0".
+Reading "M3_sky130_fd_bd_sram__openram_sense_amp".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_sense_amp_array".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_23".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_21".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_22".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w0_550_sli_dli".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_1".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array_0".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_port_data_0".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pinv".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pnand2".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_pand2".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_write_mask_and_array".
+Reading "M3_sky130_fd_bd_sram__openram_write_driver".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_write_driver_array".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_0".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_port_data".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_9".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_contact_8".
+Reading "M3_sky130_fd_bd_sram__openram_dp_cell_cap_row".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array_0".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array".
+Reading "M3_sky130_fd_bd_sram__openram_dp_cell_cap_col".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array_0".
+Reading "M3_sky130_fd_bd_sram__openram_dp_cell_dummy".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_dummy_array".
+Reading "M3_sky130_fd_bd_sram__openram_dp_cell_replica".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_replica_column_0".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_replica_column".
+Reading "M3_sky130_fd_bd_sram__openram_dp_cell".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_bitcell_array".
+    5000 uses
+    10000 uses
+    15000 uses
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_replica_bitcell_array".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8_bank".
+Reading "M3_sky130_sram_2kbyte_1rw1r_32x512_8".
+    5000 uses
+Reading "M3_sky130_fd_sc_hd__o32a_2".
+Reading "M3_sky130_fd_sc_hd__o21ai_2".
+Reading "M3_sky130_ef_sc_hd__decap_12".
+Reading "M3_sky130_fd_sc_hd__o221a_2".
+Reading "M3_sky130_fd_sc_hd__o2bb2a_2".
+Reading "M3_sky130_fd_sc_hd__a221o_2".
+Reading "M3_sky130_fd_sc_hd__buf_2".
+Reading "M3_sky130_fd_sc_hd__and4b_2".
+Reading "M3_sky130_fd_sc_hd__nand2_2".
+Reading "M3_sky130_fd_sc_hd__a31oi_2".
+Reading "M3_sky130_fd_sc_hd__or4_2".
+Reading "M3_sky130_fd_sc_hd__or3b_2".
+Reading "M3_sky130_fd_sc_hd__or3_2".
+Reading "M3_sky130_fd_sc_hd__and2b_2".
+Reading "M3_sky130_fd_sc_hd__a31o_2".
+Reading "M3_sky130_fd_sc_hd__xor2_2".
+Reading "M3_sky130_fd_sc_hd__nor2_2".
+Reading "M3_sky130_fd_sc_hd__a22o_2".
+Reading "M3_sky130_fd_sc_hd__o21a_2".
+Reading "M3_sky130_fd_sc_hd__a21oi_2".
+Reading "M3_sky130_fd_sc_hd__nand2b_2".
+Reading "M3_sky130_fd_sc_hd__o211a_2".
+Reading "M3_sky130_fd_sc_hd__a21o_2".
+Reading "M3_sky130_fd_sc_hd__o22a_2".
+Reading "M3_sky130_fd_sc_hd__nand3b_2".
+Reading "M3_sky130_fd_sc_hd__and4_2".
+Reading "M3_sky130_fd_sc_hd__a311o_2".
+Reading "M3_sky130_fd_sc_hd__clkbuf_2".
+Reading "M3_sky130_fd_sc_hd__a211o_2".
+Reading "M3_sky130_fd_sc_hd__decap_6".
+Reading "M3_sky130_fd_sc_hd__clkinv_2".
+Reading "M3_sky130_fd_sc_hd__and3_2".
+Reading "M3_sky130_fd_sc_hd__a32o_2".
+Reading "M3_sky130_fd_sc_hd__mux2_1".
+Reading "M3_sky130_fd_sc_hd__xnor2_2".
+Reading "M3_sky130_fd_sc_hd__and2_2".
+Reading "M3_sky130_fd_sc_hd__dfrtp_2".
+Reading "M3_sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "M3_sky130_fd_sc_hd__inv_2".
+Reading "M3_sky130_fd_sc_hd__conb_1".
+Reading "M3_sky130_fd_sc_hd__or2_2".
+Reading "M3_sky130_fd_sc_hd__decap_8".
+Reading "M3_sky130_fd_sc_hd__fill_1".
+Reading "M3_sky130_fd_sc_hd__fill_2".
+Reading "M3_sky130_fd_sc_hd__decap_4".
+Reading "M3_sky130_fd_sc_hd__decap_3".
+Reading "M3_sky130_fd_sc_hd__clkbuf_1".
+Reading "M3_sky130_fd_sc_hd__a2bb2o_2".
+Reading "M3_sky130_fd_sc_hd__a22oi_1".
+Reading "M3_sky130_fd_sc_hd__and4bb_4".
+Reading "M3_sky130_fd_sc_hd__o211ai_4".
+Reading "M3_sky130_fd_sc_hd__nand4_1".
+Reading "M3_sky130_fd_sc_hd__a21bo_2".
+Reading "M3_sky130_fd_sc_hd__nor4b_4".
+Reading "M3_sky130_fd_sc_hd__o2111a_1".
+Reading "M3_sky130_fd_sc_hd__o41a_1".
+Reading "M3_sky130_fd_sc_hd__a21o_4".
+Reading "M3_sky130_fd_sc_hd__o22ai_1".
+Reading "M3_sky130_fd_sc_hd__a31oi_1".
+Reading "M3_sky130_fd_sc_hd__a41o_1".
+Reading "M3_sky130_fd_sc_hd__o32a_4".
+Reading "M3_sky130_fd_sc_hd__a22oi_2".
+Reading "M3_sky130_fd_sc_hd__nor4_1".
+Reading "M3_sky130_fd_sc_hd__and4b_1".
+Reading "M3_sky130_fd_sc_hd__nand3_4".
+Reading "M3_sky130_fd_sc_hd__a311o_1".
+Reading "M3_sky130_fd_sc_hd__o211ai_2".
+Reading "M3_sky130_fd_sc_hd__o31ai_4".
+Reading "M3_sky130_fd_sc_hd__and3_4".
+Reading "M3_sky130_fd_sc_hd__dfstp_4".
+Reading "M3_sky130_fd_sc_hd__a31o_4".
+Reading "M3_sky130_fd_sc_hd__xor2_1".
+Reading "M3_sky130_fd_sc_hd__a21boi_1".
+Reading "M3_sky130_fd_sc_hd__dfstp_2".
+Reading "M3_sky130_fd_sc_hd__nand2_8".
+Reading "M3_sky130_fd_sc_hd__and3b_1".
+Reading "M3_sky130_fd_sc_hd__buf_12".
+Reading "M3_sky130_fd_sc_hd__o22ai_4".
+Reading "M3_sky130_fd_sc_hd__inv_4".
+Reading "M3_sky130_fd_sc_hd__o2111ai_4".
+Reading "M3_sky130_fd_sc_hd__clkinv_4".
+Reading "M3_sky130_fd_sc_hd__a21bo_1".
+Reading "M3_sky130_fd_sc_hd__xnor2_1".
+Reading "M3_sky130_fd_sc_hd__o211a_1".
+Reading "M3_sky130_fd_sc_hd__and2_4".
+Reading "M3_sky130_fd_sc_hd__a21oi_4".
+Reading "M3_sky130_fd_sc_hd__o22ai_2".
+Reading "M3_sky130_fd_sc_hd__a2111o_1".
+Reading "M3_sky130_fd_sc_hd__nor2_8".
+Reading "M3_sky130_fd_sc_hd__o21ba_1".
+Reading "M3_sky130_fd_sc_hd__or2_4".
+Reading "M3_sky130_fd_sc_hd__o221a_1".
+Reading "M3_sky130_fd_sc_hd__o31a_2".
+Reading "M3_sky130_fd_sc_hd__a22oi_4".
+Reading "M3_sky130_fd_sc_hd__dfxtp_4".
+Reading "M3_sky130_fd_sc_hd__o311a_1".
+Reading "M3_sky130_fd_sc_hd__mux4_2".
+Reading "M3_sky130_fd_sc_hd__a32o_1".
+Reading "M3_sky130_fd_sc_hd__or3b_1".
+Reading "M3_sky130_fd_sc_hd__a22o_4".
+Reading "M3_sky130_fd_sc_hd__a211oi_4".
+Reading "M3_sky130_fd_sc_hd__a221oi_1".
+Reading "M3_sky130_fd_sc_hd__a221oi_4".
+Reading "M3_sky130_fd_sc_hd__o311a_2".
+Reading "M3_sky130_fd_sc_hd__o31a_1".
+Reading "M3_sky130_fd_sc_hd__a31o_1".
+Reading "M3_sky130_fd_sc_hd__dfxtp_2".
+Reading "M3_sky130_fd_sc_hd__a21oi_1".
+Reading "M3_sky130_fd_sc_hd__a211o_4".
+Reading "M3_sky130_fd_sc_hd__buf_8".
+Reading "M3_sky130_fd_sc_hd__dfrtp_4".
+Reading "M3_sky130_fd_sc_hd__nor2_4".
+Reading "M3_sky130_fd_sc_hd__a211o_1".
+Reading "M3_sky130_fd_sc_hd__o2bb2a_1".
+Reading "M3_sky130_fd_sc_hd__o22a_1".
+Reading "M3_sky130_fd_sc_hd__mux2_2".
+Reading "M3_sky130_fd_sc_hd__o21ai_1".
+Reading "M3_sky130_fd_sc_hd__o21ai_4".
+Reading "M3_sky130_fd_sc_hd__a211oi_1".
+Reading "M3_sky130_fd_sc_hd__mux4_1".
+Reading "M3_sky130_fd_sc_hd__and4bb_1".
+Reading "M3_sky130_fd_sc_hd__mux2_4".
+Reading "M3_sky130_fd_sc_hd__and2_1".
+Reading "M3_sky130_fd_sc_hd__or4_4".
+Reading "M3_sky130_fd_sc_hd__or3_1".
+Reading "M3_sky130_fd_sc_hd__nand2_4".
+Reading "M3_sky130_fd_sc_hd__or4b_4".
+Reading "M3_sky130_fd_sc_hd__or3_4".
+Reading "M3_sky130_fd_sc_hd__nor3_1".
+Reading "M3_sky130_fd_sc_hd__a22o_1".
+Reading "M3_sky130_fd_sc_hd__or2_1".
+Reading "M3_sky130_fd_sc_hd__and4_1".
+Reading "M3_sky130_fd_sc_hd__nand2_1".
+Reading "M3_sky130_fd_sc_hd__a21o_1".
+Reading "M3_sky130_fd_sc_hd__and2b_1".
+Reading "M3_sky130_fd_sc_hd__or4b_1".
+Reading "M3_sky130_fd_sc_hd__nor4_4".
+Reading "M3_sky130_fd_sc_hd__nand3_1".
+Reading "M3_sky130_fd_sc_hd__nor3_4".
+Reading "M3_sky130_fd_sc_hd__and3_1".
+Reading "M3_sky130_fd_sc_hd__a2bb2o_1".
+Reading "M3_sky130_fd_sc_hd__dfstp_1".
+Reading "M3_sky130_fd_sc_hd__dfxtp_1".
+Reading "M3_sky130_fd_sc_hd__or4_1".
+Reading "M3_sky130_fd_sc_hd__o21a_1".
+Reading "M3_sky130_fd_sc_hd__a221o_1".
+Reading "M3_sky130_fd_sc_hd__clkbuf_16".
+Reading "M3_sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "M3_sky130_fd_sc_hd__nor2_1".
+Reading "M3_sky130_fd_sc_hd__dfrtp_1".
+Reading "M3_sky130_fd_sc_hd__clkbuf_4".
+Reading "M3_sky130_fd_sc_hd__diode_2".
+Reading "M3_sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "M3_sky130_fd_sc_hd__clkbuf_8".
+Reading "M3_sky130_fd_sc_hd__buf_4".
+Reading "M3_sky130_fd_sc_hd__buf_6".
+Reading "M3_sky130_fd_sc_hd__o31ai_1".
+Reading "M3_sky130_fd_sc_hd__nand2b_1".
+Reading "M3_sky130_fd_sc_hd__a311oi_1".
+Reading "M3_sky130_fd_sc_hd__nand2b_4".
+Reading "M3_sky130_fd_sc_hd__or4bb_1".
+Reading "M3_sky130_fd_sc_hd__o32a_1".
+Reading "M3_sky130_fd_sc_hd__o21bai_1".
+Reading "M3_sky130_fd_sc_hd__nor3_2".
+Reading "M3_sky130_fd_sc_hd__nand4b_1".
+Reading "M3_sky130_fd_sc_hd__xor2_4".
+Reading "M3_sky130_fd_sc_hd__o21ba_2".
+Reading "M3_sky130_fd_sc_hd__a2111o_2".
+Reading "M3_sky130_fd_sc_hd__or3b_4".
+Reading "M3_sky130_fd_sc_hd__a31oi_4".
+Reading "M3_sky130_fd_sc_hd__nand3b_1".
+Reading "M3_sky130_fd_sc_hd__nor4b_2".
+Reading "M3_sky130_fd_sc_hd__a41o_2".
+Reading "M3_sky130_fd_sc_hd__nor3b_4".
+Reading "M3_sky130_fd_sc_hd__a2111o_4".
+Reading "M3_sky130_fd_sc_hd__a2111oi_4".
+Reading "M3_sky130_fd_sc_hd__o32ai_1".
+Reading "M3_sky130_fd_sc_hd__and4bb_2".
+Reading "M3_sky130_fd_sc_hd__or4b_2".
+Reading "M3_sky130_fd_sc_hd__nor3b_1".
+Reading "M3_sky130_fd_sc_hd__nor4_2".
+Reading "M3_sky130_fd_sc_hd__a311oi_4".
+Reading "M3_sky130_fd_sc_hd__o21bai_2".
+Reading "M3_sky130_fd_sc_hd__nor3b_2".
+Reading "M3_sky130_fd_sc_hd__a311oi_2".
+Reading "M3_sky130_fd_sc_hd__and3b_4".
+Reading "M3_sky130_fd_sc_hd__a2bb2o_4".
+Reading "M3_sky130_fd_sc_hd__a21bo_4".
+Reading "M3_sky130_fd_sc_hd__xnor2_4".
+Reading "M3_sky130_fd_sc_hd__o311ai_4".
+Reading "M3_sky130_fd_sc_hd__o2bb2a_4".
+Reading "M3_sky130_fd_sc_hd__o211a_4".
+Reading "M3_sky130_fd_sc_hd__and2b_4".
+Reading "M3_sky130_fd_sc_hd__o21bai_4".
+Reading "M3_sky130_fd_sc_hd__nand3b_4".
+Reading "M3_sky130_fd_sc_hd__o2111ai_1".
+Reading "M3_sky130_fd_sc_hd__nand4_4".
+Reading "M3_sky130_fd_sc_hd__o221ai_2".
+Reading "M3_sky130_fd_sc_hd__o211ai_1".
+Reading "M3_sky130_fd_sc_hd__o2bb2ai_4".
+Reading "M3_sky130_fd_sc_hd__o22a_4".
+Reading "M3_sky130_fd_sc_hd__nor4b_1".
+Reading "M3_sky130_fd_sc_hd__o2111a_2".
+Reading "M3_ycr_core_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+Reading "M3_sky130_fd_sc_hd__and3b_2".
+Reading "M3_sky130_fd_sc_hd__nand4_2".
+Reading "M3_sky130_fd_sc_hd__o31ai_2".
+Reading "M3_sky130_fd_sc_hd__nand3_2".
+Reading "M3_sky130_fd_sc_hd__or2b_1".
+Reading "M3_sky130_fd_sc_hd__o2bb2ai_2".
+Reading "M3_sky130_fd_sc_hd__or2b_2".
+Reading "M3_sky130_fd_sc_hd__and4_4".
+Reading "M3_sky130_fd_sc_hd__a221o_4".
+Reading "M3_sky130_fd_sc_hd__or4bb_4".
+Reading "M3_sky130_fd_sc_hd__or2b_4".
+Reading "M3_sky130_fd_sc_hd__o41ai_4".
+Reading "M3_sky130_fd_sc_hd__a21boi_4".
+Reading "M3_sky130_fd_sc_hd__o221ai_1".
+Reading "M3_sky130_fd_sc_hd__o31a_4".
+Reading "M3_sky130_fd_sc_hd__buf_1".
+Reading "M3_sky130_fd_sc_hd__dlygate4sd1_1".
+Reading "M3_sky130_fd_sc_hd__mux2_8".
+Reading "M3_ycr4_iconnect".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+    75000 uses
+    80000 uses
+    85000 uses
+    90000 uses
+    95000 uses
+    100000 uses
+Reading "M3_sky130_fd_sc_hd__a2111oi_2".
+Reading "M3_sky130_fd_sc_hd__a2111oi_1".
+Reading "M3_sky130_fd_sc_hd__o2bb2ai_1".
+Reading "M3_sky130_fd_sc_hd__o41a_4".
+Reading "M3_sky130_fd_sc_hd__nand4b_4".
+Reading "M3_sky130_fd_sc_hd__a32o_4".
+Reading "M3_sky130_fd_sc_hd__or4bb_2".
+Reading "M3_ycr_intf".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+Reading "M3_switchn".
+Reading "M3_resistor".
+Reading "M3_resistor_3xh".
+Reading "M3_switch2".
+Reading "M3_switch2n".
+Reading "M3_2bit_DAC".
+Reading "M3_resistor_h".
+Reading "M3_3bit_DAC".
+Reading "M3_4bit_DAC".
+Reading "M3_5bit_DAC".
+Reading "M3_6bit_DAC".
+Reading "M3_7bit_DAC".
+Reading "M3_8bit_DAC".
+Reading "M3_2x8bit_DAC".
+Reading "M3_4x8bit_DAC".
+Reading "M3_dac_top".
+Reading "M3_sky130_fd_sc_hd__einvn_8".
+Reading "M3_sky130_fd_sc_hd__clkinv_1".
+Reading "M3_sky130_fd_sc_hd__einvp_2".
+Reading "M3_sky130_fd_sc_hd__einvn_2".
+Reading "M3_sky130_fd_sc_hd__a21boi_2".
+Reading "M3_sky130_fd_sc_hd__clkinv_8".
+Reading "M3_sky130_fd_sc_hd__einvp_1".
+Reading "M3_dg_pll".
+Reading "M3_sky130_fd_sc_hd__a41oi_4".
+Reading "M3_sky130_fd_sc_hd__o21a_4".
+Reading "M3_sky130_fd_sc_hd__o311a_4".
+Reading "M3_sky130_fd_sc_hd__o221a_4".
+Reading "M3_sky130_fd_sc_hd__a41o_4".
+Reading "M3_wb_interconnect".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+Reading "M3_sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "M3_sky130_fd_sc_hd__o41a_2".
+Reading "M3_sky130_fd_sc_hd__a211oi_2".
+Reading "M3_sky130_fd_sc_hd__clkdlybuf4s50_1".
+Reading "M3_qspim_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+Reading "M3_sky130_fd_sc_hd__dlclkp_1".
+Reading "M3_sky130_fd_sc_hd__dlclkp_4".
+Reading "M3_sky130_fd_sc_hd__a32oi_4".
+Reading "M3_sky130_fd_sc_hd__o311ai_2".
+Reading "M3_sky130_fd_sc_hd__o2111ai_2".
+Reading "M3_wb_host".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+Reading "M3_sky130_fd_sc_hd__and4b_4".
+Reading "M3_sky130_fd_sc_hd__nor2b_2".
+Reading "M3_sky130_fd_sc_hd__nor2b_1".
+Reading "M3_uart_i2c_usb_spi_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+Reading "M3_sky130_fd_sc_hd__dlxtn_1".
+Reading "M3_sky130_fd_sc_hd__dlxtn_2".
+Reading "M3_sky130_fd_sc_hd__nand4b_2".
+Reading "M3_sky130_fd_sc_hd__a32oi_1".
+Reading "M3_pinmux_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+Reading "user_project_wrapper".
+Reading "sky130_ef_io__com_bus_slice_20um".
+Reading "sky130_fd_io__corner_bus_overlay".
+Reading "sky130_ef_io__corner_pad".
+Reading "sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um".
+Reading "sky130_ef_io__com_bus_slice_1um".
+Reading "sky130_ef_io__com_bus_slice_5um".
+Reading "sky130_ef_io__com_bus_slice_10um".
+Reading "sky130_fd_pr__hvdfl1sd__example_5595914180851".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808664".
+Reading "sky130_fd_io__sio_clamp_pcap_4x5".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808680".
+Reading "sky130_fd_io__esd_rcclamp_nfetcap".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808336".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808666".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808665".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808678".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808679".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808677".
+Reading "sky130_fd_pr__via_pol1__example_5595914180839".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808667".
+Reading "sky130_fd_pr__hvdftpl1s__example_55959141808671".
+Reading "sky130_fd_pr__hvdftpl1s2__example_55959141808672".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808673".
+Reading "sky130_fd_pr__dfl1__example_55959141808663".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808660".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808670".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808668".
+Reading "sky130_fd_pr__hvdftpl1s__example_55959141808675".
+Reading "sky130_fd_pr__hvdftpl1s2__example_55959141808676".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808674".
+Reading "sky130_fd_pr__dfl1__example_55959141808662".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808661".
+Reading "sky130_fd_pr__via_l1m1__example_559591418084".
+Reading "sky130_fd_pr__genrivetdlring__example_559591418082".
+Reading "sky130_fd_pr__gendlring__example_559591418081".
+Reading "sky130_fd_pr__padplhp__example_559591418080".
+Reading "sky130_fd_io__pad_esd".
+Reading "sky130_fd_io__com_bus_slice".
+Reading "sky130_fd_io__com_bus_hookup".
+Reading "sky130_fd_io__com_busses_esd".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808669".
+Reading "sky130_fd_io__top_ground_hvc_wpad".
+Reading "sky130_fd_io__overlay_vssa_hvc".
+Reading "sky130_ef_io__hvc_vdda_overlay".
+Reading "sky130_ef_io__vssa_hvc_clamped_pad".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808719".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808767".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808765".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808764".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808720".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808718".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808717".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808716".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808243".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808723".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808722".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180890".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808721".
+Reading "sky130_fd_io__xres_inv_hysv2".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180838".
+Reading "sky130_fd_io__tk_tie_r_out_esd".
+Reading "sky130_fd_io__res250_sub_small".
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 704338550): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 704338582): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 704341174): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 704341206): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 704341238): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 704341270): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 704341302): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 704341398): NODE elements not supported: skipping.
+Reading "sky130_fd_io__res250only_small".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808264".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180858".
+Reading "sky130_fd_pr__via_pol1__example_5595914180833".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180864".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808715".
+Reading "sky130_fd_pr__res_bent_po__example_5595914180863".
+Reading "sky130_fd_pr__res_bent_po__example_5595914180862".
+Reading "sky130_fd_io__tk_em1s_cdns_55959141808288".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180859".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808289".
+Reading "sky130_fd_io__com_res_weak_v2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808274".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808728".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808727".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808726".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808725".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808724".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808554".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808553".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808552".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808551".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808402".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808350".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808261".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808260".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808259".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808400".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808372".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808326".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808290".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808128".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808127".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180897".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180819".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808555".
+Reading "sky130_fd_pr__via_pol1__example_55959141808147".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808157".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808156".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808155".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808154".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808153".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808152".
+Reading "sky130_fd_pr__tpl1__example_55959141808151".
+Reading "sky130_fd_pr__tpl1__example_55959141808150".
+Reading "sky130_fd_pr__tpl1__example_55959141808149".
+Reading "sky130_fd_pr__tpl1__example_55959141808148".
+Reading "sky130_fd_pr__dfl1__example_55959141808158".
+Reading "sky130_fd_io__signal_5_sym_hv_local_5term".
+Reading "sky130_fd_io__gpio_buf_localesdv2".
+Reading "sky130_fd_pr__via_pol1__example_559591418083".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808137".
+Reading "sky130_fd_pr__dfl1sd__example_559591418086".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808371".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808370".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808369".
+Reading "sky130_fd_io__hvsbt_inv_x1".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808316".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808421".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808385".
+Reading "sky130_fd_pr__dfl1sd__example_559591418088".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808422".
+Reading "sky130_fd_io__hvsbt_inv_x2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808612".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808616".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808615".
+Reading "sky130_fd_io__hvsbt_inv_x4".
+Reading "sky130_fd_pr__hvdfm1sd__example_5595914180848".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180849".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808766".
+Reading "sky130_fd_pr__via_m2m3__example_55959141808714".
+Reading "sky130_fd_pr__via_pol1_centered__example_559591418081".
+Reading "sky130_fd_io__tk_em2s_cdns_55959141808652".
+Reading "sky130_fd_io__tk_em2o_cdns_55959141808653".
+Reading "sky130_fd_pr__via_l1m1_centered__example_5595914180812".
+Reading "sky130_fd_pr__via_l1m1_centered__example_5595914180811".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418086".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418084".
+Reading "sky130_fd_pr__hvdftpm1s2__example_55959141808659".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808658".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808657".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808202".
+Reading "sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2".
+Reading "sky130_fd_io__gpio_pudrvr_strong_axres4v2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808273".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808740".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808739".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808738".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808737".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808736".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808735".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808734".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808733".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808732".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808731".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808730".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808752".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808751".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808750".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808749".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808748".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808747".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808746".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808745".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808744".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808743".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808742".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808741".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808324".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808270".
+Reading "sky130_fd_pr__dfl1__example_55959141808187".
+Reading "sky130_fd_pr__res_generic_nd__example_55959141808755".
+Reading "sky130_fd_pr__res_generic_nd__example_55959141808754".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808338".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808337".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808763".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808700".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808559".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808762".
+Reading "sky130_fd_pr__dfl1__example_55959141808729".
+Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808758".
+Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808757".
+Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808756".
+Reading "sky130_fd_io__xres_tk_p_em1c_cdns_55959141808761".
+Reading "sky130_fd_io__xres_tk_p_em1c_cdns_55959141808760".
+Reading "sky130_fd_io__xres_tk_p_em1c_cdns_55959141808759".
+Reading "sky130_fd_io__xres_p_em1c_cdns_55959141808753".
+Reading "sky130_fd_io__xres2v2_rcfilter_lpfv2".
+Reading "sky130_fd_io__tk_em1o_cdns_5595914180860".
+Reading "sky130_fd_pr__res_bent_po__example_5595914180861".
+Reading "sky130_fd_io__com_res_weak_bentbigres".
+Reading "sky130_fd_io__com_res_weak".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180857".
+Reading "sky130_fd_pr__hvdftpm1s2__example_55959141808649".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808651".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808650".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808648".
+Reading "sky130_fd_pr__hvdftpl1s__example_55959141808646".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808647".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808645".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808378".
+Reading "sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2".
+Reading "sky130_fd_io__gpio_pddrvr_strong_xres4v2".
+Reading "sky130_fd_io__top_gpio_pad".
+Reading "sky130_fd_io__com_busses".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808768".
+Reading "sky130_fd_pr__res_bent_nd__example_55959141808769".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808787".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808786".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808782".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808785".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808449".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808784".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808452".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808783".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808781".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808780".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808779".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808233".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180827".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808778".
+Reading "sky130_fd_pr__hvdfm1sd__example_5595914180835".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808777".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808776".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808775".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808242".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808774".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180829".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808773".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808237".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808772".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808771".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808770".
+Reading "sky130_fd_io__tap_1".
+Reading "sky130_fd_io__inv_1".
+Reading "sky130_fd_pr__pfet_01v8__example_559591418085".
+Reading "sky130_fd_pr__nfet_01v8__example_559591418089".
+Reading "sky130_fd_pr__nfet_01v8__example_559591418087".
+Reading "sky130_fd_io__hvsbt_nand2".
+Reading "sky130_fd_io__xres4v2_in_buf".
+Reading "sky130_fd_io__top_xres4v2".
+Reading "sky130_fd_sc_hd__fill_4".
+Reading "sky130_fd_sc_hd__fill_8".
+Reading "constant_block".
+Reading "sky130_fd_io__res75only_small".
+Reading "sky130_fd_io__com_bus_slice_m4".
+Reading "sky130_fd_io__overlay_gpiov2_m4".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808420".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808419".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808418".
+Reading "sky130_fd_io__hvsbt_nor".
+Reading "sky130_fd_io__hvsbt_nand2v2".
+Reading "sky130_fd_io__gpiov2_ictl_logic".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808190".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808611".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180811".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808549".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808548".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808191".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808189".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808517".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808518".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808610".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808609".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180815".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180816".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808608".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808604".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808533".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808529".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180884".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808230".
+Reading "sky130_fd_io__gpiov2_in_buf".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808537".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808106".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808481".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808607".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808504".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808600".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808550".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808528".
+Reading "sky130_fd_io__gpiov2_ipath_hvls".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808595".
+Reading "sky130_fd_pr__nfet_01v8__example_5595914180825".
+Reading "sky130_fd_io__gpiov2_inbuf_lvinv_x1".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180812".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808599".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808598".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808597".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808596".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808547".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808546".
+Reading "sky130_fd_io__gpiov2_ipath_lvls".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808606".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180875".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808605".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808540".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808603".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808602".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808601".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808535".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808527".
+Reading "sky130_fd_io__gpiov2_vcchib_in_buf".
+Reading "sky130_fd_io__gpiov2_ibuf_se".
+Reading "sky130_fd_io__gpiov2_buf_localesd".
+Reading "sky130_fd_io__gpiov2_ipath".
+Reading "sky130_fd_io__tk_em2s_cdns_55959141808438".
+Reading "sky130_fd_io__tk_em2o_cdns_55959141808439".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180882".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180881".
+Reading "sky130_fd_io__tk_em1o_cdns_5595914180880".
+Reading "sky130_fd_io__tk_em1o_cdns_5595914180879".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808430".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180823".
+Reading "sky130_fd_pr__pfet_01v8__example_5595914180822".
+Reading "sky130_fd_pr__pfet_01v8__example_5595914180813".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808624".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808510".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808623".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808622".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808621".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808620".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808619".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808618".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808116".
+Reading "sky130_fd_io__com_ctl_lsv2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808394".
+Reading "sky130_fd_pr__via_pol1__example_55959141808298".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808440".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180878".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808434".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808435".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808433".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808432".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808102".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808431".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808115".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808429".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808428".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808100".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808140".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808427".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808426".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808280".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808425".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808424".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808423".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808306".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808383".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808382".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808380".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808379".
+Reading "sky130_fd_io__com_ctl_ls_v2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808617".
+Reading "sky130_fd_io__com_ctl_ls_en_1_v2".
+Reading "sky130_fd_io__com_ctl_ls_1v2".
+Reading "sky130_fd_io__gpiov2_ctl_lsbank".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808614".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808613".
+Reading "sky130_fd_io__hvsbt_inv_x8v2".
+Reading "sky130_fd_io__hvsbt_inv_x8".
+Reading "sky130_fd_io__com_ctl_ls".
+Reading "sky130_fd_io__com_ctl_hldv2".
+Reading "sky130_fd_io__gpiov2_ctl".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808178".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808591".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808594".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808593".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808488".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808592".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808586".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808122".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808123".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808477".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808476".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808475".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808589".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808570".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808569".
+Reading "sky130_fd_io__gpiov2_amux_ctl_lshv2hv".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808588".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808587".
+Reading "sky130_fd_io__gpiov2_amux_ctl_lshv2hv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808590".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808460".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808468".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808467".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808466".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808465".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808464".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808463".
+Reading "sky130_fd_io__gpiov2_amux_ctl_ls".
+Reading "sky130_fd_io__gpiov2_amux_ctl_inv_1".
+Reading "sky130_fd_io__gpiov2_amux_ls".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808573".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808572".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808579".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808578".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808577".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808576".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808566".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180868".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180869".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808565".
+Reading "sky130_fd_io__gpiov2_amx_pucsd_inv".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808441".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808571".
+Reading "sky130_fd_io__gpiov2_amx_inv4".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808567".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808568".
+Reading "sky130_fd_io__gpiov2_amux_drvr_lshv2hv".
+Reading "sky130_fd_io__gpiov2_amux_drvr_lshv2hv2".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808581".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808580".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808278".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808462".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808583".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808582".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808498".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808497".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808496".
+Reading "sky130_fd_io__gpiov2_amux_drvr_ls".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808574".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808575".
+Reading "sky130_fd_io__amx_inv1".
+Reading "sky130_fd_io__gpiov2_amux_drvr".
+Reading "sky130_fd_io__xor2_1".
+Reading "sky130_fd_io__nor2_1".
+Reading "sky130_fd_io__nand2_1".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808200".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808457".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808451".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808450".
+Reading "sky130_fd_pr__hvdfl1sd__example_5595914180894".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808584".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808455".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808447".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808445".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808248".
+Reading "sky130_fd_io__gpiov2_amux_nand5".
+Reading "sky130_fd_pr__dfm1sd__example_55959141808258".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808585".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808446".
+Reading "sky130_fd_io__gpiov2_amux_nand4".
+Reading "sky130_fd_io__gpiov2_amux_decoder".
+Reading "sky130_fd_io__gpiov2_amux_ctl_logic".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808563".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808564".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808562".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808251".
+Reading "sky130_fd_pr__dfm1sd2__example_55959141808561".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808560".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808558".
+Reading "sky130_fd_io__amux_switch_1v2b".
+Reading "sky130_fd_io__gpiov2_amux".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808416".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808417".
+Reading "sky130_fd_io__hvsbt_xorv2".
+Reading "sky130_fd_io__hvsbt_xor".
+Reading "sky130_fd_io__com_ctl_ls_octl".
+Reading "sky130_fd_io__gpiov2_octl".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808267".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808266".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808642".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808184".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808141".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808643".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808183".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808139".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808636".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808635".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808634".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808633".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808632".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808630".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808638".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808637".
+Reading "sky130_fd_io__gpiov2_pdpredrvr_strong_nr3".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808629".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808628".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808627".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808626".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808354".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808631".
+Reading "sky130_fd_io__gpiov2_pdpredrvr_strong_nr2".
+Reading "sky130_fd_pr__nfet_01v8__example_5595914180888".
+Reading "sky130_fd_io__gpiov2_octl_mux".
+Reading "sky130_fd_pr__via_pol1__example_55959141808322".
+Reading "sky130_fd_pr__via_pol1__example_55959141808321".
+Reading "sky130_fd_pr__via_pol1__example_55959141808320".
+Reading "sky130_fd_pr__via_pol1__example_55959141808294".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808325".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808323".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808291".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808641".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808640".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808639".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808348".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808347".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808194".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808346".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808345".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808344".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808343".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808334".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808333".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808332".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808331".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808330".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808329".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808304".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808134".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808328".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808327".
+Reading "sky130_fd_io__com_pdpredrvr_pbiasv2".
+Reading "sky130_fd_io__gpiov2_pdpredrvr_strong".
+Reading "sky130_fd_pr__via_pol1__example_55959141808272".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808271".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808143".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808142".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808101".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808144".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_5595914180899".
+Reading "sky130_fd_pr__via_pol1__example_55959141808275".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808276".
+Reading "sky130_fd_pr__res_generic_po__example_55959141808286".
+Reading "sky130_fd_pr__res_generic_po__example_55959141808285".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808284".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808283".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808644".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808287".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808282".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808281".
+Reading "sky130_fd_io__gpiov2_pupredrvr_strong_nd2_a".
+Reading "sky130_fd_io__gpiov2_pupredrvr_strong_nd2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808297".
+Reading "sky130_fd_pr__via_pol1__example_55959141808296".
+Reading "sky130_fd_pr__via_pol1__example_55959141808295".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808293".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808292".
+Reading "sky130_fd_pr__tpl1__example_55959141808300".
+Reading "sky130_fd_pr__tpl1__example_55959141808299".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808319".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808318".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808317".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808315".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808314".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808313".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808312".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808311".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808310".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808309".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808308".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808307".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808305".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808303".
+Reading "sky130_fd_io__tk_em1s_cdns_55959141808301".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808302".
+Reading "sky130_fd_io__feascom_pupredrvr_nbiasv2".
+Reading "sky130_fd_io__gpio_pupredrvr_strongv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808361".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808360".
+Reading "sky130_fd_io__feas_com_pupredrvr_weak".
+Reading "sky130_fd_pr__via_pol1__example_5595914180854".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808363".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808362".
+Reading "sky130_fd_io__com_pupredrvr_strong_slowv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808366".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808365".
+Reading "sky130_fd_io__com_pdpredrvr_weakv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808364".
+Reading "sky130_fd_io__com_pdpredrvr_strong_slowv2".
+Reading "sky130_fd_io__gpiov2_obpredrvr".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808368".
+Reading "sky130_fd_pr__tpl1__example_55959141808625".
+Reading "sky130_fd_pr__via_pol1__example_55959141808373".
+Reading "sky130_fd_pr__tpl1__example_55959141808374".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808393".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808392".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808391".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808390".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808389".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808388".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808387".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808386".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808384".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808381".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808377".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808376".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808375".
+Reading "sky130_fd_io__gpio_dat_lsv2".
+Reading "sky130_fd_io__gpio_dat_ls_1v2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808398".
+Reading "sky130_fd_pr__via_pol1__example_55959141808397".
+Reading "sky130_fd_pr__via_pol1__example_55959141808396".
+Reading "sky130_fd_pr__via_pol1__example_55959141808395".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808401".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808399".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808269".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808410".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808409".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808408".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808407".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808406".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808405".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808404".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808403".
+Reading "sky130_fd_io__com_cclat".
+Reading "sky130_fd_io__com_opath_datoev2".
+Reading "sky130_fd_io__gpiov2_octl_dat".
+Reading "sky130_fd_pr__via_pol1_centered__example_559591418080".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180832".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180856".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180855".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180853".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180852".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418083".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418082".
+Reading "sky130_fd_io__nfet_con_diff_wo_abt_270v2".
+Reading "sky130_fd_io__gpiov2_pddrvr_strong".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418085".
+Reading "sky130_fd_io__pfet_con_diff_wo_abt_270v2".
+Reading "sky130_fd_io__gpio_pudrvr_strongv2".
+Reading "sky130_fd_pr__nfet_01v8__example_5595914180850".
+Reading "sky130_fd_io__gpio_pddrvr_weakv2".
+Reading "sky130_fd_io__gpio_pddrvr_strong_slowv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808656".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808655".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808654".
+Reading "sky130_fd_io__com_pudrvr_weakv2".
+Reading "sky130_fd_io__com_pudrvr_strong_slowv2".
+Reading "sky130_fd_io__gpio_odrvr_subv2".
+Reading "sky130_fd_io__gpio_odrvrv2".
+Reading "sky130_fd_io__gpio_opathv2".
+Reading "sky130_fd_io__top_gpiov2".
+Reading "sky130_fd_io__overlay_gpiov2".
+Reading "sky130_ef_io__gpiov2_pad".
+Reading "sky130_ef_io__gpiov2_pad_wrapped".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808691".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808687".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808684".
+Reading "sky130_fd_pr__tpl1__example_55959141808686".
+Reading "sky130_fd_pr__tpl1__example_55959141808685".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808683".
+Reading "sky130_fd_io__gnd2gnd_strap".
+Reading "sky130_fd_io__gnd2gnd_tap".
+Reading "sky130_fd_io__gnd2gnd_diff".
+Reading "sky130_fd_io__gnd2gnd_sub_dnwl".
+Reading "sky130_fd_io__gnd2gnd_120x2_lv_isosub".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808690".
+Reading "sky130_fd_pr__dftpl1s2__example_55959141808702".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808705".
+Reading "sky130_fd_pr__dfl1__example_55959141808682".
+Reading "sky130_fd_pr__dftpl1s2__example_55959141808694".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808693".
+Reading "sky130_fd_pr__dfl1__example_55959141808681".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808688".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808699".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808698".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808697".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808696".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808695".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808704".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808703".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808701".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808689".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808692".
+Reading "sky130_fd_io__top_ground_lvc_wpad".
+Reading "sky130_fd_io__overlay_vssd_lvc".
+Reading "sky130_ef_io__lvc_vccdx_overlay".
+Reading "sky130_ef_io__vssd_lvc_clamped_pad".
+Reading "sky130_fd_io__overlay_vssio_hvc".
+Reading "sky130_ef_io__hvc_vssio_overlay".
+Reading "sky130_ef_io__vssio_hvc_clamped_pad".
+Reading "sky130_fd_io__hvc_clampv2".
+Reading "sky130_fd_io__top_power_hvc_wpadv2".
+Reading "sky130_fd_io__overlay_vdda_hvc".
+Reading "sky130_ef_io__vdda_hvc_clamped_pad".
+Reading "sky130_fd_io__top_power_lvc_wpad".
+Reading "sky130_fd_io__overlay_vccd_lvc".
+Reading "sky130_ef_io__vccd_lvc_clamped_pad".
+Reading "sky130_ef_io__disconnect_vdda_slice_5um".
+Reading "sky130_fd_io__overlay_vddio_hvc".
+Reading "sky130_ef_io__hvc_vddio_overlay".
+Reading "sky130_ef_io__vddio_hvc_clamped_pad".
+Reading "chip_io_gpio_connects".
+Reading "sky130_ef_io__lvc_vccdy_overlay".
+Reading "sky130_ef_io__vssd_lvc_clamped3_pad".
+Reading "sky130_ef_io__vccd_lvc_clamped3_pad".
+Reading "chip_io".
+Reading "gpio_signal_buffering".
+Reading "caravel".
+Flattening layout of tile x=0 y=0. . . 
+Flattening layout of tile x=1 y=0. . . 
+Flattening layout of tile x=2 y=0. . . 
+Flattening layout of tile x=3 y=0. . . 
+Flattening layout of tile x=4 y=0. . . 
+Flattening layout of tile x=5 y=0. . . 
+Flattening layout of tile x=0 y=1. . . 
+Flattening layout of tile x=1 y=1. . . 
+Flattening layout of tile x=2 y=1. . . 
+Flattening layout of tile x=3 y=1. . . 
+Flattening layout of tile x=4 y=1. . . 
+Flattening layout of tile x=5 y=1. . . 
+Flattening layout of tile x=0 y=2. . . 
+Flattening layout of tile x=1 y=2. . . 
+Flattening layout of tile x=2 y=2. . . 
+Flattening layout of tile x=3 y=2. . . 
+Flattening layout of tile x=4 y=2. . . 
+Flattening layout of tile x=5 y=2. . . 
+Flattening layout of tile x=0 y=3. . . 
+Flattening layout of tile x=1 y=3. . . 
+Flattening layout of tile x=2 y=3. . . 
+Flattening layout of tile x=3 y=3. . . 
+Flattening layout of tile x=4 y=3. . . 
+Flattening layout of tile x=5 y=3. . . 
+Flattening layout of tile x=0 y=4. . . 
+Flattening layout of tile x=1 y=4. . . 
+Flattening layout of tile x=2 y=4. . . 
+Flattening layout of tile x=3 y=4. . . 
+Flattening layout of tile x=4 y=4. . . 
+Flattening layout of tile x=5 y=4. . . 
+Flattening layout of tile x=0 y=5. . . 
+Flattening layout of tile x=1 y=5. . . 
+Flattening layout of tile x=2 y=5. . . 
+Flattening layout of tile x=3 y=5. . . 
+Flattening layout of tile x=4 y=5. . . 
+Flattening layout of tile x=5 y=5. . . 
+Flattening layout of tile x=0 y=6. . . 
+Flattening layout of tile x=1 y=6. . . 
+Flattening layout of tile x=2 y=6. . . 
+Flattening layout of tile x=3 y=6. . . 
+Flattening layout of tile x=4 y=6. . . 
+Flattening layout of tile x=5 y=6. . . 
+Flattening layout of tile x=0 y=7. . . 
+Flattening layout of tile x=1 y=7. . . 
+Flattening layout of tile x=2 y=7. . . 
+Flattening layout of tile x=3 y=7. . . 
+Flattening layout of tile x=4 y=7. . . 
+Flattening layout of tile x=5 y=7. . . 
+Ended: 12/04/2022 06:04:22
diff --git a/tapeout/logs/fill_intermediate.log b/tapeout/logs/fill_intermediate.log
new file mode 100644
index 0000000..2bf43ef
--- /dev/null
+++ b/tapeout/logs/fill_intermediate.log
@@ -0,0 +1,19819 @@
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Using the terminal as the console.
+Starting magic under Tcl interpreter
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Using the terminal as the console.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Using NULL graphics device.
+Using NULL graphics device.
+Using NULL graphics device.
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Using NULL graphics device.
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Using NULL graphics device.
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+Processing system .magicrc file
+Processing system .magicrc file
+2 Magic internal units = 1 Lambda
+Sourcing design .magicrc for technology sky130A ...
+Processing system .magicrc file
+Processing system .magicrc file
+2 Magic internal units = 1 Lambda
+Sourcing design .magicrc for technology sky130A ...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+Sourcing design .magicrc for technology sky130A ...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+Sourcing design .magicrc for technology sky130A ...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Sourcing design .magicrc for technology sky130A ...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+Sourcing design .magicrc for technology sky130A ...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+Sourcing design .magicrc for technology sky130A ...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Loading sky130A Device Generator Menu ...
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Scaled tech values by 2 / 1 to match internal grid scaling
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading sky130A Device Generator Menu ...
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Scaled tech values by 2 / 1 to match internal grid scaling
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading sky130A Device Generator Menu ...
+Loading sky130A Device Generator Menu ...
+Loading sky130A Device Generator Menu ...
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading sky130A Device Generator Menu ...
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading sky130A Device Generator Menu ...
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading sky130A Device Generator Menu ...
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading sky130A Device Generator Menu ...
+Scaled tech values by 2 / 1 to match internal grid scaling
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading sky130A Device Generator Menu ...
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_00088bca_fill_pattern_2_7: 10000 rects
+caravel_00088bca_fill_pattern_5_4: 10000 rects
+caravel_00088bca_fill_pattern_4_5: 10000 rects
+caravel_00088bca_fill_pattern_1_0: 10000 rects
+caravel_00088bca_fill_pattern_3_6: 10000 rects
+caravel_00088bca_fill_pattern_2_7: 20000 rects
+caravel_00088bca_fill_pattern_5_6: 10000 rects
+caravel_00088bca_fill_pattern_5_4: 20000 rects
+caravel_00088bca_fill_pattern_1_2: 10000 rects
+caravel_00088bca_fill_pattern_4_7: 10000 rects
+caravel_00088bca_fill_pattern_1_0: 20000 rects
+caravel_00088bca_fill_pattern_4_1: 10000 rects
+caravel_00088bca_fill_pattern_0_1: 10000 rects
+caravel_00088bca_fill_pattern_4_5: 20000 rects
+caravel_00088bca_fill_pattern_2_7: 30000 rects
+caravel_00088bca_fill_pattern_3_6: 20000 rects
+caravel_00088bca_fill_pattern_5_6: 20000 rects
+caravel_00088bca_fill_pattern_5_0: 10000 rects
+caravel_00088bca_fill_pattern_3_2: 10000 rects
+caravel_00088bca_fill_pattern_5_4: 30000 rects
+caravel_00088bca_fill_pattern_1_0: 30000 rects
+caravel_00088bca_fill_pattern_4_7: 20000 rects
+caravel_00088bca_fill_pattern_4_1: 20000 rects
+caravel_00088bca_fill_pattern_0_1: 20000 rects
+caravel_00088bca_fill_pattern_1_2: 20000 rects
+caravel_00088bca_fill_pattern_0_5: 10000 rects
+caravel_00088bca_fill_pattern_2_7: 40000 rects
+caravel_00088bca_fill_pattern_5_6: 30000 rects
+caravel_00088bca_fill_pattern_5_0: 20000 rects
+caravel_00088bca_fill_pattern_4_5: 30000 rects
+caravel_00088bca_fill_pattern_3_6: 30000 rects
+caravel_00088bca_fill_pattern_5_4: 40000 rects
+caravel_00088bca_fill_pattern_3_2: 20000 rects
+caravel_00088bca_fill_pattern_3_0: 10000 rects
+caravel_00088bca_fill_pattern_1_0: 40000 rects
+caravel_00088bca_fill_pattern_2_3: 10000 rects
+caravel_00088bca_fill_pattern_0_1: 30000 rects
+caravel_00088bca_fill_pattern_4_1: 30000 rects
+caravel_00088bca_fill_pattern_4_7: 30000 rects
+caravel_00088bca_fill_pattern_1_4: 10000 rects
+caravel_00088bca_fill_pattern_0_5: 20000 rects
+caravel_00088bca_fill_pattern_5_6: 40000 rects
+caravel_00088bca_fill_pattern_5_0: 30000 rects
+caravel_00088bca_fill_pattern_5_4: 50000 rects
+caravel_00088bca_fill_pattern_4_5: 40000 rects
+caravel_00088bca_fill_pattern_2_7: 50000 rects
+caravel_00088bca_fill_pattern_3_2: 30000 rects
+caravel_00088bca_fill_pattern_3_0: 20000 rects
+caravel_00088bca_fill_pattern_3_6: 40000 rects
+caravel_00088bca_fill_pattern_1_0: 50000 rects
+caravel_00088bca_fill_pattern_1_2: 30000 rects
+caravel_00088bca_fill_pattern_0_1: 40000 rects
+caravel_00088bca_fill_pattern_4_7: 40000 rects
+caravel_00088bca_fill_pattern_4_1: 40000 rects
+caravel_00088bca_fill_pattern_5_6: 50000 rects
+caravel_00088bca_fill_pattern_0_5: 30000 rects
+caravel_00088bca_fill_pattern_5_4: 60000 rects
+caravel_00088bca_fill_pattern_5_0: 40000 rects
+caravel_00088bca_fill_pattern_4_5: 50000 rects
+caravel_00088bca_fill_pattern_3_2: 40000 rects
+caravel_00088bca_fill_pattern_3_0: 30000 rects
+caravel_00088bca_fill_pattern_0_1: 50000 rects
+caravel_00088bca_fill_pattern_1_0: 60000 rects
+caravel_00088bca_fill_pattern_3_6: 50000 rects
+caravel_00088bca_fill_pattern_1_4: 20000 rects
+caravel_00088bca_fill_pattern_2_7: 60000 rects
+caravel_00088bca_fill_pattern_4_7: 50000 rects
+caravel_00088bca_fill_pattern_1_2: 40000 rects
+caravel_00088bca_fill_pattern_4_1: 50000 rects
+caravel_00088bca_fill_pattern_5_4: 70000 rects
+caravel_00088bca_fill_pattern_2_3: 20000 rects
+caravel_00088bca_fill_pattern_0_5: 40000 rects
+caravel_00088bca_fill_pattern_5_6: 60000 rects
+caravel_00088bca_fill_pattern_0_1: 60000 rects
+caravel_00088bca_fill_pattern_4_5: 60000 rects
+caravel_00088bca_fill_pattern_3_2: 50000 rects
+caravel_00088bca_fill_pattern_3_0: 40000 rects
+caravel_00088bca_fill_pattern_1_0: 70000 rects
+caravel_00088bca_fill_pattern_3_6: 60000 rects
+caravel_00088bca_fill_pattern_2_7: 70000 rects
+caravel_00088bca_fill_pattern_5_0: 50000 rects
+caravel_00088bca_fill_pattern_4_7: 60000 rects
+caravel_00088bca_fill_pattern_1_2: 50000 rects
+caravel_00088bca_fill_pattern_5_4: 80000 rects
+caravel_00088bca_fill_pattern_4_1: 60000 rects
+caravel_00088bca_fill_pattern_0_5: 50000 rects
+caravel_00088bca_fill_pattern_0_1: 70000 rects
+caravel_00088bca_fill_pattern_3_2: 60000 rects
+caravel_00088bca_fill_pattern_2_3: 30000 rects
+caravel_00088bca_fill_pattern_5_6: 70000 rects
+caravel_00088bca_fill_pattern_3_0: 50000 rects
+caravel_00088bca_fill_pattern_4_5: 70000 rects
+caravel_00088bca_fill_pattern_1_0: 80000 rects
+caravel_00088bca_fill_pattern_3_6: 70000 rects
+caravel_00088bca_fill_pattern_4_7: 70000 rects
+caravel_00088bca_fill_pattern_2_7: 80000 rects
+caravel_00088bca_fill_pattern_5_0: 60000 rects
+caravel_00088bca_fill_pattern_5_4: 90000 rects
+caravel_00088bca_fill_pattern_1_4: 30000 rects
+caravel_00088bca_fill_pattern_1_2: 60000 rects
+caravel_00088bca_fill_pattern_4_1: 70000 rects
+caravel_00088bca_fill_pattern_0_5: 60000 rects
+caravel_00088bca_fill_pattern_3_2: 70000 rects
+caravel_00088bca_fill_pattern_3_0: 60000 rects
+caravel_00088bca_fill_pattern_4_5: 80000 rects
+caravel_00088bca_fill_pattern_2_3: 40000 rects
+caravel_00088bca_fill_pattern_2_7: 90000 rects
+caravel_00088bca_fill_pattern_3_6: 80000 rects
+caravel_00088bca_fill_pattern_0_1: 80000 rects
+caravel_00088bca_fill_pattern_1_0: 90000 rects
+caravel_00088bca_fill_pattern_4_7: 80000 rects
+caravel_00088bca_fill_pattern_5_6: 80000 rects
+caravel_00088bca_fill_pattern_5_4: 100000 rects
+caravel_00088bca_fill_pattern_1_4: 40000 rects
+caravel_00088bca_fill_pattern_0_5: 70000 rects
+caravel_00088bca_fill_pattern_4_1: 80000 rects
+caravel_00088bca_fill_pattern_3_2: 80000 rects
+caravel_00088bca_fill_pattern_3_0: 70000 rects
+caravel_00088bca_fill_pattern_4_5: 90000 rects
+caravel_00088bca_fill_pattern_2_7: 100000 rects
+caravel_00088bca_fill_pattern_5_0: 70000 rects
+caravel_00088bca_fill_pattern_2_3: 50000 rects
+caravel_00088bca_fill_pattern_1_2: 70000 rects
+caravel_00088bca_fill_pattern_3_6: 90000 rects
+caravel_00088bca_fill_pattern_4_7: 90000 rects
+caravel_00088bca_fill_pattern_1_0: 100000 rects
+caravel_00088bca_fill_pattern_0_1: 90000 rects
+caravel_00088bca_fill_pattern_1_4: 50000 rects
+caravel_00088bca_fill_pattern_5_4: 110000 rects
+caravel_00088bca_fill_pattern_5_6: 90000 rects
+caravel_00088bca_fill_pattern_0_5: 80000 rects
+caravel_00088bca_fill_pattern_3_0: 80000 rects
+caravel_00088bca_fill_pattern_3_2: 90000 rects
+caravel_00088bca_fill_pattern_4_5: 100000 rects
+caravel_00088bca_fill_pattern_2_7: 110000 rects
+caravel_00088bca_fill_pattern_4_1: 90000 rects
+caravel_00088bca_fill_pattern_3_6: 100000 rects
+caravel_00088bca_fill_pattern_2_3: 60000 rects
+caravel_00088bca_fill_pattern_4_7: 100000 rects
+caravel_00088bca_fill_pattern_5_0: 80000 rects
+caravel_00088bca_fill_pattern_1_2: 80000 rects
+caravel_00088bca_fill_pattern_1_0: 110000 rects
+caravel_00088bca_fill_pattern_5_4: 120000 rects
+caravel_00088bca_fill_pattern_0_1: 100000 rects
+caravel_00088bca_fill_pattern_1_4: 60000 rects
+caravel_00088bca_fill_pattern_0_5: 90000 rects
+caravel_00088bca_fill_pattern_5_6: 100000 rects
+caravel_00088bca_fill_pattern_3_2: 100000 rects
+caravel_00088bca_fill_pattern_4_5: 110000 rects
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+CIF output style is now "wafflefill(tiled)"
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+   Generating output for cell caravel_00088bca_fill_pattern_5_0
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+caravel_00088bca_fill_pattern_2_7: 640000 rects
+caravel_00088bca_fill_pattern_4_5: 1030000 rects
+caravel_00088bca_fill_pattern_3_2: 990000 rects
+caravel_00088bca_fill_pattern_4_7: 660000 rects
+caravel_00088bca_fill_pattern_4_1: 950000 rects
+caravel_00088bca_fill_pattern_1_4: 770000 rects
+caravel_00088bca_fill_pattern_3_0: 790000 rects
+caravel_00088bca_fill_pattern_1_2: 780000 rects
+caravel_00088bca_fill_pattern_0_1: 870000 rects
+caravel_00088bca_fill_pattern_3_2: 1000000 rects
+caravel_00088bca_fill_pattern_4_7: 670000 rects
+caravel_00088bca_fill_pattern_3_6: 540000 rects
+caravel_00088bca_fill_pattern_0_5: 1020000 rects
+caravel_00088bca_fill_pattern_4_5: 1040000 rects
+caravel_00088bca_fill_pattern_5_4: 670000 rects
+caravel_00088bca_fill_pattern_4_1: 960000 rects
+caravel_00088bca_fill_pattern_2_3: 790000 rects
+caravel_00088bca_fill_pattern_1_0: 760000 rects
+caravel_00088bca_fill_pattern_3_0: 800000 rects
+caravel_00088bca_fill_pattern_0_1: 880000 rects
+caravel_00088bca_fill_pattern_1_4: 780000 rects
+caravel_00088bca_fill_pattern_3_2: 1010000 rects
+caravel_00088bca_fill_pattern_1_2: 790000 rects
+caravel_00088bca_fill_pattern_2_7: 650000 rects
+caravel_00088bca_fill_pattern_0_5: 1030000 rects
+caravel_00088bca_fill_pattern_4_5: 1050000 rects
+caravel_00088bca_fill_pattern_4_1: 970000 rects
+caravel_00088bca_fill_pattern_1_0: 770000 rects
+caravel_00088bca_fill_pattern_2_3: 800000 rects
+caravel_00088bca_fill_pattern_0_1: 890000 rects
+caravel_00088bca_fill_pattern_3_2: 1020000 rects
+caravel_00088bca_fill_pattern_3_0: 810000 rects
+caravel_00088bca_fill_pattern_5_4: 680000 rects
+caravel_00088bca_fill_pattern_4_7: 680000 rects
+caravel_00088bca_fill_pattern_1_4: 790000 rects
+caravel_00088bca_fill_pattern_1_2: 800000 rects
+caravel_00088bca_fill_pattern_0_5: 1040000 rects
+caravel_00088bca_fill_pattern_4_5: 1060000 rects
+caravel_00088bca_fill_pattern_0_1: 900000 rects
+caravel_00088bca_fill_pattern_3_2: 1030000 rects
+caravel_00088bca_fill_pattern_4_1: 980000 rects
+caravel_00088bca_fill_pattern_3_0: 820000 rects
+caravel_00088bca_fill_pattern_1_0: 780000 rects
+caravel_00088bca_fill_pattern_2_3: 810000 rects
+caravel_00088bca_fill_pattern_1_2: 810000 rects
+caravel_00088bca_fill_pattern_1_4: 800000 rects
+caravel_00088bca_fill_pattern_2_7: 660000 rects
+caravel_00088bca_fill_pattern_0_5: 1050000 rects
+caravel_00088bca_fill_pattern_4_5: 1070000 rects
+caravel_00088bca_fill_pattern_3_0: 830000 rects
+caravel_00088bca_fill_pattern_5_4: 690000 rects
+caravel_00088bca_fill_pattern_3_2: 1040000 rects
+caravel_00088bca_fill_pattern_1_0: 790000 rects
+caravel_00088bca_fill_pattern_4_7: 690000 rects
+caravel_00088bca_fill_pattern_0_1: 910000 rects
+caravel_00088bca_fill_pattern_1_2: 820000 rects
+caravel_00088bca_fill_pattern_4_1: 990000 rects
+caravel_00088bca_fill_pattern_2_3: 820000 rects
+caravel_00088bca_fill_pattern_3_0: 840000 rects
+caravel_00088bca_fill_pattern_0_5: 1060000 rects
+caravel_00088bca_fill_pattern_1_0: 800000 rects
+caravel_00088bca_fill_pattern_1_4: 810000 rects
+caravel_00088bca_fill_pattern_4_5: 1080000 rects
+caravel_00088bca_fill_pattern_3_2: 1050000 rects
+caravel_00088bca_fill_pattern_1_2: 830000 rects
+caravel_00088bca_fill_pattern_0_1: 920000 rects
+caravel_00088bca_fill_pattern_3_0: 850000 rects
+caravel_00088bca_fill_pattern_5_4: 700000 rects
+caravel_00088bca_fill_pattern_1_0: 810000 rects
+caravel_00088bca_fill_pattern_0_5: 1070000 rects
+caravel_00088bca_fill_pattern_2_3: 830000 rects
+caravel_00088bca_fill_pattern_3_2: 1060000 rects
+caravel_00088bca_fill_pattern_2_7: 670000 rects
+caravel_00088bca_fill_pattern_4_7: 700000 rects
+caravel_00088bca_fill_pattern_4_5: 1090000 rects
+caravel_00088bca_fill_pattern_4_1: 1000000 rects
+caravel_00088bca_fill_pattern_1_4: 820000 rects
+caravel_00088bca_fill_pattern_1_2: 840000 rects
+caravel_00088bca_fill_pattern_3_0: 860000 rects
+caravel_00088bca_fill_pattern_1_0: 820000 rects
+caravel_00088bca_fill_pattern_0_1: 930000 rects
+caravel_00088bca_fill_pattern_3_2: 1070000 rects
+caravel_00088bca_fill_pattern_0_5: 1080000 rects
+caravel_00088bca_fill_pattern_1_2: 850000 rects
+caravel_00088bca_fill_pattern_5_4: 710000 rects
+caravel_00088bca_fill_pattern_2_3: 840000 rects
+caravel_00088bca_fill_pattern_4_5: 1100000 rects
+caravel_00088bca_fill_pattern_3_0: 870000 rects
+caravel_00088bca_fill_pattern_1_0: 830000 rects
+caravel_00088bca_fill_pattern_1_4: 830000 rects
+caravel_00088bca_fill_pattern_2_7: 680000 rects
+caravel_00088bca_fill_pattern_4_7: 710000 rects
+caravel_00088bca_fill_pattern_3_2: 1080000 rects
+caravel_00088bca_fill_pattern_0_1: 940000 rects
+caravel_00088bca_fill_pattern_1_2: 860000 rects
+caravel_00088bca_fill_pattern_0_5: 1090000 rects
+caravel_00088bca_fill_pattern_4_1: 1010000 rects
+caravel_00088bca_fill_pattern_1_0: 840000 rects
+caravel_00088bca_fill_pattern_4_5: 1110000 rects
+caravel_00088bca_fill_pattern_3_0: 880000 rects
+caravel_00088bca_fill_pattern_2_3: 850000 rects
+caravel_00088bca_fill_pattern_2_7: 690000 rects
+caravel_00088bca_fill_pattern_4_7: 720000 rects
+caravel_00088bca_fill_pattern_1_4: 840000 rects
+caravel_00088bca_fill_pattern_1_2: 870000 rects
+caravel_00088bca_fill_pattern_3_2: 1090000 rects
+caravel_00088bca_fill_pattern_5_4: 720000 rects
+caravel_00088bca_fill_pattern_0_5: 1100000 rects
+caravel_00088bca_fill_pattern_1_0: 850000 rects
+caravel_00088bca_fill_pattern_4_1: 1020000 rects
+caravel_00088bca_fill_pattern_0_1: 950000 rects
+caravel_00088bca_fill_pattern_4_5: 1120000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00088bca_fill_pattern_3_0: 890000 rects
+caravel_00088bca_fill_pattern_1_2: 880000 rects
+caravel_00088bca_fill_pattern_2_7: 700000 rects
+caravel_00088bca_fill_pattern_3_2: 1100000 rects
+caravel_00088bca_fill_pattern_2_3: 860000 rects
+caravel_00088bca_fill_pattern_1_4: 850000 rects
+   Generating output for cell caravel_00088bca_fill_pattern_5_6
+caravel_00088bca_fill_pattern_1_0: 860000 rects
+caravel_00088bca_fill_pattern_0_5: 1110000 rects
+caravel_00088bca_fill_pattern_4_1: 1030000 rects
+caravel_00088bca_fill_pattern_5_4: 730000 rects
+caravel_00088bca_fill_pattern_1_2: 890000 rects
+caravel_00088bca_fill_pattern_4_7: 730000 rects
+caravel_00088bca_fill_pattern_4_5: 1130000 rects
+caravel_00088bca_fill_pattern_3_0: 900000 rects
+caravel_00088bca_fill_pattern_3_2: 1110000 rects
+caravel_00088bca_fill_pattern_0_1: 960000 rects
+caravel_00088bca_fill_pattern_2_7: 710000 rects
+caravel_00088bca_fill_pattern_2_3: 870000 rects
+caravel_00088bca_fill_pattern_1_4: 860000 rects
+caravel_00088bca_fill_pattern_1_0: 870000 rects
+caravel_00088bca_fill_pattern_1_2: 900000 rects
+caravel_00088bca_fill_pattern_0_5: 1120000 rects
+caravel_00088bca_fill_pattern_3_2: 1120000 rects
+caravel_00088bca_fill_pattern_4_5: 1140000 rects
+caravel_00088bca_fill_pattern_3_0: 910000 rects
+caravel_00088bca_fill_pattern_5_4: 740000 rects
+caravel_00088bca_fill_pattern_2_7: 720000 rects
+caravel_00088bca_fill_pattern_1_4: 870000 rects
+caravel_00088bca_fill_pattern_4_1: 1040000 rects
+caravel_00088bca_fill_pattern_1_2: 910000 rects
+caravel_00088bca_fill_pattern_1_0: 880000 rects
+caravel_00088bca_fill_pattern_2_3: 880000 rects
+caravel_00088bca_fill_pattern_0_1: 970000 rects
+caravel_00088bca_fill_pattern_3_2: 1130000 rects
+caravel_00088bca_fill_pattern_4_5: 1150000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00088bca_fill_pattern_0_5: 1130000 rects
+caravel_00088bca_fill_pattern_3_0: 920000 rects
+caravel_00088bca_fill_pattern_1_2: 920000 rects
+caravel_00088bca_fill_pattern_1_4: 880000 rects
+   Generating output for cell caravel_00088bca_fill_pattern_3_6
+caravel_00088bca_fill_pattern_2_7: 730000 rects
+caravel_00088bca_fill_pattern_4_1: 1050000 rects
+caravel_00088bca_fill_pattern_1_0: 890000 rects
+caravel_00088bca_fill_pattern_3_2: 1140000 rects
+caravel_00088bca_fill_pattern_5_4: 750000 rects
+caravel_00088bca_fill_pattern_0_1: 980000 rects
+caravel_00088bca_fill_pattern_2_3: 890000 rects
+caravel_00088bca_fill_pattern_4_7: 740000 rects
+caravel_00088bca_fill_pattern_4_5: 1160000 rects
+caravel_00088bca_fill_pattern_1_2: 930000 rects
+caravel_00088bca_fill_pattern_3_0: 930000 rects
+caravel_00088bca_fill_pattern_1_4: 890000 rects
+caravel_00088bca_fill_pattern_2_7: 740000 rects
+caravel_00088bca_fill_pattern_4_1: 1060000 rects
+caravel_00088bca_fill_pattern_3_2: 1150000 rects
+caravel_00088bca_fill_pattern_0_5: 1140000 rects
+caravel_00088bca_fill_pattern_1_2: 940000 rects
+caravel_00088bca_fill_pattern_0_1: 990000 rects
+caravel_00088bca_fill_pattern_5_4: 760000 rects
+caravel_00088bca_fill_pattern_4_5: 1170000 rects
+caravel_00088bca_fill_pattern_2_3: 900000 rects
+caravel_00088bca_fill_pattern_1_0: 900000 rects
+caravel_00088bca_fill_pattern_1_4: 900000 rects
+caravel_00088bca_fill_pattern_3_0: 940000 rects
+caravel_00088bca_fill_pattern_3_2: 1160000 rects
+caravel_00088bca_fill_pattern_2_7: 750000 rects
+caravel_00088bca_fill_pattern_4_7: 750000 rects
+caravel_00088bca_fill_pattern_5_4: 770000 rects
+caravel_00088bca_fill_pattern_1_2: 950000 rects
+caravel_00088bca_fill_pattern_0_1: 1000000 rects
+caravel_00088bca_fill_pattern_4_5: 1180000 rects
+caravel_00088bca_fill_pattern_1_4: 910000 rects
+caravel_00088bca_fill_pattern_2_3: 910000 rects
+caravel_00088bca_fill_pattern_4_1: 1070000 rects
+caravel_00088bca_fill_pattern_3_0: 950000 rects
+caravel_00088bca_fill_pattern_0_5: 1150000 rects
+caravel_00088bca_fill_pattern_3_2: 1170000 rects
+caravel_00088bca_fill_pattern_4_7: 760000 rects
+caravel_00088bca_fill_pattern_5_4: 780000 rects
+caravel_00088bca_fill_pattern_1_0: 910000 rects
+caravel_00088bca_fill_pattern_2_7: 760000 rects
+caravel_00088bca_fill_pattern_0_1: 1010000 rects
+caravel_00088bca_fill_pattern_1_4: 920000 rects
+caravel_00088bca_fill_pattern_1_2: 960000 rects
+caravel_00088bca_fill_pattern_4_5: 1190000 rects
+caravel_00088bca_fill_pattern_5_4: 790000 rects
+caravel_00088bca_fill_pattern_3_0: 960000 rects
+caravel_00088bca_fill_pattern_3_2: 1180000 rects
+caravel_00088bca_fill_pattern_2_3: 920000 rects
+caravel_00088bca_fill_pattern_4_7: 770000 rects
+caravel_00088bca_fill_pattern_1_0: 920000 rects
+caravel_00088bca_fill_pattern_2_7: 770000 rects
+caravel_00088bca_fill_pattern_0_5: 1160000 rects
+caravel_00088bca_fill_pattern_4_1: 1080000 rects
+caravel_00088bca_fill_pattern_1_4: 930000 rects
+caravel_00088bca_fill_pattern_0_1: 1020000 rects
+caravel_00088bca_fill_pattern_5_4: 800000 rects
+caravel_00088bca_fill_pattern_4_5: 1200000 rects
+caravel_00088bca_fill_pattern_1_2: 970000 rects
+caravel_00088bca_fill_pattern_3_0: 970000 rects
+caravel_00088bca_fill_pattern_3_2: 1190000 rects
+caravel_00088bca_fill_pattern_1_0: 930000 rects
+caravel_00088bca_fill_pattern_2_3: 930000 rects
+caravel_00088bca_fill_pattern_2_7: 780000 rects
+caravel_00088bca_fill_pattern_0_5: 1170000 rects
+caravel_00088bca_fill_pattern_5_4: 810000 rects
+caravel_00088bca_fill_pattern_1_4: 940000 rects
+caravel_00088bca_fill_pattern_0_1: 1030000 rects
+caravel_00088bca_fill_pattern_4_5: 1210000 rects
+caravel_00088bca_fill_pattern_4_1: 1090000 rects
+caravel_00088bca_fill_pattern_3_0: 980000 rects
+caravel_00088bca_fill_pattern_3_2: 1200000 rects
+caravel_00088bca_fill_pattern_1_2: 980000 rects
+caravel_00088bca_fill_pattern_2_7: 790000 rects
+caravel_00088bca_fill_pattern_5_4: 820000 rects
+caravel_00088bca_fill_pattern_2_3: 940000 rects
+caravel_00088bca_fill_pattern_1_4: 950000 rects
+caravel_00088bca_fill_pattern_0_5: 1180000 rects
+caravel_00088bca_fill_pattern_0_1: 1040000 rects
+caravel_00088bca_fill_pattern_4_5: 1220000 rects
+caravel_00088bca_fill_pattern_1_0: 940000 rects
+caravel_00088bca_fill_pattern_3_0: 990000 rects
+caravel_00088bca_fill_pattern_3_2: 1210000 rects
+caravel_00088bca_fill_pattern_1_2: 990000 rects
+caravel_00088bca_fill_pattern_4_1: 1100000 rects
+caravel_00088bca_fill_pattern_4_7: 780000 rects
+caravel_00088bca_fill_pattern_2_7: 800000 rects
+caravel_00088bca_fill_pattern_2_3: 950000 rects
+caravel_00088bca_fill_pattern_5_4: 830000 rects
+caravel_00088bca_fill_pattern_0_1: 1050000 rects
+caravel_00088bca_fill_pattern_0_5: 1190000 rects
+caravel_00088bca_fill_pattern_4_5: 1230000 rects
+caravel_00088bca_fill_pattern_1_0: 950000 rects
+caravel_00088bca_fill_pattern_3_0: 1000000 rects
+caravel_00088bca_fill_pattern_1_4: 960000 rects
+caravel_00088bca_fill_pattern_3_2: 1220000 rects
+caravel_00088bca_fill_pattern_2_7: 810000 rects
+caravel_00088bca_fill_pattern_1_2: 1000000 rects
+caravel_00088bca_fill_pattern_2_3: 960000 rects
+caravel_00088bca_fill_pattern_4_1: 1110000 rects
+caravel_00088bca_fill_pattern_1_0: 960000 rects
+caravel_00088bca_fill_pattern_1_4: 970000 rects
+caravel_00088bca_fill_pattern_4_5: 1240000 rects
+caravel_00088bca_fill_pattern_0_1: 1060000 rects
+caravel_00088bca_fill_pattern_3_0: 1010000 rects
+caravel_00088bca_fill_pattern_0_5: 1200000 rects
+caravel_00088bca_fill_pattern_3_2: 1230000 rects
+caravel_00088bca_fill_pattern_5_4: 840000 rects
+caravel_00088bca_fill_pattern_2_7: 820000 rects
+caravel_00088bca_fill_pattern_1_2: 1010000 rects
+caravel_00088bca_fill_pattern_2_3: 970000 rects
+caravel_00088bca_fill_pattern_1_4: 980000 rects
+caravel_00088bca_fill_pattern_1_0: 970000 rects
+caravel_00088bca_fill_pattern_4_5: 1250000 rects
+caravel_00088bca_fill_pattern_3_0: 1020000 rects
+caravel_00088bca_fill_pattern_0_1: 1070000 rects
+caravel_00088bca_fill_pattern_4_1: 1120000 rects
+caravel_00088bca_fill_pattern_3_2: 1240000 rects
+caravel_00088bca_fill_pattern_0_5: 1210000 rects
+caravel_00088bca_fill_pattern_2_7: 830000 rects
+caravel_00088bca_fill_pattern_5_4: 850000 rects
+caravel_00088bca_fill_pattern_2_3: 980000 rects
+caravel_00088bca_fill_pattern_1_2: 1020000 rects
+caravel_00088bca_fill_pattern_4_5: 1260000 rects
+caravel_00088bca_fill_pattern_1_0: 980000 rects
+caravel_00088bca_fill_pattern_3_0: 1030000 rects
+caravel_00088bca_fill_pattern_1_4: 990000 rects
+caravel_00088bca_fill_pattern_0_1: 1080000 rects
+caravel_00088bca_fill_pattern_3_2: 1250000 rects
+caravel_00088bca_fill_pattern_4_1: 1130000 rects
+caravel_00088bca_fill_pattern_2_7: 840000 rects
+caravel_00088bca_fill_pattern_2_3: 990000 rects
+caravel_00088bca_fill_pattern_0_5: 1220000 rects
+caravel_00088bca_fill_pattern_1_0: 990000 rects
+caravel_00088bca_fill_pattern_1_2: 1030000 rects
+caravel_00088bca_fill_pattern_3_0: 1040000 rects
+caravel_00088bca_fill_pattern_1_4: 1000000 rects
+caravel_00088bca_fill_pattern_4_5: 1270000 rects
+caravel_00088bca_fill_pattern_0_1: 1090000 rects
+caravel_00088bca_fill_pattern_5_4: 860000 rects
+caravel_00088bca_fill_pattern_3_2: 1260000 rects
+caravel_00088bca_fill_pattern_2_3: 1000000 rects
+caravel_00088bca_fill_pattern_1_0: 1000000 rects
+caravel_00088bca_fill_pattern_0_5: 1230000 rects
+caravel_00088bca_fill_pattern_2_7: 850000 rects
+caravel_00088bca_fill_pattern_1_4: 1010000 rects
+caravel_00088bca_fill_pattern_3_0: 1050000 rects
+caravel_00088bca_fill_pattern_4_1: 1140000 rects
+caravel_00088bca_fill_pattern_1_2: 1040000 rects
+caravel_00088bca_fill_pattern_3_2: 1270000 rects
+caravel_00088bca_fill_pattern_0_1: 1100000 rects
+caravel_00088bca_fill_pattern_2_3: 1010000 rects
+caravel_00088bca_fill_pattern_1_0: 1010000 rects
+caravel_00088bca_fill_pattern_4_5: 1280000 rects
+caravel_00088bca_fill_pattern_1_4: 1020000 rects
+caravel_00088bca_fill_pattern_3_0: 1060000 rects
+caravel_00088bca_fill_pattern_5_4: 870000 rects
+caravel_00088bca_fill_pattern_0_5: 1240000 rects
+caravel_00088bca_fill_pattern_1_2: 1050000 rects
+caravel_00088bca_fill_pattern_3_2: 1280000 rects
+caravel_00088bca_fill_pattern_2_7: 860000 rects
+caravel_00088bca_fill_pattern_4_1: 1150000 rects
+caravel_00088bca_fill_pattern_1_0: 1020000 rects
+caravel_00088bca_fill_pattern_2_3: 1020000 rects
+caravel_00088bca_fill_pattern_1_4: 1030000 rects
+caravel_00088bca_fill_pattern_3_0: 1070000 rects
+caravel_00088bca_fill_pattern_4_5: 1290000 rects
+caravel_00088bca_fill_pattern_5_4: 880000 rects
+caravel_00088bca_fill_pattern_3_2: 1290000 rects
+caravel_00088bca_fill_pattern_0_1: 1110000 rects
+caravel_00088bca_fill_pattern_1_2: 1060000 rects
+caravel_00088bca_fill_pattern_1_0: 1030000 rects
+caravel_00088bca_fill_pattern_2_3: 1030000 rects
+caravel_00088bca_fill_pattern_1_4: 1040000 rects
+caravel_00088bca_fill_pattern_0_5: 1250000 rects
+caravel_00088bca_fill_pattern_4_1: 1160000 rects
+caravel_00088bca_fill_pattern_5_4: 890000 rects
+caravel_00088bca_fill_pattern_3_0: 1080000 rects
+caravel_00088bca_fill_pattern_2_7: 870000 rects
+caravel_00088bca_fill_pattern_4_5: 1300000 rects
+caravel_00088bca_fill_pattern_3_2: 1300000 rects
+caravel_00088bca_fill_pattern_1_0: 1040000 rects
+caravel_00088bca_fill_pattern_1_2: 1070000 rects
+caravel_00088bca_fill_pattern_1_4: 1050000 rects
+caravel_00088bca_fill_pattern_5_4: 900000 rects
+caravel_00088bca_fill_pattern_2_3: 1040000 rects
+caravel_00088bca_fill_pattern_0_1: 1120000 rects
+caravel_00088bca_fill_pattern_3_0: 1090000 rects
+caravel_00088bca_fill_pattern_4_5: 1310000 rects
+caravel_00088bca_fill_pattern_4_1: 1170000 rects
+caravel_00088bca_fill_pattern_0_5: 1260000 rects
+caravel_00088bca_fill_pattern_3_2: 1310000 rects
+caravel_00088bca_fill_pattern_2_7: 880000 rects
+caravel_00088bca_fill_pattern_5_4: 910000 rects
+caravel_00088bca_fill_pattern_1_0: 1050000 rects
+caravel_00088bca_fill_pattern_1_4: 1060000 rects
+caravel_00088bca_fill_pattern_2_3: 1050000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00088bca_fill_pattern_1_2: 1080000 rects
+caravel_00088bca_fill_pattern_0_1: 1130000 rects
+caravel_00088bca_fill_pattern_3_0: 1100000 rects
+   Generating output for cell caravel_00088bca_fill_pattern_4_7
+caravel_00088bca_fill_pattern_3_2: 1320000 rects
+caravel_00088bca_fill_pattern_4_5: 1320000 rects
+caravel_00088bca_fill_pattern_1_0: 1060000 rects
+caravel_00088bca_fill_pattern_1_4: 1070000 rects
+caravel_00088bca_fill_pattern_4_1: 1180000 rects
+caravel_00088bca_fill_pattern_5_4: 920000 rects
+caravel_00088bca_fill_pattern_2_3: 1060000 rects
+caravel_00088bca_fill_pattern_3_0: 1110000 rects
+caravel_00088bca_fill_pattern_2_7: 890000 rects
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+caravel_00088bca_fill_pattern_3_2: 1330000 rects
+caravel_00088bca_fill_pattern_1_2: 1090000 rects
+caravel_00088bca_fill_pattern_0_5: 1270000 rects
+caravel_00088bca_fill_pattern_1_0: 1070000 rects
+caravel_00088bca_fill_pattern_1_4: 1080000 rects
+caravel_00088bca_fill_pattern_2_3: 1070000 rects
+caravel_00088bca_fill_pattern_4_1: 1190000 rects
+caravel_00088bca_fill_pattern_3_0: 1120000 rects
+caravel_00088bca_fill_pattern_4_5: 1330000 rects
+caravel_00088bca_fill_pattern_5_4: 930000 rects
+caravel_00088bca_fill_pattern_3_2: 1340000 rects
+caravel_00088bca_fill_pattern_0_1: 1150000 rects
+caravel_00088bca_fill_pattern_1_0: 1080000 rects
+caravel_00088bca_fill_pattern_1_4: 1090000 rects
+caravel_00088bca_fill_pattern_0_5: 1280000 rects
+caravel_00088bca_fill_pattern_2_3: 1080000 rects
+caravel_00088bca_fill_pattern_2_7: 900000 rects
+caravel_00088bca_fill_pattern_3_0: 1130000 rects
+caravel_00088bca_fill_pattern_3_2: 1350000 rects
+caravel_00088bca_fill_pattern_1_2: 1100000 rects
+caravel_00088bca_fill_pattern_4_1: 1200000 rects
+caravel_00088bca_fill_pattern_5_4: 940000 rects
+caravel_00088bca_fill_pattern_1_0: 1090000 rects
+caravel_00088bca_fill_pattern_1_4: 1100000 rects
+caravel_00088bca_fill_pattern_0_1: 1160000 rects
+caravel_00088bca_fill_pattern_4_5: 1340000 rects
+caravel_00088bca_fill_pattern_2_3: 1090000 rects
+caravel_00088bca_fill_pattern_0_5: 1290000 rects
+caravel_00088bca_fill_pattern_3_0: 1140000 rects
+caravel_00088bca_fill_pattern_3_2: 1360000 rects
+caravel_00088bca_fill_pattern_1_0: 1100000 rects
+caravel_00088bca_fill_pattern_1_4: 1110000 rects
+caravel_00088bca_fill_pattern_2_7: 910000 rects
+caravel_00088bca_fill_pattern_4_5: 1350000 rects
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+caravel_00088bca_fill_pattern_2_3: 1100000 rects
+caravel_00088bca_fill_pattern_5_4: 950000 rects
+caravel_00088bca_fill_pattern_3_0: 1150000 rects
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+caravel_00088bca_fill_pattern_1_2: 1110000 rects
+caravel_00088bca_fill_pattern_0_5: 1300000 rects
+caravel_00088bca_fill_pattern_1_0: 1110000 rects
+caravel_00088bca_fill_pattern_1_4: 1120000 rects
+caravel_00088bca_fill_pattern_2_3: 1110000 rects
+caravel_00088bca_fill_pattern_3_0: 1160000 rects
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+caravel_00088bca_fill_pattern_3_2: 1380000 rects
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+caravel_00088bca_fill_pattern_5_4: 960000 rects
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+caravel_00088bca_fill_pattern_2_3: 1120000 rects
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+caravel_00088bca_fill_pattern_5_4: 970000 rects
+caravel_00088bca_fill_pattern_4_5: 1370000 rects
+caravel_00088bca_fill_pattern_2_7: 930000 rects
+caravel_00088bca_fill_pattern_4_1: 1230000 rects
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+caravel_00088bca_fill_pattern_3_0: 1180000 rects
+caravel_00088bca_fill_pattern_3_2: 1400000 rects
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+caravel_00088bca_fill_pattern_1_4: 1150000 rects
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+caravel_00088bca_fill_pattern_4_5: 1380000 rects
+caravel_00088bca_fill_pattern_2_3: 1140000 rects
+caravel_00088bca_fill_pattern_1_2: 1130000 rects
+caravel_00088bca_fill_pattern_3_2: 1410000 rects
+caravel_00088bca_fill_pattern_4_1: 1240000 rects
+caravel_00088bca_fill_pattern_3_0: 1190000 rects
+caravel_00088bca_fill_pattern_1_4: 1160000 rects
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+caravel_00088bca_fill_pattern_3_0: 1200000 rects
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+caravel_00088bca_fill_pattern_3_0: 1210000 rects
+caravel_00088bca_fill_pattern_1_0: 1170000 rects
+caravel_00088bca_fill_pattern_5_4: 1000000 rects
+caravel_00088bca_fill_pattern_0_1: 1220000 rects
+caravel_00088bca_fill_pattern_0_5: 1340000 rects
+caravel_00088bca_fill_pattern_2_7: 950000 rects
+caravel_00088bca_fill_pattern_1_4: 1180000 rects
+caravel_00088bca_fill_pattern_1_2: 1150000 rects
+caravel_00088bca_fill_pattern_4_1: 1260000 rects
+caravel_00088bca_fill_pattern_2_3: 1170000 rects
+caravel_00088bca_fill_pattern_1_0: 1180000 rects
+caravel_00088bca_fill_pattern_4_5: 1410000 rects
+caravel_00088bca_fill_pattern_3_0: 1220000 rects
+caravel_00088bca_fill_pattern_3_2: 1430000 rects
+caravel_00088bca_fill_pattern_1_4: 1190000 rects
+caravel_00088bca_fill_pattern_0_5: 1350000 rects
+caravel_00088bca_fill_pattern_5_4: 1010000 rects
+caravel_00088bca_fill_pattern_1_2: 1160000 rects
+caravel_00088bca_fill_pattern_2_3: 1180000 rects
+caravel_00088bca_fill_pattern_0_1: 1230000 rects
+caravel_00088bca_fill_pattern_1_0: 1190000 rects
+caravel_00088bca_fill_pattern_3_0: 1230000 rects
+caravel_00088bca_fill_pattern_4_5: 1420000 rects
+caravel_00088bca_fill_pattern_1_4: 1200000 rects
+caravel_00088bca_fill_pattern_4_1: 1270000 rects
+caravel_00088bca_fill_pattern_5_4: 1020000 rects
+caravel_00088bca_fill_pattern_2_7: 960000 rects
+caravel_00088bca_fill_pattern_0_5: 1360000 rects
+caravel_00088bca_fill_pattern_2_3: 1190000 rects
+caravel_00088bca_fill_pattern_1_0: 1200000 rects
+caravel_00088bca_fill_pattern_1_2: 1170000 rects
+caravel_00088bca_fill_pattern_5_4: 1030000 rects
+caravel_00088bca_fill_pattern_3_0: 1240000 rects
+caravel_00088bca_fill_pattern_0_1: 1240000 rects
+caravel_00088bca_fill_pattern_4_5: 1430000 rects
+caravel_00088bca_fill_pattern_3_2: 1440000 rects
+caravel_00088bca_fill_pattern_1_4: 1210000 rects
+caravel_00088bca_fill_pattern_4_1: 1280000 rects
+caravel_00088bca_fill_pattern_1_0: 1210000 rects
+caravel_00088bca_fill_pattern_2_3: 1200000 rects
+caravel_00088bca_fill_pattern_2_7: 970000 rects
+caravel_00088bca_fill_pattern_0_5: 1370000 rects
+caravel_00088bca_fill_pattern_3_0: 1250000 rects
+caravel_00088bca_fill_pattern_4_5: 1440000 rects
+caravel_00088bca_fill_pattern_1_2: 1180000 rects
+caravel_00088bca_fill_pattern_0_1: 1250000 rects
+caravel_00088bca_fill_pattern_1_4: 1220000 rects
+caravel_00088bca_fill_pattern_3_2: 1450000 rects
+caravel_00088bca_fill_pattern_1_0: 1220000 rects
+caravel_00088bca_fill_pattern_2_3: 1210000 rects
+caravel_00088bca_fill_pattern_4_1: 1290000 rects
+caravel_00088bca_fill_pattern_0_5: 1380000 rects
+caravel_00088bca_fill_pattern_3_0: 1260000 rects
+caravel_00088bca_fill_pattern_2_7: 980000 rects
+caravel_00088bca_fill_pattern_4_5: 1450000 rects
+caravel_00088bca_fill_pattern_1_4: 1230000 rects
+caravel_00088bca_fill_pattern_1_2: 1190000 rects
+caravel_00088bca_fill_pattern_0_1: 1260000 rects
+caravel_00088bca_fill_pattern_1_0: 1230000 rects
+caravel_00088bca_fill_pattern_2_3: 1220000 rects
+caravel_00088bca_fill_pattern_3_2: 1460000 rects
+caravel_00088bca_fill_pattern_3_0: 1270000 rects
+caravel_00088bca_fill_pattern_0_5: 1390000 rects
+caravel_00088bca_fill_pattern_4_1: 1300000 rects
+caravel_00088bca_fill_pattern_1_4: 1240000 rects
+caravel_00088bca_fill_pattern_4_5: 1460000 rects
+caravel_00088bca_fill_pattern_1_0: 1240000 rects
+caravel_00088bca_fill_pattern_2_7: 990000 rects
+caravel_00088bca_fill_pattern_2_3: 1230000 rects
+caravel_00088bca_fill_pattern_0_1: 1270000 rects
+caravel_00088bca_fill_pattern_3_0: 1280000 rects
+caravel_00088bca_fill_pattern_1_2: 1200000 rects
+caravel_00088bca_fill_pattern_1_4: 1250000 rects
+caravel_00088bca_fill_pattern_3_2: 1470000 rects
+caravel_00088bca_fill_pattern_0_5: 1400000 rects
+caravel_00088bca_fill_pattern_4_5: 1470000 rects
+caravel_00088bca_fill_pattern_4_1: 1310000 rects
+caravel_00088bca_fill_pattern_1_0: 1250000 rects
+caravel_00088bca_fill_pattern_2_3: 1240000 rects
+caravel_00088bca_fill_pattern_3_0: 1290000 rects
+caravel_00088bca_fill_pattern_2_7: 1000000 rects
+caravel_00088bca_fill_pattern_1_4: 1260000 rects
+caravel_00088bca_fill_pattern_0_1: 1280000 rects
+caravel_00088bca_fill_pattern_4_5: 1480000 rects
+caravel_00088bca_fill_pattern_1_0: 1260000 rects
+caravel_00088bca_fill_pattern_0_5: 1410000 rects
+caravel_00088bca_fill_pattern_3_2: 1480000 rects
+caravel_00088bca_fill_pattern_4_1: 1320000 rects
+caravel_00088bca_fill_pattern_2_3: 1250000 rects
+caravel_00088bca_fill_pattern_1_2: 1210000 rects
+caravel_00088bca_fill_pattern_3_0: 1300000 rects
+caravel_00088bca_fill_pattern_1_4: 1270000 rects
+caravel_00088bca_fill_pattern_4_5: 1490000 rects
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+caravel_00088bca_fill_pattern_2_7: 1010000 rects
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+caravel_00088bca_fill_pattern_0_5: 1430000 rects
+caravel_00088bca_fill_pattern_0_1: 1300000 rects
+caravel_00088bca_fill_pattern_3_0: 1320000 rects
+caravel_00088bca_fill_pattern_1_4: 1290000 rects
+caravel_00088bca_fill_pattern_3_2: 1500000 rects
+caravel_00088bca_fill_pattern_2_7: 1020000 rects
+caravel_00088bca_fill_pattern_1_0: 1290000 rects
+caravel_00088bca_fill_pattern_4_1: 1340000 rects
+caravel_00088bca_fill_pattern_4_5: 1510000 rects
+caravel_00088bca_fill_pattern_2_3: 1280000 rects
+caravel_00088bca_fill_pattern_0_1: 1310000 rects
+caravel_00088bca_fill_pattern_3_0: 1330000 rects
+caravel_00088bca_fill_pattern_0_5: 1440000 rects
+caravel_00088bca_fill_pattern_1_4: 1300000 rects
+caravel_00088bca_fill_pattern_3_2: 1510000 rects
+caravel_00088bca_fill_pattern_1_0: 1300000 rects
+caravel_00088bca_fill_pattern_1_2: 1230000 rects
+caravel_00088bca_fill_pattern_4_5: 1520000 rects
+caravel_00088bca_fill_pattern_2_7: 1030000 rects
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+caravel_00088bca_fill_pattern_4_1: 1350000 rects
+caravel_00088bca_fill_pattern_2_3: 1290000 rects
+caravel_00088bca_fill_pattern_1_4: 1310000 rects
+caravel_00088bca_fill_pattern_3_0: 1340000 rects
+caravel_00088bca_fill_pattern_3_2: 1520000 rects
+caravel_00088bca_fill_pattern_0_5: 1450000 rects
+caravel_00088bca_fill_pattern_1_0: 1310000 rects
+caravel_00088bca_fill_pattern_2_7: 1040000 rects
+caravel_00088bca_fill_pattern_4_5: 1530000 rects
+caravel_00088bca_fill_pattern_1_2: 1240000 rects
+caravel_00088bca_fill_pattern_0_1: 1330000 rects
+caravel_00088bca_fill_pattern_1_4: 1320000 rects
+caravel_00088bca_fill_pattern_2_3: 1300000 rects
+caravel_00088bca_fill_pattern_3_0: 1350000 rects
+caravel_00088bca_fill_pattern_4_1: 1360000 rects
+caravel_00088bca_fill_pattern_1_0: 1320000 rects
+caravel_00088bca_fill_pattern_3_2: 1530000 rects
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+caravel_00088bca_fill_pattern_0_5: 1460000 rects
+caravel_00088bca_fill_pattern_1_4: 1330000 rects
+caravel_00088bca_fill_pattern_4_5: 1540000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00088bca_fill_pattern_2_3: 1310000 rects
+caravel_00088bca_fill_pattern_0_1: 1340000 rects
+caravel_00088bca_fill_pattern_3_0: 1360000 rects
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+caravel_00088bca_fill_pattern_2_7: 1060000 rects
+caravel_00088bca_fill_pattern_1_0: 1330000 rects
+   Generating output for cell caravel_00088bca_fill_pattern_5_4
+caravel_00088bca_fill_pattern_3_2: 1540000 rects
+caravel_00088bca_fill_pattern_4_1: 1370000 rects
+caravel_00088bca_fill_pattern_0_5: 1470000 rects
+caravel_00088bca_fill_pattern_2_3: 1320000 rects
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+caravel_00088bca_fill_pattern_2_7: 1070000 rects
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+caravel_00088bca_fill_pattern_1_4: 1340000 rects
+caravel_00088bca_fill_pattern_1_0: 1340000 rects
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+caravel_00088bca_fill_pattern_1_2: 1260000 rects
+caravel_00088bca_fill_pattern_4_1: 1380000 rects
+caravel_00088bca_fill_pattern_2_3: 1330000 rects
+caravel_00088bca_fill_pattern_0_5: 1480000 rects
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+caravel_00088bca_fill_pattern_3_0: 1380000 rects
+caravel_00088bca_fill_pattern_1_4: 1350000 rects
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+caravel_00088bca_fill_pattern_1_0: 1350000 rects
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+caravel_00088bca_fill_pattern_2_7: 1090000 rects
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+caravel_00088bca_fill_pattern_1_4: 1360000 rects
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+caravel_00088bca_fill_pattern_3_0: 1390000 rects
+caravel_00088bca_fill_pattern_1_0: 1360000 rects
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+caravel_00088bca_fill_pattern_1_2: 1270000 rects
+caravel_00088bca_fill_pattern_4_5: 1570000 rects
+caravel_00088bca_fill_pattern_3_2: 1570000 rects
+caravel_00088bca_fill_pattern_2_7: 1100000 rects
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+caravel_00088bca_fill_pattern_2_3: 1350000 rects
+caravel_00088bca_fill_pattern_1_4: 1370000 rects
+caravel_00088bca_fill_pattern_1_0: 1370000 rects
+caravel_00088bca_fill_pattern_3_0: 1400000 rects
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+caravel_00088bca_fill_pattern_1_2: 1290000 rects
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+caravel_00088bca_fill_pattern_4_1: 1410000 rects
+caravel_00088bca_fill_pattern_3_2: 1590000 rects
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+caravel_00088bca_fill_pattern_2_3: 1370000 rects
+caravel_00088bca_fill_pattern_1_4: 1390000 rects
+caravel_00088bca_fill_pattern_1_0: 1390000 rects
+caravel_00088bca_fill_pattern_3_0: 1420000 rects
+caravel_00088bca_fill_pattern_0_1: 1380000 rects
+caravel_00088bca_fill_pattern_1_2: 1300000 rects
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+caravel_00088bca_fill_pattern_1_4: 1400000 rects
+caravel_00088bca_fill_pattern_2_3: 1380000 rects
+caravel_00088bca_fill_pattern_4_5: 1600000 rects
+caravel_00088bca_fill_pattern_1_0: 1400000 rects
+caravel_00088bca_fill_pattern_4_1: 1420000 rects
+caravel_00088bca_fill_pattern_3_2: 1600000 rects
+caravel_00088bca_fill_pattern_3_0: 1430000 rects
+caravel_00088bca_fill_pattern_2_7: 1130000 rects
+caravel_00088bca_fill_pattern_0_1: 1390000 rects
+caravel_00088bca_fill_pattern_2_3: 1390000 rects
+caravel_00088bca_fill_pattern_1_2: 1310000 rects
+caravel_00088bca_fill_pattern_0_5: 1530000 rects
+caravel_00088bca_fill_pattern_1_0: 1410000 rects
+caravel_00088bca_fill_pattern_1_4: 1410000 rects
+caravel_00088bca_fill_pattern_4_5: 1610000 rects
+caravel_00088bca_fill_pattern_3_0: 1440000 rects
+caravel_00088bca_fill_pattern_4_1: 1430000 rects
+caravel_00088bca_fill_pattern_3_2: 1610000 rects
+caravel_00088bca_fill_pattern_2_3: 1400000 rects
+caravel_00088bca_fill_pattern_0_1: 1400000 rects
+caravel_00088bca_fill_pattern_1_2: 1320000 rects
+caravel_00088bca_fill_pattern_1_0: 1420000 rects
+caravel_00088bca_fill_pattern_2_7: 1140000 rects
+caravel_00088bca_fill_pattern_0_5: 1540000 rects
+caravel_00088bca_fill_pattern_1_4: 1420000 rects
+caravel_00088bca_fill_pattern_3_0: 1450000 rects
+caravel_00088bca_fill_pattern_4_5: 1620000 rects
+caravel_00088bca_fill_pattern_4_1: 1440000 rects
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+Ended: 12/04/2022 06:04:31
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+caravel_00088bca_fill_pattern_4_5: 1980000 rects
+caravel_00088bca_fill_pattern_1_2: 1690000 rects
+caravel_00088bca_fill_pattern_1_4: 1780000 rects
+caravel_00088bca_fill_pattern_3_2: 1950000 rects
+caravel_00088bca_fill_pattern_3_0: 1820000 rects
+caravel_00088bca_fill_pattern_0_1: 1680000 rects
+caravel_00088bca_fill_pattern_0_5: 1900000 rects
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_00088bca_fill_pattern_1_0: 1770000 rects
+caravel_00088bca_fill_pattern_4_5: 1990000 rects
+caravel_00088bca_fill_pattern_2_3: 1820000 rects
+caravel_00088bca_fill_pattern_1_2: 1700000 rects
+caravel_00088bca_fill_pattern_1_4: 1790000 rects
+caravel_00088bca_fill_pattern_3_2: 1960000 rects
+caravel_00088bca_fill_pattern_4_1: 1640000 rects
+caravel_00088bca_fill_pattern_3_0: 1830000 rects
+caravel_00088bca_fill_pattern_4_5: 2000000 rects
+Processing system .magicrc file
+caravel_00088bca_fill_pattern_2_3: 1830000 rects
+caravel_00088bca_fill_pattern_1_0: 1780000 rects
+caravel_00088bca_fill_pattern_1_2: 1710000 rects
+caravel_00088bca_fill_pattern_0_1: 1690000 rects
+caravel_00088bca_fill_pattern_2_7: 1390000 rects
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_00088bca_fill_pattern_1_4: 1800000 rects
+caravel_00088bca_fill_pattern_3_2: 1970000 rects
+caravel_00088bca_fill_pattern_0_5: 1910000 rects
+caravel_00088bca_fill_pattern_2_3: 1840000 rects
+caravel_00088bca_fill_pattern_4_5: 2010000 rects
+caravel_00088bca_fill_pattern_3_0: 1840000 rects
+caravel_00088bca_fill_pattern_1_2: 1720000 rects
+caravel_00088bca_fill_pattern_1_0: 1790000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_00088bca_fill_pattern_0_1: 1700000 rects
+caravel_00088bca_fill_pattern_1_4: 1810000 rects
+caravel_00088bca_fill_pattern_4_5: 2020000 rects
+caravel_00088bca_fill_pattern_2_3: 1850000 rects
+caravel_00088bca_fill_pattern_2_7: 1400000 rects
+caravel_00088bca_fill_pattern_3_2: 1980000 rects
+caravel_00088bca_fill_pattern_3_0: 1850000 rects
+caravel_00088bca_fill_pattern_1_2: 1730000 rects
+caravel_00088bca_fill_pattern_4_1: 1650000 rects
+caravel_00088bca_fill_pattern_0_5: 1920000 rects
+caravel_00088bca_fill_pattern_1_0: 1800000 rects
+caravel_00088bca_fill_pattern_2_7: 1410000 rects
+caravel_00088bca_fill_pattern_4_5: 2030000 rects
+caravel_00088bca_fill_pattern_2_3: 1860000 rects
+caravel_00088bca_fill_pattern_1_4: 1820000 rects
+caravel_00088bca_fill_pattern_1_2: 1740000 rects
+caravel_00088bca_fill_pattern_3_2: 1990000 rects
+caravel_00088bca_fill_pattern_3_0: 1860000 rects
+caravel_00088bca_fill_pattern_0_1: 1710000 rects
+caravel_00088bca_fill_pattern_2_7: 1420000 rects
+caravel_00088bca_fill_pattern_2_3: 1870000 rects
+caravel_00088bca_fill_pattern_4_5: 2040000 rects
+caravel_00088bca_fill_pattern_1_4: 1830000 rects
+caravel_00088bca_fill_pattern_1_0: 1810000 rects
+caravel_00088bca_fill_pattern_1_2: 1750000 rects
+caravel_00088bca_fill_pattern_2_7: 1430000 rects
+caravel_00088bca_fill_pattern_3_0: 1870000 rects
+caravel_00088bca_fill_pattern_3_2: 2000000 rects
+caravel_00088bca_fill_pattern_2_3: 1880000 rects
+caravel_00088bca_fill_pattern_4_5: 2050000 rects
+caravel_00088bca_fill_pattern_0_1: 1720000 rects
+caravel_00088bca_fill_pattern_1_4: 1840000 rects
+caravel_00088bca_fill_pattern_0_5: 1930000 rects
+caravel_00088bca_fill_pattern_1_0: 1820000 rects
+caravel_00088bca_fill_pattern_1_2: 1760000 rects
+caravel_00088bca_fill_pattern_4_1: 1660000 rects
+caravel_00088bca_fill_pattern_2_7: 1440000 rects
+caravel_00088bca_fill_pattern_4_5: 2060000 rects
+caravel_00088bca_fill_pattern_3_0: 1880000 rects
+caravel_00088bca_fill_pattern_3_2: 2010000 rects
+caravel_00088bca_fill_pattern_2_3: 1890000 rects
+caravel_00088bca_fill_pattern_1_4: 1850000 rects
+caravel_00088bca_fill_pattern_1_2: 1770000 rects
+caravel_00088bca_fill_pattern_0_1: 1730000 rects
+caravel_00088bca_fill_pattern_1_0: 1830000 rects
+caravel_00088bca_fill_pattern_4_5: 2070000 rects
+caravel_00088bca_fill_pattern_3_0: 1890000 rects
+caravel_00088bca_fill_pattern_1_4: 1860000 rects
+caravel_00088bca_fill_pattern_3_2: 2020000 rects
+caravel_00088bca_fill_pattern_2_3: 1900000 rects
+caravel_00088bca_fill_pattern_1_2: 1780000 rects
+caravel_00088bca_fill_pattern_0_5: 1940000 rects
+caravel_00088bca_fill_pattern_4_5: 2080000 rects
+caravel_00088bca_fill_pattern_1_0: 1840000 rects
+caravel_00088bca_fill_pattern_0_1: 1740000 rects
+caravel_00088bca_fill_pattern_3_0: 1900000 rects
+caravel_00088bca_fill_pattern_4_1: 1670000 rects
+caravel_00088bca_fill_pattern_3_2: 2030000 rects
+caravel_00088bca_fill_pattern_1_2: 1790000 rects
+caravel_00088bca_fill_pattern_1_4: 1870000 rects
+caravel_00088bca_fill_pattern_2_3: 1910000 rects
+caravel_00088bca_fill_pattern_1_0: 1850000 rects
+caravel_00088bca_fill_pattern_3_0: 1910000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+caravel_00088bca_fill_pattern_1_2: 1800000 rects
+caravel_00088bca_fill_pattern_1_4: 1880000 rects
+caravel_00088bca_fill_pattern_0_1: 1750000 rects
+caravel_00088bca_fill_pattern_3_2: 2040000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+caravel_00088bca_fill_pattern_2_3: 1920000 rects
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_00088bca_fill_pattern_3_0: 1920000 rects
+caravel_00088bca_fill_pattern_1_0: 1860000 rects
+caravel_00088bca_fill_pattern_4_5: 2090000 rects
+caravel_00088bca_fill_pattern_4_1: 1680000 rects
+caravel_00088bca_fill_pattern_1_2: 1810000 rects
+caravel_00088bca_fill_pattern_1_4: 1890000 rects
+caravel_00088bca_fill_pattern_0_5: 1950000 rects
+caravel_00088bca_fill_pattern_3_2: 2050000 rects
+caravel_00088bca_fill_pattern_2_3: 1930000 rects
+caravel_00088bca_fill_pattern_0_1: 1760000 rects
+caravel_00088bca_fill_pattern_3_0: 1930000 rects
+caravel_00088bca_fill_pattern_0_3: 10000 rects
+caravel_00088bca_fill_pattern_1_2: 1820000 rects
+caravel_00088bca_fill_pattern_1_0: 1870000 rects
+caravel_00088bca_fill_pattern_1_4: 1900000 rects
+caravel_00088bca_fill_pattern_0_1: 1770000 rects
+caravel_00088bca_fill_pattern_2_3: 1940000 rects
+caravel_00088bca_fill_pattern_3_2: 2060000 rects
+caravel_00088bca_fill_pattern_0_3: 20000 rects
+caravel_00088bca_fill_pattern_1_2: 1830000 rects
+caravel_00088bca_fill_pattern_3_0: 1940000 rects
+caravel_00088bca_fill_pattern_0_3: 30000 rects
+caravel_00088bca_fill_pattern_0_1: 1780000 rects
+caravel_00088bca_fill_pattern_4_1: 1690000 rects
+caravel_00088bca_fill_pattern_4_5: 2100000 rects
+caravel_00088bca_fill_pattern_3_2: 2070000 rects
+caravel_00088bca_fill_pattern_2_3: 1950000 rects
+caravel_00088bca_fill_pattern_1_4: 1910000 rects
+caravel_00088bca_fill_pattern_0_5: 1960000 rects
+caravel_00088bca_fill_pattern_0_3: 40000 rects
+caravel_00088bca_fill_pattern_1_2: 1840000 rects
+caravel_00088bca_fill_pattern_3_0: 1950000 rects
+caravel_00088bca_fill_pattern_1_0: 1880000 rects
+caravel_00088bca_fill_pattern_0_1: 1790000 rects
+caravel_00088bca_fill_pattern_0_3: 50000 rects
+caravel_00088bca_fill_pattern_1_2: 1850000 rects
+caravel_00088bca_fill_pattern_3_2: 2080000 rects
+caravel_00088bca_fill_pattern_2_3: 1960000 rects
+caravel_00088bca_fill_pattern_0_1: 1800000 rects
+caravel_00088bca_fill_pattern_1_4: 1920000 rects
+caravel_00088bca_fill_pattern_3_0: 1960000 rects
+caravel_00088bca_fill_pattern_0_3: 60000 rects
+caravel_00088bca_fill_pattern_0_1: 1810000 rects
+caravel_00088bca_fill_pattern_1_2: 1860000 rects
+caravel_00088bca_fill_pattern_0_3: 70000 rects
+caravel_00088bca_fill_pattern_3_2: 2090000 rects
+caravel_00088bca_fill_pattern_1_4: 1930000 rects
+caravel_00088bca_fill_pattern_1_0: 1890000 rects
+caravel_00088bca_fill_pattern_4_1: 1700000 rects
+caravel_00088bca_fill_pattern_2_3: 1970000 rects
+caravel_00088bca_fill_pattern_3_0: 1970000 rects
+caravel_00088bca_fill_pattern_0_5: 1970000 rects
+caravel_00088bca_fill_pattern_4_5: 2110000 rects
+caravel_00088bca_fill_pattern_0_1: 1820000 rects
+caravel_00088bca_fill_pattern_0_3: 80000 rects
+caravel_00088bca_fill_pattern_3_2: 2100000 rects
+caravel_00088bca_fill_pattern_1_2: 1870000 rects
+caravel_00088bca_fill_pattern_1_4: 1940000 rects
+caravel_00088bca_fill_pattern_1_0: 1900000 rects
+caravel_00088bca_fill_pattern_3_0: 1980000 rects
+caravel_00088bca_fill_pattern_0_3: 90000 rects
+caravel_00088bca_fill_pattern_2_3: 1980000 rects
+caravel_00088bca_fill_pattern_3_2: 2110000 rects
+caravel_00088bca_fill_pattern_0_1: 1830000 rects
+caravel_00088bca_fill_pattern_1_2: 1880000 rects
+caravel_00088bca_fill_pattern_1_4: 1950000 rects
+caravel_00088bca_fill_pattern_0_3: 100000 rects
+caravel_00088bca_fill_pattern_3_0: 1990000 rects
+caravel_00088bca_fill_pattern_1_0: 1910000 rects
+caravel_00088bca_fill_pattern_3_2: 2120000 rects
+caravel_00088bca_fill_pattern_0_1: 1840000 rects
+caravel_00088bca_fill_pattern_2_3: 1990000 rects
+caravel_00088bca_fill_pattern_0_3: 110000 rects
+caravel_00088bca_fill_pattern_1_2: 1890000 rects
+caravel_00088bca_fill_pattern_1_4: 1960000 rects
+caravel_00088bca_fill_pattern_0_5: 1980000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00088bca_fill_pattern_4_5: 2120000 rects
+caravel_00088bca_fill_pattern_4_1: 1710000 rects
+caravel_00088bca_fill_pattern_3_0: 2000000 rects
+caravel_00088bca_fill_pattern_3_2: 2130000 rects
+caravel_00088bca_fill_pattern_0_1: 1850000 rects
+caravel_00088bca_fill_pattern_0_3: 120000 rects
+   Generating output for cell caravel_00088bca_fill_pattern_2_7
+caravel_00088bca_fill_pattern_1_0: 1920000 rects
+caravel_00088bca_fill_pattern_2_3: 2000000 rects
+caravel_00088bca_fill_pattern_1_2: 1900000 rects
+caravel_00088bca_fill_pattern_3_2: 2140000 rects
+caravel_00088bca_fill_pattern_0_3: 130000 rects
+caravel_00088bca_fill_pattern_1_4: 1970000 rects
+caravel_00088bca_fill_pattern_0_1: 1860000 rects
+caravel_00088bca_fill_pattern_3_0: 2010000 rects
+caravel_00088bca_fill_pattern_1_2: 1910000 rects
+caravel_00088bca_fill_pattern_3_2: 2150000 rects
+caravel_00088bca_fill_pattern_0_3: 140000 rects
+caravel_00088bca_fill_pattern_2_3: 2010000 rects
+caravel_00088bca_fill_pattern_1_4: 1980000 rects
+caravel_00088bca_fill_pattern_0_1: 1870000 rects
+caravel_00088bca_fill_pattern_4_1: 1720000 rects
+caravel_00088bca_fill_pattern_0_3: 150000 rects
+caravel_00088bca_fill_pattern_3_2: 2160000 rects
+caravel_00088bca_fill_pattern_1_2: 1920000 rects
+caravel_00088bca_fill_pattern_1_0: 1930000 rects
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+caravel_00088bca_fill_pattern_4_5: 2130000 rects
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+caravel_00088bca_fill_pattern_2_3: 2020000 rects
+caravel_00088bca_fill_pattern_1_4: 1990000 rects
+caravel_00088bca_fill_pattern_0_3: 160000 rects
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+caravel_00088bca_fill_pattern_3_2: 2170000 rects
+caravel_00088bca_fill_pattern_1_2: 1930000 rects
+caravel_00088bca_fill_pattern_1_0: 1940000 rects
+caravel_00088bca_fill_pattern_1_4: 2000000 rects
+caravel_00088bca_fill_pattern_0_3: 170000 rects
+caravel_00088bca_fill_pattern_2_3: 2030000 rects
+caravel_00088bca_fill_pattern_3_2: 2180000 rects
+caravel_00088bca_fill_pattern_3_0: 2030000 rects
+caravel_00088bca_fill_pattern_1_2: 1940000 rects
+caravel_00088bca_fill_pattern_0_1: 1890000 rects
+caravel_00088bca_fill_pattern_1_0: 1950000 rects
+caravel_00088bca_fill_pattern_0_3: 180000 rects
+caravel_00088bca_fill_pattern_1_4: 2010000 rects
+caravel_00088bca_fill_pattern_4_1: 1730000 rects
+caravel_00088bca_fill_pattern_3_2: 2190000 rects
+caravel_00088bca_fill_pattern_0_5: 2000000 rects
+caravel_00088bca_fill_pattern_2_3: 2040000 rects
+caravel_00088bca_fill_pattern_1_2: 1950000 rects
+caravel_00088bca_fill_pattern_4_5: 2140000 rects
+caravel_00088bca_fill_pattern_0_3: 190000 rects
+caravel_00088bca_fill_pattern_3_0: 2040000 rects
+caravel_00088bca_fill_pattern_1_4: 2020000 rects
+caravel_00088bca_fill_pattern_3_2: 2200000 rects
+caravel_00088bca_fill_pattern_0_3: 200000 rects
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+caravel_00088bca_fill_pattern_0_1: 1900000 rects
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+caravel_00088bca_fill_pattern_1_0: 1960000 rects
+caravel_00088bca_fill_pattern_3_0: 2050000 rects
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+caravel_00088bca_fill_pattern_0_3: 210000 rects
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+caravel_00088bca_fill_pattern_3_0: 2070000 rects
+caravel_00088bca_fill_pattern_0_3: 240000 rects
+caravel_00088bca_fill_pattern_1_0: 1980000 rects
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+caravel_00088bca_fill_pattern_3_0: 2080000 rects
+caravel_00088bca_fill_pattern_1_4: 2050000 rects
+caravel_00088bca_fill_pattern_3_2: 2230000 rects
+caravel_00088bca_fill_pattern_0_1: 1920000 rects
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+caravel_00088bca_fill_pattern_3_0: 2090000 rects
+caravel_00088bca_fill_pattern_0_5: 2020000 rects
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+caravel_00088bca_fill_pattern_4_5: 2160000 rects
+caravel_00088bca_fill_pattern_0_3: 260000 rects
+caravel_00088bca_fill_pattern_1_0: 2000000 rects
+caravel_00088bca_fill_pattern_1_2: 2010000 rects
+caravel_00088bca_fill_pattern_1_4: 2060000 rects
+caravel_00088bca_fill_pattern_0_3: 270000 rects
+caravel_00088bca_fill_pattern_2_3: 2100000 rects
+caravel_00088bca_fill_pattern_0_1: 1930000 rects
+caravel_00088bca_fill_pattern_3_0: 2100000 rects
+caravel_00088bca_fill_pattern_0_3: 280000 rects
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+caravel_00088bca_fill_pattern_1_0: 2010000 rects
+caravel_00088bca_fill_pattern_1_2: 2020000 rects
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+caravel_00088bca_fill_pattern_1_4: 2070000 rects
+caravel_00088bca_fill_pattern_0_5: 2030000 rects
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+caravel_00088bca_fill_pattern_3_0: 2110000 rects
+caravel_00088bca_fill_pattern_4_5: 2170000 rects
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+caravel_00088bca_fill_pattern_4_1: 1990000 rects
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+Ended: 12/04/2022 06:04:35
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+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
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+Processing system .magicrc file
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+caravel_00088bca_fill_pattern_1_0: 2430000 rects
+caravel_00088bca_fill_pattern_1_4: 2560000 rects
+caravel_00088bca_fill_pattern_3_2: 2500000 rects
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
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+Input style sky130(vendor): scaleFactor=2, multiplier=2
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+caravel_00088bca_fill_pattern_4_1: 2030000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
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+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
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+caravel_00088bca_fill_pattern_2_1: 920000 rects
+Ended: 12/04/2022 06:04:39
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+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
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+Processing system .magicrc file
+caravel_00088bca_fill_pattern_1_2: 3410000 rects
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
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+Input style sky130(vendor): scaleFactor=2, multiplier=2
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+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
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+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
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+   Generating output for cell caravel_00088bca_fill_pattern_0_3
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+CIF output style is now "wafflefill(tiled)"
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+   Generating output for cell caravel_00088bca_fill_pattern_4_1
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+CIF output style is now "wafflefill(tiled)"
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+   Generating output for cell caravel_00088bca_fill_pattern_0_5
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+caravel_00088bca_fill_pattern_4_5: 4670000 rects
+caravel_00088bca_fill_pattern_4_5: 4680000 rects
+caravel_00088bca_fill_pattern_4_5: 4690000 rects
+caravel_00088bca_fill_pattern_3_0: 4320000 rects
+caravel_00088bca_fill_pattern_3_4: 3330000 rects
+caravel_00088bca_fill_pattern_0_1: 4530000 rects
+caravel_00088bca_fill_pattern_4_5: 4700000 rects
+caravel_00088bca_fill_pattern_3_2: 4620000 rects
+caravel_00088bca_fill_pattern_4_5: 4710000 rects
+caravel_00088bca_fill_pattern_1_4: 4290000 rects
+caravel_00088bca_fill_pattern_1_0: 4370000 rects
+caravel_00088bca_fill_pattern_2_3: 4460000 rects
+caravel_00088bca_fill_pattern_2_1: 2990000 rects
+caravel_00088bca_fill_pattern_4_5: 4720000 rects
+caravel_00088bca_fill_pattern_1_2: 4380000 rects
+caravel_00088bca_fill_pattern_0_1: 4540000 rects
+caravel_00088bca_fill_pattern_3_4: 3340000 rects
+caravel_00088bca_fill_pattern_4_5: 4730000 rects
+caravel_00088bca_fill_pattern_0_1: 4550000 rects
+caravel_00088bca_fill_pattern_4_5: 4740000 rects
+caravel_00088bca_fill_pattern_0_1: 4560000 rects
+caravel_00088bca_fill_pattern_3_0: 4330000 rects
+caravel_00088bca_fill_pattern_3_2: 4630000 rects
+caravel_00088bca_fill_pattern_0_1: 4570000 rects
+caravel_00088bca_fill_pattern_4_5: 4750000 rects
+caravel_00088bca_fill_pattern_3_4: 3350000 rects
+caravel_00088bca_fill_pattern_1_0: 4380000 rects
+caravel_00088bca_fill_pattern_0_1: 4580000 rects
+caravel_00088bca_fill_pattern_2_1: 3000000 rects
+caravel_00088bca_fill_pattern_1_4: 4300000 rects
+caravel_00088bca_fill_pattern_0_1: 4590000 rects
+caravel_00088bca_fill_pattern_2_3: 4470000 rects
+caravel_00088bca_fill_pattern_4_5: 4760000 rects
+caravel_00088bca_fill_pattern_3_4: 3360000 rects
+caravel_00088bca_fill_pattern_1_2: 4390000 rects
+caravel_00088bca_fill_pattern_3_0: 4340000 rects
+caravel_00088bca_fill_pattern_3_2: 4640000 rects
+caravel_00088bca_fill_pattern_0_1: 4600000 rects
+caravel_00088bca_fill_pattern_1_0: 4390000 rects
+caravel_00088bca_fill_pattern_4_5: 4770000 rects
+caravel_00088bca_fill_pattern_1_4: 4310000 rects
+caravel_00088bca_fill_pattern_3_4: 3370000 rects
+caravel_00088bca_fill_pattern_2_1: 3010000 rects
+caravel_00088bca_fill_pattern_0_1: 4610000 rects
+caravel_00088bca_fill_pattern_2_3: 4480000 rects
+caravel_00088bca_fill_pattern_3_0: 4350000 rects
+caravel_00088bca_fill_pattern_1_0: 4400000 rects
+caravel_00088bca_fill_pattern_4_5: 4780000 rects
+caravel_00088bca_fill_pattern_3_4: 3380000 rects
+caravel_00088bca_fill_pattern_3_2: 4650000 rects
+caravel_00088bca_fill_pattern_1_4: 4320000 rects
+caravel_00088bca_fill_pattern_1_2: 4400000 rects
+caravel_00088bca_fill_pattern_0_1: 4620000 rects
+caravel_00088bca_fill_pattern_2_1: 3020000 rects
+caravel_00088bca_fill_pattern_3_4: 3390000 rects
+caravel_00088bca_fill_pattern_3_0: 4360000 rects
+caravel_00088bca_fill_pattern_1_0: 4410000 rects
+caravel_00088bca_fill_pattern_4_5: 4790000 rects
+caravel_00088bca_fill_pattern_2_3: 4490000 rects
+caravel_00088bca_fill_pattern_3_4: 3400000 rects
+caravel_00088bca_fill_pattern_0_1: 4630000 rects
+caravel_00088bca_fill_pattern_4_5: 4800000 rects
+caravel_00088bca_fill_pattern_1_4: 4330000 rects
+caravel_00088bca_fill_pattern_0_1: 4640000 rects
+caravel_00088bca_fill_pattern_1_0: 4420000 rects
+caravel_00088bca_fill_pattern_2_1: 3030000 rects
+caravel_00088bca_fill_pattern_0_1: 4650000 rects
+caravel_00088bca_fill_pattern_3_0: 4370000 rects
+caravel_00088bca_fill_pattern_4_5: 4810000 rects
+caravel_00088bca_fill_pattern_0_1: 4660000 rects
+caravel_00088bca_fill_pattern_3_4: 3410000 rects
+caravel_00088bca_fill_pattern_1_2: 4410000 rects
+caravel_00088bca_fill_pattern_4_5: 4820000 rects
+caravel_00088bca_fill_pattern_0_1: 4670000 rects
+caravel_00088bca_fill_pattern_4_5: 4830000 rects
+caravel_00088bca_fill_pattern_3_2: 4660000 rects
+caravel_00088bca_fill_pattern_2_3: 4500000 rects
+caravel_00088bca_fill_pattern_4_5: 4840000 rects
+caravel_00088bca_fill_pattern_1_0: 4430000 rects
+caravel_00088bca_fill_pattern_4_5: 4850000 rects
+caravel_00088bca_fill_pattern_3_4: 3420000 rects
+caravel_00088bca_fill_pattern_1_4: 4340000 rects
+caravel_00088bca_fill_pattern_4_5: 4860000 rects
+caravel_00088bca_fill_pattern_2_1: 3040000 rects
+caravel_00088bca_fill_pattern_3_0: 4380000 rects
+caravel_00088bca_fill_pattern_4_5: 4870000 rects
+caravel_00088bca_fill_pattern_0_1: 4680000 rects
+caravel_00088bca_fill_pattern_3_4: 3430000 rects
+caravel_00088bca_fill_pattern_3_2: 4670000 rects
+caravel_00088bca_fill_pattern_1_0: 4440000 rects
+caravel_00088bca_fill_pattern_2_3: 4510000 rects
+caravel_00088bca_fill_pattern_1_4: 4350000 rects
+caravel_00088bca_fill_pattern_1_2: 4420000 rects
+caravel_00088bca_fill_pattern_3_4: 3440000 rects
+caravel_00088bca_fill_pattern_3_0: 4390000 rects
+caravel_00088bca_fill_pattern_2_1: 3050000 rects
+caravel_00088bca_fill_pattern_3_2: 4680000 rects
+caravel_00088bca_fill_pattern_1_0: 4450000 rects
+caravel_00088bca_fill_pattern_3_4: 3450000 rects
+caravel_00088bca_fill_pattern_2_3: 4520000 rects
+caravel_00088bca_fill_pattern_1_4: 4360000 rects
+caravel_00088bca_fill_pattern_3_0: 4400000 rects
+caravel_00088bca_fill_pattern_3_2: 4690000 rects
+caravel_00088bca_fill_pattern_3_4: 3460000 rects
+caravel_00088bca_fill_pattern_2_1: 3060000 rects
+caravel_00088bca_fill_pattern_1_0: 4460000 rects
+caravel_00088bca_fill_pattern_1_2: 4430000 rects
+caravel_00088bca_fill_pattern_3_4: 3470000 rects
+caravel_00088bca_fill_pattern_3_2: 4700000 rects
+caravel_00088bca_fill_pattern_1_4: 4370000 rects
+caravel_00088bca_fill_pattern_2_3: 4530000 rects
+caravel_00088bca_fill_pattern_2_1: 3070000 rects
+caravel_00088bca_fill_pattern_3_0: 4410000 rects
+caravel_00088bca_fill_pattern_3_2: 4710000 rects
+caravel_00088bca_fill_pattern_1_0: 4470000 rects
+caravel_00088bca_fill_pattern_3_4: 3480000 rects
+caravel_00088bca_fill_pattern_3_2: 4720000 rects
+caravel_00088bca_fill_pattern_3_2: 4730000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00088bca_fill_pattern_3_2: 4740000 rects
+   Generating output for cell caravel_00088bca_fill_pattern_0_1
+caravel_00088bca_fill_pattern_3_0: 4420000 rects
+caravel_00088bca_fill_pattern_3_2: 4750000 rects
+caravel_00088bca_fill_pattern_3_4: 3490000 rects
+caravel_00088bca_fill_pattern_1_4: 4380000 rects
+caravel_00088bca_fill_pattern_3_2: 4760000 rects
+caravel_00088bca_fill_pattern_1_0: 4480000 rects
+caravel_00088bca_fill_pattern_2_1: 3080000 rects
+caravel_00088bca_fill_pattern_1_2: 4440000 rects
+caravel_00088bca_fill_pattern_3_2: 4770000 rects
+caravel_00088bca_fill_pattern_2_3: 4540000 rects
+caravel_00088bca_fill_pattern_3_4: 3500000 rects
+caravel_00088bca_fill_pattern_4_5: 4880000 rects
+caravel_00088bca_fill_pattern_3_2: 4780000 rects
+caravel_00088bca_fill_pattern_1_0: 4490000 rects
+caravel_00088bca_fill_pattern_3_0: 4430000 rects
+caravel_00088bca_fill_pattern_3_4: 3510000 rects
+caravel_00088bca_fill_pattern_2_1: 3090000 rects
+caravel_00088bca_fill_pattern_1_4: 4390000 rects
+caravel_00088bca_fill_pattern_3_2: 4790000 rects
+caravel_00088bca_fill_pattern_2_3: 4550000 rects
+caravel_00088bca_fill_pattern_1_0: 4500000 rects
+caravel_00088bca_fill_pattern_3_4: 3520000 rects
+caravel_00088bca_fill_pattern_3_0: 4440000 rects
+caravel_00088bca_fill_pattern_3_2: 4800000 rects
+caravel_00088bca_fill_pattern_1_2: 4450000 rects
+caravel_00088bca_fill_pattern_1_4: 4400000 rects
+caravel_00088bca_fill_pattern_2_1: 3100000 rects
+caravel_00088bca_fill_pattern_3_4: 3530000 rects
+caravel_00088bca_fill_pattern_1_0: 4510000 rects
+caravel_00088bca_fill_pattern_3_2: 4810000 rects
+caravel_00088bca_fill_pattern_2_3: 4560000 rects
+caravel_00088bca_fill_pattern_3_2: 4820000 rects
+caravel_00088bca_fill_pattern_3_0: 4450000 rects
+caravel_00088bca_fill_pattern_3_4: 3540000 rects
+caravel_00088bca_fill_pattern_3_2: 4830000 rects
+caravel_00088bca_fill_pattern_3_2: 4840000 rects
+caravel_00088bca_fill_pattern_1_4: 4410000 rects
+caravel_00088bca_fill_pattern_3_2: 4850000 rects
+caravel_00088bca_fill_pattern_1_0: 4520000 rects
+caravel_00088bca_fill_pattern_2_1: 3110000 rects
+caravel_00088bca_fill_pattern_3_2: 4860000 rects
+caravel_00088bca_fill_pattern_3_4: 3550000 rects
+caravel_00088bca_fill_pattern_3_2: 4870000 rects
+caravel_00088bca_fill_pattern_2_3: 4570000 rects
+caravel_00088bca_fill_pattern_1_2: 4460000 rects
+caravel_00088bca_fill_pattern_3_0: 4460000 rects
+caravel_00088bca_fill_pattern_3_2: 4880000 rects
+caravel_00088bca_fill_pattern_3_4: 3560000 rects
+caravel_00088bca_fill_pattern_1_0: 4530000 rects
+caravel_00088bca_fill_pattern_1_4: 4420000 rects
+caravel_00088bca_fill_pattern_2_1: 3120000 rects
+caravel_00088bca_fill_pattern_2_3: 4580000 rects
+caravel_00088bca_fill_pattern_3_4: 3570000 rects
+caravel_00088bca_fill_pattern_3_0: 4470000 rects
+caravel_00088bca_fill_pattern_1_0: 4540000 rects
+caravel_00088bca_fill_pattern_1_4: 4430000 rects
+caravel_00088bca_fill_pattern_3_4: 3580000 rects
+caravel_00088bca_fill_pattern_3_0: 4480000 rects
+caravel_00088bca_fill_pattern_2_1: 3130000 rects
+caravel_00088bca_fill_pattern_1_2: 4470000 rects
+caravel_00088bca_fill_pattern_3_2: 4890000 rects
+caravel_00088bca_fill_pattern_2_3: 4590000 rects
+caravel_00088bca_fill_pattern_1_0: 4550000 rects
+caravel_00088bca_fill_pattern_3_4: 3590000 rects
+caravel_00088bca_fill_pattern_4_5: 4890000 rects
+caravel_00088bca_fill_pattern_3_0: 4490000 rects
+caravel_00088bca_fill_pattern_2_1: 3140000 rects
+caravel_00088bca_fill_pattern_3_4: 3600000 rects
+caravel_00088bca_fill_pattern_1_4: 4440000 rects
+caravel_00088bca_fill_pattern_1_0: 4560000 rects
+caravel_00088bca_fill_pattern_4_5: 4900000 rects
+caravel_00088bca_fill_pattern_2_3: 4600000 rects
+caravel_00088bca_fill_pattern_3_4: 3610000 rects
+caravel_00088bca_fill_pattern_4_5: 4910000 rects
+caravel_00088bca_fill_pattern_1_0: 4570000 rects
+caravel_00088bca_fill_pattern_3_0: 4500000 rects
+caravel_00088bca_fill_pattern_4_5: 4920000 rects
+caravel_00088bca_fill_pattern_2_1: 3150000 rects
+caravel_00088bca_fill_pattern_1_4: 4450000 rects
+caravel_00088bca_fill_pattern_3_4: 3620000 rects
+caravel_00088bca_fill_pattern_2_3: 4610000 rects
+caravel_00088bca_fill_pattern_1_0: 4580000 rects
+caravel_00088bca_fill_pattern_3_4: 3630000 rects
+caravel_00088bca_fill_pattern_3_0: 4510000 rects
+caravel_00088bca_fill_pattern_2_1: 3160000 rects
+caravel_00088bca_fill_pattern_1_4: 4460000 rects
+caravel_00088bca_fill_pattern_4_5: 4930000 rects
+caravel_00088bca_fill_pattern_3_4: 3640000 rects
+caravel_00088bca_fill_pattern_1_0: 4590000 rects
+caravel_00088bca_fill_pattern_2_3: 4620000 rects
+caravel_00088bca_fill_pattern_3_0: 4520000 rects
+caravel_00088bca_fill_pattern_3_4: 3650000 rects
+caravel_00088bca_fill_pattern_2_1: 3170000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00088bca_fill_pattern_3_2
+caravel_00088bca_fill_pattern_1_4: 4470000 rects
+caravel_00088bca_fill_pattern_3_4: 3660000 rects
+caravel_00088bca_fill_pattern_1_0: 4600000 rects
+caravel_00088bca_fill_pattern_3_0: 4530000 rects
+caravel_00088bca_fill_pattern_2_3: 4630000 rects
+caravel_00088bca_fill_pattern_2_1: 3180000 rects
+caravel_00088bca_fill_pattern_3_4: 3670000 rects
+caravel_00088bca_fill_pattern_1_0: 4610000 rects
+caravel_00088bca_fill_pattern_1_4: 4480000 rects
+caravel_00088bca_fill_pattern_3_0: 4540000 rects
+caravel_00088bca_fill_pattern_3_4: 3680000 rects
+caravel_00088bca_fill_pattern_2_3: 4640000 rects
+caravel_00088bca_fill_pattern_2_1: 3190000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00088bca_fill_pattern_4_5
+caravel_00088bca_fill_pattern_1_0: 4620000 rects
+caravel_00088bca_fill_pattern_3_4: 3690000 rects
+caravel_00088bca_fill_pattern_1_4: 4490000 rects
+caravel_00088bca_fill_pattern_3_0: 4550000 rects
+caravel_00088bca_fill_pattern_3_4: 3700000 rects
+caravel_00088bca_fill_pattern_2_3: 4650000 rects
+caravel_00088bca_fill_pattern_2_1: 3200000 rects
+caravel_00088bca_fill_pattern_1_0: 4630000 rects
+caravel_00088bca_fill_pattern_1_4: 4500000 rects
+caravel_00088bca_fill_pattern_3_4: 3710000 rects
+caravel_00088bca_fill_pattern_3_0: 4560000 rects
+caravel_00088bca_fill_pattern_1_0: 4640000 rects
+caravel_00088bca_fill_pattern_2_1: 3210000 rects
+caravel_00088bca_fill_pattern_3_4: 3720000 rects
+caravel_00088bca_fill_pattern_2_3: 4660000 rects
+caravel_00088bca_fill_pattern_1_4: 4510000 rects
+caravel_00088bca_fill_pattern_3_0: 4570000 rects
+caravel_00088bca_fill_pattern_3_4: 3730000 rects
+caravel_00088bca_fill_pattern_1_0: 4650000 rects
+caravel_00088bca_fill_pattern_2_1: 3220000 rects
+caravel_00088bca_fill_pattern_2_3: 4670000 rects
+caravel_00088bca_fill_pattern_3_4: 3740000 rects
+caravel_00088bca_fill_pattern_3_0: 4580000 rects
+caravel_00088bca_fill_pattern_1_4: 4520000 rects
+caravel_00088bca_fill_pattern_1_0: 4660000 rects
+caravel_00088bca_fill_pattern_3_4: 3750000 rects
+caravel_00088bca_fill_pattern_2_1: 3230000 rects
+caravel_00088bca_fill_pattern_3_0: 4590000 rects
+caravel_00088bca_fill_pattern_2_3: 4680000 rects
+caravel_00088bca_fill_pattern_1_0: 4670000 rects
+caravel_00088bca_fill_pattern_3_4: 3760000 rects
+caravel_00088bca_fill_pattern_1_4: 4530000 rects
+caravel_00088bca_fill_pattern_3_4: 3770000 rects
+caravel_00088bca_fill_pattern_2_1: 3240000 rects
+caravel_00088bca_fill_pattern_1_2: 4480000 rects
+caravel_00088bca_fill_pattern_3_0: 4600000 rects
+caravel_00088bca_fill_pattern_1_0: 4680000 rects
+caravel_00088bca_fill_pattern_2_3: 4690000 rects
+caravel_00088bca_fill_pattern_3_4: 3780000 rects
+caravel_00088bca_fill_pattern_1_2: 4490000 rects
+caravel_00088bca_fill_pattern_1_4: 4540000 rects
+caravel_00088bca_fill_pattern_1_2: 4500000 rects
+caravel_00088bca_fill_pattern_2_1: 3250000 rects
+caravel_00088bca_fill_pattern_1_2: 4510000 rects
+caravel_00088bca_fill_pattern_1_0: 4690000 rects
+caravel_00088bca_fill_pattern_3_4: 3790000 rects
+caravel_00088bca_fill_pattern_3_0: 4610000 rects
+caravel_00088bca_fill_pattern_1_2: 4520000 rects
+caravel_00088bca_fill_pattern_1_4: 4550000 rects
+caravel_00088bca_fill_pattern_2_3: 4700000 rects
+caravel_00088bca_fill_pattern_1_0: 4700000 rects
+caravel_00088bca_fill_pattern_1_2: 4530000 rects
+caravel_00088bca_fill_pattern_3_4: 3800000 rects
+caravel_00088bca_fill_pattern_2_1: 3260000 rects
+caravel_00088bca_fill_pattern_1_2: 4540000 rects
+caravel_00088bca_fill_pattern_3_0: 4620000 rects
+caravel_00088bca_fill_pattern_3_4: 3810000 rects
+caravel_00088bca_fill_pattern_1_0: 4710000 rects
+caravel_00088bca_fill_pattern_1_2: 4550000 rects
+caravel_00088bca_fill_pattern_2_1: 3270000 rects
+caravel_00088bca_fill_pattern_1_4: 4560000 rects
+caravel_00088bca_fill_pattern_2_3: 4710000 rects
+caravel_00088bca_fill_pattern_3_4: 3820000 rects
+caravel_00088bca_fill_pattern_3_0: 4630000 rects
+caravel_00088bca_fill_pattern_1_0: 4720000 rects
+caravel_00088bca_fill_pattern_3_4: 3830000 rects
+caravel_00088bca_fill_pattern_1_2: 4560000 rects
+caravel_00088bca_fill_pattern_1_4: 4570000 rects
+caravel_00088bca_fill_pattern_2_1: 3280000 rects
+caravel_00088bca_fill_pattern_2_3: 4720000 rects
+caravel_00088bca_fill_pattern_3_0: 4640000 rects
+caravel_00088bca_fill_pattern_3_4: 3840000 rects
+caravel_00088bca_fill_pattern_1_0: 4730000 rects
+caravel_00088bca_fill_pattern_3_4: 3850000 rects
+caravel_00088bca_fill_pattern_2_1: 3290000 rects
+caravel_00088bca_fill_pattern_1_4: 4580000 rects
+caravel_00088bca_fill_pattern_3_0: 4650000 rects
+caravel_00088bca_fill_pattern_2_3: 4730000 rects
+caravel_00088bca_fill_pattern_3_4: 3860000 rects
+caravel_00088bca_fill_pattern_1_0: 4740000 rects
+caravel_00088bca_fill_pattern_2_1: 3300000 rects
+caravel_00088bca_fill_pattern_1_4: 4590000 rects
+caravel_00088bca_fill_pattern_3_4: 3870000 rects
+caravel_00088bca_fill_pattern_3_0: 4660000 rects
+caravel_00088bca_fill_pattern_1_0: 4750000 rects
+caravel_00088bca_fill_pattern_2_3: 4740000 rects
+caravel_00088bca_fill_pattern_3_4: 3880000 rects
+caravel_00088bca_fill_pattern_2_1: 3310000 rects
+caravel_00088bca_fill_pattern_1_4: 4600000 rects
+caravel_00088bca_fill_pattern_3_4: 3890000 rects
+caravel_00088bca_fill_pattern_3_0: 4670000 rects
+caravel_00088bca_fill_pattern_1_0: 4760000 rects
+caravel_00088bca_fill_pattern_2_1: 3320000 rects
+caravel_00088bca_fill_pattern_2_3: 4750000 rects
+caravel_00088bca_fill_pattern_3_4: 3900000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00088bca_fill_pattern_1_2
+caravel_00088bca_fill_pattern_3_0: 4680000 rects
+caravel_00088bca_fill_pattern_1_4: 4610000 rects
+caravel_00088bca_fill_pattern_1_0: 4770000 rects
+caravel_00088bca_fill_pattern_3_4: 3910000 rects
+caravel_00088bca_fill_pattern_2_1: 3330000 rects
+caravel_00088bca_fill_pattern_2_3: 4760000 rects
+caravel_00088bca_fill_pattern_3_4: 3920000 rects
+caravel_00088bca_fill_pattern_1_0: 4780000 rects
+caravel_00088bca_fill_pattern_1_4: 4620000 rects
+caravel_00088bca_fill_pattern_3_0: 4690000 rects
+caravel_00088bca_fill_pattern_2_1: 3340000 rects
+caravel_00088bca_fill_pattern_3_4: 3930000 rects
+caravel_00088bca_fill_pattern_1_0: 4790000 rects
+caravel_00088bca_fill_pattern_2_3: 4770000 rects
+caravel_00088bca_fill_pattern_3_0: 4700000 rects
+caravel_00088bca_fill_pattern_1_4: 4630000 rects
+caravel_00088bca_fill_pattern_3_4: 3940000 rects
+caravel_00088bca_fill_pattern_1_0: 4800000 rects
+caravel_00088bca_fill_pattern_2_1: 3350000 rects
+caravel_00088bca_fill_pattern_3_4: 3950000 rects
+caravel_00088bca_fill_pattern_1_0: 4810000 rects
+caravel_00088bca_fill_pattern_3_0: 4710000 rects
+caravel_00088bca_fill_pattern_2_3: 4780000 rects
+caravel_00088bca_fill_pattern_1_0: 4820000 rects
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+caravel_00088bca_fill_pattern_3_4: 4870000 rects
+caravel_00088bca_fill_pattern_2_3: 5120000 rects
+caravel_00088bca_fill_pattern_1_0: 5780000 rects
+caravel_00088bca_fill_pattern_1_4: 5020000 rects
+caravel_00088bca_fill_pattern_3_0: 5300000 rects
+caravel_00088bca_fill_pattern_3_4: 4880000 rects
+caravel_00088bca_fill_pattern_3_0: 5310000 rects
+caravel_00088bca_fill_pattern_2_1: 3760000 rects
+caravel_00088bca_fill_pattern_1_0: 5790000 rects
+caravel_00088bca_fill_pattern_3_4: 4890000 rects
+caravel_00088bca_fill_pattern_3_0: 5320000 rects
+caravel_00088bca_fill_pattern_2_3: 5130000 rects
+caravel_00088bca_fill_pattern_1_4: 5030000 rects
+caravel_00088bca_fill_pattern_1_0: 5800000 rects
+caravel_00088bca_fill_pattern_3_0: 5330000 rects
+caravel_00088bca_fill_pattern_3_4: 4900000 rects
+caravel_00088bca_fill_pattern_2_1: 3770000 rects
+caravel_00088bca_fill_pattern_3_0: 5340000 rects
+caravel_00088bca_fill_pattern_1_0: 5810000 rects
+caravel_00088bca_fill_pattern_3_4: 4910000 rects
+caravel_00088bca_fill_pattern_1_4: 5040000 rects
+caravel_00088bca_fill_pattern_3_0: 5350000 rects
+caravel_00088bca_fill_pattern_2_3: 5140000 rects
+caravel_00088bca_fill_pattern_3_4: 4920000 rects
+caravel_00088bca_fill_pattern_1_0: 5820000 rects
+caravel_00088bca_fill_pattern_3_0: 5360000 rects
+caravel_00088bca_fill_pattern_3_4: 4930000 rects
+caravel_00088bca_fill_pattern_3_0: 5370000 rects
+caravel_00088bca_fill_pattern_1_0: 5830000 rects
+caravel_00088bca_fill_pattern_1_4: 5050000 rects
+caravel_00088bca_fill_pattern_2_1: 3780000 rects
+caravel_00088bca_fill_pattern_3_4: 4940000 rects
+caravel_00088bca_fill_pattern_3_0: 5380000 rects
+caravel_00088bca_fill_pattern_1_0: 5840000 rects
+caravel_00088bca_fill_pattern_2_3: 5150000 rects
+caravel_00088bca_fill_pattern_3_0: 5390000 rects
+caravel_00088bca_fill_pattern_3_4: 4950000 rects
+caravel_00088bca_fill_pattern_2_1: 3790000 rects
+caravel_00088bca_fill_pattern_1_0: 5850000 rects
+caravel_00088bca_fill_pattern_1_4: 5060000 rects
+caravel_00088bca_fill_pattern_3_0: 5400000 rects
+caravel_00088bca_fill_pattern_3_4: 4960000 rects
+caravel_00088bca_fill_pattern_3_0: 5410000 rects
+caravel_00088bca_fill_pattern_1_0: 5860000 rects
+caravel_00088bca_fill_pattern_2_3: 5160000 rects
+caravel_00088bca_fill_pattern_3_4: 4970000 rects
+Ended: 12/04/2022 06:05:12
+caravel_00088bca_fill_pattern_3_0: 5420000 rects
+caravel_00088bca_fill_pattern_2_1: 3800000 rects
+caravel_00088bca_fill_pattern_1_4: 5070000 rects
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_00088bca_fill_pattern_1_0: 5870000 rects
+caravel_00088bca_fill_pattern_3_4: 4980000 rects
+Processing system .magicrc file
+caravel_00088bca_fill_pattern_3_0: 5430000 rects
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_00088bca_fill_pattern_1_0: 5880000 rects
+caravel_00088bca_fill_pattern_3_4: 4990000 rects
+caravel_00088bca_fill_pattern_3_0: 5440000 rects
+caravel_00088bca_fill_pattern_2_3: 5170000 rects
+caravel_00088bca_fill_pattern_2_1: 3810000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_00088bca_fill_pattern_1_4: 5080000 rects
+caravel_00088bca_fill_pattern_3_0: 5450000 rects
+caravel_00088bca_fill_pattern_3_4: 5000000 rects
+caravel_00088bca_fill_pattern_1_0: 5890000 rects
+caravel_00088bca_fill_pattern_3_0: 5460000 rects
+caravel_00088bca_fill_pattern_3_4: 5010000 rects
+caravel_00088bca_fill_pattern_2_1: 3820000 rects
+caravel_00088bca_fill_pattern_1_0: 5900000 rects
+caravel_00088bca_fill_pattern_2_3: 5180000 rects
+caravel_00088bca_fill_pattern_3_0: 5470000 rects
+caravel_00088bca_fill_pattern_3_4: 5020000 rects
+caravel_00088bca_fill_pattern_1_4: 5090000 rects
+caravel_00088bca_fill_pattern_3_0: 5480000 rects
+caravel_00088bca_fill_pattern_1_0: 5910000 rects
+caravel_00088bca_fill_pattern_3_4: 5030000 rects
+caravel_00088bca_fill_pattern_3_0: 5490000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+caravel_00088bca_fill_pattern_2_1: 3830000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_00088bca_fill_pattern_2_3: 5190000 rects
+caravel_00088bca_fill_pattern_1_0: 5920000 rects
+caravel_00088bca_fill_pattern_3_0: 5500000 rects
+caravel_00088bca_fill_pattern_3_4: 5040000 rects
+caravel_00088bca_fill_pattern_5_2: 10000 rects
+caravel_00088bca_fill_pattern_1_4: 5100000 rects
+caravel_00088bca_fill_pattern_5_2: 20000 rects
+caravel_00088bca_fill_pattern_3_0: 5510000 rects
+caravel_00088bca_fill_pattern_5_2: 30000 rects
+caravel_00088bca_fill_pattern_1_0: 5930000 rects
+caravel_00088bca_fill_pattern_3_4: 5050000 rects
+caravel_00088bca_fill_pattern_5_2: 40000 rects
+caravel_00088bca_fill_pattern_3_0: 5520000 rects
+caravel_00088bca_fill_pattern_5_2: 50000 rects
+caravel_00088bca_fill_pattern_2_1: 3840000 rects
+caravel_00088bca_fill_pattern_5_2: 60000 rects
+caravel_00088bca_fill_pattern_2_3: 5200000 rects
+caravel_00088bca_fill_pattern_3_4: 5060000 rects
+caravel_00088bca_fill_pattern_1_0: 5940000 rects
+caravel_00088bca_fill_pattern_5_2: 70000 rects
+caravel_00088bca_fill_pattern_3_0: 5530000 rects
+caravel_00088bca_fill_pattern_5_2: 80000 rects
+caravel_00088bca_fill_pattern_1_4: 5110000 rects
+caravel_00088bca_fill_pattern_5_2: 90000 rects
+caravel_00088bca_fill_pattern_3_4: 5070000 rects
+caravel_00088bca_fill_pattern_3_0: 5540000 rects
+caravel_00088bca_fill_pattern_5_2: 100000 rects
+caravel_00088bca_fill_pattern_1_0: 5950000 rects
+caravel_00088bca_fill_pattern_2_1: 3850000 rects
+caravel_00088bca_fill_pattern_5_2: 110000 rects
+caravel_00088bca_fill_pattern_3_4: 5080000 rects
+caravel_00088bca_fill_pattern_3_0: 5550000 rects
+caravel_00088bca_fill_pattern_5_2: 120000 rects
+caravel_00088bca_fill_pattern_2_3: 5210000 rects
+caravel_00088bca_fill_pattern_1_0: 5960000 rects
+caravel_00088bca_fill_pattern_5_2: 130000 rects
+caravel_00088bca_fill_pattern_3_4: 5090000 rects
+caravel_00088bca_fill_pattern_1_4: 5120000 rects
+caravel_00088bca_fill_pattern_5_2: 140000 rects
+caravel_00088bca_fill_pattern_3_0: 5560000 rects
+caravel_00088bca_fill_pattern_2_1: 3860000 rects
+caravel_00088bca_fill_pattern_5_2: 150000 rects
+caravel_00088bca_fill_pattern_1_0: 5970000 rects
+caravel_00088bca_fill_pattern_3_4: 5100000 rects
+caravel_00088bca_fill_pattern_5_2: 160000 rects
+caravel_00088bca_fill_pattern_2_3: 5220000 rects
+caravel_00088bca_fill_pattern_5_2: 170000 rects
+caravel_00088bca_fill_pattern_3_0: 5570000 rects
+caravel_00088bca_fill_pattern_1_0: 5980000 rects
+caravel_00088bca_fill_pattern_3_4: 5110000 rects
+caravel_00088bca_fill_pattern_5_2: 180000 rects
+caravel_00088bca_fill_pattern_3_0: 5580000 rects
+caravel_00088bca_fill_pattern_1_4: 5130000 rects
+caravel_00088bca_fill_pattern_5_2: 190000 rects
+caravel_00088bca_fill_pattern_3_0: 5590000 rects
+caravel_00088bca_fill_pattern_2_1: 3870000 rects
+caravel_00088bca_fill_pattern_3_4: 5120000 rects
+caravel_00088bca_fill_pattern_1_0: 5990000 rects
+caravel_00088bca_fill_pattern_3_0: 5600000 rects
+caravel_00088bca_fill_pattern_5_2: 200000 rects
+caravel_00088bca_fill_pattern_3_0: 5610000 rects
+caravel_00088bca_fill_pattern_2_3: 5230000 rects
+caravel_00088bca_fill_pattern_5_2: 210000 rects
+caravel_00088bca_fill_pattern_3_4: 5130000 rects
+caravel_00088bca_fill_pattern_3_0: 5620000 rects
+caravel_00088bca_fill_pattern_1_0: 6000000 rects
+caravel_00088bca_fill_pattern_5_2: 220000 rects
+caravel_00088bca_fill_pattern_3_0: 5630000 rects
+caravel_00088bca_fill_pattern_1_4: 5140000 rects
+caravel_00088bca_fill_pattern_2_1: 3880000 rects
+caravel_00088bca_fill_pattern_3_4: 5140000 rects
+caravel_00088bca_fill_pattern_5_2: 230000 rects
+caravel_00088bca_fill_pattern_3_0: 5640000 rects
+caravel_00088bca_fill_pattern_5_2: 240000 rects
+caravel_00088bca_fill_pattern_3_0: 5650000 rects
+caravel_00088bca_fill_pattern_1_0: 6010000 rects
+caravel_00088bca_fill_pattern_2_3: 5240000 rects
+caravel_00088bca_fill_pattern_3_4: 5150000 rects
+caravel_00088bca_fill_pattern_5_2: 250000 rects
+caravel_00088bca_fill_pattern_3_0: 5660000 rects
+caravel_00088bca_fill_pattern_5_2: 260000 rects
+caravel_00088bca_fill_pattern_3_0: 5670000 rects
+caravel_00088bca_fill_pattern_1_4: 5150000 rects
+caravel_00088bca_fill_pattern_5_2: 270000 rects
+caravel_00088bca_fill_pattern_3_4: 5160000 rects
+caravel_00088bca_fill_pattern_1_0: 6020000 rects
+caravel_00088bca_fill_pattern_3_0: 5680000 rects
+caravel_00088bca_fill_pattern_2_1: 3890000 rects
+caravel_00088bca_fill_pattern_5_2: 280000 rects
+caravel_00088bca_fill_pattern_3_0: 5690000 rects
+caravel_00088bca_fill_pattern_3_4: 5170000 rects
+caravel_00088bca_fill_pattern_5_2: 290000 rects
+caravel_00088bca_fill_pattern_1_0: 6030000 rects
+caravel_00088bca_fill_pattern_2_3: 5250000 rects
+caravel_00088bca_fill_pattern_1_4: 5160000 rects
+caravel_00088bca_fill_pattern_3_0: 5700000 rects
+caravel_00088bca_fill_pattern_3_4: 5180000 rects
+caravel_00088bca_fill_pattern_5_2: 300000 rects
+caravel_00088bca_fill_pattern_1_0: 6040000 rects
+caravel_00088bca_fill_pattern_3_0: 5710000 rects
+caravel_00088bca_fill_pattern_1_4: 5170000 rects
+caravel_00088bca_fill_pattern_2_1: 3900000 rects
+caravel_00088bca_fill_pattern_3_4: 5190000 rects
+caravel_00088bca_fill_pattern_5_2: 310000 rects
+caravel_00088bca_fill_pattern_3_4: 5200000 rects
+caravel_00088bca_fill_pattern_1_0: 6050000 rects
+caravel_00088bca_fill_pattern_3_0: 5720000 rects
+caravel_00088bca_fill_pattern_1_4: 5180000 rects
+caravel_00088bca_fill_pattern_3_4: 5210000 rects
+caravel_00088bca_fill_pattern_2_3: 5260000 rects
+caravel_00088bca_fill_pattern_3_4: 5220000 rects
+caravel_00088bca_fill_pattern_5_2: 320000 rects
+caravel_00088bca_fill_pattern_3_4: 5230000 rects
+caravel_00088bca_fill_pattern_2_1: 3910000 rects
+caravel_00088bca_fill_pattern_3_0: 5730000 rects
+caravel_00088bca_fill_pattern_1_4: 5190000 rects
+caravel_00088bca_fill_pattern_1_0: 6060000 rects
+caravel_00088bca_fill_pattern_3_4: 5240000 rects
+caravel_00088bca_fill_pattern_5_2: 330000 rects
+Ended: 12/04/2022 06:05:14
+caravel_00088bca_fill_pattern_3_4: 5250000 rects
+caravel_00088bca_fill_pattern_3_0: 5740000 rects
+caravel_00088bca_fill_pattern_1_4: 5200000 rects
+caravel_00088bca_fill_pattern_3_4: 5260000 rects
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_00088bca_fill_pattern_1_0: 6070000 rects
+caravel_00088bca_fill_pattern_3_4: 5270000 rects
+caravel_00088bca_fill_pattern_5_2: 340000 rects
+caravel_00088bca_fill_pattern_2_3: 5270000 rects
+Processing system .magicrc file
+caravel_00088bca_fill_pattern_3_4: 5280000 rects
+Sourcing design .magicrc for technology sky130A ...
+caravel_00088bca_fill_pattern_3_0: 5750000 rects
+2 Magic internal units = 1 Lambda
+caravel_00088bca_fill_pattern_1_4: 5210000 rects
+caravel_00088bca_fill_pattern_3_4: 5290000 rects
+caravel_00088bca_fill_pattern_2_1: 3920000 rects
+caravel_00088bca_fill_pattern_1_0: 6080000 rects
+caravel_00088bca_fill_pattern_5_2: 350000 rects
+caravel_00088bca_fill_pattern_3_4: 5300000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_00088bca_fill_pattern_3_4: 5310000 rects
+caravel_00088bca_fill_pattern_3_0: 5760000 rects
+caravel_00088bca_fill_pattern_1_4: 5220000 rects
+caravel_00088bca_fill_pattern_3_4: 5320000 rects
+caravel_00088bca_fill_pattern_5_2: 360000 rects
+caravel_00088bca_fill_pattern_1_0: 6090000 rects
+caravel_00088bca_fill_pattern_3_4: 5330000 rects
+caravel_00088bca_fill_pattern_2_3: 5280000 rects
+caravel_00088bca_fill_pattern_3_0: 5770000 rects
+caravel_00088bca_fill_pattern_1_4: 5230000 rects
+caravel_00088bca_fill_pattern_3_4: 5340000 rects
+caravel_00088bca_fill_pattern_2_1: 3930000 rects
+caravel_00088bca_fill_pattern_5_2: 370000 rects
+caravel_00088bca_fill_pattern_3_4: 5350000 rects
+caravel_00088bca_fill_pattern_3_4: 5360000 rects
+caravel_00088bca_fill_pattern_1_0: 6100000 rects
+caravel_00088bca_fill_pattern_3_0: 5780000 rects
+caravel_00088bca_fill_pattern_1_4: 5240000 rects
+caravel_00088bca_fill_pattern_5_2: 380000 rects
+caravel_00088bca_fill_pattern_3_0: 5790000 rects
+caravel_00088bca_fill_pattern_1_4: 5250000 rects
+caravel_00088bca_fill_pattern_1_0: 6110000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+caravel_00088bca_fill_pattern_5_2: 390000 rects
+caravel_00088bca_fill_pattern_2_1: 3940000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+caravel_00088bca_fill_pattern_2_3: 5290000 rects
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_00088bca_fill_pattern_3_0: 5800000 rects
+caravel_00088bca_fill_pattern_1_4: 5260000 rects
+caravel_00088bca_fill_pattern_1_0: 6120000 rects
+caravel_00088bca_fill_pattern_5_2: 400000 rects
+caravel_00088bca_fill_pattern_1_6: 10000 rects
+caravel_00088bca_fill_pattern_1_6: 20000 rects
+caravel_00088bca_fill_pattern_3_0: 5810000 rects
+caravel_00088bca_fill_pattern_1_4: 5270000 rects
+caravel_00088bca_fill_pattern_1_6: 30000 rects
+caravel_00088bca_fill_pattern_5_2: 410000 rects
+caravel_00088bca_fill_pattern_2_1: 3950000 rects
+caravel_00088bca_fill_pattern_1_6: 40000 rects
+caravel_00088bca_fill_pattern_1_0: 6130000 rects
+caravel_00088bca_fill_pattern_1_6: 50000 rects
+caravel_00088bca_fill_pattern_2_3: 5300000 rects
+caravel_00088bca_fill_pattern_1_4: 5280000 rects
+caravel_00088bca_fill_pattern_3_0: 5820000 rects
+caravel_00088bca_fill_pattern_1_6: 60000 rects
+caravel_00088bca_fill_pattern_5_2: 420000 rects
+caravel_00088bca_fill_pattern_1_6: 70000 rects
+caravel_00088bca_fill_pattern_1_0: 6140000 rects
+caravel_00088bca_fill_pattern_1_6: 80000 rects
+caravel_00088bca_fill_pattern_1_4: 5290000 rects
+caravel_00088bca_fill_pattern_3_0: 5830000 rects
+caravel_00088bca_fill_pattern_5_2: 430000 rects
+caravel_00088bca_fill_pattern_1_6: 90000 rects
+caravel_00088bca_fill_pattern_1_6: 100000 rects
+caravel_00088bca_fill_pattern_2_1: 3960000 rects
+caravel_00088bca_fill_pattern_1_0: 6150000 rects
+caravel_00088bca_fill_pattern_1_4: 5300000 rects
+caravel_00088bca_fill_pattern_2_3: 5310000 rects
+caravel_00088bca_fill_pattern_3_0: 5840000 rects
+caravel_00088bca_fill_pattern_1_6: 110000 rects
+caravel_00088bca_fill_pattern_5_2: 440000 rects
+caravel_00088bca_fill_pattern_1_6: 120000 rects
+caravel_00088bca_fill_pattern_1_6: 130000 rects
+caravel_00088bca_fill_pattern_1_4: 5310000 rects
+caravel_00088bca_fill_pattern_3_0: 5850000 rects
+caravel_00088bca_fill_pattern_1_0: 6160000 rects
+caravel_00088bca_fill_pattern_1_6: 140000 rects
+caravel_00088bca_fill_pattern_5_2: 450000 rects
+caravel_00088bca_fill_pattern_1_6: 150000 rects
+caravel_00088bca_fill_pattern_1_4: 5320000 rects
+caravel_00088bca_fill_pattern_3_0: 5860000 rects
+caravel_00088bca_fill_pattern_1_6: 160000 rects
+caravel_00088bca_fill_pattern_5_2: 460000 rects
+caravel_00088bca_fill_pattern_2_1: 3970000 rects
+caravel_00088bca_fill_pattern_2_3: 5320000 rects
+caravel_00088bca_fill_pattern_1_0: 6170000 rects
+caravel_00088bca_fill_pattern_1_6: 170000 rects
+caravel_00088bca_fill_pattern_1_4: 5330000 rects
+caravel_00088bca_fill_pattern_3_0: 5870000 rects
+caravel_00088bca_fill_pattern_1_6: 180000 rects
+caravel_00088bca_fill_pattern_5_2: 470000 rects
+caravel_00088bca_fill_pattern_1_0: 6180000 rects
+caravel_00088bca_fill_pattern_1_6: 190000 rects
+caravel_00088bca_fill_pattern_1_4: 5340000 rects
+caravel_00088bca_fill_pattern_3_0: 5880000 rects
+caravel_00088bca_fill_pattern_5_2: 480000 rects
+caravel_00088bca_fill_pattern_2_1: 3980000 rects
+caravel_00088bca_fill_pattern_1_6: 200000 rects
+caravel_00088bca_fill_pattern_2_3: 5330000 rects
+caravel_00088bca_fill_pattern_1_0: 6190000 rects
+caravel_00088bca_fill_pattern_1_6: 210000 rects
+caravel_00088bca_fill_pattern_1_4: 5350000 rects
+caravel_00088bca_fill_pattern_3_0: 5890000 rects
+caravel_00088bca_fill_pattern_5_2: 490000 rects
+caravel_00088bca_fill_pattern_1_0: 6200000 rects
+caravel_00088bca_fill_pattern_1_6: 220000 rects
+caravel_00088bca_fill_pattern_5_2: 500000 rects
+caravel_00088bca_fill_pattern_1_6: 230000 rects
+caravel_00088bca_fill_pattern_1_4: 5360000 rects
+caravel_00088bca_fill_pattern_3_0: 5900000 rects
+caravel_00088bca_fill_pattern_1_0: 6210000 rects
+caravel_00088bca_fill_pattern_5_2: 510000 rects
+caravel_00088bca_fill_pattern_2_1: 3990000 rects
+caravel_00088bca_fill_pattern_1_6: 240000 rects
+caravel_00088bca_fill_pattern_2_3: 5340000 rects
+caravel_00088bca_fill_pattern_1_6: 250000 rects
+caravel_00088bca_fill_pattern_5_2: 520000 rects
+caravel_00088bca_fill_pattern_1_4: 5370000 rects
+caravel_00088bca_fill_pattern_1_0: 6220000 rects
+caravel_00088bca_fill_pattern_1_6: 260000 rects
+caravel_00088bca_fill_pattern_3_0: 5910000 rects
+caravel_00088bca_fill_pattern_5_2: 530000 rects
+caravel_00088bca_fill_pattern_1_6: 270000 rects
+caravel_00088bca_fill_pattern_5_2: 540000 rects
+caravel_00088bca_fill_pattern_1_0: 6230000 rects
+caravel_00088bca_fill_pattern_1_6: 280000 rects
+caravel_00088bca_fill_pattern_1_4: 5380000 rects
+caravel_00088bca_fill_pattern_5_2: 550000 rects
+caravel_00088bca_fill_pattern_3_0: 5920000 rects
+caravel_00088bca_fill_pattern_2_1: 4000000 rects
+caravel_00088bca_fill_pattern_1_6: 290000 rects
+caravel_00088bca_fill_pattern_1_0: 6240000 rects
+caravel_00088bca_fill_pattern_5_2: 560000 rects
+caravel_00088bca_fill_pattern_1_6: 300000 rects
+caravel_00088bca_fill_pattern_2_3: 5350000 rects
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+CIF output style is now "wafflefill(tiled)"
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+   Generating output for cell caravel_00088bca_fill_pattern_5_2
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+   Generating output for cell caravel_00088bca_fill_pattern_1_0
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+caravel_00088bca_fill_pattern_2_3: 6340000 rects
+caravel_00088bca_fill_pattern_3_4: 5760000 rects
+Ended: 12/04/2022 06:05:28
+caravel_00088bca_fill_pattern_3_4: 5770000 rects
+caravel_00088bca_fill_pattern_1_6: 2850000 rects
+caravel_00088bca_fill_pattern_2_1: 5330000 rects
+caravel_00088bca_fill_pattern_3_4: 5780000 rects
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
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+caravel_00088bca_fill_pattern_3_4: 5790000 rects
+caravel_00088bca_fill_pattern_3_4: 5800000 rects
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_00088bca_fill_pattern_1_6: 2860000 rects
+caravel_00088bca_fill_pattern_2_3: 6360000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_00088bca_fill_pattern_1_6: 2870000 rects
+caravel_00088bca_fill_pattern_2_3: 6370000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00088bca_fill_pattern_3_0
+caravel_00088bca_fill_pattern_2_1: 5340000 rects
+caravel_00088bca_fill_pattern_1_6: 2880000 rects
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+caravel_00088bca_fill_pattern_3_4: 5810000 rects
+caravel_00088bca_fill_pattern_1_6: 2890000 rects
+caravel_00088bca_fill_pattern_2_3: 6390000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
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+CIF output style is now "wafflefill(tiled)"
+caravel_00088bca_fill_pattern_1_6: 3130000 rects
+   Generating output for cell caravel_00088bca_fill_pattern_3_4
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+CIF output style is now "wafflefill(tiled)"
+caravel_00088bca_fill_pattern_4_3: 1660000 rects
+   Generating output for cell caravel_00088bca_fill_pattern_2_1
+caravel_00088bca_fill_pattern_1_4: 7080000 rects
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+caravel_00088bca_fill_pattern_4_3: 1920000 rects
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+caravel_00088bca_fill_pattern_1_6: 3790000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00088bca_fill_pattern_1_4
+caravel_00088bca_fill_pattern_4_3: 1950000 rects
+caravel_00088bca_fill_pattern_1_6: 3800000 rects
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+caravel_00088bca_fill_pattern_4_3: 2000000 rects
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+caravel_00088bca_fill_pattern_1_6: 4610000 rects
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+caravel_00088bca_fill_pattern_4_3: 2550000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00088bca_fill_pattern_2_3
+caravel_00088bca_fill_pattern_1_6: 4700000 rects
+caravel_00088bca_fill_pattern_4_3: 2560000 rects
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+caravel_00088bca_fill_pattern_4_3: 3180000 rects
+caravel_00088bca_fill_pattern_4_3: 3190000 rects
+caravel_00088bca_fill_pattern_4_3: 3200000 rects
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+caravel_00088bca_fill_pattern_4_3: 3300000 rects
+caravel_00088bca_fill_pattern_1_6: 5170000 rects
+caravel_00088bca_fill_pattern_4_3: 3310000 rects
+caravel_00088bca_fill_pattern_4_3: 3320000 rects
+caravel_00088bca_fill_pattern_4_3: 3330000 rects
+caravel_00088bca_fill_pattern_4_3: 3340000 rects
+caravel_00088bca_fill_pattern_4_3: 3350000 rects
+caravel_00088bca_fill_pattern_4_3: 3360000 rects
+caravel_00088bca_fill_pattern_4_3: 3370000 rects
+caravel_00088bca_fill_pattern_4_3: 3380000 rects
+caravel_00088bca_fill_pattern_4_3: 3390000 rects
+caravel_00088bca_fill_pattern_4_3: 3400000 rects
+caravel_00088bca_fill_pattern_4_3: 3410000 rects
+caravel_00088bca_fill_pattern_4_3: 3420000 rects
+caravel_00088bca_fill_pattern_4_3: 3430000 rects
+caravel_00088bca_fill_pattern_4_3: 3440000 rects
+caravel_00088bca_fill_pattern_4_3: 3450000 rects
+caravel_00088bca_fill_pattern_4_3: 3460000 rects
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+caravel_00088bca_fill_pattern_4_3: 3480000 rects
+caravel_00088bca_fill_pattern_4_3: 3490000 rects
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+caravel_00088bca_fill_pattern_4_3: 3500000 rects
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+caravel_00088bca_fill_pattern_1_6: 5200000 rects
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+caravel_00088bca_fill_pattern_1_6: 5230000 rects
+caravel_00088bca_fill_pattern_1_6: 5240000 rects
+caravel_00088bca_fill_pattern_1_6: 5250000 rects
+caravel_00088bca_fill_pattern_1_6: 5260000 rects
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+caravel_00088bca_fill_pattern_1_6: 5280000 rects
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+caravel_00088bca_fill_pattern_1_6: 5450000 rects
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+caravel_00088bca_fill_pattern_1_6: 5470000 rects
+caravel_00088bca_fill_pattern_1_6: 5480000 rects
+caravel_00088bca_fill_pattern_1_6: 5490000 rects
+caravel_00088bca_fill_pattern_1_6: 5500000 rects
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+caravel_00088bca_fill_pattern_4_3: 3720000 rects
+caravel_00088bca_fill_pattern_4_3: 3730000 rects
+caravel_00088bca_fill_pattern_4_3: 3740000 rects
+caravel_00088bca_fill_pattern_4_3: 3750000 rects
+caravel_00088bca_fill_pattern_4_3: 3760000 rects
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+caravel_00088bca_fill_pattern_4_3: 3770000 rects
+caravel_00088bca_fill_pattern_4_3: 3780000 rects
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+caravel_00088bca_fill_pattern_4_3: 3820000 rects
+caravel_00088bca_fill_pattern_4_3: 3830000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00088bca_fill_pattern_1_6
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00088bca_fill_pattern_4_3
+Ended: 12/04/2022 06:06:02
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_00088bca_fill_pattern_0_7: 10000 rects
+caravel_00088bca_fill_pattern_0_7: 20000 rects
+caravel_00088bca_fill_pattern_0_7: 30000 rects
+caravel_00088bca_fill_pattern_0_7: 40000 rects
+caravel_00088bca_fill_pattern_0_7: 50000 rects
+caravel_00088bca_fill_pattern_0_7: 60000 rects
+caravel_00088bca_fill_pattern_0_7: 70000 rects
+caravel_00088bca_fill_pattern_0_7: 80000 rects
+caravel_00088bca_fill_pattern_0_7: 90000 rects
+caravel_00088bca_fill_pattern_0_7: 100000 rects
+caravel_00088bca_fill_pattern_0_7: 110000 rects
+caravel_00088bca_fill_pattern_0_7: 120000 rects
+caravel_00088bca_fill_pattern_0_7: 130000 rects
+caravel_00088bca_fill_pattern_0_7: 140000 rects
+caravel_00088bca_fill_pattern_0_7: 150000 rects
+caravel_00088bca_fill_pattern_0_7: 160000 rects
+caravel_00088bca_fill_pattern_0_7: 170000 rects
+caravel_00088bca_fill_pattern_0_7: 180000 rects
+caravel_00088bca_fill_pattern_0_7: 190000 rects
+caravel_00088bca_fill_pattern_0_7: 200000 rects
+caravel_00088bca_fill_pattern_0_7: 210000 rects
+caravel_00088bca_fill_pattern_0_7: 220000 rects
+caravel_00088bca_fill_pattern_0_7: 230000 rects
+caravel_00088bca_fill_pattern_0_7: 240000 rects
+caravel_00088bca_fill_pattern_0_7: 250000 rects
+caravel_00088bca_fill_pattern_0_7: 260000 rects
+caravel_00088bca_fill_pattern_0_7: 270000 rects
+caravel_00088bca_fill_pattern_0_7: 280000 rects
+caravel_00088bca_fill_pattern_0_7: 290000 rects
+caravel_00088bca_fill_pattern_0_7: 300000 rects
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+caravel_00088bca_fill_pattern_0_7: 860000 rects
+caravel_00088bca_fill_pattern_0_7: 870000 rects
+caravel_00088bca_fill_pattern_0_7: 880000 rects
+caravel_00088bca_fill_pattern_0_7: 890000 rects
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+caravel_00088bca_fill_pattern_0_7: 950000 rects
+caravel_00088bca_fill_pattern_0_7: 960000 rects
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+caravel_00088bca_fill_pattern_0_7: 980000 rects
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+caravel_00088bca_fill_pattern_0_7: 1000000 rects
+caravel_00088bca_fill_pattern_0_7: 1010000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00088bca_fill_pattern_0_7
+Ended: 12/04/2022 06:06:47
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_00088bca_fill_pattern_2_5: 10000 rects
+caravel_00088bca_fill_pattern_2_5: 20000 rects
+caravel_00088bca_fill_pattern_2_5: 30000 rects
+caravel_00088bca_fill_pattern_2_5: 40000 rects
+caravel_00088bca_fill_pattern_2_5: 50000 rects
+caravel_00088bca_fill_pattern_2_5: 60000 rects
+caravel_00088bca_fill_pattern_2_5: 70000 rects
+caravel_00088bca_fill_pattern_2_5: 80000 rects
+caravel_00088bca_fill_pattern_2_5: 90000 rects
+caravel_00088bca_fill_pattern_2_5: 100000 rects
+caravel_00088bca_fill_pattern_2_5: 110000 rects
+caravel_00088bca_fill_pattern_2_5: 120000 rects
+caravel_00088bca_fill_pattern_2_5: 130000 rects
+caravel_00088bca_fill_pattern_2_5: 140000 rects
+caravel_00088bca_fill_pattern_2_5: 150000 rects
+caravel_00088bca_fill_pattern_2_5: 160000 rects
+caravel_00088bca_fill_pattern_2_5: 170000 rects
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+caravel_00088bca_fill_pattern_2_5: 3790000 rects
+caravel_00088bca_fill_pattern_2_5: 3800000 rects
+Ended: 12/04/2022 06:07:16
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_00088bca_fill_pattern_2_5: 3810000 rects
+caravel_00088bca_fill_pattern_2_5: 3820000 rects
+caravel_00088bca_fill_pattern_2_5: 3830000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_00088bca_fill_pattern_5_5: 10000 rects
+caravel_00088bca_fill_pattern_5_5: 20000 rects
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+caravel_00088bca_fill_pattern_5_5: 530000 rects
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+caravel_00088bca_fill_pattern_5_5: 550000 rects
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+caravel_00088bca_fill_pattern_5_5: 570000 rects
+caravel_00088bca_fill_pattern_5_5: 580000 rects
+Ended: 12/04/2022 06:07:19
+caravel_00088bca_fill_pattern_5_5: 590000 rects
+caravel_00088bca_fill_pattern_2_5: 4050000 rects
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_00088bca_fill_pattern_5_5: 600000 rects
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_00088bca_fill_pattern_5_5: 610000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_00088bca_fill_pattern_5_5: 620000 rects
+caravel_00088bca_fill_pattern_2_5: 4060000 rects
+caravel_00088bca_fill_pattern_5_5: 630000 rects
+caravel_00088bca_fill_pattern_5_5: 640000 rects
+caravel_00088bca_fill_pattern_5_5: 650000 rects
+caravel_00088bca_fill_pattern_5_5: 660000 rects
+caravel_00088bca_fill_pattern_2_5: 4070000 rects
+caravel_00088bca_fill_pattern_5_5: 670000 rects
+caravel_00088bca_fill_pattern_5_5: 680000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_00088bca_fill_pattern_5_5: 690000 rects
+caravel_00088bca_fill_pattern_3_7: 10000 rects
+caravel_00088bca_fill_pattern_2_5: 4080000 rects
+caravel_00088bca_fill_pattern_5_5: 700000 rects
+caravel_00088bca_fill_pattern_3_7: 20000 rects
+caravel_00088bca_fill_pattern_5_5: 710000 rects
+caravel_00088bca_fill_pattern_3_7: 30000 rects
+caravel_00088bca_fill_pattern_3_7: 40000 rects
+caravel_00088bca_fill_pattern_5_5: 720000 rects
+caravel_00088bca_fill_pattern_3_7: 50000 rects
+caravel_00088bca_fill_pattern_3_7: 60000 rects
+caravel_00088bca_fill_pattern_2_5: 4090000 rects
+caravel_00088bca_fill_pattern_5_5: 730000 rects
+caravel_00088bca_fill_pattern_3_7: 70000 rects
+caravel_00088bca_fill_pattern_5_5: 740000 rects
+caravel_00088bca_fill_pattern_3_7: 80000 rects
+caravel_00088bca_fill_pattern_3_7: 90000 rects
+caravel_00088bca_fill_pattern_3_7: 100000 rects
+caravel_00088bca_fill_pattern_5_5: 750000 rects
+caravel_00088bca_fill_pattern_3_7: 110000 rects
+caravel_00088bca_fill_pattern_2_5: 4100000 rects
+caravel_00088bca_fill_pattern_3_7: 120000 rects
+caravel_00088bca_fill_pattern_3_7: 130000 rects
+caravel_00088bca_fill_pattern_3_7: 140000 rects
+caravel_00088bca_fill_pattern_3_7: 150000 rects
+caravel_00088bca_fill_pattern_3_7: 160000 rects
+caravel_00088bca_fill_pattern_3_7: 170000 rects
+caravel_00088bca_fill_pattern_2_5: 4110000 rects
+caravel_00088bca_fill_pattern_3_7: 180000 rects
+caravel_00088bca_fill_pattern_3_7: 190000 rects
+caravel_00088bca_fill_pattern_3_7: 200000 rects
+caravel_00088bca_fill_pattern_2_5: 4120000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00088bca_fill_pattern_3_7: 210000 rects
+   Generating output for cell caravel_00088bca_fill_pattern_5_5
+caravel_00088bca_fill_pattern_3_7: 220000 rects
+caravel_00088bca_fill_pattern_3_7: 230000 rects
+caravel_00088bca_fill_pattern_2_5: 4130000 rects
+caravel_00088bca_fill_pattern_3_7: 240000 rects
+caravel_00088bca_fill_pattern_3_7: 250000 rects
+caravel_00088bca_fill_pattern_3_7: 260000 rects
+caravel_00088bca_fill_pattern_3_7: 270000 rects
+caravel_00088bca_fill_pattern_2_5: 4140000 rects
+caravel_00088bca_fill_pattern_3_7: 280000 rects
+Ended: 12/04/2022 06:07:21
+caravel_00088bca_fill_pattern_3_7: 290000 rects
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_00088bca_fill_pattern_3_7: 300000 rects
+caravel_00088bca_fill_pattern_2_5: 4150000 rects
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_00088bca_fill_pattern_3_7: 310000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_00088bca_fill_pattern_3_7: 320000 rects
+caravel_00088bca_fill_pattern_3_7: 330000 rects
+caravel_00088bca_fill_pattern_3_7: 340000 rects
+caravel_00088bca_fill_pattern_2_5: 4160000 rects
+caravel_00088bca_fill_pattern_3_7: 350000 rects
+caravel_00088bca_fill_pattern_3_7: 360000 rects
+caravel_00088bca_fill_pattern_3_7: 370000 rects
+caravel_00088bca_fill_pattern_3_7: 380000 rects
+caravel_00088bca_fill_pattern_2_5: 4170000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+caravel_00088bca_fill_pattern_3_7: 390000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_00088bca_fill_pattern_4_6: 10000 rects
+caravel_00088bca_fill_pattern_3_7: 400000 rects
+caravel_00088bca_fill_pattern_4_6: 20000 rects
+caravel_00088bca_fill_pattern_2_5: 4180000 rects
+caravel_00088bca_fill_pattern_4_6: 30000 rects
+caravel_00088bca_fill_pattern_4_6: 40000 rects
+caravel_00088bca_fill_pattern_4_6: 50000 rects
+caravel_00088bca_fill_pattern_4_6: 60000 rects
+caravel_00088bca_fill_pattern_3_7: 410000 rects
+caravel_00088bca_fill_pattern_4_6: 70000 rects
+caravel_00088bca_fill_pattern_4_6: 80000 rects
+caravel_00088bca_fill_pattern_2_5: 4190000 rects
+caravel_00088bca_fill_pattern_3_7: 420000 rects
+caravel_00088bca_fill_pattern_4_6: 90000 rects
+caravel_00088bca_fill_pattern_4_6: 100000 rects
+caravel_00088bca_fill_pattern_4_6: 110000 rects
+caravel_00088bca_fill_pattern_3_7: 430000 rects
+caravel_00088bca_fill_pattern_4_6: 120000 rects
+caravel_00088bca_fill_pattern_4_6: 130000 rects
+caravel_00088bca_fill_pattern_2_5: 4200000 rects
+caravel_00088bca_fill_pattern_4_6: 140000 rects
+caravel_00088bca_fill_pattern_3_7: 440000 rects
+caravel_00088bca_fill_pattern_4_6: 150000 rects
+caravel_00088bca_fill_pattern_4_6: 160000 rects
+caravel_00088bca_fill_pattern_3_7: 450000 rects
+caravel_00088bca_fill_pattern_4_6: 170000 rects
+caravel_00088bca_fill_pattern_4_6: 180000 rects
+caravel_00088bca_fill_pattern_4_6: 190000 rects
+caravel_00088bca_fill_pattern_3_7: 460000 rects
+caravel_00088bca_fill_pattern_4_6: 200000 rects
+caravel_00088bca_fill_pattern_2_5: 4210000 rects
+caravel_00088bca_fill_pattern_4_6: 210000 rects
+caravel_00088bca_fill_pattern_4_6: 220000 rects
+caravel_00088bca_fill_pattern_3_7: 470000 rects
+caravel_00088bca_fill_pattern_4_6: 230000 rects
+caravel_00088bca_fill_pattern_4_6: 240000 rects
+caravel_00088bca_fill_pattern_4_6: 250000 rects
+caravel_00088bca_fill_pattern_3_7: 480000 rects
+caravel_00088bca_fill_pattern_2_5: 4220000 rects
+caravel_00088bca_fill_pattern_4_6: 260000 rects
+caravel_00088bca_fill_pattern_4_6: 270000 rects
+caravel_00088bca_fill_pattern_3_7: 490000 rects
+caravel_00088bca_fill_pattern_4_6: 280000 rects
+caravel_00088bca_fill_pattern_4_6: 290000 rects
+caravel_00088bca_fill_pattern_3_7: 500000 rects
+caravel_00088bca_fill_pattern_2_5: 4230000 rects
+caravel_00088bca_fill_pattern_4_6: 300000 rects
+caravel_00088bca_fill_pattern_4_6: 310000 rects
+caravel_00088bca_fill_pattern_3_7: 510000 rects
+caravel_00088bca_fill_pattern_4_6: 320000 rects
+caravel_00088bca_fill_pattern_4_6: 330000 rects
+caravel_00088bca_fill_pattern_3_7: 520000 rects
+caravel_00088bca_fill_pattern_2_5: 4240000 rects
+caravel_00088bca_fill_pattern_4_6: 340000 rects
+caravel_00088bca_fill_pattern_3_7: 530000 rects
+caravel_00088bca_fill_pattern_4_6: 350000 rects
+caravel_00088bca_fill_pattern_4_6: 360000 rects
+caravel_00088bca_fill_pattern_4_6: 370000 rects
+caravel_00088bca_fill_pattern_3_7: 540000 rects
+caravel_00088bca_fill_pattern_2_5: 4250000 rects
+caravel_00088bca_fill_pattern_4_6: 380000 rects
+caravel_00088bca_fill_pattern_4_6: 390000 rects
+caravel_00088bca_fill_pattern_3_7: 550000 rects
+caravel_00088bca_fill_pattern_4_6: 400000 rects
+caravel_00088bca_fill_pattern_4_6: 410000 rects
+caravel_00088bca_fill_pattern_3_7: 560000 rects
+caravel_00088bca_fill_pattern_4_6: 420000 rects
+caravel_00088bca_fill_pattern_2_5: 4260000 rects
+caravel_00088bca_fill_pattern_4_6: 430000 rects
+caravel_00088bca_fill_pattern_3_7: 570000 rects
+caravel_00088bca_fill_pattern_4_6: 440000 rects
+caravel_00088bca_fill_pattern_4_6: 450000 rects
+caravel_00088bca_fill_pattern_3_7: 580000 rects
+caravel_00088bca_fill_pattern_4_6: 460000 rects
+caravel_00088bca_fill_pattern_2_5: 4270000 rects
+caravel_00088bca_fill_pattern_4_6: 470000 rects
+caravel_00088bca_fill_pattern_3_7: 590000 rects
+caravel_00088bca_fill_pattern_4_6: 480000 rects
+caravel_00088bca_fill_pattern_3_7: 600000 rects
+caravel_00088bca_fill_pattern_2_5: 4280000 rects
+caravel_00088bca_fill_pattern_4_6: 490000 rects
+caravel_00088bca_fill_pattern_3_7: 610000 rects
+caravel_00088bca_fill_pattern_4_6: 500000 rects
+caravel_00088bca_fill_pattern_3_7: 620000 rects
+caravel_00088bca_fill_pattern_4_6: 510000 rects
+caravel_00088bca_fill_pattern_2_5: 4290000 rects
+caravel_00088bca_fill_pattern_3_7: 630000 rects
+caravel_00088bca_fill_pattern_4_6: 520000 rects
+caravel_00088bca_fill_pattern_3_7: 640000 rects
+caravel_00088bca_fill_pattern_4_6: 530000 rects
+caravel_00088bca_fill_pattern_3_7: 650000 rects
+caravel_00088bca_fill_pattern_2_5: 4300000 rects
+caravel_00088bca_fill_pattern_3_7: 660000 rects
+caravel_00088bca_fill_pattern_4_6: 540000 rects
+caravel_00088bca_fill_pattern_3_7: 670000 rects
+caravel_00088bca_fill_pattern_3_7: 680000 rects
+caravel_00088bca_fill_pattern_4_6: 550000 rects
+caravel_00088bca_fill_pattern_2_5: 4310000 rects
+caravel_00088bca_fill_pattern_3_7: 690000 rects
+caravel_00088bca_fill_pattern_3_7: 700000 rects
+caravel_00088bca_fill_pattern_4_6: 560000 rects
+caravel_00088bca_fill_pattern_3_7: 710000 rects
+caravel_00088bca_fill_pattern_3_7: 720000 rects
+caravel_00088bca_fill_pattern_4_6: 570000 rects
+caravel_00088bca_fill_pattern_3_7: 730000 rects
+caravel_00088bca_fill_pattern_2_5: 4320000 rects
+caravel_00088bca_fill_pattern_3_7: 740000 rects
+caravel_00088bca_fill_pattern_3_7: 750000 rects
+caravel_00088bca_fill_pattern_4_6: 580000 rects
+caravel_00088bca_fill_pattern_3_7: 760000 rects
+caravel_00088bca_fill_pattern_3_7: 770000 rects
+caravel_00088bca_fill_pattern_4_6: 590000 rects
+caravel_00088bca_fill_pattern_3_7: 780000 rects
+caravel_00088bca_fill_pattern_2_5: 4330000 rects
+caravel_00088bca_fill_pattern_4_6: 600000 rects
+caravel_00088bca_fill_pattern_3_7: 790000 rects
+caravel_00088bca_fill_pattern_4_6: 610000 rects
+caravel_00088bca_fill_pattern_3_7: 800000 rects
+caravel_00088bca_fill_pattern_2_5: 4340000 rects
+caravel_00088bca_fill_pattern_4_6: 620000 rects
+caravel_00088bca_fill_pattern_3_7: 810000 rects
+caravel_00088bca_fill_pattern_4_6: 630000 rects
+caravel_00088bca_fill_pattern_3_7: 820000 rects
+caravel_00088bca_fill_pattern_3_7: 830000 rects
+caravel_00088bca_fill_pattern_2_5: 4350000 rects
+caravel_00088bca_fill_pattern_4_6: 640000 rects
+caravel_00088bca_fill_pattern_3_7: 840000 rects
+caravel_00088bca_fill_pattern_3_7: 850000 rects
+caravel_00088bca_fill_pattern_4_6: 650000 rects
+caravel_00088bca_fill_pattern_3_7: 860000 rects
+caravel_00088bca_fill_pattern_2_5: 4360000 rects
+caravel_00088bca_fill_pattern_3_7: 870000 rects
+caravel_00088bca_fill_pattern_3_7: 880000 rects
+caravel_00088bca_fill_pattern_4_6: 660000 rects
+caravel_00088bca_fill_pattern_3_7: 890000 rects
+caravel_00088bca_fill_pattern_2_5: 4370000 rects
+caravel_00088bca_fill_pattern_3_7: 900000 rects
+caravel_00088bca_fill_pattern_4_6: 670000 rects
+caravel_00088bca_fill_pattern_3_7: 910000 rects
+caravel_00088bca_fill_pattern_2_5: 4380000 rects
+caravel_00088bca_fill_pattern_3_7: 920000 rects
+caravel_00088bca_fill_pattern_4_6: 680000 rects
+caravel_00088bca_fill_pattern_3_7: 930000 rects
+caravel_00088bca_fill_pattern_3_7: 940000 rects
+caravel_00088bca_fill_pattern_4_6: 690000 rects
+caravel_00088bca_fill_pattern_2_5: 4390000 rects
+caravel_00088bca_fill_pattern_3_7: 950000 rects
+caravel_00088bca_fill_pattern_3_7: 960000 rects
+caravel_00088bca_fill_pattern_3_7: 970000 rects
+caravel_00088bca_fill_pattern_4_6: 700000 rects
+caravel_00088bca_fill_pattern_3_7: 980000 rects
+caravel_00088bca_fill_pattern_3_7: 990000 rects
+caravel_00088bca_fill_pattern_3_7: 1000000 rects
+caravel_00088bca_fill_pattern_2_5: 4400000 rects
+caravel_00088bca_fill_pattern_3_7: 1010000 rects
+caravel_00088bca_fill_pattern_4_6: 710000 rects
+caravel_00088bca_fill_pattern_3_7: 1020000 rects
+caravel_00088bca_fill_pattern_3_7: 1030000 rects
+caravel_00088bca_fill_pattern_4_6: 720000 rects
+caravel_00088bca_fill_pattern_2_5: 4410000 rects
+caravel_00088bca_fill_pattern_3_7: 1040000 rects
+caravel_00088bca_fill_pattern_4_6: 730000 rects
+caravel_00088bca_fill_pattern_3_7: 1050000 rects
+caravel_00088bca_fill_pattern_2_5: 4420000 rects
+caravel_00088bca_fill_pattern_4_6: 740000 rects
+caravel_00088bca_fill_pattern_3_7: 1060000 rects
+caravel_00088bca_fill_pattern_3_7: 1070000 rects
+caravel_00088bca_fill_pattern_4_6: 750000 rects
+caravel_00088bca_fill_pattern_2_5: 4430000 rects
+caravel_00088bca_fill_pattern_3_7: 1080000 rects
+caravel_00088bca_fill_pattern_3_7: 1090000 rects
+caravel_00088bca_fill_pattern_4_6: 760000 rects
+caravel_00088bca_fill_pattern_3_7: 1100000 rects
+caravel_00088bca_fill_pattern_2_5: 4440000 rects
+caravel_00088bca_fill_pattern_4_6: 770000 rects
+caravel_00088bca_fill_pattern_3_7: 1110000 rects
+caravel_00088bca_fill_pattern_4_6: 780000 rects
+caravel_00088bca_fill_pattern_3_7: 1120000 rects
+caravel_00088bca_fill_pattern_4_6: 790000 rects
+caravel_00088bca_fill_pattern_3_7: 1130000 rects
+caravel_00088bca_fill_pattern_4_6: 800000 rects
+caravel_00088bca_fill_pattern_4_6: 810000 rects
+caravel_00088bca_fill_pattern_2_5: 4450000 rects
+caravel_00088bca_fill_pattern_4_6: 820000 rects
+caravel_00088bca_fill_pattern_3_7: 1140000 rects
+caravel_00088bca_fill_pattern_4_6: 830000 rects
+caravel_00088bca_fill_pattern_3_7: 1150000 rects
+caravel_00088bca_fill_pattern_4_6: 840000 rects
+caravel_00088bca_fill_pattern_4_6: 850000 rects
+caravel_00088bca_fill_pattern_2_5: 4460000 rects
+caravel_00088bca_fill_pattern_4_6: 860000 rects
+caravel_00088bca_fill_pattern_3_7: 1160000 rects
+caravel_00088bca_fill_pattern_4_6: 870000 rects
+caravel_00088bca_fill_pattern_3_7: 1170000 rects
+caravel_00088bca_fill_pattern_4_6: 880000 rects
+caravel_00088bca_fill_pattern_3_7: 1180000 rects
+caravel_00088bca_fill_pattern_2_5: 4470000 rects
+caravel_00088bca_fill_pattern_4_6: 890000 rects
+caravel_00088bca_fill_pattern_3_7: 1190000 rects
+caravel_00088bca_fill_pattern_3_7: 1200000 rects
+caravel_00088bca_fill_pattern_4_6: 900000 rects
+caravel_00088bca_fill_pattern_3_7: 1210000 rects
+caravel_00088bca_fill_pattern_4_6: 910000 rects
+caravel_00088bca_fill_pattern_2_5: 4480000 rects
+caravel_00088bca_fill_pattern_4_6: 920000 rects
+caravel_00088bca_fill_pattern_3_7: 1220000 rects
+caravel_00088bca_fill_pattern_4_6: 930000 rects
+caravel_00088bca_fill_pattern_2_5: 4490000 rects
+caravel_00088bca_fill_pattern_3_7: 1230000 rects
+caravel_00088bca_fill_pattern_4_6: 940000 rects
+caravel_00088bca_fill_pattern_3_7: 1240000 rects
+caravel_00088bca_fill_pattern_3_7: 1250000 rects
+caravel_00088bca_fill_pattern_3_7: 1260000 rects
+caravel_00088bca_fill_pattern_2_5: 4500000 rects
+caravel_00088bca_fill_pattern_3_7: 1270000 rects
+caravel_00088bca_fill_pattern_4_6: 950000 rects
+caravel_00088bca_fill_pattern_2_5: 4510000 rects
+caravel_00088bca_fill_pattern_4_6: 960000 rects
+caravel_00088bca_fill_pattern_4_6: 970000 rects
+caravel_00088bca_fill_pattern_2_5: 4520000 rects
+caravel_00088bca_fill_pattern_4_6: 980000 rects
+caravel_00088bca_fill_pattern_4_6: 990000 rects
+caravel_00088bca_fill_pattern_4_6: 1000000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00088bca_fill_pattern_3_7
+caravel_00088bca_fill_pattern_4_6: 1010000 rects
+caravel_00088bca_fill_pattern_2_5: 4530000 rects
+caravel_00088bca_fill_pattern_4_6: 1020000 rects
+caravel_00088bca_fill_pattern_4_6: 1030000 rects
+caravel_00088bca_fill_pattern_2_5: 4540000 rects
+caravel_00088bca_fill_pattern_4_6: 1040000 rects
+caravel_00088bca_fill_pattern_4_6: 1050000 rects
+caravel_00088bca_fill_pattern_4_6: 1060000 rects
+caravel_00088bca_fill_pattern_4_6: 1070000 rects
+caravel_00088bca_fill_pattern_2_5: 4550000 rects
+caravel_00088bca_fill_pattern_4_6: 1080000 rects
+caravel_00088bca_fill_pattern_4_6: 1090000 rects
+caravel_00088bca_fill_pattern_4_6: 1100000 rects
+caravel_00088bca_fill_pattern_4_6: 1110000 rects
+caravel_00088bca_fill_pattern_4_6: 1120000 rects
+caravel_00088bca_fill_pattern_2_5: 4560000 rects
+caravel_00088bca_fill_pattern_4_6: 1130000 rects
+caravel_00088bca_fill_pattern_2_5: 4570000 rects
+caravel_00088bca_fill_pattern_2_5: 4580000 rects
+caravel_00088bca_fill_pattern_4_6: 1140000 rects
+caravel_00088bca_fill_pattern_2_5: 4590000 rects
+caravel_00088bca_fill_pattern_4_6: 1150000 rects
+caravel_00088bca_fill_pattern_2_5: 4600000 rects
+caravel_00088bca_fill_pattern_4_6: 1160000 rects
+caravel_00088bca_fill_pattern_4_6: 1170000 rects
+caravel_00088bca_fill_pattern_4_6: 1180000 rects
+caravel_00088bca_fill_pattern_2_5: 4610000 rects
+caravel_00088bca_fill_pattern_4_6: 1190000 rects
+caravel_00088bca_fill_pattern_4_6: 1200000 rects
+caravel_00088bca_fill_pattern_4_6: 1210000 rects
+caravel_00088bca_fill_pattern_4_6: 1220000 rects
+caravel_00088bca_fill_pattern_2_5: 4620000 rects
+caravel_00088bca_fill_pattern_4_6: 1230000 rects
+caravel_00088bca_fill_pattern_4_6: 1240000 rects
+caravel_00088bca_fill_pattern_2_5: 4630000 rects
+caravel_00088bca_fill_pattern_4_6: 1250000 rects
+caravel_00088bca_fill_pattern_4_6: 1260000 rects
+caravel_00088bca_fill_pattern_4_6: 1270000 rects
+caravel_00088bca_fill_pattern_2_5: 4640000 rects
+Ended: 12/04/2022 06:07:29
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_00088bca_fill_pattern_4_6: 1280000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_00088bca_fill_pattern_4_6: 1290000 rects
+caravel_00088bca_fill_pattern_2_5: 4650000 rects
+caravel_00088bca_fill_pattern_4_6: 1300000 rects
+caravel_00088bca_fill_pattern_4_6: 1310000 rects
+caravel_00088bca_fill_pattern_2_5: 4660000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_00088bca_fill_pattern_2_5: 4670000 rects
+caravel_00088bca_fill_pattern_1_1: 10000 rects
+caravel_00088bca_fill_pattern_1_1: 20000 rects
+caravel_00088bca_fill_pattern_1_1: 30000 rects
+caravel_00088bca_fill_pattern_1_1: 40000 rects
+caravel_00088bca_fill_pattern_1_1: 50000 rects
+caravel_00088bca_fill_pattern_2_5: 4680000 rects
+caravel_00088bca_fill_pattern_1_1: 60000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00088bca_fill_pattern_1_1: 70000 rects
+   Generating output for cell caravel_00088bca_fill_pattern_4_6
+caravel_00088bca_fill_pattern_1_1: 80000 rects
+caravel_00088bca_fill_pattern_1_1: 90000 rects
+caravel_00088bca_fill_pattern_1_1: 100000 rects
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+caravel_00088bca_fill_pattern_1_1: 140000 rects
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+caravel_00088bca_fill_pattern_1_1: 190000 rects
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+caravel_00088bca_fill_pattern_1_1: 200000 rects
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+caravel_00088bca_fill_pattern_2_5: 5250000 rects
+caravel_00088bca_fill_pattern_1_1: 1260000 rects
+Ended: 12/04/2022 06:07:35
+caravel_00088bca_fill_pattern_1_1: 1270000 rects
+caravel_00088bca_fill_pattern_2_5: 5260000 rects
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_00088bca_fill_pattern_1_1: 1280000 rects
+Processing system .magicrc file
+caravel_00088bca_fill_pattern_1_1: 1290000 rects
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_00088bca_fill_pattern_1_1: 1300000 rects
+caravel_00088bca_fill_pattern_2_5: 5270000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
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+caravel_00088bca_fill_pattern_2_5: 5280000 rects
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+caravel_00088bca_fill_pattern_1_1: 1400000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
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+Ended: 12/04/2022 06:07:44
+caravel_00088bca_fill_pattern_2_0: 1960000 rects
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
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+Processing system .magicrc file
+caravel_00088bca_fill_pattern_1_1: 2780000 rects
+caravel_00088bca_fill_pattern_2_0: 1980000 rects
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_00088bca_fill_pattern_2_0: 1990000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_00088bca_fill_pattern_2_5: 6110000 rects
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+caravel_00088bca_fill_pattern_1_1: 2790000 rects
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+caravel_00088bca_fill_pattern_2_0: 2050000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
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+caravel_00088bca_fill_pattern_0_2: 190000 rects
+caravel_00088bca_fill_pattern_2_0: 2180000 rects
+caravel_00088bca_fill_pattern_0_2: 200000 rects
+Ended: 12/04/2022 06:07:45
+caravel_00088bca_fill_pattern_1_1: 2850000 rects
+caravel_00088bca_fill_pattern_2_0: 2190000 rects
+caravel_00088bca_fill_pattern_0_2: 210000 rects
+caravel_00088bca_fill_pattern_0_2: 220000 rects
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_00088bca_fill_pattern_2_0: 2200000 rects
+caravel_00088bca_fill_pattern_2_5: 6170000 rects
+caravel_00088bca_fill_pattern_0_2: 230000 rects
+caravel_00088bca_fill_pattern_2_0: 2210000 rects
+Processing system .magicrc file
+caravel_00088bca_fill_pattern_0_2: 240000 rects
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_00088bca_fill_pattern_2_0: 2220000 rects
+caravel_00088bca_fill_pattern_0_2: 250000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
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+caravel_00088bca_fill_pattern_0_2: 260000 rects
+caravel_00088bca_fill_pattern_1_1: 2860000 rects
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+caravel_00088bca_fill_pattern_0_2: 270000 rects
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+caravel_00088bca_fill_pattern_2_0: 2250000 rects
+caravel_00088bca_fill_pattern_0_2: 280000 rects
+caravel_00088bca_fill_pattern_2_0: 2260000 rects
+caravel_00088bca_fill_pattern_0_2: 290000 rects
+caravel_00088bca_fill_pattern_2_0: 2270000 rects
+caravel_00088bca_fill_pattern_0_2: 300000 rects
+caravel_00088bca_fill_pattern_0_2: 310000 rects
+caravel_00088bca_fill_pattern_2_0: 2280000 rects
+caravel_00088bca_fill_pattern_1_1: 2870000 rects
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+caravel_00088bca_fill_pattern_0_2: 330000 rects
+caravel_00088bca_fill_pattern_2_0: 2300000 rects
+caravel_00088bca_fill_pattern_0_2: 340000 rects
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+caravel_00088bca_fill_pattern_2_0: 2310000 rects
+caravel_00088bca_fill_pattern_0_2: 360000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+caravel_00088bca_fill_pattern_2_0: 2320000 rects
+caravel_00088bca_fill_pattern_1_1: 2880000 rects
+caravel_00088bca_fill_pattern_0_2: 370000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
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+caravel_00088bca_fill_pattern_0_2: 380000 rects
+caravel_00088bca_fill_pattern_0_2: 390000 rects
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+caravel_00088bca_fill_pattern_2_0: 2340000 rects
+caravel_00088bca_fill_pattern_5_1: 20000 rects
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+caravel_00088bca_fill_pattern_2_0: 2550000 rects
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+caravel_00088bca_fill_pattern_5_1: 830000 rects
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+CIF output style is now "wafflefill(tiled)"
+caravel_00088bca_fill_pattern_5_1: 860000 rects
+   Generating output for cell caravel_00088bca_fill_pattern_2_5
+caravel_00088bca_fill_pattern_2_0: 2640000 rects
+caravel_00088bca_fill_pattern_0_2: 1270000 rects
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+caravel_00088bca_fill_pattern_5_1: 920000 rects
+caravel_00088bca_fill_pattern_0_2: 1300000 rects
+caravel_00088bca_fill_pattern_5_1: 930000 rects
+caravel_00088bca_fill_pattern_0_2: 1310000 rects
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+caravel_00088bca_fill_pattern_0_2: 1340000 rects
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+caravel_00088bca_fill_pattern_2_0: 2690000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00088bca_fill_pattern_0_2: 1380000 rects
+   Generating output for cell caravel_00088bca_fill_pattern_5_1
+caravel_00088bca_fill_pattern_1_1: 3150000 rects
+caravel_00088bca_fill_pattern_0_2: 1390000 rects
+caravel_00088bca_fill_pattern_0_2: 1400000 rects
+caravel_00088bca_fill_pattern_2_0: 2700000 rects
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+caravel_00088bca_fill_pattern_2_0: 2710000 rects
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+caravel_00088bca_fill_pattern_0_2: 2910000 rects
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+caravel_00088bca_fill_pattern_0_2: 2950000 rects
+caravel_00088bca_fill_pattern_0_2: 2960000 rects
+Ended: 12/04/2022 06:08:01
+caravel_00088bca_fill_pattern_1_1: 3760000 rects
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_00088bca_fill_pattern_0_2: 2970000 rects
+caravel_00088bca_fill_pattern_2_0: 3300000 rects
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_00088bca_fill_pattern_0_2: 2980000 rects
+caravel_00088bca_fill_pattern_0_2: 2990000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_00088bca_fill_pattern_0_2: 3000000 rects
+caravel_00088bca_fill_pattern_0_2: 3010000 rects
+caravel_00088bca_fill_pattern_1_1: 3770000 rects
+caravel_00088bca_fill_pattern_2_0: 3310000 rects
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+caravel_00088bca_fill_pattern_0_2: 3030000 rects
+caravel_00088bca_fill_pattern_1_1: 3780000 rects
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+caravel_00088bca_fill_pattern_2_0: 3320000 rects
+caravel_00088bca_fill_pattern_1_1: 3790000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+caravel_00088bca_fill_pattern_0_2: 3050000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_00088bca_fill_pattern_1_5: 10000 rects
+caravel_00088bca_fill_pattern_1_1: 3800000 rects
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+caravel_00088bca_fill_pattern_1_5: 20000 rects
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+caravel_00088bca_fill_pattern_1_5: 40000 rects
+caravel_00088bca_fill_pattern_1_5: 50000 rects
+caravel_00088bca_fill_pattern_1_5: 60000 rects
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+caravel_00088bca_fill_pattern_1_5: 70000 rects
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+caravel_00088bca_fill_pattern_1_5: 80000 rects
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+caravel_00088bca_fill_pattern_1_5: 90000 rects
+caravel_00088bca_fill_pattern_0_2: 3100000 rects
+caravel_00088bca_fill_pattern_1_5: 100000 rects
+caravel_00088bca_fill_pattern_0_2: 3110000 rects
+caravel_00088bca_fill_pattern_1_1: 3820000 rects
+caravel_00088bca_fill_pattern_1_5: 110000 rects
+caravel_00088bca_fill_pattern_0_2: 3120000 rects
+caravel_00088bca_fill_pattern_1_5: 120000 rects
+caravel_00088bca_fill_pattern_2_0: 3350000 rects
+caravel_00088bca_fill_pattern_1_5: 130000 rects
+caravel_00088bca_fill_pattern_1_5: 140000 rects
+caravel_00088bca_fill_pattern_1_5: 150000 rects
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+caravel_00088bca_fill_pattern_0_2: 3130000 rects
+caravel_00088bca_fill_pattern_1_5: 160000 rects
+caravel_00088bca_fill_pattern_1_5: 170000 rects
+caravel_00088bca_fill_pattern_2_0: 3360000 rects
+caravel_00088bca_fill_pattern_1_5: 180000 rects
+caravel_00088bca_fill_pattern_1_1: 3840000 rects
+caravel_00088bca_fill_pattern_1_5: 190000 rects
+caravel_00088bca_fill_pattern_1_5: 200000 rects
+caravel_00088bca_fill_pattern_2_0: 3370000 rects
+caravel_00088bca_fill_pattern_1_5: 210000 rects
+caravel_00088bca_fill_pattern_1_1: 3850000 rects
+caravel_00088bca_fill_pattern_1_5: 220000 rects
+caravel_00088bca_fill_pattern_1_5: 230000 rects
+caravel_00088bca_fill_pattern_1_5: 240000 rects
+caravel_00088bca_fill_pattern_1_5: 250000 rects
+caravel_00088bca_fill_pattern_1_1: 3860000 rects
+caravel_00088bca_fill_pattern_1_5: 260000 rects
+caravel_00088bca_fill_pattern_2_0: 3380000 rects
+caravel_00088bca_fill_pattern_1_5: 270000 rects
+caravel_00088bca_fill_pattern_1_5: 280000 rects
+caravel_00088bca_fill_pattern_1_5: 290000 rects
+caravel_00088bca_fill_pattern_1_1: 3870000 rects
+caravel_00088bca_fill_pattern_1_5: 300000 rects
+caravel_00088bca_fill_pattern_1_5: 310000 rects
+caravel_00088bca_fill_pattern_2_0: 3390000 rects
+caravel_00088bca_fill_pattern_1_5: 320000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00088bca_fill_pattern_1_5: 330000 rects
+   Generating output for cell caravel_00088bca_fill_pattern_0_2
+caravel_00088bca_fill_pattern_1_5: 340000 rects
+caravel_00088bca_fill_pattern_1_1: 3880000 rects
+caravel_00088bca_fill_pattern_1_5: 350000 rects
+caravel_00088bca_fill_pattern_1_5: 360000 rects
+caravel_00088bca_fill_pattern_2_0: 3400000 rects
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+caravel_00088bca_fill_pattern_1_5: 2600000 rects
+caravel_00088bca_fill_pattern_2_0: 4090000 rects
+caravel_00088bca_fill_pattern_1_1: 4540000 rects
+caravel_00088bca_fill_pattern_1_5: 2610000 rects
+caravel_00088bca_fill_pattern_2_0: 4100000 rects
+caravel_00088bca_fill_pattern_1_1: 4550000 rects
+caravel_00088bca_fill_pattern_1_5: 2620000 rects
+caravel_00088bca_fill_pattern_2_0: 4110000 rects
+caravel_00088bca_fill_pattern_1_1: 4560000 rects
+caravel_00088bca_fill_pattern_1_5: 2630000 rects
+caravel_00088bca_fill_pattern_2_0: 4120000 rects
+caravel_00088bca_fill_pattern_1_1: 4570000 rects
+caravel_00088bca_fill_pattern_2_0: 4130000 rects
+caravel_00088bca_fill_pattern_1_5: 2640000 rects
+caravel_00088bca_fill_pattern_1_1: 4580000 rects
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+caravel_00088bca_fill_pattern_1_5: 2650000 rects
+caravel_00088bca_fill_pattern_1_1: 4590000 rects
+caravel_00088bca_fill_pattern_2_0: 4150000 rects
+caravel_00088bca_fill_pattern_1_1: 4600000 rects
+caravel_00088bca_fill_pattern_1_5: 2660000 rects
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+caravel_00088bca_fill_pattern_1_1: 4610000 rects
+caravel_00088bca_fill_pattern_1_5: 2670000 rects
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+caravel_00088bca_fill_pattern_1_1: 4620000 rects
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+caravel_00088bca_fill_pattern_1_5: 2680000 rects
+caravel_00088bca_fill_pattern_1_1: 4630000 rects
+caravel_00088bca_fill_pattern_2_0: 4190000 rects
+caravel_00088bca_fill_pattern_1_1: 4640000 rects
+caravel_00088bca_fill_pattern_1_5: 2690000 rects
+caravel_00088bca_fill_pattern_2_0: 4200000 rects
+caravel_00088bca_fill_pattern_1_1: 4650000 rects
+caravel_00088bca_fill_pattern_1_5: 2700000 rects
+caravel_00088bca_fill_pattern_2_0: 4210000 rects
+caravel_00088bca_fill_pattern_1_1: 4660000 rects
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+caravel_00088bca_fill_pattern_2_0: 4220000 rects
+caravel_00088bca_fill_pattern_1_1: 4670000 rects
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+caravel_00088bca_fill_pattern_1_1: 4690000 rects
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+caravel_00088bca_fill_pattern_2_0: 4260000 rects
+caravel_00088bca_fill_pattern_1_5: 2750000 rects
+caravel_00088bca_fill_pattern_1_1: 4720000 rects
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+caravel_00088bca_fill_pattern_1_1: 4730000 rects
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+caravel_00088bca_fill_pattern_1_1: 4750000 rects
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+caravel_00088bca_fill_pattern_1_1: 4780000 rects
+caravel_00088bca_fill_pattern_2_0: 4310000 rects
+caravel_00088bca_fill_pattern_1_1: 4790000 rects
+caravel_00088bca_fill_pattern_1_5: 2790000 rects
+caravel_00088bca_fill_pattern_2_0: 4320000 rects
+caravel_00088bca_fill_pattern_1_1: 4800000 rects
+caravel_00088bca_fill_pattern_1_1: 4810000 rects
+caravel_00088bca_fill_pattern_2_0: 4330000 rects
+caravel_00088bca_fill_pattern_1_5: 2800000 rects
+caravel_00088bca_fill_pattern_1_1: 4820000 rects
+caravel_00088bca_fill_pattern_1_1: 4830000 rects
+caravel_00088bca_fill_pattern_2_0: 4340000 rects
+caravel_00088bca_fill_pattern_1_5: 2810000 rects
+caravel_00088bca_fill_pattern_2_0: 4350000 rects
+caravel_00088bca_fill_pattern_1_1: 4840000 rects
+caravel_00088bca_fill_pattern_2_0: 4360000 rects
+caravel_00088bca_fill_pattern_1_1: 4850000 rects
+caravel_00088bca_fill_pattern_2_0: 4370000 rects
+caravel_00088bca_fill_pattern_1_5: 2820000 rects
+caravel_00088bca_fill_pattern_2_0: 4380000 rects
+Ended: 12/04/2022 06:08:15
+caravel_00088bca_fill_pattern_1_1: 4860000 rects
+caravel_00088bca_fill_pattern_2_0: 4390000 rects
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_00088bca_fill_pattern_2_0: 4400000 rects
+caravel_00088bca_fill_pattern_1_5: 2830000 rects
+Processing system .magicrc file
+caravel_00088bca_fill_pattern_2_0: 4410000 rects
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_00088bca_fill_pattern_2_0: 4420000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_00088bca_fill_pattern_1_1: 4870000 rects
+caravel_00088bca_fill_pattern_2_0: 4430000 rects
+caravel_00088bca_fill_pattern_1_5: 2840000 rects
+caravel_00088bca_fill_pattern_2_0: 4440000 rects
+caravel_00088bca_fill_pattern_2_0: 4450000 rects
+caravel_00088bca_fill_pattern_1_1: 4880000 rects
+caravel_00088bca_fill_pattern_2_0: 4460000 rects
+caravel_00088bca_fill_pattern_1_5: 2850000 rects
+caravel_00088bca_fill_pattern_2_0: 4470000 rects
+caravel_00088bca_fill_pattern_2_0: 4480000 rects
+caravel_00088bca_fill_pattern_1_1: 4890000 rects
+caravel_00088bca_fill_pattern_2_0: 4490000 rects
+caravel_00088bca_fill_pattern_1_5: 2860000 rects
+caravel_00088bca_fill_pattern_2_0: 4500000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_00088bca_fill_pattern_2_0: 4510000 rects
+caravel_00088bca_fill_pattern_1_5: 2870000 rects
+caravel_00088bca_fill_pattern_2_0: 4520000 rects
+caravel_00088bca_fill_pattern_1_1: 4900000 rects
+caravel_00088bca_fill_pattern_3_3: 10000 rects
+caravel_00088bca_fill_pattern_3_3: 20000 rects
+caravel_00088bca_fill_pattern_3_3: 30000 rects
+caravel_00088bca_fill_pattern_2_0: 4530000 rects
+caravel_00088bca_fill_pattern_3_3: 40000 rects
+Ended: 12/04/2022 06:08:16
+caravel_00088bca_fill_pattern_1_5: 2880000 rects
+caravel_00088bca_fill_pattern_1_1: 4910000 rects
+caravel_00088bca_fill_pattern_3_3: 50000 rects
+caravel_00088bca_fill_pattern_3_3: 60000 rects
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_00088bca_fill_pattern_3_3: 70000 rects
+caravel_00088bca_fill_pattern_2_0: 4540000 rects
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_00088bca_fill_pattern_3_3: 80000 rects
+caravel_00088bca_fill_pattern_1_5: 2890000 rects
+caravel_00088bca_fill_pattern_3_3: 90000 rects
+caravel_00088bca_fill_pattern_1_1: 4920000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_00088bca_fill_pattern_3_3: 100000 rects
+caravel_00088bca_fill_pattern_2_0: 4550000 rects
+caravel_00088bca_fill_pattern_3_3: 110000 rects
+caravel_00088bca_fill_pattern_3_3: 120000 rects
+caravel_00088bca_fill_pattern_1_5: 2900000 rects
+caravel_00088bca_fill_pattern_1_1: 4930000 rects
+caravel_00088bca_fill_pattern_3_3: 130000 rects
+caravel_00088bca_fill_pattern_2_0: 4560000 rects
+caravel_00088bca_fill_pattern_3_3: 140000 rects
+caravel_00088bca_fill_pattern_3_3: 150000 rects
+caravel_00088bca_fill_pattern_1_1: 4940000 rects
+caravel_00088bca_fill_pattern_3_3: 160000 rects
+caravel_00088bca_fill_pattern_1_5: 2910000 rects
+caravel_00088bca_fill_pattern_2_0: 4570000 rects
+caravel_00088bca_fill_pattern_3_3: 170000 rects
+caravel_00088bca_fill_pattern_3_3: 180000 rects
+caravel_00088bca_fill_pattern_1_5: 2920000 rects
+caravel_00088bca_fill_pattern_1_1: 4950000 rects
+caravel_00088bca_fill_pattern_3_3: 190000 rects
+caravel_00088bca_fill_pattern_2_0: 4580000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_00088bca_fill_pattern_3_3: 200000 rects
+caravel_00088bca_fill_pattern_3_3: 210000 rects
+caravel_00088bca_fill_pattern_1_1: 4960000 rects
+caravel_00088bca_fill_pattern_1_5: 2930000 rects
+caravel_00088bca_fill_pattern_2_4: 10000 rects
+caravel_00088bca_fill_pattern_2_0: 4590000 rects
+caravel_00088bca_fill_pattern_3_3: 220000 rects
+caravel_00088bca_fill_pattern_2_4: 20000 rects
+caravel_00088bca_fill_pattern_3_3: 230000 rects
+caravel_00088bca_fill_pattern_2_4: 30000 rects
+caravel_00088bca_fill_pattern_3_3: 240000 rects
+caravel_00088bca_fill_pattern_1_1: 4970000 rects
+caravel_00088bca_fill_pattern_2_0: 4600000 rects
+caravel_00088bca_fill_pattern_2_4: 40000 rects
+caravel_00088bca_fill_pattern_1_5: 2940000 rects
+caravel_00088bca_fill_pattern_3_3: 250000 rects
+caravel_00088bca_fill_pattern_2_4: 50000 rects
+caravel_00088bca_fill_pattern_3_3: 260000 rects
+caravel_00088bca_fill_pattern_2_4: 60000 rects
+caravel_00088bca_fill_pattern_3_3: 270000 rects
+caravel_00088bca_fill_pattern_2_4: 70000 rects
+caravel_00088bca_fill_pattern_2_0: 4610000 rects
+caravel_00088bca_fill_pattern_1_5: 2950000 rects
+caravel_00088bca_fill_pattern_3_3: 280000 rects
+caravel_00088bca_fill_pattern_1_1: 4980000 rects
+caravel_00088bca_fill_pattern_2_4: 80000 rects
+caravel_00088bca_fill_pattern_3_3: 290000 rects
+caravel_00088bca_fill_pattern_2_4: 90000 rects
+caravel_00088bca_fill_pattern_3_3: 300000 rects
+caravel_00088bca_fill_pattern_2_4: 100000 rects
+caravel_00088bca_fill_pattern_2_0: 4620000 rects
+caravel_00088bca_fill_pattern_3_3: 310000 rects
+caravel_00088bca_fill_pattern_1_5: 2960000 rects
+caravel_00088bca_fill_pattern_2_4: 110000 rects
+caravel_00088bca_fill_pattern_1_1: 4990000 rects
+caravel_00088bca_fill_pattern_3_3: 320000 rects
+caravel_00088bca_fill_pattern_2_4: 120000 rects
+caravel_00088bca_fill_pattern_3_3: 330000 rects
+caravel_00088bca_fill_pattern_2_0: 4630000 rects
+caravel_00088bca_fill_pattern_2_4: 130000 rects
+caravel_00088bca_fill_pattern_3_3: 340000 rects
+caravel_00088bca_fill_pattern_1_5: 2970000 rects
+caravel_00088bca_fill_pattern_2_4: 140000 rects
+caravel_00088bca_fill_pattern_3_3: 350000 rects
+caravel_00088bca_fill_pattern_3_3: 360000 rects
+caravel_00088bca_fill_pattern_2_4: 150000 rects
+caravel_00088bca_fill_pattern_2_0: 4640000 rects
+caravel_00088bca_fill_pattern_3_3: 370000 rects
+caravel_00088bca_fill_pattern_2_4: 160000 rects
+caravel_00088bca_fill_pattern_1_5: 2980000 rects
+caravel_00088bca_fill_pattern_3_3: 380000 rects
+caravel_00088bca_fill_pattern_2_4: 170000 rects
+caravel_00088bca_fill_pattern_1_1: 5000000 rects
+caravel_00088bca_fill_pattern_3_3: 390000 rects
+caravel_00088bca_fill_pattern_2_4: 180000 rects
+caravel_00088bca_fill_pattern_2_0: 4650000 rects
+caravel_00088bca_fill_pattern_3_3: 400000 rects
+caravel_00088bca_fill_pattern_2_4: 190000 rects
+caravel_00088bca_fill_pattern_1_5: 2990000 rects
+caravel_00088bca_fill_pattern_3_3: 410000 rects
+caravel_00088bca_fill_pattern_2_4: 200000 rects
+caravel_00088bca_fill_pattern_3_3: 420000 rects
+caravel_00088bca_fill_pattern_1_1: 5010000 rects
+caravel_00088bca_fill_pattern_2_4: 210000 rects
+caravel_00088bca_fill_pattern_2_0: 4660000 rects
+caravel_00088bca_fill_pattern_3_3: 430000 rects
+caravel_00088bca_fill_pattern_2_4: 220000 rects
+caravel_00088bca_fill_pattern_3_3: 440000 rects
+caravel_00088bca_fill_pattern_1_5: 3000000 rects
+caravel_00088bca_fill_pattern_3_3: 450000 rects
+caravel_00088bca_fill_pattern_1_1: 5020000 rects
+caravel_00088bca_fill_pattern_2_4: 230000 rects
+caravel_00088bca_fill_pattern_2_0: 4670000 rects
+caravel_00088bca_fill_pattern_3_3: 460000 rects
+caravel_00088bca_fill_pattern_2_4: 240000 rects
+caravel_00088bca_fill_pattern_3_3: 470000 rects
+caravel_00088bca_fill_pattern_2_4: 250000 rects
+caravel_00088bca_fill_pattern_1_5: 3010000 rects
+caravel_00088bca_fill_pattern_1_1: 5030000 rects
+caravel_00088bca_fill_pattern_3_3: 480000 rects
+caravel_00088bca_fill_pattern_2_4: 260000 rects
+caravel_00088bca_fill_pattern_2_0: 4680000 rects
+caravel_00088bca_fill_pattern_3_3: 490000 rects
+caravel_00088bca_fill_pattern_2_4: 270000 rects
+caravel_00088bca_fill_pattern_3_3: 500000 rects
+caravel_00088bca_fill_pattern_3_3: 510000 rects
+caravel_00088bca_fill_pattern_1_5: 3020000 rects
+caravel_00088bca_fill_pattern_2_4: 280000 rects
+caravel_00088bca_fill_pattern_1_1: 5040000 rects
+caravel_00088bca_fill_pattern_2_0: 4690000 rects
+caravel_00088bca_fill_pattern_3_3: 520000 rects
+caravel_00088bca_fill_pattern_2_4: 290000 rects
+caravel_00088bca_fill_pattern_3_3: 530000 rects
+caravel_00088bca_fill_pattern_2_4: 300000 rects
+caravel_00088bca_fill_pattern_1_1: 5050000 rects
+caravel_00088bca_fill_pattern_3_3: 540000 rects
+caravel_00088bca_fill_pattern_1_5: 3030000 rects
+caravel_00088bca_fill_pattern_2_4: 310000 rects
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+caravel_00088bca_fill_pattern_3_3: 580000 rects
+caravel_00088bca_fill_pattern_2_0: 4710000 rects
+caravel_00088bca_fill_pattern_2_4: 340000 rects
+caravel_00088bca_fill_pattern_3_3: 590000 rects
+caravel_00088bca_fill_pattern_1_1: 5070000 rects
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+caravel_00088bca_fill_pattern_3_3: 600000 rects
+caravel_00088bca_fill_pattern_1_5: 3050000 rects
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+caravel_00088bca_fill_pattern_2_0: 4720000 rects
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+caravel_00088bca_fill_pattern_1_5: 3060000 rects
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+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00088bca_fill_pattern_1_1
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+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00088bca_fill_pattern_2_0
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+caravel_00088bca_fill_pattern_1_5: 4090000 rects
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+caravel_00088bca_fill_pattern_1_5: 5150000 rects
+caravel_00088bca_fill_pattern_2_4: 4150000 rects
+Ended: 12/04/2022 06:08:41
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+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
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+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
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+Input style sky130(vendor): scaleFactor=2, multiplier=2
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+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
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+caravel_00088bca_fill_pattern_0_6: 2380000 rects
+caravel_00088bca_fill_pattern_2_4: 4870000 rects
+caravel_00088bca_fill_pattern_0_6: 2390000 rects
+caravel_00088bca_fill_pattern_0_6: 2400000 rects
+caravel_00088bca_fill_pattern_2_4: 4880000 rects
+caravel_00088bca_fill_pattern_0_6: 2410000 rects
+caravel_00088bca_fill_pattern_0_6: 2420000 rects
+caravel_00088bca_fill_pattern_2_4: 4890000 rects
+caravel_00088bca_fill_pattern_0_6: 2430000 rects
+caravel_00088bca_fill_pattern_3_3: 5480000 rects
+caravel_00088bca_fill_pattern_2_4: 4900000 rects
+caravel_00088bca_fill_pattern_0_6: 2440000 rects
+caravel_00088bca_fill_pattern_0_6: 2450000 rects
+caravel_00088bca_fill_pattern_2_4: 4910000 rects
+caravel_00088bca_fill_pattern_0_6: 2460000 rects
+caravel_00088bca_fill_pattern_0_6: 2470000 rects
+caravel_00088bca_fill_pattern_2_4: 4920000 rects
+caravel_00088bca_fill_pattern_1_5: 5920000 rects
+caravel_00088bca_fill_pattern_0_6: 2480000 rects
+Ended: 12/04/2022 06:08:55
+caravel_00088bca_fill_pattern_0_6: 2490000 rects
+caravel_00088bca_fill_pattern_2_4: 4930000 rects
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_00088bca_fill_pattern_0_6: 2500000 rects
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_00088bca_fill_pattern_0_6: 2510000 rects
+caravel_00088bca_fill_pattern_2_4: 4940000 rects
+caravel_00088bca_fill_pattern_3_3: 5490000 rects
+caravel_00088bca_fill_pattern_0_6: 2520000 rects
+caravel_00088bca_fill_pattern_0_6: 2530000 rects
+caravel_00088bca_fill_pattern_2_4: 4950000 rects
+caravel_00088bca_fill_pattern_0_6: 2540000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+caravel_00088bca_fill_pattern_0_6: 2550000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_00088bca_fill_pattern_2_4: 4960000 rects
+caravel_00088bca_fill_pattern_4_2: 10000 rects
+caravel_00088bca_fill_pattern_0_6: 2560000 rects
+caravel_00088bca_fill_pattern_4_2: 20000 rects
+caravel_00088bca_fill_pattern_1_5: 5930000 rects
+caravel_00088bca_fill_pattern_4_2: 30000 rects
+caravel_00088bca_fill_pattern_4_2: 40000 rects
+caravel_00088bca_fill_pattern_0_6: 2570000 rects
+caravel_00088bca_fill_pattern_4_2: 50000 rects
+caravel_00088bca_fill_pattern_3_3: 5500000 rects
+caravel_00088bca_fill_pattern_4_2: 60000 rects
+caravel_00088bca_fill_pattern_2_4: 4970000 rects
+caravel_00088bca_fill_pattern_4_2: 70000 rects
+caravel_00088bca_fill_pattern_4_2: 80000 rects
+caravel_00088bca_fill_pattern_0_6: 2580000 rects
+caravel_00088bca_fill_pattern_4_2: 90000 rects
+caravel_00088bca_fill_pattern_4_2: 100000 rects
+caravel_00088bca_fill_pattern_4_2: 110000 rects
+caravel_00088bca_fill_pattern_4_2: 120000 rects
+caravel_00088bca_fill_pattern_0_6: 2590000 rects
+caravel_00088bca_fill_pattern_2_4: 4980000 rects
+caravel_00088bca_fill_pattern_4_2: 130000 rects
+caravel_00088bca_fill_pattern_4_2: 140000 rects
+caravel_00088bca_fill_pattern_4_2: 150000 rects
+caravel_00088bca_fill_pattern_4_2: 160000 rects
+caravel_00088bca_fill_pattern_0_6: 2600000 rects
+caravel_00088bca_fill_pattern_4_2: 170000 rects
+caravel_00088bca_fill_pattern_4_2: 180000 rects
+caravel_00088bca_fill_pattern_4_2: 190000 rects
+caravel_00088bca_fill_pattern_2_4: 4990000 rects
+caravel_00088bca_fill_pattern_0_6: 2610000 rects
+caravel_00088bca_fill_pattern_4_2: 200000 rects
+caravel_00088bca_fill_pattern_4_2: 210000 rects
+caravel_00088bca_fill_pattern_4_2: 220000 rects
+caravel_00088bca_fill_pattern_4_2: 230000 rects
+caravel_00088bca_fill_pattern_0_6: 2620000 rects
+caravel_00088bca_fill_pattern_4_2: 240000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00088bca_fill_pattern_2_4: 5000000 rects
+caravel_00088bca_fill_pattern_4_2: 250000 rects
+   Generating output for cell caravel_00088bca_fill_pattern_1_5
+caravel_00088bca_fill_pattern_4_2: 260000 rects
+caravel_00088bca_fill_pattern_0_6: 2630000 rects
+caravel_00088bca_fill_pattern_4_2: 270000 rects
+caravel_00088bca_fill_pattern_4_2: 280000 rects
+caravel_00088bca_fill_pattern_4_2: 290000 rects
+caravel_00088bca_fill_pattern_4_2: 300000 rects
+caravel_00088bca_fill_pattern_0_6: 2640000 rects
+caravel_00088bca_fill_pattern_2_4: 5010000 rects
+caravel_00088bca_fill_pattern_4_2: 310000 rects
+caravel_00088bca_fill_pattern_4_2: 320000 rects
+caravel_00088bca_fill_pattern_4_2: 330000 rects
+caravel_00088bca_fill_pattern_0_6: 2650000 rects
+caravel_00088bca_fill_pattern_4_2: 340000 rects
+caravel_00088bca_fill_pattern_4_2: 350000 rects
+caravel_00088bca_fill_pattern_2_4: 5020000 rects
+caravel_00088bca_fill_pattern_4_2: 360000 rects
+caravel_00088bca_fill_pattern_3_3: 5510000 rects
+caravel_00088bca_fill_pattern_0_6: 2660000 rects
+caravel_00088bca_fill_pattern_4_2: 370000 rects
+caravel_00088bca_fill_pattern_4_2: 380000 rects
+caravel_00088bca_fill_pattern_4_2: 390000 rects
+caravel_00088bca_fill_pattern_0_6: 2670000 rects
+caravel_00088bca_fill_pattern_4_2: 400000 rects
+caravel_00088bca_fill_pattern_2_4: 5030000 rects
+caravel_00088bca_fill_pattern_4_2: 410000 rects
+caravel_00088bca_fill_pattern_4_2: 420000 rects
+caravel_00088bca_fill_pattern_0_6: 2680000 rects
+caravel_00088bca_fill_pattern_4_2: 430000 rects
+caravel_00088bca_fill_pattern_4_2: 440000 rects
+caravel_00088bca_fill_pattern_4_2: 450000 rects
+caravel_00088bca_fill_pattern_0_6: 2690000 rects
+caravel_00088bca_fill_pattern_4_2: 460000 rects
+caravel_00088bca_fill_pattern_2_4: 5040000 rects
+caravel_00088bca_fill_pattern_4_2: 470000 rects
+caravel_00088bca_fill_pattern_0_6: 2700000 rects
+caravel_00088bca_fill_pattern_4_2: 480000 rects
+caravel_00088bca_fill_pattern_4_2: 490000 rects
+caravel_00088bca_fill_pattern_4_2: 500000 rects
+caravel_00088bca_fill_pattern_2_4: 5050000 rects
+caravel_00088bca_fill_pattern_0_6: 2710000 rects
+caravel_00088bca_fill_pattern_4_2: 510000 rects
+caravel_00088bca_fill_pattern_4_2: 520000 rects
+caravel_00088bca_fill_pattern_0_6: 2720000 rects
+caravel_00088bca_fill_pattern_4_2: 530000 rects
+caravel_00088bca_fill_pattern_4_2: 540000 rects
+caravel_00088bca_fill_pattern_2_4: 5060000 rects
+caravel_00088bca_fill_pattern_4_2: 550000 rects
+caravel_00088bca_fill_pattern_0_6: 2730000 rects
+caravel_00088bca_fill_pattern_4_2: 560000 rects
+caravel_00088bca_fill_pattern_4_2: 570000 rects
+caravel_00088bca_fill_pattern_4_2: 580000 rects
+caravel_00088bca_fill_pattern_0_6: 2740000 rects
+caravel_00088bca_fill_pattern_2_4: 5070000 rects
+caravel_00088bca_fill_pattern_4_2: 590000 rects
+caravel_00088bca_fill_pattern_4_2: 600000 rects
+caravel_00088bca_fill_pattern_0_6: 2750000 rects
+caravel_00088bca_fill_pattern_4_2: 610000 rects
+caravel_00088bca_fill_pattern_3_3: 5520000 rects
+caravel_00088bca_fill_pattern_4_2: 620000 rects
+caravel_00088bca_fill_pattern_4_2: 630000 rects
+caravel_00088bca_fill_pattern_2_4: 5080000 rects
+caravel_00088bca_fill_pattern_0_6: 2760000 rects
+caravel_00088bca_fill_pattern_4_2: 640000 rects
+caravel_00088bca_fill_pattern_4_2: 650000 rects
+caravel_00088bca_fill_pattern_4_2: 660000 rects
+caravel_00088bca_fill_pattern_0_6: 2770000 rects
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+caravel_00088bca_fill_pattern_2_4: 5090000 rects
+caravel_00088bca_fill_pattern_4_2: 680000 rects
+caravel_00088bca_fill_pattern_0_6: 2780000 rects
+caravel_00088bca_fill_pattern_4_2: 690000 rects
+caravel_00088bca_fill_pattern_4_2: 700000 rects
+caravel_00088bca_fill_pattern_4_2: 710000 rects
+caravel_00088bca_fill_pattern_0_6: 2790000 rects
+caravel_00088bca_fill_pattern_2_4: 5100000 rects
+caravel_00088bca_fill_pattern_4_2: 720000 rects
+caravel_00088bca_fill_pattern_4_2: 730000 rects
+caravel_00088bca_fill_pattern_4_2: 740000 rects
+caravel_00088bca_fill_pattern_0_6: 2800000 rects
+caravel_00088bca_fill_pattern_4_2: 750000 rects
+caravel_00088bca_fill_pattern_2_4: 5110000 rects
+caravel_00088bca_fill_pattern_0_6: 2810000 rects
+caravel_00088bca_fill_pattern_4_2: 760000 rects
+caravel_00088bca_fill_pattern_0_6: 2820000 rects
+caravel_00088bca_fill_pattern_2_4: 5120000 rects
+caravel_00088bca_fill_pattern_4_2: 770000 rects
+caravel_00088bca_fill_pattern_0_6: 2830000 rects
+caravel_00088bca_fill_pattern_4_2: 780000 rects
+caravel_00088bca_fill_pattern_2_4: 5130000 rects
+caravel_00088bca_fill_pattern_0_6: 2840000 rects
+caravel_00088bca_fill_pattern_4_2: 790000 rects
+Ended: 12/04/2022 06:08:59
+caravel_00088bca_fill_pattern_0_6: 2850000 rects
+caravel_00088bca_fill_pattern_4_2: 800000 rects
+caravel_00088bca_fill_pattern_2_4: 5140000 rects
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_00088bca_fill_pattern_0_6: 2860000 rects
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_00088bca_fill_pattern_4_2: 810000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_00088bca_fill_pattern_0_6: 2870000 rects
+caravel_00088bca_fill_pattern_2_4: 5150000 rects
+caravel_00088bca_fill_pattern_4_2: 820000 rects
+caravel_00088bca_fill_pattern_0_6: 2880000 rects
+caravel_00088bca_fill_pattern_4_2: 830000 rects
+caravel_00088bca_fill_pattern_0_6: 2890000 rects
+caravel_00088bca_fill_pattern_2_4: 5160000 rects
+caravel_00088bca_fill_pattern_0_6: 2900000 rects
+caravel_00088bca_fill_pattern_0_6: 2910000 rects
+caravel_00088bca_fill_pattern_4_2: 840000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_00088bca_fill_pattern_0_6: 2920000 rects
+caravel_00088bca_fill_pattern_3_3: 5530000 rects
+caravel_00088bca_fill_pattern_0_6: 2930000 rects
+caravel_00088bca_fill_pattern_0_6: 2940000 rects
+caravel_00088bca_fill_pattern_2_4: 5170000 rects
+caravel_00088bca_fill_pattern_4_2: 850000 rects
+caravel_00088bca_fill_pattern_0_6: 2950000 rects
+caravel_00088bca_fill_pattern_3_3: 5540000 rects
+caravel_00088bca_fill_pattern_0_6: 2960000 rects
+caravel_00088bca_fill_pattern_0_6: 2970000 rects
+caravel_00088bca_fill_pattern_4_2: 860000 rects
+caravel_00088bca_fill_pattern_0_6: 2980000 rects
+caravel_00088bca_fill_pattern_2_4: 5180000 rects
+caravel_00088bca_fill_pattern_3_3: 5550000 rects
+caravel_00088bca_fill_pattern_0_6: 2990000 rects
+caravel_00088bca_fill_pattern_4_2: 870000 rects
+caravel_00088bca_fill_pattern_0_6: 3000000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00088bca_fill_pattern_5_7
+caravel_00088bca_fill_pattern_0_6: 3010000 rects
+caravel_00088bca_fill_pattern_4_2: 880000 rects
+caravel_00088bca_fill_pattern_3_3: 5560000 rects
+caravel_00088bca_fill_pattern_2_4: 5190000 rects
+caravel_00088bca_fill_pattern_0_6: 3020000 rects
+caravel_00088bca_fill_pattern_0_6: 3030000 rects
+caravel_00088bca_fill_pattern_0_6: 3040000 rects
+caravel_00088bca_fill_pattern_4_2: 890000 rects
+caravel_00088bca_fill_pattern_3_3: 5570000 rects
+caravel_00088bca_fill_pattern_0_6: 3050000 rects
+caravel_00088bca_fill_pattern_0_6: 3060000 rects
+caravel_00088bca_fill_pattern_2_4: 5200000 rects
+caravel_00088bca_fill_pattern_4_2: 900000 rects
+caravel_00088bca_fill_pattern_0_6: 3070000 rects
+caravel_00088bca_fill_pattern_3_3: 5580000 rects
+caravel_00088bca_fill_pattern_0_6: 3080000 rects
+caravel_00088bca_fill_pattern_4_2: 910000 rects
+caravel_00088bca_fill_pattern_0_6: 3090000 rects
+caravel_00088bca_fill_pattern_3_3: 5590000 rects
+caravel_00088bca_fill_pattern_2_4: 5210000 rects
+caravel_00088bca_fill_pattern_0_6: 3100000 rects
+caravel_00088bca_fill_pattern_4_2: 920000 rects
+caravel_00088bca_fill_pattern_0_6: 3110000 rects
+caravel_00088bca_fill_pattern_0_6: 3120000 rects
+caravel_00088bca_fill_pattern_3_3: 5600000 rects
+caravel_00088bca_fill_pattern_0_6: 3130000 rects
+caravel_00088bca_fill_pattern_4_2: 930000 rects
+caravel_00088bca_fill_pattern_2_4: 5220000 rects
+caravel_00088bca_fill_pattern_0_6: 3140000 rects
+caravel_00088bca_fill_pattern_0_6: 3150000 rects
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+caravel_00088bca_fill_pattern_0_6: 3160000 rects
+caravel_00088bca_fill_pattern_4_2: 940000 rects
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+caravel_00088bca_fill_pattern_3_3: 5620000 rects
+caravel_00088bca_fill_pattern_2_4: 5230000 rects
+caravel_00088bca_fill_pattern_3_3: 5630000 rects
+caravel_00088bca_fill_pattern_0_6: 3180000 rects
+caravel_00088bca_fill_pattern_3_3: 5640000 rects
+caravel_00088bca_fill_pattern_4_2: 950000 rects
+caravel_00088bca_fill_pattern_3_3: 5650000 rects
+caravel_00088bca_fill_pattern_0_6: 3190000 rects
+caravel_00088bca_fill_pattern_3_3: 5660000 rects
+caravel_00088bca_fill_pattern_3_3: 5670000 rects
+caravel_00088bca_fill_pattern_0_6: 3200000 rects
+caravel_00088bca_fill_pattern_3_3: 5680000 rects
+caravel_00088bca_fill_pattern_4_2: 960000 rects
+caravel_00088bca_fill_pattern_2_4: 5240000 rects
+caravel_00088bca_fill_pattern_0_6: 3210000 rects
+caravel_00088bca_fill_pattern_3_3: 5690000 rects
+caravel_00088bca_fill_pattern_3_3: 5700000 rects
+caravel_00088bca_fill_pattern_0_6: 3220000 rects
+caravel_00088bca_fill_pattern_3_3: 5710000 rects
+caravel_00088bca_fill_pattern_3_3: 5720000 rects
+caravel_00088bca_fill_pattern_4_2: 970000 rects
+caravel_00088bca_fill_pattern_0_6: 3230000 rects
+caravel_00088bca_fill_pattern_3_3: 5730000 rects
+caravel_00088bca_fill_pattern_0_6: 3240000 rects
+caravel_00088bca_fill_pattern_2_4: 5250000 rects
+caravel_00088bca_fill_pattern_0_6: 3250000 rects
+caravel_00088bca_fill_pattern_4_2: 980000 rects
+caravel_00088bca_fill_pattern_3_3: 5740000 rects
+caravel_00088bca_fill_pattern_0_6: 3260000 rects
+Ended: 12/04/2022 06:09:01
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_00088bca_fill_pattern_0_6: 3270000 rects
+Processing system .magicrc file
+caravel_00088bca_fill_pattern_3_3: 5750000 rects
+caravel_00088bca_fill_pattern_4_2: 990000 rects
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_00088bca_fill_pattern_0_6: 3280000 rects
+caravel_00088bca_fill_pattern_2_4: 5260000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_00088bca_fill_pattern_0_6: 3290000 rects
+caravel_00088bca_fill_pattern_3_3: 5760000 rects
+caravel_00088bca_fill_pattern_4_2: 1000000 rects
+caravel_00088bca_fill_pattern_0_6: 3300000 rects
+caravel_00088bca_fill_pattern_3_3: 5770000 rects
+caravel_00088bca_fill_pattern_2_4: 5270000 rects
+caravel_00088bca_fill_pattern_4_2: 1010000 rects
+caravel_00088bca_fill_pattern_0_6: 3310000 rects
+caravel_00088bca_fill_pattern_3_3: 5780000 rects
+caravel_00088bca_fill_pattern_0_6: 3320000 rects
+caravel_00088bca_fill_pattern_4_2: 1020000 rects
+caravel_00088bca_fill_pattern_0_6: 3330000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+caravel_00088bca_fill_pattern_3_3: 5790000 rects
+caravel_00088bca_fill_pattern_2_4: 5280000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_00088bca_fill_pattern_4_2: 1030000 rects
+caravel_00088bca_fill_pattern_0_6: 3340000 rects
+caravel_00088bca_fill_pattern_1_3: 10000 rects
+caravel_00088bca_fill_pattern_0_6: 3350000 rects
+caravel_00088bca_fill_pattern_3_3: 5800000 rects
+caravel_00088bca_fill_pattern_4_2: 1040000 rects
+caravel_00088bca_fill_pattern_1_3: 20000 rects
+caravel_00088bca_fill_pattern_3_3: 5810000 rects
+caravel_00088bca_fill_pattern_0_6: 3360000 rects
+caravel_00088bca_fill_pattern_2_4: 5290000 rects
+caravel_00088bca_fill_pattern_3_3: 5820000 rects
+caravel_00088bca_fill_pattern_1_3: 30000 rects
+caravel_00088bca_fill_pattern_3_3: 5830000 rects
+caravel_00088bca_fill_pattern_0_6: 3370000 rects
+caravel_00088bca_fill_pattern_4_2: 1050000 rects
+caravel_00088bca_fill_pattern_3_3: 5840000 rects
+caravel_00088bca_fill_pattern_1_3: 40000 rects
+caravel_00088bca_fill_pattern_3_3: 5850000 rects
+caravel_00088bca_fill_pattern_1_3: 50000 rects
+caravel_00088bca_fill_pattern_0_6: 3380000 rects
+caravel_00088bca_fill_pattern_3_3: 5860000 rects
+caravel_00088bca_fill_pattern_1_3: 60000 rects
+caravel_00088bca_fill_pattern_3_3: 5870000 rects
+caravel_00088bca_fill_pattern_4_2: 1060000 rects
+caravel_00088bca_fill_pattern_1_3: 70000 rects
+caravel_00088bca_fill_pattern_0_6: 3390000 rects
+caravel_00088bca_fill_pattern_3_3: 5880000 rects
+caravel_00088bca_fill_pattern_1_3: 80000 rects
+caravel_00088bca_fill_pattern_2_4: 5300000 rects
+caravel_00088bca_fill_pattern_3_3: 5890000 rects
+caravel_00088bca_fill_pattern_1_3: 90000 rects
+caravel_00088bca_fill_pattern_3_3: 5900000 rects
+caravel_00088bca_fill_pattern_4_2: 1070000 rects
+caravel_00088bca_fill_pattern_1_3: 100000 rects
+caravel_00088bca_fill_pattern_1_3: 110000 rects
+caravel_00088bca_fill_pattern_1_3: 120000 rects
+caravel_00088bca_fill_pattern_4_2: 1080000 rects
+caravel_00088bca_fill_pattern_2_4: 5310000 rects
+caravel_00088bca_fill_pattern_1_3: 130000 rects
+caravel_00088bca_fill_pattern_1_3: 140000 rects
+caravel_00088bca_fill_pattern_4_2: 1090000 rects
+caravel_00088bca_fill_pattern_1_3: 150000 rects
+caravel_00088bca_fill_pattern_0_6: 3400000 rects
+caravel_00088bca_fill_pattern_1_3: 160000 rects
+caravel_00088bca_fill_pattern_4_2: 1100000 rects
+caravel_00088bca_fill_pattern_2_4: 5320000 rects
+caravel_00088bca_fill_pattern_1_3: 170000 rects
+caravel_00088bca_fill_pattern_0_6: 3410000 rects
+caravel_00088bca_fill_pattern_1_3: 180000 rects
+caravel_00088bca_fill_pattern_1_3: 190000 rects
+caravel_00088bca_fill_pattern_0_6: 3420000 rects
+caravel_00088bca_fill_pattern_4_2: 1110000 rects
+caravel_00088bca_fill_pattern_1_3: 200000 rects
+caravel_00088bca_fill_pattern_0_6: 3430000 rects
+caravel_00088bca_fill_pattern_3_3: 5910000 rects
+caravel_00088bca_fill_pattern_1_3: 210000 rects
+caravel_00088bca_fill_pattern_4_2: 1120000 rects
+caravel_00088bca_fill_pattern_2_4: 5330000 rects
+caravel_00088bca_fill_pattern_1_3: 220000 rects
+caravel_00088bca_fill_pattern_0_6: 3440000 rects
+caravel_00088bca_fill_pattern_4_2: 1130000 rects
+caravel_00088bca_fill_pattern_1_3: 230000 rects
+caravel_00088bca_fill_pattern_0_6: 3450000 rects
+caravel_00088bca_fill_pattern_1_3: 240000 rects
+caravel_00088bca_fill_pattern_1_3: 250000 rects
+caravel_00088bca_fill_pattern_4_2: 1140000 rects
+caravel_00088bca_fill_pattern_0_6: 3460000 rects
+caravel_00088bca_fill_pattern_2_4: 5340000 rects
+caravel_00088bca_fill_pattern_1_3: 260000 rects
+caravel_00088bca_fill_pattern_4_2: 1150000 rects
+caravel_00088bca_fill_pattern_0_6: 3470000 rects
+caravel_00088bca_fill_pattern_1_3: 270000 rects
+caravel_00088bca_fill_pattern_4_2: 1160000 rects
+caravel_00088bca_fill_pattern_1_3: 280000 rects
+caravel_00088bca_fill_pattern_0_6: 3480000 rects
+caravel_00088bca_fill_pattern_1_3: 290000 rects
+caravel_00088bca_fill_pattern_4_2: 1170000 rects
+caravel_00088bca_fill_pattern_0_6: 3490000 rects
+caravel_00088bca_fill_pattern_2_4: 5350000 rects
+caravel_00088bca_fill_pattern_1_3: 300000 rects
+caravel_00088bca_fill_pattern_4_2: 1180000 rects
+caravel_00088bca_fill_pattern_0_6: 3500000 rects
+caravel_00088bca_fill_pattern_1_3: 310000 rects
+caravel_00088bca_fill_pattern_1_3: 320000 rects
+caravel_00088bca_fill_pattern_4_2: 1190000 rects
+caravel_00088bca_fill_pattern_0_6: 3510000 rects
+caravel_00088bca_fill_pattern_1_3: 330000 rects
+caravel_00088bca_fill_pattern_2_4: 5360000 rects
+caravel_00088bca_fill_pattern_0_6: 3520000 rects
+caravel_00088bca_fill_pattern_4_2: 1200000 rects
+caravel_00088bca_fill_pattern_1_3: 340000 rects
+caravel_00088bca_fill_pattern_1_3: 350000 rects
+caravel_00088bca_fill_pattern_0_6: 3530000 rects
+caravel_00088bca_fill_pattern_4_2: 1210000 rects
+caravel_00088bca_fill_pattern_1_3: 360000 rects
+caravel_00088bca_fill_pattern_1_3: 370000 rects
+caravel_00088bca_fill_pattern_0_6: 3540000 rects
+caravel_00088bca_fill_pattern_4_2: 1220000 rects
+caravel_00088bca_fill_pattern_1_3: 380000 rects
+caravel_00088bca_fill_pattern_2_4: 5370000 rects
+caravel_00088bca_fill_pattern_1_3: 390000 rects
+caravel_00088bca_fill_pattern_4_2: 1230000 rects
+caravel_00088bca_fill_pattern_0_6: 3550000 rects
+caravel_00088bca_fill_pattern_1_3: 400000 rects
+caravel_00088bca_fill_pattern_4_2: 1240000 rects
+caravel_00088bca_fill_pattern_1_3: 410000 rects
+caravel_00088bca_fill_pattern_0_6: 3560000 rects
+caravel_00088bca_fill_pattern_4_2: 1250000 rects
+caravel_00088bca_fill_pattern_1_3: 420000 rects
+caravel_00088bca_fill_pattern_2_4: 5380000 rects
+caravel_00088bca_fill_pattern_4_2: 1260000 rects
+caravel_00088bca_fill_pattern_0_6: 3570000 rects
+caravel_00088bca_fill_pattern_1_3: 430000 rects
+caravel_00088bca_fill_pattern_4_2: 1270000 rects
+caravel_00088bca_fill_pattern_1_3: 440000 rects
+caravel_00088bca_fill_pattern_0_6: 3580000 rects
+caravel_00088bca_fill_pattern_1_3: 450000 rects
+caravel_00088bca_fill_pattern_4_2: 1280000 rects
+caravel_00088bca_fill_pattern_1_3: 460000 rects
+caravel_00088bca_fill_pattern_0_6: 3590000 rects
+caravel_00088bca_fill_pattern_4_2: 1290000 rects
+caravel_00088bca_fill_pattern_2_4: 5390000 rects
+caravel_00088bca_fill_pattern_4_2: 1300000 rects
+caravel_00088bca_fill_pattern_1_3: 470000 rects
+caravel_00088bca_fill_pattern_0_6: 3600000 rects
+caravel_00088bca_fill_pattern_4_2: 1310000 rects
+caravel_00088bca_fill_pattern_1_3: 480000 rects
+caravel_00088bca_fill_pattern_0_6: 3610000 rects
+caravel_00088bca_fill_pattern_1_3: 490000 rects
+caravel_00088bca_fill_pattern_4_2: 1320000 rects
+caravel_00088bca_fill_pattern_1_3: 500000 rects
+caravel_00088bca_fill_pattern_4_2: 1330000 rects
+caravel_00088bca_fill_pattern_2_4: 5400000 rects
+caravel_00088bca_fill_pattern_0_6: 3620000 rects
+caravel_00088bca_fill_pattern_1_3: 510000 rects
+caravel_00088bca_fill_pattern_4_2: 1340000 rects
+caravel_00088bca_fill_pattern_1_3: 520000 rects
+caravel_00088bca_fill_pattern_4_2: 1350000 rects
+caravel_00088bca_fill_pattern_4_2: 1360000 rects
+caravel_00088bca_fill_pattern_1_3: 530000 rects
+caravel_00088bca_fill_pattern_0_6: 3630000 rects
+caravel_00088bca_fill_pattern_3_3: 5920000 rects
+caravel_00088bca_fill_pattern_4_2: 1370000 rects
+caravel_00088bca_fill_pattern_1_3: 540000 rects
+caravel_00088bca_fill_pattern_2_4: 5410000 rects
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+caravel_00088bca_fill_pattern_1_3: 550000 rects
+caravel_00088bca_fill_pattern_0_6: 3640000 rects
+caravel_00088bca_fill_pattern_1_3: 560000 rects
+caravel_00088bca_fill_pattern_4_2: 1390000 rects
+caravel_00088bca_fill_pattern_0_6: 3650000 rects
+caravel_00088bca_fill_pattern_1_3: 570000 rects
+caravel_00088bca_fill_pattern_4_2: 1400000 rects
+caravel_00088bca_fill_pattern_1_3: 580000 rects
+caravel_00088bca_fill_pattern_2_4: 5420000 rects
+caravel_00088bca_fill_pattern_0_6: 3660000 rects
+caravel_00088bca_fill_pattern_1_3: 590000 rects
+caravel_00088bca_fill_pattern_4_2: 1410000 rects
+caravel_00088bca_fill_pattern_1_3: 600000 rects
+caravel_00088bca_fill_pattern_0_6: 3670000 rects
+caravel_00088bca_fill_pattern_4_2: 1420000 rects
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+caravel_00088bca_fill_pattern_1_3: 620000 rects
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+caravel_00088bca_fill_pattern_1_3: 690000 rects
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+caravel_00088bca_fill_pattern_2_4: 5450000 rects
+caravel_00088bca_fill_pattern_1_3: 710000 rects
+caravel_00088bca_fill_pattern_0_6: 3740000 rects
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+caravel_00088bca_fill_pattern_1_3: 740000 rects
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+caravel_00088bca_fill_pattern_1_3: 780000 rects
+caravel_00088bca_fill_pattern_0_6: 3790000 rects
+caravel_00088bca_fill_pattern_2_4: 5470000 rects
+caravel_00088bca_fill_pattern_1_3: 790000 rects
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+caravel_00088bca_fill_pattern_1_3: 800000 rects
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+caravel_00088bca_fill_pattern_0_6: 3840000 rects
+caravel_00088bca_fill_pattern_0_6: 3850000 rects
+caravel_00088bca_fill_pattern_1_3: 830000 rects
+caravel_00088bca_fill_pattern_3_3: 5930000 rects
+caravel_00088bca_fill_pattern_2_4: 5480000 rects
+caravel_00088bca_fill_pattern_0_6: 3860000 rects
+caravel_00088bca_fill_pattern_1_3: 840000 rects
+caravel_00088bca_fill_pattern_0_6: 3870000 rects
+caravel_00088bca_fill_pattern_1_3: 850000 rects
+caravel_00088bca_fill_pattern_0_6: 3880000 rects
+caravel_00088bca_fill_pattern_1_3: 860000 rects
+caravel_00088bca_fill_pattern_0_6: 3890000 rects
+caravel_00088bca_fill_pattern_0_6: 3900000 rects
+caravel_00088bca_fill_pattern_1_3: 870000 rects
+caravel_00088bca_fill_pattern_2_4: 5490000 rects
+caravel_00088bca_fill_pattern_0_6: 3910000 rects
+caravel_00088bca_fill_pattern_1_3: 880000 rects
+caravel_00088bca_fill_pattern_0_6: 3920000 rects
+caravel_00088bca_fill_pattern_0_6: 3930000 rects
+caravel_00088bca_fill_pattern_1_3: 890000 rects
+caravel_00088bca_fill_pattern_3_3: 5940000 rects
+caravel_00088bca_fill_pattern_0_6: 3940000 rects
+caravel_00088bca_fill_pattern_1_3: 900000 rects
+caravel_00088bca_fill_pattern_0_6: 3950000 rects
+caravel_00088bca_fill_pattern_1_3: 910000 rects
+Ended: 12/04/2022 06:09:06
+caravel_00088bca_fill_pattern_0_6: 3960000 rects
+caravel_00088bca_fill_pattern_2_4: 5500000 rects
+caravel_00088bca_fill_pattern_0_6: 3970000 rects
+caravel_00088bca_fill_pattern_1_3: 920000 rects
+caravel_00088bca_fill_pattern_0_6: 3980000 rects
+caravel_00088bca_fill_pattern_1_3: 930000 rects
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_00088bca_fill_pattern_1_3: 940000 rects
+caravel_00088bca_fill_pattern_0_6: 3990000 rects
+caravel_00088bca_fill_pattern_1_3: 950000 rects
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_00088bca_fill_pattern_0_6: 4000000 rects
+caravel_00088bca_fill_pattern_1_3: 960000 rects
+caravel_00088bca_fill_pattern_1_3: 970000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_00088bca_fill_pattern_2_4: 5510000 rects
+caravel_00088bca_fill_pattern_1_3: 980000 rects
+caravel_00088bca_fill_pattern_0_6: 4010000 rects
+caravel_00088bca_fill_pattern_1_3: 990000 rects
+caravel_00088bca_fill_pattern_1_3: 1000000 rects
+caravel_00088bca_fill_pattern_1_3: 1010000 rects
+caravel_00088bca_fill_pattern_1_3: 1020000 rects
+caravel_00088bca_fill_pattern_0_6: 4020000 rects
+caravel_00088bca_fill_pattern_1_3: 1030000 rects
+caravel_00088bca_fill_pattern_2_4: 5520000 rects
+caravel_00088bca_fill_pattern_1_3: 1040000 rects
+caravel_00088bca_fill_pattern_0_6: 4030000 rects
+caravel_00088bca_fill_pattern_1_3: 1050000 rects
+caravel_00088bca_fill_pattern_4_2: 1520000 rects
+caravel_00088bca_fill_pattern_1_3: 1060000 rects
+caravel_00088bca_fill_pattern_0_6: 4040000 rects
+caravel_00088bca_fill_pattern_1_3: 1070000 rects
+caravel_00088bca_fill_pattern_4_2: 1530000 rects
+caravel_00088bca_fill_pattern_1_3: 1080000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00088bca_fill_pattern_3_3
+caravel_00088bca_fill_pattern_1_3: 1090000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+caravel_00088bca_fill_pattern_0_6: 4050000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_00088bca_fill_pattern_2_4: 5530000 rects
+caravel_00088bca_fill_pattern_1_3: 1100000 rects
+caravel_00088bca_fill_pattern_4_2: 1540000 rects
+caravel_00088bca_fill_pattern_0_6: 4060000 rects
+caravel_00088bca_fill_pattern_1_3: 1110000 rects
+caravel_00088bca_fill_pattern_1_3: 1120000 rects
+caravel_00088bca_fill_pattern_4_2: 1550000 rects
+caravel_00088bca_fill_pattern_3_1: 10000 rects
+caravel_00088bca_fill_pattern_1_3: 1130000 rects
+caravel_00088bca_fill_pattern_3_1: 20000 rects
+caravel_00088bca_fill_pattern_1_3: 1140000 rects
+caravel_00088bca_fill_pattern_4_2: 1560000 rects
+caravel_00088bca_fill_pattern_3_1: 30000 rects
+caravel_00088bca_fill_pattern_1_3: 1150000 rects
+caravel_00088bca_fill_pattern_3_1: 40000 rects
+caravel_00088bca_fill_pattern_1_3: 1160000 rects
+caravel_00088bca_fill_pattern_2_4: 5540000 rects
+caravel_00088bca_fill_pattern_3_1: 50000 rects
+caravel_00088bca_fill_pattern_4_2: 1570000 rects
+caravel_00088bca_fill_pattern_1_3: 1170000 rects
+caravel_00088bca_fill_pattern_3_1: 60000 rects
+caravel_00088bca_fill_pattern_1_3: 1180000 rects
+caravel_00088bca_fill_pattern_3_1: 70000 rects
+caravel_00088bca_fill_pattern_1_3: 1190000 rects
+caravel_00088bca_fill_pattern_3_1: 80000 rects
+caravel_00088bca_fill_pattern_4_2: 1580000 rects
+caravel_00088bca_fill_pattern_1_3: 1200000 rects
+caravel_00088bca_fill_pattern_3_1: 90000 rects
+caravel_00088bca_fill_pattern_1_3: 1210000 rects
+caravel_00088bca_fill_pattern_3_1: 100000 rects
+caravel_00088bca_fill_pattern_4_2: 1590000 rects
+caravel_00088bca_fill_pattern_1_3: 1220000 rects
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+caravel_00088bca_fill_pattern_3_1: 110000 rects
+caravel_00088bca_fill_pattern_1_3: 1230000 rects
+caravel_00088bca_fill_pattern_4_2: 1600000 rects
+caravel_00088bca_fill_pattern_1_3: 1240000 rects
+caravel_00088bca_fill_pattern_3_1: 120000 rects
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+caravel_00088bca_fill_pattern_1_3: 1250000 rects
+caravel_00088bca_fill_pattern_3_1: 130000 rects
+caravel_00088bca_fill_pattern_4_2: 1610000 rects
+caravel_00088bca_fill_pattern_3_1: 140000 rects
+caravel_00088bca_fill_pattern_1_3: 1260000 rects
+caravel_00088bca_fill_pattern_3_1: 150000 rects
+caravel_00088bca_fill_pattern_2_4: 5560000 rects
+caravel_00088bca_fill_pattern_4_2: 1620000 rects
+caravel_00088bca_fill_pattern_1_3: 1270000 rects
+caravel_00088bca_fill_pattern_3_1: 160000 rects
+caravel_00088bca_fill_pattern_1_3: 1280000 rects
+caravel_00088bca_fill_pattern_0_6: 4080000 rects
+caravel_00088bca_fill_pattern_3_1: 170000 rects
+caravel_00088bca_fill_pattern_4_2: 1630000 rects
+caravel_00088bca_fill_pattern_1_3: 1290000 rects
+caravel_00088bca_fill_pattern_4_2: 1640000 rects
+caravel_00088bca_fill_pattern_3_1: 180000 rects
+caravel_00088bca_fill_pattern_1_3: 1300000 rects
+caravel_00088bca_fill_pattern_2_4: 5570000 rects
+caravel_00088bca_fill_pattern_3_1: 190000 rects
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+caravel_00088bca_fill_pattern_3_1: 200000 rects
+caravel_00088bca_fill_pattern_4_2: 1670000 rects
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+caravel_00088bca_fill_pattern_1_3: 1330000 rects
+caravel_00088bca_fill_pattern_3_1: 220000 rects
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+caravel_00088bca_fill_pattern_4_2: 1700000 rects
+caravel_00088bca_fill_pattern_2_4: 5580000 rects
+caravel_00088bca_fill_pattern_3_1: 230000 rects
+caravel_00088bca_fill_pattern_1_3: 1340000 rects
+caravel_00088bca_fill_pattern_4_2: 1710000 rects
+caravel_00088bca_fill_pattern_0_6: 4100000 rects
+caravel_00088bca_fill_pattern_4_2: 1720000 rects
+caravel_00088bca_fill_pattern_3_1: 240000 rects
+caravel_00088bca_fill_pattern_1_3: 1350000 rects
+caravel_00088bca_fill_pattern_4_2: 1730000 rects
+caravel_00088bca_fill_pattern_3_1: 250000 rects
+caravel_00088bca_fill_pattern_1_3: 1360000 rects
+caravel_00088bca_fill_pattern_3_1: 260000 rects
+caravel_00088bca_fill_pattern_1_3: 1370000 rects
+caravel_00088bca_fill_pattern_4_2: 1740000 rects
+caravel_00088bca_fill_pattern_2_4: 5590000 rects
+caravel_00088bca_fill_pattern_3_1: 270000 rects
+caravel_00088bca_fill_pattern_0_6: 4110000 rects
+caravel_00088bca_fill_pattern_1_3: 1380000 rects
+caravel_00088bca_fill_pattern_3_1: 280000 rects
+caravel_00088bca_fill_pattern_3_1: 290000 rects
+caravel_00088bca_fill_pattern_1_3: 1390000 rects
+caravel_00088bca_fill_pattern_3_1: 300000 rects
+caravel_00088bca_fill_pattern_1_3: 1400000 rects
+caravel_00088bca_fill_pattern_3_1: 310000 rects
+caravel_00088bca_fill_pattern_1_3: 1410000 rects
+caravel_00088bca_fill_pattern_4_2: 1750000 rects
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+caravel_00088bca_fill_pattern_3_1: 320000 rects
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+caravel_00088bca_fill_pattern_3_1: 340000 rects
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+caravel_00088bca_fill_pattern_3_1: 360000 rects
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+caravel_00088bca_fill_pattern_3_1: 370000 rects
+caravel_00088bca_fill_pattern_3_1: 380000 rects
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+caravel_00088bca_fill_pattern_3_1: 390000 rects
+caravel_00088bca_fill_pattern_2_4: 5620000 rects
+caravel_00088bca_fill_pattern_1_3: 1480000 rects
+caravel_00088bca_fill_pattern_3_1: 400000 rects
+caravel_00088bca_fill_pattern_1_3: 1490000 rects
+caravel_00088bca_fill_pattern_3_1: 410000 rects
+caravel_00088bca_fill_pattern_1_3: 1500000 rects
+caravel_00088bca_fill_pattern_3_1: 420000 rects
+caravel_00088bca_fill_pattern_0_6: 4150000 rects
+caravel_00088bca_fill_pattern_3_1: 430000 rects
+caravel_00088bca_fill_pattern_1_3: 1510000 rects
+caravel_00088bca_fill_pattern_3_1: 440000 rects
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+caravel_00088bca_fill_pattern_3_1: 530000 rects
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+caravel_00088bca_fill_pattern_3_1: 550000 rects
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+caravel_00088bca_fill_pattern_3_1: 650000 rects
+caravel_00088bca_fill_pattern_4_2: 1800000 rects
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+caravel_00088bca_fill_pattern_2_4: 5680000 rects
+caravel_00088bca_fill_pattern_3_1: 660000 rects
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+caravel_00088bca_fill_pattern_3_1: 730000 rects
+caravel_00088bca_fill_pattern_1_3: 1740000 rects
+caravel_00088bca_fill_pattern_3_1: 740000 rects
+caravel_00088bca_fill_pattern_0_6: 4350000 rects
+caravel_00088bca_fill_pattern_1_3: 1750000 rects
+caravel_00088bca_fill_pattern_3_1: 750000 rects
+caravel_00088bca_fill_pattern_2_4: 5700000 rects
+caravel_00088bca_fill_pattern_4_2: 1870000 rects
+caravel_00088bca_fill_pattern_1_3: 1760000 rects
+caravel_00088bca_fill_pattern_3_1: 760000 rects
+caravel_00088bca_fill_pattern_0_6: 4360000 rects
+caravel_00088bca_fill_pattern_1_3: 1770000 rects
+caravel_00088bca_fill_pattern_0_6: 4370000 rects
+caravel_00088bca_fill_pattern_3_1: 770000 rects
+caravel_00088bca_fill_pattern_4_2: 1880000 rects
+caravel_00088bca_fill_pattern_1_3: 1780000 rects
+caravel_00088bca_fill_pattern_0_6: 4380000 rects
+caravel_00088bca_fill_pattern_0_6: 4390000 rects
+caravel_00088bca_fill_pattern_3_1: 780000 rects
+caravel_00088bca_fill_pattern_1_3: 1790000 rects
+caravel_00088bca_fill_pattern_4_2: 1890000 rects
+caravel_00088bca_fill_pattern_0_6: 4400000 rects
+caravel_00088bca_fill_pattern_1_3: 1800000 rects
+caravel_00088bca_fill_pattern_0_6: 4410000 rects
+caravel_00088bca_fill_pattern_3_1: 790000 rects
+caravel_00088bca_fill_pattern_4_2: 1900000 rects
+caravel_00088bca_fill_pattern_2_4: 5710000 rects
+caravel_00088bca_fill_pattern_1_3: 1810000 rects
+caravel_00088bca_fill_pattern_0_6: 4420000 rects
+caravel_00088bca_fill_pattern_4_2: 1910000 rects
+caravel_00088bca_fill_pattern_3_1: 800000 rects
+caravel_00088bca_fill_pattern_0_6: 4430000 rects
+caravel_00088bca_fill_pattern_1_3: 1820000 rects
+caravel_00088bca_fill_pattern_4_2: 1920000 rects
+caravel_00088bca_fill_pattern_0_6: 4440000 rects
+caravel_00088bca_fill_pattern_3_1: 810000 rects
+caravel_00088bca_fill_pattern_1_3: 1830000 rects
+caravel_00088bca_fill_pattern_3_1: 820000 rects
+caravel_00088bca_fill_pattern_1_3: 1840000 rects
+caravel_00088bca_fill_pattern_3_1: 830000 rects
+caravel_00088bca_fill_pattern_0_6: 4450000 rects
+caravel_00088bca_fill_pattern_2_4: 5720000 rects
+caravel_00088bca_fill_pattern_1_3: 1850000 rects
+caravel_00088bca_fill_pattern_3_1: 840000 rects
+caravel_00088bca_fill_pattern_1_3: 1860000 rects
+caravel_00088bca_fill_pattern_3_1: 850000 rects
+caravel_00088bca_fill_pattern_0_6: 4460000 rects
+caravel_00088bca_fill_pattern_3_1: 860000 rects
+caravel_00088bca_fill_pattern_1_3: 1870000 rects
+caravel_00088bca_fill_pattern_3_1: 870000 rects
+caravel_00088bca_fill_pattern_4_2: 1930000 rects
+caravel_00088bca_fill_pattern_1_3: 1880000 rects
+caravel_00088bca_fill_pattern_3_1: 880000 rects
+caravel_00088bca_fill_pattern_2_4: 5730000 rects
+caravel_00088bca_fill_pattern_1_3: 1890000 rects
+caravel_00088bca_fill_pattern_3_1: 890000 rects
+caravel_00088bca_fill_pattern_1_3: 1900000 rects
+caravel_00088bca_fill_pattern_3_1: 900000 rects
+caravel_00088bca_fill_pattern_4_2: 1940000 rects
+caravel_00088bca_fill_pattern_1_3: 1910000 rects
+caravel_00088bca_fill_pattern_3_1: 910000 rects
+caravel_00088bca_fill_pattern_0_6: 4470000 rects
+caravel_00088bca_fill_pattern_3_1: 920000 rects
+caravel_00088bca_fill_pattern_1_3: 1920000 rects
+caravel_00088bca_fill_pattern_3_1: 930000 rects
+caravel_00088bca_fill_pattern_2_4: 5740000 rects
+caravel_00088bca_fill_pattern_1_3: 1930000 rects
+caravel_00088bca_fill_pattern_4_2: 1950000 rects
+caravel_00088bca_fill_pattern_3_1: 940000 rects
+caravel_00088bca_fill_pattern_1_3: 1940000 rects
+caravel_00088bca_fill_pattern_4_2: 1960000 rects
+caravel_00088bca_fill_pattern_3_1: 950000 rects
+caravel_00088bca_fill_pattern_4_2: 1970000 rects
+caravel_00088bca_fill_pattern_1_3: 1950000 rects
+caravel_00088bca_fill_pattern_3_1: 960000 rects
+caravel_00088bca_fill_pattern_3_1: 970000 rects
+caravel_00088bca_fill_pattern_1_3: 1960000 rects
+caravel_00088bca_fill_pattern_3_1: 980000 rects
+caravel_00088bca_fill_pattern_2_4: 5750000 rects
+caravel_00088bca_fill_pattern_1_3: 1970000 rects
+caravel_00088bca_fill_pattern_3_1: 990000 rects
+caravel_00088bca_fill_pattern_4_2: 1980000 rects
+caravel_00088bca_fill_pattern_1_3: 1980000 rects
+caravel_00088bca_fill_pattern_3_1: 1000000 rects
+caravel_00088bca_fill_pattern_1_3: 1990000 rects
+caravel_00088bca_fill_pattern_3_1: 1010000 rects
+caravel_00088bca_fill_pattern_0_6: 4480000 rects
+caravel_00088bca_fill_pattern_1_3: 2000000 rects
+caravel_00088bca_fill_pattern_3_1: 1020000 rects
+caravel_00088bca_fill_pattern_1_3: 2010000 rects
+caravel_00088bca_fill_pattern_3_1: 1030000 rects
+caravel_00088bca_fill_pattern_2_4: 5760000 rects
+caravel_00088bca_fill_pattern_3_1: 1040000 rects
+caravel_00088bca_fill_pattern_1_3: 2020000 rects
+caravel_00088bca_fill_pattern_3_1: 1050000 rects
+caravel_00088bca_fill_pattern_1_3: 2030000 rects
+caravel_00088bca_fill_pattern_3_1: 1060000 rects
+caravel_00088bca_fill_pattern_1_3: 2040000 rects
+caravel_00088bca_fill_pattern_3_1: 1070000 rects
+caravel_00088bca_fill_pattern_1_3: 2050000 rects
+caravel_00088bca_fill_pattern_3_1: 1080000 rects
+caravel_00088bca_fill_pattern_2_4: 5770000 rects
+caravel_00088bca_fill_pattern_1_3: 2060000 rects
+caravel_00088bca_fill_pattern_3_1: 1090000 rects
+caravel_00088bca_fill_pattern_0_6: 4490000 rects
+caravel_00088bca_fill_pattern_1_3: 2070000 rects
+caravel_00088bca_fill_pattern_0_6: 4500000 rects
+caravel_00088bca_fill_pattern_3_1: 1100000 rects
+caravel_00088bca_fill_pattern_0_6: 4510000 rects
+caravel_00088bca_fill_pattern_3_1: 1110000 rects
+caravel_00088bca_fill_pattern_1_3: 2080000 rects
+caravel_00088bca_fill_pattern_0_6: 4520000 rects
+caravel_00088bca_fill_pattern_3_1: 1120000 rects
+caravel_00088bca_fill_pattern_1_3: 2090000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00088bca_fill_pattern_2_4: 5780000 rects
+caravel_00088bca_fill_pattern_3_1: 1130000 rects
+   Generating output for cell caravel_00088bca_fill_pattern_4_2
+caravel_00088bca_fill_pattern_1_3: 2100000 rects
+caravel_00088bca_fill_pattern_3_1: 1140000 rects
+caravel_00088bca_fill_pattern_1_3: 2110000 rects
+caravel_00088bca_fill_pattern_3_1: 1150000 rects
+caravel_00088bca_fill_pattern_0_6: 4530000 rects
+caravel_00088bca_fill_pattern_1_3: 2120000 rects
+caravel_00088bca_fill_pattern_3_1: 1160000 rects
+caravel_00088bca_fill_pattern_1_3: 2130000 rects
+caravel_00088bca_fill_pattern_3_1: 1170000 rects
+caravel_00088bca_fill_pattern_1_3: 2140000 rects
+caravel_00088bca_fill_pattern_3_1: 1180000 rects
+caravel_00088bca_fill_pattern_2_4: 5790000 rects
+caravel_00088bca_fill_pattern_1_3: 2150000 rects
+caravel_00088bca_fill_pattern_3_1: 1190000 rects
+caravel_00088bca_fill_pattern_1_3: 2160000 rects
+caravel_00088bca_fill_pattern_3_1: 1200000 rects
+caravel_00088bca_fill_pattern_3_1: 1210000 rects
+caravel_00088bca_fill_pattern_1_3: 2170000 rects
+caravel_00088bca_fill_pattern_3_1: 1220000 rects
+caravel_00088bca_fill_pattern_1_3: 2180000 rects
+caravel_00088bca_fill_pattern_3_1: 1230000 rects
+caravel_00088bca_fill_pattern_2_4: 5800000 rects
+caravel_00088bca_fill_pattern_1_3: 2190000 rects
+caravel_00088bca_fill_pattern_3_1: 1240000 rects
+caravel_00088bca_fill_pattern_1_3: 2200000 rects
+caravel_00088bca_fill_pattern_1_3: 2210000 rects
+caravel_00088bca_fill_pattern_3_1: 1250000 rects
+caravel_00088bca_fill_pattern_1_3: 2220000 rects
+caravel_00088bca_fill_pattern_3_1: 1260000 rects
+caravel_00088bca_fill_pattern_1_3: 2230000 rects
+caravel_00088bca_fill_pattern_2_4: 5810000 rects
+caravel_00088bca_fill_pattern_3_1: 1270000 rects
+caravel_00088bca_fill_pattern_1_3: 2240000 rects
+caravel_00088bca_fill_pattern_3_1: 1280000 rects
+caravel_00088bca_fill_pattern_1_3: 2250000 rects
+caravel_00088bca_fill_pattern_3_1: 1290000 rects
+caravel_00088bca_fill_pattern_1_3: 2260000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00088bca_fill_pattern_0_6
+caravel_00088bca_fill_pattern_1_3: 2270000 rects
+caravel_00088bca_fill_pattern_3_1: 1300000 rects
+caravel_00088bca_fill_pattern_2_4: 5820000 rects
+caravel_00088bca_fill_pattern_1_3: 2280000 rects
+caravel_00088bca_fill_pattern_3_1: 1310000 rects
+caravel_00088bca_fill_pattern_1_3: 2290000 rects
+caravel_00088bca_fill_pattern_3_1: 1320000 rects
+caravel_00088bca_fill_pattern_1_3: 2300000 rects
+caravel_00088bca_fill_pattern_3_1: 1330000 rects
+caravel_00088bca_fill_pattern_1_3: 2310000 rects
+caravel_00088bca_fill_pattern_2_4: 5830000 rects
+caravel_00088bca_fill_pattern_3_1: 1340000 rects
+caravel_00088bca_fill_pattern_1_3: 2320000 rects
+caravel_00088bca_fill_pattern_1_3: 2330000 rects
+caravel_00088bca_fill_pattern_3_1: 1350000 rects
+caravel_00088bca_fill_pattern_1_3: 2340000 rects
+caravel_00088bca_fill_pattern_3_1: 1360000 rects
+caravel_00088bca_fill_pattern_1_3: 2350000 rects
+caravel_00088bca_fill_pattern_3_1: 1370000 rects
+caravel_00088bca_fill_pattern_2_4: 5840000 rects
+caravel_00088bca_fill_pattern_1_3: 2360000 rects
+caravel_00088bca_fill_pattern_3_1: 1380000 rects
+caravel_00088bca_fill_pattern_1_3: 2370000 rects
+caravel_00088bca_fill_pattern_3_1: 1390000 rects
+caravel_00088bca_fill_pattern_1_3: 2380000 rects
+caravel_00088bca_fill_pattern_3_1: 1400000 rects
+caravel_00088bca_fill_pattern_1_3: 2390000 rects
+caravel_00088bca_fill_pattern_2_4: 5850000 rects
+caravel_00088bca_fill_pattern_3_1: 1410000 rects
+caravel_00088bca_fill_pattern_1_3: 2400000 rects
+caravel_00088bca_fill_pattern_3_1: 1420000 rects
+caravel_00088bca_fill_pattern_1_3: 2410000 rects
+caravel_00088bca_fill_pattern_3_1: 1430000 rects
+caravel_00088bca_fill_pattern_1_3: 2420000 rects
+caravel_00088bca_fill_pattern_3_1: 1440000 rects
+caravel_00088bca_fill_pattern_1_3: 2430000 rects
+caravel_00088bca_fill_pattern_2_4: 5860000 rects
+caravel_00088bca_fill_pattern_3_1: 1450000 rects
+caravel_00088bca_fill_pattern_1_3: 2440000 rects
+caravel_00088bca_fill_pattern_3_1: 1460000 rects
+caravel_00088bca_fill_pattern_1_3: 2450000 rects
+caravel_00088bca_fill_pattern_3_1: 1470000 rects
+caravel_00088bca_fill_pattern_1_3: 2460000 rects
+caravel_00088bca_fill_pattern_3_1: 1480000 rects
+caravel_00088bca_fill_pattern_1_3: 2470000 rects
+caravel_00088bca_fill_pattern_1_3: 2480000 rects
+caravel_00088bca_fill_pattern_3_1: 1490000 rects
+caravel_00088bca_fill_pattern_2_4: 5870000 rects
+caravel_00088bca_fill_pattern_1_3: 2490000 rects
+caravel_00088bca_fill_pattern_3_1: 1500000 rects
+Ended: 12/04/2022 06:09:12
+caravel_00088bca_fill_pattern_1_3: 2500000 rects
+caravel_00088bca_fill_pattern_3_1: 1510000 rects
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_00088bca_fill_pattern_1_3: 2510000 rects
+Processing system .magicrc file
+caravel_00088bca_fill_pattern_1_3: 2520000 rects
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_00088bca_fill_pattern_2_4: 5880000 rects
+caravel_00088bca_fill_pattern_3_1: 1520000 rects
+caravel_00088bca_fill_pattern_1_3: 2530000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_00088bca_fill_pattern_1_3: 2540000 rects
+caravel_00088bca_fill_pattern_3_1: 1530000 rects
+caravel_00088bca_fill_pattern_1_3: 2550000 rects
+caravel_00088bca_fill_pattern_3_1: 1540000 rects
+caravel_00088bca_fill_pattern_1_3: 2560000 rects
+caravel_00088bca_fill_pattern_2_4: 5890000 rects
+caravel_00088bca_fill_pattern_1_3: 2570000 rects
+caravel_00088bca_fill_pattern_3_1: 1550000 rects
+caravel_00088bca_fill_pattern_1_3: 2580000 rects
+caravel_00088bca_fill_pattern_3_1: 1560000 rects
+caravel_00088bca_fill_pattern_1_3: 2590000 rects
+caravel_00088bca_fill_pattern_2_4: 5900000 rects
+caravel_00088bca_fill_pattern_3_1: 1570000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+caravel_00088bca_fill_pattern_1_3: 2600000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_00088bca_fill_pattern_3_1: 1580000 rects
+caravel_00088bca_fill_pattern_1_3: 2610000 rects
+caravel_00088bca_fill_pattern_3_1: 1590000 rects
+caravel_00088bca_fill_pattern_2_2: 10000 rects
+caravel_00088bca_fill_pattern_3_1: 1600000 rects
+caravel_00088bca_fill_pattern_1_3: 2620000 rects
+caravel_00088bca_fill_pattern_2_2: 20000 rects
+caravel_00088bca_fill_pattern_3_1: 1610000 rects
+caravel_00088bca_fill_pattern_2_4: 5910000 rects
+caravel_00088bca_fill_pattern_1_3: 2630000 rects
+caravel_00088bca_fill_pattern_2_2: 30000 rects
+caravel_00088bca_fill_pattern_3_1: 1620000 rects
+caravel_00088bca_fill_pattern_1_3: 2640000 rects
+caravel_00088bca_fill_pattern_2_2: 40000 rects
+caravel_00088bca_fill_pattern_3_1: 1630000 rects
+caravel_00088bca_fill_pattern_1_3: 2650000 rects
+caravel_00088bca_fill_pattern_2_2: 50000 rects
+caravel_00088bca_fill_pattern_3_1: 1640000 rects
+caravel_00088bca_fill_pattern_1_3: 2660000 rects
+caravel_00088bca_fill_pattern_2_2: 60000 rects
+caravel_00088bca_fill_pattern_2_4: 5920000 rects
+caravel_00088bca_fill_pattern_3_1: 1650000 rects
+caravel_00088bca_fill_pattern_2_2: 70000 rects
+caravel_00088bca_fill_pattern_2_2: 80000 rects
+caravel_00088bca_fill_pattern_1_3: 2670000 rects
+caravel_00088bca_fill_pattern_2_2: 90000 rects
+caravel_00088bca_fill_pattern_3_1: 1660000 rects
+caravel_00088bca_fill_pattern_2_2: 100000 rects
+caravel_00088bca_fill_pattern_1_3: 2680000 rects
+caravel_00088bca_fill_pattern_2_4: 5930000 rects
+caravel_00088bca_fill_pattern_2_2: 110000 rects
+caravel_00088bca_fill_pattern_3_1: 1670000 rects
+caravel_00088bca_fill_pattern_2_2: 120000 rects
+caravel_00088bca_fill_pattern_1_3: 2690000 rects
+caravel_00088bca_fill_pattern_2_2: 130000 rects
+caravel_00088bca_fill_pattern_2_2: 140000 rects
+caravel_00088bca_fill_pattern_2_4: 5940000 rects
+caravel_00088bca_fill_pattern_1_3: 2700000 rects
+caravel_00088bca_fill_pattern_2_2: 150000 rects
+caravel_00088bca_fill_pattern_3_1: 1680000 rects
+caravel_00088bca_fill_pattern_2_2: 160000 rects
+caravel_00088bca_fill_pattern_1_3: 2710000 rects
+caravel_00088bca_fill_pattern_2_2: 170000 rects
+caravel_00088bca_fill_pattern_3_1: 1690000 rects
+caravel_00088bca_fill_pattern_2_2: 180000 rects
+caravel_00088bca_fill_pattern_2_4: 5950000 rects
+caravel_00088bca_fill_pattern_1_3: 2720000 rects
+caravel_00088bca_fill_pattern_3_1: 1700000 rects
+caravel_00088bca_fill_pattern_2_2: 190000 rects
+caravel_00088bca_fill_pattern_2_2: 200000 rects
+caravel_00088bca_fill_pattern_3_1: 1710000 rects
+caravel_00088bca_fill_pattern_1_3: 2730000 rects
+caravel_00088bca_fill_pattern_2_2: 210000 rects
+caravel_00088bca_fill_pattern_3_1: 1720000 rects
+caravel_00088bca_fill_pattern_2_2: 220000 rects
+caravel_00088bca_fill_pattern_2_4: 5960000 rects
+caravel_00088bca_fill_pattern_3_1: 1730000 rects
+caravel_00088bca_fill_pattern_1_3: 2740000 rects
+caravel_00088bca_fill_pattern_2_2: 230000 rects
+caravel_00088bca_fill_pattern_3_1: 1740000 rects
+caravel_00088bca_fill_pattern_2_2: 240000 rects
+caravel_00088bca_fill_pattern_1_3: 2750000 rects
+caravel_00088bca_fill_pattern_3_1: 1750000 rects
+caravel_00088bca_fill_pattern_2_2: 250000 rects
+caravel_00088bca_fill_pattern_2_4: 5970000 rects
+caravel_00088bca_fill_pattern_2_2: 260000 rects
+caravel_00088bca_fill_pattern_3_1: 1760000 rects
+caravel_00088bca_fill_pattern_1_3: 2760000 rects
+caravel_00088bca_fill_pattern_3_1: 1770000 rects
+caravel_00088bca_fill_pattern_2_2: 270000 rects
+caravel_00088bca_fill_pattern_3_1: 1780000 rects
+caravel_00088bca_fill_pattern_2_2: 280000 rects
+caravel_00088bca_fill_pattern_1_3: 2770000 rects
+caravel_00088bca_fill_pattern_3_1: 1790000 rects
+caravel_00088bca_fill_pattern_2_4: 5980000 rects
+caravel_00088bca_fill_pattern_2_2: 290000 rects
+caravel_00088bca_fill_pattern_3_1: 1800000 rects
+caravel_00088bca_fill_pattern_1_3: 2780000 rects
+caravel_00088bca_fill_pattern_2_2: 300000 rects
+caravel_00088bca_fill_pattern_3_1: 1810000 rects
+caravel_00088bca_fill_pattern_2_2: 310000 rects
+caravel_00088bca_fill_pattern_1_3: 2790000 rects
+caravel_00088bca_fill_pattern_3_1: 1820000 rects
+caravel_00088bca_fill_pattern_2_2: 320000 rects
+caravel_00088bca_fill_pattern_2_4: 5990000 rects
+caravel_00088bca_fill_pattern_3_1: 1830000 rects
+caravel_00088bca_fill_pattern_2_2: 330000 rects
+caravel_00088bca_fill_pattern_1_3: 2800000 rects
+caravel_00088bca_fill_pattern_3_1: 1840000 rects
+caravel_00088bca_fill_pattern_2_2: 340000 rects
+caravel_00088bca_fill_pattern_3_1: 1850000 rects
+caravel_00088bca_fill_pattern_2_2: 350000 rects
+caravel_00088bca_fill_pattern_1_3: 2810000 rects
+caravel_00088bca_fill_pattern_2_2: 360000 rects
+caravel_00088bca_fill_pattern_3_1: 1860000 rects
+caravel_00088bca_fill_pattern_2_4: 6000000 rects
+caravel_00088bca_fill_pattern_1_3: 2820000 rects
+caravel_00088bca_fill_pattern_2_2: 370000 rects
+caravel_00088bca_fill_pattern_3_1: 1870000 rects
+caravel_00088bca_fill_pattern_3_1: 1880000 rects
+caravel_00088bca_fill_pattern_2_2: 380000 rects
+caravel_00088bca_fill_pattern_1_3: 2830000 rects
+caravel_00088bca_fill_pattern_2_4: 6010000 rects
+caravel_00088bca_fill_pattern_3_1: 1890000 rects
+caravel_00088bca_fill_pattern_2_2: 390000 rects
+caravel_00088bca_fill_pattern_2_2: 400000 rects
+caravel_00088bca_fill_pattern_2_4: 6020000 rects
+caravel_00088bca_fill_pattern_3_1: 1900000 rects
+caravel_00088bca_fill_pattern_1_3: 2840000 rects
+caravel_00088bca_fill_pattern_2_2: 410000 rects
+caravel_00088bca_fill_pattern_3_1: 1910000 rects
+caravel_00088bca_fill_pattern_2_4: 6030000 rects
+caravel_00088bca_fill_pattern_2_2: 420000 rects
+caravel_00088bca_fill_pattern_1_3: 2850000 rects
+caravel_00088bca_fill_pattern_2_2: 430000 rects
+caravel_00088bca_fill_pattern_3_1: 1920000 rects
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+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00088bca_fill_pattern_2_4
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+CIF output style is now "wafflefill(tiled)"
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+   Generating output for cell caravel_00088bca_fill_pattern_1_3
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+caravel_00088bca_fill_pattern_2_2: 5180000 rects
+caravel_00088bca_fill_pattern_3_1: 5380000 rects
+Ended: 12/04/2022 06:10:00
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+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_00088bca_fill_pattern_3_1: 5410000 rects
+Processing system .magicrc file
+caravel_00088bca_fill_pattern_3_1: 5420000 rects
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_00088bca_fill_pattern_2_2: 5190000 rects
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+Input style sky130(vendor): scaleFactor=2, multiplier=2
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+caravel_00088bca_fill_pattern_3_1: 5460000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
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+CIF output style is now "wafflefill(tiled)"
+caravel_00088bca_fill_pattern_4_0: 460000 rects
+   Generating output for cell caravel_00088bca_fill_pattern_3_1
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+caravel_00088bca_fill_pattern_2_2: 5940000 rects
+caravel_00088bca_fill_pattern_4_0: 1400000 rects
+Ended: 12/04/2022 06:10:08
+caravel_00088bca_fill_pattern_4_0: 1410000 rects
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_00088bca_fill_pattern_4_0: 1420000 rects
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_00088bca_fill_pattern_4_0: 1430000 rects
+caravel_00088bca_fill_pattern_2_2: 5950000 rects
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+caravel_00088bca_fill_pattern_4_0: 1450000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
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+caravel_00088bca_fill_pattern_0_4: 1090000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00088bca_fill_pattern_2_2
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+caravel_00088bca_fill_pattern_4_0: 1840000 rects
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+   Generating output for cell caravel_00088bca_fill_pattern_4_0
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+caravel_00088bca_fill_pattern_0_4: 3630000 rects
+caravel_00088bca_fill_pattern_0_4: 3640000 rects
+Ended: 12/04/2022 06:10:32
+caravel_00088bca_fill_pattern_0_4: 3650000 rects
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
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+Input style sky130(vendor): scaleFactor=2, multiplier=2
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+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
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+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
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+caravel_00088bca_fill_pattern_0_0: 4730000 rects
+caravel_00088bca_fill_pattern_0_0: 4740000 rects
+caravel_00088bca_fill_pattern_0_0: 4750000 rects
+Ended: 12/04/2022 06:11:10
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_00088bca_fill_pattern_0_0: 4760000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_00088bca_fill_pattern_0_0: 4770000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+caravel_00088bca_fill_pattern_0_0: 4780000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_00088bca_fill_pattern_1_7: 10000 rects
+caravel_00088bca_fill_pattern_1_7: 20000 rects
+caravel_00088bca_fill_pattern_1_7: 30000 rects
+caravel_00088bca_fill_pattern_0_0: 4790000 rects
+caravel_00088bca_fill_pattern_1_7: 40000 rects
+caravel_00088bca_fill_pattern_1_7: 50000 rects
+caravel_00088bca_fill_pattern_1_7: 60000 rects
+caravel_00088bca_fill_pattern_1_7: 70000 rects
+caravel_00088bca_fill_pattern_1_7: 80000 rects
+caravel_00088bca_fill_pattern_0_0: 4800000 rects
+caravel_00088bca_fill_pattern_1_7: 90000 rects
+caravel_00088bca_fill_pattern_1_7: 100000 rects
+caravel_00088bca_fill_pattern_1_7: 110000 rects
+caravel_00088bca_fill_pattern_1_7: 120000 rects
+caravel_00088bca_fill_pattern_1_7: 130000 rects
+caravel_00088bca_fill_pattern_1_7: 140000 rects
+caravel_00088bca_fill_pattern_0_0: 4810000 rects
+caravel_00088bca_fill_pattern_1_7: 150000 rects
+caravel_00088bca_fill_pattern_1_7: 160000 rects
+caravel_00088bca_fill_pattern_1_7: 170000 rects
+caravel_00088bca_fill_pattern_1_7: 180000 rects
+caravel_00088bca_fill_pattern_1_7: 190000 rects
+caravel_00088bca_fill_pattern_0_0: 4820000 rects
+Ended: 12/04/2022 06:11:12
+caravel_00088bca_fill_pattern_1_7: 200000 rects
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_00088bca_fill_pattern_1_7: 210000 rects
+Processing system .magicrc file
+caravel_00088bca_fill_pattern_1_7: 220000 rects
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_00088bca_fill_pattern_0_0: 4830000 rects
+caravel_00088bca_fill_pattern_1_7: 230000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_00088bca_fill_pattern_0_0: 4840000 rects
+caravel_00088bca_fill_pattern_1_7: 240000 rects
+caravel_00088bca_fill_pattern_1_7: 250000 rects
+caravel_00088bca_fill_pattern_0_0: 4850000 rects
+caravel_00088bca_fill_pattern_1_7: 260000 rects
+caravel_00088bca_fill_pattern_0_0: 4860000 rects
+caravel_00088bca_fill_pattern_1_7: 270000 rects
+caravel_00088bca_fill_pattern_0_0: 4870000 rects
+caravel_00088bca_fill_pattern_0_0: 4880000 rects
+caravel_00088bca_fill_pattern_1_7: 280000 rects
+caravel_00088bca_fill_pattern_0_0: 4890000 rects
+caravel_00088bca_fill_pattern_1_7: 290000 rects
+caravel_00088bca_fill_pattern_0_0: 4900000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+caravel_00088bca_fill_pattern_0_0: 4910000 rects
+caravel_00088bca_fill_pattern_1_7: 300000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_00088bca_fill_pattern_0_0: 4920000 rects
+caravel_00088bca_fill_pattern_0_0: 4930000 rects
+caravel_00088bca_fill_pattern_1_7: 310000 rects
+caravel_00088bca_fill_pattern_5_3: 10000 rects
+caravel_00088bca_fill_pattern_5_3: 20000 rects
+caravel_00088bca_fill_pattern_0_0: 4940000 rects
+caravel_00088bca_fill_pattern_1_7: 320000 rects
+caravel_00088bca_fill_pattern_5_3: 30000 rects
+caravel_00088bca_fill_pattern_5_3: 40000 rects
+caravel_00088bca_fill_pattern_1_7: 330000 rects
+caravel_00088bca_fill_pattern_5_3: 50000 rects
+caravel_00088bca_fill_pattern_0_0: 4950000 rects
+caravel_00088bca_fill_pattern_5_3: 60000 rects
+caravel_00088bca_fill_pattern_1_7: 340000 rects
+caravel_00088bca_fill_pattern_5_3: 70000 rects
+caravel_00088bca_fill_pattern_5_3: 80000 rects
+caravel_00088bca_fill_pattern_1_7: 350000 rects
+caravel_00088bca_fill_pattern_0_0: 4960000 rects
+caravel_00088bca_fill_pattern_5_3: 90000 rects
+caravel_00088bca_fill_pattern_1_7: 360000 rects
+caravel_00088bca_fill_pattern_5_3: 100000 rects
+caravel_00088bca_fill_pattern_1_7: 370000 rects
+caravel_00088bca_fill_pattern_5_3: 110000 rects
+caravel_00088bca_fill_pattern_0_0: 4970000 rects
+caravel_00088bca_fill_pattern_1_7: 380000 rects
+caravel_00088bca_fill_pattern_5_3: 120000 rects
+caravel_00088bca_fill_pattern_1_7: 390000 rects
+caravel_00088bca_fill_pattern_5_3: 130000 rects
+caravel_00088bca_fill_pattern_1_7: 400000 rects
+caravel_00088bca_fill_pattern_0_0: 4980000 rects
+caravel_00088bca_fill_pattern_5_3: 140000 rects
+caravel_00088bca_fill_pattern_1_7: 410000 rects
+caravel_00088bca_fill_pattern_5_3: 150000 rects
+caravel_00088bca_fill_pattern_1_7: 420000 rects
+caravel_00088bca_fill_pattern_0_0: 4990000 rects
+caravel_00088bca_fill_pattern_5_3: 160000 rects
+caravel_00088bca_fill_pattern_1_7: 430000 rects
+caravel_00088bca_fill_pattern_0_0: 5000000 rects
+caravel_00088bca_fill_pattern_5_3: 170000 rects
+caravel_00088bca_fill_pattern_0_0: 5010000 rects
+caravel_00088bca_fill_pattern_5_3: 180000 rects
+caravel_00088bca_fill_pattern_1_7: 440000 rects
+caravel_00088bca_fill_pattern_0_0: 5020000 rects
+caravel_00088bca_fill_pattern_5_3: 190000 rects
+caravel_00088bca_fill_pattern_0_0: 5030000 rects
+caravel_00088bca_fill_pattern_0_0: 5040000 rects
+caravel_00088bca_fill_pattern_5_3: 200000 rects
+caravel_00088bca_fill_pattern_1_7: 450000 rects
+caravel_00088bca_fill_pattern_0_0: 5050000 rects
+caravel_00088bca_fill_pattern_5_3: 210000 rects
+caravel_00088bca_fill_pattern_1_7: 460000 rects
+caravel_00088bca_fill_pattern_5_3: 220000 rects
+caravel_00088bca_fill_pattern_0_0: 5060000 rects
+caravel_00088bca_fill_pattern_1_7: 470000 rects
+caravel_00088bca_fill_pattern_5_3: 230000 rects
+caravel_00088bca_fill_pattern_1_7: 480000 rects
+caravel_00088bca_fill_pattern_0_0: 5070000 rects
+caravel_00088bca_fill_pattern_5_3: 240000 rects
+caravel_00088bca_fill_pattern_1_7: 490000 rects
+caravel_00088bca_fill_pattern_5_3: 250000 rects
+caravel_00088bca_fill_pattern_0_0: 5080000 rects
+caravel_00088bca_fill_pattern_1_7: 500000 rects
+caravel_00088bca_fill_pattern_0_0: 5090000 rects
+caravel_00088bca_fill_pattern_5_3: 260000 rects
+caravel_00088bca_fill_pattern_0_0: 5100000 rects
+caravel_00088bca_fill_pattern_1_7: 510000 rects
+caravel_00088bca_fill_pattern_0_0: 5110000 rects
+caravel_00088bca_fill_pattern_0_0: 5120000 rects
+caravel_00088bca_fill_pattern_5_3: 270000 rects
+caravel_00088bca_fill_pattern_1_7: 520000 rects
+caravel_00088bca_fill_pattern_5_3: 280000 rects
+caravel_00088bca_fill_pattern_0_0: 5130000 rects
+caravel_00088bca_fill_pattern_1_7: 530000 rects
+caravel_00088bca_fill_pattern_5_3: 290000 rects
+caravel_00088bca_fill_pattern_1_7: 540000 rects
+caravel_00088bca_fill_pattern_5_3: 300000 rects
+caravel_00088bca_fill_pattern_5_3: 310000 rects
+caravel_00088bca_fill_pattern_1_7: 550000 rects
+caravel_00088bca_fill_pattern_5_3: 320000 rects
+caravel_00088bca_fill_pattern_5_3: 330000 rects
+caravel_00088bca_fill_pattern_0_0: 5140000 rects
+caravel_00088bca_fill_pattern_5_3: 340000 rects
+caravel_00088bca_fill_pattern_1_7: 560000 rects
+caravel_00088bca_fill_pattern_5_3: 350000 rects
+caravel_00088bca_fill_pattern_5_3: 360000 rects
+caravel_00088bca_fill_pattern_1_7: 570000 rects
+caravel_00088bca_fill_pattern_5_3: 370000 rects
+caravel_00088bca_fill_pattern_5_3: 380000 rects
+caravel_00088bca_fill_pattern_1_7: 580000 rects
+caravel_00088bca_fill_pattern_5_3: 390000 rects
+caravel_00088bca_fill_pattern_5_3: 400000 rects
+caravel_00088bca_fill_pattern_1_7: 590000 rects
+caravel_00088bca_fill_pattern_5_3: 410000 rects
+caravel_00088bca_fill_pattern_1_7: 600000 rects
+caravel_00088bca_fill_pattern_5_3: 420000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00088bca_fill_pattern_0_0
+caravel_00088bca_fill_pattern_5_3: 430000 rects
+caravel_00088bca_fill_pattern_1_7: 610000 rects
+caravel_00088bca_fill_pattern_5_3: 440000 rects
+caravel_00088bca_fill_pattern_5_3: 450000 rects
+caravel_00088bca_fill_pattern_5_3: 460000 rects
+caravel_00088bca_fill_pattern_1_7: 620000 rects
+caravel_00088bca_fill_pattern_5_3: 470000 rects
+caravel_00088bca_fill_pattern_5_3: 480000 rects
+caravel_00088bca_fill_pattern_1_7: 630000 rects
+caravel_00088bca_fill_pattern_5_3: 490000 rects
+caravel_00088bca_fill_pattern_1_7: 640000 rects
+caravel_00088bca_fill_pattern_5_3: 500000 rects
+caravel_00088bca_fill_pattern_5_3: 510000 rects
+caravel_00088bca_fill_pattern_1_7: 650000 rects
+caravel_00088bca_fill_pattern_5_3: 520000 rects
+caravel_00088bca_fill_pattern_1_7: 660000 rects
+caravel_00088bca_fill_pattern_5_3: 530000 rects
+caravel_00088bca_fill_pattern_5_3: 540000 rects
+caravel_00088bca_fill_pattern_5_3: 550000 rects
+caravel_00088bca_fill_pattern_1_7: 670000 rects
+caravel_00088bca_fill_pattern_5_3: 560000 rects
+caravel_00088bca_fill_pattern_5_3: 570000 rects
+caravel_00088bca_fill_pattern_1_7: 680000 rects
+caravel_00088bca_fill_pattern_5_3: 580000 rects
+caravel_00088bca_fill_pattern_1_7: 690000 rects
+caravel_00088bca_fill_pattern_5_3: 590000 rects
+caravel_00088bca_fill_pattern_5_3: 600000 rects
+caravel_00088bca_fill_pattern_1_7: 700000 rects
+caravel_00088bca_fill_pattern_5_3: 610000 rects
+caravel_00088bca_fill_pattern_1_7: 710000 rects
+caravel_00088bca_fill_pattern_5_3: 620000 rects
+caravel_00088bca_fill_pattern_1_7: 720000 rects
+caravel_00088bca_fill_pattern_5_3: 630000 rects
+caravel_00088bca_fill_pattern_1_7: 730000 rects
+caravel_00088bca_fill_pattern_1_7: 740000 rects
+caravel_00088bca_fill_pattern_1_7: 750000 rects
+caravel_00088bca_fill_pattern_1_7: 760000 rects
+caravel_00088bca_fill_pattern_1_7: 770000 rects
+caravel_00088bca_fill_pattern_1_7: 780000 rects
+caravel_00088bca_fill_pattern_1_7: 790000 rects
+caravel_00088bca_fill_pattern_1_7: 800000 rects
+caravel_00088bca_fill_pattern_1_7: 810000 rects
+caravel_00088bca_fill_pattern_1_7: 820000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00088bca_fill_pattern_1_7: 830000 rects
+   Generating output for cell caravel_00088bca_fill_pattern_5_3
+caravel_00088bca_fill_pattern_1_7: 840000 rects
+caravel_00088bca_fill_pattern_1_7: 850000 rects
+caravel_00088bca_fill_pattern_1_7: 860000 rects
+caravel_00088bca_fill_pattern_1_7: 870000 rects
+caravel_00088bca_fill_pattern_1_7: 880000 rects
+caravel_00088bca_fill_pattern_1_7: 890000 rects
+caravel_00088bca_fill_pattern_1_7: 900000 rects
+caravel_00088bca_fill_pattern_1_7: 910000 rects
+caravel_00088bca_fill_pattern_1_7: 920000 rects
+caravel_00088bca_fill_pattern_1_7: 930000 rects
+caravel_00088bca_fill_pattern_1_7: 940000 rects
+caravel_00088bca_fill_pattern_1_7: 950000 rects
+caravel_00088bca_fill_pattern_1_7: 960000 rects
+caravel_00088bca_fill_pattern_1_7: 970000 rects
+caravel_00088bca_fill_pattern_1_7: 980000 rects
+caravel_00088bca_fill_pattern_1_7: 990000 rects
+caravel_00088bca_fill_pattern_1_7: 1000000 rects
+caravel_00088bca_fill_pattern_1_7: 1010000 rects
+caravel_00088bca_fill_pattern_1_7: 1020000 rects
+caravel_00088bca_fill_pattern_1_7: 1030000 rects
+caravel_00088bca_fill_pattern_1_7: 1040000 rects
+caravel_00088bca_fill_pattern_1_7: 1050000 rects
+caravel_00088bca_fill_pattern_1_7: 1060000 rects
+caravel_00088bca_fill_pattern_1_7: 1070000 rects
+caravel_00088bca_fill_pattern_1_7: 1080000 rects
+caravel_00088bca_fill_pattern_1_7: 1090000 rects
+caravel_00088bca_fill_pattern_1_7: 1100000 rects
+caravel_00088bca_fill_pattern_1_7: 1110000 rects
+caravel_00088bca_fill_pattern_1_7: 1120000 rects
+caravel_00088bca_fill_pattern_1_7: 1130000 rects
+caravel_00088bca_fill_pattern_1_7: 1140000 rects
+caravel_00088bca_fill_pattern_1_7: 1150000 rects
+caravel_00088bca_fill_pattern_1_7: 1160000 rects
+caravel_00088bca_fill_pattern_1_7: 1170000 rects
+caravel_00088bca_fill_pattern_1_7: 1180000 rects
+caravel_00088bca_fill_pattern_1_7: 1190000 rects
+caravel_00088bca_fill_pattern_1_7: 1200000 rects
+caravel_00088bca_fill_pattern_1_7: 1210000 rects
+caravel_00088bca_fill_pattern_1_7: 1220000 rects
+caravel_00088bca_fill_pattern_1_7: 1230000 rects
+caravel_00088bca_fill_pattern_1_7: 1240000 rects
+caravel_00088bca_fill_pattern_1_7: 1250000 rects
+caravel_00088bca_fill_pattern_1_7: 1260000 rects
+caravel_00088bca_fill_pattern_1_7: 1270000 rects
+caravel_00088bca_fill_pattern_1_7: 1280000 rects
+caravel_00088bca_fill_pattern_1_7: 1290000 rects
+caravel_00088bca_fill_pattern_1_7: 1300000 rects
+caravel_00088bca_fill_pattern_1_7: 1310000 rects
+caravel_00088bca_fill_pattern_1_7: 1320000 rects
+caravel_00088bca_fill_pattern_1_7: 1330000 rects
+caravel_00088bca_fill_pattern_1_7: 1340000 rects
+caravel_00088bca_fill_pattern_1_7: 1350000 rects
+caravel_00088bca_fill_pattern_1_7: 1360000 rects
+caravel_00088bca_fill_pattern_1_7: 1370000 rects
+caravel_00088bca_fill_pattern_1_7: 1380000 rects
+caravel_00088bca_fill_pattern_1_7: 1390000 rects
+caravel_00088bca_fill_pattern_1_7: 1400000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00088bca_fill_pattern_1_7
+Ended: 12/04/2022 06:11:23
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_00088bca_fill_pattern_3_5: 10000 rects
+caravel_00088bca_fill_pattern_3_5: 20000 rects
+caravel_00088bca_fill_pattern_3_5: 30000 rects
+caravel_00088bca_fill_pattern_3_5: 40000 rects
+caravel_00088bca_fill_pattern_3_5: 50000 rects
+caravel_00088bca_fill_pattern_3_5: 60000 rects
+caravel_00088bca_fill_pattern_3_5: 70000 rects
+caravel_00088bca_fill_pattern_3_5: 80000 rects
+caravel_00088bca_fill_pattern_3_5: 90000 rects
+caravel_00088bca_fill_pattern_3_5: 100000 rects
+caravel_00088bca_fill_pattern_3_5: 110000 rects
+caravel_00088bca_fill_pattern_3_5: 120000 rects
+caravel_00088bca_fill_pattern_3_5: 130000 rects
+caravel_00088bca_fill_pattern_3_5: 140000 rects
+caravel_00088bca_fill_pattern_3_5: 150000 rects
+caravel_00088bca_fill_pattern_3_5: 160000 rects
+caravel_00088bca_fill_pattern_3_5: 170000 rects
+caravel_00088bca_fill_pattern_3_5: 180000 rects
+caravel_00088bca_fill_pattern_3_5: 190000 rects
+caravel_00088bca_fill_pattern_3_5: 200000 rects
+caravel_00088bca_fill_pattern_3_5: 210000 rects
+caravel_00088bca_fill_pattern_3_5: 220000 rects
+caravel_00088bca_fill_pattern_3_5: 230000 rects
+caravel_00088bca_fill_pattern_3_5: 240000 rects
+caravel_00088bca_fill_pattern_3_5: 250000 rects
+caravel_00088bca_fill_pattern_3_5: 260000 rects
+caravel_00088bca_fill_pattern_3_5: 270000 rects
+caravel_00088bca_fill_pattern_3_5: 280000 rects
+caravel_00088bca_fill_pattern_3_5: 290000 rects
+caravel_00088bca_fill_pattern_3_5: 300000 rects
+caravel_00088bca_fill_pattern_3_5: 310000 rects
+caravel_00088bca_fill_pattern_3_5: 320000 rects
+caravel_00088bca_fill_pattern_3_5: 330000 rects
+caravel_00088bca_fill_pattern_3_5: 340000 rects
+caravel_00088bca_fill_pattern_3_5: 350000 rects
+caravel_00088bca_fill_pattern_3_5: 360000 rects
+caravel_00088bca_fill_pattern_3_5: 370000 rects
+caravel_00088bca_fill_pattern_3_5: 380000 rects
+caravel_00088bca_fill_pattern_3_5: 390000 rects
+caravel_00088bca_fill_pattern_3_5: 400000 rects
+caravel_00088bca_fill_pattern_3_5: 410000 rects
+caravel_00088bca_fill_pattern_3_5: 420000 rects
+caravel_00088bca_fill_pattern_3_5: 430000 rects
+caravel_00088bca_fill_pattern_3_5: 440000 rects
+caravel_00088bca_fill_pattern_3_5: 450000 rects
+caravel_00088bca_fill_pattern_3_5: 460000 rects
+caravel_00088bca_fill_pattern_3_5: 470000 rects
+caravel_00088bca_fill_pattern_3_5: 480000 rects
+caravel_00088bca_fill_pattern_3_5: 490000 rects
+caravel_00088bca_fill_pattern_3_5: 500000 rects
+caravel_00088bca_fill_pattern_3_5: 510000 rects
+caravel_00088bca_fill_pattern_3_5: 520000 rects
+caravel_00088bca_fill_pattern_3_5: 530000 rects
+caravel_00088bca_fill_pattern_3_5: 540000 rects
+caravel_00088bca_fill_pattern_3_5: 550000 rects
+caravel_00088bca_fill_pattern_3_5: 560000 rects
+caravel_00088bca_fill_pattern_3_5: 570000 rects
+caravel_00088bca_fill_pattern_3_5: 580000 rects
+caravel_00088bca_fill_pattern_3_5: 590000 rects
+caravel_00088bca_fill_pattern_3_5: 600000 rects
+caravel_00088bca_fill_pattern_3_5: 610000 rects
+caravel_00088bca_fill_pattern_3_5: 620000 rects
+caravel_00088bca_fill_pattern_3_5: 630000 rects
+caravel_00088bca_fill_pattern_3_5: 640000 rects
+caravel_00088bca_fill_pattern_3_5: 650000 rects
+caravel_00088bca_fill_pattern_3_5: 660000 rects
+caravel_00088bca_fill_pattern_3_5: 670000 rects
+caravel_00088bca_fill_pattern_3_5: 680000 rects
+caravel_00088bca_fill_pattern_3_5: 690000 rects
+caravel_00088bca_fill_pattern_3_5: 700000 rects
+caravel_00088bca_fill_pattern_3_5: 710000 rects
+caravel_00088bca_fill_pattern_3_5: 720000 rects
+caravel_00088bca_fill_pattern_3_5: 730000 rects
+caravel_00088bca_fill_pattern_3_5: 740000 rects
+caravel_00088bca_fill_pattern_3_5: 750000 rects
+caravel_00088bca_fill_pattern_3_5: 760000 rects
+caravel_00088bca_fill_pattern_3_5: 770000 rects
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+caravel_00088bca_fill_pattern_3_5: 910000 rects
+caravel_00088bca_fill_pattern_3_5: 920000 rects
+Ended: 12/04/2022 06:11:27
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+caravel_00088bca_fill_pattern_3_5: 940000 rects
+caravel_00088bca_fill_pattern_3_5: 950000 rects
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
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+Processing system .magicrc file
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+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
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+Input style sky130(vendor): scaleFactor=2, multiplier=2
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+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
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+Ended: 12/04/2022 06:11:48
+caravel_00088bca_fill_pattern_3_5: 3730000 rects
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
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+caravel_00088bca_fill_pattern_3_5: 3740000 rects
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_00088bca_fill_pattern_3_5: 3750000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
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+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
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+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
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+CIF output style is now "wafflefill(tiled)"
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+   Generating output for cell caravel_00088bca_fill_pattern_3_5
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+Ended: 12/04/2022 06:12:07
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+caravel_00088bca_fill_pattern_2_6: 5800000 rects
+caravel_00088bca_fill_pattern_2_6: 5810000 rects
+caravel_00088bca_fill_pattern_2_6: 5820000 rects
+caravel_00088bca_fill_pattern_2_6: 5830000 rects
+caravel_00088bca_fill_pattern_2_6: 5840000 rects
+caravel_00088bca_fill_pattern_2_6: 5850000 rects
+caravel_00088bca_fill_pattern_2_6: 5860000 rects
+caravel_00088bca_fill_pattern_2_6: 5870000 rects
+caravel_00088bca_fill_pattern_2_6: 5880000 rects
+caravel_00088bca_fill_pattern_2_6: 5890000 rects
+caravel_00088bca_fill_pattern_2_6: 5900000 rects
+caravel_00088bca_fill_pattern_2_6: 5910000 rects
+caravel_00088bca_fill_pattern_2_6: 5920000 rects
+caravel_00088bca_fill_pattern_4_4: 4090000 rects
+caravel_00088bca_fill_pattern_4_4: 4100000 rects
+caravel_00088bca_fill_pattern_2_6: 5930000 rects
+Ended: 12/04/2022 06:12:20
+caravel_00088bca_fill_pattern_4_4: 4110000 rects
+caravel_00088bca_fill_pattern_2_6: 5940000 rects
+caravel_00088bca_fill_pattern_4_4: 4120000 rects
+caravel_00088bca_fill_pattern_2_6: 5950000 rects
+caravel_00088bca_fill_pattern_4_4: 4130000 rects
+caravel_00088bca_fill_pattern_2_6: 5960000 rects
+caravel_00088bca_fill_pattern_4_4: 4140000 rects
+caravel_00088bca_fill_pattern_4_4: 4150000 rects
+caravel_00088bca_fill_pattern_4_4: 4160000 rects
+caravel_00088bca_fill_pattern_2_6: 5970000 rects
+caravel_00088bca_fill_pattern_4_4: 4170000 rects
+caravel_00088bca_fill_pattern_4_4: 4180000 rects
+caravel_00088bca_fill_pattern_2_6: 5980000 rects
+caravel_00088bca_fill_pattern_4_4: 4190000 rects
+caravel_00088bca_fill_pattern_4_4: 4200000 rects
+caravel_00088bca_fill_pattern_4_4: 4210000 rects
+caravel_00088bca_fill_pattern_2_6: 5990000 rects
+caravel_00088bca_fill_pattern_2_6: 6000000 rects
+caravel_00088bca_fill_pattern_4_4: 4220000 rects
+caravel_00088bca_fill_pattern_2_6: 6010000 rects
+caravel_00088bca_fill_pattern_4_4: 4230000 rects
+caravel_00088bca_fill_pattern_4_4: 4240000 rects
+caravel_00088bca_fill_pattern_2_6: 6020000 rects
+caravel_00088bca_fill_pattern_4_4: 4250000 rects
+caravel_00088bca_fill_pattern_2_6: 6030000 rects
+caravel_00088bca_fill_pattern_4_4: 4260000 rects
+caravel_00088bca_fill_pattern_4_4: 4270000 rects
+caravel_00088bca_fill_pattern_4_4: 4280000 rects
+caravel_00088bca_fill_pattern_2_6: 6040000 rects
+caravel_00088bca_fill_pattern_4_4: 4290000 rects
+caravel_00088bca_fill_pattern_4_4: 4300000 rects
+caravel_00088bca_fill_pattern_4_4: 4310000 rects
+caravel_00088bca_fill_pattern_4_4: 4320000 rects
+caravel_00088bca_fill_pattern_2_6: 6050000 rects
+caravel_00088bca_fill_pattern_2_6: 6060000 rects
+caravel_00088bca_fill_pattern_2_6: 6070000 rects
+caravel_00088bca_fill_pattern_2_6: 6080000 rects
+caravel_00088bca_fill_pattern_2_6: 6090000 rects
+caravel_00088bca_fill_pattern_4_4: 4330000 rects
+caravel_00088bca_fill_pattern_2_6: 6100000 rects
+caravel_00088bca_fill_pattern_2_6: 6110000 rects
+caravel_00088bca_fill_pattern_2_6: 6120000 rects
+caravel_00088bca_fill_pattern_4_4: 4340000 rects
+caravel_00088bca_fill_pattern_2_6: 6130000 rects
+caravel_00088bca_fill_pattern_4_4: 4350000 rects
+caravel_00088bca_fill_pattern_2_6: 6140000 rects
+caravel_00088bca_fill_pattern_4_4: 4360000 rects
+caravel_00088bca_fill_pattern_4_4: 4370000 rects
+caravel_00088bca_fill_pattern_2_6: 6150000 rects
+caravel_00088bca_fill_pattern_4_4: 4380000 rects
+caravel_00088bca_fill_pattern_2_6: 6160000 rects
+caravel_00088bca_fill_pattern_2_6: 6170000 rects
+caravel_00088bca_fill_pattern_2_6: 6180000 rects
+caravel_00088bca_fill_pattern_2_6: 6190000 rects
+caravel_00088bca_fill_pattern_2_6: 6200000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00088bca_fill_pattern_4_4
+caravel_00088bca_fill_pattern_2_6: 6210000 rects
+caravel_00088bca_fill_pattern_2_6: 6220000 rects
+caravel_00088bca_fill_pattern_2_6: 6230000 rects
+caravel_00088bca_fill_pattern_2_6: 6240000 rects
+caravel_00088bca_fill_pattern_2_6: 6250000 rects
+caravel_00088bca_fill_pattern_2_6: 6260000 rects
+caravel_00088bca_fill_pattern_2_6: 6270000 rects
+caravel_00088bca_fill_pattern_2_6: 6280000 rects
+caravel_00088bca_fill_pattern_2_6: 6290000 rects
+caravel_00088bca_fill_pattern_2_6: 6300000 rects
+caravel_00088bca_fill_pattern_2_6: 6310000 rects
+caravel_00088bca_fill_pattern_2_6: 6320000 rects
+caravel_00088bca_fill_pattern_2_6: 6330000 rects
+caravel_00088bca_fill_pattern_2_6: 6340000 rects
+caravel_00088bca_fill_pattern_2_6: 6350000 rects
+caravel_00088bca_fill_pattern_2_6: 6360000 rects
+caravel_00088bca_fill_pattern_2_6: 6370000 rects
+caravel_00088bca_fill_pattern_2_6: 6380000 rects
+caravel_00088bca_fill_pattern_2_6: 6390000 rects
+caravel_00088bca_fill_pattern_2_6: 6400000 rects
+caravel_00088bca_fill_pattern_2_6: 6410000 rects
+caravel_00088bca_fill_pattern_2_6: 6420000 rects
+caravel_00088bca_fill_pattern_2_6: 6430000 rects
+caravel_00088bca_fill_pattern_2_6: 6440000 rects
+caravel_00088bca_fill_pattern_2_6: 6450000 rects
+caravel_00088bca_fill_pattern_2_6: 6460000 rects
+caravel_00088bca_fill_pattern_2_6: 6470000 rects
+caravel_00088bca_fill_pattern_2_6: 6480000 rects
+caravel_00088bca_fill_pattern_2_6: 6490000 rects
+caravel_00088bca_fill_pattern_2_6: 6500000 rects
+caravel_00088bca_fill_pattern_2_6: 6510000 rects
+caravel_00088bca_fill_pattern_2_6: 6520000 rects
+caravel_00088bca_fill_pattern_2_6: 6530000 rects
+caravel_00088bca_fill_pattern_2_6: 6540000 rects
+caravel_00088bca_fill_pattern_2_6: 6550000 rects
+caravel_00088bca_fill_pattern_2_6: 6560000 rects
+caravel_00088bca_fill_pattern_2_6: 6570000 rects
+caravel_00088bca_fill_pattern_2_6: 6580000 rects
+caravel_00088bca_fill_pattern_2_6: 6590000 rects
+caravel_00088bca_fill_pattern_2_6: 6600000 rects
+caravel_00088bca_fill_pattern_2_6: 6610000 rects
+caravel_00088bca_fill_pattern_2_6: 6620000 rects
+caravel_00088bca_fill_pattern_2_6: 6630000 rects
+caravel_00088bca_fill_pattern_2_6: 6640000 rects
+caravel_00088bca_fill_pattern_2_6: 6650000 rects
+caravel_00088bca_fill_pattern_2_6: 6660000 rects
+caravel_00088bca_fill_pattern_2_6: 6670000 rects
+caravel_00088bca_fill_pattern_2_6: 6680000 rects
+caravel_00088bca_fill_pattern_2_6: 6690000 rects
+caravel_00088bca_fill_pattern_2_6: 6700000 rects
+caravel_00088bca_fill_pattern_2_6: 6710000 rects
+caravel_00088bca_fill_pattern_2_6: 6720000 rects
+caravel_00088bca_fill_pattern_2_6: 6730000 rects
+caravel_00088bca_fill_pattern_2_6: 6740000 rects
+caravel_00088bca_fill_pattern_2_6: 6750000 rects
+caravel_00088bca_fill_pattern_2_6: 6760000 rects
+caravel_00088bca_fill_pattern_2_6: 6770000 rects
+caravel_00088bca_fill_pattern_2_6: 6780000 rects
+caravel_00088bca_fill_pattern_2_6: 6790000 rects
+caravel_00088bca_fill_pattern_2_6: 6800000 rects
+caravel_00088bca_fill_pattern_2_6: 6810000 rects
+caravel_00088bca_fill_pattern_2_6: 6820000 rects
+caravel_00088bca_fill_pattern_2_6: 6830000 rects
+caravel_00088bca_fill_pattern_2_6: 6840000 rects
+caravel_00088bca_fill_pattern_2_6: 6850000 rects
+caravel_00088bca_fill_pattern_2_6: 6860000 rects
+caravel_00088bca_fill_pattern_2_6: 6870000 rects
+caravel_00088bca_fill_pattern_2_6: 6880000 rects
+caravel_00088bca_fill_pattern_2_6: 6890000 rects
+caravel_00088bca_fill_pattern_2_6: 6900000 rects
+caravel_00088bca_fill_pattern_2_6: 6910000 rects
+caravel_00088bca_fill_pattern_2_6: 6920000 rects
+caravel_00088bca_fill_pattern_2_6: 6930000 rects
+caravel_00088bca_fill_pattern_2_6: 6940000 rects
+caravel_00088bca_fill_pattern_2_6: 6950000 rects
+caravel_00088bca_fill_pattern_2_6: 6960000 rects
+caravel_00088bca_fill_pattern_2_6: 6970000 rects
+caravel_00088bca_fill_pattern_2_6: 6980000 rects
+caravel_00088bca_fill_pattern_2_6: 6990000 rects
+caravel_00088bca_fill_pattern_2_6: 7000000 rects
+caravel_00088bca_fill_pattern_2_6: 7010000 rects
+caravel_00088bca_fill_pattern_2_6: 7020000 rects
+caravel_00088bca_fill_pattern_2_6: 7030000 rects
+caravel_00088bca_fill_pattern_2_6: 7040000 rects
+caravel_00088bca_fill_pattern_2_6: 7050000 rects
+caravel_00088bca_fill_pattern_2_6: 7060000 rects
+caravel_00088bca_fill_pattern_2_6: 7070000 rects
+caravel_00088bca_fill_pattern_2_6: 7080000 rects
+caravel_00088bca_fill_pattern_2_6: 7090000 rects
+caravel_00088bca_fill_pattern_2_6: 7100000 rects
+Ended: 12/04/2022 06:12:33
+caravel_00088bca_fill_pattern_2_6: 7110000 rects
+caravel_00088bca_fill_pattern_2_6: 7120000 rects
+caravel_00088bca_fill_pattern_2_6: 7130000 rects
+caravel_00088bca_fill_pattern_2_6: 7140000 rects
+Ended: 12/04/2022 06:12:35
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00088bca_fill_pattern_2_6
+Ended: 12/04/2022 06:12:40
+Ended: 12/04/2022 06:12:54
+Ended: 12/04/2022 06:12:58
+Ended: 12/04/2022 06:13:21
+Ended: 12/04/2022 06:13:43
+Ended: 12/04/2022 06:13:53
+Ended: 12/04/2022 06:14:08
+Ended: 12/04/2022 06:14:22
+Ended: 12/04/2022 06:14:32
+Ended: 12/04/2022 06:16:05
+Ended: 12/04/2022 06:18:05
+Ended: 12/04/2022 06:20:33
diff --git a/tapeout/logs/gds.info b/tapeout/logs/gds.info
new file mode 100644
index 0000000..86992e7
--- /dev/null
+++ b/tapeout/logs/gds.info
@@ -0,0 +1 @@
+user_project_wrapper.gds: 11ce2a835a013823c4f4b9bf82aa5f1f991c0748
\ No newline at end of file
diff --git a/tapeout/logs/gen_gpio_defaults.log b/tapeout/logs/gen_gpio_defaults.log
new file mode 100644
index 0000000..d470522
--- /dev/null
+++ b/tapeout/logs/gen_gpio_defaults.log
@@ -0,0 +1,79 @@
+Step 1:  Create new cells for new GPIO default vectors.
+Creating new layout file /root/project/mag/gpio_defaults_block_1803.mag
+Creating new gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1803.v
+Layout file /root/project/mag/gpio_defaults_block_1803.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1803.v already exists and does not need to be generated.
+Creating new layout file /root/project/mag/gpio_defaults_block_0403.mag
+Creating new gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v
+Creating new layout file /root/project/mag/gpio_defaults_block_0801.mag
+Creating new gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0801.v
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Creating new layout file /root/project/mag/gpio_defaults_block_1800.mag
+Creating new gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Step 2:  Modify top-level layouts to use the specified defaults.
+Done.
diff --git a/tapeout/logs/git_clone.log b/tapeout/logs/git_clone.log
new file mode 100644
index 0000000..b29fbdc
--- /dev/null
+++ b/tapeout/logs/git_clone.log
@@ -0,0 +1,2 @@
+https://github.com/dineshannayya/riscduino_qcore.git
+Cloning into '/root/project'...
diff --git a/tapeout/logs/klayout_beol.log b/tapeout/logs/klayout_beol.log
new file mode 100644
index 0000000..b25a18b
--- /dev/null
+++ b/tapeout/logs/klayout_beol.log
@@ -0,0 +1,1005 @@
+/opt/scripts/tech/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::FEOL
+/opt/scripts/tech/sky130A_mr.drc:40: warning: previous definition of FEOL was here
+/opt/scripts/tech/sky130A_mr.drc:54: warning: already initialized constant DRC::DRCEngine::BEOL
+/opt/scripts/tech/sky130A_mr.drc:41: warning: previous definition of BEOL was here
+/opt/scripts/tech/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/scripts/tech/sky130A_mr.drc:42: warning: previous definition of OFFGRID was here
+/opt/scripts/tech/sky130A_mr.drc:68: warning: already initialized constant DRC::DRCEngine::SEAL
+/opt/scripts/tech/sky130A_mr.drc:43: warning: previous definition of SEAL was here
+/opt/scripts/tech/sky130A_mr.drc:74: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/opt/scripts/tech/sky130A_mr.drc:44: warning: previous definition of FLOATING_MET was here
+"input" in: sky130A_mr.drc:124
+    Polygons (raw): 2550253 (flat)  4755 (hierarchical)
+    Elapsed: 0.400s  Memory: 2616.00M
+"polygons" in: sky130A_mr.drc:125
+    Polygons (raw): 416037 (flat)  1037 (hierarchical)
+    Elapsed: 0.300s  Memory: 2616.00M
+"polygons" in: sky130A_mr.drc:126
+    Polygons (raw): 1278200 (flat)  1474 (hierarchical)
+    Elapsed: 0.260s  Memory: 2616.00M
+"polygons" in: sky130A_mr.drc:127
+    Polygons (raw): 856 (flat)  37 (hierarchical)
+    Elapsed: 0.020s  Memory: 2616.00M
+"polygons" in: sky130A_mr.drc:128
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2616.00M
+"polygons" in: sky130A_mr.drc:129
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2616.00M
+"polygons" in: sky130A_mr.drc:130
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2616.00M
+"polygons" in: sky130A_mr.drc:131
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2616.00M
+"polygons" in: sky130A_mr.drc:132
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+START: 76/20 (pad)
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+END: 76/20 (pad)
+Writing report database: /mnt/uffs/user/u5295_dinesha/design/riscduino-qcore_q3_/jobs/tapeout/93ac86dc-4d36-47e3-89b7-84b37ff26e49/outputs/klayout_beol_report.xml ..
+Total elapsed: 8456.780s  Memory: 15370.00M
+ 
+Cell exclusion list:
+   rule    | cell
+   nwell.6 | sky130_fd_io__gpiov2_amux, sky130_fd_io__simple_pad_and_busses, sram
+   nsd.1   | sram
+   nsd.2   | sram
+   psd.1   | sram
+   psd.2   | sram
+ 
+release 2022.6.30_01.07
diff --git a/tapeout/logs/klayout_feol.log b/tapeout/logs/klayout_feol.log
new file mode 100644
index 0000000..e01ed7e
--- /dev/null
+++ b/tapeout/logs/klayout_feol.log
@@ -0,0 +1,817 @@
+/opt/scripts/tech/sky130A_mr.drc:48: warning: already initialized constant DRC::DRCEngine::FEOL
+/opt/scripts/tech/sky130A_mr.drc:40: warning: previous definition of FEOL was here
+/opt/scripts/tech/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::BEOL
+/opt/scripts/tech/sky130A_mr.drc:41: warning: previous definition of BEOL was here
+/opt/scripts/tech/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/scripts/tech/sky130A_mr.drc:42: warning: previous definition of OFFGRID was here
+/opt/scripts/tech/sky130A_mr.drc:68: warning: already initialized constant DRC::DRCEngine::SEAL
+/opt/scripts/tech/sky130A_mr.drc:43: warning: previous definition of SEAL was here
+/opt/scripts/tech/sky130A_mr.drc:74: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/opt/scripts/tech/sky130A_mr.drc:44: warning: previous definition of FLOATING_MET was here
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+DRC section
+FEOL section
+START: 64/18 (dnwell)
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+    Elapsed: 0.430s  Memory: 6740.00M
+"output" in: sky130A_mr.drc:382
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 6740.00M
+"interacting" in: sky130A_mr.drc:383
+    Polygons (raw): 1 (flat)  1 (hierarchical)
+    Elapsed: 0.340s  Memory: 6740.00M
+"isolated" in: sky130A_mr.drc:383
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.420s  Memory: 6740.00M
+"output" in: sky130A_mr.drc:383
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 6740.00M
+"and" in: sky130A_mr.drc:384
+    Polygons (raw): 1 (flat)  1 (hierarchical)
+    Elapsed: 0.070s  Memory: 6740.00M
+"enclosing" in: sky130A_mr.drc:384
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.430s  Memory: 6740.00M
+"output" in: sky130A_mr.drc:384
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 6740.00M
+"enclosing" in: sky130A_mr.drc:385
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.320s  Memory: 6740.00M
+"output" in: sky130A_mr.drc:385
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 6740.00M
+"enclosing" in: sky130A_mr.drc:386
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.040s  Memory: 6740.00M
+"output" in: sky130A_mr.drc:386
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 6740.00M
+"separation" in: sky130A_mr.drc:387
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.030s  Memory: 6740.00M
+"output" in: sky130A_mr.drc:387
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 6740.00M
+"not_interacting" in: sky130A_mr.drc:388
+    Polygons (raw): 28901 (flat)  16981 (hierarchical)
+    Elapsed: 0.700s  Memory: 6740.00M
+"separation" in: sky130A_mr.drc:388
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 4.350s  Memory: 6740.00M
+"output" in: sky130A_mr.drc:388
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 6740.00M
+END: 97/44 (cap2m)
+FEOL section
+START: 75/20 (hvi)
+"not" in: sky130A_mr.drc:688
+    Polygons (raw): 54311 (flat)  575 (hierarchical)
+    Elapsed: 0.170s  Memory: 6740.00M
+"width" in: sky130A_mr.drc:689
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.400s  Memory: 6740.00M
+"output" in: sky130A_mr.drc:689
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 6740.00M
+"space" in: sky130A_mr.drc:690
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.050s  Memory: 6740.00M
+"output" in: sky130A_mr.drc:690
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 6740.00M
+END: 75/20 (hvi)
+START: 125/20 (hvntm)
+"not" in: sky130A_mr.drc:695
+    Polygons (raw): 33 (flat)  16 (hierarchical)
+    Elapsed: 0.090s  Memory: 6740.00M
+"width" in: sky130A_mr.drc:696
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.360s  Memory: 6740.00M
+"output" in: sky130A_mr.drc:696
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 6740.00M
+"space" in: sky130A_mr.drc:697
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.030s  Memory: 6740.00M
+"output" in: sky130A_mr.drc:697
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 6740.00M
+END: 125/20 (hvntm)
+Writing report database: /mnt/uffs/user/u5295_dinesha/design/riscduino-qcore_q3_/jobs/tapeout/93ac86dc-4d36-47e3-89b7-84b37ff26e49/outputs/klayout_feol_report.xml ..
+Total elapsed: 2134.880s  Memory: 6724.00M
+ 
+Cell exclusion list:
+   rule    | cell
+   nwell.6 | sky130_fd_io__gpiov2_amux, sky130_fd_io__simple_pad_and_busses, sram
+   nsd.1   | sram
+   nsd.2   | sram
+   psd.1   | sram
+   psd.2   | sram
+ 
+release 2022.6.30_01.07
diff --git a/tapeout/logs/klayout_fom_density.log b/tapeout/logs/klayout_fom_density.log
new file mode 100644
index 0000000..45cb42f
--- /dev/null
+++ b/tapeout/logs/klayout_fom_density.log
@@ -0,0 +1,58 @@
+fom_density.drc:: sourcing design file=/mnt/uffs/user/u5295_dinesha/design/riscduino-qcore_q3_/jobs/tapeout/93ac86dc-4d36-47e3-89b7-84b37ff26e49/outputs/caravel_00088bca.oas topcell=caravel_00088bca ...
+done.
+flattening chip boundary...
+done.
+step size = 70.0
+llx=5.964999999999999 lly=5.999999999999999 urx=3594.0349999999994 ury=5193.999999999999
+x_cnt = 51
+y_cnt = 74
+dbu = 0.0009999999999999998
+bbox_area = 18614907.159999993
+calculating subtile areas (= 3774)...
+tiles per step = 10
+calculating window step densities (= 2730)...
+{{ CHECK }} 0/2730
+{{ CHECK }} 65/2730
+{{ CHECK }} 130/2730
+{{ CHECK }} 195/2730
+{{ CHECK }} 260/2730
+{{ CHECK }} 325/2730
+{{ CHECK }} 390/2730
+{{ CHECK }} 455/2730
+{{ CHECK }} 520/2730
+{{ CHECK }} 585/2730
+{{ CHECK }} 650/2730
+{{ CHECK }} 715/2730
+{{ CHECK }} 780/2730
+{{ CHECK }} 845/2730
+{{ CHECK }} 910/2730
+{{ CHECK }} 975/2730
+{{ CHECK }} 1040/2730
+{{ CHECK }} 1105/2730
+{{ CHECK }} 1170/2730
+{{ CHECK }} 1235/2730
+{{ CHECK }} 1300/2730
+{{ CHECK }} 1365/2730
+{{ CHECK }} 1430/2730
+{{ CHECK }} 1495/2730
+{{ CHECK }} 1560/2730
+{{ CHECK }} 1625/2730
+{{ CHECK }} 1690/2730
+{{ CHECK }} 1755/2730
+{{ CHECK }} 1820/2730
+{{ CHECK }} 1885/2730
+{{ CHECK }} 1950/2730
+{{ CHECK }} 2015/2730
+{{ CHECK }} 2080/2730
+{{ CHECK }} 2145/2730
+{{ CHECK }} 2210/2730
+{{ CHECK }} 2275/2730
+{{ CHECK }} 2340/2730
+{{ CHECK }} 2405/2730
+{{ CHECK }} 2470/2730
+{{ CHECK }} 2535/2730
+{{ CHECK }} 2600/2730
+{{ CHECK }} 2665/2730
+minimum fom density  = 0.3556
+maximum fom density  = 0.5074
+finish received: success = true
diff --git a/tapeout/logs/klayout_gds2oas.log b/tapeout/logs/klayout_gds2oas.log
new file mode 100644
index 0000000..6e92606
--- /dev/null
+++ b/tapeout/logs/klayout_gds2oas.log
@@ -0,0 +1 @@
+[INFO] Changing from /mnt/uffs/user/u5295_dinesha/design/riscduino-qcore_q3_/jobs/tapeout/93ac86dc-4d36-47e3-89b7-84b37ff26e49/outputs/caravel_00088bca.gds to /mnt/uffs/user/u5295_dinesha/design/riscduino-qcore_q3_/jobs/tapeout/93ac86dc-4d36-47e3-89b7-84b37ff26e49/outputs/caravel_00088bca.oas
diff --git a/tapeout/logs/klayout_met_density.log b/tapeout/logs/klayout_met_density.log
new file mode 100644
index 0000000..506240e
--- /dev/null
+++ b/tapeout/logs/klayout_met_density.log
@@ -0,0 +1,6 @@
+li1_ca_density is 0.457040123284574
+m1_ca_density is 0.5553998881528637
+m2_ca_density is 0.5983528535753269
+m3_ca_density is 0.5557356236722301
+m4_ca_density is 0.4726089381535771
+m5_ca_density is 0.4937952815124007
diff --git a/tapeout/logs/klayout_missing_cells.log b/tapeout/logs/klayout_missing_cells.log
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/tapeout/logs/klayout_missing_cells.log
diff --git a/tapeout/logs/klayout_zero_area.log b/tapeout/logs/klayout_zero_area.log
new file mode 100644
index 0000000..7e8efd2
--- /dev/null
+++ b/tapeout/logs/klayout_zero_area.log
@@ -0,0 +1,4 @@
+0 zero-length paths,  0 zero-length paths deleted.
+0 total zero-area objects,  0 total objects deleted.
+VmPeak:	 3656280 kB
+VmHWM:	 3068956 kB
diff --git a/tapeout/logs/missing_cells.info b/tapeout/logs/missing_cells.info
new file mode 100644
index 0000000..bc59c12
--- /dev/null
+++ b/tapeout/logs/missing_cells.info
@@ -0,0 +1 @@
+False
diff --git a/tapeout/logs/oasis.info b/tapeout/logs/oasis.info
new file mode 100644
index 0000000..afa8e35
--- /dev/null
+++ b/tapeout/logs/oasis.info
@@ -0,0 +1 @@
+caravel_00088bca.oas: 6110e7555e32e8b9731ef4519ff18e84f97a5ee5
\ No newline at end of file
diff --git a/tapeout/logs/pdks.info b/tapeout/logs/pdks.info
new file mode 100644
index 0000000..3bb11c6
--- /dev/null
+++ b/tapeout/logs/pdks.info
@@ -0,0 +1,2 @@
+Open PDKs: 0059588eebfc704681dc2368bd1d33d96281d10f
+Skywater PDK: f70d8ca46961ff92719d8870a18a076370b85f6c
\ No newline at end of file
diff --git a/tapeout/logs/rram.info b/tapeout/logs/rram.info
new file mode 100644
index 0000000..bc59c12
--- /dev/null
+++ b/tapeout/logs/rram.info
@@ -0,0 +1 @@
+False
diff --git a/tapeout/logs/set_user_id.log b/tapeout/logs/set_user_id.log
new file mode 100644
index 0000000..66e0b1f
--- /dev/null
+++ b/tapeout/logs/set_user_id.log
@@ -0,0 +1,10 @@
+Project Chip ID is: 560074
+Setting Project Chip ID to: 00088bca
+Step 1: Modify Layout of the user_id_programming subcell
+Done!
+Step 2: Add user project ID parameter to source verilog.
+Done!
+Step 3: Add user project ID parameter to gate-level verilog.
+Done!
+Step 4: Add user project ID text to top level layout.
+Done!
diff --git a/tapeout/logs/ship_truck.log b/tapeout/logs/ship_truck.log
new file mode 100644
index 0000000..fcc7724
--- /dev/null
+++ b/tapeout/logs/ship_truck.log
@@ -0,0 +1,2224 @@
+
+Magic 8.3 revision 346 - Compiled on Wed Nov 23 17:18:53 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/mag2gds.tcl" from command line.
+Scaled magic input cell user_project_wrapper geometry by factor of 2
+user_project_wrapper: 10000 rects
+user_project_wrapper: 20000 rects
+user_project_wrapper: 30000 rects
+user_project_wrapper: 40000 rects
+user_project_wrapper: 50000 rects
+Scaled magic input cell user_id_textblock geometry by factor of 2
+caravel: 10000 rects
+caravel: 20000 rects
+caravel: 30000 rects
+caravel: 40000 rects
+caravel: 50000 rects
+caravel: 60000 rects
+caravel: 70000 rects
+caravel: 80000 rects
+Processing timestamp mismatches: simple_por.
+Scaled magic input cell caravel_motto geometry by factor of 2
+Scaled magic input cell font_22 geometry by factor of 24
+Scaled magic input cell font_73 geometry by factor of 24
+Scaled magic input cell font_43 geometry by factor of 24
+Scaled magic input cell font_49 geometry by factor of 24
+Scaled magic input cell font_65 geometry by factor of 24
+Scaled magic input cell font_68 geometry by factor of 24
+Scaled magic input cell font_54 geometry by factor of 24
+Scaled magic input cell font_67 geometry by factor of 24
+Scaled magic input cell font_6E geometry by factor of 24
+Scaled magic input cell font_69 geometry by factor of 24
+Scaled magic input cell font_6C geometry by factor of 24
+Scaled magic input cell font_61 geometry by factor of 24
+Scaled magic input cell font_53 geometry by factor of 24
+Scaled magic input cell font_79 geometry by factor of 24
+Scaled magic input cell font_76 geometry by factor of 24
+Scaled magic input cell font_74 geometry by factor of 24
+Scaled magic input cell font_72 geometry by factor of 24
+Scaled magic input cell font_70 geometry by factor of 24
+Scaled magic input cell font_66 geometry by factor of 24
+Scaled magic input cell font_63 geometry by factor of 24
+Scaled magic input cell font_62 geometry by factor of 24
+Scaled magic input cell font_57 geometry by factor of 24
+Scaled magic input cell font_56 geometry by factor of 24
+Scaled magic input cell font_50 geometry by factor of 24
+Scaled magic input cell font_47 geometry by factor of 24
+Scaled magic input cell font_44 geometry by factor of 24
+Scaled magic input cell font_35 geometry by factor of 24
+Scaled magic input cell font_32 geometry by factor of 24
+Scaled magic input cell font_30 geometry by factor of 24
+Scaled magic input cell font_29 geometry by factor of 24
+Scaled magic input cell font_28 geometry by factor of 24
+Scaled magic input cell font_20 geometry by factor of 24
+Scaled magic input cell font_6F geometry by factor of 24
+Scaled magic input cell font_6B geometry by factor of 24
+Scaled magic input cell font_4F geometry by factor of 24
+Scaled magic input cell font_4B geometry by factor of 24
+Scaled magic input cell font_2D geometry by factor of 24
+Scaled magic input cell open_source geometry by factor of 2
+Scaled magic input cell alpha_0 geometry by factor of 2
+Scaled magic input cell alpha_8 geometry by factor of 72
+Scaled magic input cell alpha_B geometry by factor of 72
+Scaled magic input cell alpha_C geometry by factor of 72
+Scaled magic input cell alpha_A geometry by factor of 72
+caravel_clocking: 10000 rects
+caravel_clocking: 20000 rects
+caravel_clocking: 30000 rects
+housekeeping: 10000 rects
+housekeeping: 20000 rects
+housekeeping: 30000 rects
+housekeeping: 40000 rects
+housekeeping: 50000 rects
+housekeeping: 60000 rects
+housekeeping: 70000 rects
+housekeeping: 80000 rects
+housekeeping: 90000 rects
+housekeeping: 100000 rects
+housekeeping: 110000 rects
+housekeeping: 120000 rects
+housekeeping: 130000 rects
+housekeeping: 140000 rects
+housekeeping: 150000 rects
+housekeeping: 160000 rects
+housekeeping: 170000 rects
+housekeeping: 180000 rects
+housekeeping: 190000 rects
+housekeeping: 200000 rects
+housekeeping: 210000 rects
+housekeeping: 220000 rects
+housekeeping: 230000 rects
+housekeeping: 240000 rects
+housekeeping: 250000 rects
+housekeeping: 260000 rects
+housekeeping: 270000 rects
+housekeeping: 280000 rects
+housekeeping: 290000 rects
+housekeeping: 300000 rects
+housekeeping: 310000 rects
+housekeeping: 320000 rects
+housekeeping: 330000 rects
+housekeeping: 340000 rects
+housekeeping: 350000 rects
+housekeeping: 360000 rects
+housekeeping: 370000 rects
+housekeeping: 380000 rects
+housekeeping: 390000 rects
+housekeeping: 400000 rects
+housekeeping: 410000 rects
+housekeeping: 420000 rects
+housekeeping: 430000 rects
+housekeeping: 440000 rects
+housekeeping: 450000 rects
+housekeeping: 460000 rects
+housekeeping: 470000 rects
+housekeeping: 480000 rects
+housekeeping: 490000 rects
+housekeeping: 500000 rects
+housekeeping: 510000 rects
+housekeeping: 520000 rects
+digital_pll: 10000 rects
+digital_pll: 20000 rects
+mgmt_protect: 10000 rects
+mgmt_protect: 20000 rects
+mgmt_protect: 30000 rects
+mgmt_protect: 40000 rects
+mgmt_protect: 50000 rects
+mgmt_protect: 60000 rects
+mgmt_protect: 70000 rects
+mgmt_protect: 80000 rects
+mgmt_protect: 90000 rects
+mgmt_protect: 100000 rects
+mgmt_protect: 110000 rects
+mgmt_protect: 120000 rects
+mgmt_protect: 130000 rects
+mgmt_protect: 140000 rects
+mgmt_protect: 150000 rects
+mgmt_protect: 160000 rects
+mgmt_protect: 170000 rects
+mgmt_protect: 180000 rects
+mgmt_protect: 190000 rects
+mgmt_protect: 200000 rects
+mgmt_protect: 210000 rects
+mgmt_protect: 220000 rects
+mgmt_protect: 230000 rects
+mgmt_protect: 240000 rects
+mgmt_protect: 250000 rects
+mgmt_protect: 260000 rects
+mgmt_protect: 270000 rects
+mgmt_protect: 280000 rects
+mgmt_protect: 290000 rects
+mgmt_protect: 300000 rects
+mgmt_protect: 310000 rects
+mgmt_protect: 320000 rects
+mgmt_protect: 330000 rects
+mgmt_protect: 340000 rects
+mgmt_protect: 350000 rects
+mgmt_protect: 360000 rects
+mgmt_protect: 370000 rects
+mgmt_protect: 380000 rects
+mgmt_protect: 390000 rects
+mgmt_protect: 400000 rects
+sky130_fd_io__corner_bus_overlay: 10000 rects
+sky130_fd_io__top_ground_hvc_wpad: 10000 rects
+sky130_fd_io__top_ground_hvc_wpad: 20000 rects
+sky130_fd_io__top_ground_hvc_wpad: 30000 rects
+sky130_fd_io__top_ground_hvc_wpad: 40000 rects
+sky130_fd_io__top_ground_hvc_wpad: 50000 rects
+sky130_fd_io__top_ground_hvc_wpad: 60000 rects
+sky130_fd_io__top_ground_hvc_wpad: 70000 rects
+sky130_fd_io__top_ground_hvc_wpad: 80000 rects
+sky130_fd_io__top_ground_hvc_wpad: 90000 rects
+sky130_fd_io__top_ground_hvc_wpad: 100000 rects
+sky130_fd_io__top_ground_hvc_wpad: 110000 rects
+sky130_fd_io__top_ground_hvc_wpad: 120000 rects
+sky130_fd_io__top_ground_hvc_wpad: 130000 rects
+sky130_fd_io__top_ground_hvc_wpad: 140000 rects
+sky130_fd_io__top_ground_hvc_wpad: 150000 rects
+sky130_fd_io__top_ground_hvc_wpad: 160000 rects
+sky130_fd_io__top_ground_hvc_wpad: 170000 rects
+sky130_fd_io__top_ground_hvc_wpad: 180000 rects
+sky130_fd_io__top_ground_hvc_wpad: 190000 rects
+sky130_fd_io__top_ground_hvc_wpad: 200000 rects
+sky130_fd_io__top_ground_hvc_wpad: 210000 rects
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_5595914180851 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808336 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_55959141808666 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808678 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_55959141808679 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_5595914180839 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdftpl1s__example_55959141808671 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdftpl1s2__example_55959141808672 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808663 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808660 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdftpl1s__example_55959141808675 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdftpl1s2__example_55959141808676 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808662 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808661 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_559591418084 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__genrivetdlring__example_559591418082 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__gendlring__example_559591418081 geometry by factor of 2
+sky130_fd_io__top_xres4v2: 10000 rects
+sky130_fd_io__top_xres4v2: 20000 rects
+sky130_fd_io__top_xres4v2: 30000 rects
+sky130_fd_io__top_xres4v2: 40000 rects
+sky130_fd_io__top_xres4v2: 50000 rects
+sky130_fd_io__top_xres4v2: 60000 rects
+sky130_fd_io__top_xres4v2: 70000 rects
+sky130_fd_io__top_xres4v2: 80000 rects
+sky130_fd_io__top_xres4v2: 90000 rects
+sky130_fd_io__top_xres4v2: 100000 rects
+sky130_fd_io__top_xres4v2: 110000 rects
+sky130_fd_io__top_xres4v2: 120000 rects
+sky130_fd_io__top_xres4v2: 130000 rects
+sky130_fd_io__top_xres4v2: 140000 rects
+sky130_fd_io__top_xres4v2: 150000 rects
+sky130_fd_io__top_xres4v2: 160000 rects
+sky130_fd_io__top_xres4v2: 170000 rects
+sky130_fd_io__top_xres4v2: 180000 rects
+sky130_fd_io__top_xres4v2: 190000 rects
+sky130_fd_io__top_xres4v2: 200000 rects
+sky130_fd_io__top_xres4v2: 210000 rects
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808719 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808765 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808717 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808243 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_5595914180890 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808264 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_5595914180858 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_5595914180833 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1s_cdns_55959141808288 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1s_cdns_5595914180859 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1o_cdns_55959141808289 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808274 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808728 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808727 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808726 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808725 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808724 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808554 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808553 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808552 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808551 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808402 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808350 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808261 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808260 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808259 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808400 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808372 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808326 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808290 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808128 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808127 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_5595914180897 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_5595914180819 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808147 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808157 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808156 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808155 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808154 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808153 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808152 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808151 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808150 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808149 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808148 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808158 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_559591418083 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808137 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_559591418086 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808370 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808316 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808385 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_559591418088 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808612 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_5595914180848 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_5595914180849 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m2m3__example_55959141808714 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1_centered__example_559591418081 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em2s_cdns_55959141808652 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em2o_cdns_55959141808653 geometry by factor of 2
+sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2: 10000 rects
+sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2: 20000 rects
+sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2: 30000 rects
+sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2: 40000 rects
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_5595914180812 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_5595914180811 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_559591418086 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_559591418084 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdftpm1s2__example_55959141808659 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__pfet_01v8__example_55959141808657 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808202 geometry by factor of 2
+sky130_fd_io__xres2v2_rcfilter_lpfv2: 10000 rects
+sky130_fd_io__xres2v2_rcfilter_lpfv2: 20000 rects
+sky130_fd_io__xres2v2_rcfilter_lpfv2: 30000 rects
+sky130_fd_io__xres2v2_rcfilter_lpfv2: 40000 rects
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808273 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808740 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808739 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808738 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808737 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808736 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808735 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808734 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808733 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808732 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808731 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808730 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808752 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808751 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808750 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808749 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808748 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808747 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808746 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808745 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808744 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808743 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808742 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808741 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808324 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808270 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808187 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808338 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808337 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808700 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808559 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808729 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__xres_tk_p_em1o_cdns_55959141808758 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__xres_tk_p_em1o_cdns_55959141808757 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__xres_tk_p_em1o_cdns_55959141808756 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__xres_tk_p_em1c_cdns_55959141808761 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__xres_tk_p_em1c_cdns_55959141808760 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__xres_tk_p_em1c_cdns_55959141808759 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__xres_p_em1c_cdns_55959141808753 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1o_cdns_5595914180860 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_5595914180857 geometry by factor of 2
+sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2: 10000 rects
+sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2: 20000 rects
+sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2: 30000 rects
+sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2: 40000 rects
+sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2: 50000 rects
+Scaled magic input cell sky130_fd_pr__hvdftpm1s2__example_55959141808649 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdftpl1s__example_55959141808646 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808378 geometry by factor of 2
+sky130_fd_io__xres4v2_in_buf: 10000 rects
+sky130_fd_io__xres4v2_in_buf: 20000 rects
+sky130_fd_io__xres4v2_in_buf: 30000 rects
+sky130_fd_io__xres4v2_in_buf: 40000 rects
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808782 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808449 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808452 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808233 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_5595914180827 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_5595914180835 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808242 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_5595914180829 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808237 geometry by factor of 2
+sky130_fd_io__top_gpiov2: 10000 rects
+sky130_fd_io__top_gpiov2: 20000 rects
+sky130_fd_io__top_gpiov2: 30000 rects
+sky130_fd_io__top_gpiov2: 40000 rects
+sky130_fd_io__top_gpiov2: 50000 rects
+sky130_fd_io__top_gpiov2: 60000 rects
+sky130_fd_io__top_gpiov2: 70000 rects
+sky130_fd_io__top_gpiov2: 80000 rects
+sky130_fd_io__top_gpiov2: 90000 rects
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808418 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808190 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_5595914180811 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_55959141808191 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808517 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_55959141808518 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_5595914180815 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_5595914180816 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_5595914180884 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808106 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808504 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_5595914180812 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_5595914180875 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em2s_cdns_55959141808438 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em2o_cdns_55959141808439 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1s_cdns_5595914180882 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1s_cdns_5595914180881 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1o_cdns_5595914180880 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1o_cdns_5595914180879 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_5595914180823 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808510 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808394 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808298 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808440 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_5595914180878 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808434 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808102 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808115 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808100 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808140 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808280 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808425 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808306 geometry by factor of 2
+sky130_fd_io__gpiov2_amux: 10000 rects
+sky130_fd_io__gpiov2_amux: 20000 rects
+sky130_fd_io__gpiov2_amux: 30000 rects
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808178 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808488 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808122 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808123 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808476 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_5595914180868 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_5595914180869 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808581 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808278 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808462 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808200 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_5595914180894 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfm1sd__example_55959141808258 geometry by factor of 2
+sky130_fd_io__amux_switch_1v2b: 10000 rects
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808563 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808251 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfm1sd2__example_55959141808561 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808267 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808266 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_55959141808633 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808322 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808321 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808320 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808294 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808325 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808323 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808291 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__pfet_01v8__example_55959141808640 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808194 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1o_cdns_55959141808328 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1o_cdns_55959141808327 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808272 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808271 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808143 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808275 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808276 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808297 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808296 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808295 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808293 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808292 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808300 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808299 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__nfet_01v8__example_55959141808308 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1s_cdns_55959141808301 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1o_cdns_55959141808302 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_5595914180854 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808368 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808625 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808373 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808374 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808398 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808397 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808396 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808395 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808401 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808399 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808269 geometry by factor of 2
+sky130_fd_io__gpio_odrvr_subv2: 10000 rects
+sky130_fd_io__gpio_odrvr_subv2: 20000 rects
+sky130_fd_io__gpio_odrvr_subv2: 30000 rects
+Scaled magic input cell sky130_fd_pr__via_pol1_centered__example_559591418080 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_5595914180832 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1s_cdns_5595914180852 geometry by factor of 2
+sky130_fd_io__nfet_con_diff_wo_abt_270v2: 10000 rects
+sky130_fd_io__nfet_con_diff_wo_abt_270v2: 20000 rects
+sky130_fd_io__nfet_con_diff_wo_abt_270v2: 30000 rects
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_559591418083 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_559591418082 geometry by factor of 2
+sky130_fd_io__pfet_con_diff_wo_abt_270v2: 10000 rects
+sky130_fd_io__pfet_con_diff_wo_abt_270v2: 20000 rects
+sky130_fd_io__pfet_con_diff_wo_abt_270v2: 30000 rects
+sky130_fd_io__pfet_con_diff_wo_abt_270v2: 40000 rects
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_559591418085 geometry by factor of 2
+sky130_fd_io__gpio_pddrvr_strong_slowv2: 10000 rects
+sky130_fd_io__gpio_pddrvr_strong_slowv2: 20000 rects
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808655 geometry by factor of 2
+sky130_fd_io__top_ground_lvc_wpad: 10000 rects
+sky130_fd_io__top_ground_lvc_wpad: 20000 rects
+sky130_fd_io__top_ground_lvc_wpad: 30000 rects
+sky130_fd_io__top_ground_lvc_wpad: 40000 rects
+sky130_fd_io__top_ground_lvc_wpad: 50000 rects
+sky130_fd_io__top_ground_lvc_wpad: 60000 rects
+sky130_fd_io__top_ground_lvc_wpad: 70000 rects
+sky130_fd_io__top_ground_lvc_wpad: 80000 rects
+sky130_fd_io__top_ground_lvc_wpad: 90000 rects
+sky130_fd_io__top_ground_lvc_wpad: 100000 rects
+sky130_fd_io__top_ground_lvc_wpad: 110000 rects
+sky130_fd_io__top_ground_lvc_wpad: 120000 rects
+sky130_fd_io__top_ground_lvc_wpad: 130000 rects
+sky130_fd_io__top_ground_lvc_wpad: 140000 rects
+sky130_fd_io__top_ground_lvc_wpad: 150000 rects
+sky130_fd_io__top_ground_lvc_wpad: 160000 rects
+sky130_fd_io__top_ground_lvc_wpad: 170000 rects
+sky130_fd_io__top_ground_lvc_wpad: 180000 rects
+sky130_fd_io__top_ground_lvc_wpad: 190000 rects
+sky130_fd_io__top_ground_lvc_wpad: 200000 rects
+sky130_fd_io__top_ground_lvc_wpad: 210000 rects
+sky130_fd_io__top_ground_lvc_wpad: 220000 rects
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808684 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808686 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808685 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__gnd2gnd_tap geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808683 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dftpl1s2__example_55959141808702 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808682 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dftpl1s2__example_55959141808694 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808681 geometry by factor of 2
+sky130_fd_io__overlay_vssio_hvc: 10000 rects
+sky130_fd_io__hvc_clampv2: 10000 rects
+sky130_fd_io__hvc_clampv2: 20000 rects
+sky130_fd_io__hvc_clampv2: 30000 rects
+sky130_fd_io__hvc_clampv2: 40000 rects
+sky130_fd_io__hvc_clampv2: 50000 rects
+sky130_fd_io__hvc_clampv2: 60000 rects
+sky130_fd_io__hvc_clampv2: 70000 rects
+sky130_fd_io__hvc_clampv2: 80000 rects
+sky130_fd_io__hvc_clampv2: 90000 rects
+sky130_fd_io__hvc_clampv2: 100000 rects
+sky130_fd_io__hvc_clampv2: 110000 rects
+sky130_fd_io__hvc_clampv2: 120000 rects
+sky130_fd_io__hvc_clampv2: 130000 rects
+sky130_fd_io__hvc_clampv2: 140000 rects
+sky130_fd_io__hvc_clampv2: 150000 rects
+sky130_fd_io__hvc_clampv2: 160000 rects
+sky130_fd_io__hvc_clampv2: 170000 rects
+sky130_fd_io__hvc_clampv2: 180000 rects
+sky130_fd_io__hvc_clampv2: 190000 rects
+sky130_fd_io__hvc_clampv2: 200000 rects
+sky130_fd_io__hvc_clampv2: 210000 rects
+sky130_fd_io__hvc_clampv2: 220000 rects
+sky130_fd_io__hvc_clampv2: 230000 rects
+sky130_fd_io__hvc_clampv2: 240000 rects
+sky130_fd_io__hvc_clampv2: 250000 rects
+sky130_fd_io__hvc_clampv2: 260000 rects
+sky130_fd_io__hvc_clampv2: 270000 rects
+sky130_fd_io__hvc_clampv2: 280000 rects
+sky130_fd_io__top_power_lvc_wpad: 10000 rects
+sky130_fd_io__top_power_lvc_wpad: 20000 rects
+sky130_fd_io__top_power_lvc_wpad: 30000 rects
+sky130_fd_io__top_power_lvc_wpad: 40000 rects
+sky130_fd_io__top_power_lvc_wpad: 50000 rects
+sky130_fd_io__top_power_lvc_wpad: 60000 rects
+sky130_fd_io__top_power_lvc_wpad: 70000 rects
+sky130_fd_io__top_power_lvc_wpad: 80000 rects
+sky130_fd_io__top_power_lvc_wpad: 90000 rects
+sky130_fd_io__top_power_lvc_wpad: 100000 rects
+sky130_fd_io__top_power_lvc_wpad: 110000 rects
+sky130_fd_io__top_power_lvc_wpad: 120000 rects
+sky130_fd_io__top_power_lvc_wpad: 130000 rects
+sky130_fd_io__top_power_lvc_wpad: 140000 rects
+sky130_fd_io__top_power_lvc_wpad: 150000 rects
+sky130_fd_io__top_power_lvc_wpad: 160000 rects
+sky130_fd_io__top_power_lvc_wpad: 170000 rects
+sky130_fd_io__top_power_lvc_wpad: 180000 rects
+sky130_fd_io__top_power_lvc_wpad: 190000 rects
+sky130_fd_io__top_power_lvc_wpad: 200000 rects
+sky130_fd_io__top_power_lvc_wpad: 210000 rects
+sky130_fd_io__top_power_lvc_wpad: 220000 rects
+sky130_fd_io__top_power_lvc_wpad: 230000 rects
+sky130_fd_io__overlay_vddio_hvc: 10000 rects
+Processing timestamp mismatches: sky130_fd_sc_hd__tapvpwrvgnd_1, sky130_fd_sc_hd__buf_8, sky130_ef_sc_hd__decap_12, sky130_ef_io__vccd_lvc_clamped3_pad, sky130_ef_io__vssd_lvc_clamped3_pad, sky130_ef_io__vddio_hvc_clamped_pad, sky130_ef_io__disconnect_vdda_slice_5um, sky130_ef_io__vccd_lvc_clamped_pad, sky130_ef_io__vdda_hvc_clamped_pad, sky130_ef_io__vssio_hvc_clamped_pad, sky130_ef_io__vssd_lvc_clamped_pad, sky130_ef_io__gpiov2_pad_wrapped, sky130_fd_sc_hd__fill_8, sky130_fd_sc_hd__fill_4, constant_block, sky130_fd_sc_hd__buf_16, sky130_fd_sc_hd__conb_1, sky130_fd_sc_hd__fill_1, sky130_fd_sc_hd__fill_2, sky130_fd_io__top_xres4v2, sky130_ef_io__vssa_hvc_clamped_pad, sky130_ef_io__com_bus_slice_10um, sky130_ef_io__com_bus_slice_5um, sky130_ef_io__com_bus_slice_1um, sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um, sky130_ef_io__corner_pad, sky130_ef_io__com_bus_slice_20um, gpio_control_power_routing, gpio_control_power_routing_right, gpio_control_power_routing_top, gpio_defaults_block_0801, sky130_fd_sc_hd__decap_3, sky130_fd_sc_hd__decap_4, sky130_fd_sc_hd__decap_12, sky130_fd_sc_hd__decap_6, sky130_fd_sc_hd__inv_12, mprj2_logic_high, mprj_logic_high, sky130_fd_sc_hd__decap_8, sky130_fd_sc_hvl__conb_1, mgmt_protect_hv, sky130_fd_sc_hvl__lsbufhv2lv_1, sky130_fd_sc_hvl__fill_2, sky130_fd_sc_hvl__fill_1, sky130_fd_sc_hd__bufbuf_8, sky130_fd_sc_hd__buf_6, sky130_fd_sc_hd__buf_4, sky130_fd_sc_hd__nand2_8, sky130_fd_sc_hd__nand2_4, sky130_fd_sc_hd__nand2_2, sky130_fd_sc_hd__nand2_1, sky130_fd_sc_hd__clkbuf_4, sky130_fd_sc_hd__clkbuf_8, sky130_fd_sc_hd__and2_1, sky130_fd_sc_hd__and2_2, sky130_fd_sc_hd__and2_4, sky130_fd_sc_hd__and3b_4, sky130_fd_sc_hd__and3b_2, sky130_fd_sc_hd__and3b_1, sky130_fd_sc_hd__and2b_4, sky130_fd_sc_hd__clkinv_2, sky130_fd_sc_hd__inv_2, sky130_fd_sc_hd__clkinv_8, sky130_fd_sc_hd__clkinv_4, sky130_fd_sc_hd__inv_4, sky130_fd_sc_hd__diode_2, sky130_fd_sc_hd__dfbbp_1, sky130_fd_sc_hd__inv_8, sky130_fd_sc_hd__nor2_2, sky130_fd_sc_hd__mux2_2, gpio_defaults_block_1800, gpio_defaults_block_0403, sky130_fd_sc_hd__o32a_2, sky130_fd_sc_hd__o21ba_2, sky130_fd_sc_hd__nand4b_2, sky130_fd_sc_hd__o2bb2a_2, sky130_fd_sc_hd__xor2_2, sky130_fd_sc_hd__a21boi_2, sky130_fd_sc_hd__nand3b_2, sky130_fd_sc_hd__o221a_2, sky130_fd_sc_hd__o22a_2, sky130_fd_sc_hd__o2111a_2, sky130_fd_sc_hd__a32o_2, sky130_fd_sc_hd__or2_2, sky130_fd_sc_hd__einvp_2, sky130_fd_sc_hd__einvn_8, sky130_fd_sc_hd__einvn_4, sky130_fd_sc_hd__clkinv_1, sky130_fd_sc_hd__einvp_1, sky130_fd_sc_hd__clkbuf_1, sky130_fd_sc_hd__clkbuf_2, sky130_fd_sc_hd__clkbuf_16, sky130_fd_sc_hd__dfrtp_2, sky130_fd_sc_hd__buf_2, sky130_fd_sc_hd__a22o_2, sky130_fd_sc_hd__a21o_2, sky130_fd_sc_hd__nand3_2, sky130_fd_sc_hd__o31a_2, sky130_fd_sc_hd__o21ai_2, sky130_fd_sc_hd__o211a_2, sky130_fd_sc_hd__and3_2, sky130_fd_sc_hd__nand2b_2, sky130_fd_sc_hd__a211o_2, sky130_fd_sc_hd__o21a_2, sky130_fd_sc_hd__a21oi_2, sky130_fd_sc_hd__and2b_2, sky130_fd_sc_hd__xnor2_2, sky130_fd_sc_hd__and4b_2, sky130_fd_sc_hd__nand4_2, sky130_fd_sc_hd__a31o_2, sky130_fd_sc_hd__inv_6, sky130_fd_sc_hd__a21o_4, sky130_fd_sc_hd__a21oi_4, sky130_fd_sc_hd__a221o_4, sky130_fd_sc_hd__a221oi_1, sky130_fd_sc_hd__and4_2, sky130_fd_sc_hd__o31a_4, sky130_fd_sc_hd__mux2_8, sky130_fd_sc_hd__o221a_4, sky130_fd_sc_hd__nor3_4, sky130_fd_sc_hd__xor2_1, sky130_fd_sc_hd__o21a_4, sky130_fd_sc_hd__nand3b_4, sky130_fd_sc_hd__and4b_4, sky130_fd_sc_hd__a31oi_4, sky130_fd_sc_hd__nand4b_4, sky130_fd_sc_hd__a2111oi_1, sky130_fd_sc_hd__nor3b_1, sky130_fd_sc_hd__o41a_1, sky130_fd_sc_hd__a311oi_2, sky130_fd_sc_hd__and2b_1, sky130_fd_sc_hd__a41o_1, sky130_fd_sc_hd__and4_1, sky130_fd_sc_hd__a31oi_1, sky130_fd_sc_hd__nand4b_1, sky130_fd_sc_hd__o2111a_1, sky130_fd_sc_hd__o211a_1, sky130_fd_sc_hd__o311a_1, sky130_fd_sc_hd__nand4_1, sky130_fd_sc_hd__a21boi_1, sky130_fd_sc_hd__o32a_1, sky130_fd_sc_hd__and3_1, sky130_fd_sc_hd__nand2b_4, sky130_fd_sc_hd__a2111o_2, sky130_fd_sc_hd__nor4_4, sky130_fd_sc_hd__a2111o_4, sky130_fd_sc_hd__nor4_2, sky130_fd_sc_hd__a2111o_1, sky130_fd_sc_hd__o221a_1, sky130_fd_sc_hd__nor2_8, sky130_fd_sc_hd__nor2_4, sky130_fd_sc_hd__a311o_1, sky130_fd_sc_hd__nand3_4, sky130_fd_sc_hd__and3_4, sky130_fd_sc_hd__and4bb_2, sky130_fd_sc_hd__and4bb_1, sky130_fd_sc_hd__and4b_1, sky130_fd_sc_hd__o21ba_1, sky130_fd_sc_hd__a211o_1, sky130_fd_sc_hd__a221o_2, sky130_fd_sc_hd__o2bb2a_1, sky130_fd_sc_hd__a21bo_1, sky130_fd_sc_hd__a211o_4, sky130_fd_sc_hd__a221o_1, sky130_fd_sc_hd__a22o_1, sky130_fd_sc_hd__a32o_1, sky130_fd_sc_hd__dfstp_4, sky130_fd_sc_hd__buf_12, sky130_fd_sc_hd__dlymetal6s2s_1, sky130_fd_sc_hd__dlygate4sd3_1, sky130_fd_sc_hd__dfrtp_1, sky130_fd_sc_hd__dfstp_2, sky130_fd_sc_hd__dfrtn_1, sky130_fd_sc_hd__dfrtp_4, sky130_fd_sc_hd__dfstp_1, sky130_fd_sc_hd__dfxtp_1, sky130_fd_sc_hd__mux2_1, sky130_fd_sc_hd__o31a_1, sky130_fd_sc_hd__a21o_1, sky130_fd_sc_hd__o31ai_1, sky130_fd_sc_hd__nor4_1, sky130_fd_sc_hd__nor3_1, sky130_fd_sc_hd__nor3_2, sky130_fd_sc_hd__a21oi_1, sky130_fd_sc_hd__nor2_1, sky130_fd_sc_hd__a2bb2o_1, sky130_fd_sc_hd__o21ai_1, sky130_fd_sc_hd__o22a_1, sky130_fd_sc_hd__nand2b_1, sky130_fd_sc_hd__o21a_1, sky130_fd_sc_hd__a31o_1, sky130_fd_sc_hd__nand3_1, sky130_fd_sc_hd__o2111ai_1, sky130_fd_sc_hd__xnor2_1, sky130_fd_sc_hd__mux2_4, gpio_defaults_block_1803, sky130_fd_sc_hd__and2_0, sky130_fd_sc_hd__o21ai_4, sky130_fd_sc_hd__or2_0, sky130_fd_sc_hd__dfbbn_2, sky130_fd_sc_hd__macro_sparecell, sky130_fd_sc_hd__nor3b_2, sky130_fd_sc_hd__o211ai_4, sky130_fd_sc_hd__a41oi_1, sky130_fd_sc_hd__o2bb2ai_1, sky130_fd_sc_hd__o31ai_2, sky130_fd_sc_hd__o2111ai_2, sky130_fd_sc_hd__nand4bb_1, sky130_fd_sc_hd__nand3b_1, sky130_fd_sc_hd__o21bai_1, alpha_A, alpha_C, alpha_B, alpha_8, sky130_fd_sc_hvl__diode_2, sky130_fd_sc_hvl__decap_4, sky130_fd_sc_hvl__decap_8.
+   Generating output for cell caravel_logo
+   Generating output for cell font_22
+   Generating output for cell font_73
+   Generating output for cell font_43
+   Generating output for cell font_49
+   Generating output for cell font_65
+   Generating output for cell font_68
+   Generating output for cell font_54
+   Generating output for cell font_67
+   Generating output for cell font_6E
+   Generating output for cell font_69
+   Generating output for cell font_6C
+   Generating output for cell font_61
+   Generating output for cell font_53
+   Generating output for cell caravel_motto
+   Generating output for cell font_79
+   Generating output for cell font_76
+   Generating output for cell font_74
+   Generating output for cell font_72
+   Generating output for cell font_70
+   Generating output for cell font_66
+   Generating output for cell font_63
+   Generating output for cell font_62
+   Generating output for cell font_57
+   Generating output for cell font_56
+   Generating output for cell font_50
+   Generating output for cell font_47
+   Generating output for cell font_44
+   Generating output for cell font_35
+   Generating output for cell font_32
+   Generating output for cell font_30
+   Generating output for cell font_29
+   Generating output for cell font_28
+   Generating output for cell font_20
+   Generating output for cell font_6F
+   Generating output for cell font_6B
+   Generating output for cell font_4F
+   Generating output for cell font_4B
+   Generating output for cell font_2D
+   Generating output for cell copyright_block
+   Generating output for cell open_source
+   Generating output for cell sky130_fd_sc_hvl__decap_8
+   Generating output for cell sky130_fd_sc_hvl__decap_4
+   Generating output for cell sky130_fd_sc_hvl__diode_2
+   Generating output for cell sky130_fd_sc_hvl__fill_1
+   Generating output for cell sky130_fd_sc_hvl__fill_2
+   Generating output for cell sky130_fd_sc_hvl__lsbufhv2lv_1
+   Generating output for cell xres_buf
+   Generating output for cell alpha_8
+   Generating output for cell alpha_B
+   Generating output for cell alpha_C
+   Generating output for cell alpha_A
+   Generating output for cell alpha_0
+   Generating output for cell user_id_textblock
+   Generating output for cell sky130_fd_sc_hd__decap_6
+   Generating output for cell sky130_fd_sc_hd__decap_12
+   Generating output for cell sky130_fd_sc_hd__decap_4
+   Generating output for cell sky130_fd_sc_hd__decap_3
+   Generating output for cell sky130_fd_sc_hd__fill_2
+   Generating output for cell sky130_fd_sc_hd__fill_1
+   Generating output for cell sky130_fd_sc_hd__conb_1
+   Generating output for cell sky130_fd_sc_hd__tapvpwrvgnd_1
+   Generating output for cell gpio_defaults_block_1803
+   Generating output for cell sky130_fd_sc_hd__o21bai_1
+   Generating output for cell sky130_fd_sc_hd__nand3b_1
+   Generating output for cell sky130_fd_sc_hd__nand4bb_1
+   Generating output for cell sky130_fd_sc_hd__o2111ai_2
+   Generating output for cell sky130_fd_sc_hd__o31ai_2
+   Generating output for cell sky130_fd_sc_hd__o2bb2ai_1
+   Generating output for cell sky130_fd_sc_hd__a41oi_1
+   Generating output for cell sky130_fd_sc_hd__o211ai_4
+   Generating output for cell sky130_fd_sc_hd__nor3b_2
+   Generating output for cell sky130_fd_sc_hd__xnor2_1
+   Generating output for cell sky130_fd_sc_hd__o2111ai_1
+   Generating output for cell sky130_fd_sc_hd__nand3_1
+   Generating output for cell sky130_fd_sc_hd__a31o_1
+   Generating output for cell sky130_fd_sc_hd__o21a_1
+   Generating output for cell sky130_fd_sc_hd__nand2b_1
+   Generating output for cell sky130_fd_sc_hd__o22a_1
+   Generating output for cell sky130_fd_sc_hd__o21ai_1
+   Generating output for cell sky130_fd_sc_hd__a2bb2o_1
+   Generating output for cell sky130_fd_sc_hd__nor2_1
+   Generating output for cell sky130_fd_sc_hd__a21oi_1
+   Generating output for cell sky130_fd_sc_hd__nor3_2
+   Generating output for cell sky130_fd_sc_hd__nor3_1
+   Generating output for cell sky130_fd_sc_hd__nor4_1
+   Generating output for cell sky130_fd_sc_hd__o31ai_1
+   Generating output for cell sky130_fd_sc_hd__a21o_1
+   Generating output for cell sky130_fd_sc_hd__o31a_1
+   Generating output for cell sky130_fd_sc_hd__mux2_1
+   Generating output for cell sky130_fd_sc_hd__dfxtp_1
+   Generating output for cell sky130_fd_sc_hd__dfstp_1
+   Generating output for cell sky130_fd_sc_hd__dfrtp_4
+   Generating output for cell sky130_fd_sc_hd__dfrtn_1
+   Generating output for cell sky130_fd_sc_hd__dfstp_2
+   Generating output for cell sky130_fd_sc_hd__dfrtp_1
+   Generating output for cell sky130_fd_sc_hd__dlymetal6s2s_1
+   Generating output for cell sky130_fd_sc_hd__buf_12
+   Generating output for cell sky130_fd_sc_hd__o21a_2
+   Generating output for cell sky130_fd_sc_hd__nand2b_2
+   Generating output for cell sky130_fd_sc_hd__o21ai_2
+   Generating output for cell sky130_fd_sc_hd__buf_2
+   Generating output for cell sky130_fd_sc_hd__dfrtp_2
+   Generating output for cell sky130_fd_sc_hd__clkbuf_16
+   Generating output for cell sky130_fd_sc_hd__clkbuf_2
+   Generating output for cell sky130_fd_sc_hd__clkbuf_1
+   Generating output for cell sky130_fd_sc_hd__nor2_2
+   Generating output for cell sky130_fd_sc_hd__diode_2
+   Generating output for cell sky130_fd_sc_hd__inv_4
+   Generating output for cell sky130_fd_sc_hd__clkinv_4
+   Generating output for cell sky130_fd_sc_hd__inv_2
+   Generating output for cell sky130_fd_sc_hd__clkinv_2
+   Generating output for cell sky130_fd_sc_hd__and2_1
+   Generating output for cell sky130_fd_sc_hd__clkbuf_4
+   Generating output for cell sky130_fd_sc_hd__nand2_1
+   Generating output for cell sky130_fd_sc_hd__buf_4
+   Generating output for cell sky130_fd_sc_hd__decap_8
+   Generating output for cell sky130_ef_sc_hd__decap_12
+   Generating output for cell caravel_clocking
+   Generating output for cell sky130_fd_sc_hd__clkbuf_8
+   Generating output for cell buff_flash_clkrst
+   Generating output for cell sky130_fd_sc_hd__nand2_2
+   Generating output for cell sky130_fd_sc_hd__macro_sparecell
+   Generating output for cell sky130_fd_sc_hd__dfbbn_2
+   Generating output for cell sky130_fd_sc_hd__or2_0
+   Generating output for cell sky130_fd_sc_hd__o21ai_4
+   Generating output for cell sky130_fd_sc_hd__and2_0
+   Generating output for cell sky130_fd_sc_hd__mux2_4
+   Generating output for cell sky130_fd_sc_hd__dlygate4sd3_1
+   Generating output for cell sky130_fd_sc_hd__and2b_2
+   Generating output for cell sky130_fd_sc_hd__and3b_2
+   Generating output for cell sky130_fd_sc_hd__and2_2
+   Generating output for cell sky130_fd_sc_hd__buf_16
+   Generating output for cell gpio_logic_high
+   Generating output for cell gpio_control_block
+   Generating output for cell sky130_fd_sc_hd__dfstp_4
+   Generating output for cell sky130_fd_sc_hd__a32o_1
+   Generating output for cell sky130_fd_sc_hd__a22o_1
+   Generating output for cell sky130_fd_sc_hd__a221o_1
+   Generating output for cell sky130_fd_sc_hd__a211o_4
+   Generating output for cell sky130_fd_sc_hd__a21bo_1
+   Generating output for cell sky130_fd_sc_hd__o2bb2a_1
+   Generating output for cell sky130_fd_sc_hd__a221o_2
+   Generating output for cell sky130_fd_sc_hd__a211o_1
+   Generating output for cell sky130_fd_sc_hd__o21ba_1
+   Generating output for cell sky130_fd_sc_hd__and4b_1
+   Generating output for cell sky130_fd_sc_hd__and4bb_1
+   Generating output for cell sky130_fd_sc_hd__and4bb_2
+   Generating output for cell sky130_fd_sc_hd__and3_4
+   Generating output for cell sky130_fd_sc_hd__nand3_4
+   Generating output for cell sky130_fd_sc_hd__a311o_1
+   Generating output for cell sky130_fd_sc_hd__nor2_4
+   Generating output for cell sky130_fd_sc_hd__nor2_8
+   Generating output for cell sky130_fd_sc_hd__o221a_1
+   Generating output for cell sky130_fd_sc_hd__a2111o_1
+   Generating output for cell sky130_fd_sc_hd__nor4_2
+   Generating output for cell sky130_fd_sc_hd__a2111o_4
+   Generating output for cell sky130_fd_sc_hd__nor4_4
+   Generating output for cell sky130_fd_sc_hd__a2111o_2
+   Generating output for cell sky130_fd_sc_hd__nand2b_4
+   Generating output for cell sky130_fd_sc_hd__and3_1
+   Generating output for cell sky130_fd_sc_hd__o32a_1
+   Generating output for cell sky130_fd_sc_hd__a21boi_1
+   Generating output for cell sky130_fd_sc_hd__nand4_1
+   Generating output for cell sky130_fd_sc_hd__o311a_1
+   Generating output for cell sky130_fd_sc_hd__o211a_1
+   Generating output for cell sky130_fd_sc_hd__o2111a_1
+   Generating output for cell sky130_fd_sc_hd__nand4b_1
+   Generating output for cell sky130_fd_sc_hd__a31oi_1
+   Generating output for cell sky130_fd_sc_hd__and4_1
+   Generating output for cell sky130_fd_sc_hd__a41o_1
+   Generating output for cell sky130_fd_sc_hd__and2b_1
+   Generating output for cell sky130_fd_sc_hd__a311oi_2
+   Generating output for cell sky130_fd_sc_hd__o41a_1
+   Generating output for cell sky130_fd_sc_hd__nor3b_1
+   Generating output for cell sky130_fd_sc_hd__a2111oi_1
+   Generating output for cell sky130_fd_sc_hd__nand4b_4
+   Generating output for cell sky130_fd_sc_hd__a31oi_4
+   Generating output for cell sky130_fd_sc_hd__and4b_4
+   Generating output for cell sky130_fd_sc_hd__nand3b_4
+   Generating output for cell sky130_fd_sc_hd__o21a_4
+   Generating output for cell sky130_fd_sc_hd__xor2_1
+   Generating output for cell sky130_fd_sc_hd__nor3_4
+   Generating output for cell sky130_fd_sc_hd__o221a_4
+   Generating output for cell sky130_fd_sc_hd__mux2_8
+   Generating output for cell sky130_fd_sc_hd__o31a_4
+   Generating output for cell sky130_fd_sc_hd__and4_2
+   Generating output for cell sky130_fd_sc_hd__a221oi_1
+   Generating output for cell sky130_fd_sc_hd__a221o_4
+   Generating output for cell sky130_fd_sc_hd__a21oi_4
+   Generating output for cell sky130_fd_sc_hd__a21o_4
+   Generating output for cell sky130_fd_sc_hd__inv_6
+   Generating output for cell sky130_fd_sc_hd__a31o_2
+   Generating output for cell sky130_fd_sc_hd__nand4_2
+   Generating output for cell sky130_fd_sc_hd__and4b_2
+   Generating output for cell sky130_fd_sc_hd__xnor2_2
+   Generating output for cell sky130_fd_sc_hd__a21oi_2
+   Generating output for cell sky130_fd_sc_hd__a211o_2
+   Generating output for cell sky130_fd_sc_hd__and3_2
+   Generating output for cell sky130_fd_sc_hd__o211a_2
+   Generating output for cell sky130_fd_sc_hd__o31a_2
+   Generating output for cell sky130_fd_sc_hd__nand3_2
+   Generating output for cell sky130_fd_sc_hd__a21o_2
+   Generating output for cell sky130_fd_sc_hd__a22o_2
+   Generating output for cell sky130_fd_sc_hd__mux2_2
+   Generating output for cell sky130_fd_sc_hd__and2b_4
+   Generating output for cell sky130_fd_sc_hd__and3b_1
+   Generating output for cell sky130_fd_sc_hd__and3b_4
+   Generating output for cell sky130_fd_sc_hd__and2_4
+   Generating output for cell sky130_fd_sc_hd__nand2_4
+   Generating output for cell sky130_fd_sc_hd__nand2_8
+   Generating output for cell sky130_fd_sc_hd__buf_6
+   Generating output for cell sky130_fd_sc_hd__buf_8
+   Generating output for cell housekeeping
+   Generating output for cell sky130_fd_sc_hd__einvp_1
+   Generating output for cell sky130_fd_sc_hd__clkinv_1
+   Generating output for cell sky130_fd_sc_hd__einvn_4
+   Generating output for cell sky130_fd_sc_hd__einvn_8
+   Generating output for cell sky130_fd_sc_hd__einvp_2
+   Generating output for cell sky130_fd_sc_hd__or2_2
+   Generating output for cell sky130_fd_sc_hd__a32o_2
+   Generating output for cell sky130_fd_sc_hd__o2111a_2
+   Generating output for cell sky130_fd_sc_hd__o22a_2
+   Generating output for cell sky130_fd_sc_hd__o221a_2
+   Generating output for cell sky130_fd_sc_hd__nand3b_2
+   Generating output for cell sky130_fd_sc_hd__a21boi_2
+   Generating output for cell sky130_fd_sc_hd__xor2_2
+   Generating output for cell sky130_fd_sc_hd__o2bb2a_2
+   Generating output for cell sky130_fd_sc_hd__nand4b_2
+   Generating output for cell sky130_fd_sc_hd__o21ba_2
+   Generating output for cell sky130_fd_sc_hd__o32a_2
+   Generating output for cell sky130_fd_sc_hd__clkinv_8
+   Generating output for cell digital_pll
+   Generating output for cell user_id_programming
+   Generating output for cell simple_por
+Reading "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ".
+Reading "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB".
+Reading "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC".
+Reading "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS".
+Reading "sky130_fd_pr__pfet_g5v0d10v5_YUHPBG".
+Reading "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV".
+Reading "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM".
+Reading "sky130_fd_pr__pfet_g5v0d10v5_YUHPXE".
+Reading "sky130_fd_sc_hvl__schmittbuf_1".
+Reading "sky130_fd_sc_hvl__buf_8".
+Reading "sky130_fd_sc_hvl__inv_8".
+Reading "sky130_fd_sc_hvl__fill_4".
+Reading "sky130_fd_pr__cap_mim_m3_1_WRT4AW".
+Reading "sky130_fd_pr__cap_mim_m3_2_W5U4AW".
+Reading "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3".
+Reading "simple_por".
+   Generating output for cell mgmt_core_wrapper
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_ef_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__o211a_1".
+Reading "sky130_fd_sc_hd__dfxtp_2".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "sky130_fd_sc_hd__a21o_2".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__a22o_4".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__o21a_2".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__dfxtp_4".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__mux4_1".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__mux4_2".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__and3_2".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__a2bb2o_1".
+Reading "sky130_fd_sc_hd__or3b_1".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__a2bb2o_2".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__o221a_1".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__a211oi_1".
+Reading "sky130_fd_sc_hd__and4_4".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__o21ba_1".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__a311o_1".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__a41o_1".
+Reading "sky130_fd_sc_hd__nor3_2".
+Reading "sky130_fd_sc_hd__or4bb_4".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__or4b_4".
+Reading "sky130_fd_sc_hd__or3b_4".
+Reading "sky130_fd_sc_hd__a31o_1".
+Reading "sky130_fd_sc_hd__a211o_2".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__and4b_4".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "sky130_fd_sc_hd__o21ai_2".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__or4b_1".
+Reading "sky130_fd_sc_hd__o211a_4".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__a21boi_1".
+Reading "sky130_fd_sc_hd__o41ai_4".
+Reading "sky130_fd_sc_hd__o31a_2".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__a31oi_4".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__and4b_2".
+Reading "sky130_fd_sc_hd__o41a_4".
+Reading "sky130_fd_sc_hd__and4bb_2".
+Reading "sky130_fd_sc_hd__clkinv_2".
+Reading "sky130_fd_sc_hd__and2b_2".
+Reading "sky130_fd_sc_hd__or4bb_1".
+Reading "sky130_fd_sc_hd__a21oi_2".
+Reading "sky130_fd_sc_hd__a221oi_1".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "sky130_fd_sc_hd__xor2_4".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__nand3b_4".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__nand4_4".
+Reading "sky130_fd_sc_hd__a32o_2".
+Reading "sky130_fd_sc_hd__nor4_1".
+Reading "sky130_fd_sc_hd__nand4_1".
+Reading "sky130_fd_sc_hd__xor2_1".
+Reading "sky130_fd_sc_hd__and4bb_4".
+Reading "sky130_fd_sc_hd__a41o_2".
+Reading "sky130_fd_sc_hd__o2bb2a_1".
+Reading "sky130_fd_sc_hd__xnor2_2".
+Reading "sky130_fd_sc_hd__xor2_2".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__a2111oi_2".
+Reading "sky130_fd_sc_hd__nor4_4".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__nor4b_1".
+Reading "sky130_fd_sc_hd__o2111ai_4".
+Reading "sky130_fd_sc_hd__nor4_2".
+Reading "sky130_fd_sc_hd__nand3b_2".
+Reading "sky130_fd_sc_hd__nand3_1".
+Reading "sky130_fd_sc_hd__nand2b_2".
+Reading "sky130_fd_sc_hd__o31ai_1".
+Reading "sky130_fd_sc_hd__o41a_1".
+Reading "sky130_fd_sc_hd__a21bo_1".
+Reading "sky130_fd_sc_hd__o41ai_1".
+Reading "sky130_fd_sc_hd__nand3b_1".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__or3b_2".
+Reading "sky130_fd_sc_hd__nand2b_1".
+Reading "sky130_fd_sc_hd__nor4b_4".
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__o41a_2".
+Reading "sky130_fd_sc_hd__or4b_2".
+Reading "sky130_fd_sc_hd__a221o_4".
+Reading "sky130_fd_sc_hd__a2111oi_1".
+Reading "sky130_fd_sc_hd__o31a_4".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "sky130_fd_sc_hd__a221o_2".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__a31o_4".
+Reading "sky130_fd_sc_hd__ebufn_4".
+Reading "sky130_fd_sc_hd__dlxtp_1".
+Reading "sky130_fd_sc_hd__dlclkp_1".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__inv_1".
+Reading "sky130_fd_sc_hd__nor4b_2".
+Reading "sky130_fd_sc_hd__and3b_2".
+Reading "sky130_fd_sc_hd__nor3b_2".
+Reading "RAM256".
+Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__o2111a_4".
+Reading "sky130_fd_sc_hd__a22o_2".
+Reading "sky130_fd_sc_hd__o211ai_4".
+Reading "sky130_fd_sc_hd__o22ai_4".
+Reading "sky130_fd_sc_hd__a221oi_4".
+Reading "sky130_fd_sc_hd__and2b_4".
+Reading "sky130_fd_sc_hd__and3b_4".
+Reading "sky130_fd_sc_hd__and4bb_1".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__o22ai_1".
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__a311o_2".
+Reading "sky130_fd_sc_hd__a2111o_1".
+Reading "sky130_fd_sc_hd__o311a_4".
+Reading "sky130_fd_sc_hd__o2111ai_1".
+Reading "sky130_fd_sc_hd__clkinv_8".
+Reading "sky130_fd_sc_hd__nand3_2".
+Reading "sky130_fd_sc_hd__a22oi_1".
+Reading "sky130_fd_sc_hd__nand4b_4".
+Reading "sky130_fd_sc_hd__o221ai_4".
+Reading "sky130_fd_sc_hd__nand4_2".
+Reading "sky130_fd_sc_hd__inv_6".
+Reading "sky130_fd_sc_hd__o2bb2ai_1".
+Reading "sky130_fd_sc_hd__a311oi_4".
+Reading "sky130_fd_sc_hd__o32ai_4".
+Reading "sky130_fd_sc_hd__o211ai_1".
+Reading "sky130_fd_sc_hd__nand4b_1".
+Reading "sky130_fd_sc_hd__o211ai_2".
+Reading "sky130_fd_sc_hd__a22oi_4".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__a211oi_4".
+Reading "sky130_fd_sc_hd__nor3b_4".
+Reading "sky130_fd_sc_hd__o22a_2".
+Reading "sky130_fd_sc_hd__a2111oi_4".
+Reading "sky130_fd_sc_hd__nand2b_4".
+Reading "sky130_fd_sc_hd__a2bb2o_4".
+Reading "sky130_fd_sc_hd__o2bb2a_2".
+Reading "sky130_fd_sc_hd__o2111ai_2".
+Reading "sky130_fd_sc_hd__a22oi_2".
+Reading "sky130_fd_sc_hd__nor3b_1".
+Reading "sky130_fd_sc_hd__o2bb2a_4".
+Reading "sky130_fd_sc_hd__o21bai_4".
+Reading "sky130_fd_sc_hd__o311ai_1".
+Reading "sky130_fd_sc_hd__a32oi_2".
+Reading "sky130_fd_sc_hd__o2bb2ai_2".
+Reading "sky130_fd_sc_hd__o311ai_4".
+Reading "sky130_fd_sc_hd__o2bb2ai_4".
+Reading "sky130_fd_sc_hd__o31ai_4".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__o2111a_2".
+Reading "sky130_fd_sc_hd__a31oi_2".
+Reading "sky130_fd_sc_hd__o311a_2".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__a32oi_4".
+Reading "sky130_fd_sc_hd__a211oi_2".
+Reading "sky130_fd_sc_hd__o31ai_2".
+Reading "sky130_fd_sc_hd__o221ai_1".
+Reading "sky130_fd_sc_hd__clkinv_16".
+Reading "sky130_fd_sc_hd__or4bb_2".
+Reading "sky130_fd_sc_hd__a221oi_2".
+Reading "sky130_fd_sc_hd__inv_8".
+Reading "sky130_fd_sc_hd__a311oi_2".
+Reading "sky130_fd_sc_hd__a311oi_1".
+Reading "sky130_fd_sc_hd__o311ai_2".
+Reading "sky130_fd_sc_hd__a32oi_1".
+Reading "sky130_fd_sc_hd__a2bb2oi_2".
+Reading "sky130_fd_sc_hd__a2bb2oi_1".
+Reading "sky130_fd_sc_hd__a2bb2oi_4".
+Reading "sky130_fd_sc_hd__xnor2_4".
+Reading "sky130_fd_sc_hd__inv_12".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__a32o_4".
+Reading "sky130_fd_sc_hd__o21ba_2".
+Reading "sky130_fd_sc_hd__a41oi_2".
+Reading "sky130_fd_sc_hd__o22ai_2".
+Reading "sky130_fd_sc_hd__o21bai_2".
+Reading "sky130_fd_sc_hd__a41oi_4".
+Reading "sky130_fd_sc_hd__a41o_4".
+Reading "sky130_fd_sc_hd__a311o_4".
+Reading "sky130_fd_sc_hd__o32ai_1".
+Reading "sky130_fd_sc_hd__a21boi_4".
+Reading "sky130_fd_sc_hd__o32ai_2".
+Reading "sky130_fd_sc_hd__a21bo_2".
+Reading "RAM128".
+Reading "mgmt_core_wrapper".
+   Generating output for cell gpio_defaults_block_0403
+   Generating output for cell gpio_defaults_block_1800
+   Generating output for cell sky130_fd_sc_hd__inv_8
+   Generating output for cell sky130_fd_sc_hd__dfbbp_1
+   Generating output for cell spare_logic_block
+   Generating output for cell sky130_fd_sc_hd__bufbuf_8
+   Generating output for cell sky130_fd_sc_hvl__conb_1
+   Generating output for cell mgmt_protect_hv
+   Generating output for cell mprj_logic_high
+   Generating output for cell mprj2_logic_high
+   Generating output for cell sky130_fd_sc_hd__inv_12
+   Generating output for cell mgmt_protect
+   Generating output for cell gpio_defaults_block_0801
+   Generating output for cell gpio_control_power_routing_top
+   Generating output for cell gpio_control_power_routing_right
+   Generating output for cell gpio_control_power_routing
+   Generating output for cell caravel_power_routing
+   Generating output for cell user_project_wrapper
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_39".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_38".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_33".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_32".
+Reading "sky130_fd_bd_sram__openram_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wmask_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_data_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_29".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_28".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_360_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sli_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w0_740_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m7_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m7_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_delay_chain".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_10".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_rw".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_18".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_6".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_r".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec_0".
+Reading "sky130_fd_bd_sram__openram_dp_nand2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec".
+Reading "sky130_fd_bd_sram__openram_dp_nand3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode3x8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_decoder".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_27".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_26".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_25".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_24".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w2_880_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array_0".
+Reading "sky130_fd_bd_sram__openram_sense_amp".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_sense_amp_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_23".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_21".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_22".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w0_550_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_mask_and_array".
+Reading "sky130_fd_bd_sram__openram_write_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_8".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_row".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_col".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array_0".
+Reading "sky130_fd_bd_sram__openram_dp_cell_dummy".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dummy_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_replica".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column".
+Reading "sky130_fd_bd_sram__openram_dp_cell".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bitcell_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_bitcell_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bank".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8".
+Reading "sky130_fd_sc_hd__o32a_2".
+Reading "sky130_fd_sc_hd__o21ai_2".
+Reading "sky130_ef_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__o2bb2a_2".
+Reading "sky130_fd_sc_hd__a221o_2".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__and4b_2".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__a31oi_2".
+Reading "sky130_fd_sc_hd__or4_2".
+Reading "sky130_fd_sc_hd__or3b_2".
+Reading "sky130_fd_sc_hd__or3_2".
+Reading "sky130_fd_sc_hd__and2b_2".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__xor2_2".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__a22o_2".
+Reading "sky130_fd_sc_hd__o21a_2".
+Reading "sky130_fd_sc_hd__a21oi_2".
+Reading "sky130_fd_sc_hd__nand2b_2".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__a21o_2".
+Reading "sky130_fd_sc_hd__o22a_2".
+Reading "sky130_fd_sc_hd__nand3b_2".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__a311o_2".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__a211o_2".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__clkinv_2".
+Reading "sky130_fd_sc_hd__and3_2".
+Reading "sky130_fd_sc_hd__a32o_2".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__xnor2_2".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__dfrtp_2".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__a2bb2o_2".
+Reading "sky130_fd_sc_hd__a22oi_1".
+Reading "sky130_fd_sc_hd__and4bb_4".
+Reading "sky130_fd_sc_hd__o211ai_4".
+Reading "sky130_fd_sc_hd__nand4_1".
+Reading "sky130_fd_sc_hd__a21bo_2".
+Reading "sky130_fd_sc_hd__nor4b_4".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__o41a_1".
+Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__o22ai_1".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "sky130_fd_sc_hd__a41o_1".
+Reading "sky130_fd_sc_hd__o32a_4".
+Reading "sky130_fd_sc_hd__a22oi_2".
+Reading "sky130_fd_sc_hd__nor4_1".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__a311o_1".
+Reading "sky130_fd_sc_hd__o211ai_2".
+Reading "sky130_fd_sc_hd__o31ai_4".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__a31o_4".
+Reading "sky130_fd_sc_hd__xor2_1".
+Reading "sky130_fd_sc_hd__a21boi_1".
+Reading "sky130_fd_sc_hd__dfstp_2".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__o22ai_4".
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__o2111ai_4".
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "sky130_fd_sc_hd__a21bo_1".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__o211a_1".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__o22ai_2".
+Reading "sky130_fd_sc_hd__a2111o_1".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__o21ba_1".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__o221a_1".
+Reading "sky130_fd_sc_hd__o31a_2".
+Reading "sky130_fd_sc_hd__a22oi_4".
+Reading "sky130_fd_sc_hd__dfxtp_4".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__mux4_2".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__or3b_1".
+Reading "sky130_fd_sc_hd__a22o_4".
+Reading "sky130_fd_sc_hd__a211oi_4".
+Reading "sky130_fd_sc_hd__a221oi_1".
+Reading "sky130_fd_sc_hd__a221oi_4".
+Reading "sky130_fd_sc_hd__o311a_2".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__a31o_1".
+Reading "sky130_fd_sc_hd__dfxtp_2".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__o2bb2a_1".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__a211oi_1".
+Reading "sky130_fd_sc_hd__mux4_1".
+Reading "sky130_fd_sc_hd__and4bb_1".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__or4_4".
+Reading "sky130_fd_sc_hd__or3_1".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__or4b_4".
+Reading "sky130_fd_sc_hd__or3_4".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__or4b_1".
+Reading "sky130_fd_sc_hd__nor4_4".
+Reading "sky130_fd_sc_hd__nand3_1".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__a2bb2o_1".
+Reading "sky130_fd_sc_hd__dfstp_1".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__or4_1".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_fd_sc_hd__dfrtp_1".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__o31ai_1".
+Reading "sky130_fd_sc_hd__nand2b_1".
+Reading "sky130_fd_sc_hd__a311oi_1".
+Reading "sky130_fd_sc_hd__nand2b_4".
+Reading "sky130_fd_sc_hd__or4bb_1".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__nor3_2".
+Reading "sky130_fd_sc_hd__nand4b_1".
+Reading "sky130_fd_sc_hd__xor2_4".
+Reading "sky130_fd_sc_hd__o21ba_2".
+Reading "sky130_fd_sc_hd__a2111o_2".
+Reading "sky130_fd_sc_hd__or3b_4".
+Reading "sky130_fd_sc_hd__a31oi_4".
+Reading "sky130_fd_sc_hd__nand3b_1".
+Reading "sky130_fd_sc_hd__nor4b_2".
+Reading "sky130_fd_sc_hd__a41o_2".
+Reading "sky130_fd_sc_hd__nor3b_4".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__a2111oi_4".
+Reading "sky130_fd_sc_hd__o32ai_1".
+Reading "sky130_fd_sc_hd__and4bb_2".
+Reading "sky130_fd_sc_hd__or4b_2".
+Reading "sky130_fd_sc_hd__nor3b_1".
+Reading "sky130_fd_sc_hd__nor4_2".
+Reading "sky130_fd_sc_hd__a311oi_4".
+Reading "sky130_fd_sc_hd__o21bai_2".
+Reading "sky130_fd_sc_hd__nor3b_2".
+Reading "sky130_fd_sc_hd__a311oi_2".
+Reading "sky130_fd_sc_hd__and3b_4".
+Reading "sky130_fd_sc_hd__a2bb2o_4".
+Reading "sky130_fd_sc_hd__a21bo_4".
+Reading "sky130_fd_sc_hd__xnor2_4".
+Reading "sky130_fd_sc_hd__o311ai_4".
+Reading "sky130_fd_sc_hd__o2bb2a_4".
+Reading "sky130_fd_sc_hd__o211a_4".
+Reading "sky130_fd_sc_hd__and2b_4".
+Reading "sky130_fd_sc_hd__o21bai_4".
+Reading "sky130_fd_sc_hd__nand3b_4".
+Reading "sky130_fd_sc_hd__o2111ai_1".
+Reading "sky130_fd_sc_hd__nand4_4".
+Reading "sky130_fd_sc_hd__o221ai_2".
+Reading "sky130_fd_sc_hd__o211ai_1".
+Reading "sky130_fd_sc_hd__o2bb2ai_4".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__nor4b_1".
+Reading "sky130_fd_sc_hd__o2111a_2".
+Reading "ycr_core_top".
+Reading "sky130_fd_sc_hd__and3b_2".
+Reading "sky130_fd_sc_hd__nand4_2".
+Reading "sky130_fd_sc_hd__o31ai_2".
+Reading "sky130_fd_sc_hd__nand3_2".
+Reading "sky130_fd_sc_hd__or2b_1".
+Reading "sky130_fd_sc_hd__o2bb2ai_2".
+Reading "sky130_fd_sc_hd__or2b_2".
+Reading "sky130_fd_sc_hd__and4_4".
+Reading "sky130_fd_sc_hd__a221o_4".
+Reading "sky130_fd_sc_hd__or4bb_4".
+Reading "sky130_fd_sc_hd__or2b_4".
+Reading "sky130_fd_sc_hd__o41ai_4".
+Reading "sky130_fd_sc_hd__a21boi_4".
+Reading "sky130_fd_sc_hd__o221ai_1".
+Reading "sky130_fd_sc_hd__o31a_4".
+Reading "sky130_fd_sc_hd__buf_1".
+Reading "sky130_fd_sc_hd__dlygate4sd1_1".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "ycr4_iconnect".
+Reading "sky130_fd_sc_hd__a2111oi_2".
+Reading "sky130_fd_sc_hd__a2111oi_1".
+Reading "sky130_fd_sc_hd__o2bb2ai_1".
+Reading "sky130_fd_sc_hd__o41a_4".
+Reading "sky130_fd_sc_hd__nand4b_4".
+Reading "sky130_fd_sc_hd__a32o_4".
+Reading "sky130_fd_sc_hd__or4bb_2".
+Reading "ycr_intf".
+Reading "switchn".
+Reading "resistor".
+Reading "resistor_3xh".
+Reading "switch2".
+Reading "switch2n".
+Reading "2bit_DAC".
+Reading "resistor_h".
+Reading "3bit_DAC".
+Reading "4bit_DAC".
+Reading "5bit_DAC".
+Reading "6bit_DAC".
+Reading "7bit_DAC".
+Reading "8bit_DAC".
+Reading "2x8bit_DAC".
+Reading "4x8bit_DAC".
+Reading "dac_top".
+Reading "sky130_fd_sc_hd__einvn_8".
+Reading "sky130_fd_sc_hd__clkinv_1".
+Reading "sky130_fd_sc_hd__einvp_2".
+Reading "sky130_fd_sc_hd__einvn_2".
+Reading "sky130_fd_sc_hd__a21boi_2".
+Reading "sky130_fd_sc_hd__clkinv_8".
+Reading "sky130_fd_sc_hd__einvp_1".
+Reading "dg_pll".
+Reading "sky130_fd_sc_hd__a41oi_4".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__o311a_4".
+Reading "sky130_fd_sc_hd__o221a_4".
+Reading "sky130_fd_sc_hd__a41o_4".
+Reading "wb_interconnect".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "sky130_fd_sc_hd__o41a_2".
+Reading "sky130_fd_sc_hd__a211oi_2".
+Reading "sky130_fd_sc_hd__clkdlybuf4s50_1".
+Reading "qspim_top".
+Reading "sky130_fd_sc_hd__dlclkp_1".
+Reading "sky130_fd_sc_hd__dlclkp_4".
+Reading "sky130_fd_sc_hd__a32oi_4".
+Reading "sky130_fd_sc_hd__o311ai_2".
+Reading "sky130_fd_sc_hd__o2111ai_2".
+Reading "wb_host".
+Reading "sky130_fd_sc_hd__and4b_4".
+Reading "sky130_fd_sc_hd__nor2b_2".
+Reading "sky130_fd_sc_hd__nor2b_1".
+Reading "uart_i2c_usb_spi_top".
+Reading "sky130_fd_sc_hd__dlxtn_1".
+Reading "sky130_fd_sc_hd__dlxtn_2".
+Reading "sky130_fd_sc_hd__nand4b_2".
+Reading "sky130_fd_sc_hd__a32oi_1".
+Reading "pinmux_top".
+Reading "user_project_wrapper".
+   Generating output for cell sky130_ef_io__com_bus_slice_20um
+   Generating output for cell sky130_fd_io__corner_bus_overlay
+   Generating output for cell sky130_ef_io__corner_pad
+   Generating output for cell sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um
+   Generating output for cell sky130_ef_io__com_bus_slice_1um
+   Generating output for cell sky130_ef_io__com_bus_slice_5um
+   Generating output for cell sky130_ef_io__com_bus_slice_10um
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_5595914180851
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808664
+   Generating output for cell sky130_fd_io__sio_clamp_pcap_4x5
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808680
+   Generating output for cell sky130_fd_io__esd_rcclamp_nfetcap
+   Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808336
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_55959141808666
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808665
+   Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808678
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_55959141808679
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808677
+   Generating output for cell sky130_fd_pr__via_pol1__example_5595914180839
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808667
+   Generating output for cell sky130_fd_pr__hvdftpl1s__example_55959141808671
+   Generating output for cell sky130_fd_pr__hvdftpl1s2__example_55959141808672
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808673
+   Generating output for cell sky130_fd_pr__dfl1__example_55959141808663
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808660
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808670
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808668
+   Generating output for cell sky130_fd_pr__hvdftpl1s__example_55959141808675
+   Generating output for cell sky130_fd_pr__hvdftpl1s2__example_55959141808676
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808674
+   Generating output for cell sky130_fd_pr__dfl1__example_55959141808662
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808661
+   Generating output for cell sky130_fd_pr__via_l1m1__example_559591418084
+   Generating output for cell sky130_fd_pr__genrivetdlring__example_559591418082
+   Generating output for cell sky130_fd_pr__gendlring__example_559591418081
+   Generating output for cell sky130_fd_pr__padplhp__example_559591418080
+   Generating output for cell sky130_fd_io__pad_esd
+   Generating output for cell sky130_fd_io__com_bus_slice
+   Generating output for cell sky130_fd_io__com_bus_hookup
+   Generating output for cell sky130_fd_io__com_busses_esd
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808669
+   Generating output for cell sky130_fd_io__top_ground_hvc_wpad
+   Generating output for cell sky130_fd_io__overlay_vssa_hvc
+   Generating output for cell sky130_ef_io__hvc_vdda_overlay
+   Generating output for cell sky130_ef_io__vssa_hvc_clamped_pad
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808719
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808767
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808765
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808764
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808720
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808718
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808717
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808716
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808243
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808723
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808722
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_5595914180890
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808721
+   Generating output for cell sky130_fd_io__xres_inv_hysv2
+   Generating output for cell sky130_fd_pr__res_generic_po__example_5595914180838
+   Generating output for cell sky130_fd_io__tk_tie_r_out_esd
+   Generating output for cell sky130_fd_io__res250_sub_small
+   Generating output for cell sky130_fd_io__res250only_small
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808264
+   Generating output for cell sky130_fd_pr__via_l1m1__example_5595914180858
+   Generating output for cell sky130_fd_pr__via_pol1__example_5595914180833
+   Generating output for cell sky130_fd_pr__res_generic_po__example_5595914180864
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808715
+   Generating output for cell sky130_fd_pr__res_bent_po__example_5595914180863
+   Generating output for cell sky130_fd_pr__res_bent_po__example_5595914180862
+   Generating output for cell sky130_fd_io__tk_em1s_cdns_55959141808288
+   Generating output for cell sky130_fd_io__tk_em1s_cdns_5595914180859
+   Generating output for cell sky130_fd_io__tk_em1o_cdns_55959141808289
+   Generating output for cell sky130_fd_io__com_res_weak_v2
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808274
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808728
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808727
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808726
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808725
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808724
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808554
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808553
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808552
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808551
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808402
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808350
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808261
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808260
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808259
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808400
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808372
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808326
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808290
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808128
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808127
+   Generating output for cell sky130_fd_pr__via_l1m1__example_5595914180897
+   Generating output for cell sky130_fd_pr__dfl1sd__example_5595914180819
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808555
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808147
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808157
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808156
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808155
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808154
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808153
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808152
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808151
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808150
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808149
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808148
+   Generating output for cell sky130_fd_pr__dfl1__example_55959141808158
+   Generating output for cell sky130_fd_io__signal_5_sym_hv_local_5term
+   Generating output for cell sky130_fd_io__gpio_buf_localesdv2
+   Generating output for cell sky130_fd_pr__via_pol1__example_559591418083
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808137
+   Generating output for cell sky130_fd_pr__dfl1sd__example_559591418086
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808371
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808370
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808369
+   Generating output for cell sky130_fd_io__hvsbt_inv_x1
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808316
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808421
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808385
+   Generating output for cell sky130_fd_pr__dfl1sd__example_559591418088
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808422
+   Generating output for cell sky130_fd_io__hvsbt_inv_x2
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808612
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808616
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808615
+   Generating output for cell sky130_fd_io__hvsbt_inv_x4
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_5595914180848
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_5595914180849
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808766
+   Generating output for cell sky130_fd_pr__via_m2m3__example_55959141808714
+   Generating output for cell sky130_fd_pr__via_pol1_centered__example_559591418081
+   Generating output for cell sky130_fd_io__tk_em2s_cdns_55959141808652
+   Generating output for cell sky130_fd_io__tk_em2o_cdns_55959141808653
+   Generating output for cell sky130_fd_pr__via_l1m1_centered__example_5595914180812
+   Generating output for cell sky130_fd_pr__via_l1m1_centered__example_5595914180811
+   Generating output for cell sky130_fd_pr__via_l1m1_centered__example_559591418086
+   Generating output for cell sky130_fd_pr__via_l1m1_centered__example_559591418084
+   Generating output for cell sky130_fd_pr__hvdftpm1s2__example_55959141808659
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808658
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808657
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808202
+   Generating output for cell sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2
+   Generating output for cell sky130_fd_io__gpio_pudrvr_strong_axres4v2
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808273
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808740
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808739
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808738
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808737
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808736
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808735
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808734
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808733
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808732
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808731
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808730
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808752
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808751
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808750
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808749
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808748
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808747
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808746
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808745
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808744
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808743
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808742
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808741
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808324
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808270
+   Generating output for cell sky130_fd_pr__dfl1__example_55959141808187
+   Generating output for cell sky130_fd_pr__res_generic_nd__example_55959141808755
+   Generating output for cell sky130_fd_pr__res_generic_nd__example_55959141808754
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808338
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808337
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808763
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808700
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808559
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808762
+   Generating output for cell sky130_fd_pr__dfl1__example_55959141808729
+   Generating output for cell sky130_fd_io__xres_tk_p_em1o_cdns_55959141808758
+   Generating output for cell sky130_fd_io__xres_tk_p_em1o_cdns_55959141808757
+   Generating output for cell sky130_fd_io__xres_tk_p_em1o_cdns_55959141808756
+   Generating output for cell sky130_fd_io__xres_tk_p_em1c_cdns_55959141808761
+   Generating output for cell sky130_fd_io__xres_tk_p_em1c_cdns_55959141808760
+   Generating output for cell sky130_fd_io__xres_tk_p_em1c_cdns_55959141808759
+   Generating output for cell sky130_fd_io__xres_p_em1c_cdns_55959141808753
+   Generating output for cell sky130_fd_io__xres2v2_rcfilter_lpfv2
+   Generating output for cell sky130_fd_io__tk_em1o_cdns_5595914180860
+   Generating output for cell sky130_fd_pr__res_bent_po__example_5595914180861
+   Generating output for cell sky130_fd_io__com_res_weak_bentbigres
+   Generating output for cell sky130_fd_io__com_res_weak
+   Generating output for cell sky130_fd_pr__via_l1m1__example_5595914180857
+   Generating output for cell sky130_fd_pr__hvdftpm1s2__example_55959141808649
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808651
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808650
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808648
+   Generating output for cell sky130_fd_pr__hvdftpl1s__example_55959141808646
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808647
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808645
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808378
+   Generating output for cell sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2
+   Generating output for cell sky130_fd_io__gpio_pddrvr_strong_xres4v2
+   Generating output for cell sky130_fd_io__top_gpio_pad
+   Generating output for cell sky130_fd_io__com_busses
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808768
+   Generating output for cell sky130_fd_pr__res_bent_nd__example_55959141808769
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808787
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808786
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808782
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808785
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808449
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808784
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808452
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808783
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808781
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808780
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808779
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808233
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_5595914180827
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808778
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_5595914180835
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808777
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808776
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808775
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808242
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808774
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_5595914180829
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808773
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808237
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808772
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808771
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808770
+   Generating output for cell sky130_fd_io__tap_1
+   Generating output for cell sky130_fd_io__inv_1
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_559591418085
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_559591418089
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_559591418087
+   Generating output for cell sky130_fd_io__hvsbt_nand2
+   Generating output for cell sky130_fd_io__xres4v2_in_buf
+   Generating output for cell sky130_fd_io__top_xres4v2
+   Generating output for cell sky130_fd_sc_hd__fill_4
+   Generating output for cell sky130_fd_sc_hd__fill_8
+   Generating output for cell constant_block
+   Generating output for cell sky130_fd_io__res75only_small
+   Generating output for cell sky130_fd_io__com_bus_slice_m4
+   Generating output for cell sky130_fd_io__overlay_gpiov2_m4
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808420
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808419
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808418
+   Generating output for cell sky130_fd_io__hvsbt_nor
+   Generating output for cell sky130_fd_io__hvsbt_nand2v2
+   Generating output for cell sky130_fd_io__gpiov2_ictl_logic
+   Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808190
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808611
+   Generating output for cell sky130_fd_pr__dfl1sd__example_5595914180811
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808549
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808548
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_55959141808191
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808189
+   Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808517
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_55959141808518
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808610
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808609
+   Generating output for cell sky130_fd_pr__dfl1sd__example_5595914180815
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_5595914180816
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808608
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808604
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808533
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808529
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_5595914180884
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808230
+   Generating output for cell sky130_fd_io__gpiov2_in_buf
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808537
+   Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808106
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808481
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808607
+   Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808504
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808600
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808550
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808528
+   Generating output for cell sky130_fd_io__gpiov2_ipath_hvls
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808595
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_5595914180825
+   Generating output for cell sky130_fd_io__gpiov2_inbuf_lvinv_x1
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_5595914180812
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808599
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808598
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808597
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808596
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808547
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808546
+   Generating output for cell sky130_fd_io__gpiov2_ipath_lvls
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808606
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_5595914180875
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808605
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808540
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808603
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808602
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808601
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808535
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808527
+   Generating output for cell sky130_fd_io__gpiov2_vcchib_in_buf
+   Generating output for cell sky130_fd_io__gpiov2_ibuf_se
+   Generating output for cell sky130_fd_io__gpiov2_buf_localesd
+   Generating output for cell sky130_fd_io__gpiov2_ipath
+   Generating output for cell sky130_fd_io__tk_em2s_cdns_55959141808438
+   Generating output for cell sky130_fd_io__tk_em2o_cdns_55959141808439
+   Generating output for cell sky130_fd_io__tk_em1s_cdns_5595914180882
+   Generating output for cell sky130_fd_io__tk_em1s_cdns_5595914180881
+   Generating output for cell sky130_fd_io__tk_em1o_cdns_5595914180880
+   Generating output for cell sky130_fd_io__tk_em1o_cdns_5595914180879
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808430
+   Generating output for cell sky130_fd_pr__dfl1sd__example_5595914180823
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_5595914180822
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_5595914180813
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808624
+   Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808510
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808623
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808622
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808621
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808620
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808619
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808618
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808116
+   Generating output for cell sky130_fd_io__com_ctl_lsv2
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808394
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808298
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808440
+   Generating output for cell sky130_fd_pr__via_l1m1__example_5595914180878
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808434
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808435
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808433
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808432
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808102
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808431
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808115
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808429
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808428
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808100
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808140
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808427
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808426
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808280
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808425
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808424
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808423
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808306
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808383
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808382
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808380
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808379
+   Generating output for cell sky130_fd_io__com_ctl_ls_v2
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808617
+   Generating output for cell sky130_fd_io__com_ctl_ls_en_1_v2
+   Generating output for cell sky130_fd_io__com_ctl_ls_1v2
+   Generating output for cell sky130_fd_io__gpiov2_ctl_lsbank
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808614
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808613
+   Generating output for cell sky130_fd_io__hvsbt_inv_x8v2
+   Generating output for cell sky130_fd_io__hvsbt_inv_x8
+   Generating output for cell sky130_fd_io__com_ctl_ls
+   Generating output for cell sky130_fd_io__com_ctl_hldv2
+   Generating output for cell sky130_fd_io__gpiov2_ctl
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808178
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808591
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808594
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808593
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808488
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808592
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808586
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808122
+   Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808123
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808477
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808476
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808475
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808589
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808570
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808569
+   Generating output for cell sky130_fd_io__gpiov2_amux_ctl_lshv2hv
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808588
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808587
+   Generating output for cell sky130_fd_io__gpiov2_amux_ctl_lshv2hv2
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808590
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808460
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808468
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808467
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808466
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808465
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808464
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808463
+   Generating output for cell sky130_fd_io__gpiov2_amux_ctl_ls
+   Generating output for cell sky130_fd_io__gpiov2_amux_ctl_inv_1
+   Generating output for cell sky130_fd_io__gpiov2_amux_ls
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808573
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808572
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808579
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808578
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808577
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808576
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808566
+   Generating output for cell sky130_fd_pr__dfl1sd__example_5595914180868
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_5595914180869
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808565
+   Generating output for cell sky130_fd_io__gpiov2_amx_pucsd_inv
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808441
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808571
+   Generating output for cell sky130_fd_io__gpiov2_amx_inv4
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808567
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808568
+   Generating output for cell sky130_fd_io__gpiov2_amux_drvr_lshv2hv
+   Generating output for cell sky130_fd_io__gpiov2_amux_drvr_lshv2hv2
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808581
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808580
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808278
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808462
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808583
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808582
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808498
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808497
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808496
+   Generating output for cell sky130_fd_io__gpiov2_amux_drvr_ls
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808574
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808575
+   Generating output for cell sky130_fd_io__amx_inv1
+   Generating output for cell sky130_fd_io__gpiov2_amux_drvr
+   Generating output for cell sky130_fd_io__xor2_1
+   Generating output for cell sky130_fd_io__nor2_1
+   Generating output for cell sky130_fd_io__nand2_1
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808200
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808457
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808451
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808450
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_5595914180894
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808584
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808455
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808447
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808445
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808248
+   Generating output for cell sky130_fd_io__gpiov2_amux_nand5
+   Generating output for cell sky130_fd_pr__dfm1sd__example_55959141808258
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808585
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808446
+   Generating output for cell sky130_fd_io__gpiov2_amux_nand4
+   Generating output for cell sky130_fd_io__gpiov2_amux_decoder
+   Generating output for cell sky130_fd_io__gpiov2_amux_ctl_logic
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808563
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808564
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808562
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808251
+   Generating output for cell sky130_fd_pr__dfm1sd2__example_55959141808561
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808560
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808558
+   Generating output for cell sky130_fd_io__amux_switch_1v2b
+   Generating output for cell sky130_fd_io__gpiov2_amux
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808416
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808417
+   Generating output for cell sky130_fd_io__hvsbt_xorv2
+   Generating output for cell sky130_fd_io__hvsbt_xor
+   Generating output for cell sky130_fd_io__com_ctl_ls_octl
+   Generating output for cell sky130_fd_io__gpiov2_octl
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808267
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808266
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808642
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808184
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808141
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808643
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808183
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808139
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808636
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808635
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808634
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_55959141808633
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808632
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808630
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808638
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808637
+   Generating output for cell sky130_fd_io__gpiov2_pdpredrvr_strong_nr3
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808629
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808628
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808627
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808626
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808354
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808631
+   Generating output for cell sky130_fd_io__gpiov2_pdpredrvr_strong_nr2
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_5595914180888
+   Generating output for cell sky130_fd_io__gpiov2_octl_mux
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808322
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808321
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808320
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808294
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808325
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808323
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808291
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808641
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808640
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808639
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808348
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808347
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808194
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808346
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808345
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808344
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808343
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808334
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808333
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808332
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808331
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808330
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808329
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808304
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808134
+   Generating output for cell sky130_fd_io__tk_em1o_cdns_55959141808328
+   Generating output for cell sky130_fd_io__tk_em1o_cdns_55959141808327
+   Generating output for cell sky130_fd_io__com_pdpredrvr_pbiasv2
+   Generating output for cell sky130_fd_io__gpiov2_pdpredrvr_strong
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808272
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808271
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808143
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808142
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808101
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808144
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_5595914180899
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808275
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808276
+   Generating output for cell sky130_fd_pr__res_generic_po__example_55959141808286
+   Generating output for cell sky130_fd_pr__res_generic_po__example_55959141808285
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808284
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808283
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808644
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808287
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808282
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808281
+   Generating output for cell sky130_fd_io__gpiov2_pupredrvr_strong_nd2_a
+   Generating output for cell sky130_fd_io__gpiov2_pupredrvr_strong_nd2
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808297
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808296
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808295
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808293
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808292
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808300
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808299
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808319
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808318
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808317
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808315
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808314
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808313
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808312
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808311
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808310
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808309
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808308
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808307
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808305
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808303
+   Generating output for cell sky130_fd_io__tk_em1s_cdns_55959141808301
+   Generating output for cell sky130_fd_io__tk_em1o_cdns_55959141808302
+   Generating output for cell sky130_fd_io__feascom_pupredrvr_nbiasv2
+   Generating output for cell sky130_fd_io__gpio_pupredrvr_strongv2
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808361
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808360
+   Generating output for cell sky130_fd_io__feas_com_pupredrvr_weak
+   Generating output for cell sky130_fd_pr__via_pol1__example_5595914180854
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808363
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808362
+   Generating output for cell sky130_fd_io__com_pupredrvr_strong_slowv2
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808366
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808365
+   Generating output for cell sky130_fd_io__com_pdpredrvr_weakv2
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808364
+   Generating output for cell sky130_fd_io__com_pdpredrvr_strong_slowv2
+   Generating output for cell sky130_fd_io__gpiov2_obpredrvr
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808368
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808625
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808373
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808374
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808393
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808392
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808391
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808390
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808389
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808388
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808387
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808386
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808384
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808381
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808377
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808376
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808375
+   Generating output for cell sky130_fd_io__gpio_dat_lsv2
+   Generating output for cell sky130_fd_io__gpio_dat_ls_1v2
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808398
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808397
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808396
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808395
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808401
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808399
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808269
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808410
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808409
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808408
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808407
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808406
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808405
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808404
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808403
+   Generating output for cell sky130_fd_io__com_cclat
+   Generating output for cell sky130_fd_io__com_opath_datoev2
+   Generating output for cell sky130_fd_io__gpiov2_octl_dat
+   Generating output for cell sky130_fd_pr__via_pol1_centered__example_559591418080
+   Generating output for cell sky130_fd_pr__via_l1m1__example_5595914180832
+   Generating output for cell sky130_fd_pr__res_generic_po__example_5595914180856
+   Generating output for cell sky130_fd_pr__res_generic_po__example_5595914180855
+   Generating output for cell sky130_fd_pr__res_generic_po__example_5595914180853
+   Generating output for cell sky130_fd_io__tk_em1s_cdns_5595914180852
+   Generating output for cell sky130_fd_pr__via_l1m1_centered__example_559591418083
+   Generating output for cell sky130_fd_pr__via_l1m1_centered__example_559591418082
+   Generating output for cell sky130_fd_io__nfet_con_diff_wo_abt_270v2
+   Generating output for cell sky130_fd_io__gpiov2_pddrvr_strong
+   Generating output for cell sky130_fd_pr__via_l1m1_centered__example_559591418085
+   Generating output for cell sky130_fd_io__pfet_con_diff_wo_abt_270v2
+   Generating output for cell sky130_fd_io__gpio_pudrvr_strongv2
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_5595914180850
+   Generating output for cell sky130_fd_io__gpio_pddrvr_weakv2
+   Generating output for cell sky130_fd_io__gpio_pddrvr_strong_slowv2
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808656
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808655
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808654
+   Generating output for cell sky130_fd_io__com_pudrvr_weakv2
+   Generating output for cell sky130_fd_io__com_pudrvr_strong_slowv2
+   Generating output for cell sky130_fd_io__gpio_odrvr_subv2
+   Generating output for cell sky130_fd_io__gpio_odrvrv2
+   Generating output for cell sky130_fd_io__gpio_opathv2
+   Generating output for cell sky130_fd_io__top_gpiov2
+   Generating output for cell sky130_fd_io__overlay_gpiov2
+   Generating output for cell sky130_ef_io__gpiov2_pad
+   Generating output for cell sky130_ef_io__gpiov2_pad_wrapped
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808691
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808687
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808684
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808686
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808685
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808683
+   Generating output for cell sky130_fd_io__gnd2gnd_strap
+   Generating output for cell sky130_fd_io__gnd2gnd_tap
+   Generating output for cell sky130_fd_io__gnd2gnd_diff
+   Generating output for cell sky130_fd_io__gnd2gnd_sub_dnwl
+   Generating output for cell sky130_fd_io__gnd2gnd_120x2_lv_isosub
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808690
+   Generating output for cell sky130_fd_pr__dftpl1s2__example_55959141808702
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808705
+   Generating output for cell sky130_fd_pr__dfl1__example_55959141808682
+   Generating output for cell sky130_fd_pr__dftpl1s2__example_55959141808694
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808693
+   Generating output for cell sky130_fd_pr__dfl1__example_55959141808681
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808688
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808699
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808698
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808697
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808696
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808695
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808704
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808703
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808701
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808689
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808692
+   Generating output for cell sky130_fd_io__top_ground_lvc_wpad
+   Generating output for cell sky130_fd_io__overlay_vssd_lvc
+   Generating output for cell sky130_ef_io__lvc_vccdx_overlay
+   Generating output for cell sky130_ef_io__vssd_lvc_clamped_pad
+   Generating output for cell sky130_fd_io__overlay_vssio_hvc
+   Generating output for cell sky130_ef_io__hvc_vssio_overlay
+   Generating output for cell sky130_ef_io__vssio_hvc_clamped_pad
+   Generating output for cell sky130_fd_io__hvc_clampv2
+   Generating output for cell sky130_fd_io__top_power_hvc_wpadv2
+   Generating output for cell sky130_fd_io__overlay_vdda_hvc
+   Generating output for cell sky130_ef_io__vdda_hvc_clamped_pad
+   Generating output for cell sky130_fd_io__top_power_lvc_wpad
+   Generating output for cell sky130_fd_io__overlay_vccd_lvc
+   Generating output for cell sky130_ef_io__vccd_lvc_clamped_pad
+   Generating output for cell sky130_ef_io__disconnect_vdda_slice_5um
+   Generating output for cell sky130_fd_io__overlay_vddio_hvc
+   Generating output for cell sky130_ef_io__hvc_vddio_overlay
+   Generating output for cell sky130_ef_io__vddio_hvc_clamped_pad
+   Generating output for cell chip_io_gpio_connects
+   Generating output for cell sky130_ef_io__lvc_vccdy_overlay
+   Generating output for cell sky130_ef_io__vssd_lvc_clamped3_pad
+   Generating output for cell sky130_ef_io__vccd_lvc_clamped3_pad
+   Generating output for cell chip_io
+   Generating output for cell gpio_signal_buffering
+   Generating output for cell caravel
diff --git a/tapeout/logs/tools.info b/tapeout/logs/tools.info
new file mode 100644
index 0000000..a1b78f5
--- /dev/null
+++ b/tapeout/logs/tools.info
@@ -0,0 +1,2 @@
+KLayout: 0.27.12
+Magic: 8.3.346
\ No newline at end of file
diff --git a/tapeout/logs/uncompress.log b/tapeout/logs/uncompress.log
new file mode 100644
index 0000000..cf8015b
--- /dev/null
+++ b/tapeout/logs/uncompress.log
@@ -0,0 +1,5 @@
+make: Nothing to be done for `check-env'.
+gds/user_project_wrapper.gds.gz -> gds/user_project_wrapper.gds
+lef/user_project_wrapper.lef.gz -> lef/user_project_wrapper.lef
+verilog/gl/user_project_wrapper.v.gz -> verilog/gl/user_project_wrapper.v
+All files are uncompressed!
diff --git a/tapeout/outputs/gds/caravel_00088bca.gds.gz.00.split b/tapeout/outputs/gds/caravel_00088bca.gds.gz.00.split
new file mode 100644
index 0000000..260b7ed
--- /dev/null
+++ b/tapeout/outputs/gds/caravel_00088bca.gds.gz.00.split
Binary files differ
diff --git a/tapeout/outputs/gds/caravel_00088bca.gds.gz.01.split b/tapeout/outputs/gds/caravel_00088bca.gds.gz.01.split
new file mode 100644
index 0000000..9719e13
--- /dev/null
+++ b/tapeout/outputs/gds/caravel_00088bca.gds.gz.01.split
Binary files differ
diff --git a/tapeout/outputs/gds/caravel_00088bca.gds.gz.02.split b/tapeout/outputs/gds/caravel_00088bca.gds.gz.02.split
new file mode 100644
index 0000000..370c3b9
--- /dev/null
+++ b/tapeout/outputs/gds/caravel_00088bca.gds.gz.02.split
Binary files differ
diff --git a/tapeout/outputs/gds/caravel_00088bca.gds.gz.03.split b/tapeout/outputs/gds/caravel_00088bca.gds.gz.03.split
new file mode 100644
index 0000000..edef3f7
--- /dev/null
+++ b/tapeout/outputs/gds/caravel_00088bca.gds.gz.03.split
Binary files differ
diff --git a/tapeout/outputs/gds/caravel_00088bca.gds.gz.04.split b/tapeout/outputs/gds/caravel_00088bca.gds.gz.04.split
new file mode 100644
index 0000000..01a076a
--- /dev/null
+++ b/tapeout/outputs/gds/caravel_00088bca.gds.gz.04.split
Binary files differ
diff --git a/tapeout/outputs/gds/caravel_00088bca.gds.gz.05.split b/tapeout/outputs/gds/caravel_00088bca.gds.gz.05.split
new file mode 100644
index 0000000..3168425
--- /dev/null
+++ b/tapeout/outputs/gds/caravel_00088bca.gds.gz.05.split
Binary files differ
diff --git a/tapeout/outputs/gds/caravel_00088bca.gds.gz.06.split b/tapeout/outputs/gds/caravel_00088bca.gds.gz.06.split
new file mode 100644
index 0000000..1eb9a06
--- /dev/null
+++ b/tapeout/outputs/gds/caravel_00088bca.gds.gz.06.split
Binary files differ
diff --git a/tapeout/outputs/klayout_beol_report.xml b/tapeout/outputs/klayout_beol_report.xml
new file mode 100644
index 0000000..fc54931
--- /dev/null
+++ b/tapeout/outputs/klayout_beol_report.xml
@@ -0,0 +1,447 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/scripts/tech/sky130A_mr.drc'</generator>
+ <top-cell>caravel_00088bca</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>li.1</name>
+   <description>li.1 : min. li width : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.3</name>
+   <description>li.3 : min. li spacing : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.5</name>
+   <description>li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.6</name>
+   <description>li.6 : min. li area : 0.0561um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1</name>
+   <description>ct.1: non-ring mcon should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1_a</name>
+   <description>ct.1_a : minimum width of mcon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1_b</name>
+   <description>ct.1_b : maximum length of mcon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.2</name>
+   <description>ct.2 : min. mcon spacing : 0.19um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.4</name>
+   <description>ct.4 : mcon should covered by li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.1</name>
+   <description>m1.1 : min. m1 width : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.2</name>
+   <description>m1.2 : min. m1 spacing : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.3ab</name>
+   <description>m1.3ab : min. 3um.m1 spacing m1 : 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>791_m1.4</name>
+   <description>791_m1.4 : min. m1 enclosure of mcon : 0.03um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4</name>
+   <description>m1.4 : mcon periphery must be enclosed by m1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4a</name>
+   <description>m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4a_a</name>
+   <description>m1.4a_a : mcon periph must be enclosed by met1 for specific cells</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.6</name>
+   <description>m1.6 : min. m1 area : 0.083um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.7</name>
+   <description>m1.7 : min. m1 with holes area : 0.14um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.5</name>
+   <description>m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a</name>
+   <description>via.1a : via outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a_a</name>
+   <description>via.1a_a : min. width of via outside of moduleCut : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a_b</name>
+   <description>via.1a_b : maximum length of via : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.2</name>
+   <description>via.2 : min. via spacing : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.4a</name>
+   <description>via.4a : min. m1 enclosure of 0.15um via : 0.055um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.4a_a</name>
+   <description>via.4a_a : 0.15um via must be enclosed by met1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.5a</name>
+   <description>via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.1</name>
+   <description>m2.1 : min. m2 width : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.2</name>
+   <description>m2.2 : min. m2 spacing : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.3ab</name>
+   <description>m2.3ab : min. 3um.m2 spacing m2 : 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.6</name>
+   <description>m2.6 : min. m2 area : 0.0676um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.7</name>
+   <description>m2.7 : min. m2 holes area : 0.14um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.4</name>
+   <description>m2.4 : min. m2 enclosure of via : 0.055um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.4_a</name>
+   <description>m2.4_a : via in periphery must be enclosed by met2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.5</name>
+   <description>m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a</name>
+   <description>via2.1a : via2 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a_a</name>
+   <description>via2.1a_a : min. width of via2 outside of moduleCut : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a_b</name>
+   <description>via2.1a_b : maximum length of via2 : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.2</name>
+   <description>via2.2 : min. via2 spacing : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.4</name>
+   <description>via2.4 : min. m2 enclosure of via2 : 0.04um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.4_a</name>
+   <description>via2.4_a : via must be enclosed by met2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.5</name>
+   <description>via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.1</name>
+   <description>m3.1 : min. m3 width : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.2</name>
+   <description>m3.2 : min. m3 spacing : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.3cd</name>
+   <description>m3.3cd : min. 3um.m3 spacing m3 : 0.4um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.4</name>
+   <description>m3.4 : min. m3 enclosure of via2 : 0.065um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.4_a</name>
+   <description>m3.4_a : via2 must be enclosed by met3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1</name>
+   <description>via3.1 : via3 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1_a</name>
+   <description>via3.1_a : min. width of via3 outside of moduleCut : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1_b</name>
+   <description>via3.1_b : maximum length of via3 : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.2</name>
+   <description>via3.2 : min. via3 spacing : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.4</name>
+   <description>via3.4 : min. m3 enclosure of via3 : 0.06um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.4_a</name>
+   <description>via3.4_a : non-ring via3 must be enclosed by met3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.5</name>
+   <description>via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.1</name>
+   <description>m4.1 : min. m4 width : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.2</name>
+   <description>m4.2 : min. m4 spacing : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.4a</name>
+   <description>m4.4a : min. m4 area : 0.240um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.5ab</name>
+   <description>m4.5ab : min. 3um.m4 spacing m4 : 0.4um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.3</name>
+   <description>m4.3 : min. m4 enclosure of via3 : 0.065um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.3_a</name>
+   <description>m4.3_a : via3 must be enclosed by met4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1</name>
+   <description>via4.1 : via4 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1_a</name>
+   <description>via4.1_a : min. width of via4 outside of moduleCut : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1_b</name>
+   <description>via4.1_b : maximum length of via4 : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.2</name>
+   <description>via4.2 : min. via4 spacing : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.4</name>
+   <description>via4.4 : min. m4 enclosure of via4 : 0.19um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.4_a</name>
+   <description>via4.4_a : m4 must enclose all via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.1</name>
+   <description>m5.1 : min. m5 width : 1.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.2</name>
+   <description>m5.2 : min. m5 spacing : 1.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.3</name>
+   <description>m5.3 : min. m5 enclosure of via4 : 0.31um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.3_a</name>
+   <description>m5.3_a : via must be enclosed by m5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.4</name>
+   <description>m5.4 : min. m5 area : 4.0um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad.2</name>
+   <description>pad.2 : min. pad spacing : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>caravel_00088bca</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/tapeout/outputs/klayout_beol_report.xml.summary b/tapeout/outputs/klayout_beol_report.xml.summary
new file mode 100644
index 0000000..79b5c11
--- /dev/null
+++ b/tapeout/outputs/klayout_beol_report.xml.summary
@@ -0,0 +1,72 @@
+       0 791_m1.4 : min. m1 enclosure of mcon : 0.03um
+       0 ct.1: non-ring mcon should be rectangular
+       0 ct.1_a : minimum width of mcon : 0.17um
+       0 ct.1_b : maximum length of mcon : 0.17um
+       0 ct.2 : min. mcon spacing : 0.19um
+       0 ct.4 : mcon should covered by li
+       0 li.1 : min. li width : 0.17um
+       0 li.3 : min. li spacing : 0.17um
+       0 li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um
+       0 li.6 : min. li area : 0.0561um²
+       0 m1.1 : min. m1 width : 0.14um
+       0 m1.2 : min. m1 spacing : 0.14um
+       0 m1.3ab : min. 3um.m1 spacing m1 : 0.28um
+       0 m1.4 : mcon periphery must be enclosed by m1
+       0 m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um
+       0 m1.4a_a : mcon periph must be enclosed by met1 for specific cells
+       0 m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um
+       0 m1.6 : min. m1 area : 0.083um²
+       0 m1.7 : min. m1 with holes area : 0.14um²
+       0 m2.1 : min. m2 width : 0.14um
+       0 m2.2 : min. m2 spacing : 0.14um
+       0 m2.3ab : min. 3um.m2 spacing m2 : 0.28um
+       0 m2.4 : min. m2 enclosure of via : 0.055um
+       0 m2.4_a : via in periphery must be enclosed by met2
+       0 m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um
+       0 m2.6 : min. m2 area : 0.0676um²
+       0 m2.7 : min. m2 holes area : 0.14um²
+       0 m3.1 : min. m3 width : 0.3um
+       0 m3.2 : min. m3 spacing : 0.3um
+       0 m3.3cd : min. 3um.m3 spacing m3 : 0.4um
+       0 m3.4 : min. m3 enclosure of via2 : 0.065um
+       0 m3.4_a : via2 must be enclosed by met3
+       0 m4.1 : min. m4 width : 0.3um
+       0 m4.2 : min. m4 spacing : 0.3um
+       0 m4.3 : min. m4 enclosure of via3 : 0.065um
+       0 m4.3_a : via3 must be enclosed by met4
+       0 m4.4a : min. m4 area : 0.240um²
+       0 m4.5ab : min. 3um.m4 spacing m4 : 0.4um
+       0 m5.1 : min. m5 width : 1.6um
+       0 m5.2 : min. m5 spacing : 1.6um
+       0 m5.3 : min. m5 enclosure of via4 : 0.31um
+       0 m5.3_a : via must be enclosed by m5
+       0 m5.4 : min. m5 area : 4.0um²
+       0 pad.2 : min. pad spacing : 1.27um
+       0 via2.1a : via2 outside of moduleCut should be rectangular
+       0 via2.1a_a : min. width of via2 outside of moduleCut : 0.2um
+       0 via2.1a_b : maximum length of via2 : 0.2um
+       0 via2.2 : min. via2 spacing : 0.2um
+       0 via2.4 : min. m2 enclosure of via2 : 0.04um
+       0 via2.4_a : via must be enclosed by met2
+       0 via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um
+       0 via3.1 : via3 outside of moduleCut should be rectangular
+       0 via3.1_a : min. width of via3 outside of moduleCut : 0.2um
+       0 via3.1_b : maximum length of via3 : 0.2um
+       0 via3.2 : min. via3 spacing : 0.2um
+       0 via3.4 : min. m3 enclosure of via3 : 0.06um
+       0 via3.4_a : non-ring via3 must be enclosed by met3
+       0 via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um
+       0 via4.1 : via4 outside of moduleCut should be rectangular
+       0 via4.1_a : min. width of via4 outside of moduleCut : 0.8um
+       0 via4.1_b : maximum length of via4 : 0.8um
+       0 via4.2 : min. via4 spacing : 0.8um
+       0 via4.4 : min. m4 enclosure of via4 : 0.19um
+       0 via4.4_a : m4 must enclose all via4
+       0 via.1a : via outside of moduleCut should be rectangular
+       0 via.1a_a : min. width of via outside of moduleCut : 0.15um
+       0 via.1a_b : maximum length of via : 0.15um
+       0 via.2 : min. via spacing : 0.17um
+       0 via.4a : min. m1 enclosure of 0.15um via : 0.055um
+       0 via.4a_a : 0.15um via must be enclosed by met1
+       0 via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um
+       0 total error(s) among 71 error type(s), 0 non-zero type(s)
diff --git a/tapeout/outputs/klayout_feol_report.xml b/tapeout/outputs/klayout_feol_report.xml
new file mode 100644
index 0000000..575b8bf
--- /dev/null
+++ b/tapeout/outputs/klayout_feol_report.xml
@@ -0,0 +1,375 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/scripts/tech/sky130A_mr.drc'</generator>
+ <top-cell>caravel_00088bca</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>dnwell.2</name>
+   <description>dnwell.2 : min. dnwell width : 3.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell.1</name>
+   <description>nwell.1 : min. nwell width : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell.2a</name>
+   <description>nwell.2a : min. nwell spacing (merged if less) : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell.6</name>
+   <description>nwell.6 : min enclosure of nwellHole by dnwell : 1.03um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp.1</name>
+   <description>hvtp.1 : min. hvtp width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp.2</name>
+   <description>hvtp.2 : min. hvtp spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.1</name>
+   <description>hvtr.1 : min. hvtr width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.2</name>
+   <description>hvtr.2 : min. hvtr spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.2_a</name>
+   <description>hvtr.2_a : hvtr must not overlap hvtp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn.1a</name>
+   <description>lvtn.1a : min. lvtn width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn.2</name>
+   <description>lvtn.2 : min. lvtn spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm.1</name>
+   <description>ncm.1 : min. ncm width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm.2a</name>
+   <description>ncm.2a : min. ncm spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1</name>
+   <description>difftap.1 : min. diff width across areaid:ce : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_a</name>
+   <description>difftap.1_a : min. diff width in periphery : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_b</name>
+   <description>difftap.1_b : min. tap width across areaid:ce : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_c</name>
+   <description>difftap.1_c : min. tap width in periphery : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.3</name>
+   <description>difftap.3 : min. difftap spacing : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm.1</name>
+   <description>tunm.1 : min. tunm width : 0.41um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm.2</name>
+   <description>tunm.2 : min. tunm spacing : 0.5um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly.1a</name>
+   <description>poly.1a : min. poly width : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly.2</name>
+   <description>poly.2 : min. poly spacing : 0.21um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm.1a</name>
+   <description>rpm.1a : min. rpm width : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm.2</name>
+   <description>rpm.2 : min. rpm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>urpm.1a</name>
+   <description>urpm.1a : min. rpm width : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>urpm.2</name>
+   <description>urpm.2 : min. rpm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc.1</name>
+   <description>npc.1 : min. npc width : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc.2</name>
+   <description>npc.2 : min. npc spacing, should be manually merged if less than : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsd.1</name>
+   <description>nsd.1 : min. nsdm width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsd.2</name>
+   <description>nsd.2 : min. nsdm spacing, should be manually merged if less than : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psd.1</name>
+   <description>psd.1 : min. psdm width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psd.2</name>
+   <description>psd.2 : min. psdm spacing, should be manually merged if less than : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.1</name>
+   <description>licon.1 : licon should be rectangle</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.1_a/b</name>
+   <description>licon.1_a/b : minimum/maximum width of licon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.13</name>
+   <description>licon.13 : min. difftap licon spacing to npc : 0.09um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.13_a</name>
+   <description>licon.13_a : licon of diffTap in periphery must not overlap npc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.17</name>
+   <description>licon.17 : Licons may not overlap both poly and (diff or tap)</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.1</name>
+   <description>capm.1 : min. capm width : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2a</name>
+   <description>capm.2a : min. capm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2b</name>
+   <description>capm.2b : min. capm spacing : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2b_a</name>
+   <description>capm.2b_a : min. spacing of m3_bot_plate : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.3</name>
+   <description>capm.3 : min. capm and m3 enclosure of m3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.3_a</name>
+   <description>capm.3_a : min. m3 enclosure of capm : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.4</name>
+   <description>capm.4 : min. capm enclosure of via3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.5</name>
+   <description>capm.5 : min. capm spacing to via3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.11</name>
+   <description>capm.11 : Min spacing of capm and met3 not overlapping capm : 0.5um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.1</name>
+   <description>cap2m.1 : min. cap2m width : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2a</name>
+   <description>cap2m.2a : min. cap2m spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2b</name>
+   <description>cap2m.2b : min. cap2m spacing : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2b_a</name>
+   <description>cap2m.2b_a : min. spacing of m4_bot_plate : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.3</name>
+   <description>cap2m.3 : min. m4 enclosure of cap2m : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.3_a</name>
+   <description>cap2m.3_a : min. m4 enclosure of cap2m : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.4</name>
+   <description>cap2m.4 : min. cap2m enclosure of via4 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.5</name>
+   <description>cap2m.5 : min. cap2m spacing to via4 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.11</name>
+   <description>cap2m.11 : Min spacing of cap2m and met4 not overlapping cap2m : 0.5um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi.1</name>
+   <description>hvi.1 : min. hvi width : 0.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi.2a</name>
+   <description>hvi.2a : min. hvi spacing : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm.1</name>
+   <description>hvntm.1 : min. hvntm width : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm.2</name>
+   <description>hvntm.2 : min. hvntm spacing : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>caravel_00088bca</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/tapeout/outputs/klayout_feol_report.xml.summary b/tapeout/outputs/klayout_feol_report.xml.summary
new file mode 100644
index 0000000..2a7a007
--- /dev/null
+++ b/tapeout/outputs/klayout_feol_report.xml.summary
@@ -0,0 +1,60 @@
+       0 cap2m.1 : min. cap2m width : 1.0um
+       0 cap2m.2a : min. cap2m spacing : 0.84um
+       0 cap2m.2b : min. cap2m spacing : 1.2um
+       0 cap2m.2b_a : min. spacing of m4_bot_plate : 1.2um
+       0 cap2m.3 : min. m4 enclosure of cap2m : 0.14um
+       0 cap2m.3_a : min. m4 enclosure of cap2m : 0.14um
+       0 cap2m.4 : min. cap2m enclosure of via4 : 0.14um
+       0 cap2m.5 : min. cap2m spacing to via4 : 0.14um
+       0 cap2m.11 : Min spacing of cap2m and met4 not overlapping cap2m : 0.5um
+       0 capm.1 : min. capm width : 1.0um
+       0 capm.2a : min. capm spacing : 0.84um
+       0 capm.2b : min. capm spacing : 1.2um
+       0 capm.2b_a : min. spacing of m3_bot_plate : 1.2um
+       0 capm.3 : min. capm and m3 enclosure of m3 : 0.14um
+       0 capm.3_a : min. m3 enclosure of capm : 0.14um
+       0 capm.4 : min. capm enclosure of via3 : 0.14um
+       0 capm.5 : min. capm spacing to via3 : 0.14um
+       0 capm.11 : Min spacing of capm and met3 not overlapping capm : 0.5um
+       0 difftap.1 : min. diff width across areaid:ce : 0.15um
+       0 difftap.1_a : min. diff width in periphery : 0.15um
+       0 difftap.1_b : min. tap width across areaid:ce : 0.15um
+       0 difftap.1_c : min. tap width in periphery : 0.15um
+       0 difftap.3 : min. difftap spacing : 0.27um
+       0 dnwell.2 : min. dnwell width : 3.0um
+       0 hvi.1 : min. hvi width : 0.6um
+       0 hvi.2a : min. hvi spacing : 0.7um
+       0 hvntm.1 : min. hvntm width : 0.7um
+       0 hvntm.2 : min. hvntm spacing : 0.7um
+       0 hvtp.1 : min. hvtp width : 0.38um
+       0 hvtp.2 : min. hvtp spacing : 0.38um
+       0 hvtr.1 : min. hvtr width : 0.38um
+       0 hvtr.2 : min. hvtr spacing : 0.38um
+       0 hvtr.2_a : hvtr must not overlap hvtp
+       0 licon.1 : licon should be rectangle
+       0 licon.1_a/b : minimum/maximum width of licon : 0.17um
+       0 licon.13 : min. difftap licon spacing to npc : 0.09um
+       0 licon.13_a : licon of diffTap in periphery must not overlap npc
+       0 licon.17 : Licons may not overlap both poly and (diff or tap)
+       0 lvtn.1a : min. lvtn width : 0.38um
+       0 lvtn.2 : min. lvtn spacing : 0.38um
+       0 ncm.1 : min. ncm width : 0.38um
+       0 ncm.2a : min. ncm spacing : 0.38um
+       0 npc.1 : min. npc width : 0.27um
+       0 npc.2 : min. npc spacing, should be manually merged if less than : 0.27um
+       0 nsd.1 : min. nsdm width : 0.38um
+       0 nsd.2 : min. nsdm spacing, should be manually merged if less than : 0.38um
+       0 nwell.1 : min. nwell width : 0.84um
+       0 nwell.2a : min. nwell spacing (merged if less) : 1.27um
+       0 nwell.6 : min enclosure of nwellHole by dnwell : 1.03um
+       0 poly.1a : min. poly width : 0.15um
+       0 poly.2 : min. poly spacing : 0.21um
+       0 psd.1 : min. psdm width : 0.38um
+       0 psd.2 : min. psdm spacing, should be manually merged if less than : 0.38um
+       0 rpm.1a : min. rpm width : 1.27um
+       0 rpm.2 : min. rpm spacing : 0.84um
+       0 tunm.1 : min. tunm width : 0.41um
+       0 tunm.2 : min. tunm spacing : 0.5um
+       0 urpm.1a : min. rpm width : 1.27um
+       0 urpm.2 : min. rpm spacing : 0.84um
+       0 total error(s) among 59 error type(s), 0 non-zero type(s)
diff --git a/tapeout/outputs/klayout_fom_density_report.xml b/tapeout/outputs/klayout_fom_density_report.xml
new file mode 100644
index 0000000..e76d01e
--- /dev/null
+++ b/tapeout/outputs/klayout_fom_density_report.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>Density Checks</description>
+ <original-file/>
+ <generator>drc: script='/opt/scripts/tech/fom_density.drc'</generator>
+ <top-cell>caravel_00088bca</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+  <cell>
+   <name>caravel_00088bca</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/tapeout/outputs/klayout_fom_density_report.xml.summary b/tapeout/outputs/klayout_fom_density_report.xml.summary
new file mode 100644
index 0000000..8d461a0
--- /dev/null
+++ b/tapeout/outputs/klayout_fom_density_report.xml.summary
@@ -0,0 +1 @@
+       0 total error(s) among 0 error type(s), 0 non-zero type(s)
diff --git a/tapeout/outputs/klayout_met_density_report.xml b/tapeout/outputs/klayout_met_density_report.xml
new file mode 100644
index 0000000..ba58793
--- /dev/null
+++ b/tapeout/outputs/klayout_met_density_report.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>Density Checks</description>
+ <original-file/>
+ <generator>drc: script='/opt/scripts/tech/met_density.lydrc'</generator>
+ <top-cell>caravel_00088bca</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+  <cell>
+   <name>caravel_00088bca</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/tapeout/outputs/klayout_met_density_report.xml.summary b/tapeout/outputs/klayout_met_density_report.xml.summary
new file mode 100644
index 0000000..8d461a0
--- /dev/null
+++ b/tapeout/outputs/klayout_met_density_report.xml.summary
@@ -0,0 +1 @@
+       0 total error(s) among 0 error type(s), 0 non-zero type(s)
diff --git a/tapeout/outputs/mag/.magicrc b/tapeout/outputs/mag/.magicrc
new file mode 100755
index 0000000..7ec699d
--- /dev/null
+++ b/tapeout/outputs/mag/.magicrc
@@ -0,0 +1,109 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# Allow override of PDK path from environment variable PDKPATH.  Failing
+# that, fall back on definitions of PDK_ROOT and PDK.  If either of those
+# fails, substitute a default.  If PDKPATH has been specified, then get
+# PDK_VARIANT from the tail of PDKPATH.
+
+if {[catch {set PDKPATH $env(PDKPATH)}]} {
+    if {[catch {set PDK_ROOT $env(PDK_ROOT)}]} {
+	set PDK_ROOT /usr/share/pdk
+    }
+    if {[catch {set PDK_VARIANT $env(PDK)}]} {
+	set PDK_VARIANT sky130A
+    }
+    set PDKPATH ${PDK_ROOT}/${PDK_VARIANT}
+} else {
+    set PDK_VARIANT [file tail ${PDKPATH}]
+}
+
+puts stdout "Sourcing design .magicrc for technology $PDK_VARIANT ..."
+
+# Put grid on 0.005 pitch.  This is important, as some commands don't
+# rescale the grid automatically (such as lef read?).
+
+set scalefac [tech lambda]
+if {[lindex $scalefac 1] < 2} {
+    scalegrid 1 2
+}
+
+drc off
+drc euclidean on
+
+# loading technology
+tech load $PDKPATH/libs.tech/magic/${PDK_VARIANT}.tech
+
+# load device generator
+source $PDKPATH/libs.tech/magic/${PDK_VARIANT}.tcl
+
+# load bind keys (optional)
+# source $PDKPATH/libs.tech/magic/${PDK_VARIANT}-BindKeys
+
+# set units to lambda grid 
+snap lambda
+
+# set sky130 standard power, ground, and substrate names
+set VDD VPWR
+set GND VGND
+set SUB VSUBS
+
+# Allow override of type of magic library views used, "mag" or "maglef",
+# from environment variable MAGTYPE
+
+if {[catch {set MAGTYPE $env(MAGTYPE)}]} {
+   set MAGTYPE maglef
+}
+
+	path search [concat "../$MAGTYPE" [path search]]
+
+
+# add path to reference cells
+if {[file isdir ${PDKPATH}/libs.ref/${MAGTYPE}]} {
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_pr
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_io
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hd
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hdll
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hs
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hvl
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_lp
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ls
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ms
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc
+    addpath ${PDKPATH}/libs.ref/mag/sky130_ml_xx_hd
+} else {
+    addpath ${PDKPATH}/libs.ref/sky130_fd_pr/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_fd_io/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hd/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hdll/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hs/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hvl/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_lp/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ls/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ms/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_osu_sc/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_ml_xx_hd/mag
+}
+
+addpath hexdigits
+addpath ../subcells/simple_por/mag
+
+# add path to GDS cells
+
+# add path to IP from catalog.  This procedure defined in the PDK script.
+catch {magic::query_mylib_ip}
+# add path to local IP from user design space.  Defined in the PDK script.
+catch {magic::query_my_projects}
diff --git a/tapeout/outputs/mag/caravel.mag b/tapeout/outputs/mag/caravel.mag
new file mode 100644
index 0000000..4afe9bc
--- /dev/null
+++ b/tapeout/outputs/mag/caravel.mag
@@ -0,0 +1,83878 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1667299471
+<< checkpaint >>
+rect -1260 -1260 718860 1038860
+<< metal1 >>
+rect 366174 1027828 366180 1027880
+rect 366232 1027868 366238 1027880
+rect 366542 1027868 366548 1027880
+rect 366232 1027840 366548 1027868
+rect 366232 1027828 366238 1027840
+rect 366542 1027828 366548 1027840
+rect 366600 1027828 366606 1027880
+rect 366174 1024360 366180 1024412
+rect 366232 1024400 366238 1024412
+rect 366542 1024400 366548 1024412
+rect 366232 1024372 366548 1024400
+rect 366232 1024360 366238 1024372
+rect 366542 1024360 366548 1024372
+rect 366600 1024360 366606 1024412
+rect 427998 1006816 428004 1006868
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+<< via4 >>
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+<< metal5 >>
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+rect 425250 41702 441390 41938
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+rect 424972 41660 441668 41702
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+rect 412460 41300 412780 41660
+rect 411724 40980 412780 41300
+rect 421476 41300 421796 41660
+rect 423500 41300 423820 41660
+rect 442084 41300 442404 41660
+rect 421476 40980 422440 41300
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+rect 451100 41938 463932 41980
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+rect 451100 41660 463932 41702
+rect 451100 41300 451420 41660
+rect 450364 40980 451420 41300
+rect 422120 40620 422440 40980
+rect 422120 40578 425292 40620
+rect 422120 40342 425014 40578
+rect 425250 40342 425292 40578
+rect 422120 40300 425292 40342
+rect 80222 6811 92390 18976
+rect 136713 7143 144150 18309
+rect 187640 6598 200160 19088
+rect 243266 6167 254146 19620
+rect 296240 6598 308760 19088
+rect 351040 6598 363560 19088
+rect 405840 6598 418360 19088
+rect 460640 6598 473160 19088
+rect 515440 6598 527960 19088
+rect 570422 6811 582590 18976
+rect 624222 6811 636390 18976
+use caravel_logo  caravel_logo
+timestamp 1638586901
+transform 1 0 269370 0 1 5100
+box -2520 0 15000 15560
+use caravel_motto  caravel_motto
+timestamp 1637698310
+transform 1 0 -54372 0 1 -4446
+box 373080 14838 395618 19242
+use caravel_power_routing  caravel_power_routing
+timestamp 1666994345
+transform 1 0 0 0 1 0
+box 6022 30806 711814 1031696
+use caravel_clocking  clock_ctrl
+timestamp 1666097791
+transform 1 0 626764 0 1 55284
+box 136 496 20000 20000
+use copyright_block  copyright_block
+timestamp 1665519328
+transform 1 0 149582 0 1 16298
+box -262 -10348 35048 2764
+use buff_flash_clkrst  flash_clkrst_buffers
+timestamp 1665682149
+transform 1 0 458400 0 1 47600
+box 330 0 7699 5000
+use gpio_control_block  gpio_control_bidir_1\[0\]
+timestamp 1666126335
+transform -1 0 710203 0 1 121000
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_bidir_1\[1\]
+timestamp 1666126335
+transform -1 0 710203 0 1 166200
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_bidir_2\[0\]
+timestamp 1666126335
+transform 1 0 7631 0 1 289000
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_bidir_2\[1\]
+timestamp 1666126335
+transform 1 0 7631 0 1 245800
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_bidir_2\[2\]
+timestamp 1666126335
+transform 1 0 7631 0 1 202600
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_1\[0\]
+timestamp 1666126335
+transform -1 0 710203 0 1 523800
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_1\[1\]
+timestamp 1666126335
+transform -1 0 710203 0 1 568800
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_1\[2\]
+timestamp 1666126335
+transform -1 0 710203 0 1 614000
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_1\[3\]
+timestamp 1666126335
+transform -1 0 710203 0 1 659000
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_1\[4\]
+timestamp 1666126335
+transform -1 0 710203 0 1 704200
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_1\[5\]
+timestamp 1666126335
+transform -1 0 710203 0 1 749200
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_1\[6\]
+timestamp 1666126335
+transform -1 0 710203 0 1 927600
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_1\[7\]
+timestamp 1666126335
+transform 0 1 549200 -1 0 1030077
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_1\[8\]
+timestamp 1666126335
+transform 0 1 497800 -1 0 1030077
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_1\[9\]
+timestamp 1666126335
+transform 0 1 420800 -1 0 1030077
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_1\[10\]
+timestamp 1666126335
+transform 0 1 353400 -1 0 1030077
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_1a\[0\]
+timestamp 1666126335
+transform -1 0 710203 0 1 211200
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_1a\[1\]
+timestamp 1666126335
+transform -1 0 710203 0 1 256400
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_1a\[2\]
+timestamp 1666126335
+transform -1 0 710203 0 1 301400
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_1a\[3\]
+timestamp 1666126335
+transform -1 0 710203 0 1 346400
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_1a\[4\]
+timestamp 1666126335
+transform -1 0 710203 0 1 391600
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_1a\[5\]
+timestamp 1666126335
+transform -1 0 710203 0 1 479800
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_2\[0\]
+timestamp 1666126335
+transform 0 1 303000 -1 0 1030077
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_2\[1\]
+timestamp 1666126335
+transform 0 1 251400 -1 0 1030077
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_2\[2\]
+timestamp 1666126335
+transform 0 1 200000 -1 0 1030077
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_2\[3\]
+timestamp 1666126335
+transform 0 1 148600 -1 0 1030077
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_2\[4\]
+timestamp 1666126335
+transform 0 1 97200 -1 0 1030077
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_2\[5\]
+timestamp 1666126335
+transform 1 0 7631 0 1 931200
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_2\[6\]
+timestamp 1666126335
+transform 1 0 7631 0 1 805400
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_2\[7\]
+timestamp 1666126335
+transform 1 0 7631 0 1 762200
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_2\[8\]
+timestamp 1666126335
+transform 1 0 7631 0 1 719000
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_2\[9\]
+timestamp 1666126335
+transform 1 0 7631 0 1 675800
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_2\[10\]
+timestamp 1666126335
+transform 1 0 7631 0 1 632600
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_2\[11\]
+timestamp 1666126335
+transform 1 0 7631 0 1 589400
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_2\[12\]
+timestamp 1666126335
+transform 1 0 7631 0 1 546200
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_2\[13\]
+timestamp 1666126335
+transform 1 0 7631 0 1 418600
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_2\[14\]
+timestamp 1666126335
+transform 1 0 7631 0 1 375400
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_2\[15\]
+timestamp 1666126335
+transform 1 0 7631 0 1 332200
+box 872 416 34000 13000
+use gpio_defaults_block_1803 gpio_defaults_block_0 ~/caravel_top_level/mag
+timestamp 1666360185
+transform -1 0 709467 0 1 134000
+box -38 0 6018 2224
+use gpio_defaults_block_1803 gpio_defaults_block_1
+timestamp 1666360185
+transform -1 0 709467 0 1 179200
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_2
+timestamp 1666360185
+transform -1 0 709467 0 1 224200
+box -38 0 6018 2224
+use gpio_defaults_block_0801 gpio_defaults_block_3
+timestamp 1666360185
+transform -1 0 709467 0 1 269400
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_4
+timestamp 1666360185
+transform -1 0 709467 0 1 314400
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_5
+timestamp 1666360185
+transform -1 0 709467 0 1 359400
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_6
+timestamp 1666360185
+transform -1 0 709467 0 1 404600
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_7
+timestamp 1666360185
+transform -1 0 709467 0 1 492800
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_8
+timestamp 1666360185
+transform -1 0 709467 0 1 536800
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_9
+timestamp 1666360185
+transform -1 0 709467 0 1 581800
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_10
+timestamp 1666360185
+transform -1 0 709467 0 1 627000
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_11
+timestamp 1666360185
+transform -1 0 709467 0 1 672000
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_12
+timestamp 1666360185
+transform -1 0 709467 0 1 717200
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_13
+timestamp 1666360185
+transform -1 0 709467 0 1 762200
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_14
+timestamp 1666360185
+transform -1 0 709467 0 1 940600
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_15
+timestamp 1666360185
+transform 0 1 562194 -1 0 1029341
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_16
+timestamp 1666360185
+transform 0 1 510794 -1 0 1029341
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_17
+timestamp 1666360185
+transform 0 1 433794 -1 0 1029341
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_18
+timestamp 1666360185
+transform 0 1 366394 -1 0 1029341
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_19
+timestamp 1666360185
+transform 0 1 315994 -1 0 1029341
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_20
+timestamp 1666360185
+transform 0 1 264394 -1 0 1029341
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_21
+timestamp 1666360185
+transform 0 1 212994 -1 0 1029341
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_22
+timestamp 1666360185
+transform 0 1 161594 -1 0 1029341
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_23
+timestamp 1666360185
+transform 0 1 110194 -1 0 1029341
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_24
+timestamp 1666360185
+transform 1 0 8367 0 1 944200
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_25
+timestamp 1666360185
+transform 1 0 8367 0 1 818400
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_26
+timestamp 1666360185
+transform 1 0 8367 0 1 775200
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_27
+timestamp 1666360185
+transform 1 0 8367 0 1 732000
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_28
+timestamp 1666360185
+transform 1 0 8367 0 1 688800
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_29
+timestamp 1666360185
+transform 1 0 8367 0 1 645600
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_30
+timestamp 1666360185
+transform 1 0 8367 0 1 602400
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_31
+timestamp 1666360185
+transform 1 0 8367 0 1 559200
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_32
+timestamp 1666360185
+transform 1 0 8367 0 1 431600
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_33
+timestamp 1666360185
+transform 1 0 8367 0 1 388400
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_34
+timestamp 1666360185
+transform 1 0 8367 0 1 345200
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_35
+timestamp 1666360185
+transform 1 0 8367 0 1 302000
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_36
+timestamp 1666360185
+transform 1 0 8367 0 1 258800
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_37
+timestamp 1666360185
+transform 1 0 8367 0 1 215600
+box -38 0 6018 2224
+use housekeeping  housekeeping
+timestamp 1666084955
+transform 1 0 592434 0 1 100002
+box 0 0 74046 110190
+use mgmt_protect  mgmt_buffers
+timestamp 1666987233
+transform 1 0 128180 0 1 232036
+box 1066 -400 424400 32400
+use user_project_wrapper  mprj
+timestamp 1637147503
+transform 1 0 65308 0 1 278718
+box -8726 -7654 592650 711590
+use open_source  open_source
+timestamp 1666123577
+transform 1 0 206098 0 1 2054
+box 752 5164 29030 16242
+use chip_io  padframe
+timestamp 1666101711
+transform 1 0 0 0 1 0
+box 0 0 717600 1037600
+use digital_pll  pll
+timestamp 1666101174
+transform 1 0 628146 0 1 80944
+box 0 0 20000 15000
+use simple_por  por
+timestamp 1650914729
+transform 1 0 650146 0 -1 55282
+box -52 -62 11344 8684
+use xres_buf  rstb_level
+timestamp 1649268499
+transform -1 0 145710 0 -1 50488
+box 374 -400 3540 3800
+use gpio_signal_buffering  sigbuf
+timestamp 1666028385
+transform 1 0 0 0 1 0
+box 39992 41960 677583 997915
+use mgmt_core_wrapper  soc
+timestamp 1668034664
+transform 1 0 52034 0 1 53002
+box -156 0 524096 164000
+use spare_logic_block  spare_logic\[0\]
+timestamp 1638030917
+transform 1 0 88632 0 1 232528
+box 0 0 9000 9000
+use spare_logic_block  spare_logic\[1\]
+timestamp 1638030917
+transform 1 0 108632 0 1 232528
+box 0 0 9000 9000
+use spare_logic_block  spare_logic\[2\]
+timestamp 1638030917
+transform 1 0 640874 0 1 220592
+box 0 0 9000 9000
+use spare_logic_block  spare_logic\[3\]
+timestamp 1638030917
+transform 1 0 578632 0 1 232528
+box 0 0 9000 9000
+use user_id_textblock  user_id_textblock
+timestamp 1608324878
+transform 1 0 96272 0 1 6890
+box -656 1508 33720 10344
+use user_id_programming  user_id_value
+timestamp 1650371074
+transform 1 0 656624 0 1 88126
+box 0 0 7109 7077
+<< labels >>
+flabel metal5 s 187640 6598 200160 19088 0 FreeSans 16000 0 0 0 clock
+port 1 nsew signal input
+flabel metal5 s 351040 6598 363560 19088 0 FreeSans 16000 0 0 0 flash_clk
+port 2 nsew signal output
+flabel metal5 s 296240 6598 308760 19088 0 FreeSans 16000 0 0 0 flash_csb
+port 3 nsew signal output
+flabel metal5 s 405840 6598 418360 19088 0 FreeSans 16000 0 0 0 flash_io0
+port 4 nsew signal output
+flabel metal5 s 460640 6598 473160 19088 0 FreeSans 16000 0 0 0 flash_io1
+port 5 nsew signal output
+flabel metal5 s 515440 6598 527960 19088 0 FreeSans 16000 0 0 0 gpio
+port 6 nsew signal bidirectional
+flabel metal5 s 698512 101240 711002 113760 0 FreeSans 16000 0 0 0 mprj_io[0]
+port 7 nsew signal bidirectional
+flabel metal5 s 698512 684440 711002 696960 0 FreeSans 16000 0 0 0 mprj_io[10]
+port 8 nsew signal bidirectional
+flabel metal5 s 698512 729440 711002 741960 0 FreeSans 16000 0 0 0 mprj_io[11]
+port 9 nsew signal bidirectional
+flabel metal5 s 698512 774440 711002 786960 0 FreeSans 16000 0 0 0 mprj_io[12]
+port 10 nsew signal bidirectional
+flabel metal5 s 698512 863640 711002 876160 0 FreeSans 16000 0 0 0 mprj_io[13]
+port 11 nsew signal bidirectional
+flabel metal5 s 698512 952840 711002 965360 0 FreeSans 16000 0 0 0 mprj_io[14]
+port 12 nsew signal bidirectional
+flabel metal5 s 628240 1018512 640760 1031002 0 FreeSans 16000 0 0 0 mprj_io[15]
+port 13 nsew signal bidirectional
+flabel metal5 s 526440 1018512 538960 1031002 0 FreeSans 16000 0 0 0 mprj_io[16]
+port 14 nsew signal bidirectional
+flabel metal5 s 475040 1018512 487560 1031002 0 FreeSans 16000 0 0 0 mprj_io[17]
+port 15 nsew signal bidirectional
+flabel metal5 s 386040 1018512 398560 1031002 0 FreeSans 16000 0 0 0 mprj_io[18]
+port 16 nsew signal bidirectional
+flabel metal5 s 284240 1018512 296760 1031002 0 FreeSans 16000 0 0 0 mprj_io[19]
+port 17 nsew signal bidirectional
+flabel metal5 s 698512 146440 711002 158960 0 FreeSans 16000 0 0 0 mprj_io[1]
+port 18 nsew signal bidirectional
+flabel metal5 s 232640 1018512 245160 1031002 0 FreeSans 16000 0 0 0 mprj_io[20]
+port 19 nsew signal bidirectional
+flabel metal5 s 181240 1018512 193760 1031002 0 FreeSans 16000 0 0 0 mprj_io[21]
+port 20 nsew signal bidirectional
+flabel metal5 s 129840 1018512 142360 1031002 0 FreeSans 16000 0 0 0 mprj_io[22]
+port 21 nsew signal bidirectional
+flabel metal5 s 78440 1018512 90960 1031002 0 FreeSans 16000 0 0 0 mprj_io[23]
+port 22 nsew signal bidirectional
+flabel metal5 s 6598 956440 19088 968960 0 FreeSans 16000 0 0 0 mprj_io[24]
+port 23 nsew signal bidirectional
+flabel metal5 s 6598 786640 19088 799160 0 FreeSans 16000 0 0 0 mprj_io[25]
+port 24 nsew signal bidirectional
+flabel metal5 s 6598 743440 19088 755960 0 FreeSans 16000 0 0 0 mprj_io[26]
+port 25 nsew signal bidirectional
+flabel metal5 s 6598 700240 19088 712760 0 FreeSans 16000 0 0 0 mprj_io[27]
+port 26 nsew signal bidirectional
+flabel metal5 s 6598 657040 19088 669560 0 FreeSans 16000 0 0 0 mprj_io[28]
+port 27 nsew signal bidirectional
+flabel metal5 s 6598 613840 19088 626360 0 FreeSans 16000 0 0 0 mprj_io[29]
+port 28 nsew signal bidirectional
+flabel metal5 s 698512 191440 711002 203960 0 FreeSans 16000 0 0 0 mprj_io[2]
+port 29 nsew signal bidirectional
+flabel metal5 s 6598 570640 19088 583160 0 FreeSans 16000 0 0 0 mprj_io[30]
+port 30 nsew signal bidirectional
+flabel metal5 s 6598 527440 19088 539960 0 FreeSans 16000 0 0 0 mprj_io[31]
+port 31 nsew signal bidirectional
+flabel metal5 s 6598 399840 19088 412360 0 FreeSans 16000 0 0 0 mprj_io[32]
+port 32 nsew signal bidirectional
+flabel metal5 s 6598 356640 19088 369160 0 FreeSans 16000 0 0 0 mprj_io[33]
+port 33 nsew signal bidirectional
+flabel metal5 s 6598 313440 19088 325960 0 FreeSans 16000 0 0 0 mprj_io[34]
+port 34 nsew signal bidirectional
+flabel metal5 s 6598 270240 19088 282760 0 FreeSans 16000 0 0 0 mprj_io[35]
+port 35 nsew signal bidirectional
+flabel metal5 s 6598 227040 19088 239560 0 FreeSans 16000 0 0 0 mprj_io[36]
+port 36 nsew signal bidirectional
+flabel metal5 s 6598 183840 19088 196360 0 FreeSans 16000 0 0 0 mprj_io[37]
+port 37 nsew signal bidirectional
+flabel metal5 s 698512 236640 711002 249160 0 FreeSans 16000 0 0 0 mprj_io[3]
+port 38 nsew signal bidirectional
+flabel metal5 s 698512 281640 711002 294160 0 FreeSans 16000 0 0 0 mprj_io[4]
+port 39 nsew signal bidirectional
+flabel metal5 s 698512 326640 711002 339160 0 FreeSans 16000 0 0 0 mprj_io[5]
+port 40 nsew signal bidirectional
+flabel metal5 s 698512 371840 711002 384360 0 FreeSans 16000 0 0 0 mprj_io[6]
+port 41 nsew signal bidirectional
+flabel metal5 s 698512 549040 711002 561560 0 FreeSans 16000 0 0 0 mprj_io[7]
+port 42 nsew signal bidirectional
+flabel metal5 s 698512 594240 711002 606760 0 FreeSans 16000 0 0 0 mprj_io[8]
+port 43 nsew signal bidirectional
+flabel metal5 s 698512 639240 711002 651760 0 FreeSans 16000 0 0 0 mprj_io[9]
+port 44 nsew signal bidirectional
+flabel metal5 s 136713 7143 144150 18309 0 FreeSans 16000 0 0 0 resetb
+port 45 nsew signal input
+flabel metal5 s 6167 70054 19620 80934 0 FreeSans 16000 0 0 0 vccd
+port 46 nsew power input
+flabel metal5 s 697980 909666 711433 920546 0 FreeSans 16000 0 0 0 vccd1
+port 47 nsew power input
+flabel metal5 s 6167 914054 19620 924934 0 FreeSans 16000 0 0 0 vccd2
+port 48 nsew power input
+flabel metal5 s 624222 6811 636390 18976 0 FreeSans 16000 0 0 0 vdda
+port 49 nsew power input
+flabel metal5 s 698624 819822 710789 831990 0 FreeSans 16000 0 0 0 vdda1
+port 50 nsew power input
+flabel metal5 s 698624 505222 710789 517390 0 FreeSans 16000 0 0 0 vdda1_2
+port 51 nsew power input
+flabel metal5 s 6811 484410 18976 496578 0 FreeSans 16000 0 0 0 vdda2
+port 52 nsew power input
+flabel metal5 s 6811 111610 18976 123778 0 FreeSans 16000 0 0 0 vddio
+port 53 nsew power input
+flabel metal5 s 6811 871210 18976 883378 0 FreeSans 16000 0 0 0 vddio_2
+port 54 nsew power input
+flabel metal5 s 80222 6811 92390 18976 0 FreeSans 16000 0 0 0 vssa
+port 55 nsew ground input
+flabel metal5 s 577010 1018624 589178 1030789 0 FreeSans 16000 0 0 0 vssa1
+port 56 nsew ground input
+flabel metal5 s 698624 417022 710789 429190 0 FreeSans 16000 0 0 0 vssa1_2
+port 57 nsew ground input
+flabel metal5 s 6811 829010 18976 841178 0 FreeSans 16000 0 0 0 vssa2
+port 58 nsew ground input
+flabel metal5 s 243266 6167 254146 19620 0 FreeSans 16000 0 0 0 vssd
+port 59 nsew ground input
+flabel metal5 s 697980 461866 711433 472746 0 FreeSans 16000 0 0 0 vssd1
+port 60 nsew ground input
+flabel metal5 s 6167 442854 19620 453734 0 FreeSans 16000 0 0 0 vssd2
+port 61 nsew ground input
+flabel metal5 s 570422 6811 582590 18976 0 FreeSans 16000 0 0 0 vssio
+port 62 nsew ground input
+flabel metal5 s 334810 1018624 346978 1030789 0 FreeSans 16000 0 0 0 vssio_2
+port 63 nsew ground input
+<< properties >>
+string FIXED_BBOX 0 0 717600 1037600
+string LEFclass BLOCK
+<< end >>
diff --git a/tapeout/outputs/mag/gpio_defaults_block_0403.mag b/tapeout/outputs/mag/gpio_defaults_block_0403.mag
new file mode 100644
index 0000000..e15b2ba
--- /dev/null
+++ b/tapeout/outputs/mag/gpio_defaults_block_0403.mag
@@ -0,0 +1,1461 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1638587925
+<< viali >>
+rect 949 833 983 867
+rect 1639 833 1673 867
+rect 4721 833 4755 867
+rect 1225 765 1259 799
+rect 1915 765 1949 799
+rect 2191 765 2225 799
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+rect 3433 765 3467 799
+rect 3893 765 3927 799
+rect 4353 765 4387 799
+rect 4813 765 4847 799
+rect 5411 765 5445 799
+<< metal1 >>
+rect 0 2202 5980 2224
+rect 0 2150 78 2202
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+rect 1636 728 1722 756
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+rect 716 688 722 700
+rect 0 570 5980 592
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+<< via1 >>
+rect 78 2150 130 2202
+rect 142 2150 194 2202
+rect 206 2150 258 2202
+rect 270 2150 322 2202
+rect 1478 2150 1530 2202
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+rect 3052 1060 3108 1116
+rect 3108 1060 3112 1116
+rect 3048 1056 3112 1060
+rect 4288 1116 4352 1120
+rect 4288 1060 4292 1116
+rect 4292 1060 4348 1116
+rect 4348 1060 4352 1116
+rect 4288 1056 4352 1060
+rect 4368 1116 4432 1120
+rect 4368 1060 4372 1116
+rect 4372 1060 4428 1116
+rect 4428 1060 4432 1116
+rect 4368 1056 4432 1060
+rect 4448 1116 4512 1120
+rect 4448 1060 4452 1116
+rect 4452 1060 4508 1116
+rect 4508 1060 4512 1116
+rect 4448 1056 4512 1060
+rect 788 572 852 576
+rect 788 516 792 572
+rect 792 516 848 572
+rect 848 516 852 572
+rect 788 512 852 516
+rect 868 572 932 576
+rect 868 516 872 572
+rect 872 516 928 572
+rect 928 516 932 572
+rect 868 512 932 516
+rect 948 572 1012 576
+rect 948 516 952 572
+rect 952 516 1008 572
+rect 1008 516 1012 572
+rect 948 512 1012 516
+rect 2188 572 2252 576
+rect 2188 516 2192 572
+rect 2192 516 2248 572
+rect 2248 516 2252 572
+rect 2188 512 2252 516
+rect 2268 572 2332 576
+rect 2268 516 2272 572
+rect 2272 516 2328 572
+rect 2328 516 2332 572
+rect 2268 512 2332 516
+rect 2348 572 2412 576
+rect 2348 516 2352 572
+rect 2352 516 2408 572
+rect 2408 516 2412 572
+rect 2348 512 2412 516
+rect 3588 572 3652 576
+rect 3588 516 3592 572
+rect 3592 516 3648 572
+rect 3648 516 3652 572
+rect 3588 512 3652 516
+rect 3668 572 3732 576
+rect 3668 516 3672 572
+rect 3672 516 3728 572
+rect 3728 516 3732 572
+rect 3668 512 3732 516
+rect 3748 572 3812 576
+rect 3748 516 3752 572
+rect 3752 516 3808 572
+rect 3808 516 3812 572
+rect 3748 512 3812 516
+rect 4988 572 5052 576
+rect 4988 516 4992 572
+rect 4992 516 5048 572
+rect 5048 516 5052 572
+rect 4988 512 5052 516
+rect 5068 572 5132 576
+rect 5068 516 5072 572
+rect 5072 516 5128 572
+rect 5128 516 5132 572
+rect 5068 512 5132 516
+rect 5148 572 5212 576
+rect 5148 516 5152 572
+rect 5152 516 5208 572
+rect 5208 516 5212 572
+rect 5148 512 5212 516
+<< metal4 >>
+rect 60 2208 340 2224
+rect 60 2144 88 2208
+rect 152 2144 168 2208
+rect 232 2144 248 2208
+rect 312 2144 340 2208
+rect 60 1120 340 2144
+rect 60 1056 88 1120
+rect 152 1056 168 1120
+rect 232 1056 248 1120
+rect 312 1056 340 1120
+rect 60 1014 340 1056
+rect 60 778 82 1014
+rect 318 778 340 1014
+rect 60 496 340 778
+rect 760 1714 1040 2224
+rect 760 1478 782 1714
+rect 1018 1478 1040 1714
+rect 760 576 1040 1478
+rect 760 512 788 576
+rect 852 512 868 576
+rect 932 512 948 576
+rect 1012 512 1040 576
+rect 760 496 1040 512
+rect 1460 2208 1740 2224
+rect 1460 2144 1488 2208
+rect 1552 2144 1568 2208
+rect 1632 2144 1648 2208
+rect 1712 2144 1740 2208
+rect 1460 1120 1740 2144
+rect 1460 1056 1488 1120
+rect 1552 1056 1568 1120
+rect 1632 1056 1648 1120
+rect 1712 1056 1740 1120
+rect 1460 1014 1740 1056
+rect 1460 778 1482 1014
+rect 1718 778 1740 1014
+rect 1460 496 1740 778
+rect 2160 1714 2440 2224
+rect 2160 1478 2182 1714
+rect 2418 1478 2440 1714
+rect 2160 576 2440 1478
+rect 2160 512 2188 576
+rect 2252 512 2268 576
+rect 2332 512 2348 576
+rect 2412 512 2440 576
+rect 2160 496 2440 512
+rect 2860 2208 3140 2224
+rect 2860 2144 2888 2208
+rect 2952 2144 2968 2208
+rect 3032 2144 3048 2208
+rect 3112 2144 3140 2208
+rect 2860 1120 3140 2144
+rect 2860 1056 2888 1120
+rect 2952 1056 2968 1120
+rect 3032 1056 3048 1120
+rect 3112 1056 3140 1120
+rect 2860 1014 3140 1056
+rect 2860 778 2882 1014
+rect 3118 778 3140 1014
+rect 2860 496 3140 778
+rect 3560 1714 3840 2224
+rect 3560 1478 3582 1714
+rect 3818 1478 3840 1714
+rect 3560 576 3840 1478
+rect 3560 512 3588 576
+rect 3652 512 3668 576
+rect 3732 512 3748 576
+rect 3812 512 3840 576
+rect 3560 496 3840 512
+rect 4260 2208 4540 2224
+rect 4260 2144 4288 2208
+rect 4352 2144 4368 2208
+rect 4432 2144 4448 2208
+rect 4512 2144 4540 2208
+rect 4260 1120 4540 2144
+rect 4260 1056 4288 1120
+rect 4352 1056 4368 1120
+rect 4432 1056 4448 1120
+rect 4512 1056 4540 1120
+rect 4260 1014 4540 1056
+rect 4260 778 4282 1014
+rect 4518 778 4540 1014
+rect 4260 496 4540 778
+rect 4960 1714 5240 2224
+rect 4960 1478 4982 1714
+rect 5218 1478 5240 1714
+rect 4960 576 5240 1478
+rect 4960 512 4988 576
+rect 5052 512 5068 576
+rect 5132 512 5148 576
+rect 5212 512 5240 576
+rect 4960 496 5240 512
+<< via4 >>
+rect 82 778 318 1014
+rect 782 1664 1018 1714
+rect 782 1600 788 1664
+rect 788 1600 852 1664
+rect 852 1600 868 1664
+rect 868 1600 932 1664
+rect 932 1600 948 1664
+rect 948 1600 1012 1664
+rect 1012 1600 1018 1664
+rect 782 1478 1018 1600
+rect 1482 778 1718 1014
+rect 2182 1664 2418 1714
+rect 2182 1600 2188 1664
+rect 2188 1600 2252 1664
+rect 2252 1600 2268 1664
+rect 2268 1600 2332 1664
+rect 2332 1600 2348 1664
+rect 2348 1600 2412 1664
+rect 2412 1600 2418 1664
+rect 2182 1478 2418 1600
+rect 2882 778 3118 1014
+rect 3582 1664 3818 1714
+rect 3582 1600 3588 1664
+rect 3588 1600 3652 1664
+rect 3652 1600 3668 1664
+rect 3668 1600 3732 1664
+rect 3732 1600 3748 1664
+rect 3748 1600 3812 1664
+rect 3812 1600 3818 1664
+rect 3582 1478 3818 1600
+rect 4282 778 4518 1014
+rect 4982 1664 5218 1714
+rect 4982 1600 4988 1664
+rect 4988 1600 5052 1664
+rect 5052 1600 5068 1664
+rect 5068 1600 5132 1664
+rect 5132 1600 5148 1664
+rect 5148 1600 5212 1664
+rect 5212 1600 5218 1664
+rect 4982 1478 5218 1600
+<< metal5 >>
+rect 0 1714 5980 1756
+rect 0 1478 782 1714
+rect 1018 1478 2182 1714
+rect 2418 1478 3582 1714
+rect 3818 1478 4982 1714
+rect 5218 1478 5980 1714
+rect 0 1436 5980 1478
+rect 0 1014 5980 1056
+rect 0 778 82 1014
+rect 318 778 1482 1014
+rect 1718 778 2882 1014
+rect 3118 778 4282 1014
+rect 4518 778 5980 1014
+rect 0 736 5980 778
+use sky130_fd_sc_hd__fill_1  FILLER_0_9 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 828 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3  PHY_2 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 0 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_0
+timestamp 1638322937
+transform 1 0 0 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 276 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_6  FILLER_0_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 276 0 1 544
+box -38 -48 590 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[0\] $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 920 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_15
+timestamp 1638322937
+transform 1 0 1380 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[5\]
+timestamp 1638322937
+transform 1 0 2300 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[1\]
+timestamp 1638322937
+transform 1 0 1196 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[4\]
+timestamp 1638322937
+transform 1 0 2024 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[3\]
+timestamp 1638322937
+transform 1 0 1748 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[2\]
+timestamp 1638322937
+transform 1 0 1472 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_6 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 2576 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_38 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 3496 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_33
+timestamp 1638322937
+transform 1 0 3036 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__fill_1  FILLER_0_29
+timestamp 1638322937
+transform 1 0 2668 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_27
+timestamp 1638322937
+transform 1 0 2484 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[7\]
+timestamp 1638322937
+transform 1 0 3220 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[6\]
+timestamp 1638322937
+transform 1 0 2760 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_43
+timestamp 1638322937
+transform 1 0 3956 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4  FILLER_1_51 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 4692 0 -1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_0_48
+timestamp 1638322937
+transform 1 0 4416 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_39
+timestamp 1638322937
+transform 1 0 3588 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[9\]
+timestamp 1638322937
+transform 1 0 4140 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[8\]
+timestamp 1638322937
+transform 1 0 3680 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[12\]
+timestamp 1638322937
+transform 1 0 4508 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_8
+timestamp 1638322937
+transform 1 0 5152 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_7
+timestamp 1638322937
+transform 1 0 5152 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1  FILLER_1_55
+timestamp 1638322937
+transform 1 0 5060 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1  FILLER_0_55
+timestamp 1638322937
+transform 1 0 5060 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[10\]
+timestamp 1638322937
+transform 1 0 4784 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_60
+timestamp 1638322937
+transform 1 0 5520 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4  FILLER_1_57
+timestamp 1638322937
+transform 1 0 5244 0 -1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_1_61
+timestamp 1638322937
+transform 1 0 5612 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[11\]
+timestamp 1638322937
+transform 1 0 5244 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_3
+timestamp 1638322937
+transform -1 0 5980 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_1
+timestamp 1638322937
+transform -1 0 5980 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_4
+timestamp 1638322937
+transform 1 0 0 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_3
+timestamp 1638322937
+transform 1 0 276 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_15
+timestamp 1638322937
+transform 1 0 1380 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_9
+timestamp 1638322937
+transform 1 0 2576 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1  FILLER_2_27
+timestamp 1638322937
+transform 1 0 2484 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_29
+timestamp 1638322937
+transform 1 0 2668 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_41
+timestamp 1638322937
+transform 1 0 3772 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_10
+timestamp 1638322937
+transform 1 0 5152 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4  FILLER_2_57
+timestamp 1638322937
+transform 1 0 5244 0 1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_2_61
+timestamp 1638322937
+transform 1 0 5612 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3  PHY_5
+timestamp 1638322937
+transform -1 0 5980 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  FILLER_2_53
+timestamp 1638322937
+transform 1 0 4876 0 1 1632
+box -38 -48 314 592
+<< labels >>
+rlabel metal5 s 0 1436 5980 1756 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 760 496 1040 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 2160 496 2440 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 3560 496 3840 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 4960 496 5240 2224 6 VGND
+port 0 nsew ground input
+rlabel metal5 s 0 736 5980 1056 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 60 496 340 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 1460 496 1740 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 2860 496 3140 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 4260 496 4540 2224 6 VPWR
+port 1 nsew power input
+rlabel metal2 s 202 0 258 400 6 gpio_defaults[0]
+port 2 nsew signal tristate
+rlabel metal2 s 4802 0 4858 400 6 gpio_defaults[10]
+port 3 nsew signal tristate
+rlabel metal2 s 5262 0 5318 400 6 gpio_defaults[11]
+port 4 nsew signal tristate
+rlabel metal2 s 5722 0 5778 400 6 gpio_defaults[12]
+port 5 nsew signal tristate
+rlabel metal2 s 662 0 718 400 6 gpio_defaults[1]
+port 6 nsew signal tristate
+rlabel metal2 s 1122 0 1178 400 6 gpio_defaults[2]
+port 7 nsew signal tristate
+rlabel metal2 s 1582 0 1638 400 6 gpio_defaults[3]
+port 8 nsew signal tristate
+rlabel metal2 s 2042 0 2098 400 6 gpio_defaults[4]
+port 9 nsew signal tristate
+rlabel metal2 s 2502 0 2558 400 6 gpio_defaults[5]
+port 10 nsew signal tristate
+rlabel metal2 s 2962 0 3018 400 6 gpio_defaults[6]
+port 11 nsew signal tristate
+rlabel metal2 s 3422 0 3478 400 6 gpio_defaults[7]
+port 12 nsew signal tristate
+rlabel metal2 s 3882 0 3938 400 6 gpio_defaults[8]
+port 13 nsew signal tristate
+rlabel metal2 s 4342 0 4398 400 6 gpio_defaults[9]
+port 14 nsew signal tristate
+<< properties >>
+string FIXED_BBOX 0 0 6000 2200
+<< end >>
diff --git a/tapeout/outputs/mag/gpio_defaults_block_0801.mag b/tapeout/outputs/mag/gpio_defaults_block_0801.mag
new file mode 100644
index 0000000..a5d837d
--- /dev/null
+++ b/tapeout/outputs/mag/gpio_defaults_block_0801.mag
@@ -0,0 +1,1461 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1638587925
+<< viali >>
+rect 949 833 983 867
+rect 1639 833 1673 867
+rect 4721 833 4755 867
+rect 1363 765 1397 799
+rect 1915 765 1949 799
+rect 2191 765 2225 799
+rect 2513 765 2547 799
+rect 2973 765 3007 799
+rect 3433 765 3467 799
+rect 3893 765 3927 799
+rect 4353 765 4387 799
+rect 4951 765 4985 799
+rect 5273 765 5307 799
+<< metal1 >>
+rect 0 2202 5980 2224
+rect 0 2150 78 2202
+rect 130 2150 142 2202
+rect 194 2150 206 2202
+rect 258 2150 270 2202
+rect 322 2150 1478 2202
+rect 1530 2150 1542 2202
+rect 1594 2150 1606 2202
+rect 1658 2150 1670 2202
+rect 1722 2150 2878 2202
+rect 2930 2150 2942 2202
+rect 2994 2150 3006 2202
+rect 3058 2150 3070 2202
+rect 3122 2150 4278 2202
+rect 4330 2150 4342 2202
+rect 4394 2150 4406 2202
+rect 4458 2150 4470 2202
+rect 4522 2150 5980 2202
+rect 0 2128 5980 2150
+rect 0 1658 5980 1680
+rect 0 1606 778 1658
+rect 830 1606 842 1658
+rect 894 1606 906 1658
+rect 958 1606 970 1658
+rect 1022 1606 2178 1658
+rect 2230 1606 2242 1658
+rect 2294 1606 2306 1658
+rect 2358 1606 2370 1658
+rect 2422 1606 3578 1658
+rect 3630 1606 3642 1658
+rect 3694 1606 3706 1658
+rect 3758 1606 3770 1658
+rect 3822 1606 4978 1658
+rect 5030 1606 5042 1658
+rect 5094 1606 5106 1658
+rect 5158 1606 5170 1658
+rect 5222 1606 5980 1658
+rect 0 1584 5980 1606
+rect 0 1114 5980 1136
+rect 0 1062 78 1114
+rect 130 1062 142 1114
+rect 194 1062 206 1114
+rect 258 1062 270 1114
+rect 322 1062 1478 1114
+rect 1530 1062 1542 1114
+rect 1594 1062 1606 1114
+rect 1658 1062 1670 1114
+rect 1722 1062 2878 1114
+rect 2930 1062 2942 1114
+rect 2994 1062 3006 1114
+rect 3058 1062 3070 1114
+rect 3122 1062 4278 1114
+rect 4330 1062 4342 1114
+rect 4394 1062 4406 1114
+rect 4458 1062 4470 1114
+rect 4522 1062 5980 1114
+rect 0 1040 5980 1062
+rect 198 824 204 876
+rect 256 864 262 876
+rect 937 864 995 873
+rect 1075 864 1133 873
+rect 1256 864 1262 916
+rect 1314 904 1320 916
+rect 1314 876 1450 904
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+rect 1422 864 1450 876
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+rect 256 824 262 836
+rect 937 827 995 836
+rect 1075 827 1133 836
+rect 1489 827 1547 836
+rect 1627 827 1685 836
+rect 4571 864 4629 873
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+rect 4571 827 4629 836
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+rect 5718 824 5724 836
+rect 5776 824 5782 876
+rect 1213 796 1271 805
+rect 1351 796 1409 805
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+rect 2038 796 2044 808
+rect 1038 768 1409 796
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+rect 658 688 664 740
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+rect 1038 728 1066 768
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+rect 2096 756 2102 768
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+rect 3267 768 3424 796
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+rect 4396 756 4402 808
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+rect 4798 756 4804 768
+rect 4856 796 4862 808
+rect 4936 796 5000 808
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+rect 3048 1056 3112 1060
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+rect 4288 1060 4292 1116
+rect 4292 1060 4348 1116
+rect 4348 1060 4352 1116
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+rect 4368 1116 4432 1120
+rect 4368 1060 4372 1116
+rect 4372 1060 4428 1116
+rect 4428 1060 4432 1116
+rect 4368 1056 4432 1060
+rect 4448 1116 4512 1120
+rect 4448 1060 4452 1116
+rect 4452 1060 4508 1116
+rect 4508 1060 4512 1116
+rect 4448 1056 4512 1060
+rect 788 572 852 576
+rect 788 516 792 572
+rect 792 516 848 572
+rect 848 516 852 572
+rect 788 512 852 516
+rect 868 572 932 576
+rect 868 516 872 572
+rect 872 516 928 572
+rect 928 516 932 572
+rect 868 512 932 516
+rect 948 572 1012 576
+rect 948 516 952 572
+rect 952 516 1008 572
+rect 1008 516 1012 572
+rect 948 512 1012 516
+rect 2188 572 2252 576
+rect 2188 516 2192 572
+rect 2192 516 2248 572
+rect 2248 516 2252 572
+rect 2188 512 2252 516
+rect 2268 572 2332 576
+rect 2268 516 2272 572
+rect 2272 516 2328 572
+rect 2328 516 2332 572
+rect 2268 512 2332 516
+rect 2348 572 2412 576
+rect 2348 516 2352 572
+rect 2352 516 2408 572
+rect 2408 516 2412 572
+rect 2348 512 2412 516
+rect 3588 572 3652 576
+rect 3588 516 3592 572
+rect 3592 516 3648 572
+rect 3648 516 3652 572
+rect 3588 512 3652 516
+rect 3668 572 3732 576
+rect 3668 516 3672 572
+rect 3672 516 3728 572
+rect 3728 516 3732 572
+rect 3668 512 3732 516
+rect 3748 572 3812 576
+rect 3748 516 3752 572
+rect 3752 516 3808 572
+rect 3808 516 3812 572
+rect 3748 512 3812 516
+rect 4988 572 5052 576
+rect 4988 516 4992 572
+rect 4992 516 5048 572
+rect 5048 516 5052 572
+rect 4988 512 5052 516
+rect 5068 572 5132 576
+rect 5068 516 5072 572
+rect 5072 516 5128 572
+rect 5128 516 5132 572
+rect 5068 512 5132 516
+rect 5148 572 5212 576
+rect 5148 516 5152 572
+rect 5152 516 5208 572
+rect 5208 516 5212 572
+rect 5148 512 5212 516
+<< metal4 >>
+rect 60 2208 340 2224
+rect 60 2144 88 2208
+rect 152 2144 168 2208
+rect 232 2144 248 2208
+rect 312 2144 340 2208
+rect 60 1120 340 2144
+rect 60 1056 88 1120
+rect 152 1056 168 1120
+rect 232 1056 248 1120
+rect 312 1056 340 1120
+rect 60 1014 340 1056
+rect 60 778 82 1014
+rect 318 778 340 1014
+rect 60 496 340 778
+rect 760 1714 1040 2224
+rect 760 1478 782 1714
+rect 1018 1478 1040 1714
+rect 760 576 1040 1478
+rect 760 512 788 576
+rect 852 512 868 576
+rect 932 512 948 576
+rect 1012 512 1040 576
+rect 760 496 1040 512
+rect 1460 2208 1740 2224
+rect 1460 2144 1488 2208
+rect 1552 2144 1568 2208
+rect 1632 2144 1648 2208
+rect 1712 2144 1740 2208
+rect 1460 1120 1740 2144
+rect 1460 1056 1488 1120
+rect 1552 1056 1568 1120
+rect 1632 1056 1648 1120
+rect 1712 1056 1740 1120
+rect 1460 1014 1740 1056
+rect 1460 778 1482 1014
+rect 1718 778 1740 1014
+rect 1460 496 1740 778
+rect 2160 1714 2440 2224
+rect 2160 1478 2182 1714
+rect 2418 1478 2440 1714
+rect 2160 576 2440 1478
+rect 2160 512 2188 576
+rect 2252 512 2268 576
+rect 2332 512 2348 576
+rect 2412 512 2440 576
+rect 2160 496 2440 512
+rect 2860 2208 3140 2224
+rect 2860 2144 2888 2208
+rect 2952 2144 2968 2208
+rect 3032 2144 3048 2208
+rect 3112 2144 3140 2208
+rect 2860 1120 3140 2144
+rect 2860 1056 2888 1120
+rect 2952 1056 2968 1120
+rect 3032 1056 3048 1120
+rect 3112 1056 3140 1120
+rect 2860 1014 3140 1056
+rect 2860 778 2882 1014
+rect 3118 778 3140 1014
+rect 2860 496 3140 778
+rect 3560 1714 3840 2224
+rect 3560 1478 3582 1714
+rect 3818 1478 3840 1714
+rect 3560 576 3840 1478
+rect 3560 512 3588 576
+rect 3652 512 3668 576
+rect 3732 512 3748 576
+rect 3812 512 3840 576
+rect 3560 496 3840 512
+rect 4260 2208 4540 2224
+rect 4260 2144 4288 2208
+rect 4352 2144 4368 2208
+rect 4432 2144 4448 2208
+rect 4512 2144 4540 2208
+rect 4260 1120 4540 2144
+rect 4260 1056 4288 1120
+rect 4352 1056 4368 1120
+rect 4432 1056 4448 1120
+rect 4512 1056 4540 1120
+rect 4260 1014 4540 1056
+rect 4260 778 4282 1014
+rect 4518 778 4540 1014
+rect 4260 496 4540 778
+rect 4960 1714 5240 2224
+rect 4960 1478 4982 1714
+rect 5218 1478 5240 1714
+rect 4960 576 5240 1478
+rect 4960 512 4988 576
+rect 5052 512 5068 576
+rect 5132 512 5148 576
+rect 5212 512 5240 576
+rect 4960 496 5240 512
+<< via4 >>
+rect 82 778 318 1014
+rect 782 1664 1018 1714
+rect 782 1600 788 1664
+rect 788 1600 852 1664
+rect 852 1600 868 1664
+rect 868 1600 932 1664
+rect 932 1600 948 1664
+rect 948 1600 1012 1664
+rect 1012 1600 1018 1664
+rect 782 1478 1018 1600
+rect 1482 778 1718 1014
+rect 2182 1664 2418 1714
+rect 2182 1600 2188 1664
+rect 2188 1600 2252 1664
+rect 2252 1600 2268 1664
+rect 2268 1600 2332 1664
+rect 2332 1600 2348 1664
+rect 2348 1600 2412 1664
+rect 2412 1600 2418 1664
+rect 2182 1478 2418 1600
+rect 2882 778 3118 1014
+rect 3582 1664 3818 1714
+rect 3582 1600 3588 1664
+rect 3588 1600 3652 1664
+rect 3652 1600 3668 1664
+rect 3668 1600 3732 1664
+rect 3732 1600 3748 1664
+rect 3748 1600 3812 1664
+rect 3812 1600 3818 1664
+rect 3582 1478 3818 1600
+rect 4282 778 4518 1014
+rect 4982 1664 5218 1714
+rect 4982 1600 4988 1664
+rect 4988 1600 5052 1664
+rect 5052 1600 5068 1664
+rect 5068 1600 5132 1664
+rect 5132 1600 5148 1664
+rect 5148 1600 5212 1664
+rect 5212 1600 5218 1664
+rect 4982 1478 5218 1600
+<< metal5 >>
+rect 0 1714 5980 1756
+rect 0 1478 782 1714
+rect 1018 1478 2182 1714
+rect 2418 1478 3582 1714
+rect 3818 1478 4982 1714
+rect 5218 1478 5980 1714
+rect 0 1436 5980 1478
+rect 0 1014 5980 1056
+rect 0 778 82 1014
+rect 318 778 1482 1014
+rect 1718 778 2882 1014
+rect 3118 778 4282 1014
+rect 4518 778 5980 1014
+rect 0 736 5980 778
+use sky130_fd_sc_hd__fill_1  FILLER_0_9 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 828 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3  PHY_2 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 0 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_0
+timestamp 1638322937
+transform 1 0 0 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 276 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_6  FILLER_0_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 276 0 1 544
+box -38 -48 590 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[0\] $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 920 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_15
+timestamp 1638322937
+transform 1 0 1380 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[5\]
+timestamp 1638322937
+transform 1 0 2300 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[1\]
+timestamp 1638322937
+transform 1 0 1196 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[4\]
+timestamp 1638322937
+transform 1 0 2024 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[3\]
+timestamp 1638322937
+transform 1 0 1748 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[2\]
+timestamp 1638322937
+transform 1 0 1472 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_6 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 2576 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_38 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 3496 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_33
+timestamp 1638322937
+transform 1 0 3036 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__fill_1  FILLER_0_29
+timestamp 1638322937
+transform 1 0 2668 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_27
+timestamp 1638322937
+transform 1 0 2484 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[7\]
+timestamp 1638322937
+transform 1 0 3220 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[6\]
+timestamp 1638322937
+transform 1 0 2760 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_43
+timestamp 1638322937
+transform 1 0 3956 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4  FILLER_1_51 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 4692 0 -1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_0_48
+timestamp 1638322937
+transform 1 0 4416 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_39
+timestamp 1638322937
+transform 1 0 3588 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[9\]
+timestamp 1638322937
+transform 1 0 4140 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[8\]
+timestamp 1638322937
+transform 1 0 3680 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[12\]
+timestamp 1638322937
+transform 1 0 4508 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_8
+timestamp 1638322937
+transform 1 0 5152 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_7
+timestamp 1638322937
+transform 1 0 5152 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1  FILLER_1_55
+timestamp 1638322937
+transform 1 0 5060 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1  FILLER_0_55
+timestamp 1638322937
+transform 1 0 5060 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[10\]
+timestamp 1638322937
+transform 1 0 4784 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_60
+timestamp 1638322937
+transform 1 0 5520 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4  FILLER_1_57
+timestamp 1638322937
+transform 1 0 5244 0 -1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_1_61
+timestamp 1638322937
+transform 1 0 5612 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[11\]
+timestamp 1638322937
+transform 1 0 5244 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_3
+timestamp 1638322937
+transform -1 0 5980 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_1
+timestamp 1638322937
+transform -1 0 5980 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_4
+timestamp 1638322937
+transform 1 0 0 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_3
+timestamp 1638322937
+transform 1 0 276 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_15
+timestamp 1638322937
+transform 1 0 1380 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_9
+timestamp 1638322937
+transform 1 0 2576 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1  FILLER_2_27
+timestamp 1638322937
+transform 1 0 2484 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_29
+timestamp 1638322937
+transform 1 0 2668 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_41
+timestamp 1638322937
+transform 1 0 3772 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_10
+timestamp 1638322937
+transform 1 0 5152 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4  FILLER_2_57
+timestamp 1638322937
+transform 1 0 5244 0 1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_2_61
+timestamp 1638322937
+transform 1 0 5612 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3  PHY_5
+timestamp 1638322937
+transform -1 0 5980 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  FILLER_2_53
+timestamp 1638322937
+transform 1 0 4876 0 1 1632
+box -38 -48 314 592
+<< labels >>
+rlabel metal5 s 0 1436 5980 1756 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 760 496 1040 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 2160 496 2440 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 3560 496 3840 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 4960 496 5240 2224 6 VGND
+port 0 nsew ground input
+rlabel metal5 s 0 736 5980 1056 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 60 496 340 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 1460 496 1740 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 2860 496 3140 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 4260 496 4540 2224 6 VPWR
+port 1 nsew power input
+rlabel metal2 s 202 0 258 400 6 gpio_defaults[0]
+port 2 nsew signal tristate
+rlabel metal2 s 4802 0 4858 400 6 gpio_defaults[10]
+port 3 nsew signal tristate
+rlabel metal2 s 5262 0 5318 400 6 gpio_defaults[11]
+port 4 nsew signal tristate
+rlabel metal2 s 5722 0 5778 400 6 gpio_defaults[12]
+port 5 nsew signal tristate
+rlabel metal2 s 662 0 718 400 6 gpio_defaults[1]
+port 6 nsew signal tristate
+rlabel metal2 s 1122 0 1178 400 6 gpio_defaults[2]
+port 7 nsew signal tristate
+rlabel metal2 s 1582 0 1638 400 6 gpio_defaults[3]
+port 8 nsew signal tristate
+rlabel metal2 s 2042 0 2098 400 6 gpio_defaults[4]
+port 9 nsew signal tristate
+rlabel metal2 s 2502 0 2558 400 6 gpio_defaults[5]
+port 10 nsew signal tristate
+rlabel metal2 s 2962 0 3018 400 6 gpio_defaults[6]
+port 11 nsew signal tristate
+rlabel metal2 s 3422 0 3478 400 6 gpio_defaults[7]
+port 12 nsew signal tristate
+rlabel metal2 s 3882 0 3938 400 6 gpio_defaults[8]
+port 13 nsew signal tristate
+rlabel metal2 s 4342 0 4398 400 6 gpio_defaults[9]
+port 14 nsew signal tristate
+<< properties >>
+string FIXED_BBOX 0 0 6000 2200
+<< end >>
diff --git a/tapeout/outputs/mag/gpio_defaults_block_1800.mag b/tapeout/outputs/mag/gpio_defaults_block_1800.mag
new file mode 100644
index 0000000..442025f
--- /dev/null
+++ b/tapeout/outputs/mag/gpio_defaults_block_1800.mag
@@ -0,0 +1,1461 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1638587925
+<< viali >>
+rect 1087 833 1121 867
+rect 1639 833 1673 867
+rect 4583 833 4617 867
+rect 1363 765 1397 799
+rect 1915 765 1949 799
+rect 2191 765 2225 799
+rect 2513 765 2547 799
+rect 2973 765 3007 799
+rect 3433 765 3467 799
+rect 3893 765 3927 799
+rect 4353 765 4387 799
+rect 4951 765 4985 799
+rect 5273 765 5307 799
+<< metal1 >>
+rect 0 2202 5980 2224
+rect 0 2150 78 2202
+rect 130 2150 142 2202
+rect 194 2150 206 2202
+rect 258 2150 270 2202
+rect 322 2150 1478 2202
+rect 1530 2150 1542 2202
+rect 1594 2150 1606 2202
+rect 1658 2150 1670 2202
+rect 1722 2150 2878 2202
+rect 2930 2150 2942 2202
+rect 2994 2150 3006 2202
+rect 3058 2150 3070 2202
+rect 3122 2150 4278 2202
+rect 4330 2150 4342 2202
+rect 4394 2150 4406 2202
+rect 4458 2150 4470 2202
+rect 4522 2150 5980 2202
+rect 0 2128 5980 2150
+rect 0 1658 5980 1680
+rect 0 1606 778 1658
+rect 830 1606 842 1658
+rect 894 1606 906 1658
+rect 958 1606 970 1658
+rect 1022 1606 2178 1658
+rect 2230 1606 2242 1658
+rect 2294 1606 2306 1658
+rect 2358 1606 2370 1658
+rect 2422 1606 3578 1658
+rect 3630 1606 3642 1658
+rect 3694 1606 3706 1658
+rect 3758 1606 3770 1658
+rect 3822 1606 4978 1658
+rect 5030 1606 5042 1658
+rect 5094 1606 5106 1658
+rect 5158 1606 5170 1658
+rect 5222 1606 5980 1658
+rect 0 1584 5980 1606
+rect 0 1114 5980 1136
+rect 0 1062 78 1114
+rect 130 1062 142 1114
+rect 194 1062 206 1114
+rect 258 1062 270 1114
+rect 322 1062 1478 1114
+rect 1530 1062 1542 1114
+rect 1594 1062 1606 1114
+rect 1658 1062 1670 1114
+rect 1722 1062 2878 1114
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+rect 2860 1055 3140 1056
+rect 4260 1120 4540 1121
+rect 4260 1056 4288 1120
+rect 4352 1056 4368 1120
+rect 4432 1056 4448 1120
+rect 4512 1056 4540 1120
+rect 4260 1055 4540 1056
+rect 760 576 1040 577
+rect 760 512 788 576
+rect 852 512 868 576
+rect 932 512 948 576
+rect 1012 512 1040 576
+rect 760 511 1040 512
+rect 2160 576 2440 577
+rect 2160 512 2188 576
+rect 2252 512 2268 576
+rect 2332 512 2348 576
+rect 2412 512 2440 576
+rect 2160 511 2440 512
+rect 3560 576 3840 577
+rect 3560 512 3588 576
+rect 3652 512 3668 576
+rect 3732 512 3748 576
+rect 3812 512 3840 576
+rect 3560 511 3840 512
+rect 4960 576 5240 577
+rect 4960 512 4988 576
+rect 5052 512 5068 576
+rect 5132 512 5148 576
+rect 5212 512 5240 576
+rect 4960 511 5240 512
+<< via3 >>
+rect 88 2204 152 2208
+rect 88 2148 92 2204
+rect 92 2148 148 2204
+rect 148 2148 152 2204
+rect 88 2144 152 2148
+rect 168 2204 232 2208
+rect 168 2148 172 2204
+rect 172 2148 228 2204
+rect 228 2148 232 2204
+rect 168 2144 232 2148
+rect 248 2204 312 2208
+rect 248 2148 252 2204
+rect 252 2148 308 2204
+rect 308 2148 312 2204
+rect 248 2144 312 2148
+rect 1488 2204 1552 2208
+rect 1488 2148 1492 2204
+rect 1492 2148 1548 2204
+rect 1548 2148 1552 2204
+rect 1488 2144 1552 2148
+rect 1568 2204 1632 2208
+rect 1568 2148 1572 2204
+rect 1572 2148 1628 2204
+rect 1628 2148 1632 2204
+rect 1568 2144 1632 2148
+rect 1648 2204 1712 2208
+rect 1648 2148 1652 2204
+rect 1652 2148 1708 2204
+rect 1708 2148 1712 2204
+rect 1648 2144 1712 2148
+rect 2888 2204 2952 2208
+rect 2888 2148 2892 2204
+rect 2892 2148 2948 2204
+rect 2948 2148 2952 2204
+rect 2888 2144 2952 2148
+rect 2968 2204 3032 2208
+rect 2968 2148 2972 2204
+rect 2972 2148 3028 2204
+rect 3028 2148 3032 2204
+rect 2968 2144 3032 2148
+rect 3048 2204 3112 2208
+rect 3048 2148 3052 2204
+rect 3052 2148 3108 2204
+rect 3108 2148 3112 2204
+rect 3048 2144 3112 2148
+rect 4288 2204 4352 2208
+rect 4288 2148 4292 2204
+rect 4292 2148 4348 2204
+rect 4348 2148 4352 2204
+rect 4288 2144 4352 2148
+rect 4368 2204 4432 2208
+rect 4368 2148 4372 2204
+rect 4372 2148 4428 2204
+rect 4428 2148 4432 2204
+rect 4368 2144 4432 2148
+rect 4448 2204 4512 2208
+rect 4448 2148 4452 2204
+rect 4452 2148 4508 2204
+rect 4508 2148 4512 2204
+rect 4448 2144 4512 2148
+rect 788 1660 852 1664
+rect 788 1604 792 1660
+rect 792 1604 848 1660
+rect 848 1604 852 1660
+rect 788 1600 852 1604
+rect 868 1660 932 1664
+rect 868 1604 872 1660
+rect 872 1604 928 1660
+rect 928 1604 932 1660
+rect 868 1600 932 1604
+rect 948 1660 1012 1664
+rect 948 1604 952 1660
+rect 952 1604 1008 1660
+rect 1008 1604 1012 1660
+rect 948 1600 1012 1604
+rect 2188 1660 2252 1664
+rect 2188 1604 2192 1660
+rect 2192 1604 2248 1660
+rect 2248 1604 2252 1660
+rect 2188 1600 2252 1604
+rect 2268 1660 2332 1664
+rect 2268 1604 2272 1660
+rect 2272 1604 2328 1660
+rect 2328 1604 2332 1660
+rect 2268 1600 2332 1604
+rect 2348 1660 2412 1664
+rect 2348 1604 2352 1660
+rect 2352 1604 2408 1660
+rect 2408 1604 2412 1660
+rect 2348 1600 2412 1604
+rect 3588 1660 3652 1664
+rect 3588 1604 3592 1660
+rect 3592 1604 3648 1660
+rect 3648 1604 3652 1660
+rect 3588 1600 3652 1604
+rect 3668 1660 3732 1664
+rect 3668 1604 3672 1660
+rect 3672 1604 3728 1660
+rect 3728 1604 3732 1660
+rect 3668 1600 3732 1604
+rect 3748 1660 3812 1664
+rect 3748 1604 3752 1660
+rect 3752 1604 3808 1660
+rect 3808 1604 3812 1660
+rect 3748 1600 3812 1604
+rect 4988 1660 5052 1664
+rect 4988 1604 4992 1660
+rect 4992 1604 5048 1660
+rect 5048 1604 5052 1660
+rect 4988 1600 5052 1604
+rect 5068 1660 5132 1664
+rect 5068 1604 5072 1660
+rect 5072 1604 5128 1660
+rect 5128 1604 5132 1660
+rect 5068 1600 5132 1604
+rect 5148 1660 5212 1664
+rect 5148 1604 5152 1660
+rect 5152 1604 5208 1660
+rect 5208 1604 5212 1660
+rect 5148 1600 5212 1604
+rect 88 1116 152 1120
+rect 88 1060 92 1116
+rect 92 1060 148 1116
+rect 148 1060 152 1116
+rect 88 1056 152 1060
+rect 168 1116 232 1120
+rect 168 1060 172 1116
+rect 172 1060 228 1116
+rect 228 1060 232 1116
+rect 168 1056 232 1060
+rect 248 1116 312 1120
+rect 248 1060 252 1116
+rect 252 1060 308 1116
+rect 308 1060 312 1116
+rect 248 1056 312 1060
+rect 1488 1116 1552 1120
+rect 1488 1060 1492 1116
+rect 1492 1060 1548 1116
+rect 1548 1060 1552 1116
+rect 1488 1056 1552 1060
+rect 1568 1116 1632 1120
+rect 1568 1060 1572 1116
+rect 1572 1060 1628 1116
+rect 1628 1060 1632 1116
+rect 1568 1056 1632 1060
+rect 1648 1116 1712 1120
+rect 1648 1060 1652 1116
+rect 1652 1060 1708 1116
+rect 1708 1060 1712 1116
+rect 1648 1056 1712 1060
+rect 2888 1116 2952 1120
+rect 2888 1060 2892 1116
+rect 2892 1060 2948 1116
+rect 2948 1060 2952 1116
+rect 2888 1056 2952 1060
+rect 2968 1116 3032 1120
+rect 2968 1060 2972 1116
+rect 2972 1060 3028 1116
+rect 3028 1060 3032 1116
+rect 2968 1056 3032 1060
+rect 3048 1116 3112 1120
+rect 3048 1060 3052 1116
+rect 3052 1060 3108 1116
+rect 3108 1060 3112 1116
+rect 3048 1056 3112 1060
+rect 4288 1116 4352 1120
+rect 4288 1060 4292 1116
+rect 4292 1060 4348 1116
+rect 4348 1060 4352 1116
+rect 4288 1056 4352 1060
+rect 4368 1116 4432 1120
+rect 4368 1060 4372 1116
+rect 4372 1060 4428 1116
+rect 4428 1060 4432 1116
+rect 4368 1056 4432 1060
+rect 4448 1116 4512 1120
+rect 4448 1060 4452 1116
+rect 4452 1060 4508 1116
+rect 4508 1060 4512 1116
+rect 4448 1056 4512 1060
+rect 788 572 852 576
+rect 788 516 792 572
+rect 792 516 848 572
+rect 848 516 852 572
+rect 788 512 852 516
+rect 868 572 932 576
+rect 868 516 872 572
+rect 872 516 928 572
+rect 928 516 932 572
+rect 868 512 932 516
+rect 948 572 1012 576
+rect 948 516 952 572
+rect 952 516 1008 572
+rect 1008 516 1012 572
+rect 948 512 1012 516
+rect 2188 572 2252 576
+rect 2188 516 2192 572
+rect 2192 516 2248 572
+rect 2248 516 2252 572
+rect 2188 512 2252 516
+rect 2268 572 2332 576
+rect 2268 516 2272 572
+rect 2272 516 2328 572
+rect 2328 516 2332 572
+rect 2268 512 2332 516
+rect 2348 572 2412 576
+rect 2348 516 2352 572
+rect 2352 516 2408 572
+rect 2408 516 2412 572
+rect 2348 512 2412 516
+rect 3588 572 3652 576
+rect 3588 516 3592 572
+rect 3592 516 3648 572
+rect 3648 516 3652 572
+rect 3588 512 3652 516
+rect 3668 572 3732 576
+rect 3668 516 3672 572
+rect 3672 516 3728 572
+rect 3728 516 3732 572
+rect 3668 512 3732 516
+rect 3748 572 3812 576
+rect 3748 516 3752 572
+rect 3752 516 3808 572
+rect 3808 516 3812 572
+rect 3748 512 3812 516
+rect 4988 572 5052 576
+rect 4988 516 4992 572
+rect 4992 516 5048 572
+rect 5048 516 5052 572
+rect 4988 512 5052 516
+rect 5068 572 5132 576
+rect 5068 516 5072 572
+rect 5072 516 5128 572
+rect 5128 516 5132 572
+rect 5068 512 5132 516
+rect 5148 572 5212 576
+rect 5148 516 5152 572
+rect 5152 516 5208 572
+rect 5208 516 5212 572
+rect 5148 512 5212 516
+<< metal4 >>
+rect 60 2208 340 2224
+rect 60 2144 88 2208
+rect 152 2144 168 2208
+rect 232 2144 248 2208
+rect 312 2144 340 2208
+rect 60 1120 340 2144
+rect 60 1056 88 1120
+rect 152 1056 168 1120
+rect 232 1056 248 1120
+rect 312 1056 340 1120
+rect 60 1014 340 1056
+rect 60 778 82 1014
+rect 318 778 340 1014
+rect 60 496 340 778
+rect 760 1714 1040 2224
+rect 760 1478 782 1714
+rect 1018 1478 1040 1714
+rect 760 576 1040 1478
+rect 760 512 788 576
+rect 852 512 868 576
+rect 932 512 948 576
+rect 1012 512 1040 576
+rect 760 496 1040 512
+rect 1460 2208 1740 2224
+rect 1460 2144 1488 2208
+rect 1552 2144 1568 2208
+rect 1632 2144 1648 2208
+rect 1712 2144 1740 2208
+rect 1460 1120 1740 2144
+rect 1460 1056 1488 1120
+rect 1552 1056 1568 1120
+rect 1632 1056 1648 1120
+rect 1712 1056 1740 1120
+rect 1460 1014 1740 1056
+rect 1460 778 1482 1014
+rect 1718 778 1740 1014
+rect 1460 496 1740 778
+rect 2160 1714 2440 2224
+rect 2160 1478 2182 1714
+rect 2418 1478 2440 1714
+rect 2160 576 2440 1478
+rect 2160 512 2188 576
+rect 2252 512 2268 576
+rect 2332 512 2348 576
+rect 2412 512 2440 576
+rect 2160 496 2440 512
+rect 2860 2208 3140 2224
+rect 2860 2144 2888 2208
+rect 2952 2144 2968 2208
+rect 3032 2144 3048 2208
+rect 3112 2144 3140 2208
+rect 2860 1120 3140 2144
+rect 2860 1056 2888 1120
+rect 2952 1056 2968 1120
+rect 3032 1056 3048 1120
+rect 3112 1056 3140 1120
+rect 2860 1014 3140 1056
+rect 2860 778 2882 1014
+rect 3118 778 3140 1014
+rect 2860 496 3140 778
+rect 3560 1714 3840 2224
+rect 3560 1478 3582 1714
+rect 3818 1478 3840 1714
+rect 3560 576 3840 1478
+rect 3560 512 3588 576
+rect 3652 512 3668 576
+rect 3732 512 3748 576
+rect 3812 512 3840 576
+rect 3560 496 3840 512
+rect 4260 2208 4540 2224
+rect 4260 2144 4288 2208
+rect 4352 2144 4368 2208
+rect 4432 2144 4448 2208
+rect 4512 2144 4540 2208
+rect 4260 1120 4540 2144
+rect 4260 1056 4288 1120
+rect 4352 1056 4368 1120
+rect 4432 1056 4448 1120
+rect 4512 1056 4540 1120
+rect 4260 1014 4540 1056
+rect 4260 778 4282 1014
+rect 4518 778 4540 1014
+rect 4260 496 4540 778
+rect 4960 1714 5240 2224
+rect 4960 1478 4982 1714
+rect 5218 1478 5240 1714
+rect 4960 576 5240 1478
+rect 4960 512 4988 576
+rect 5052 512 5068 576
+rect 5132 512 5148 576
+rect 5212 512 5240 576
+rect 4960 496 5240 512
+<< via4 >>
+rect 82 778 318 1014
+rect 782 1664 1018 1714
+rect 782 1600 788 1664
+rect 788 1600 852 1664
+rect 852 1600 868 1664
+rect 868 1600 932 1664
+rect 932 1600 948 1664
+rect 948 1600 1012 1664
+rect 1012 1600 1018 1664
+rect 782 1478 1018 1600
+rect 1482 778 1718 1014
+rect 2182 1664 2418 1714
+rect 2182 1600 2188 1664
+rect 2188 1600 2252 1664
+rect 2252 1600 2268 1664
+rect 2268 1600 2332 1664
+rect 2332 1600 2348 1664
+rect 2348 1600 2412 1664
+rect 2412 1600 2418 1664
+rect 2182 1478 2418 1600
+rect 2882 778 3118 1014
+rect 3582 1664 3818 1714
+rect 3582 1600 3588 1664
+rect 3588 1600 3652 1664
+rect 3652 1600 3668 1664
+rect 3668 1600 3732 1664
+rect 3732 1600 3748 1664
+rect 3748 1600 3812 1664
+rect 3812 1600 3818 1664
+rect 3582 1478 3818 1600
+rect 4282 778 4518 1014
+rect 4982 1664 5218 1714
+rect 4982 1600 4988 1664
+rect 4988 1600 5052 1664
+rect 5052 1600 5068 1664
+rect 5068 1600 5132 1664
+rect 5132 1600 5148 1664
+rect 5148 1600 5212 1664
+rect 5212 1600 5218 1664
+rect 4982 1478 5218 1600
+<< metal5 >>
+rect 0 1714 5980 1756
+rect 0 1478 782 1714
+rect 1018 1478 2182 1714
+rect 2418 1478 3582 1714
+rect 3818 1478 4982 1714
+rect 5218 1478 5980 1714
+rect 0 1436 5980 1478
+rect 0 1014 5980 1056
+rect 0 778 82 1014
+rect 318 778 1482 1014
+rect 1718 778 2882 1014
+rect 3118 778 4282 1014
+rect 4518 778 5980 1014
+rect 0 736 5980 778
+use sky130_fd_sc_hd__fill_1  FILLER_0_9 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 828 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3  PHY_2 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 0 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_0
+timestamp 1638322937
+transform 1 0 0 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 276 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_6  FILLER_0_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 276 0 1 544
+box -38 -48 590 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[0\] $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 920 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_15
+timestamp 1638322937
+transform 1 0 1380 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[5\]
+timestamp 1638322937
+transform 1 0 2300 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[1\]
+timestamp 1638322937
+transform 1 0 1196 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[4\]
+timestamp 1638322937
+transform 1 0 2024 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[3\]
+timestamp 1638322937
+transform 1 0 1748 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[2\]
+timestamp 1638322937
+transform 1 0 1472 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_6 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 2576 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_38 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 3496 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_33
+timestamp 1638322937
+transform 1 0 3036 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__fill_1  FILLER_0_29
+timestamp 1638322937
+transform 1 0 2668 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_27
+timestamp 1638322937
+transform 1 0 2484 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[7\]
+timestamp 1638322937
+transform 1 0 3220 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[6\]
+timestamp 1638322937
+transform 1 0 2760 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_43
+timestamp 1638322937
+transform 1 0 3956 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4  FILLER_1_51 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 4692 0 -1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_0_48
+timestamp 1638322937
+transform 1 0 4416 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_39
+timestamp 1638322937
+transform 1 0 3588 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[9\]
+timestamp 1638322937
+transform 1 0 4140 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[8\]
+timestamp 1638322937
+transform 1 0 3680 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[12\]
+timestamp 1638322937
+transform 1 0 4508 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_8
+timestamp 1638322937
+transform 1 0 5152 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_7
+timestamp 1638322937
+transform 1 0 5152 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1  FILLER_1_55
+timestamp 1638322937
+transform 1 0 5060 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1  FILLER_0_55
+timestamp 1638322937
+transform 1 0 5060 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[10\]
+timestamp 1638322937
+transform 1 0 4784 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_60
+timestamp 1638322937
+transform 1 0 5520 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4  FILLER_1_57
+timestamp 1638322937
+transform 1 0 5244 0 -1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_1_61
+timestamp 1638322937
+transform 1 0 5612 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[11\]
+timestamp 1638322937
+transform 1 0 5244 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_3
+timestamp 1638322937
+transform -1 0 5980 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_1
+timestamp 1638322937
+transform -1 0 5980 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_4
+timestamp 1638322937
+transform 1 0 0 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_3
+timestamp 1638322937
+transform 1 0 276 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_15
+timestamp 1638322937
+transform 1 0 1380 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_9
+timestamp 1638322937
+transform 1 0 2576 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1  FILLER_2_27
+timestamp 1638322937
+transform 1 0 2484 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_29
+timestamp 1638322937
+transform 1 0 2668 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_41
+timestamp 1638322937
+transform 1 0 3772 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_10
+timestamp 1638322937
+transform 1 0 5152 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4  FILLER_2_57
+timestamp 1638322937
+transform 1 0 5244 0 1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_2_61
+timestamp 1638322937
+transform 1 0 5612 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3  PHY_5
+timestamp 1638322937
+transform -1 0 5980 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  FILLER_2_53
+timestamp 1638322937
+transform 1 0 4876 0 1 1632
+box -38 -48 314 592
+<< labels >>
+rlabel metal5 s 0 1436 5980 1756 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 760 496 1040 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 2160 496 2440 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 3560 496 3840 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 4960 496 5240 2224 6 VGND
+port 0 nsew ground input
+rlabel metal5 s 0 736 5980 1056 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 60 496 340 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 1460 496 1740 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 2860 496 3140 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 4260 496 4540 2224 6 VPWR
+port 1 nsew power input
+rlabel metal2 s 202 0 258 400 6 gpio_defaults[0]
+port 2 nsew signal tristate
+rlabel metal2 s 4802 0 4858 400 6 gpio_defaults[10]
+port 3 nsew signal tristate
+rlabel metal2 s 5262 0 5318 400 6 gpio_defaults[11]
+port 4 nsew signal tristate
+rlabel metal2 s 5722 0 5778 400 6 gpio_defaults[12]
+port 5 nsew signal tristate
+rlabel metal2 s 662 0 718 400 6 gpio_defaults[1]
+port 6 nsew signal tristate
+rlabel metal2 s 1122 0 1178 400 6 gpio_defaults[2]
+port 7 nsew signal tristate
+rlabel metal2 s 1582 0 1638 400 6 gpio_defaults[3]
+port 8 nsew signal tristate
+rlabel metal2 s 2042 0 2098 400 6 gpio_defaults[4]
+port 9 nsew signal tristate
+rlabel metal2 s 2502 0 2558 400 6 gpio_defaults[5]
+port 10 nsew signal tristate
+rlabel metal2 s 2962 0 3018 400 6 gpio_defaults[6]
+port 11 nsew signal tristate
+rlabel metal2 s 3422 0 3478 400 6 gpio_defaults[7]
+port 12 nsew signal tristate
+rlabel metal2 s 3882 0 3938 400 6 gpio_defaults[8]
+port 13 nsew signal tristate
+rlabel metal2 s 4342 0 4398 400 6 gpio_defaults[9]
+port 14 nsew signal tristate
+<< properties >>
+string FIXED_BBOX 0 0 6000 2200
+<< end >>
diff --git a/tapeout/outputs/mag/gpio_defaults_block_1803.mag b/tapeout/outputs/mag/gpio_defaults_block_1803.mag
new file mode 100644
index 0000000..39a381a
--- /dev/null
+++ b/tapeout/outputs/mag/gpio_defaults_block_1803.mag
@@ -0,0 +1,1461 @@
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+magscale 1 2
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+rect 2352 518 2358 570
+rect 2358 518 2370 570
+rect 2370 518 2408 570
+rect 2192 516 2248 518
+rect 2272 516 2328 518
+rect 2352 516 2408 518
+rect 3592 570 3648 572
+rect 3672 570 3728 572
+rect 3752 570 3808 572
+rect 3592 518 3630 570
+rect 3630 518 3642 570
+rect 3642 518 3648 570
+rect 3672 518 3694 570
+rect 3694 518 3706 570
+rect 3706 518 3728 570
+rect 3752 518 3758 570
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+rect 3770 518 3808 570
+rect 3592 516 3648 518
+rect 3672 516 3728 518
+rect 3752 516 3808 518
+rect 4992 570 5048 572
+rect 5072 570 5128 572
+rect 5152 570 5208 572
+rect 4992 518 5030 570
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+rect 5158 518 5170 570
+rect 5170 518 5208 570
+rect 4992 516 5048 518
+rect 5072 516 5128 518
+rect 5152 516 5208 518
+<< metal3 >>
+rect 60 2208 340 2209
+rect 60 2144 88 2208
+rect 152 2144 168 2208
+rect 232 2144 248 2208
+rect 312 2144 340 2208
+rect 60 2143 340 2144
+rect 1460 2208 1740 2209
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+rect 1552 2144 1568 2208
+rect 1632 2144 1648 2208
+rect 1712 2144 1740 2208
+rect 1460 2143 1740 2144
+rect 2860 2208 3140 2209
+rect 2860 2144 2888 2208
+rect 2952 2144 2968 2208
+rect 3032 2144 3048 2208
+rect 3112 2144 3140 2208
+rect 2860 2143 3140 2144
+rect 4260 2208 4540 2209
+rect 4260 2144 4288 2208
+rect 4352 2144 4368 2208
+rect 4432 2144 4448 2208
+rect 4512 2144 4540 2208
+rect 4260 2143 4540 2144
+rect 760 1664 1040 1665
+rect 760 1600 788 1664
+rect 852 1600 868 1664
+rect 932 1600 948 1664
+rect 1012 1600 1040 1664
+rect 760 1599 1040 1600
+rect 2160 1664 2440 1665
+rect 2160 1600 2188 1664
+rect 2252 1600 2268 1664
+rect 2332 1600 2348 1664
+rect 2412 1600 2440 1664
+rect 2160 1599 2440 1600
+rect 3560 1664 3840 1665
+rect 3560 1600 3588 1664
+rect 3652 1600 3668 1664
+rect 3732 1600 3748 1664
+rect 3812 1600 3840 1664
+rect 3560 1599 3840 1600
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+rect 4960 1600 4988 1664
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+rect 5212 1600 5240 1664
+rect 4960 1599 5240 1600
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+rect 312 1056 340 1120
+rect 60 1055 340 1056
+rect 1460 1120 1740 1121
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+rect 1552 1056 1568 1120
+rect 1632 1056 1648 1120
+rect 1712 1056 1740 1120
+rect 1460 1055 1740 1056
+rect 2860 1120 3140 1121
+rect 2860 1056 2888 1120
+rect 2952 1056 2968 1120
+rect 3032 1056 3048 1120
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+rect 2860 1055 3140 1056
+rect 4260 1120 4540 1121
+rect 4260 1056 4288 1120
+rect 4352 1056 4368 1120
+rect 4432 1056 4448 1120
+rect 4512 1056 4540 1120
+rect 4260 1055 4540 1056
+rect 760 576 1040 577
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+rect 2160 511 2440 512
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+rect 3652 512 3668 576
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+rect 3812 512 3840 576
+rect 3560 511 3840 512
+rect 4960 576 5240 577
+rect 4960 512 4988 576
+rect 5052 512 5068 576
+rect 5132 512 5148 576
+rect 5212 512 5240 576
+rect 4960 511 5240 512
+<< via3 >>
+rect 88 2204 152 2208
+rect 88 2148 92 2204
+rect 92 2148 148 2204
+rect 148 2148 152 2204
+rect 88 2144 152 2148
+rect 168 2204 232 2208
+rect 168 2148 172 2204
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+rect 228 2148 232 2204
+rect 168 2144 232 2148
+rect 248 2204 312 2208
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+rect 252 2148 308 2204
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+rect 248 2144 312 2148
+rect 1488 2204 1552 2208
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+rect 1492 2148 1548 2204
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+rect 1488 2144 1552 2148
+rect 1568 2204 1632 2208
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+rect 1572 2148 1628 2204
+rect 1628 2148 1632 2204
+rect 1568 2144 1632 2148
+rect 1648 2204 1712 2208
+rect 1648 2148 1652 2204
+rect 1652 2148 1708 2204
+rect 1708 2148 1712 2204
+rect 1648 2144 1712 2148
+rect 2888 2204 2952 2208
+rect 2888 2148 2892 2204
+rect 2892 2148 2948 2204
+rect 2948 2148 2952 2204
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+rect 2968 2204 3032 2208
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+rect 3028 2148 3032 2204
+rect 2968 2144 3032 2148
+rect 3048 2204 3112 2208
+rect 3048 2148 3052 2204
+rect 3052 2148 3108 2204
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+rect 4288 2204 4352 2208
+rect 4288 2148 4292 2204
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+rect 4288 2144 4352 2148
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+rect 4372 2148 4428 2204
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+rect 4368 2144 4432 2148
+rect 4448 2204 4512 2208
+rect 4448 2148 4452 2204
+rect 4452 2148 4508 2204
+rect 4508 2148 4512 2204
+rect 4448 2144 4512 2148
+rect 788 1660 852 1664
+rect 788 1604 792 1660
+rect 792 1604 848 1660
+rect 848 1604 852 1660
+rect 788 1600 852 1604
+rect 868 1660 932 1664
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+rect 872 1604 928 1660
+rect 928 1604 932 1660
+rect 868 1600 932 1604
+rect 948 1660 1012 1664
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+rect 952 1604 1008 1660
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+rect 2268 1660 2332 1664
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+rect 2348 1660 2412 1664
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+rect 2352 1604 2408 1660
+rect 2408 1604 2412 1660
+rect 2348 1600 2412 1604
+rect 3588 1660 3652 1664
+rect 3588 1604 3592 1660
+rect 3592 1604 3648 1660
+rect 3648 1604 3652 1660
+rect 3588 1600 3652 1604
+rect 3668 1660 3732 1664
+rect 3668 1604 3672 1660
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+rect 3728 1604 3732 1660
+rect 3668 1600 3732 1604
+rect 3748 1660 3812 1664
+rect 3748 1604 3752 1660
+rect 3752 1604 3808 1660
+rect 3808 1604 3812 1660
+rect 3748 1600 3812 1604
+rect 4988 1660 5052 1664
+rect 4988 1604 4992 1660
+rect 4992 1604 5048 1660
+rect 5048 1604 5052 1660
+rect 4988 1600 5052 1604
+rect 5068 1660 5132 1664
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+rect 5072 1604 5128 1660
+rect 5128 1604 5132 1660
+rect 5068 1600 5132 1604
+rect 5148 1660 5212 1664
+rect 5148 1604 5152 1660
+rect 5152 1604 5208 1660
+rect 5208 1604 5212 1660
+rect 5148 1600 5212 1604
+rect 88 1116 152 1120
+rect 88 1060 92 1116
+rect 92 1060 148 1116
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+rect 88 1056 152 1060
+rect 168 1116 232 1120
+rect 168 1060 172 1116
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+rect 168 1056 232 1060
+rect 248 1116 312 1120
+rect 248 1060 252 1116
+rect 252 1060 308 1116
+rect 308 1060 312 1116
+rect 248 1056 312 1060
+rect 1488 1116 1552 1120
+rect 1488 1060 1492 1116
+rect 1492 1060 1548 1116
+rect 1548 1060 1552 1116
+rect 1488 1056 1552 1060
+rect 1568 1116 1632 1120
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+rect 1572 1060 1628 1116
+rect 1628 1060 1632 1116
+rect 1568 1056 1632 1060
+rect 1648 1116 1712 1120
+rect 1648 1060 1652 1116
+rect 1652 1060 1708 1116
+rect 1708 1060 1712 1116
+rect 1648 1056 1712 1060
+rect 2888 1116 2952 1120
+rect 2888 1060 2892 1116
+rect 2892 1060 2948 1116
+rect 2948 1060 2952 1116
+rect 2888 1056 2952 1060
+rect 2968 1116 3032 1120
+rect 2968 1060 2972 1116
+rect 2972 1060 3028 1116
+rect 3028 1060 3032 1116
+rect 2968 1056 3032 1060
+rect 3048 1116 3112 1120
+rect 3048 1060 3052 1116
+rect 3052 1060 3108 1116
+rect 3108 1060 3112 1116
+rect 3048 1056 3112 1060
+rect 4288 1116 4352 1120
+rect 4288 1060 4292 1116
+rect 4292 1060 4348 1116
+rect 4348 1060 4352 1116
+rect 4288 1056 4352 1060
+rect 4368 1116 4432 1120
+rect 4368 1060 4372 1116
+rect 4372 1060 4428 1116
+rect 4428 1060 4432 1116
+rect 4368 1056 4432 1060
+rect 4448 1116 4512 1120
+rect 4448 1060 4452 1116
+rect 4452 1060 4508 1116
+rect 4508 1060 4512 1116
+rect 4448 1056 4512 1060
+rect 788 572 852 576
+rect 788 516 792 572
+rect 792 516 848 572
+rect 848 516 852 572
+rect 788 512 852 516
+rect 868 572 932 576
+rect 868 516 872 572
+rect 872 516 928 572
+rect 928 516 932 572
+rect 868 512 932 516
+rect 948 572 1012 576
+rect 948 516 952 572
+rect 952 516 1008 572
+rect 1008 516 1012 572
+rect 948 512 1012 516
+rect 2188 572 2252 576
+rect 2188 516 2192 572
+rect 2192 516 2248 572
+rect 2248 516 2252 572
+rect 2188 512 2252 516
+rect 2268 572 2332 576
+rect 2268 516 2272 572
+rect 2272 516 2328 572
+rect 2328 516 2332 572
+rect 2268 512 2332 516
+rect 2348 572 2412 576
+rect 2348 516 2352 572
+rect 2352 516 2408 572
+rect 2408 516 2412 572
+rect 2348 512 2412 516
+rect 3588 572 3652 576
+rect 3588 516 3592 572
+rect 3592 516 3648 572
+rect 3648 516 3652 572
+rect 3588 512 3652 516
+rect 3668 572 3732 576
+rect 3668 516 3672 572
+rect 3672 516 3728 572
+rect 3728 516 3732 572
+rect 3668 512 3732 516
+rect 3748 572 3812 576
+rect 3748 516 3752 572
+rect 3752 516 3808 572
+rect 3808 516 3812 572
+rect 3748 512 3812 516
+rect 4988 572 5052 576
+rect 4988 516 4992 572
+rect 4992 516 5048 572
+rect 5048 516 5052 572
+rect 4988 512 5052 516
+rect 5068 572 5132 576
+rect 5068 516 5072 572
+rect 5072 516 5128 572
+rect 5128 516 5132 572
+rect 5068 512 5132 516
+rect 5148 572 5212 576
+rect 5148 516 5152 572
+rect 5152 516 5208 572
+rect 5208 516 5212 572
+rect 5148 512 5212 516
+<< metal4 >>
+rect 60 2208 340 2224
+rect 60 2144 88 2208
+rect 152 2144 168 2208
+rect 232 2144 248 2208
+rect 312 2144 340 2208
+rect 60 1120 340 2144
+rect 60 1056 88 1120
+rect 152 1056 168 1120
+rect 232 1056 248 1120
+rect 312 1056 340 1120
+rect 60 1014 340 1056
+rect 60 778 82 1014
+rect 318 778 340 1014
+rect 60 496 340 778
+rect 760 1714 1040 2224
+rect 760 1478 782 1714
+rect 1018 1478 1040 1714
+rect 760 576 1040 1478
+rect 760 512 788 576
+rect 852 512 868 576
+rect 932 512 948 576
+rect 1012 512 1040 576
+rect 760 496 1040 512
+rect 1460 2208 1740 2224
+rect 1460 2144 1488 2208
+rect 1552 2144 1568 2208
+rect 1632 2144 1648 2208
+rect 1712 2144 1740 2208
+rect 1460 1120 1740 2144
+rect 1460 1056 1488 1120
+rect 1552 1056 1568 1120
+rect 1632 1056 1648 1120
+rect 1712 1056 1740 1120
+rect 1460 1014 1740 1056
+rect 1460 778 1482 1014
+rect 1718 778 1740 1014
+rect 1460 496 1740 778
+rect 2160 1714 2440 2224
+rect 2160 1478 2182 1714
+rect 2418 1478 2440 1714
+rect 2160 576 2440 1478
+rect 2160 512 2188 576
+rect 2252 512 2268 576
+rect 2332 512 2348 576
+rect 2412 512 2440 576
+rect 2160 496 2440 512
+rect 2860 2208 3140 2224
+rect 2860 2144 2888 2208
+rect 2952 2144 2968 2208
+rect 3032 2144 3048 2208
+rect 3112 2144 3140 2208
+rect 2860 1120 3140 2144
+rect 2860 1056 2888 1120
+rect 2952 1056 2968 1120
+rect 3032 1056 3048 1120
+rect 3112 1056 3140 1120
+rect 2860 1014 3140 1056
+rect 2860 778 2882 1014
+rect 3118 778 3140 1014
+rect 2860 496 3140 778
+rect 3560 1714 3840 2224
+rect 3560 1478 3582 1714
+rect 3818 1478 3840 1714
+rect 3560 576 3840 1478
+rect 3560 512 3588 576
+rect 3652 512 3668 576
+rect 3732 512 3748 576
+rect 3812 512 3840 576
+rect 3560 496 3840 512
+rect 4260 2208 4540 2224
+rect 4260 2144 4288 2208
+rect 4352 2144 4368 2208
+rect 4432 2144 4448 2208
+rect 4512 2144 4540 2208
+rect 4260 1120 4540 2144
+rect 4260 1056 4288 1120
+rect 4352 1056 4368 1120
+rect 4432 1056 4448 1120
+rect 4512 1056 4540 1120
+rect 4260 1014 4540 1056
+rect 4260 778 4282 1014
+rect 4518 778 4540 1014
+rect 4260 496 4540 778
+rect 4960 1714 5240 2224
+rect 4960 1478 4982 1714
+rect 5218 1478 5240 1714
+rect 4960 576 5240 1478
+rect 4960 512 4988 576
+rect 5052 512 5068 576
+rect 5132 512 5148 576
+rect 5212 512 5240 576
+rect 4960 496 5240 512
+<< via4 >>
+rect 82 778 318 1014
+rect 782 1664 1018 1714
+rect 782 1600 788 1664
+rect 788 1600 852 1664
+rect 852 1600 868 1664
+rect 868 1600 932 1664
+rect 932 1600 948 1664
+rect 948 1600 1012 1664
+rect 1012 1600 1018 1664
+rect 782 1478 1018 1600
+rect 1482 778 1718 1014
+rect 2182 1664 2418 1714
+rect 2182 1600 2188 1664
+rect 2188 1600 2252 1664
+rect 2252 1600 2268 1664
+rect 2268 1600 2332 1664
+rect 2332 1600 2348 1664
+rect 2348 1600 2412 1664
+rect 2412 1600 2418 1664
+rect 2182 1478 2418 1600
+rect 2882 778 3118 1014
+rect 3582 1664 3818 1714
+rect 3582 1600 3588 1664
+rect 3588 1600 3652 1664
+rect 3652 1600 3668 1664
+rect 3668 1600 3732 1664
+rect 3732 1600 3748 1664
+rect 3748 1600 3812 1664
+rect 3812 1600 3818 1664
+rect 3582 1478 3818 1600
+rect 4282 778 4518 1014
+rect 4982 1664 5218 1714
+rect 4982 1600 4988 1664
+rect 4988 1600 5052 1664
+rect 5052 1600 5068 1664
+rect 5068 1600 5132 1664
+rect 5132 1600 5148 1664
+rect 5148 1600 5212 1664
+rect 5212 1600 5218 1664
+rect 4982 1478 5218 1600
+<< metal5 >>
+rect 0 1714 5980 1756
+rect 0 1478 782 1714
+rect 1018 1478 2182 1714
+rect 2418 1478 3582 1714
+rect 3818 1478 4982 1714
+rect 5218 1478 5980 1714
+rect 0 1436 5980 1478
+rect 0 1014 5980 1056
+rect 0 778 82 1014
+rect 318 778 1482 1014
+rect 1718 778 2882 1014
+rect 3118 778 4282 1014
+rect 4518 778 5980 1014
+rect 0 736 5980 778
+use sky130_fd_sc_hd__fill_1  FILLER_0_9 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 828 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3  PHY_2 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 0 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_0
+timestamp 1638322937
+transform 1 0 0 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 276 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_6  FILLER_0_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 276 0 1 544
+box -38 -48 590 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[0\] $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 920 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_15
+timestamp 1638322937
+transform 1 0 1380 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[5\]
+timestamp 1638322937
+transform 1 0 2300 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[1\]
+timestamp 1638322937
+transform 1 0 1196 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[4\]
+timestamp 1638322937
+transform 1 0 2024 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[3\]
+timestamp 1638322937
+transform 1 0 1748 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[2\]
+timestamp 1638322937
+transform 1 0 1472 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_6 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 2576 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_38 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 3496 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_33
+timestamp 1638322937
+transform 1 0 3036 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__fill_1  FILLER_0_29
+timestamp 1638322937
+transform 1 0 2668 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_27
+timestamp 1638322937
+transform 1 0 2484 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[7\]
+timestamp 1638322937
+transform 1 0 3220 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[6\]
+timestamp 1638322937
+transform 1 0 2760 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_43
+timestamp 1638322937
+transform 1 0 3956 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4  FILLER_1_51 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 4692 0 -1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_0_48
+timestamp 1638322937
+transform 1 0 4416 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_39
+timestamp 1638322937
+transform 1 0 3588 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[9\]
+timestamp 1638322937
+transform 1 0 4140 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[8\]
+timestamp 1638322937
+transform 1 0 3680 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[12\]
+timestamp 1638322937
+transform 1 0 4508 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_8
+timestamp 1638322937
+transform 1 0 5152 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_7
+timestamp 1638322937
+transform 1 0 5152 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1  FILLER_1_55
+timestamp 1638322937
+transform 1 0 5060 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1  FILLER_0_55
+timestamp 1638322937
+transform 1 0 5060 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[10\]
+timestamp 1638322937
+transform 1 0 4784 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_60
+timestamp 1638322937
+transform 1 0 5520 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4  FILLER_1_57
+timestamp 1638322937
+transform 1 0 5244 0 -1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_1_61
+timestamp 1638322937
+transform 1 0 5612 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[11\]
+timestamp 1638322937
+transform 1 0 5244 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_3
+timestamp 1638322937
+transform -1 0 5980 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_1
+timestamp 1638322937
+transform -1 0 5980 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_4
+timestamp 1638322937
+transform 1 0 0 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_3
+timestamp 1638322937
+transform 1 0 276 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_15
+timestamp 1638322937
+transform 1 0 1380 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_9
+timestamp 1638322937
+transform 1 0 2576 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1  FILLER_2_27
+timestamp 1638322937
+transform 1 0 2484 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_29
+timestamp 1638322937
+transform 1 0 2668 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_41
+timestamp 1638322937
+transform 1 0 3772 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_10
+timestamp 1638322937
+transform 1 0 5152 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4  FILLER_2_57
+timestamp 1638322937
+transform 1 0 5244 0 1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_2_61
+timestamp 1638322937
+transform 1 0 5612 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3  PHY_5
+timestamp 1638322937
+transform -1 0 5980 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  FILLER_2_53
+timestamp 1638322937
+transform 1 0 4876 0 1 1632
+box -38 -48 314 592
+<< labels >>
+rlabel metal5 s 0 1436 5980 1756 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 760 496 1040 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 2160 496 2440 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 3560 496 3840 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 4960 496 5240 2224 6 VGND
+port 0 nsew ground input
+rlabel metal5 s 0 736 5980 1056 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 60 496 340 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 1460 496 1740 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 2860 496 3140 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 4260 496 4540 2224 6 VPWR
+port 1 nsew power input
+rlabel metal2 s 202 0 258 400 6 gpio_defaults[0]
+port 2 nsew signal tristate
+rlabel metal2 s 4802 0 4858 400 6 gpio_defaults[10]
+port 3 nsew signal tristate
+rlabel metal2 s 5262 0 5318 400 6 gpio_defaults[11]
+port 4 nsew signal tristate
+rlabel metal2 s 5722 0 5778 400 6 gpio_defaults[12]
+port 5 nsew signal tristate
+rlabel metal2 s 662 0 718 400 6 gpio_defaults[1]
+port 6 nsew signal tristate
+rlabel metal2 s 1122 0 1178 400 6 gpio_defaults[2]
+port 7 nsew signal tristate
+rlabel metal2 s 1582 0 1638 400 6 gpio_defaults[3]
+port 8 nsew signal tristate
+rlabel metal2 s 2042 0 2098 400 6 gpio_defaults[4]
+port 9 nsew signal tristate
+rlabel metal2 s 2502 0 2558 400 6 gpio_defaults[5]
+port 10 nsew signal tristate
+rlabel metal2 s 2962 0 3018 400 6 gpio_defaults[6]
+port 11 nsew signal tristate
+rlabel metal2 s 3422 0 3478 400 6 gpio_defaults[7]
+port 12 nsew signal tristate
+rlabel metal2 s 3882 0 3938 400 6 gpio_defaults[8]
+port 13 nsew signal tristate
+rlabel metal2 s 4342 0 4398 400 6 gpio_defaults[9]
+port 14 nsew signal tristate
+<< properties >>
+string FIXED_BBOX 0 0 6000 2200
+<< end >>
diff --git a/tapeout/outputs/mag/user_id_prog_zero.mag b/tapeout/outputs/mag/user_id_prog_zero.mag
new file mode 100644
index 0000000..6ad139c
--- /dev/null
+++ b/tapeout/outputs/mag/user_id_prog_zero.mag
@@ -0,0 +1,3074 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1650371074
+<< nwell >>
+rect 2304 2369 2397 2389
+<< viali >>
+rect 4353 5117 4387 5151
+rect 5273 5117 5307 5151
+rect 2145 4641 2179 4675
+rect 3249 4641 3283 4675
+rect 3617 4641 3651 4675
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+rect 1593 1853 1627 1887
+rect 2145 1853 2179 1887
+rect 2605 1853 2639 1887
+rect 2881 1853 2915 1887
+rect 3249 1853 3283 1887
+rect 4077 1853 4111 1887
+rect 5641 1853 5675 1887
+rect 1685 1377 1719 1411
+rect 2973 1377 3007 1411
+rect 4629 1377 4663 1411
+<< locali >>
+rect 4353 5117 4387 5151
+rect 5273 5117 5307 5151
+rect 2145 4641 2179 4675
+rect 3249 4641 3283 4675
+rect 3617 4641 3651 4675
+rect 4721 4641 4755 4675
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+rect 3249 1853 3283 1887
+rect 4077 1853 4111 1887
+rect 5641 1853 5675 1887
+rect 1685 1377 1719 1411
+rect 2973 1377 3007 1411
+rect 4629 1377 4663 1411
+<< metal1 >>
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+rect 1104 1040 5980 1062
+<< via1 >>
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+rect 4232 5958 4284 6010
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+<< metal4 >>
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+<< metal5 >>
+rect 1104 5238 5980 5280
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+rect 1104 1696 5980 1738
+use sky130_fd_sc_hd__fill_1  FILLER_0_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 1380 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_8  FILLER_0_7 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1648946573
+transform 1 0 1748 0 -1 1632
+box -38 -48 774 592
+use sky130_fd_sc_hd__decap_3  FILLER_0_15 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 2484 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_8  FILLER_0_21
+timestamp 1648946573
+transform 1 0 3036 0 -1 1632
+box -38 -48 774 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_29 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 3772 0 -1 1632
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4  FILLER_0_32 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 4048 0 -1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_8  FILLER_0_39
+timestamp 1648946573
+transform 1 0 4692 0 -1 1632
+box -38 -48 774 592
+use sky130_fd_sc_hd__decap_3  FILLER_0_47
+timestamp 1638025753
+transform 1 0 5428 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  FILLER_1_6
+timestamp 1638025753
+transform 1 0 1656 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2  FILLER_1_12
+timestamp 1638025753
+transform 1 0 2208 0 1 1632
+box -38 -48 222 592
+use sky130_fd_sc_hd__fill_1  FILLER_1_20
+timestamp 1638025753
+transform 1 0 2944 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_6  FILLER_1_24 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 3312 0 1 1632
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_33 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 4140 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__fill_2  FILLER_1_45
+timestamp 1638025753
+transform 1 0 5244 0 1 1632
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_3
+timestamp 1638025753
+transform 1 0 1380 0 -1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_15
+timestamp 1638025753
+transform 1 0 2484 0 -1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_4  FILLER_2_27
+timestamp 1638025753
+transform 1 0 3588 0 -1 2720
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_6  FILLER_2_32
+timestamp 1638025753
+transform 1 0 4048 0 -1 2720
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_6  FILLER_2_44
+timestamp 1638025753
+transform 1 0 5152 0 -1 2720
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_12  FILLER_3_6
+timestamp 1638025753
+transform 1 0 1656 0 1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_3_18
+timestamp 1638025753
+transform 1 0 2760 0 1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_3_30
+timestamp 1638025753
+transform 1 0 3864 0 1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_8  FILLER_3_42
+timestamp 1648946573
+transform 1 0 4968 0 1 2720
+box -38 -48 774 592
+use sky130_fd_sc_hd__fill_1  FILLER_4_3
+timestamp 1638025753
+transform 1 0 1380 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4  FILLER_4_10
+timestamp 1638025753
+transform 1 0 2024 0 -1 3808
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_4_14
+timestamp 1638025753
+transform 1 0 2392 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_2  FILLER_4_18
+timestamp 1638025753
+transform 1 0 2760 0 -1 3808
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4  FILLER_4_26
+timestamp 1638025753
+transform 1 0 3496 0 -1 3808
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_4_30
+timestamp 1638025753
+transform 1 0 3864 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3  FILLER_4_35
+timestamp 1638025753
+transform 1 0 4324 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2  FILLER_4_41
+timestamp 1638025753
+transform 1 0 4876 0 -1 3808
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4  FILLER_4_46
+timestamp 1638025753
+transform 1 0 5336 0 -1 3808
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_2  FILLER_5_6
+timestamp 1638025753
+transform 1 0 1656 0 1 3808
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_12  FILLER_5_11
+timestamp 1638025753
+transform 1 0 2116 0 1 3808
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_8  FILLER_5_23
+timestamp 1648946573
+transform 1 0 3220 0 1 3808
+box -38 -48 774 592
+use sky130_fd_sc_hd__decap_3  FILLER_5_31
+timestamp 1638025753
+transform 1 0 3956 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_6  FILLER_5_40
+timestamp 1638025753
+transform 1 0 4784 0 1 3808
+box -38 -48 590 592
+use sky130_fd_sc_hd__fill_1  FILLER_5_49
+timestamp 1638025753
+transform 1 0 5612 0 1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_6  FILLER_6_3
+timestamp 1638025753
+transform 1 0 1380 0 -1 4896
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_8  FILLER_6_12
+timestamp 1648946573
+transform 1 0 2208 0 -1 4896
+box -38 -48 774 592
+use sky130_fd_sc_hd__fill_1  FILLER_6_20
+timestamp 1638025753
+transform 1 0 2944 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1  FILLER_6_24
+timestamp 1638025753
+transform 1 0 3312 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3  FILLER_6_28
+timestamp 1638025753
+transform 1 0 3680 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_4  FILLER_6_32
+timestamp 1638025753
+transform 1 0 4048 0 -1 4896
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_6_36
+timestamp 1638025753
+transform 1 0 4416 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_8  FILLER_6_40
+timestamp 1648946573
+transform 1 0 4784 0 -1 4896
+box -38 -48 774 592
+use sky130_fd_sc_hd__fill_2  FILLER_6_48
+timestamp 1638025753
+transform 1 0 5520 0 -1 4896
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_12  FILLER_7_3
+timestamp 1638025753
+transform 1 0 1380 0 1 4896
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_7_15
+timestamp 1638025753
+transform 1 0 2484 0 1 4896
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_6  FILLER_7_27
+timestamp 1638025753
+transform 1 0 3588 0 1 4896
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_6  FILLER_7_36
+timestamp 1638025753
+transform 1 0 4416 0 1 4896
+box -38 -48 590 592
+use sky130_fd_sc_hd__fill_1  FILLER_7_42
+timestamp 1638025753
+transform 1 0 4968 0 1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4  FILLER_7_46
+timestamp 1638025753
+transform 1 0 5336 0 1 4896
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_12  FILLER_8_3
+timestamp 1638025753
+transform 1 0 1380 0 -1 5984
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_8_15
+timestamp 1638025753
+transform 1 0 2484 0 -1 5984
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_4  FILLER_8_27
+timestamp 1638025753
+transform 1 0 3588 0 -1 5984
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_12  FILLER_8_32
+timestamp 1638025753
+transform 1 0 4048 0 -1 5984
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_6  FILLER_8_44
+timestamp 1638025753
+transform 1 0 5152 0 -1 5984
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_3  PHY_0
+timestamp 1638025753
+transform 1 0 1104 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_1
+timestamp 1638025753
+transform -1 0 5980 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_2
+timestamp 1638025753
+transform 1 0 1104 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_3
+timestamp 1638025753
+transform -1 0 5980 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_4
+timestamp 1638025753
+transform 1 0 1104 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_5
+timestamp 1638025753
+transform -1 0 5980 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_6
+timestamp 1638025753
+transform 1 0 1104 0 1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_7
+timestamp 1638025753
+transform -1 0 5980 0 1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_8
+timestamp 1638025753
+transform 1 0 1104 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_9
+timestamp 1638025753
+transform -1 0 5980 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_10
+timestamp 1638025753
+transform 1 0 1104 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_11
+timestamp 1638025753
+transform -1 0 5980 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_12
+timestamp 1638025753
+transform 1 0 1104 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_13
+timestamp 1638025753
+transform -1 0 5980 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_14
+timestamp 1638025753
+transform 1 0 1104 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_15
+timestamp 1638025753
+transform -1 0 5980 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_16
+timestamp 1638025753
+transform 1 0 1104 0 -1 5984
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_17
+timestamp 1638025753
+transform -1 0 5980 0 -1 5984
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  PHY_18 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 3956 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  PHY_19
+timestamp 1638025753
+transform 1 0 3956 0 -1 2720
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  PHY_20
+timestamp 1638025753
+transform 1 0 3956 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  PHY_21
+timestamp 1638025753
+transform 1 0 3956 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  PHY_22
+timestamp 1638025753
+transform 1 0 3956 0 -1 5984
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[0\] $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1648946573
+transform 1 0 2392 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[1\]
+timestamp 1648946573
+transform 1 0 3036 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[2\]
+timestamp 1648946573
+transform 1 0 1840 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[3\]
+timestamp 1648946573
+transform 1 0 1380 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[4\]
+timestamp 1648946573
+transform 1 0 5428 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[5\]
+timestamp 1648946573
+transform 1 0 4140 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[6\]
+timestamp 1648946573
+transform 1 0 1380 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[7\]
+timestamp 1648946573
+transform 1 0 3864 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[8\]
+timestamp 1648946573
+transform 1 0 3220 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[9\]
+timestamp 1648946573
+transform 1 0 4876 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[10\]
+timestamp 1648946573
+transform 1 0 4232 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[11\]
+timestamp 1648946573
+transform 1 0 2668 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[12\]
+timestamp 1648946573
+transform 1 0 4508 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[13\]
+timestamp 1648946573
+transform 1 0 4600 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[14\]
+timestamp 1648946573
+transform 1 0 2484 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[15\]
+timestamp 1648946573
+transform 1 0 4416 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[16\]
+timestamp 1648946573
+transform 1 0 4600 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[17\]
+timestamp 1648946573
+transform 1 0 1472 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[18\]
+timestamp 1648946573
+transform 1 0 4508 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[19\]
+timestamp 1648946573
+transform 1 0 1932 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[20\]
+timestamp 1648946573
+transform 1 0 2760 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[21\]
+timestamp 1648946573
+transform 1 0 3404 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[22\]
+timestamp 1648946573
+transform 1 0 4048 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[23\]
+timestamp 1648946573
+transform 1 0 5060 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[24\]
+timestamp 1648946573
+transform 1 0 1748 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[25\]
+timestamp 1648946573
+transform 1 0 2944 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[26\]
+timestamp 1648946573
+transform 1 0 5060 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[27\]
+timestamp 1648946573
+transform 1 0 1472 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[28\]
+timestamp 1648946573
+transform 1 0 1932 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[29\]
+timestamp 1648946573
+transform 1 0 5336 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[30\]
+timestamp 1648946573
+transform 1 0 3036 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[31\]
+timestamp 1648946573
+transform 1 0 1380 0 1 2720
+box -38 -48 314 592
+<< labels >>
+rlabel metal2 s 4066 6277 4122 7077 4 mask_rev[0]
+port 1 nsew
+rlabel metal2 s 4066 0 4122 800 4 mask_rev[10]
+port 2 nsew
+rlabel metal2 s 1122 0 1178 800 4 mask_rev[11]
+port 3 nsew
+rlabel metal2 s 570 0 626 800 4 mask_rev[12]
+port 4 nsew
+rlabel metal2 s 5354 6277 5410 7077 4 mask_rev[13]
+port 5 nsew
+rlabel metal2 s 5906 0 5962 800 4 mask_rev[14]
+port 6 nsew
+rlabel metal3 s 6309 1640 7109 1760 4 mask_rev[15]
+port 7 nsew
+rlabel metal2 s 2226 0 2282 800 4 mask_rev[16]
+port 8 nsew
+rlabel metal2 s 1674 6277 1730 7077 4 mask_rev[17]
+port 9 nsew
+rlabel metal3 s 0 5176 800 5296 4 mask_rev[18]
+port 10 nsew
+rlabel metal2 s 2962 6277 3018 7077 4 mask_rev[19]
+port 11 nsew
+rlabel metal3 s 0 3272 800 3392 4 mask_rev[1]
+port 12 nsew
+rlabel metal3 s 6309 2456 7109 2576 4 mask_rev[20]
+port 13 nsew
+rlabel metal3 s 6309 824 7109 944 4 mask_rev[21]
+port 14 nsew
+rlabel metal3 s 0 5992 800 6112 4 mask_rev[22]
+port 15 nsew
+rlabel metal2 s 1674 0 1730 800 4 mask_rev[23]
+port 16 nsew
+rlabel metal2 s 5906 6277 5962 7077 4 mask_rev[24]
+port 17 nsew
+rlabel metal3 s 0 1640 800 1760 4 mask_rev[25]
+port 18 nsew
+rlabel metal2 s 4802 6277 4858 7077 4 mask_rev[26]
+port 19 nsew
+rlabel metal2 s 1122 6277 1178 7077 4 mask_rev[27]
+port 20 nsew
+rlabel metal2 s 6458 6277 6514 7077 4 mask_rev[28]
+port 21 nsew
+rlabel metal2 s 5354 0 5410 800 4 mask_rev[29]
+port 22 nsew
+rlabel metal3 s 0 2456 800 2576 4 mask_rev[2]
+port 23 nsew
+rlabel metal3 s 6309 5176 7109 5296 4 mask_rev[30]
+port 24 nsew
+rlabel metal2 s 2962 0 3018 800 4 mask_rev[31]
+port 25 nsew
+rlabel metal2 s 3514 0 3570 800 4 mask_rev[3]
+port 26 nsew
+rlabel metal3 s 6309 3544 7109 3664 4 mask_rev[4]
+port 27 nsew
+rlabel metal3 s 6309 4360 7109 4480 4 mask_rev[5]
+port 28 nsew
+rlabel metal3 s 0 4360 800 4480 4 mask_rev[6]
+port 29 nsew
+rlabel metal2 s 3514 6277 3570 7077 4 mask_rev[7]
+port 30 nsew
+rlabel metal2 s 4802 0 4858 800 4 mask_rev[8]
+port 31 nsew
+rlabel metal2 s 2226 6277 2282 7077 4 mask_rev[9]
+port 32 nsew
+rlabel metal5 s 1104 1696 5980 2016 4 VPWR
+port 33 nsew
+rlabel metal5 s 1104 2512 5980 2832 4 VGND
+port 34 nsew
+<< properties >>
+string FIXED_BBOX 0 0 7109 7077
+<< end >>
diff --git a/tapeout/outputs/mag/user_id_programming.mag b/tapeout/outputs/mag/user_id_programming.mag
new file mode 100644
index 0000000..ac76a7b
--- /dev/null
+++ b/tapeout/outputs/mag/user_id_programming.mag
@@ -0,0 +1,3074 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1650371074
+<< nwell >>
+rect 2304 2369 2397 2389
+<< viali >>
+rect 4353 5117 4387 5151
+rect 5089 5117 5123 5151
+rect 2145 4641 2179 4675
+rect 3065 4641 3099 4675
+rect 3617 4641 3651 4675
+rect 4537 4641 4571 4675
+rect 1593 4029 1627 4063
+rect 2053 4029 2087 4063
+rect 4445 4029 4479 4063
+rect 4721 4029 4755 4063
+rect 5549 4029 5583 4063
+rect 1685 3553 1719 3587
+rect 1777 3553 1811 3587
+rect 2697 3553 2731 3587
+rect 2973 3553 3007 3587
+rect 3433 3553 3467 3587
+rect 4077 3553 4111 3587
+rect 4629 3553 4663 3587
+rect 5273 3553 5307 3587
+rect 1593 2941 1627 2975
+rect 4813 2397 4847 2431
+rect 5089 2397 5123 2431
+rect 1593 1853 1627 1887
+rect 1961 1853 1995 1887
+rect 2605 1853 2639 1887
+rect 2881 1853 2915 1887
+rect 3249 1853 3283 1887
+rect 4077 1853 4111 1887
+rect 5641 1853 5675 1887
+rect 1685 1377 1719 1411
+rect 2789 1377 2823 1411
+rect 4629 1377 4663 1411
+<< locali >>
+rect 4353 5117 4387 5151
+rect 5089 5117 5123 5151
+rect 2145 4641 2179 4675
+rect 3065 4641 3099 4675
+rect 3617 4641 3651 4675
+rect 4537 4641 4571 4675
+rect 1593 4029 1627 4063
+rect 2053 4029 2087 4063
+rect 4445 4029 4479 4063
+rect 4721 4029 4755 4063
+rect 5549 4029 5583 4063
+rect 1685 3553 1719 3587
+rect 1777 3553 1811 3587
+rect 2697 3553 2731 3587
+rect 2973 3553 3007 3587
+rect 3433 3553 3467 3587
+rect 4077 3553 4111 3587
+rect 4629 3553 4663 3587
+rect 5273 3553 5307 3587
+rect 1593 2941 1627 2975
+rect 4813 2397 4847 2431
+rect 5089 2397 5123 2431
+rect 1593 1853 1627 1887
+rect 1961 1853 1995 1887
+rect 2605 1853 2639 1887
+rect 2881 1853 2915 1887
+rect 3249 1853 3283 1887
+rect 4077 1853 4111 1887
+rect 5641 1853 5675 1887
+rect 1685 1377 1719 1411
+rect 2789 1377 2823 1411
+rect 4629 1377 4663 1411
+<< metal1 >>
+rect 1104 6010 5980 6032
+rect 1104 5958 2607 6010
+rect 2659 5958 2671 6010
+rect 2723 5958 2735 6010
+rect 2787 5958 2799 6010
+rect 2851 5958 4232 6010
+rect 4284 5958 4296 6010
+rect 4348 5958 4360 6010
+rect 4412 5958 4424 6010
+rect 4476 5958 5980 6010
+rect 1104 5936 5980 5958
+rect 1104 5466 5980 5488
+rect 1104 5414 1794 5466
+rect 1846 5414 1858 5466
+rect 1910 5414 1922 5466
+rect 1974 5414 1986 5466
+rect 2038 5414 3420 5466
+rect 3472 5414 3484 5466
+rect 3536 5414 3548 5466
+rect 3600 5414 3612 5466
+rect 3664 5414 5045 5466
+rect 5097 5414 5109 5466
+rect 5161 5414 5173 5466
+rect 5225 5414 5237 5466
+rect 5289 5414 5980 5466
+rect 1104 5392 5980 5414
+rect 4062 5108 4068 5160
+rect 4120 5148 4126 5160
+rect 4157 5148 4215 5157
+rect 4341 5148 4399 5157
+rect 4120 5120 4399 5148
+rect 4120 5108 4126 5120
+rect 4157 5111 4215 5120
+rect 4341 5111 4399 5120
+rect 4614 5108 4620 5160
+rect 4672 5148 4678 5160
+rect 5077 5148 5135 5157
+rect 5261 5148 5319 5157
+rect 4672 5120 5319 5148
+rect 4672 5108 4678 5120
+rect 5077 5111 5135 5120
+rect 5261 5111 5319 5120
+rect 1104 4922 5980 4944
+rect 1104 4870 2607 4922
+rect 2659 4870 2671 4922
+rect 2723 4870 2735 4922
+rect 2787 4870 2799 4922
+rect 2851 4870 4232 4922
+rect 4284 4870 4296 4922
+rect 4348 4870 4360 4922
+rect 4412 4870 4424 4922
+rect 4476 4870 5980 4922
+rect 1104 4848 5980 4870
+rect 1949 4672 2007 4681
+rect 2133 4672 2191 4681
+rect 2958 4672 2964 4684
+rect 1949 4644 2964 4672
+rect 1949 4635 2007 4644
+rect 2133 4635 2191 4644
+rect 2958 4632 2964 4644
+rect 3016 4632 3022 4684
+rect 3050 4672 3114 4684
+rect 3234 4672 3240 4684
+rect 3050 4644 3240 4672
+rect 3050 4632 3114 4644
+rect 3234 4632 3240 4644
+rect 3292 4632 3298 4684
+rect 3418 4672 3482 4684
+rect 3602 4672 3666 4684
+rect 3418 4644 3666 4672
+rect 3418 4632 3482 4644
+rect 3602 4632 3666 4644
+rect 4522 4674 4586 4684
+rect 4706 4674 4770 4684
+rect 4522 4644 4770 4674
+rect 4522 4632 4586 4644
+rect 4706 4632 4770 4644
+rect 3620 4468 3648 4632
+rect 4720 4539 4755 4632
+rect 4720 4505 4754 4539
+rect 4720 4480 4755 4505
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+rect 1764 1060 1768 1116
+rect 1768 1060 1824 1116
+rect 1824 1060 1828 1116
+rect 1764 1056 1828 1060
+rect 1844 1116 1908 1120
+rect 1844 1060 1848 1116
+rect 1848 1060 1904 1116
+rect 1904 1060 1908 1116
+rect 1844 1056 1908 1060
+rect 1924 1116 1988 1120
+rect 1924 1060 1928 1116
+rect 1928 1060 1984 1116
+rect 1984 1060 1988 1116
+rect 1924 1056 1988 1060
+rect 2004 1116 2068 1120
+rect 2004 1060 2008 1116
+rect 2008 1060 2064 1116
+rect 2064 1060 2068 1116
+rect 2004 1056 2068 1060
+rect 3390 1116 3454 1120
+rect 3390 1060 3394 1116
+rect 3394 1060 3450 1116
+rect 3450 1060 3454 1116
+rect 3390 1056 3454 1060
+rect 3470 1116 3534 1120
+rect 3470 1060 3474 1116
+rect 3474 1060 3530 1116
+rect 3530 1060 3534 1116
+rect 3470 1056 3534 1060
+rect 3550 1116 3614 1120
+rect 3550 1060 3554 1116
+rect 3554 1060 3610 1116
+rect 3610 1060 3614 1116
+rect 3550 1056 3614 1060
+rect 3630 1116 3694 1120
+rect 3630 1060 3634 1116
+rect 3634 1060 3690 1116
+rect 3690 1060 3694 1116
+rect 3630 1056 3694 1060
+rect 5015 1116 5079 1120
+rect 5015 1060 5019 1116
+rect 5019 1060 5075 1116
+rect 5075 1060 5079 1116
+rect 5015 1056 5079 1060
+rect 5095 1116 5159 1120
+rect 5095 1060 5099 1116
+rect 5099 1060 5155 1116
+rect 5155 1060 5159 1116
+rect 5095 1056 5159 1060
+rect 5175 1116 5239 1120
+rect 5175 1060 5179 1116
+rect 5179 1060 5235 1116
+rect 5235 1060 5239 1116
+rect 5175 1056 5239 1060
+rect 5255 1116 5319 1120
+rect 5255 1060 5259 1116
+rect 5259 1060 5315 1116
+rect 5315 1060 5319 1116
+rect 5255 1056 5319 1060
+<< metal4 >>
+rect 1756 5472 2076 6032
+rect 1756 5408 1764 5472
+rect 1828 5408 1844 5472
+rect 1908 5408 1924 5472
+rect 1988 5408 2004 5472
+rect 2068 5408 2076 5472
+rect 1756 5238 2076 5408
+rect 1756 5002 1798 5238
+rect 2034 5002 2076 5238
+rect 1756 4384 2076 5002
+rect 1756 4320 1764 4384
+rect 1828 4320 1844 4384
+rect 1908 4320 1924 4384
+rect 1988 4320 2004 4384
+rect 2068 4320 2076 4384
+rect 1756 3606 2076 4320
+rect 1756 3370 1798 3606
+rect 2034 3370 2076 3606
+rect 1756 3296 2076 3370
+rect 1756 3232 1764 3296
+rect 1828 3232 1844 3296
+rect 1908 3232 1924 3296
+rect 1988 3232 2004 3296
+rect 2068 3232 2076 3296
+rect 1756 2208 2076 3232
+rect 1756 2144 1764 2208
+rect 1828 2144 1844 2208
+rect 1908 2144 1924 2208
+rect 1988 2144 2004 2208
+rect 2068 2144 2076 2208
+rect 1756 1974 2076 2144
+rect 1756 1738 1798 1974
+rect 2034 1738 2076 1974
+rect 1756 1120 2076 1738
+rect 1756 1056 1764 1120
+rect 1828 1056 1844 1120
+rect 1908 1056 1924 1120
+rect 1988 1056 2004 1120
+rect 2068 1056 2076 1120
+rect 1756 1040 2076 1056
+rect 2569 6016 2889 6032
+rect 2569 5952 2577 6016
+rect 2641 5952 2657 6016
+rect 2721 5952 2737 6016
+rect 2801 5952 2817 6016
+rect 2881 5952 2889 6016
+rect 2569 4928 2889 5952
+rect 2569 4864 2577 4928
+rect 2641 4864 2657 4928
+rect 2721 4864 2737 4928
+rect 2801 4864 2817 4928
+rect 2881 4864 2889 4928
+rect 2569 4422 2889 4864
+rect 2569 4186 2611 4422
+rect 2847 4186 2889 4422
+rect 2569 3840 2889 4186
+rect 2569 3776 2577 3840
+rect 2641 3776 2657 3840
+rect 2721 3776 2737 3840
+rect 2801 3776 2817 3840
+rect 2881 3776 2889 3840
+rect 2569 2790 2889 3776
+rect 2569 2752 2611 2790
+rect 2847 2752 2889 2790
+rect 2569 2688 2577 2752
+rect 2881 2688 2889 2752
+rect 2569 2554 2611 2688
+rect 2847 2554 2889 2688
+rect 2569 1664 2889 2554
+rect 2569 1600 2577 1664
+rect 2641 1600 2657 1664
+rect 2721 1600 2737 1664
+rect 2801 1600 2817 1664
+rect 2881 1600 2889 1664
+rect 2569 1040 2889 1600
+rect 3382 5472 3702 6032
+rect 3382 5408 3390 5472
+rect 3454 5408 3470 5472
+rect 3534 5408 3550 5472
+rect 3614 5408 3630 5472
+rect 3694 5408 3702 5472
+rect 3382 5238 3702 5408
+rect 3382 5002 3424 5238
+rect 3660 5002 3702 5238
+rect 3382 4384 3702 5002
+rect 3382 4320 3390 4384
+rect 3454 4320 3470 4384
+rect 3534 4320 3550 4384
+rect 3614 4320 3630 4384
+rect 3694 4320 3702 4384
+rect 3382 3606 3702 4320
+rect 3382 3370 3424 3606
+rect 3660 3370 3702 3606
+rect 3382 3296 3702 3370
+rect 3382 3232 3390 3296
+rect 3454 3232 3470 3296
+rect 3534 3232 3550 3296
+rect 3614 3232 3630 3296
+rect 3694 3232 3702 3296
+rect 3382 2208 3702 3232
+rect 3382 2144 3390 2208
+rect 3454 2144 3470 2208
+rect 3534 2144 3550 2208
+rect 3614 2144 3630 2208
+rect 3694 2144 3702 2208
+rect 3382 1974 3702 2144
+rect 3382 1738 3424 1974
+rect 3660 1738 3702 1974
+rect 3382 1120 3702 1738
+rect 3382 1056 3390 1120
+rect 3454 1056 3470 1120
+rect 3534 1056 3550 1120
+rect 3614 1056 3630 1120
+rect 3694 1056 3702 1120
+rect 3382 1040 3702 1056
+rect 4194 6016 4514 6032
+rect 4194 5952 4202 6016
+rect 4266 5952 4282 6016
+rect 4346 5952 4362 6016
+rect 4426 5952 4442 6016
+rect 4506 5952 4514 6016
+rect 4194 4928 4514 5952
+rect 4194 4864 4202 4928
+rect 4266 4864 4282 4928
+rect 4346 4864 4362 4928
+rect 4426 4864 4442 4928
+rect 4506 4864 4514 4928
+rect 4194 4422 4514 4864
+rect 4194 4186 4236 4422
+rect 4472 4186 4514 4422
+rect 4194 3840 4514 4186
+rect 4194 3776 4202 3840
+rect 4266 3776 4282 3840
+rect 4346 3776 4362 3840
+rect 4426 3776 4442 3840
+rect 4506 3776 4514 3840
+rect 4194 2790 4514 3776
+rect 4194 2752 4236 2790
+rect 4472 2752 4514 2790
+rect 4194 2688 4202 2752
+rect 4506 2688 4514 2752
+rect 4194 2554 4236 2688
+rect 4472 2554 4514 2688
+rect 4194 1664 4514 2554
+rect 4194 1600 4202 1664
+rect 4266 1600 4282 1664
+rect 4346 1600 4362 1664
+rect 4426 1600 4442 1664
+rect 4506 1600 4514 1664
+rect 4194 1040 4514 1600
+rect 5007 5472 5327 6032
+rect 5007 5408 5015 5472
+rect 5079 5408 5095 5472
+rect 5159 5408 5175 5472
+rect 5239 5408 5255 5472
+rect 5319 5408 5327 5472
+rect 5007 5238 5327 5408
+rect 5007 5002 5049 5238
+rect 5285 5002 5327 5238
+rect 5007 4384 5327 5002
+rect 5007 4320 5015 4384
+rect 5079 4320 5095 4384
+rect 5159 4320 5175 4384
+rect 5239 4320 5255 4384
+rect 5319 4320 5327 4384
+rect 5007 3606 5327 4320
+rect 5007 3370 5049 3606
+rect 5285 3370 5327 3606
+rect 5007 3296 5327 3370
+rect 5007 3232 5015 3296
+rect 5079 3232 5095 3296
+rect 5159 3232 5175 3296
+rect 5239 3232 5255 3296
+rect 5319 3232 5327 3296
+rect 5007 2208 5327 3232
+rect 5007 2144 5015 2208
+rect 5079 2144 5095 2208
+rect 5159 2144 5175 2208
+rect 5239 2144 5255 2208
+rect 5319 2144 5327 2208
+rect 5007 1974 5327 2144
+rect 5007 1738 5049 1974
+rect 5285 1738 5327 1974
+rect 5007 1120 5327 1738
+rect 5007 1056 5015 1120
+rect 5079 1056 5095 1120
+rect 5159 1056 5175 1120
+rect 5239 1056 5255 1120
+rect 5319 1056 5327 1120
+rect 5007 1040 5327 1056
+<< via4 >>
+rect 1798 5002 2034 5238
+rect 1798 3370 2034 3606
+rect 1798 1738 2034 1974
+rect 2611 4186 2847 4422
+rect 2611 2752 2847 2790
+rect 2611 2688 2641 2752
+rect 2641 2688 2657 2752
+rect 2657 2688 2721 2752
+rect 2721 2688 2737 2752
+rect 2737 2688 2801 2752
+rect 2801 2688 2817 2752
+rect 2817 2688 2847 2752
+rect 2611 2554 2847 2688
+rect 3424 5002 3660 5238
+rect 3424 3370 3660 3606
+rect 3424 1738 3660 1974
+rect 4236 4186 4472 4422
+rect 4236 2752 4472 2790
+rect 4236 2688 4266 2752
+rect 4266 2688 4282 2752
+rect 4282 2688 4346 2752
+rect 4346 2688 4362 2752
+rect 4362 2688 4426 2752
+rect 4426 2688 4442 2752
+rect 4442 2688 4472 2752
+rect 4236 2554 4472 2688
+rect 5049 5002 5285 5238
+rect 5049 3370 5285 3606
+rect 5049 1738 5285 1974
+<< metal5 >>
+rect 1104 5238 5980 5280
+rect 1104 5002 1798 5238
+rect 2034 5002 3424 5238
+rect 3660 5002 5049 5238
+rect 5285 5002 5980 5238
+rect 1104 4960 5980 5002
+rect 1104 4422 5980 4464
+rect 1104 4186 2611 4422
+rect 2847 4186 4236 4422
+rect 4472 4186 5980 4422
+rect 1104 4144 5980 4186
+rect 1104 3606 5980 3648
+rect 1104 3370 1798 3606
+rect 2034 3370 3424 3606
+rect 3660 3370 5049 3606
+rect 5285 3370 5980 3606
+rect 1104 3328 5980 3370
+rect 1104 2790 5980 2832
+rect 1104 2554 2611 2790
+rect 2847 2554 4236 2790
+rect 4472 2554 5980 2790
+rect 1104 2512 5980 2554
+rect 1104 1974 5980 2016
+rect 1104 1738 1798 1974
+rect 2034 1738 3424 1974
+rect 3660 1738 5049 1974
+rect 5285 1738 5980 1974
+rect 1104 1696 5980 1738
+use sky130_fd_sc_hd__fill_1  FILLER_0_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 1380 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_8  FILLER_0_7 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1648946573
+transform 1 0 1748 0 -1 1632
+box -38 -48 774 592
+use sky130_fd_sc_hd__decap_3  FILLER_0_15 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 2484 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_8  FILLER_0_21
+timestamp 1648946573
+transform 1 0 3036 0 -1 1632
+box -38 -48 774 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_29 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 3772 0 -1 1632
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4  FILLER_0_32 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 4048 0 -1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_8  FILLER_0_39
+timestamp 1648946573
+transform 1 0 4692 0 -1 1632
+box -38 -48 774 592
+use sky130_fd_sc_hd__decap_3  FILLER_0_47
+timestamp 1638025753
+transform 1 0 5428 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  FILLER_1_6
+timestamp 1638025753
+transform 1 0 1656 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2  FILLER_1_12
+timestamp 1638025753
+transform 1 0 2208 0 1 1632
+box -38 -48 222 592
+use sky130_fd_sc_hd__fill_1  FILLER_1_20
+timestamp 1638025753
+transform 1 0 2944 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_6  FILLER_1_24 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 3312 0 1 1632
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_33 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 4140 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__fill_2  FILLER_1_45
+timestamp 1638025753
+transform 1 0 5244 0 1 1632
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_3
+timestamp 1638025753
+transform 1 0 1380 0 -1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_15
+timestamp 1638025753
+transform 1 0 2484 0 -1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_4  FILLER_2_27
+timestamp 1638025753
+transform 1 0 3588 0 -1 2720
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_6  FILLER_2_32
+timestamp 1638025753
+transform 1 0 4048 0 -1 2720
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_6  FILLER_2_44
+timestamp 1638025753
+transform 1 0 5152 0 -1 2720
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_12  FILLER_3_6
+timestamp 1638025753
+transform 1 0 1656 0 1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_3_18
+timestamp 1638025753
+transform 1 0 2760 0 1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_3_30
+timestamp 1638025753
+transform 1 0 3864 0 1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_8  FILLER_3_42
+timestamp 1648946573
+transform 1 0 4968 0 1 2720
+box -38 -48 774 592
+use sky130_fd_sc_hd__fill_1  FILLER_4_3
+timestamp 1638025753
+transform 1 0 1380 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4  FILLER_4_10
+timestamp 1638025753
+transform 1 0 2024 0 -1 3808
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_4_14
+timestamp 1638025753
+transform 1 0 2392 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_2  FILLER_4_18
+timestamp 1638025753
+transform 1 0 2760 0 -1 3808
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4  FILLER_4_26
+timestamp 1638025753
+transform 1 0 3496 0 -1 3808
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_4_30
+timestamp 1638025753
+transform 1 0 3864 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3  FILLER_4_35
+timestamp 1638025753
+transform 1 0 4324 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2  FILLER_4_41
+timestamp 1638025753
+transform 1 0 4876 0 -1 3808
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4  FILLER_4_46
+timestamp 1638025753
+transform 1 0 5336 0 -1 3808
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_2  FILLER_5_6
+timestamp 1638025753
+transform 1 0 1656 0 1 3808
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_12  FILLER_5_11
+timestamp 1638025753
+transform 1 0 2116 0 1 3808
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_8  FILLER_5_23
+timestamp 1648946573
+transform 1 0 3220 0 1 3808
+box -38 -48 774 592
+use sky130_fd_sc_hd__decap_3  FILLER_5_31
+timestamp 1638025753
+transform 1 0 3956 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_6  FILLER_5_40
+timestamp 1638025753
+transform 1 0 4784 0 1 3808
+box -38 -48 590 592
+use sky130_fd_sc_hd__fill_1  FILLER_5_49
+timestamp 1638025753
+transform 1 0 5612 0 1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_6  FILLER_6_3
+timestamp 1638025753
+transform 1 0 1380 0 -1 4896
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_8  FILLER_6_12
+timestamp 1648946573
+transform 1 0 2208 0 -1 4896
+box -38 -48 774 592
+use sky130_fd_sc_hd__fill_1  FILLER_6_20
+timestamp 1638025753
+transform 1 0 2944 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1  FILLER_6_24
+timestamp 1638025753
+transform 1 0 3312 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3  FILLER_6_28
+timestamp 1638025753
+transform 1 0 3680 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_4  FILLER_6_32
+timestamp 1638025753
+transform 1 0 4048 0 -1 4896
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_6_36
+timestamp 1638025753
+transform 1 0 4416 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_8  FILLER_6_40
+timestamp 1648946573
+transform 1 0 4784 0 -1 4896
+box -38 -48 774 592
+use sky130_fd_sc_hd__fill_2  FILLER_6_48
+timestamp 1638025753
+transform 1 0 5520 0 -1 4896
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_12  FILLER_7_3
+timestamp 1638025753
+transform 1 0 1380 0 1 4896
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_7_15
+timestamp 1638025753
+transform 1 0 2484 0 1 4896
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_6  FILLER_7_27
+timestamp 1638025753
+transform 1 0 3588 0 1 4896
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_6  FILLER_7_36
+timestamp 1638025753
+transform 1 0 4416 0 1 4896
+box -38 -48 590 592
+use sky130_fd_sc_hd__fill_1  FILLER_7_42
+timestamp 1638025753
+transform 1 0 4968 0 1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4  FILLER_7_46
+timestamp 1638025753
+transform 1 0 5336 0 1 4896
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_12  FILLER_8_3
+timestamp 1638025753
+transform 1 0 1380 0 -1 5984
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_8_15
+timestamp 1638025753
+transform 1 0 2484 0 -1 5984
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_4  FILLER_8_27
+timestamp 1638025753
+transform 1 0 3588 0 -1 5984
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_12  FILLER_8_32
+timestamp 1638025753
+transform 1 0 4048 0 -1 5984
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_6  FILLER_8_44
+timestamp 1638025753
+transform 1 0 5152 0 -1 5984
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_3  PHY_0
+timestamp 1638025753
+transform 1 0 1104 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_1
+timestamp 1638025753
+transform -1 0 5980 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_2
+timestamp 1638025753
+transform 1 0 1104 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_3
+timestamp 1638025753
+transform -1 0 5980 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_4
+timestamp 1638025753
+transform 1 0 1104 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_5
+timestamp 1638025753
+transform -1 0 5980 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_6
+timestamp 1638025753
+transform 1 0 1104 0 1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_7
+timestamp 1638025753
+transform -1 0 5980 0 1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_8
+timestamp 1638025753
+transform 1 0 1104 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_9
+timestamp 1638025753
+transform -1 0 5980 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_10
+timestamp 1638025753
+transform 1 0 1104 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_11
+timestamp 1638025753
+transform -1 0 5980 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_12
+timestamp 1638025753
+transform 1 0 1104 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_13
+timestamp 1638025753
+transform -1 0 5980 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_14
+timestamp 1638025753
+transform 1 0 1104 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_15
+timestamp 1638025753
+transform -1 0 5980 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_16
+timestamp 1638025753
+transform 1 0 1104 0 -1 5984
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_17
+timestamp 1638025753
+transform -1 0 5980 0 -1 5984
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  PHY_18 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 3956 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  PHY_19
+timestamp 1638025753
+transform 1 0 3956 0 -1 2720
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  PHY_20
+timestamp 1638025753
+transform 1 0 3956 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  PHY_21
+timestamp 1638025753
+transform 1 0 3956 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  PHY_22
+timestamp 1638025753
+transform 1 0 3956 0 -1 5984
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[0\] $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1648946573
+transform 1 0 2392 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[1\]
+timestamp 1648946573
+transform 1 0 3036 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[2\]
+timestamp 1648946573
+transform 1 0 1840 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[3\]
+timestamp 1648946573
+transform 1 0 1380 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[4\]
+timestamp 1648946573
+transform 1 0 5428 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[5\]
+timestamp 1648946573
+transform 1 0 4140 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[6\]
+timestamp 1648946573
+transform 1 0 1380 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[7\]
+timestamp 1648946573
+transform 1 0 3864 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[8\]
+timestamp 1648946573
+transform 1 0 3220 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[9\]
+timestamp 1648946573
+transform 1 0 4876 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[10\]
+timestamp 1648946573
+transform 1 0 4232 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[11\]
+timestamp 1648946573
+transform 1 0 2668 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[12\]
+timestamp 1648946573
+transform 1 0 4508 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[13\]
+timestamp 1648946573
+transform 1 0 4600 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[14\]
+timestamp 1648946573
+transform 1 0 2484 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[15\]
+timestamp 1648946573
+transform 1 0 4416 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[16\]
+timestamp 1648946573
+transform 1 0 4600 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[17\]
+timestamp 1648946573
+transform 1 0 1472 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[18\]
+timestamp 1648946573
+transform 1 0 4508 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[19\]
+timestamp 1648946573
+transform 1 0 1932 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[20\]
+timestamp 1648946573
+transform 1 0 2760 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[21\]
+timestamp 1648946573
+transform 1 0 3404 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[22\]
+timestamp 1648946573
+transform 1 0 4048 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[23\]
+timestamp 1648946573
+transform 1 0 5060 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[24\]
+timestamp 1648946573
+transform 1 0 1748 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[25\]
+timestamp 1648946573
+transform 1 0 2944 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[26\]
+timestamp 1648946573
+transform 1 0 5060 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[27\]
+timestamp 1648946573
+transform 1 0 1472 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[28\]
+timestamp 1648946573
+transform 1 0 1932 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[29\]
+timestamp 1648946573
+transform 1 0 5336 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[30\]
+timestamp 1648946573
+transform 1 0 3036 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[31\]
+timestamp 1648946573
+transform 1 0 1380 0 1 2720
+box -38 -48 314 592
+<< labels >>
+rlabel metal2 s 4066 6277 4122 7077 4 mask_rev[0]
+port 1 nsew
+rlabel metal2 s 4066 0 4122 800 4 mask_rev[10]
+port 2 nsew
+rlabel metal2 s 1122 0 1178 800 4 mask_rev[11]
+port 3 nsew
+rlabel metal2 s 570 0 626 800 4 mask_rev[12]
+port 4 nsew
+rlabel metal2 s 5354 6277 5410 7077 4 mask_rev[13]
+port 5 nsew
+rlabel metal2 s 5906 0 5962 800 4 mask_rev[14]
+port 6 nsew
+rlabel metal3 s 6309 1640 7109 1760 4 mask_rev[15]
+port 7 nsew
+rlabel metal2 s 2226 0 2282 800 4 mask_rev[16]
+port 8 nsew
+rlabel metal2 s 1674 6277 1730 7077 4 mask_rev[17]
+port 9 nsew
+rlabel metal3 s 0 5176 800 5296 4 mask_rev[18]
+port 10 nsew
+rlabel metal2 s 2962 6277 3018 7077 4 mask_rev[19]
+port 11 nsew
+rlabel metal3 s 0 3272 800 3392 4 mask_rev[1]
+port 12 nsew
+rlabel metal3 s 6309 2456 7109 2576 4 mask_rev[20]
+port 13 nsew
+rlabel metal3 s 6309 824 7109 944 4 mask_rev[21]
+port 14 nsew
+rlabel metal3 s 0 5992 800 6112 4 mask_rev[22]
+port 15 nsew
+rlabel metal2 s 1674 0 1730 800 4 mask_rev[23]
+port 16 nsew
+rlabel metal2 s 5906 6277 5962 7077 4 mask_rev[24]
+port 17 nsew
+rlabel metal3 s 0 1640 800 1760 4 mask_rev[25]
+port 18 nsew
+rlabel metal2 s 4802 6277 4858 7077 4 mask_rev[26]
+port 19 nsew
+rlabel metal2 s 1122 6277 1178 7077 4 mask_rev[27]
+port 20 nsew
+rlabel metal2 s 6458 6277 6514 7077 4 mask_rev[28]
+port 21 nsew
+rlabel metal2 s 5354 0 5410 800 4 mask_rev[29]
+port 22 nsew
+rlabel metal3 s 0 2456 800 2576 4 mask_rev[2]
+port 23 nsew
+rlabel metal3 s 6309 5176 7109 5296 4 mask_rev[30]
+port 24 nsew
+rlabel metal2 s 2962 0 3018 800 4 mask_rev[31]
+port 25 nsew
+rlabel metal2 s 3514 0 3570 800 4 mask_rev[3]
+port 26 nsew
+rlabel metal3 s 6309 3544 7109 3664 4 mask_rev[4]
+port 27 nsew
+rlabel metal3 s 6309 4360 7109 4480 4 mask_rev[5]
+port 28 nsew
+rlabel metal3 s 0 4360 800 4480 4 mask_rev[6]
+port 29 nsew
+rlabel metal2 s 3514 6277 3570 7077 4 mask_rev[7]
+port 30 nsew
+rlabel metal2 s 4802 0 4858 800 4 mask_rev[8]
+port 31 nsew
+rlabel metal2 s 2226 6277 2282 7077 4 mask_rev[9]
+port 32 nsew
+rlabel metal5 s 1104 1696 5980 2016 4 VPWR
+port 33 nsew
+rlabel metal5 s 1104 2512 5980 2832 4 VGND
+port 34 nsew
+<< properties >>
+string FIXED_BBOX 0 0 7109 7077
+<< end >>
diff --git a/tapeout/outputs/mag/user_id_textblock.mag b/tapeout/outputs/mag/user_id_textblock.mag
new file mode 100644
index 0000000..6f40b29
--- /dev/null
+++ b/tapeout/outputs/mag/user_id_textblock.mag
@@ -0,0 +1,43 @@
+magic
+tech sky130A
+timestamp 1608324878
+<< checkpaint >>
+rect 1495 5490 6500 6570
+rect -630 428 19262 5490
+rect -630 -630 6210 428
+rect 16092 356 18972 428
+<< fillblock >>
+rect -328 754 16860 5172
+use alpha_A  alphaX_0 hexdigits
+timestamp 1598786981
+transform 1 0 14887 0 1 1080
+box 0 0 1620 3780
+use alpha_C  alphaX_1 hexdigits
+timestamp 1598786981
+transform 1 0 12750 0 1 1080
+box 0 0 1620 3780
+use alpha_B  alphaX_2 hexdigits
+timestamp 1598786981
+transform 1 0 10625 0 1 1080
+box 0 0 1620 3780
+use alpha_8  alphaX_3 hexdigits
+timestamp 1598786981
+transform 1 0 8500 0 1 1080
+box 0 0 1620 3780
+use alpha_8  alphaX_4
+timestamp 1598786981
+transform 1 0 6375 0 1 1080
+box 0 0 1620 3780
+use alpha_0  alphaX_5 hexdigits
+timestamp 1598786981
+transform 1 0 4250 0 1 1080
+box 0 0 1620 3780
+use alpha_0  alphaX_6
+timestamp 1598786981
+transform 1 0 2125 0 1 1080
+box 0 0 1620 3780
+use alpha_0  alphaX_7
+timestamp 1598786981
+transform 1 0 0 0 1 1080
+box 0 0 1620 3780
+<< end >>
diff --git a/tapeout/outputs/oas/caravel_00088bca.oas b/tapeout/outputs/oas/caravel_00088bca.oas
new file mode 100644
index 0000000..d36e0ba
--- /dev/null
+++ b/tapeout/outputs/oas/caravel_00088bca.oas
Binary files differ
diff --git a/tapeout/outputs/verilog/gl/caravel.v b/tapeout/outputs/verilog/gl/caravel.v
new file mode 100644
index 0000000..4b63be3
--- /dev/null
+++ b/tapeout/outputs/verilog/gl/caravel.v
@@ -0,0 +1,5435 @@
+/* Generated by Yosys 0.9+4052 (git sha1 d061b0e, gcc 8.3.1 -fPIC -Os) */
+
+module caravel(vddio, vddio_2, vssio, vssio_2, vdda, vssa, vccd, vssd, vdda1, vdda1_2, vdda2, vssa1, vssa1_2, vssa2, vccd1, vccd2, vssd1, vssd2, gpio, mprj_io, clock, resetb, flash_csb, flash_clk, flash_io0, flash_io1);
+  wire caravel_clk;
+  wire caravel_clk2;
+  wire caravel_clk_buf;
+  wire caravel_rstn;
+  wire caravel_rstn_buf;
+  wire clk_passthru;
+  input clock;
+  wire clock_core;
+  wire clock_core_buf;
+  wire debug_in;
+  wire debug_mode;
+  wire debug_oeb;
+  wire debug_out;
+  wire ext_clk_sel;
+  wire ext_reset;
+  output flash_clk;
+  wire flash_clk_core;
+  wire flash_clk_frame;
+  wire flash_clk_frame_buf;
+  wire flash_clk_ieb;
+  wire flash_clk_ieb_buf;
+  wire flash_clk_oeb;
+  wire flash_clk_oeb_buf;
+  wire flash_clk_oeb_core;
+  output flash_csb;
+  wire flash_csb_core;
+  wire flash_csb_frame;
+  wire flash_csb_frame_buf;
+  wire flash_csb_ieb;
+  wire flash_csb_ieb_buf;
+  wire flash_csb_oeb;
+  wire flash_csb_oeb_buf;
+  wire flash_csb_oeb_core;
+  output flash_io0;
+  wire flash_io0_di;
+  wire flash_io0_di_buf;
+  wire flash_io0_di_core;
+  wire flash_io0_do;
+  wire flash_io0_do_buf;
+  wire flash_io0_do_core;
+  wire flash_io0_ieb;
+  wire flash_io0_ieb_buf;
+  wire flash_io0_ieb_core;
+  wire flash_io0_oeb;
+  wire flash_io0_oeb_buf;
+  wire flash_io0_oeb_core;
+  output flash_io1;
+  wire flash_io1_di;
+  wire flash_io1_di_buf;
+  wire flash_io1_di_core;
+  wire flash_io1_do;
+  wire flash_io1_do_buf;
+  wire flash_io1_do_core;
+  wire flash_io1_ieb;
+  wire flash_io1_ieb_buf;
+  wire flash_io1_ieb_core;
+  wire flash_io1_oeb;
+  wire flash_io1_oeb_buf;
+  wire flash_io1_oeb_core;
+  wire flash_io2_di_core;
+  wire flash_io2_do_core;
+  wire flash_io2_ieb_core;
+  wire flash_io2_oeb_core;
+  wire flash_io3_di_core;
+  wire flash_io3_do_core;
+  wire flash_io3_ieb_core;
+  wire flash_io3_oeb_core;
+  inout gpio;
+  wire \gpio_clock_1[0] ;
+  wire \gpio_clock_1[10] ;
+  wire \gpio_clock_1[11] ;
+  wire \gpio_clock_1[12] ;
+  wire \gpio_clock_1[13] ;
+  wire \gpio_clock_1[14] ;
+  wire \gpio_clock_1[15] ;
+  wire \gpio_clock_1[16] ;
+  wire \gpio_clock_1[17] ;
+  wire \gpio_clock_1[18] ;
+  wire \gpio_clock_1[1] ;
+  wire \gpio_clock_1[2] ;
+  wire \gpio_clock_1[3] ;
+  wire \gpio_clock_1[4] ;
+  wire \gpio_clock_1[5] ;
+  wire \gpio_clock_1[6] ;
+  wire \gpio_clock_1[7] ;
+  wire \gpio_clock_1[8] ;
+  wire \gpio_clock_1[9] ;
+  wire \gpio_clock_1_shifted[0] ;
+  wire \gpio_clock_1_shifted[10] ;
+  wire \gpio_clock_1_shifted[11] ;
+  wire \gpio_clock_1_shifted[12] ;
+  wire \gpio_clock_1_shifted[13] ;
+  wire \gpio_clock_1_shifted[14] ;
+  wire \gpio_clock_1_shifted[15] ;
+  wire \gpio_clock_1_shifted[16] ;
+  wire \gpio_clock_1_shifted[17] ;
+  wire \gpio_clock_1_shifted[18] ;
+  wire \gpio_clock_1_shifted[1] ;
+  wire \gpio_clock_1_shifted[2] ;
+  wire \gpio_clock_1_shifted[3] ;
+  wire \gpio_clock_1_shifted[4] ;
+  wire \gpio_clock_1_shifted[5] ;
+  wire \gpio_clock_1_shifted[6] ;
+  wire \gpio_clock_1_shifted[7] ;
+  wire \gpio_clock_1_shifted[8] ;
+  wire \gpio_clock_1_shifted[9] ;
+  wire \gpio_clock_2[0] ;
+  wire \gpio_clock_2[10] ;
+  wire \gpio_clock_2[11] ;
+  wire \gpio_clock_2[12] ;
+  wire \gpio_clock_2[13] ;
+  wire \gpio_clock_2[14] ;
+  wire \gpio_clock_2[15] ;
+  wire \gpio_clock_2[16] ;
+  wire \gpio_clock_2[17] ;
+  wire \gpio_clock_2[18] ;
+  wire \gpio_clock_2[1] ;
+  wire \gpio_clock_2[2] ;
+  wire \gpio_clock_2[3] ;
+  wire \gpio_clock_2[4] ;
+  wire \gpio_clock_2[5] ;
+  wire \gpio_clock_2[6] ;
+  wire \gpio_clock_2[7] ;
+  wire \gpio_clock_2[8] ;
+  wire \gpio_clock_2[9] ;
+  wire \gpio_clock_2_shifted[0] ;
+  wire \gpio_clock_2_shifted[10] ;
+  wire \gpio_clock_2_shifted[11] ;
+  wire \gpio_clock_2_shifted[12] ;
+  wire \gpio_clock_2_shifted[13] ;
+  wire \gpio_clock_2_shifted[14] ;
+  wire \gpio_clock_2_shifted[15] ;
+  wire \gpio_clock_2_shifted[16] ;
+  wire \gpio_clock_2_shifted[17] ;
+  wire \gpio_clock_2_shifted[18] ;
+  wire \gpio_clock_2_shifted[1] ;
+  wire \gpio_clock_2_shifted[2] ;
+  wire \gpio_clock_2_shifted[3] ;
+  wire \gpio_clock_2_shifted[4] ;
+  wire \gpio_clock_2_shifted[5] ;
+  wire \gpio_clock_2_shifted[6] ;
+  wire \gpio_clock_2_shifted[7] ;
+  wire \gpio_clock_2_shifted[8] ;
+  wire \gpio_clock_2_shifted[9] ;
+  wire \gpio_defaults[0] ;
+  wire \gpio_defaults[100] ;
+  wire \gpio_defaults[101] ;
+  wire \gpio_defaults[102] ;
+  wire \gpio_defaults[103] ;
+  wire \gpio_defaults[104] ;
+  wire \gpio_defaults[105] ;
+  wire \gpio_defaults[106] ;
+  wire \gpio_defaults[107] ;
+  wire \gpio_defaults[108] ;
+  wire \gpio_defaults[109] ;
+  wire \gpio_defaults[10] ;
+  wire \gpio_defaults[110] ;
+  wire \gpio_defaults[111] ;
+  wire \gpio_defaults[112] ;
+  wire \gpio_defaults[113] ;
+  wire \gpio_defaults[114] ;
+  wire \gpio_defaults[115] ;
+  wire \gpio_defaults[116] ;
+  wire \gpio_defaults[117] ;
+  wire \gpio_defaults[118] ;
+  wire \gpio_defaults[119] ;
+  wire \gpio_defaults[11] ;
+  wire \gpio_defaults[120] ;
+  wire \gpio_defaults[121] ;
+  wire \gpio_defaults[122] ;
+  wire \gpio_defaults[123] ;
+  wire \gpio_defaults[124] ;
+  wire \gpio_defaults[125] ;
+  wire \gpio_defaults[126] ;
+  wire \gpio_defaults[127] ;
+  wire \gpio_defaults[128] ;
+  wire \gpio_defaults[129] ;
+  wire \gpio_defaults[12] ;
+  wire \gpio_defaults[130] ;
+  wire \gpio_defaults[131] ;
+  wire \gpio_defaults[132] ;
+  wire \gpio_defaults[133] ;
+  wire \gpio_defaults[134] ;
+  wire \gpio_defaults[135] ;
+  wire \gpio_defaults[136] ;
+  wire \gpio_defaults[137] ;
+  wire \gpio_defaults[138] ;
+  wire \gpio_defaults[139] ;
+  wire \gpio_defaults[13] ;
+  wire \gpio_defaults[140] ;
+  wire \gpio_defaults[141] ;
+  wire \gpio_defaults[142] ;
+  wire \gpio_defaults[143] ;
+  wire \gpio_defaults[144] ;
+  wire \gpio_defaults[145] ;
+  wire \gpio_defaults[146] ;
+  wire \gpio_defaults[147] ;
+  wire \gpio_defaults[148] ;
+  wire \gpio_defaults[149] ;
+  wire \gpio_defaults[14] ;
+  wire \gpio_defaults[150] ;
+  wire \gpio_defaults[151] ;
+  wire \gpio_defaults[152] ;
+  wire \gpio_defaults[153] ;
+  wire \gpio_defaults[154] ;
+  wire \gpio_defaults[155] ;
+  wire \gpio_defaults[156] ;
+  wire \gpio_defaults[157] ;
+  wire \gpio_defaults[158] ;
+  wire \gpio_defaults[159] ;
+  wire \gpio_defaults[15] ;
+  wire \gpio_defaults[160] ;
+  wire \gpio_defaults[161] ;
+  wire \gpio_defaults[162] ;
+  wire \gpio_defaults[163] ;
+  wire \gpio_defaults[164] ;
+  wire \gpio_defaults[165] ;
+  wire \gpio_defaults[166] ;
+  wire \gpio_defaults[167] ;
+  wire \gpio_defaults[168] ;
+  wire \gpio_defaults[169] ;
+  wire \gpio_defaults[16] ;
+  wire \gpio_defaults[170] ;
+  wire \gpio_defaults[171] ;
+  wire \gpio_defaults[172] ;
+  wire \gpio_defaults[173] ;
+  wire \gpio_defaults[174] ;
+  wire \gpio_defaults[175] ;
+  wire \gpio_defaults[176] ;
+  wire \gpio_defaults[177] ;
+  wire \gpio_defaults[178] ;
+  wire \gpio_defaults[179] ;
+  wire \gpio_defaults[17] ;
+  wire \gpio_defaults[180] ;
+  wire \gpio_defaults[181] ;
+  wire \gpio_defaults[182] ;
+  wire \gpio_defaults[183] ;
+  wire \gpio_defaults[184] ;
+  wire \gpio_defaults[185] ;
+  wire \gpio_defaults[186] ;
+  wire \gpio_defaults[187] ;
+  wire \gpio_defaults[188] ;
+  wire \gpio_defaults[189] ;
+  wire \gpio_defaults[18] ;
+  wire \gpio_defaults[190] ;
+  wire \gpio_defaults[191] ;
+  wire \gpio_defaults[192] ;
+  wire \gpio_defaults[193] ;
+  wire \gpio_defaults[194] ;
+  wire \gpio_defaults[195] ;
+  wire \gpio_defaults[196] ;
+  wire \gpio_defaults[197] ;
+  wire \gpio_defaults[198] ;
+  wire \gpio_defaults[199] ;
+  wire \gpio_defaults[19] ;
+  wire \gpio_defaults[1] ;
+  wire \gpio_defaults[200] ;
+  wire \gpio_defaults[201] ;
+  wire \gpio_defaults[202] ;
+  wire \gpio_defaults[203] ;
+  wire \gpio_defaults[204] ;
+  wire \gpio_defaults[205] ;
+  wire \gpio_defaults[206] ;
+  wire \gpio_defaults[207] ;
+  wire \gpio_defaults[208] ;
+  wire \gpio_defaults[209] ;
+  wire \gpio_defaults[20] ;
+  wire \gpio_defaults[210] ;
+  wire \gpio_defaults[211] ;
+  wire \gpio_defaults[212] ;
+  wire \gpio_defaults[213] ;
+  wire \gpio_defaults[214] ;
+  wire \gpio_defaults[215] ;
+  wire \gpio_defaults[216] ;
+  wire \gpio_defaults[217] ;
+  wire \gpio_defaults[218] ;
+  wire \gpio_defaults[219] ;
+  wire \gpio_defaults[21] ;
+  wire \gpio_defaults[220] ;
+  wire \gpio_defaults[221] ;
+  wire \gpio_defaults[222] ;
+  wire \gpio_defaults[223] ;
+  wire \gpio_defaults[224] ;
+  wire \gpio_defaults[225] ;
+  wire \gpio_defaults[226] ;
+  wire \gpio_defaults[227] ;
+  wire \gpio_defaults[228] ;
+  wire \gpio_defaults[229] ;
+  wire \gpio_defaults[22] ;
+  wire \gpio_defaults[230] ;
+  wire \gpio_defaults[231] ;
+  wire \gpio_defaults[232] ;
+  wire \gpio_defaults[233] ;
+  wire \gpio_defaults[234] ;
+  wire \gpio_defaults[235] ;
+  wire \gpio_defaults[236] ;
+  wire \gpio_defaults[237] ;
+  wire \gpio_defaults[238] ;
+  wire \gpio_defaults[239] ;
+  wire \gpio_defaults[23] ;
+  wire \gpio_defaults[240] ;
+  wire \gpio_defaults[241] ;
+  wire \gpio_defaults[242] ;
+  wire \gpio_defaults[243] ;
+  wire \gpio_defaults[244] ;
+  wire \gpio_defaults[245] ;
+  wire \gpio_defaults[246] ;
+  wire \gpio_defaults[247] ;
+  wire \gpio_defaults[248] ;
+  wire \gpio_defaults[249] ;
+  wire \gpio_defaults[24] ;
+  wire \gpio_defaults[250] ;
+  wire \gpio_defaults[251] ;
+  wire \gpio_defaults[252] ;
+  wire \gpio_defaults[253] ;
+  wire \gpio_defaults[254] ;
+  wire \gpio_defaults[255] ;
+  wire \gpio_defaults[256] ;
+  wire \gpio_defaults[257] ;
+  wire \gpio_defaults[258] ;
+  wire \gpio_defaults[259] ;
+  wire \gpio_defaults[25] ;
+  wire \gpio_defaults[260] ;
+  wire \gpio_defaults[261] ;
+  wire \gpio_defaults[262] ;
+  wire \gpio_defaults[263] ;
+  wire \gpio_defaults[264] ;
+  wire \gpio_defaults[265] ;
+  wire \gpio_defaults[266] ;
+  wire \gpio_defaults[267] ;
+  wire \gpio_defaults[268] ;
+  wire \gpio_defaults[269] ;
+  wire \gpio_defaults[26] ;
+  wire \gpio_defaults[270] ;
+  wire \gpio_defaults[271] ;
+  wire \gpio_defaults[272] ;
+  wire \gpio_defaults[273] ;
+  wire \gpio_defaults[274] ;
+  wire \gpio_defaults[275] ;
+  wire \gpio_defaults[276] ;
+  wire \gpio_defaults[277] ;
+  wire \gpio_defaults[278] ;
+  wire \gpio_defaults[279] ;
+  wire \gpio_defaults[27] ;
+  wire \gpio_defaults[280] ;
+  wire \gpio_defaults[281] ;
+  wire \gpio_defaults[282] ;
+  wire \gpio_defaults[283] ;
+  wire \gpio_defaults[284] ;
+  wire \gpio_defaults[285] ;
+  wire \gpio_defaults[286] ;
+  wire \gpio_defaults[287] ;
+  wire \gpio_defaults[288] ;
+  wire \gpio_defaults[289] ;
+  wire \gpio_defaults[28] ;
+  wire \gpio_defaults[290] ;
+  wire \gpio_defaults[291] ;
+  wire \gpio_defaults[292] ;
+  wire \gpio_defaults[293] ;
+  wire \gpio_defaults[294] ;
+  wire \gpio_defaults[295] ;
+  wire \gpio_defaults[296] ;
+  wire \gpio_defaults[297] ;
+  wire \gpio_defaults[298] ;
+  wire \gpio_defaults[299] ;
+  wire \gpio_defaults[29] ;
+  wire \gpio_defaults[2] ;
+  wire \gpio_defaults[300] ;
+  wire \gpio_defaults[301] ;
+  wire \gpio_defaults[302] ;
+  wire \gpio_defaults[303] ;
+  wire \gpio_defaults[304] ;
+  wire \gpio_defaults[305] ;
+  wire \gpio_defaults[306] ;
+  wire \gpio_defaults[307] ;
+  wire \gpio_defaults[308] ;
+  wire \gpio_defaults[309] ;
+  wire \gpio_defaults[30] ;
+  wire \gpio_defaults[310] ;
+  wire \gpio_defaults[311] ;
+  wire \gpio_defaults[312] ;
+  wire \gpio_defaults[313] ;
+  wire \gpio_defaults[314] ;
+  wire \gpio_defaults[315] ;
+  wire \gpio_defaults[316] ;
+  wire \gpio_defaults[317] ;
+  wire \gpio_defaults[318] ;
+  wire \gpio_defaults[319] ;
+  wire \gpio_defaults[31] ;
+  wire \gpio_defaults[320] ;
+  wire \gpio_defaults[321] ;
+  wire \gpio_defaults[322] ;
+  wire \gpio_defaults[323] ;
+  wire \gpio_defaults[324] ;
+  wire \gpio_defaults[325] ;
+  wire \gpio_defaults[326] ;
+  wire \gpio_defaults[327] ;
+  wire \gpio_defaults[328] ;
+  wire \gpio_defaults[329] ;
+  wire \gpio_defaults[32] ;
+  wire \gpio_defaults[330] ;
+  wire \gpio_defaults[331] ;
+  wire \gpio_defaults[332] ;
+  wire \gpio_defaults[333] ;
+  wire \gpio_defaults[334] ;
+  wire \gpio_defaults[335] ;
+  wire \gpio_defaults[336] ;
+  wire \gpio_defaults[337] ;
+  wire \gpio_defaults[338] ;
+  wire \gpio_defaults[339] ;
+  wire \gpio_defaults[33] ;
+  wire \gpio_defaults[340] ;
+  wire \gpio_defaults[341] ;
+  wire \gpio_defaults[342] ;
+  wire \gpio_defaults[343] ;
+  wire \gpio_defaults[344] ;
+  wire \gpio_defaults[345] ;
+  wire \gpio_defaults[346] ;
+  wire \gpio_defaults[347] ;
+  wire \gpio_defaults[348] ;
+  wire \gpio_defaults[349] ;
+  wire \gpio_defaults[34] ;
+  wire \gpio_defaults[350] ;
+  wire \gpio_defaults[351] ;
+  wire \gpio_defaults[352] ;
+  wire \gpio_defaults[353] ;
+  wire \gpio_defaults[354] ;
+  wire \gpio_defaults[355] ;
+  wire \gpio_defaults[356] ;
+  wire \gpio_defaults[357] ;
+  wire \gpio_defaults[358] ;
+  wire \gpio_defaults[359] ;
+  wire \gpio_defaults[35] ;
+  wire \gpio_defaults[360] ;
+  wire \gpio_defaults[361] ;
+  wire \gpio_defaults[362] ;
+  wire \gpio_defaults[363] ;
+  wire \gpio_defaults[364] ;
+  wire \gpio_defaults[365] ;
+  wire \gpio_defaults[366] ;
+  wire \gpio_defaults[367] ;
+  wire \gpio_defaults[368] ;
+  wire \gpio_defaults[369] ;
+  wire \gpio_defaults[36] ;
+  wire \gpio_defaults[370] ;
+  wire \gpio_defaults[371] ;
+  wire \gpio_defaults[372] ;
+  wire \gpio_defaults[373] ;
+  wire \gpio_defaults[374] ;
+  wire \gpio_defaults[375] ;
+  wire \gpio_defaults[376] ;
+  wire \gpio_defaults[377] ;
+  wire \gpio_defaults[378] ;
+  wire \gpio_defaults[379] ;
+  wire \gpio_defaults[37] ;
+  wire \gpio_defaults[380] ;
+  wire \gpio_defaults[381] ;
+  wire \gpio_defaults[382] ;
+  wire \gpio_defaults[383] ;
+  wire \gpio_defaults[384] ;
+  wire \gpio_defaults[385] ;
+  wire \gpio_defaults[386] ;
+  wire \gpio_defaults[387] ;
+  wire \gpio_defaults[388] ;
+  wire \gpio_defaults[389] ;
+  wire \gpio_defaults[38] ;
+  wire \gpio_defaults[390] ;
+  wire \gpio_defaults[391] ;
+  wire \gpio_defaults[392] ;
+  wire \gpio_defaults[393] ;
+  wire \gpio_defaults[394] ;
+  wire \gpio_defaults[395] ;
+  wire \gpio_defaults[396] ;
+  wire \gpio_defaults[397] ;
+  wire \gpio_defaults[398] ;
+  wire \gpio_defaults[399] ;
+  wire \gpio_defaults[39] ;
+  wire \gpio_defaults[3] ;
+  wire \gpio_defaults[400] ;
+  wire \gpio_defaults[401] ;
+  wire \gpio_defaults[402] ;
+  wire \gpio_defaults[403] ;
+  wire \gpio_defaults[404] ;
+  wire \gpio_defaults[405] ;
+  wire \gpio_defaults[406] ;
+  wire \gpio_defaults[407] ;
+  wire \gpio_defaults[408] ;
+  wire \gpio_defaults[409] ;
+  wire \gpio_defaults[40] ;
+  wire \gpio_defaults[410] ;
+  wire \gpio_defaults[411] ;
+  wire \gpio_defaults[412] ;
+  wire \gpio_defaults[413] ;
+  wire \gpio_defaults[414] ;
+  wire \gpio_defaults[415] ;
+  wire \gpio_defaults[416] ;
+  wire \gpio_defaults[417] ;
+  wire \gpio_defaults[418] ;
+  wire \gpio_defaults[419] ;
+  wire \gpio_defaults[41] ;
+  wire \gpio_defaults[420] ;
+  wire \gpio_defaults[421] ;
+  wire \gpio_defaults[422] ;
+  wire \gpio_defaults[423] ;
+  wire \gpio_defaults[424] ;
+  wire \gpio_defaults[425] ;
+  wire \gpio_defaults[426] ;
+  wire \gpio_defaults[427] ;
+  wire \gpio_defaults[428] ;
+  wire \gpio_defaults[429] ;
+  wire \gpio_defaults[42] ;
+  wire \gpio_defaults[430] ;
+  wire \gpio_defaults[431] ;
+  wire \gpio_defaults[432] ;
+  wire \gpio_defaults[433] ;
+  wire \gpio_defaults[434] ;
+  wire \gpio_defaults[435] ;
+  wire \gpio_defaults[436] ;
+  wire \gpio_defaults[437] ;
+  wire \gpio_defaults[438] ;
+  wire \gpio_defaults[439] ;
+  wire \gpio_defaults[43] ;
+  wire \gpio_defaults[440] ;
+  wire \gpio_defaults[441] ;
+  wire \gpio_defaults[442] ;
+  wire \gpio_defaults[443] ;
+  wire \gpio_defaults[444] ;
+  wire \gpio_defaults[445] ;
+  wire \gpio_defaults[446] ;
+  wire \gpio_defaults[447] ;
+  wire \gpio_defaults[448] ;
+  wire \gpio_defaults[449] ;
+  wire \gpio_defaults[44] ;
+  wire \gpio_defaults[450] ;
+  wire \gpio_defaults[451] ;
+  wire \gpio_defaults[452] ;
+  wire \gpio_defaults[453] ;
+  wire \gpio_defaults[454] ;
+  wire \gpio_defaults[455] ;
+  wire \gpio_defaults[456] ;
+  wire \gpio_defaults[457] ;
+  wire \gpio_defaults[458] ;
+  wire \gpio_defaults[459] ;
+  wire \gpio_defaults[45] ;
+  wire \gpio_defaults[460] ;
+  wire \gpio_defaults[461] ;
+  wire \gpio_defaults[462] ;
+  wire \gpio_defaults[463] ;
+  wire \gpio_defaults[464] ;
+  wire \gpio_defaults[465] ;
+  wire \gpio_defaults[466] ;
+  wire \gpio_defaults[467] ;
+  wire \gpio_defaults[468] ;
+  wire \gpio_defaults[469] ;
+  wire \gpio_defaults[46] ;
+  wire \gpio_defaults[470] ;
+  wire \gpio_defaults[471] ;
+  wire \gpio_defaults[472] ;
+  wire \gpio_defaults[473] ;
+  wire \gpio_defaults[474] ;
+  wire \gpio_defaults[475] ;
+  wire \gpio_defaults[476] ;
+  wire \gpio_defaults[477] ;
+  wire \gpio_defaults[478] ;
+  wire \gpio_defaults[479] ;
+  wire \gpio_defaults[47] ;
+  wire \gpio_defaults[480] ;
+  wire \gpio_defaults[481] ;
+  wire \gpio_defaults[482] ;
+  wire \gpio_defaults[483] ;
+  wire \gpio_defaults[484] ;
+  wire \gpio_defaults[485] ;
+  wire \gpio_defaults[486] ;
+  wire \gpio_defaults[487] ;
+  wire \gpio_defaults[488] ;
+  wire \gpio_defaults[489] ;
+  wire \gpio_defaults[48] ;
+  wire \gpio_defaults[490] ;
+  wire \gpio_defaults[491] ;
+  wire \gpio_defaults[492] ;
+  wire \gpio_defaults[493] ;
+  wire \gpio_defaults[49] ;
+  wire \gpio_defaults[4] ;
+  wire \gpio_defaults[50] ;
+  wire \gpio_defaults[51] ;
+  wire \gpio_defaults[52] ;
+  wire \gpio_defaults[53] ;
+  wire \gpio_defaults[54] ;
+  wire \gpio_defaults[55] ;
+  wire \gpio_defaults[56] ;
+  wire \gpio_defaults[57] ;
+  wire \gpio_defaults[58] ;
+  wire \gpio_defaults[59] ;
+  wire \gpio_defaults[5] ;
+  wire \gpio_defaults[60] ;
+  wire \gpio_defaults[61] ;
+  wire \gpio_defaults[62] ;
+  wire \gpio_defaults[63] ;
+  wire \gpio_defaults[64] ;
+  wire \gpio_defaults[65] ;
+  wire \gpio_defaults[66] ;
+  wire \gpio_defaults[67] ;
+  wire \gpio_defaults[68] ;
+  wire \gpio_defaults[69] ;
+  wire \gpio_defaults[6] ;
+  wire \gpio_defaults[70] ;
+  wire \gpio_defaults[71] ;
+  wire \gpio_defaults[72] ;
+  wire \gpio_defaults[73] ;
+  wire \gpio_defaults[74] ;
+  wire \gpio_defaults[75] ;
+  wire \gpio_defaults[76] ;
+  wire \gpio_defaults[77] ;
+  wire \gpio_defaults[78] ;
+  wire \gpio_defaults[79] ;
+  wire \gpio_defaults[7] ;
+  wire \gpio_defaults[80] ;
+  wire \gpio_defaults[81] ;
+  wire \gpio_defaults[82] ;
+  wire \gpio_defaults[83] ;
+  wire \gpio_defaults[84] ;
+  wire \gpio_defaults[85] ;
+  wire \gpio_defaults[86] ;
+  wire \gpio_defaults[87] ;
+  wire \gpio_defaults[88] ;
+  wire \gpio_defaults[89] ;
+  wire \gpio_defaults[8] ;
+  wire \gpio_defaults[90] ;
+  wire \gpio_defaults[91] ;
+  wire \gpio_defaults[92] ;
+  wire \gpio_defaults[93] ;
+  wire \gpio_defaults[94] ;
+  wire \gpio_defaults[95] ;
+  wire \gpio_defaults[96] ;
+  wire \gpio_defaults[97] ;
+  wire \gpio_defaults[98] ;
+  wire \gpio_defaults[99] ;
+  wire \gpio_defaults[9] ;
+  wire gpio_in_core;
+  wire gpio_inenb_core;
+  wire \gpio_load_1[0] ;
+  wire \gpio_load_1[10] ;
+  wire \gpio_load_1[11] ;
+  wire \gpio_load_1[12] ;
+  wire \gpio_load_1[13] ;
+  wire \gpio_load_1[14] ;
+  wire \gpio_load_1[15] ;
+  wire \gpio_load_1[16] ;
+  wire \gpio_load_1[17] ;
+  wire \gpio_load_1[18] ;
+  wire \gpio_load_1[1] ;
+  wire \gpio_load_1[2] ;
+  wire \gpio_load_1[3] ;
+  wire \gpio_load_1[4] ;
+  wire \gpio_load_1[5] ;
+  wire \gpio_load_1[6] ;
+  wire \gpio_load_1[7] ;
+  wire \gpio_load_1[8] ;
+  wire \gpio_load_1[9] ;
+  wire \gpio_load_1_shifted[0] ;
+  wire \gpio_load_1_shifted[10] ;
+  wire \gpio_load_1_shifted[11] ;
+  wire \gpio_load_1_shifted[12] ;
+  wire \gpio_load_1_shifted[13] ;
+  wire \gpio_load_1_shifted[14] ;
+  wire \gpio_load_1_shifted[15] ;
+  wire \gpio_load_1_shifted[16] ;
+  wire \gpio_load_1_shifted[17] ;
+  wire \gpio_load_1_shifted[18] ;
+  wire \gpio_load_1_shifted[1] ;
+  wire \gpio_load_1_shifted[2] ;
+  wire \gpio_load_1_shifted[3] ;
+  wire \gpio_load_1_shifted[4] ;
+  wire \gpio_load_1_shifted[5] ;
+  wire \gpio_load_1_shifted[6] ;
+  wire \gpio_load_1_shifted[7] ;
+  wire \gpio_load_1_shifted[8] ;
+  wire \gpio_load_1_shifted[9] ;
+  wire \gpio_load_2[0] ;
+  wire \gpio_load_2[10] ;
+  wire \gpio_load_2[11] ;
+  wire \gpio_load_2[12] ;
+  wire \gpio_load_2[13] ;
+  wire \gpio_load_2[14] ;
+  wire \gpio_load_2[15] ;
+  wire \gpio_load_2[16] ;
+  wire \gpio_load_2[17] ;
+  wire \gpio_load_2[18] ;
+  wire \gpio_load_2[1] ;
+  wire \gpio_load_2[2] ;
+  wire \gpio_load_2[3] ;
+  wire \gpio_load_2[4] ;
+  wire \gpio_load_2[5] ;
+  wire \gpio_load_2[6] ;
+  wire \gpio_load_2[7] ;
+  wire \gpio_load_2[8] ;
+  wire \gpio_load_2[9] ;
+  wire \gpio_load_2_shifted[0] ;
+  wire \gpio_load_2_shifted[10] ;
+  wire \gpio_load_2_shifted[11] ;
+  wire \gpio_load_2_shifted[12] ;
+  wire \gpio_load_2_shifted[13] ;
+  wire \gpio_load_2_shifted[14] ;
+  wire \gpio_load_2_shifted[15] ;
+  wire \gpio_load_2_shifted[16] ;
+  wire \gpio_load_2_shifted[17] ;
+  wire \gpio_load_2_shifted[18] ;
+  wire \gpio_load_2_shifted[1] ;
+  wire \gpio_load_2_shifted[2] ;
+  wire \gpio_load_2_shifted[3] ;
+  wire \gpio_load_2_shifted[4] ;
+  wire \gpio_load_2_shifted[5] ;
+  wire \gpio_load_2_shifted[6] ;
+  wire \gpio_load_2_shifted[7] ;
+  wire \gpio_load_2_shifted[8] ;
+  wire \gpio_load_2_shifted[9] ;
+  wire gpio_mode0_core;
+  wire gpio_mode1_core;
+  wire gpio_out_core;
+  wire gpio_outenb_core;
+  wire \gpio_resetn_1[0] ;
+  wire \gpio_resetn_1[10] ;
+  wire \gpio_resetn_1[11] ;
+  wire \gpio_resetn_1[12] ;
+  wire \gpio_resetn_1[13] ;
+  wire \gpio_resetn_1[14] ;
+  wire \gpio_resetn_1[15] ;
+  wire \gpio_resetn_1[16] ;
+  wire \gpio_resetn_1[17] ;
+  wire \gpio_resetn_1[18] ;
+  wire \gpio_resetn_1[1] ;
+  wire \gpio_resetn_1[2] ;
+  wire \gpio_resetn_1[3] ;
+  wire \gpio_resetn_1[4] ;
+  wire \gpio_resetn_1[5] ;
+  wire \gpio_resetn_1[6] ;
+  wire \gpio_resetn_1[7] ;
+  wire \gpio_resetn_1[8] ;
+  wire \gpio_resetn_1[9] ;
+  wire \gpio_resetn_1_shifted[0] ;
+  wire \gpio_resetn_1_shifted[10] ;
+  wire \gpio_resetn_1_shifted[11] ;
+  wire \gpio_resetn_1_shifted[12] ;
+  wire \gpio_resetn_1_shifted[13] ;
+  wire \gpio_resetn_1_shifted[14] ;
+  wire \gpio_resetn_1_shifted[15] ;
+  wire \gpio_resetn_1_shifted[16] ;
+  wire \gpio_resetn_1_shifted[17] ;
+  wire \gpio_resetn_1_shifted[18] ;
+  wire \gpio_resetn_1_shifted[1] ;
+  wire \gpio_resetn_1_shifted[2] ;
+  wire \gpio_resetn_1_shifted[3] ;
+  wire \gpio_resetn_1_shifted[4] ;
+  wire \gpio_resetn_1_shifted[5] ;
+  wire \gpio_resetn_1_shifted[6] ;
+  wire \gpio_resetn_1_shifted[7] ;
+  wire \gpio_resetn_1_shifted[8] ;
+  wire \gpio_resetn_1_shifted[9] ;
+  wire \gpio_resetn_2[0] ;
+  wire \gpio_resetn_2[10] ;
+  wire \gpio_resetn_2[11] ;
+  wire \gpio_resetn_2[12] ;
+  wire \gpio_resetn_2[13] ;
+  wire \gpio_resetn_2[14] ;
+  wire \gpio_resetn_2[15] ;
+  wire \gpio_resetn_2[16] ;
+  wire \gpio_resetn_2[17] ;
+  wire \gpio_resetn_2[18] ;
+  wire \gpio_resetn_2[1] ;
+  wire \gpio_resetn_2[2] ;
+  wire \gpio_resetn_2[3] ;
+  wire \gpio_resetn_2[4] ;
+  wire \gpio_resetn_2[5] ;
+  wire \gpio_resetn_2[6] ;
+  wire \gpio_resetn_2[7] ;
+  wire \gpio_resetn_2[8] ;
+  wire \gpio_resetn_2[9] ;
+  wire \gpio_resetn_2_shifted[0] ;
+  wire \gpio_resetn_2_shifted[10] ;
+  wire \gpio_resetn_2_shifted[11] ;
+  wire \gpio_resetn_2_shifted[12] ;
+  wire \gpio_resetn_2_shifted[13] ;
+  wire \gpio_resetn_2_shifted[14] ;
+  wire \gpio_resetn_2_shifted[15] ;
+  wire \gpio_resetn_2_shifted[16] ;
+  wire \gpio_resetn_2_shifted[17] ;
+  wire \gpio_resetn_2_shifted[18] ;
+  wire \gpio_resetn_2_shifted[1] ;
+  wire \gpio_resetn_2_shifted[2] ;
+  wire \gpio_resetn_2_shifted[3] ;
+  wire \gpio_resetn_2_shifted[4] ;
+  wire \gpio_resetn_2_shifted[5] ;
+  wire \gpio_resetn_2_shifted[6] ;
+  wire \gpio_resetn_2_shifted[7] ;
+  wire \gpio_resetn_2_shifted[8] ;
+  wire \gpio_resetn_2_shifted[9] ;
+  wire \gpio_serial_link_1[0] ;
+  wire \gpio_serial_link_1[10] ;
+  wire \gpio_serial_link_1[11] ;
+  wire \gpio_serial_link_1[12] ;
+  wire \gpio_serial_link_1[13] ;
+  wire \gpio_serial_link_1[14] ;
+  wire \gpio_serial_link_1[15] ;
+  wire \gpio_serial_link_1[16] ;
+  wire \gpio_serial_link_1[17] ;
+  wire \gpio_serial_link_1[18] ;
+  wire \gpio_serial_link_1[1] ;
+  wire \gpio_serial_link_1[2] ;
+  wire \gpio_serial_link_1[3] ;
+  wire \gpio_serial_link_1[4] ;
+  wire \gpio_serial_link_1[5] ;
+  wire \gpio_serial_link_1[6] ;
+  wire \gpio_serial_link_1[7] ;
+  wire \gpio_serial_link_1[8] ;
+  wire \gpio_serial_link_1[9] ;
+  wire \gpio_serial_link_1_shifted[0] ;
+  wire \gpio_serial_link_1_shifted[10] ;
+  wire \gpio_serial_link_1_shifted[11] ;
+  wire \gpio_serial_link_1_shifted[12] ;
+  wire \gpio_serial_link_1_shifted[13] ;
+  wire \gpio_serial_link_1_shifted[14] ;
+  wire \gpio_serial_link_1_shifted[15] ;
+  wire \gpio_serial_link_1_shifted[16] ;
+  wire \gpio_serial_link_1_shifted[17] ;
+  wire \gpio_serial_link_1_shifted[18] ;
+  wire \gpio_serial_link_1_shifted[1] ;
+  wire \gpio_serial_link_1_shifted[2] ;
+  wire \gpio_serial_link_1_shifted[3] ;
+  wire \gpio_serial_link_1_shifted[4] ;
+  wire \gpio_serial_link_1_shifted[5] ;
+  wire \gpio_serial_link_1_shifted[6] ;
+  wire \gpio_serial_link_1_shifted[7] ;
+  wire \gpio_serial_link_1_shifted[8] ;
+  wire \gpio_serial_link_1_shifted[9] ;
+  wire \gpio_serial_link_2[0] ;
+  wire \gpio_serial_link_2[10] ;
+  wire \gpio_serial_link_2[11] ;
+  wire \gpio_serial_link_2[12] ;
+  wire \gpio_serial_link_2[13] ;
+  wire \gpio_serial_link_2[14] ;
+  wire \gpio_serial_link_2[15] ;
+  wire \gpio_serial_link_2[16] ;
+  wire \gpio_serial_link_2[17] ;
+  wire \gpio_serial_link_2[18] ;
+  wire \gpio_serial_link_2[1] ;
+  wire \gpio_serial_link_2[2] ;
+  wire \gpio_serial_link_2[3] ;
+  wire \gpio_serial_link_2[4] ;
+  wire \gpio_serial_link_2[5] ;
+  wire \gpio_serial_link_2[6] ;
+  wire \gpio_serial_link_2[7] ;
+  wire \gpio_serial_link_2[8] ;
+  wire \gpio_serial_link_2[9] ;
+  wire \gpio_serial_link_2_shifted[0] ;
+  wire \gpio_serial_link_2_shifted[10] ;
+  wire \gpio_serial_link_2_shifted[11] ;
+  wire \gpio_serial_link_2_shifted[12] ;
+  wire \gpio_serial_link_2_shifted[13] ;
+  wire \gpio_serial_link_2_shifted[14] ;
+  wire \gpio_serial_link_2_shifted[15] ;
+  wire \gpio_serial_link_2_shifted[16] ;
+  wire \gpio_serial_link_2_shifted[17] ;
+  wire \gpio_serial_link_2_shifted[18] ;
+  wire \gpio_serial_link_2_shifted[1] ;
+  wire \gpio_serial_link_2_shifted[2] ;
+  wire \gpio_serial_link_2_shifted[3] ;
+  wire \gpio_serial_link_2_shifted[4] ;
+  wire \gpio_serial_link_2_shifted[5] ;
+  wire \gpio_serial_link_2_shifted[6] ;
+  wire \gpio_serial_link_2_shifted[7] ;
+  wire \gpio_serial_link_2_shifted[8] ;
+  wire \gpio_serial_link_2_shifted[9] ;
+  wire hk_ack_i;
+  wire hk_cyc_o;
+  wire \hk_dat_i[0] ;
+  wire \hk_dat_i[10] ;
+  wire \hk_dat_i[11] ;
+  wire \hk_dat_i[12] ;
+  wire \hk_dat_i[13] ;
+  wire \hk_dat_i[14] ;
+  wire \hk_dat_i[15] ;
+  wire \hk_dat_i[16] ;
+  wire \hk_dat_i[17] ;
+  wire \hk_dat_i[18] ;
+  wire \hk_dat_i[19] ;
+  wire \hk_dat_i[1] ;
+  wire \hk_dat_i[20] ;
+  wire \hk_dat_i[21] ;
+  wire \hk_dat_i[22] ;
+  wire \hk_dat_i[23] ;
+  wire \hk_dat_i[24] ;
+  wire \hk_dat_i[25] ;
+  wire \hk_dat_i[26] ;
+  wire \hk_dat_i[27] ;
+  wire \hk_dat_i[28] ;
+  wire \hk_dat_i[29] ;
+  wire \hk_dat_i[2] ;
+  wire \hk_dat_i[30] ;
+  wire \hk_dat_i[31] ;
+  wire \hk_dat_i[3] ;
+  wire \hk_dat_i[4] ;
+  wire \hk_dat_i[5] ;
+  wire \hk_dat_i[6] ;
+  wire \hk_dat_i[7] ;
+  wire \hk_dat_i[8] ;
+  wire \hk_dat_i[9] ;
+  wire hk_stb_o;
+  wire \irq_spi[0] ;
+  wire \irq_spi[1] ;
+  wire \irq_spi[2] ;
+  wire \la_data_in_mprj[0] ;
+  wire \la_data_in_mprj[100] ;
+  wire \la_data_in_mprj[101] ;
+  wire \la_data_in_mprj[102] ;
+  wire \la_data_in_mprj[103] ;
+  wire \la_data_in_mprj[104] ;
+  wire \la_data_in_mprj[105] ;
+  wire \la_data_in_mprj[106] ;
+  wire \la_data_in_mprj[107] ;
+  wire \la_data_in_mprj[108] ;
+  wire \la_data_in_mprj[109] ;
+  wire \la_data_in_mprj[10] ;
+  wire \la_data_in_mprj[110] ;
+  wire \la_data_in_mprj[111] ;
+  wire \la_data_in_mprj[112] ;
+  wire \la_data_in_mprj[113] ;
+  wire \la_data_in_mprj[114] ;
+  wire \la_data_in_mprj[115] ;
+  wire \la_data_in_mprj[116] ;
+  wire \la_data_in_mprj[117] ;
+  wire \la_data_in_mprj[118] ;
+  wire \la_data_in_mprj[119] ;
+  wire \la_data_in_mprj[11] ;
+  wire \la_data_in_mprj[120] ;
+  wire \la_data_in_mprj[121] ;
+  wire \la_data_in_mprj[122] ;
+  wire \la_data_in_mprj[123] ;
+  wire \la_data_in_mprj[124] ;
+  wire \la_data_in_mprj[125] ;
+  wire \la_data_in_mprj[126] ;
+  wire \la_data_in_mprj[127] ;
+  wire \la_data_in_mprj[12] ;
+  wire \la_data_in_mprj[13] ;
+  wire \la_data_in_mprj[14] ;
+  wire \la_data_in_mprj[15] ;
+  wire \la_data_in_mprj[16] ;
+  wire \la_data_in_mprj[17] ;
+  wire \la_data_in_mprj[18] ;
+  wire \la_data_in_mprj[19] ;
+  wire \la_data_in_mprj[1] ;
+  wire \la_data_in_mprj[20] ;
+  wire \la_data_in_mprj[21] ;
+  wire \la_data_in_mprj[22] ;
+  wire \la_data_in_mprj[23] ;
+  wire \la_data_in_mprj[24] ;
+  wire \la_data_in_mprj[25] ;
+  wire \la_data_in_mprj[26] ;
+  wire \la_data_in_mprj[27] ;
+  wire \la_data_in_mprj[28] ;
+  wire \la_data_in_mprj[29] ;
+  wire \la_data_in_mprj[2] ;
+  wire \la_data_in_mprj[30] ;
+  wire \la_data_in_mprj[31] ;
+  wire \la_data_in_mprj[32] ;
+  wire \la_data_in_mprj[33] ;
+  wire \la_data_in_mprj[34] ;
+  wire \la_data_in_mprj[35] ;
+  wire \la_data_in_mprj[36] ;
+  wire \la_data_in_mprj[37] ;
+  wire \la_data_in_mprj[38] ;
+  wire \la_data_in_mprj[39] ;
+  wire \la_data_in_mprj[3] ;
+  wire \la_data_in_mprj[40] ;
+  wire \la_data_in_mprj[41] ;
+  wire \la_data_in_mprj[42] ;
+  wire \la_data_in_mprj[43] ;
+  wire \la_data_in_mprj[44] ;
+  wire \la_data_in_mprj[45] ;
+  wire \la_data_in_mprj[46] ;
+  wire \la_data_in_mprj[47] ;
+  wire \la_data_in_mprj[48] ;
+  wire \la_data_in_mprj[49] ;
+  wire \la_data_in_mprj[4] ;
+  wire \la_data_in_mprj[50] ;
+  wire \la_data_in_mprj[51] ;
+  wire \la_data_in_mprj[52] ;
+  wire \la_data_in_mprj[53] ;
+  wire \la_data_in_mprj[54] ;
+  wire \la_data_in_mprj[55] ;
+  wire \la_data_in_mprj[56] ;
+  wire \la_data_in_mprj[57] ;
+  wire \la_data_in_mprj[58] ;
+  wire \la_data_in_mprj[59] ;
+  wire \la_data_in_mprj[5] ;
+  wire \la_data_in_mprj[60] ;
+  wire \la_data_in_mprj[61] ;
+  wire \la_data_in_mprj[62] ;
+  wire \la_data_in_mprj[63] ;
+  wire \la_data_in_mprj[64] ;
+  wire \la_data_in_mprj[65] ;
+  wire \la_data_in_mprj[66] ;
+  wire \la_data_in_mprj[67] ;
+  wire \la_data_in_mprj[68] ;
+  wire \la_data_in_mprj[69] ;
+  wire \la_data_in_mprj[6] ;
+  wire \la_data_in_mprj[70] ;
+  wire \la_data_in_mprj[71] ;
+  wire \la_data_in_mprj[72] ;
+  wire \la_data_in_mprj[73] ;
+  wire \la_data_in_mprj[74] ;
+  wire \la_data_in_mprj[75] ;
+  wire \la_data_in_mprj[76] ;
+  wire \la_data_in_mprj[77] ;
+  wire \la_data_in_mprj[78] ;
+  wire \la_data_in_mprj[79] ;
+  wire \la_data_in_mprj[7] ;
+  wire \la_data_in_mprj[80] ;
+  wire \la_data_in_mprj[81] ;
+  wire \la_data_in_mprj[82] ;
+  wire \la_data_in_mprj[83] ;
+  wire \la_data_in_mprj[84] ;
+  wire \la_data_in_mprj[85] ;
+  wire \la_data_in_mprj[86] ;
+  wire \la_data_in_mprj[87] ;
+  wire \la_data_in_mprj[88] ;
+  wire \la_data_in_mprj[89] ;
+  wire \la_data_in_mprj[8] ;
+  wire \la_data_in_mprj[90] ;
+  wire \la_data_in_mprj[91] ;
+  wire \la_data_in_mprj[92] ;
+  wire \la_data_in_mprj[93] ;
+  wire \la_data_in_mprj[94] ;
+  wire \la_data_in_mprj[95] ;
+  wire \la_data_in_mprj[96] ;
+  wire \la_data_in_mprj[97] ;
+  wire \la_data_in_mprj[98] ;
+  wire \la_data_in_mprj[99] ;
+  wire \la_data_in_mprj[9] ;
+  wire \la_data_in_user[0] ;
+  wire \la_data_in_user[100] ;
+  wire \la_data_in_user[101] ;
+  wire \la_data_in_user[102] ;
+  wire \la_data_in_user[103] ;
+  wire \la_data_in_user[104] ;
+  wire \la_data_in_user[105] ;
+  wire \la_data_in_user[106] ;
+  wire \la_data_in_user[107] ;
+  wire \la_data_in_user[108] ;
+  wire \la_data_in_user[109] ;
+  wire \la_data_in_user[10] ;
+  wire \la_data_in_user[110] ;
+  wire \la_data_in_user[111] ;
+  wire \la_data_in_user[112] ;
+  wire \la_data_in_user[113] ;
+  wire \la_data_in_user[114] ;
+  wire \la_data_in_user[115] ;
+  wire \la_data_in_user[116] ;
+  wire \la_data_in_user[117] ;
+  wire \la_data_in_user[118] ;
+  wire \la_data_in_user[119] ;
+  wire \la_data_in_user[11] ;
+  wire \la_data_in_user[120] ;
+  wire \la_data_in_user[121] ;
+  wire \la_data_in_user[122] ;
+  wire \la_data_in_user[123] ;
+  wire \la_data_in_user[124] ;
+  wire \la_data_in_user[125] ;
+  wire \la_data_in_user[126] ;
+  wire \la_data_in_user[127] ;
+  wire \la_data_in_user[12] ;
+  wire \la_data_in_user[13] ;
+  wire \la_data_in_user[14] ;
+  wire \la_data_in_user[15] ;
+  wire \la_data_in_user[16] ;
+  wire \la_data_in_user[17] ;
+  wire \la_data_in_user[18] ;
+  wire \la_data_in_user[19] ;
+  wire \la_data_in_user[1] ;
+  wire \la_data_in_user[20] ;
+  wire \la_data_in_user[21] ;
+  wire \la_data_in_user[22] ;
+  wire \la_data_in_user[23] ;
+  wire \la_data_in_user[24] ;
+  wire \la_data_in_user[25] ;
+  wire \la_data_in_user[26] ;
+  wire \la_data_in_user[27] ;
+  wire \la_data_in_user[28] ;
+  wire \la_data_in_user[29] ;
+  wire \la_data_in_user[2] ;
+  wire \la_data_in_user[30] ;
+  wire \la_data_in_user[31] ;
+  wire \la_data_in_user[32] ;
+  wire \la_data_in_user[33] ;
+  wire \la_data_in_user[34] ;
+  wire \la_data_in_user[35] ;
+  wire \la_data_in_user[36] ;
+  wire \la_data_in_user[37] ;
+  wire \la_data_in_user[38] ;
+  wire \la_data_in_user[39] ;
+  wire \la_data_in_user[3] ;
+  wire \la_data_in_user[40] ;
+  wire \la_data_in_user[41] ;
+  wire \la_data_in_user[42] ;
+  wire \la_data_in_user[43] ;
+  wire \la_data_in_user[44] ;
+  wire \la_data_in_user[45] ;
+  wire \la_data_in_user[46] ;
+  wire \la_data_in_user[47] ;
+  wire \la_data_in_user[48] ;
+  wire \la_data_in_user[49] ;
+  wire \la_data_in_user[4] ;
+  wire \la_data_in_user[50] ;
+  wire \la_data_in_user[51] ;
+  wire \la_data_in_user[52] ;
+  wire \la_data_in_user[53] ;
+  wire \la_data_in_user[54] ;
+  wire \la_data_in_user[55] ;
+  wire \la_data_in_user[56] ;
+  wire \la_data_in_user[57] ;
+  wire \la_data_in_user[58] ;
+  wire \la_data_in_user[59] ;
+  wire \la_data_in_user[5] ;
+  wire \la_data_in_user[60] ;
+  wire \la_data_in_user[61] ;
+  wire \la_data_in_user[62] ;
+  wire \la_data_in_user[63] ;
+  wire \la_data_in_user[64] ;
+  wire \la_data_in_user[65] ;
+  wire \la_data_in_user[66] ;
+  wire \la_data_in_user[67] ;
+  wire \la_data_in_user[68] ;
+  wire \la_data_in_user[69] ;
+  wire \la_data_in_user[6] ;
+  wire \la_data_in_user[70] ;
+  wire \la_data_in_user[71] ;
+  wire \la_data_in_user[72] ;
+  wire \la_data_in_user[73] ;
+  wire \la_data_in_user[74] ;
+  wire \la_data_in_user[75] ;
+  wire \la_data_in_user[76] ;
+  wire \la_data_in_user[77] ;
+  wire \la_data_in_user[78] ;
+  wire \la_data_in_user[79] ;
+  wire \la_data_in_user[7] ;
+  wire \la_data_in_user[80] ;
+  wire \la_data_in_user[81] ;
+  wire \la_data_in_user[82] ;
+  wire \la_data_in_user[83] ;
+  wire \la_data_in_user[84] ;
+  wire \la_data_in_user[85] ;
+  wire \la_data_in_user[86] ;
+  wire \la_data_in_user[87] ;
+  wire \la_data_in_user[88] ;
+  wire \la_data_in_user[89] ;
+  wire \la_data_in_user[8] ;
+  wire \la_data_in_user[90] ;
+  wire \la_data_in_user[91] ;
+  wire \la_data_in_user[92] ;
+  wire \la_data_in_user[93] ;
+  wire \la_data_in_user[94] ;
+  wire \la_data_in_user[95] ;
+  wire \la_data_in_user[96] ;
+  wire \la_data_in_user[97] ;
+  wire \la_data_in_user[98] ;
+  wire \la_data_in_user[99] ;
+  wire \la_data_in_user[9] ;
+  wire \la_data_out_mprj[0] ;
+  wire \la_data_out_mprj[100] ;
+  wire \la_data_out_mprj[101] ;
+  wire \la_data_out_mprj[102] ;
+  wire \la_data_out_mprj[103] ;
+  wire \la_data_out_mprj[104] ;
+  wire \la_data_out_mprj[105] ;
+  wire \la_data_out_mprj[106] ;
+  wire \la_data_out_mprj[107] ;
+  wire \la_data_out_mprj[108] ;
+  wire \la_data_out_mprj[109] ;
+  wire \la_data_out_mprj[10] ;
+  wire \la_data_out_mprj[110] ;
+  wire \la_data_out_mprj[111] ;
+  wire \la_data_out_mprj[112] ;
+  wire \la_data_out_mprj[113] ;
+  wire \la_data_out_mprj[114] ;
+  wire \la_data_out_mprj[115] ;
+  wire \la_data_out_mprj[116] ;
+  wire \la_data_out_mprj[117] ;
+  wire \la_data_out_mprj[118] ;
+  wire \la_data_out_mprj[119] ;
+  wire \la_data_out_mprj[11] ;
+  wire \la_data_out_mprj[120] ;
+  wire \la_data_out_mprj[121] ;
+  wire \la_data_out_mprj[122] ;
+  wire \la_data_out_mprj[123] ;
+  wire \la_data_out_mprj[124] ;
+  wire \la_data_out_mprj[125] ;
+  wire \la_data_out_mprj[126] ;
+  wire \la_data_out_mprj[127] ;
+  wire \la_data_out_mprj[12] ;
+  wire \la_data_out_mprj[13] ;
+  wire \la_data_out_mprj[14] ;
+  wire \la_data_out_mprj[15] ;
+  wire \la_data_out_mprj[16] ;
+  wire \la_data_out_mprj[17] ;
+  wire \la_data_out_mprj[18] ;
+  wire \la_data_out_mprj[19] ;
+  wire \la_data_out_mprj[1] ;
+  wire \la_data_out_mprj[20] ;
+  wire \la_data_out_mprj[21] ;
+  wire \la_data_out_mprj[22] ;
+  wire \la_data_out_mprj[23] ;
+  wire \la_data_out_mprj[24] ;
+  wire \la_data_out_mprj[25] ;
+  wire \la_data_out_mprj[26] ;
+  wire \la_data_out_mprj[27] ;
+  wire \la_data_out_mprj[28] ;
+  wire \la_data_out_mprj[29] ;
+  wire \la_data_out_mprj[2] ;
+  wire \la_data_out_mprj[30] ;
+  wire \la_data_out_mprj[31] ;
+  wire \la_data_out_mprj[32] ;
+  wire \la_data_out_mprj[33] ;
+  wire \la_data_out_mprj[34] ;
+  wire \la_data_out_mprj[35] ;
+  wire \la_data_out_mprj[36] ;
+  wire \la_data_out_mprj[37] ;
+  wire \la_data_out_mprj[38] ;
+  wire \la_data_out_mprj[39] ;
+  wire \la_data_out_mprj[3] ;
+  wire \la_data_out_mprj[40] ;
+  wire \la_data_out_mprj[41] ;
+  wire \la_data_out_mprj[42] ;
+  wire \la_data_out_mprj[43] ;
+  wire \la_data_out_mprj[44] ;
+  wire \la_data_out_mprj[45] ;
+  wire \la_data_out_mprj[46] ;
+  wire \la_data_out_mprj[47] ;
+  wire \la_data_out_mprj[48] ;
+  wire \la_data_out_mprj[49] ;
+  wire \la_data_out_mprj[4] ;
+  wire \la_data_out_mprj[50] ;
+  wire \la_data_out_mprj[51] ;
+  wire \la_data_out_mprj[52] ;
+  wire \la_data_out_mprj[53] ;
+  wire \la_data_out_mprj[54] ;
+  wire \la_data_out_mprj[55] ;
+  wire \la_data_out_mprj[56] ;
+  wire \la_data_out_mprj[57] ;
+  wire \la_data_out_mprj[58] ;
+  wire \la_data_out_mprj[59] ;
+  wire \la_data_out_mprj[5] ;
+  wire \la_data_out_mprj[60] ;
+  wire \la_data_out_mprj[61] ;
+  wire \la_data_out_mprj[62] ;
+  wire \la_data_out_mprj[63] ;
+  wire \la_data_out_mprj[64] ;
+  wire \la_data_out_mprj[65] ;
+  wire \la_data_out_mprj[66] ;
+  wire \la_data_out_mprj[67] ;
+  wire \la_data_out_mprj[68] ;
+  wire \la_data_out_mprj[69] ;
+  wire \la_data_out_mprj[6] ;
+  wire \la_data_out_mprj[70] ;
+  wire \la_data_out_mprj[71] ;
+  wire \la_data_out_mprj[72] ;
+  wire \la_data_out_mprj[73] ;
+  wire \la_data_out_mprj[74] ;
+  wire \la_data_out_mprj[75] ;
+  wire \la_data_out_mprj[76] ;
+  wire \la_data_out_mprj[77] ;
+  wire \la_data_out_mprj[78] ;
+  wire \la_data_out_mprj[79] ;
+  wire \la_data_out_mprj[7] ;
+  wire \la_data_out_mprj[80] ;
+  wire \la_data_out_mprj[81] ;
+  wire \la_data_out_mprj[82] ;
+  wire \la_data_out_mprj[83] ;
+  wire \la_data_out_mprj[84] ;
+  wire \la_data_out_mprj[85] ;
+  wire \la_data_out_mprj[86] ;
+  wire \la_data_out_mprj[87] ;
+  wire \la_data_out_mprj[88] ;
+  wire \la_data_out_mprj[89] ;
+  wire \la_data_out_mprj[8] ;
+  wire \la_data_out_mprj[90] ;
+  wire \la_data_out_mprj[91] ;
+  wire \la_data_out_mprj[92] ;
+  wire \la_data_out_mprj[93] ;
+  wire \la_data_out_mprj[94] ;
+  wire \la_data_out_mprj[95] ;
+  wire \la_data_out_mprj[96] ;
+  wire \la_data_out_mprj[97] ;
+  wire \la_data_out_mprj[98] ;
+  wire \la_data_out_mprj[99] ;
+  wire \la_data_out_mprj[9] ;
+  wire \la_data_out_user[0] ;
+  wire \la_data_out_user[100] ;
+  wire \la_data_out_user[101] ;
+  wire \la_data_out_user[102] ;
+  wire \la_data_out_user[103] ;
+  wire \la_data_out_user[104] ;
+  wire \la_data_out_user[105] ;
+  wire \la_data_out_user[106] ;
+  wire \la_data_out_user[107] ;
+  wire \la_data_out_user[108] ;
+  wire \la_data_out_user[109] ;
+  wire \la_data_out_user[10] ;
+  wire \la_data_out_user[110] ;
+  wire \la_data_out_user[111] ;
+  wire \la_data_out_user[112] ;
+  wire \la_data_out_user[113] ;
+  wire \la_data_out_user[114] ;
+  wire \la_data_out_user[115] ;
+  wire \la_data_out_user[116] ;
+  wire \la_data_out_user[117] ;
+  wire \la_data_out_user[118] ;
+  wire \la_data_out_user[119] ;
+  wire \la_data_out_user[11] ;
+  wire \la_data_out_user[120] ;
+  wire \la_data_out_user[121] ;
+  wire \la_data_out_user[122] ;
+  wire \la_data_out_user[123] ;
+  wire \la_data_out_user[124] ;
+  wire \la_data_out_user[125] ;
+  wire \la_data_out_user[126] ;
+  wire \la_data_out_user[127] ;
+  wire \la_data_out_user[12] ;
+  wire \la_data_out_user[13] ;
+  wire \la_data_out_user[14] ;
+  wire \la_data_out_user[15] ;
+  wire \la_data_out_user[16] ;
+  wire \la_data_out_user[17] ;
+  wire \la_data_out_user[18] ;
+  wire \la_data_out_user[19] ;
+  wire \la_data_out_user[1] ;
+  wire \la_data_out_user[20] ;
+  wire \la_data_out_user[21] ;
+  wire \la_data_out_user[22] ;
+  wire \la_data_out_user[23] ;
+  wire \la_data_out_user[24] ;
+  wire \la_data_out_user[25] ;
+  wire \la_data_out_user[26] ;
+  wire \la_data_out_user[27] ;
+  wire \la_data_out_user[28] ;
+  wire \la_data_out_user[29] ;
+  wire \la_data_out_user[2] ;
+  wire \la_data_out_user[30] ;
+  wire \la_data_out_user[31] ;
+  wire \la_data_out_user[32] ;
+  wire \la_data_out_user[33] ;
+  wire \la_data_out_user[34] ;
+  wire \la_data_out_user[35] ;
+  wire \la_data_out_user[36] ;
+  wire \la_data_out_user[37] ;
+  wire \la_data_out_user[38] ;
+  wire \la_data_out_user[39] ;
+  wire \la_data_out_user[3] ;
+  wire \la_data_out_user[40] ;
+  wire \la_data_out_user[41] ;
+  wire \la_data_out_user[42] ;
+  wire \la_data_out_user[43] ;
+  wire \la_data_out_user[44] ;
+  wire \la_data_out_user[45] ;
+  wire \la_data_out_user[46] ;
+  wire \la_data_out_user[47] ;
+  wire \la_data_out_user[48] ;
+  wire \la_data_out_user[49] ;
+  wire \la_data_out_user[4] ;
+  wire \la_data_out_user[50] ;
+  wire \la_data_out_user[51] ;
+  wire \la_data_out_user[52] ;
+  wire \la_data_out_user[53] ;
+  wire \la_data_out_user[54] ;
+  wire \la_data_out_user[55] ;
+  wire \la_data_out_user[56] ;
+  wire \la_data_out_user[57] ;
+  wire \la_data_out_user[58] ;
+  wire \la_data_out_user[59] ;
+  wire \la_data_out_user[5] ;
+  wire \la_data_out_user[60] ;
+  wire \la_data_out_user[61] ;
+  wire \la_data_out_user[62] ;
+  wire \la_data_out_user[63] ;
+  wire \la_data_out_user[64] ;
+  wire \la_data_out_user[65] ;
+  wire \la_data_out_user[66] ;
+  wire \la_data_out_user[67] ;
+  wire \la_data_out_user[68] ;
+  wire \la_data_out_user[69] ;
+  wire \la_data_out_user[6] ;
+  wire \la_data_out_user[70] ;
+  wire \la_data_out_user[71] ;
+  wire \la_data_out_user[72] ;
+  wire \la_data_out_user[73] ;
+  wire \la_data_out_user[74] ;
+  wire \la_data_out_user[75] ;
+  wire \la_data_out_user[76] ;
+  wire \la_data_out_user[77] ;
+  wire \la_data_out_user[78] ;
+  wire \la_data_out_user[79] ;
+  wire \la_data_out_user[7] ;
+  wire \la_data_out_user[80] ;
+  wire \la_data_out_user[81] ;
+  wire \la_data_out_user[82] ;
+  wire \la_data_out_user[83] ;
+  wire \la_data_out_user[84] ;
+  wire \la_data_out_user[85] ;
+  wire \la_data_out_user[86] ;
+  wire \la_data_out_user[87] ;
+  wire \la_data_out_user[88] ;
+  wire \la_data_out_user[89] ;
+  wire \la_data_out_user[8] ;
+  wire \la_data_out_user[90] ;
+  wire \la_data_out_user[91] ;
+  wire \la_data_out_user[92] ;
+  wire \la_data_out_user[93] ;
+  wire \la_data_out_user[94] ;
+  wire \la_data_out_user[95] ;
+  wire \la_data_out_user[96] ;
+  wire \la_data_out_user[97] ;
+  wire \la_data_out_user[98] ;
+  wire \la_data_out_user[99] ;
+  wire \la_data_out_user[9] ;
+  wire \la_iena_mprj[0] ;
+  wire \la_iena_mprj[100] ;
+  wire \la_iena_mprj[101] ;
+  wire \la_iena_mprj[102] ;
+  wire \la_iena_mprj[103] ;
+  wire \la_iena_mprj[104] ;
+  wire \la_iena_mprj[105] ;
+  wire \la_iena_mprj[106] ;
+  wire \la_iena_mprj[107] ;
+  wire \la_iena_mprj[108] ;
+  wire \la_iena_mprj[109] ;
+  wire \la_iena_mprj[10] ;
+  wire \la_iena_mprj[110] ;
+  wire \la_iena_mprj[111] ;
+  wire \la_iena_mprj[112] ;
+  wire \la_iena_mprj[113] ;
+  wire \la_iena_mprj[114] ;
+  wire \la_iena_mprj[115] ;
+  wire \la_iena_mprj[116] ;
+  wire \la_iena_mprj[117] ;
+  wire \la_iena_mprj[118] ;
+  wire \la_iena_mprj[119] ;
+  wire \la_iena_mprj[11] ;
+  wire \la_iena_mprj[120] ;
+  wire \la_iena_mprj[121] ;
+  wire \la_iena_mprj[122] ;
+  wire \la_iena_mprj[123] ;
+  wire \la_iena_mprj[124] ;
+  wire \la_iena_mprj[125] ;
+  wire \la_iena_mprj[126] ;
+  wire \la_iena_mprj[127] ;
+  wire \la_iena_mprj[12] ;
+  wire \la_iena_mprj[13] ;
+  wire \la_iena_mprj[14] ;
+  wire \la_iena_mprj[15] ;
+  wire \la_iena_mprj[16] ;
+  wire \la_iena_mprj[17] ;
+  wire \la_iena_mprj[18] ;
+  wire \la_iena_mprj[19] ;
+  wire \la_iena_mprj[1] ;
+  wire \la_iena_mprj[20] ;
+  wire \la_iena_mprj[21] ;
+  wire \la_iena_mprj[22] ;
+  wire \la_iena_mprj[23] ;
+  wire \la_iena_mprj[24] ;
+  wire \la_iena_mprj[25] ;
+  wire \la_iena_mprj[26] ;
+  wire \la_iena_mprj[27] ;
+  wire \la_iena_mprj[28] ;
+  wire \la_iena_mprj[29] ;
+  wire \la_iena_mprj[2] ;
+  wire \la_iena_mprj[30] ;
+  wire \la_iena_mprj[31] ;
+  wire \la_iena_mprj[32] ;
+  wire \la_iena_mprj[33] ;
+  wire \la_iena_mprj[34] ;
+  wire \la_iena_mprj[35] ;
+  wire \la_iena_mprj[36] ;
+  wire \la_iena_mprj[37] ;
+  wire \la_iena_mprj[38] ;
+  wire \la_iena_mprj[39] ;
+  wire \la_iena_mprj[3] ;
+  wire \la_iena_mprj[40] ;
+  wire \la_iena_mprj[41] ;
+  wire \la_iena_mprj[42] ;
+  wire \la_iena_mprj[43] ;
+  wire \la_iena_mprj[44] ;
+  wire \la_iena_mprj[45] ;
+  wire \la_iena_mprj[46] ;
+  wire \la_iena_mprj[47] ;
+  wire \la_iena_mprj[48] ;
+  wire \la_iena_mprj[49] ;
+  wire \la_iena_mprj[4] ;
+  wire \la_iena_mprj[50] ;
+  wire \la_iena_mprj[51] ;
+  wire \la_iena_mprj[52] ;
+  wire \la_iena_mprj[53] ;
+  wire \la_iena_mprj[54] ;
+  wire \la_iena_mprj[55] ;
+  wire \la_iena_mprj[56] ;
+  wire \la_iena_mprj[57] ;
+  wire \la_iena_mprj[58] ;
+  wire \la_iena_mprj[59] ;
+  wire \la_iena_mprj[5] ;
+  wire \la_iena_mprj[60] ;
+  wire \la_iena_mprj[61] ;
+  wire \la_iena_mprj[62] ;
+  wire \la_iena_mprj[63] ;
+  wire \la_iena_mprj[64] ;
+  wire \la_iena_mprj[65] ;
+  wire \la_iena_mprj[66] ;
+  wire \la_iena_mprj[67] ;
+  wire \la_iena_mprj[68] ;
+  wire \la_iena_mprj[69] ;
+  wire \la_iena_mprj[6] ;
+  wire \la_iena_mprj[70] ;
+  wire \la_iena_mprj[71] ;
+  wire \la_iena_mprj[72] ;
+  wire \la_iena_mprj[73] ;
+  wire \la_iena_mprj[74] ;
+  wire \la_iena_mprj[75] ;
+  wire \la_iena_mprj[76] ;
+  wire \la_iena_mprj[77] ;
+  wire \la_iena_mprj[78] ;
+  wire \la_iena_mprj[79] ;
+  wire \la_iena_mprj[7] ;
+  wire \la_iena_mprj[80] ;
+  wire \la_iena_mprj[81] ;
+  wire \la_iena_mprj[82] ;
+  wire \la_iena_mprj[83] ;
+  wire \la_iena_mprj[84] ;
+  wire \la_iena_mprj[85] ;
+  wire \la_iena_mprj[86] ;
+  wire \la_iena_mprj[87] ;
+  wire \la_iena_mprj[88] ;
+  wire \la_iena_mprj[89] ;
+  wire \la_iena_mprj[8] ;
+  wire \la_iena_mprj[90] ;
+  wire \la_iena_mprj[91] ;
+  wire \la_iena_mprj[92] ;
+  wire \la_iena_mprj[93] ;
+  wire \la_iena_mprj[94] ;
+  wire \la_iena_mprj[95] ;
+  wire \la_iena_mprj[96] ;
+  wire \la_iena_mprj[97] ;
+  wire \la_iena_mprj[98] ;
+  wire \la_iena_mprj[99] ;
+  wire \la_iena_mprj[9] ;
+  wire \la_oenb_mprj[0] ;
+  wire \la_oenb_mprj[100] ;
+  wire \la_oenb_mprj[101] ;
+  wire \la_oenb_mprj[102] ;
+  wire \la_oenb_mprj[103] ;
+  wire \la_oenb_mprj[104] ;
+  wire \la_oenb_mprj[105] ;
+  wire \la_oenb_mprj[106] ;
+  wire \la_oenb_mprj[107] ;
+  wire \la_oenb_mprj[108] ;
+  wire \la_oenb_mprj[109] ;
+  wire \la_oenb_mprj[10] ;
+  wire \la_oenb_mprj[110] ;
+  wire \la_oenb_mprj[111] ;
+  wire \la_oenb_mprj[112] ;
+  wire \la_oenb_mprj[113] ;
+  wire \la_oenb_mprj[114] ;
+  wire \la_oenb_mprj[115] ;
+  wire \la_oenb_mprj[116] ;
+  wire \la_oenb_mprj[117] ;
+  wire \la_oenb_mprj[118] ;
+  wire \la_oenb_mprj[119] ;
+  wire \la_oenb_mprj[11] ;
+  wire \la_oenb_mprj[120] ;
+  wire \la_oenb_mprj[121] ;
+  wire \la_oenb_mprj[122] ;
+  wire \la_oenb_mprj[123] ;
+  wire \la_oenb_mprj[124] ;
+  wire \la_oenb_mprj[125] ;
+  wire \la_oenb_mprj[126] ;
+  wire \la_oenb_mprj[127] ;
+  wire \la_oenb_mprj[12] ;
+  wire \la_oenb_mprj[13] ;
+  wire \la_oenb_mprj[14] ;
+  wire \la_oenb_mprj[15] ;
+  wire \la_oenb_mprj[16] ;
+  wire \la_oenb_mprj[17] ;
+  wire \la_oenb_mprj[18] ;
+  wire \la_oenb_mprj[19] ;
+  wire \la_oenb_mprj[1] ;
+  wire \la_oenb_mprj[20] ;
+  wire \la_oenb_mprj[21] ;
+  wire \la_oenb_mprj[22] ;
+  wire \la_oenb_mprj[23] ;
+  wire \la_oenb_mprj[24] ;
+  wire \la_oenb_mprj[25] ;
+  wire \la_oenb_mprj[26] ;
+  wire \la_oenb_mprj[27] ;
+  wire \la_oenb_mprj[28] ;
+  wire \la_oenb_mprj[29] ;
+  wire \la_oenb_mprj[2] ;
+  wire \la_oenb_mprj[30] ;
+  wire \la_oenb_mprj[31] ;
+  wire \la_oenb_mprj[32] ;
+  wire \la_oenb_mprj[33] ;
+  wire \la_oenb_mprj[34] ;
+  wire \la_oenb_mprj[35] ;
+  wire \la_oenb_mprj[36] ;
+  wire \la_oenb_mprj[37] ;
+  wire \la_oenb_mprj[38] ;
+  wire \la_oenb_mprj[39] ;
+  wire \la_oenb_mprj[3] ;
+  wire \la_oenb_mprj[40] ;
+  wire \la_oenb_mprj[41] ;
+  wire \la_oenb_mprj[42] ;
+  wire \la_oenb_mprj[43] ;
+  wire \la_oenb_mprj[44] ;
+  wire \la_oenb_mprj[45] ;
+  wire \la_oenb_mprj[46] ;
+  wire \la_oenb_mprj[47] ;
+  wire \la_oenb_mprj[48] ;
+  wire \la_oenb_mprj[49] ;
+  wire \la_oenb_mprj[4] ;
+  wire \la_oenb_mprj[50] ;
+  wire \la_oenb_mprj[51] ;
+  wire \la_oenb_mprj[52] ;
+  wire \la_oenb_mprj[53] ;
+  wire \la_oenb_mprj[54] ;
+  wire \la_oenb_mprj[55] ;
+  wire \la_oenb_mprj[56] ;
+  wire \la_oenb_mprj[57] ;
+  wire \la_oenb_mprj[58] ;
+  wire \la_oenb_mprj[59] ;
+  wire \la_oenb_mprj[5] ;
+  wire \la_oenb_mprj[60] ;
+  wire \la_oenb_mprj[61] ;
+  wire \la_oenb_mprj[62] ;
+  wire \la_oenb_mprj[63] ;
+  wire \la_oenb_mprj[64] ;
+  wire \la_oenb_mprj[65] ;
+  wire \la_oenb_mprj[66] ;
+  wire \la_oenb_mprj[67] ;
+  wire \la_oenb_mprj[68] ;
+  wire \la_oenb_mprj[69] ;
+  wire \la_oenb_mprj[6] ;
+  wire \la_oenb_mprj[70] ;
+  wire \la_oenb_mprj[71] ;
+  wire \la_oenb_mprj[72] ;
+  wire \la_oenb_mprj[73] ;
+  wire \la_oenb_mprj[74] ;
+  wire \la_oenb_mprj[75] ;
+  wire \la_oenb_mprj[76] ;
+  wire \la_oenb_mprj[77] ;
+  wire \la_oenb_mprj[78] ;
+  wire \la_oenb_mprj[79] ;
+  wire \la_oenb_mprj[7] ;
+  wire \la_oenb_mprj[80] ;
+  wire \la_oenb_mprj[81] ;
+  wire \la_oenb_mprj[82] ;
+  wire \la_oenb_mprj[83] ;
+  wire \la_oenb_mprj[84] ;
+  wire \la_oenb_mprj[85] ;
+  wire \la_oenb_mprj[86] ;
+  wire \la_oenb_mprj[87] ;
+  wire \la_oenb_mprj[88] ;
+  wire \la_oenb_mprj[89] ;
+  wire \la_oenb_mprj[8] ;
+  wire \la_oenb_mprj[90] ;
+  wire \la_oenb_mprj[91] ;
+  wire \la_oenb_mprj[92] ;
+  wire \la_oenb_mprj[93] ;
+  wire \la_oenb_mprj[94] ;
+  wire \la_oenb_mprj[95] ;
+  wire \la_oenb_mprj[96] ;
+  wire \la_oenb_mprj[97] ;
+  wire \la_oenb_mprj[98] ;
+  wire \la_oenb_mprj[99] ;
+  wire \la_oenb_mprj[9] ;
+  wire \la_oenb_user[0] ;
+  wire \la_oenb_user[100] ;
+  wire \la_oenb_user[101] ;
+  wire \la_oenb_user[102] ;
+  wire \la_oenb_user[103] ;
+  wire \la_oenb_user[104] ;
+  wire \la_oenb_user[105] ;
+  wire \la_oenb_user[106] ;
+  wire \la_oenb_user[107] ;
+  wire \la_oenb_user[108] ;
+  wire \la_oenb_user[109] ;
+  wire \la_oenb_user[10] ;
+  wire \la_oenb_user[110] ;
+  wire \la_oenb_user[111] ;
+  wire \la_oenb_user[112] ;
+  wire \la_oenb_user[113] ;
+  wire \la_oenb_user[114] ;
+  wire \la_oenb_user[115] ;
+  wire \la_oenb_user[116] ;
+  wire \la_oenb_user[117] ;
+  wire \la_oenb_user[118] ;
+  wire \la_oenb_user[119] ;
+  wire \la_oenb_user[11] ;
+  wire \la_oenb_user[120] ;
+  wire \la_oenb_user[121] ;
+  wire \la_oenb_user[122] ;
+  wire \la_oenb_user[123] ;
+  wire \la_oenb_user[124] ;
+  wire \la_oenb_user[125] ;
+  wire \la_oenb_user[126] ;
+  wire \la_oenb_user[127] ;
+  wire \la_oenb_user[12] ;
+  wire \la_oenb_user[13] ;
+  wire \la_oenb_user[14] ;
+  wire \la_oenb_user[15] ;
+  wire \la_oenb_user[16] ;
+  wire \la_oenb_user[17] ;
+  wire \la_oenb_user[18] ;
+  wire \la_oenb_user[19] ;
+  wire \la_oenb_user[1] ;
+  wire \la_oenb_user[20] ;
+  wire \la_oenb_user[21] ;
+  wire \la_oenb_user[22] ;
+  wire \la_oenb_user[23] ;
+  wire \la_oenb_user[24] ;
+  wire \la_oenb_user[25] ;
+  wire \la_oenb_user[26] ;
+  wire \la_oenb_user[27] ;
+  wire \la_oenb_user[28] ;
+  wire \la_oenb_user[29] ;
+  wire \la_oenb_user[2] ;
+  wire \la_oenb_user[30] ;
+  wire \la_oenb_user[31] ;
+  wire \la_oenb_user[32] ;
+  wire \la_oenb_user[33] ;
+  wire \la_oenb_user[34] ;
+  wire \la_oenb_user[35] ;
+  wire \la_oenb_user[36] ;
+  wire \la_oenb_user[37] ;
+  wire \la_oenb_user[38] ;
+  wire \la_oenb_user[39] ;
+  wire \la_oenb_user[3] ;
+  wire \la_oenb_user[40] ;
+  wire \la_oenb_user[41] ;
+  wire \la_oenb_user[42] ;
+  wire \la_oenb_user[43] ;
+  wire \la_oenb_user[44] ;
+  wire \la_oenb_user[45] ;
+  wire \la_oenb_user[46] ;
+  wire \la_oenb_user[47] ;
+  wire \la_oenb_user[48] ;
+  wire \la_oenb_user[49] ;
+  wire \la_oenb_user[4] ;
+  wire \la_oenb_user[50] ;
+  wire \la_oenb_user[51] ;
+  wire \la_oenb_user[52] ;
+  wire \la_oenb_user[53] ;
+  wire \la_oenb_user[54] ;
+  wire \la_oenb_user[55] ;
+  wire \la_oenb_user[56] ;
+  wire \la_oenb_user[57] ;
+  wire \la_oenb_user[58] ;
+  wire \la_oenb_user[59] ;
+  wire \la_oenb_user[5] ;
+  wire \la_oenb_user[60] ;
+  wire \la_oenb_user[61] ;
+  wire \la_oenb_user[62] ;
+  wire \la_oenb_user[63] ;
+  wire \la_oenb_user[64] ;
+  wire \la_oenb_user[65] ;
+  wire \la_oenb_user[66] ;
+  wire \la_oenb_user[67] ;
+  wire \la_oenb_user[68] ;
+  wire \la_oenb_user[69] ;
+  wire \la_oenb_user[6] ;
+  wire \la_oenb_user[70] ;
+  wire \la_oenb_user[71] ;
+  wire \la_oenb_user[72] ;
+  wire \la_oenb_user[73] ;
+  wire \la_oenb_user[74] ;
+  wire \la_oenb_user[75] ;
+  wire \la_oenb_user[76] ;
+  wire \la_oenb_user[77] ;
+  wire \la_oenb_user[78] ;
+  wire \la_oenb_user[79] ;
+  wire \la_oenb_user[7] ;
+  wire \la_oenb_user[80] ;
+  wire \la_oenb_user[81] ;
+  wire \la_oenb_user[82] ;
+  wire \la_oenb_user[83] ;
+  wire \la_oenb_user[84] ;
+  wire \la_oenb_user[85] ;
+  wire \la_oenb_user[86] ;
+  wire \la_oenb_user[87] ;
+  wire \la_oenb_user[88] ;
+  wire \la_oenb_user[89] ;
+  wire \la_oenb_user[8] ;
+  wire \la_oenb_user[90] ;
+  wire \la_oenb_user[91] ;
+  wire \la_oenb_user[92] ;
+  wire \la_oenb_user[93] ;
+  wire \la_oenb_user[94] ;
+  wire \la_oenb_user[95] ;
+  wire \la_oenb_user[96] ;
+  wire \la_oenb_user[97] ;
+  wire \la_oenb_user[98] ;
+  wire \la_oenb_user[99] ;
+  wire \la_oenb_user[9] ;
+  wire \mask_rev[0] ;
+  wire \mask_rev[10] ;
+  wire \mask_rev[11] ;
+  wire \mask_rev[12] ;
+  wire \mask_rev[13] ;
+  wire \mask_rev[14] ;
+  wire \mask_rev[15] ;
+  wire \mask_rev[16] ;
+  wire \mask_rev[17] ;
+  wire \mask_rev[18] ;
+  wire \mask_rev[19] ;
+  wire \mask_rev[1] ;
+  wire \mask_rev[20] ;
+  wire \mask_rev[21] ;
+  wire \mask_rev[22] ;
+  wire \mask_rev[23] ;
+  wire \mask_rev[24] ;
+  wire \mask_rev[25] ;
+  wire \mask_rev[26] ;
+  wire \mask_rev[27] ;
+  wire \mask_rev[28] ;
+  wire \mask_rev[29] ;
+  wire \mask_rev[2] ;
+  wire \mask_rev[30] ;
+  wire \mask_rev[31] ;
+  wire \mask_rev[3] ;
+  wire \mask_rev[4] ;
+  wire \mask_rev[5] ;
+  wire \mask_rev[6] ;
+  wire \mask_rev[7] ;
+  wire \mask_rev[8] ;
+  wire \mask_rev[9] ;
+  wire \mgmt_io_in[0] ;
+  wire \mgmt_io_in[10] ;
+  wire \mgmt_io_in[11] ;
+  wire \mgmt_io_in[12] ;
+  wire \mgmt_io_in[13] ;
+  wire \mgmt_io_in[14] ;
+  wire \mgmt_io_in[15] ;
+  wire \mgmt_io_in[16] ;
+  wire \mgmt_io_in[17] ;
+  wire \mgmt_io_in[18] ;
+  wire \mgmt_io_in[19] ;
+  wire \mgmt_io_in[1] ;
+  wire \mgmt_io_in[20] ;
+  wire \mgmt_io_in[21] ;
+  wire \mgmt_io_in[22] ;
+  wire \mgmt_io_in[23] ;
+  wire \mgmt_io_in[24] ;
+  wire \mgmt_io_in[25] ;
+  wire \mgmt_io_in[26] ;
+  wire \mgmt_io_in[27] ;
+  wire \mgmt_io_in[28] ;
+  wire \mgmt_io_in[29] ;
+  wire \mgmt_io_in[2] ;
+  wire \mgmt_io_in[30] ;
+  wire \mgmt_io_in[31] ;
+  wire \mgmt_io_in[32] ;
+  wire \mgmt_io_in[33] ;
+  wire \mgmt_io_in[34] ;
+  wire \mgmt_io_in[35] ;
+  wire \mgmt_io_in[36] ;
+  wire \mgmt_io_in[37] ;
+  wire \mgmt_io_in[3] ;
+  wire \mgmt_io_in[4] ;
+  wire \mgmt_io_in[5] ;
+  wire \mgmt_io_in[6] ;
+  wire \mgmt_io_in[7] ;
+  wire \mgmt_io_in[8] ;
+  wire \mgmt_io_in[9] ;
+  wire \mgmt_io_in_hk[0] ;
+  wire \mgmt_io_in_hk[10] ;
+  wire \mgmt_io_in_hk[11] ;
+  wire \mgmt_io_in_hk[12] ;
+  wire \mgmt_io_in_hk[13] ;
+  wire \mgmt_io_in_hk[14] ;
+  wire \mgmt_io_in_hk[15] ;
+  wire \mgmt_io_in_hk[16] ;
+  wire \mgmt_io_in_hk[17] ;
+  wire \mgmt_io_in_hk[18] ;
+  wire \mgmt_io_in_hk[19] ;
+  wire \mgmt_io_in_hk[1] ;
+  wire \mgmt_io_in_hk[20] ;
+  wire \mgmt_io_in_hk[21] ;
+  wire \mgmt_io_in_hk[22] ;
+  wire \mgmt_io_in_hk[23] ;
+  wire \mgmt_io_in_hk[24] ;
+  wire \mgmt_io_in_hk[25] ;
+  wire \mgmt_io_in_hk[26] ;
+  wire \mgmt_io_in_hk[27] ;
+  wire \mgmt_io_in_hk[28] ;
+  wire \mgmt_io_in_hk[29] ;
+  wire \mgmt_io_in_hk[2] ;
+  wire \mgmt_io_in_hk[30] ;
+  wire \mgmt_io_in_hk[31] ;
+  wire \mgmt_io_in_hk[32] ;
+  wire \mgmt_io_in_hk[33] ;
+  wire \mgmt_io_in_hk[34] ;
+  wire \mgmt_io_in_hk[35] ;
+  wire \mgmt_io_in_hk[36] ;
+  wire \mgmt_io_in_hk[37] ;
+  wire \mgmt_io_in_hk[3] ;
+  wire \mgmt_io_in_hk[4] ;
+  wire \mgmt_io_in_hk[5] ;
+  wire \mgmt_io_in_hk[6] ;
+  wire \mgmt_io_in_hk[7] ;
+  wire \mgmt_io_in_hk[8] ;
+  wire \mgmt_io_in_hk[9] ;
+  wire \mgmt_io_oeb[0] ;
+  wire \mgmt_io_oeb[10] ;
+  wire \mgmt_io_oeb[11] ;
+  wire \mgmt_io_oeb[12] ;
+  wire \mgmt_io_oeb[13] ;
+  wire \mgmt_io_oeb[14] ;
+  wire \mgmt_io_oeb[15] ;
+  wire \mgmt_io_oeb[16] ;
+  wire \mgmt_io_oeb[17] ;
+  wire \mgmt_io_oeb[18] ;
+  wire \mgmt_io_oeb[19] ;
+  wire \mgmt_io_oeb[1] ;
+  wire \mgmt_io_oeb[20] ;
+  wire \mgmt_io_oeb[21] ;
+  wire \mgmt_io_oeb[22] ;
+  wire \mgmt_io_oeb[23] ;
+  wire \mgmt_io_oeb[24] ;
+  wire \mgmt_io_oeb[25] ;
+  wire \mgmt_io_oeb[26] ;
+  wire \mgmt_io_oeb[27] ;
+  wire \mgmt_io_oeb[28] ;
+  wire \mgmt_io_oeb[29] ;
+  wire \mgmt_io_oeb[2] ;
+  wire \mgmt_io_oeb[30] ;
+  wire \mgmt_io_oeb[31] ;
+  wire \mgmt_io_oeb[32] ;
+  wire \mgmt_io_oeb[33] ;
+  wire \mgmt_io_oeb[34] ;
+  wire \mgmt_io_oeb[35] ;
+  wire \mgmt_io_oeb[36] ;
+  wire \mgmt_io_oeb[37] ;
+  wire \mgmt_io_oeb[3] ;
+  wire \mgmt_io_oeb[4] ;
+  wire \mgmt_io_oeb[5] ;
+  wire \mgmt_io_oeb[6] ;
+  wire \mgmt_io_oeb[7] ;
+  wire \mgmt_io_oeb[8] ;
+  wire \mgmt_io_oeb[9] ;
+  wire \mgmt_io_oeb_hk[0] ;
+  wire \mgmt_io_oeb_hk[10] ;
+  wire \mgmt_io_oeb_hk[11] ;
+  wire \mgmt_io_oeb_hk[12] ;
+  wire \mgmt_io_oeb_hk[13] ;
+  wire \mgmt_io_oeb_hk[14] ;
+  wire \mgmt_io_oeb_hk[15] ;
+  wire \mgmt_io_oeb_hk[16] ;
+  wire \mgmt_io_oeb_hk[17] ;
+  wire \mgmt_io_oeb_hk[18] ;
+  wire \mgmt_io_oeb_hk[19] ;
+  wire \mgmt_io_oeb_hk[1] ;
+  wire \mgmt_io_oeb_hk[20] ;
+  wire \mgmt_io_oeb_hk[21] ;
+  wire \mgmt_io_oeb_hk[22] ;
+  wire \mgmt_io_oeb_hk[23] ;
+  wire \mgmt_io_oeb_hk[24] ;
+  wire \mgmt_io_oeb_hk[25] ;
+  wire \mgmt_io_oeb_hk[26] ;
+  wire \mgmt_io_oeb_hk[27] ;
+  wire \mgmt_io_oeb_hk[28] ;
+  wire \mgmt_io_oeb_hk[29] ;
+  wire \mgmt_io_oeb_hk[2] ;
+  wire \mgmt_io_oeb_hk[30] ;
+  wire \mgmt_io_oeb_hk[31] ;
+  wire \mgmt_io_oeb_hk[32] ;
+  wire \mgmt_io_oeb_hk[33] ;
+  wire \mgmt_io_oeb_hk[34] ;
+  wire \mgmt_io_oeb_hk[35] ;
+  wire \mgmt_io_oeb_hk[36] ;
+  wire \mgmt_io_oeb_hk[37] ;
+  wire \mgmt_io_oeb_hk[3] ;
+  wire \mgmt_io_oeb_hk[4] ;
+  wire \mgmt_io_oeb_hk[5] ;
+  wire \mgmt_io_oeb_hk[6] ;
+  wire \mgmt_io_oeb_hk[7] ;
+  wire \mgmt_io_oeb_hk[8] ;
+  wire \mgmt_io_oeb_hk[9] ;
+  wire \mgmt_io_out[0] ;
+  wire \mgmt_io_out[10] ;
+  wire \mgmt_io_out[11] ;
+  wire \mgmt_io_out[12] ;
+  wire \mgmt_io_out[13] ;
+  wire \mgmt_io_out[14] ;
+  wire \mgmt_io_out[15] ;
+  wire \mgmt_io_out[16] ;
+  wire \mgmt_io_out[17] ;
+  wire \mgmt_io_out[18] ;
+  wire \mgmt_io_out[19] ;
+  wire \mgmt_io_out[1] ;
+  wire \mgmt_io_out[20] ;
+  wire \mgmt_io_out[21] ;
+  wire \mgmt_io_out[22] ;
+  wire \mgmt_io_out[23] ;
+  wire \mgmt_io_out[24] ;
+  wire \mgmt_io_out[25] ;
+  wire \mgmt_io_out[26] ;
+  wire \mgmt_io_out[27] ;
+  wire \mgmt_io_out[28] ;
+  wire \mgmt_io_out[29] ;
+  wire \mgmt_io_out[2] ;
+  wire \mgmt_io_out[30] ;
+  wire \mgmt_io_out[31] ;
+  wire \mgmt_io_out[32] ;
+  wire \mgmt_io_out[33] ;
+  wire \mgmt_io_out[34] ;
+  wire \mgmt_io_out[35] ;
+  wire \mgmt_io_out[36] ;
+  wire \mgmt_io_out[37] ;
+  wire \mgmt_io_out[3] ;
+  wire \mgmt_io_out[4] ;
+  wire \mgmt_io_out[5] ;
+  wire \mgmt_io_out[6] ;
+  wire \mgmt_io_out[7] ;
+  wire \mgmt_io_out[8] ;
+  wire \mgmt_io_out[9] ;
+  wire \mgmt_io_out_hk[0] ;
+  wire \mgmt_io_out_hk[10] ;
+  wire \mgmt_io_out_hk[11] ;
+  wire \mgmt_io_out_hk[12] ;
+  wire \mgmt_io_out_hk[13] ;
+  wire \mgmt_io_out_hk[14] ;
+  wire \mgmt_io_out_hk[15] ;
+  wire \mgmt_io_out_hk[16] ;
+  wire \mgmt_io_out_hk[17] ;
+  wire \mgmt_io_out_hk[18] ;
+  wire \mgmt_io_out_hk[19] ;
+  wire \mgmt_io_out_hk[1] ;
+  wire \mgmt_io_out_hk[20] ;
+  wire \mgmt_io_out_hk[21] ;
+  wire \mgmt_io_out_hk[22] ;
+  wire \mgmt_io_out_hk[23] ;
+  wire \mgmt_io_out_hk[24] ;
+  wire \mgmt_io_out_hk[25] ;
+  wire \mgmt_io_out_hk[26] ;
+  wire \mgmt_io_out_hk[27] ;
+  wire \mgmt_io_out_hk[28] ;
+  wire \mgmt_io_out_hk[29] ;
+  wire \mgmt_io_out_hk[2] ;
+  wire \mgmt_io_out_hk[30] ;
+  wire \mgmt_io_out_hk[31] ;
+  wire \mgmt_io_out_hk[32] ;
+  wire \mgmt_io_out_hk[33] ;
+  wire \mgmt_io_out_hk[34] ;
+  wire \mgmt_io_out_hk[35] ;
+  wire \mgmt_io_out_hk[36] ;
+  wire \mgmt_io_out_hk[37] ;
+  wire \mgmt_io_out_hk[3] ;
+  wire \mgmt_io_out_hk[4] ;
+  wire \mgmt_io_out_hk[5] ;
+  wire \mgmt_io_out_hk[6] ;
+  wire \mgmt_io_out_hk[7] ;
+  wire \mgmt_io_out_hk[8] ;
+  wire \mgmt_io_out_hk[9] ;
+  wire mprj2_vcc_pwrgood;
+  wire mprj2_vdd_pwrgood;
+  wire mprj_ack_i_core;
+  wire mprj_ack_i_user;
+  wire \mprj_adr_o_core[0] ;
+  wire \mprj_adr_o_core[10] ;
+  wire \mprj_adr_o_core[11] ;
+  wire \mprj_adr_o_core[12] ;
+  wire \mprj_adr_o_core[13] ;
+  wire \mprj_adr_o_core[14] ;
+  wire \mprj_adr_o_core[15] ;
+  wire \mprj_adr_o_core[16] ;
+  wire \mprj_adr_o_core[17] ;
+  wire \mprj_adr_o_core[18] ;
+  wire \mprj_adr_o_core[19] ;
+  wire \mprj_adr_o_core[1] ;
+  wire \mprj_adr_o_core[20] ;
+  wire \mprj_adr_o_core[21] ;
+  wire \mprj_adr_o_core[22] ;
+  wire \mprj_adr_o_core[23] ;
+  wire \mprj_adr_o_core[24] ;
+  wire \mprj_adr_o_core[25] ;
+  wire \mprj_adr_o_core[26] ;
+  wire \mprj_adr_o_core[27] ;
+  wire \mprj_adr_o_core[28] ;
+  wire \mprj_adr_o_core[29] ;
+  wire \mprj_adr_o_core[2] ;
+  wire \mprj_adr_o_core[30] ;
+  wire \mprj_adr_o_core[31] ;
+  wire \mprj_adr_o_core[3] ;
+  wire \mprj_adr_o_core[4] ;
+  wire \mprj_adr_o_core[5] ;
+  wire \mprj_adr_o_core[6] ;
+  wire \mprj_adr_o_core[7] ;
+  wire \mprj_adr_o_core[8] ;
+  wire \mprj_adr_o_core[9] ;
+  wire \mprj_adr_o_user[0] ;
+  wire \mprj_adr_o_user[10] ;
+  wire \mprj_adr_o_user[11] ;
+  wire \mprj_adr_o_user[12] ;
+  wire \mprj_adr_o_user[13] ;
+  wire \mprj_adr_o_user[14] ;
+  wire \mprj_adr_o_user[15] ;
+  wire \mprj_adr_o_user[16] ;
+  wire \mprj_adr_o_user[17] ;
+  wire \mprj_adr_o_user[18] ;
+  wire \mprj_adr_o_user[19] ;
+  wire \mprj_adr_o_user[1] ;
+  wire \mprj_adr_o_user[20] ;
+  wire \mprj_adr_o_user[21] ;
+  wire \mprj_adr_o_user[22] ;
+  wire \mprj_adr_o_user[23] ;
+  wire \mprj_adr_o_user[24] ;
+  wire \mprj_adr_o_user[25] ;
+  wire \mprj_adr_o_user[26] ;
+  wire \mprj_adr_o_user[27] ;
+  wire \mprj_adr_o_user[28] ;
+  wire \mprj_adr_o_user[29] ;
+  wire \mprj_adr_o_user[2] ;
+  wire \mprj_adr_o_user[30] ;
+  wire \mprj_adr_o_user[31] ;
+  wire \mprj_adr_o_user[3] ;
+  wire \mprj_adr_o_user[4] ;
+  wire \mprj_adr_o_user[5] ;
+  wire \mprj_adr_o_user[6] ;
+  wire \mprj_adr_o_user[7] ;
+  wire \mprj_adr_o_user[8] ;
+  wire \mprj_adr_o_user[9] ;
+  wire mprj_clock;
+  wire mprj_clock2;
+  wire mprj_cyc_o_core;
+  wire mprj_cyc_o_user;
+  wire \mprj_dat_i_core[0] ;
+  wire \mprj_dat_i_core[10] ;
+  wire \mprj_dat_i_core[11] ;
+  wire \mprj_dat_i_core[12] ;
+  wire \mprj_dat_i_core[13] ;
+  wire \mprj_dat_i_core[14] ;
+  wire \mprj_dat_i_core[15] ;
+  wire \mprj_dat_i_core[16] ;
+  wire \mprj_dat_i_core[17] ;
+  wire \mprj_dat_i_core[18] ;
+  wire \mprj_dat_i_core[19] ;
+  wire \mprj_dat_i_core[1] ;
+  wire \mprj_dat_i_core[20] ;
+  wire \mprj_dat_i_core[21] ;
+  wire \mprj_dat_i_core[22] ;
+  wire \mprj_dat_i_core[23] ;
+  wire \mprj_dat_i_core[24] ;
+  wire \mprj_dat_i_core[25] ;
+  wire \mprj_dat_i_core[26] ;
+  wire \mprj_dat_i_core[27] ;
+  wire \mprj_dat_i_core[28] ;
+  wire \mprj_dat_i_core[29] ;
+  wire \mprj_dat_i_core[2] ;
+  wire \mprj_dat_i_core[30] ;
+  wire \mprj_dat_i_core[31] ;
+  wire \mprj_dat_i_core[3] ;
+  wire \mprj_dat_i_core[4] ;
+  wire \mprj_dat_i_core[5] ;
+  wire \mprj_dat_i_core[6] ;
+  wire \mprj_dat_i_core[7] ;
+  wire \mprj_dat_i_core[8] ;
+  wire \mprj_dat_i_core[9] ;
+  wire \mprj_dat_i_user[0] ;
+  wire \mprj_dat_i_user[10] ;
+  wire \mprj_dat_i_user[11] ;
+  wire \mprj_dat_i_user[12] ;
+  wire \mprj_dat_i_user[13] ;
+  wire \mprj_dat_i_user[14] ;
+  wire \mprj_dat_i_user[15] ;
+  wire \mprj_dat_i_user[16] ;
+  wire \mprj_dat_i_user[17] ;
+  wire \mprj_dat_i_user[18] ;
+  wire \mprj_dat_i_user[19] ;
+  wire \mprj_dat_i_user[1] ;
+  wire \mprj_dat_i_user[20] ;
+  wire \mprj_dat_i_user[21] ;
+  wire \mprj_dat_i_user[22] ;
+  wire \mprj_dat_i_user[23] ;
+  wire \mprj_dat_i_user[24] ;
+  wire \mprj_dat_i_user[25] ;
+  wire \mprj_dat_i_user[26] ;
+  wire \mprj_dat_i_user[27] ;
+  wire \mprj_dat_i_user[28] ;
+  wire \mprj_dat_i_user[29] ;
+  wire \mprj_dat_i_user[2] ;
+  wire \mprj_dat_i_user[30] ;
+  wire \mprj_dat_i_user[31] ;
+  wire \mprj_dat_i_user[3] ;
+  wire \mprj_dat_i_user[4] ;
+  wire \mprj_dat_i_user[5] ;
+  wire \mprj_dat_i_user[6] ;
+  wire \mprj_dat_i_user[7] ;
+  wire \mprj_dat_i_user[8] ;
+  wire \mprj_dat_i_user[9] ;
+  wire \mprj_dat_o_core[0] ;
+  wire \mprj_dat_o_core[10] ;
+  wire \mprj_dat_o_core[11] ;
+  wire \mprj_dat_o_core[12] ;
+  wire \mprj_dat_o_core[13] ;
+  wire \mprj_dat_o_core[14] ;
+  wire \mprj_dat_o_core[15] ;
+  wire \mprj_dat_o_core[16] ;
+  wire \mprj_dat_o_core[17] ;
+  wire \mprj_dat_o_core[18] ;
+  wire \mprj_dat_o_core[19] ;
+  wire \mprj_dat_o_core[1] ;
+  wire \mprj_dat_o_core[20] ;
+  wire \mprj_dat_o_core[21] ;
+  wire \mprj_dat_o_core[22] ;
+  wire \mprj_dat_o_core[23] ;
+  wire \mprj_dat_o_core[24] ;
+  wire \mprj_dat_o_core[25] ;
+  wire \mprj_dat_o_core[26] ;
+  wire \mprj_dat_o_core[27] ;
+  wire \mprj_dat_o_core[28] ;
+  wire \mprj_dat_o_core[29] ;
+  wire \mprj_dat_o_core[2] ;
+  wire \mprj_dat_o_core[30] ;
+  wire \mprj_dat_o_core[31] ;
+  wire \mprj_dat_o_core[3] ;
+  wire \mprj_dat_o_core[4] ;
+  wire \mprj_dat_o_core[5] ;
+  wire \mprj_dat_o_core[6] ;
+  wire \mprj_dat_o_core[7] ;
+  wire \mprj_dat_o_core[8] ;
+  wire \mprj_dat_o_core[9] ;
+  wire \mprj_dat_o_user[0] ;
+  wire \mprj_dat_o_user[10] ;
+  wire \mprj_dat_o_user[11] ;
+  wire \mprj_dat_o_user[12] ;
+  wire \mprj_dat_o_user[13] ;
+  wire \mprj_dat_o_user[14] ;
+  wire \mprj_dat_o_user[15] ;
+  wire \mprj_dat_o_user[16] ;
+  wire \mprj_dat_o_user[17] ;
+  wire \mprj_dat_o_user[18] ;
+  wire \mprj_dat_o_user[19] ;
+  wire \mprj_dat_o_user[1] ;
+  wire \mprj_dat_o_user[20] ;
+  wire \mprj_dat_o_user[21] ;
+  wire \mprj_dat_o_user[22] ;
+  wire \mprj_dat_o_user[23] ;
+  wire \mprj_dat_o_user[24] ;
+  wire \mprj_dat_o_user[25] ;
+  wire \mprj_dat_o_user[26] ;
+  wire \mprj_dat_o_user[27] ;
+  wire \mprj_dat_o_user[28] ;
+  wire \mprj_dat_o_user[29] ;
+  wire \mprj_dat_o_user[2] ;
+  wire \mprj_dat_o_user[30] ;
+  wire \mprj_dat_o_user[31] ;
+  wire \mprj_dat_o_user[3] ;
+  wire \mprj_dat_o_user[4] ;
+  wire \mprj_dat_o_user[5] ;
+  wire \mprj_dat_o_user[6] ;
+  wire \mprj_dat_o_user[7] ;
+  wire \mprj_dat_o_user[8] ;
+  wire \mprj_dat_o_user[9] ;
+  wire mprj_iena_wb;
+  inout [37:0] mprj_io;
+  wire \mprj_io_analog_en[0] ;
+  wire \mprj_io_analog_en[10] ;
+  wire \mprj_io_analog_en[11] ;
+  wire \mprj_io_analog_en[12] ;
+  wire \mprj_io_analog_en[13] ;
+  wire \mprj_io_analog_en[14] ;
+  wire \mprj_io_analog_en[15] ;
+  wire \mprj_io_analog_en[16] ;
+  wire \mprj_io_analog_en[17] ;
+  wire \mprj_io_analog_en[18] ;
+  wire \mprj_io_analog_en[19] ;
+  wire \mprj_io_analog_en[1] ;
+  wire \mprj_io_analog_en[20] ;
+  wire \mprj_io_analog_en[21] ;
+  wire \mprj_io_analog_en[22] ;
+  wire \mprj_io_analog_en[23] ;
+  wire \mprj_io_analog_en[24] ;
+  wire \mprj_io_analog_en[25] ;
+  wire \mprj_io_analog_en[26] ;
+  wire \mprj_io_analog_en[27] ;
+  wire \mprj_io_analog_en[28] ;
+  wire \mprj_io_analog_en[29] ;
+  wire \mprj_io_analog_en[2] ;
+  wire \mprj_io_analog_en[30] ;
+  wire \mprj_io_analog_en[31] ;
+  wire \mprj_io_analog_en[32] ;
+  wire \mprj_io_analog_en[33] ;
+  wire \mprj_io_analog_en[34] ;
+  wire \mprj_io_analog_en[35] ;
+  wire \mprj_io_analog_en[36] ;
+  wire \mprj_io_analog_en[37] ;
+  wire \mprj_io_analog_en[3] ;
+  wire \mprj_io_analog_en[4] ;
+  wire \mprj_io_analog_en[5] ;
+  wire \mprj_io_analog_en[6] ;
+  wire \mprj_io_analog_en[7] ;
+  wire \mprj_io_analog_en[8] ;
+  wire \mprj_io_analog_en[9] ;
+  wire \mprj_io_analog_pol[0] ;
+  wire \mprj_io_analog_pol[10] ;
+  wire \mprj_io_analog_pol[11] ;
+  wire \mprj_io_analog_pol[12] ;
+  wire \mprj_io_analog_pol[13] ;
+  wire \mprj_io_analog_pol[14] ;
+  wire \mprj_io_analog_pol[15] ;
+  wire \mprj_io_analog_pol[16] ;
+  wire \mprj_io_analog_pol[17] ;
+  wire \mprj_io_analog_pol[18] ;
+  wire \mprj_io_analog_pol[19] ;
+  wire \mprj_io_analog_pol[1] ;
+  wire \mprj_io_analog_pol[20] ;
+  wire \mprj_io_analog_pol[21] ;
+  wire \mprj_io_analog_pol[22] ;
+  wire \mprj_io_analog_pol[23] ;
+  wire \mprj_io_analog_pol[24] ;
+  wire \mprj_io_analog_pol[25] ;
+  wire \mprj_io_analog_pol[26] ;
+  wire \mprj_io_analog_pol[27] ;
+  wire \mprj_io_analog_pol[28] ;
+  wire \mprj_io_analog_pol[29] ;
+  wire \mprj_io_analog_pol[2] ;
+  wire \mprj_io_analog_pol[30] ;
+  wire \mprj_io_analog_pol[31] ;
+  wire \mprj_io_analog_pol[32] ;
+  wire \mprj_io_analog_pol[33] ;
+  wire \mprj_io_analog_pol[34] ;
+  wire \mprj_io_analog_pol[35] ;
+  wire \mprj_io_analog_pol[36] ;
+  wire \mprj_io_analog_pol[37] ;
+  wire \mprj_io_analog_pol[3] ;
+  wire \mprj_io_analog_pol[4] ;
+  wire \mprj_io_analog_pol[5] ;
+  wire \mprj_io_analog_pol[6] ;
+  wire \mprj_io_analog_pol[7] ;
+  wire \mprj_io_analog_pol[8] ;
+  wire \mprj_io_analog_pol[9] ;
+  wire \mprj_io_analog_sel[0] ;
+  wire \mprj_io_analog_sel[10] ;
+  wire \mprj_io_analog_sel[11] ;
+  wire \mprj_io_analog_sel[12] ;
+  wire \mprj_io_analog_sel[13] ;
+  wire \mprj_io_analog_sel[14] ;
+  wire \mprj_io_analog_sel[15] ;
+  wire \mprj_io_analog_sel[16] ;
+  wire \mprj_io_analog_sel[17] ;
+  wire \mprj_io_analog_sel[18] ;
+  wire \mprj_io_analog_sel[19] ;
+  wire \mprj_io_analog_sel[1] ;
+  wire \mprj_io_analog_sel[20] ;
+  wire \mprj_io_analog_sel[21] ;
+  wire \mprj_io_analog_sel[22] ;
+  wire \mprj_io_analog_sel[23] ;
+  wire \mprj_io_analog_sel[24] ;
+  wire \mprj_io_analog_sel[25] ;
+  wire \mprj_io_analog_sel[26] ;
+  wire \mprj_io_analog_sel[27] ;
+  wire \mprj_io_analog_sel[28] ;
+  wire \mprj_io_analog_sel[29] ;
+  wire \mprj_io_analog_sel[2] ;
+  wire \mprj_io_analog_sel[30] ;
+  wire \mprj_io_analog_sel[31] ;
+  wire \mprj_io_analog_sel[32] ;
+  wire \mprj_io_analog_sel[33] ;
+  wire \mprj_io_analog_sel[34] ;
+  wire \mprj_io_analog_sel[35] ;
+  wire \mprj_io_analog_sel[36] ;
+  wire \mprj_io_analog_sel[37] ;
+  wire \mprj_io_analog_sel[3] ;
+  wire \mprj_io_analog_sel[4] ;
+  wire \mprj_io_analog_sel[5] ;
+  wire \mprj_io_analog_sel[6] ;
+  wire \mprj_io_analog_sel[7] ;
+  wire \mprj_io_analog_sel[8] ;
+  wire \mprj_io_analog_sel[9] ;
+  wire \mprj_io_dm[0] ;
+  wire \mprj_io_dm[100] ;
+  wire \mprj_io_dm[101] ;
+  wire \mprj_io_dm[102] ;
+  wire \mprj_io_dm[103] ;
+  wire \mprj_io_dm[104] ;
+  wire \mprj_io_dm[105] ;
+  wire \mprj_io_dm[106] ;
+  wire \mprj_io_dm[107] ;
+  wire \mprj_io_dm[108] ;
+  wire \mprj_io_dm[109] ;
+  wire \mprj_io_dm[10] ;
+  wire \mprj_io_dm[110] ;
+  wire \mprj_io_dm[111] ;
+  wire \mprj_io_dm[112] ;
+  wire \mprj_io_dm[113] ;
+  wire \mprj_io_dm[11] ;
+  wire \mprj_io_dm[12] ;
+  wire \mprj_io_dm[13] ;
+  wire \mprj_io_dm[14] ;
+  wire \mprj_io_dm[15] ;
+  wire \mprj_io_dm[16] ;
+  wire \mprj_io_dm[17] ;
+  wire \mprj_io_dm[18] ;
+  wire \mprj_io_dm[19] ;
+  wire \mprj_io_dm[1] ;
+  wire \mprj_io_dm[20] ;
+  wire \mprj_io_dm[21] ;
+  wire \mprj_io_dm[22] ;
+  wire \mprj_io_dm[23] ;
+  wire \mprj_io_dm[24] ;
+  wire \mprj_io_dm[25] ;
+  wire \mprj_io_dm[26] ;
+  wire \mprj_io_dm[27] ;
+  wire \mprj_io_dm[28] ;
+  wire \mprj_io_dm[29] ;
+  wire \mprj_io_dm[2] ;
+  wire \mprj_io_dm[30] ;
+  wire \mprj_io_dm[31] ;
+  wire \mprj_io_dm[32] ;
+  wire \mprj_io_dm[33] ;
+  wire \mprj_io_dm[34] ;
+  wire \mprj_io_dm[35] ;
+  wire \mprj_io_dm[36] ;
+  wire \mprj_io_dm[37] ;
+  wire \mprj_io_dm[38] ;
+  wire \mprj_io_dm[39] ;
+  wire \mprj_io_dm[3] ;
+  wire \mprj_io_dm[40] ;
+  wire \mprj_io_dm[41] ;
+  wire \mprj_io_dm[42] ;
+  wire \mprj_io_dm[43] ;
+  wire \mprj_io_dm[44] ;
+  wire \mprj_io_dm[45] ;
+  wire \mprj_io_dm[46] ;
+  wire \mprj_io_dm[47] ;
+  wire \mprj_io_dm[48] ;
+  wire \mprj_io_dm[49] ;
+  wire \mprj_io_dm[4] ;
+  wire \mprj_io_dm[50] ;
+  wire \mprj_io_dm[51] ;
+  wire \mprj_io_dm[52] ;
+  wire \mprj_io_dm[53] ;
+  wire \mprj_io_dm[54] ;
+  wire \mprj_io_dm[55] ;
+  wire \mprj_io_dm[56] ;
+  wire \mprj_io_dm[57] ;
+  wire \mprj_io_dm[58] ;
+  wire \mprj_io_dm[59] ;
+  wire \mprj_io_dm[5] ;
+  wire \mprj_io_dm[60] ;
+  wire \mprj_io_dm[61] ;
+  wire \mprj_io_dm[62] ;
+  wire \mprj_io_dm[63] ;
+  wire \mprj_io_dm[64] ;
+  wire \mprj_io_dm[65] ;
+  wire \mprj_io_dm[66] ;
+  wire \mprj_io_dm[67] ;
+  wire \mprj_io_dm[68] ;
+  wire \mprj_io_dm[69] ;
+  wire \mprj_io_dm[6] ;
+  wire \mprj_io_dm[70] ;
+  wire \mprj_io_dm[71] ;
+  wire \mprj_io_dm[72] ;
+  wire \mprj_io_dm[73] ;
+  wire \mprj_io_dm[74] ;
+  wire \mprj_io_dm[75] ;
+  wire \mprj_io_dm[76] ;
+  wire \mprj_io_dm[77] ;
+  wire \mprj_io_dm[78] ;
+  wire \mprj_io_dm[79] ;
+  wire \mprj_io_dm[7] ;
+  wire \mprj_io_dm[80] ;
+  wire \mprj_io_dm[81] ;
+  wire \mprj_io_dm[82] ;
+  wire \mprj_io_dm[83] ;
+  wire \mprj_io_dm[84] ;
+  wire \mprj_io_dm[85] ;
+  wire \mprj_io_dm[86] ;
+  wire \mprj_io_dm[87] ;
+  wire \mprj_io_dm[88] ;
+  wire \mprj_io_dm[89] ;
+  wire \mprj_io_dm[8] ;
+  wire \mprj_io_dm[90] ;
+  wire \mprj_io_dm[91] ;
+  wire \mprj_io_dm[92] ;
+  wire \mprj_io_dm[93] ;
+  wire \mprj_io_dm[94] ;
+  wire \mprj_io_dm[95] ;
+  wire \mprj_io_dm[96] ;
+  wire \mprj_io_dm[97] ;
+  wire \mprj_io_dm[98] ;
+  wire \mprj_io_dm[99] ;
+  wire \mprj_io_dm[9] ;
+  wire \mprj_io_holdover[0] ;
+  wire \mprj_io_holdover[10] ;
+  wire \mprj_io_holdover[11] ;
+  wire \mprj_io_holdover[12] ;
+  wire \mprj_io_holdover[13] ;
+  wire \mprj_io_holdover[14] ;
+  wire \mprj_io_holdover[15] ;
+  wire \mprj_io_holdover[16] ;
+  wire \mprj_io_holdover[17] ;
+  wire \mprj_io_holdover[18] ;
+  wire \mprj_io_holdover[19] ;
+  wire \mprj_io_holdover[1] ;
+  wire \mprj_io_holdover[20] ;
+  wire \mprj_io_holdover[21] ;
+  wire \mprj_io_holdover[22] ;
+  wire \mprj_io_holdover[23] ;
+  wire \mprj_io_holdover[24] ;
+  wire \mprj_io_holdover[25] ;
+  wire \mprj_io_holdover[26] ;
+  wire \mprj_io_holdover[27] ;
+  wire \mprj_io_holdover[28] ;
+  wire \mprj_io_holdover[29] ;
+  wire \mprj_io_holdover[2] ;
+  wire \mprj_io_holdover[30] ;
+  wire \mprj_io_holdover[31] ;
+  wire \mprj_io_holdover[32] ;
+  wire \mprj_io_holdover[33] ;
+  wire \mprj_io_holdover[34] ;
+  wire \mprj_io_holdover[35] ;
+  wire \mprj_io_holdover[36] ;
+  wire \mprj_io_holdover[37] ;
+  wire \mprj_io_holdover[3] ;
+  wire \mprj_io_holdover[4] ;
+  wire \mprj_io_holdover[5] ;
+  wire \mprj_io_holdover[6] ;
+  wire \mprj_io_holdover[7] ;
+  wire \mprj_io_holdover[8] ;
+  wire \mprj_io_holdover[9] ;
+  wire \mprj_io_ib_mode_sel[0] ;
+  wire \mprj_io_ib_mode_sel[10] ;
+  wire \mprj_io_ib_mode_sel[11] ;
+  wire \mprj_io_ib_mode_sel[12] ;
+  wire \mprj_io_ib_mode_sel[13] ;
+  wire \mprj_io_ib_mode_sel[14] ;
+  wire \mprj_io_ib_mode_sel[15] ;
+  wire \mprj_io_ib_mode_sel[16] ;
+  wire \mprj_io_ib_mode_sel[17] ;
+  wire \mprj_io_ib_mode_sel[18] ;
+  wire \mprj_io_ib_mode_sel[19] ;
+  wire \mprj_io_ib_mode_sel[1] ;
+  wire \mprj_io_ib_mode_sel[20] ;
+  wire \mprj_io_ib_mode_sel[21] ;
+  wire \mprj_io_ib_mode_sel[22] ;
+  wire \mprj_io_ib_mode_sel[23] ;
+  wire \mprj_io_ib_mode_sel[24] ;
+  wire \mprj_io_ib_mode_sel[25] ;
+  wire \mprj_io_ib_mode_sel[26] ;
+  wire \mprj_io_ib_mode_sel[27] ;
+  wire \mprj_io_ib_mode_sel[28] ;
+  wire \mprj_io_ib_mode_sel[29] ;
+  wire \mprj_io_ib_mode_sel[2] ;
+  wire \mprj_io_ib_mode_sel[30] ;
+  wire \mprj_io_ib_mode_sel[31] ;
+  wire \mprj_io_ib_mode_sel[32] ;
+  wire \mprj_io_ib_mode_sel[33] ;
+  wire \mprj_io_ib_mode_sel[34] ;
+  wire \mprj_io_ib_mode_sel[35] ;
+  wire \mprj_io_ib_mode_sel[36] ;
+  wire \mprj_io_ib_mode_sel[37] ;
+  wire \mprj_io_ib_mode_sel[3] ;
+  wire \mprj_io_ib_mode_sel[4] ;
+  wire \mprj_io_ib_mode_sel[5] ;
+  wire \mprj_io_ib_mode_sel[6] ;
+  wire \mprj_io_ib_mode_sel[7] ;
+  wire \mprj_io_ib_mode_sel[8] ;
+  wire \mprj_io_ib_mode_sel[9] ;
+  wire \mprj_io_in[0] ;
+  wire \mprj_io_in[10] ;
+  wire \mprj_io_in[11] ;
+  wire \mprj_io_in[12] ;
+  wire \mprj_io_in[13] ;
+  wire \mprj_io_in[14] ;
+  wire \mprj_io_in[15] ;
+  wire \mprj_io_in[16] ;
+  wire \mprj_io_in[17] ;
+  wire \mprj_io_in[18] ;
+  wire \mprj_io_in[19] ;
+  wire \mprj_io_in[1] ;
+  wire \mprj_io_in[20] ;
+  wire \mprj_io_in[21] ;
+  wire \mprj_io_in[22] ;
+  wire \mprj_io_in[23] ;
+  wire \mprj_io_in[24] ;
+  wire \mprj_io_in[25] ;
+  wire \mprj_io_in[26] ;
+  wire \mprj_io_in[27] ;
+  wire \mprj_io_in[28] ;
+  wire \mprj_io_in[29] ;
+  wire \mprj_io_in[2] ;
+  wire \mprj_io_in[30] ;
+  wire \mprj_io_in[31] ;
+  wire \mprj_io_in[32] ;
+  wire \mprj_io_in[33] ;
+  wire \mprj_io_in[34] ;
+  wire \mprj_io_in[35] ;
+  wire \mprj_io_in[36] ;
+  wire \mprj_io_in[37] ;
+  wire \mprj_io_in[3] ;
+  wire \mprj_io_in[4] ;
+  wire \mprj_io_in[5] ;
+  wire \mprj_io_in[6] ;
+  wire \mprj_io_in[7] ;
+  wire \mprj_io_in[8] ;
+  wire \mprj_io_in[9] ;
+  wire \mprj_io_inp_dis[0] ;
+  wire \mprj_io_inp_dis[10] ;
+  wire \mprj_io_inp_dis[11] ;
+  wire \mprj_io_inp_dis[12] ;
+  wire \mprj_io_inp_dis[13] ;
+  wire \mprj_io_inp_dis[14] ;
+  wire \mprj_io_inp_dis[15] ;
+  wire \mprj_io_inp_dis[16] ;
+  wire \mprj_io_inp_dis[17] ;
+  wire \mprj_io_inp_dis[18] ;
+  wire \mprj_io_inp_dis[19] ;
+  wire \mprj_io_inp_dis[1] ;
+  wire \mprj_io_inp_dis[20] ;
+  wire \mprj_io_inp_dis[21] ;
+  wire \mprj_io_inp_dis[22] ;
+  wire \mprj_io_inp_dis[23] ;
+  wire \mprj_io_inp_dis[24] ;
+  wire \mprj_io_inp_dis[25] ;
+  wire \mprj_io_inp_dis[26] ;
+  wire \mprj_io_inp_dis[27] ;
+  wire \mprj_io_inp_dis[28] ;
+  wire \mprj_io_inp_dis[29] ;
+  wire \mprj_io_inp_dis[2] ;
+  wire \mprj_io_inp_dis[30] ;
+  wire \mprj_io_inp_dis[31] ;
+  wire \mprj_io_inp_dis[32] ;
+  wire \mprj_io_inp_dis[33] ;
+  wire \mprj_io_inp_dis[34] ;
+  wire \mprj_io_inp_dis[35] ;
+  wire \mprj_io_inp_dis[36] ;
+  wire \mprj_io_inp_dis[37] ;
+  wire \mprj_io_inp_dis[3] ;
+  wire \mprj_io_inp_dis[4] ;
+  wire \mprj_io_inp_dis[5] ;
+  wire \mprj_io_inp_dis[6] ;
+  wire \mprj_io_inp_dis[7] ;
+  wire \mprj_io_inp_dis[8] ;
+  wire \mprj_io_inp_dis[9] ;
+  wire mprj_io_loader_clock;
+  wire mprj_io_loader_clock_buf;
+  wire mprj_io_loader_data_1;
+  wire mprj_io_loader_data_2;
+  wire mprj_io_loader_data_2_buf;
+  wire mprj_io_loader_resetn;
+  wire mprj_io_loader_resetn_buf;
+  wire mprj_io_loader_strobe;
+  wire mprj_io_loader_strobe_buf;
+  wire \mprj_io_oeb[0] ;
+  wire \mprj_io_oeb[10] ;
+  wire \mprj_io_oeb[11] ;
+  wire \mprj_io_oeb[12] ;
+  wire \mprj_io_oeb[13] ;
+  wire \mprj_io_oeb[14] ;
+  wire \mprj_io_oeb[15] ;
+  wire \mprj_io_oeb[16] ;
+  wire \mprj_io_oeb[17] ;
+  wire \mprj_io_oeb[18] ;
+  wire \mprj_io_oeb[19] ;
+  wire \mprj_io_oeb[1] ;
+  wire \mprj_io_oeb[20] ;
+  wire \mprj_io_oeb[21] ;
+  wire \mprj_io_oeb[22] ;
+  wire \mprj_io_oeb[23] ;
+  wire \mprj_io_oeb[24] ;
+  wire \mprj_io_oeb[25] ;
+  wire \mprj_io_oeb[26] ;
+  wire \mprj_io_oeb[27] ;
+  wire \mprj_io_oeb[28] ;
+  wire \mprj_io_oeb[29] ;
+  wire \mprj_io_oeb[2] ;
+  wire \mprj_io_oeb[30] ;
+  wire \mprj_io_oeb[31] ;
+  wire \mprj_io_oeb[32] ;
+  wire \mprj_io_oeb[33] ;
+  wire \mprj_io_oeb[34] ;
+  wire \mprj_io_oeb[35] ;
+  wire \mprj_io_oeb[36] ;
+  wire \mprj_io_oeb[37] ;
+  wire \mprj_io_oeb[3] ;
+  wire \mprj_io_oeb[4] ;
+  wire \mprj_io_oeb[5] ;
+  wire \mprj_io_oeb[6] ;
+  wire \mprj_io_oeb[7] ;
+  wire \mprj_io_oeb[8] ;
+  wire \mprj_io_oeb[9] ;
+  wire \mprj_io_one[0] ;
+  wire \mprj_io_one[10] ;
+  wire \mprj_io_one[11] ;
+  wire \mprj_io_one[12] ;
+  wire \mprj_io_one[13] ;
+  wire \mprj_io_one[14] ;
+  wire \mprj_io_one[15] ;
+  wire \mprj_io_one[16] ;
+  wire \mprj_io_one[17] ;
+  wire \mprj_io_one[18] ;
+  wire \mprj_io_one[19] ;
+  wire \mprj_io_one[1] ;
+  wire \mprj_io_one[20] ;
+  wire \mprj_io_one[21] ;
+  wire \mprj_io_one[22] ;
+  wire \mprj_io_one[23] ;
+  wire \mprj_io_one[24] ;
+  wire \mprj_io_one[25] ;
+  wire \mprj_io_one[26] ;
+  wire \mprj_io_one[27] ;
+  wire \mprj_io_one[28] ;
+  wire \mprj_io_one[29] ;
+  wire \mprj_io_one[2] ;
+  wire \mprj_io_one[30] ;
+  wire \mprj_io_one[31] ;
+  wire \mprj_io_one[32] ;
+  wire \mprj_io_one[33] ;
+  wire \mprj_io_one[34] ;
+  wire \mprj_io_one[35] ;
+  wire \mprj_io_one[36] ;
+  wire \mprj_io_one[37] ;
+  wire \mprj_io_one[3] ;
+  wire \mprj_io_one[4] ;
+  wire \mprj_io_one[5] ;
+  wire \mprj_io_one[6] ;
+  wire \mprj_io_one[7] ;
+  wire \mprj_io_one[8] ;
+  wire \mprj_io_one[9] ;
+  wire \mprj_io_out[0] ;
+  wire \mprj_io_out[10] ;
+  wire \mprj_io_out[11] ;
+  wire \mprj_io_out[12] ;
+  wire \mprj_io_out[13] ;
+  wire \mprj_io_out[14] ;
+  wire \mprj_io_out[15] ;
+  wire \mprj_io_out[16] ;
+  wire \mprj_io_out[17] ;
+  wire \mprj_io_out[18] ;
+  wire \mprj_io_out[19] ;
+  wire \mprj_io_out[1] ;
+  wire \mprj_io_out[20] ;
+  wire \mprj_io_out[21] ;
+  wire \mprj_io_out[22] ;
+  wire \mprj_io_out[23] ;
+  wire \mprj_io_out[24] ;
+  wire \mprj_io_out[25] ;
+  wire \mprj_io_out[26] ;
+  wire \mprj_io_out[27] ;
+  wire \mprj_io_out[28] ;
+  wire \mprj_io_out[29] ;
+  wire \mprj_io_out[2] ;
+  wire \mprj_io_out[30] ;
+  wire \mprj_io_out[31] ;
+  wire \mprj_io_out[32] ;
+  wire \mprj_io_out[33] ;
+  wire \mprj_io_out[34] ;
+  wire \mprj_io_out[35] ;
+  wire \mprj_io_out[36] ;
+  wire \mprj_io_out[37] ;
+  wire \mprj_io_out[3] ;
+  wire \mprj_io_out[4] ;
+  wire \mprj_io_out[5] ;
+  wire \mprj_io_out[6] ;
+  wire \mprj_io_out[7] ;
+  wire \mprj_io_out[8] ;
+  wire \mprj_io_out[9] ;
+  wire \mprj_io_slow_sel[0] ;
+  wire \mprj_io_slow_sel[10] ;
+  wire \mprj_io_slow_sel[11] ;
+  wire \mprj_io_slow_sel[12] ;
+  wire \mprj_io_slow_sel[13] ;
+  wire \mprj_io_slow_sel[14] ;
+  wire \mprj_io_slow_sel[15] ;
+  wire \mprj_io_slow_sel[16] ;
+  wire \mprj_io_slow_sel[17] ;
+  wire \mprj_io_slow_sel[18] ;
+  wire \mprj_io_slow_sel[19] ;
+  wire \mprj_io_slow_sel[1] ;
+  wire \mprj_io_slow_sel[20] ;
+  wire \mprj_io_slow_sel[21] ;
+  wire \mprj_io_slow_sel[22] ;
+  wire \mprj_io_slow_sel[23] ;
+  wire \mprj_io_slow_sel[24] ;
+  wire \mprj_io_slow_sel[25] ;
+  wire \mprj_io_slow_sel[26] ;
+  wire \mprj_io_slow_sel[27] ;
+  wire \mprj_io_slow_sel[28] ;
+  wire \mprj_io_slow_sel[29] ;
+  wire \mprj_io_slow_sel[2] ;
+  wire \mprj_io_slow_sel[30] ;
+  wire \mprj_io_slow_sel[31] ;
+  wire \mprj_io_slow_sel[32] ;
+  wire \mprj_io_slow_sel[33] ;
+  wire \mprj_io_slow_sel[34] ;
+  wire \mprj_io_slow_sel[35] ;
+  wire \mprj_io_slow_sel[36] ;
+  wire \mprj_io_slow_sel[37] ;
+  wire \mprj_io_slow_sel[3] ;
+  wire \mprj_io_slow_sel[4] ;
+  wire \mprj_io_slow_sel[5] ;
+  wire \mprj_io_slow_sel[6] ;
+  wire \mprj_io_slow_sel[7] ;
+  wire \mprj_io_slow_sel[8] ;
+  wire \mprj_io_slow_sel[9] ;
+  wire \mprj_io_vtrip_sel[0] ;
+  wire \mprj_io_vtrip_sel[10] ;
+  wire \mprj_io_vtrip_sel[11] ;
+  wire \mprj_io_vtrip_sel[12] ;
+  wire \mprj_io_vtrip_sel[13] ;
+  wire \mprj_io_vtrip_sel[14] ;
+  wire \mprj_io_vtrip_sel[15] ;
+  wire \mprj_io_vtrip_sel[16] ;
+  wire \mprj_io_vtrip_sel[17] ;
+  wire \mprj_io_vtrip_sel[18] ;
+  wire \mprj_io_vtrip_sel[19] ;
+  wire \mprj_io_vtrip_sel[1] ;
+  wire \mprj_io_vtrip_sel[20] ;
+  wire \mprj_io_vtrip_sel[21] ;
+  wire \mprj_io_vtrip_sel[22] ;
+  wire \mprj_io_vtrip_sel[23] ;
+  wire \mprj_io_vtrip_sel[24] ;
+  wire \mprj_io_vtrip_sel[25] ;
+  wire \mprj_io_vtrip_sel[26] ;
+  wire \mprj_io_vtrip_sel[27] ;
+  wire \mprj_io_vtrip_sel[28] ;
+  wire \mprj_io_vtrip_sel[29] ;
+  wire \mprj_io_vtrip_sel[2] ;
+  wire \mprj_io_vtrip_sel[30] ;
+  wire \mprj_io_vtrip_sel[31] ;
+  wire \mprj_io_vtrip_sel[32] ;
+  wire \mprj_io_vtrip_sel[33] ;
+  wire \mprj_io_vtrip_sel[34] ;
+  wire \mprj_io_vtrip_sel[35] ;
+  wire \mprj_io_vtrip_sel[36] ;
+  wire \mprj_io_vtrip_sel[37] ;
+  wire \mprj_io_vtrip_sel[3] ;
+  wire \mprj_io_vtrip_sel[4] ;
+  wire \mprj_io_vtrip_sel[5] ;
+  wire \mprj_io_vtrip_sel[6] ;
+  wire \mprj_io_vtrip_sel[7] ;
+  wire \mprj_io_vtrip_sel[8] ;
+  wire \mprj_io_vtrip_sel[9] ;
+  wire mprj_reset;
+  wire \mprj_sel_o_core[0] ;
+  wire \mprj_sel_o_core[1] ;
+  wire \mprj_sel_o_core[2] ;
+  wire \mprj_sel_o_core[3] ;
+  wire \mprj_sel_o_user[0] ;
+  wire \mprj_sel_o_user[1] ;
+  wire \mprj_sel_o_user[2] ;
+  wire \mprj_sel_o_user[3] ;
+  wire mprj_stb_o_core;
+  wire mprj_stb_o_user;
+  wire mprj_vcc_pwrgood;
+  wire mprj_vdd_pwrgood;
+  wire mprj_we_o_core;
+  wire mprj_we_o_user;
+  wire pll_clk;
+  wire pll_clk90;
+  wire por_l;
+  wire por_l_buf;
+  wire porb_h;
+  wire porb_h_buf;
+  wire porb_h_in_nc;
+  wire porb_h_out_nc;
+  wire porb_l;
+  wire \pwr_ctrl_nc[0] ;
+  wire \pwr_ctrl_nc[1] ;
+  wire \pwr_ctrl_nc[2] ;
+  wire \pwr_ctrl_nc[3] ;
+  wire qspi_enabled;
+  input resetb;
+  wire resetn_passthru;
+  wire rstb_h;
+  wire rstb_l;
+  wire rstb_l_buf;
+  wire ser_rx;
+  wire ser_tx;
+  wire \spare_xfq_nc[0] ;
+  wire \spare_xfq_nc[1] ;
+  wire \spare_xfq_nc[2] ;
+  wire \spare_xfq_nc[3] ;
+  wire \spare_xfq_nc[4] ;
+  wire \spare_xfq_nc[5] ;
+  wire \spare_xfq_nc[6] ;
+  wire \spare_xfq_nc[7] ;
+  wire \spare_xfqn_nc[0] ;
+  wire \spare_xfqn_nc[1] ;
+  wire \spare_xfqn_nc[2] ;
+  wire \spare_xfqn_nc[3] ;
+  wire \spare_xfqn_nc[4] ;
+  wire \spare_xfqn_nc[5] ;
+  wire \spare_xfqn_nc[6] ;
+  wire \spare_xfqn_nc[7] ;
+  wire \spare_xi_nc[0] ;
+  wire \spare_xi_nc[10] ;
+  wire \spare_xi_nc[11] ;
+  wire \spare_xi_nc[12] ;
+  wire \spare_xi_nc[13] ;
+  wire \spare_xi_nc[14] ;
+  wire \spare_xi_nc[15] ;
+  wire \spare_xi_nc[1] ;
+  wire \spare_xi_nc[2] ;
+  wire \spare_xi_nc[3] ;
+  wire \spare_xi_nc[4] ;
+  wire \spare_xi_nc[5] ;
+  wire \spare_xi_nc[6] ;
+  wire \spare_xi_nc[7] ;
+  wire \spare_xi_nc[8] ;
+  wire \spare_xi_nc[9] ;
+  wire \spare_xib_nc[0] ;
+  wire \spare_xib_nc[1] ;
+  wire \spare_xib_nc[2] ;
+  wire \spare_xib_nc[3] ;
+  wire \spare_xmx_nc[0] ;
+  wire \spare_xmx_nc[1] ;
+  wire \spare_xmx_nc[2] ;
+  wire \spare_xmx_nc[3] ;
+  wire \spare_xmx_nc[4] ;
+  wire \spare_xmx_nc[5] ;
+  wire \spare_xmx_nc[6] ;
+  wire \spare_xmx_nc[7] ;
+  wire \spare_xna_nc[0] ;
+  wire \spare_xna_nc[1] ;
+  wire \spare_xna_nc[2] ;
+  wire \spare_xna_nc[3] ;
+  wire \spare_xna_nc[4] ;
+  wire \spare_xna_nc[5] ;
+  wire \spare_xna_nc[6] ;
+  wire \spare_xna_nc[7] ;
+  wire \spare_xno_nc[0] ;
+  wire \spare_xno_nc[1] ;
+  wire \spare_xno_nc[2] ;
+  wire \spare_xno_nc[3] ;
+  wire \spare_xno_nc[4] ;
+  wire \spare_xno_nc[5] ;
+  wire \spare_xno_nc[6] ;
+  wire \spare_xno_nc[7] ;
+  wire \spare_xz_nc[0] ;
+  wire \spare_xz_nc[100] ;
+  wire \spare_xz_nc[101] ;
+  wire \spare_xz_nc[102] ;
+  wire \spare_xz_nc[103] ;
+  wire \spare_xz_nc[104] ;
+  wire \spare_xz_nc[105] ;
+  wire \spare_xz_nc[106] ;
+  wire \spare_xz_nc[107] ;
+  wire \spare_xz_nc[10] ;
+  wire \spare_xz_nc[11] ;
+  wire \spare_xz_nc[12] ;
+  wire \spare_xz_nc[13] ;
+  wire \spare_xz_nc[14] ;
+  wire \spare_xz_nc[15] ;
+  wire \spare_xz_nc[16] ;
+  wire \spare_xz_nc[17] ;
+  wire \spare_xz_nc[18] ;
+  wire \spare_xz_nc[19] ;
+  wire \spare_xz_nc[1] ;
+  wire \spare_xz_nc[20] ;
+  wire \spare_xz_nc[21] ;
+  wire \spare_xz_nc[22] ;
+  wire \spare_xz_nc[23] ;
+  wire \spare_xz_nc[24] ;
+  wire \spare_xz_nc[25] ;
+  wire \spare_xz_nc[26] ;
+  wire \spare_xz_nc[27] ;
+  wire \spare_xz_nc[28] ;
+  wire \spare_xz_nc[29] ;
+  wire \spare_xz_nc[2] ;
+  wire \spare_xz_nc[30] ;
+  wire \spare_xz_nc[31] ;
+  wire \spare_xz_nc[32] ;
+  wire \spare_xz_nc[33] ;
+  wire \spare_xz_nc[34] ;
+  wire \spare_xz_nc[35] ;
+  wire \spare_xz_nc[36] ;
+  wire \spare_xz_nc[37] ;
+  wire \spare_xz_nc[38] ;
+  wire \spare_xz_nc[39] ;
+  wire \spare_xz_nc[3] ;
+  wire \spare_xz_nc[40] ;
+  wire \spare_xz_nc[41] ;
+  wire \spare_xz_nc[42] ;
+  wire \spare_xz_nc[43] ;
+  wire \spare_xz_nc[44] ;
+  wire \spare_xz_nc[45] ;
+  wire \spare_xz_nc[46] ;
+  wire \spare_xz_nc[47] ;
+  wire \spare_xz_nc[48] ;
+  wire \spare_xz_nc[49] ;
+  wire \spare_xz_nc[4] ;
+  wire \spare_xz_nc[50] ;
+  wire \spare_xz_nc[51] ;
+  wire \spare_xz_nc[52] ;
+  wire \spare_xz_nc[53] ;
+  wire \spare_xz_nc[54] ;
+  wire \spare_xz_nc[55] ;
+  wire \spare_xz_nc[56] ;
+  wire \spare_xz_nc[57] ;
+  wire \spare_xz_nc[58] ;
+  wire \spare_xz_nc[59] ;
+  wire \spare_xz_nc[5] ;
+  wire \spare_xz_nc[60] ;
+  wire \spare_xz_nc[61] ;
+  wire \spare_xz_nc[62] ;
+  wire \spare_xz_nc[63] ;
+  wire \spare_xz_nc[64] ;
+  wire \spare_xz_nc[65] ;
+  wire \spare_xz_nc[66] ;
+  wire \spare_xz_nc[67] ;
+  wire \spare_xz_nc[68] ;
+  wire \spare_xz_nc[69] ;
+  wire \spare_xz_nc[6] ;
+  wire \spare_xz_nc[70] ;
+  wire \spare_xz_nc[71] ;
+  wire \spare_xz_nc[72] ;
+  wire \spare_xz_nc[73] ;
+  wire \spare_xz_nc[74] ;
+  wire \spare_xz_nc[75] ;
+  wire \spare_xz_nc[76] ;
+  wire \spare_xz_nc[77] ;
+  wire \spare_xz_nc[78] ;
+  wire \spare_xz_nc[79] ;
+  wire \spare_xz_nc[7] ;
+  wire \spare_xz_nc[80] ;
+  wire \spare_xz_nc[81] ;
+  wire \spare_xz_nc[82] ;
+  wire \spare_xz_nc[83] ;
+  wire \spare_xz_nc[84] ;
+  wire \spare_xz_nc[85] ;
+  wire \spare_xz_nc[86] ;
+  wire \spare_xz_nc[87] ;
+  wire \spare_xz_nc[88] ;
+  wire \spare_xz_nc[89] ;
+  wire \spare_xz_nc[8] ;
+  wire \spare_xz_nc[90] ;
+  wire \spare_xz_nc[91] ;
+  wire \spare_xz_nc[92] ;
+  wire \spare_xz_nc[93] ;
+  wire \spare_xz_nc[94] ;
+  wire \spare_xz_nc[95] ;
+  wire \spare_xz_nc[96] ;
+  wire \spare_xz_nc[97] ;
+  wire \spare_xz_nc[98] ;
+  wire \spare_xz_nc[99] ;
+  wire \spare_xz_nc[9] ;
+  wire spi_csb;
+  wire spi_enabled;
+  wire \spi_pll90_sel[0] ;
+  wire \spi_pll90_sel[1] ;
+  wire \spi_pll90_sel[2] ;
+  wire spi_pll_dco_ena;
+  wire \spi_pll_div[0] ;
+  wire \spi_pll_div[1] ;
+  wire \spi_pll_div[2] ;
+  wire \spi_pll_div[3] ;
+  wire \spi_pll_div[4] ;
+  wire spi_pll_ena;
+  wire \spi_pll_sel[0] ;
+  wire \spi_pll_sel[1] ;
+  wire \spi_pll_sel[2] ;
+  wire \spi_pll_trim[0] ;
+  wire \spi_pll_trim[10] ;
+  wire \spi_pll_trim[11] ;
+  wire \spi_pll_trim[12] ;
+  wire \spi_pll_trim[13] ;
+  wire \spi_pll_trim[14] ;
+  wire \spi_pll_trim[15] ;
+  wire \spi_pll_trim[16] ;
+  wire \spi_pll_trim[17] ;
+  wire \spi_pll_trim[18] ;
+  wire \spi_pll_trim[19] ;
+  wire \spi_pll_trim[1] ;
+  wire \spi_pll_trim[20] ;
+  wire \spi_pll_trim[21] ;
+  wire \spi_pll_trim[22] ;
+  wire \spi_pll_trim[23] ;
+  wire \spi_pll_trim[24] ;
+  wire \spi_pll_trim[25] ;
+  wire \spi_pll_trim[2] ;
+  wire \spi_pll_trim[3] ;
+  wire \spi_pll_trim[4] ;
+  wire \spi_pll_trim[5] ;
+  wire \spi_pll_trim[6] ;
+  wire \spi_pll_trim[7] ;
+  wire \spi_pll_trim[8] ;
+  wire \spi_pll_trim[9] ;
+  wire spi_sck;
+  wire spi_sdi;
+  wire spi_sdo;
+  wire spi_sdoenb;
+  wire trap;
+  wire uart_enabled;
+  wire \user_analog_io[0] ;
+  wire \user_analog_io[10] ;
+  wire \user_analog_io[11] ;
+  wire \user_analog_io[12] ;
+  wire \user_analog_io[13] ;
+  wire \user_analog_io[14] ;
+  wire \user_analog_io[15] ;
+  wire \user_analog_io[16] ;
+  wire \user_analog_io[17] ;
+  wire \user_analog_io[18] ;
+  wire \user_analog_io[19] ;
+  wire \user_analog_io[1] ;
+  wire \user_analog_io[20] ;
+  wire \user_analog_io[21] ;
+  wire \user_analog_io[22] ;
+  wire \user_analog_io[23] ;
+  wire \user_analog_io[24] ;
+  wire \user_analog_io[25] ;
+  wire \user_analog_io[26] ;
+  wire \user_analog_io[27] ;
+  wire \user_analog_io[28] ;
+  wire \user_analog_io[2] ;
+  wire \user_analog_io[3] ;
+  wire \user_analog_io[4] ;
+  wire \user_analog_io[5] ;
+  wire \user_analog_io[6] ;
+  wire \user_analog_io[7] ;
+  wire \user_analog_io[8] ;
+  wire \user_analog_io[9] ;
+  wire \user_io_in[0] ;
+  wire \user_io_in[10] ;
+  wire \user_io_in[11] ;
+  wire \user_io_in[12] ;
+  wire \user_io_in[13] ;
+  wire \user_io_in[14] ;
+  wire \user_io_in[15] ;
+  wire \user_io_in[16] ;
+  wire \user_io_in[17] ;
+  wire \user_io_in[18] ;
+  wire \user_io_in[19] ;
+  wire \user_io_in[1] ;
+  wire \user_io_in[20] ;
+  wire \user_io_in[21] ;
+  wire \user_io_in[22] ;
+  wire \user_io_in[23] ;
+  wire \user_io_in[24] ;
+  wire \user_io_in[25] ;
+  wire \user_io_in[26] ;
+  wire \user_io_in[27] ;
+  wire \user_io_in[28] ;
+  wire \user_io_in[29] ;
+  wire \user_io_in[2] ;
+  wire \user_io_in[30] ;
+  wire \user_io_in[31] ;
+  wire \user_io_in[32] ;
+  wire \user_io_in[33] ;
+  wire \user_io_in[34] ;
+  wire \user_io_in[35] ;
+  wire \user_io_in[36] ;
+  wire \user_io_in[37] ;
+  wire \user_io_in[3] ;
+  wire \user_io_in[4] ;
+  wire \user_io_in[5] ;
+  wire \user_io_in[6] ;
+  wire \user_io_in[7] ;
+  wire \user_io_in[8] ;
+  wire \user_io_in[9] ;
+  wire \user_io_oeb[0] ;
+  wire \user_io_oeb[10] ;
+  wire \user_io_oeb[11] ;
+  wire \user_io_oeb[12] ;
+  wire \user_io_oeb[13] ;
+  wire \user_io_oeb[14] ;
+  wire \user_io_oeb[15] ;
+  wire \user_io_oeb[16] ;
+  wire \user_io_oeb[17] ;
+  wire \user_io_oeb[18] ;
+  wire \user_io_oeb[19] ;
+  wire \user_io_oeb[1] ;
+  wire \user_io_oeb[20] ;
+  wire \user_io_oeb[21] ;
+  wire \user_io_oeb[22] ;
+  wire \user_io_oeb[23] ;
+  wire \user_io_oeb[24] ;
+  wire \user_io_oeb[25] ;
+  wire \user_io_oeb[26] ;
+  wire \user_io_oeb[27] ;
+  wire \user_io_oeb[28] ;
+  wire \user_io_oeb[29] ;
+  wire \user_io_oeb[2] ;
+  wire \user_io_oeb[30] ;
+  wire \user_io_oeb[31] ;
+  wire \user_io_oeb[32] ;
+  wire \user_io_oeb[33] ;
+  wire \user_io_oeb[34] ;
+  wire \user_io_oeb[35] ;
+  wire \user_io_oeb[36] ;
+  wire \user_io_oeb[37] ;
+  wire \user_io_oeb[3] ;
+  wire \user_io_oeb[4] ;
+  wire \user_io_oeb[5] ;
+  wire \user_io_oeb[6] ;
+  wire \user_io_oeb[7] ;
+  wire \user_io_oeb[8] ;
+  wire \user_io_oeb[9] ;
+  wire \user_io_out[0] ;
+  wire \user_io_out[10] ;
+  wire \user_io_out[11] ;
+  wire \user_io_out[12] ;
+  wire \user_io_out[13] ;
+  wire \user_io_out[14] ;
+  wire \user_io_out[15] ;
+  wire \user_io_out[16] ;
+  wire \user_io_out[17] ;
+  wire \user_io_out[18] ;
+  wire \user_io_out[19] ;
+  wire \user_io_out[1] ;
+  wire \user_io_out[20] ;
+  wire \user_io_out[21] ;
+  wire \user_io_out[22] ;
+  wire \user_io_out[23] ;
+  wire \user_io_out[24] ;
+  wire \user_io_out[25] ;
+  wire \user_io_out[26] ;
+  wire \user_io_out[27] ;
+  wire \user_io_out[28] ;
+  wire \user_io_out[29] ;
+  wire \user_io_out[2] ;
+  wire \user_io_out[30] ;
+  wire \user_io_out[31] ;
+  wire \user_io_out[32] ;
+  wire \user_io_out[33] ;
+  wire \user_io_out[34] ;
+  wire \user_io_out[35] ;
+  wire \user_io_out[36] ;
+  wire \user_io_out[37] ;
+  wire \user_io_out[3] ;
+  wire \user_io_out[4] ;
+  wire \user_io_out[5] ;
+  wire \user_io_out[6] ;
+  wire \user_io_out[7] ;
+  wire \user_io_out[8] ;
+  wire \user_io_out[9] ;
+  wire \user_irq[0] ;
+  wire \user_irq[1] ;
+  wire \user_irq[2] ;
+  wire \user_irq_core[0] ;
+  wire \user_irq_core[1] ;
+  wire \user_irq_core[2] ;
+  wire \user_irq_ena[0] ;
+  wire \user_irq_ena[1] ;
+  wire \user_irq_ena[2] ;
+  inout vccd;
+  inout vccd1;
+  wire vccd1_core;
+  inout vccd2;
+  wire vccd2_core;
+  wire vccd_core;
+  inout vdda;
+  inout vdda1;
+  inout vdda1_2;
+  wire vdda1_core;
+  inout vdda2;
+  wire vdda2_core;
+  wire vdda_core;
+  inout vddio;
+  inout vddio_2;
+  wire vddio_core;
+  inout vssa;
+  inout vssa1;
+  inout vssa1_2;
+  wire vssa1_core;
+  inout vssa2;
+  wire vssa2_core;
+  wire vssa_core;
+  inout vssd;
+  inout vssd1;
+  wire vssd1_core;
+  inout vssd2;
+  wire vssd2_core;
+  wire vssd_core;
+  inout vssio;
+  inout vssio_2;
+  wire vssio_core;
+  caravel_clocking clock_ctrl (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .core_clk(caravel_clk),
+    .ext_clk(clock_core_buf),
+    .ext_clk_sel(ext_clk_sel),
+    .ext_reset(ext_reset),
+    .pll_clk(pll_clk),
+    .pll_clk90(pll_clk90),
+    .resetb(rstb_l_buf),
+    .resetb_sync(caravel_rstn),
+    .sel({ \spi_pll_sel[2] , \spi_pll_sel[1] , \spi_pll_sel[0]  }),
+    .sel2({ \spi_pll90_sel[2] , \spi_pll90_sel[1] , \spi_pll90_sel[0]  }),
+    .user_clk(caravel_clk2)
+  );
+  buff_flash_clkrst flash_clkrst_buffers (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .in_n({ caravel_clk, caravel_rstn, flash_clk_frame, flash_csb_frame, flash_clk_oeb, flash_csb_oeb, flash_io0_oeb, flash_io1_oeb, flash_io0_ieb, flash_io1_ieb, flash_io0_do, flash_io1_do }),
+    .in_s({ clock_core, flash_io1_di, flash_io0_di }),
+    .out_n({ clock_core_buf, flash_io1_di_buf, flash_io0_di_buf }),
+    .out_s({ caravel_clk_buf, caravel_rstn_buf, flash_clk_frame_buf, flash_csb_frame_buf, flash_clk_oeb_buf, flash_csb_oeb_buf, flash_io0_oeb_buf, flash_io1_oeb_buf, flash_io0_ieb_buf, flash_io1_ieb_buf, flash_io0_do_buf, flash_io1_do_buf })
+  );
+  gpio_control_block \gpio_control_bidir_1[0]  (
+    .gpio_defaults({ \gpio_defaults[12] , \gpio_defaults[11] , \gpio_defaults[10] , \gpio_defaults[9] , \gpio_defaults[8] , \gpio_defaults[7] , \gpio_defaults[6] , \gpio_defaults[5] , \gpio_defaults[4] , \gpio_defaults[3] , \gpio_defaults[2] , \gpio_defaults[1] , \gpio_defaults[0]  }),
+    .mgmt_gpio_in(\mgmt_io_in[0] ),
+    .mgmt_gpio_oeb(\mgmt_io_oeb[0] ),
+    .mgmt_gpio_out(\mgmt_io_out[0] ),
+    .one(\mprj_io_one[0] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[0] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[0] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[0] ),
+    .pad_gpio_dm({ \mprj_io_dm[2] , \mprj_io_dm[1] , \mprj_io_dm[0]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[0] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[0] ),
+    .pad_gpio_in(\mprj_io_in[0] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[0] ),
+    .pad_gpio_out(\mprj_io_out[0] ),
+    .pad_gpio_outenb(\mprj_io_oeb[0] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[0] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[0] ),
+    .resetn(\gpio_resetn_1_shifted[0] ),
+    .resetn_out(\gpio_resetn_1[0] ),
+    .serial_clock(\gpio_clock_1_shifted[0] ),
+    .serial_clock_out(\gpio_clock_1[0] ),
+    .serial_data_in(\gpio_serial_link_1_shifted[0] ),
+    .serial_data_out(\gpio_serial_link_1[0] ),
+    .serial_load(\gpio_load_1_shifted[0] ),
+    .serial_load_out(\gpio_load_1[0] ),
+    .user_gpio_in(\user_io_in[0] ),
+    .user_gpio_oeb(\user_io_oeb[0] ),
+    .user_gpio_out(\user_io_out[0] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_bidir_1[1]  (
+    .gpio_defaults({ \gpio_defaults[25] , \gpio_defaults[24] , \gpio_defaults[23] , \gpio_defaults[22] , \gpio_defaults[21] , \gpio_defaults[20] , \gpio_defaults[19] , \gpio_defaults[18] , \gpio_defaults[17] , \gpio_defaults[16] , \gpio_defaults[15] , \gpio_defaults[14] , \gpio_defaults[13]  }),
+    .mgmt_gpio_in(\mgmt_io_in[1] ),
+    .mgmt_gpio_oeb(\mgmt_io_oeb[1] ),
+    .mgmt_gpio_out(\mgmt_io_out[1] ),
+    .one(\mprj_io_one[1] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[1] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[1] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[1] ),
+    .pad_gpio_dm({ \mprj_io_dm[5] , \mprj_io_dm[4] , \mprj_io_dm[3]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[1] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[1] ),
+    .pad_gpio_in(\mprj_io_in[1] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[1] ),
+    .pad_gpio_out(\mprj_io_out[1] ),
+    .pad_gpio_outenb(\mprj_io_oeb[1] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[1] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[1] ),
+    .resetn(\gpio_resetn_1[0] ),
+    .resetn_out(\gpio_resetn_1[1] ),
+    .serial_clock(\gpio_clock_1[0] ),
+    .serial_clock_out(\gpio_clock_1[1] ),
+    .serial_data_in(\gpio_serial_link_1[0] ),
+    .serial_data_out(\gpio_serial_link_1[1] ),
+    .serial_load(\gpio_load_1[0] ),
+    .serial_load_out(\gpio_load_1[1] ),
+    .user_gpio_in(\user_io_in[1] ),
+    .user_gpio_oeb(\user_io_oeb[1] ),
+    .user_gpio_out(\user_io_out[1] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_bidir_2[0]  (
+    .gpio_defaults({ \gpio_defaults[467] , \gpio_defaults[466] , \gpio_defaults[465] , \gpio_defaults[464] , \gpio_defaults[463] , \gpio_defaults[462] , \gpio_defaults[461] , \gpio_defaults[460] , \gpio_defaults[459] , \gpio_defaults[458] , \gpio_defaults[457] , \gpio_defaults[456] , \gpio_defaults[455]  }),
+    .mgmt_gpio_in(\mgmt_io_in[35] ),
+    .mgmt_gpio_oeb(\mgmt_io_oeb[35] ),
+    .mgmt_gpio_out(\mgmt_io_out[35] ),
+    .one(\mprj_io_one[35] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[35] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[35] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[35] ),
+    .pad_gpio_dm({ \mprj_io_dm[107] , \mprj_io_dm[106] , \mprj_io_dm[105]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[35] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[35] ),
+    .pad_gpio_in(\mprj_io_in[35] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[35] ),
+    .pad_gpio_out(\mprj_io_out[35] ),
+    .pad_gpio_outenb(\mprj_io_oeb[35] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[35] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[35] ),
+    .resetn(\gpio_resetn_2[17] ),
+    .resetn_out(\gpio_resetn_2[16] ),
+    .serial_clock(\gpio_clock_2[17] ),
+    .serial_clock_out(\gpio_clock_2[16] ),
+    .serial_data_in(\gpio_serial_link_2[17] ),
+    .serial_data_out(\gpio_serial_link_2[16] ),
+    .serial_load(\gpio_load_2[17] ),
+    .serial_load_out(\gpio_load_2[16] ),
+    .user_gpio_in(\user_io_in[35] ),
+    .user_gpio_oeb(\user_io_oeb[35] ),
+    .user_gpio_out(\user_io_out[35] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_bidir_2[1]  (
+    .gpio_defaults({ \gpio_defaults[480] , \gpio_defaults[479] , \gpio_defaults[478] , \gpio_defaults[477] , \gpio_defaults[476] , \gpio_defaults[475] , \gpio_defaults[474] , \gpio_defaults[473] , \gpio_defaults[472] , \gpio_defaults[471] , \gpio_defaults[470] , \gpio_defaults[469] , \gpio_defaults[468]  }),
+    .mgmt_gpio_in(\mgmt_io_in[36] ),
+    .mgmt_gpio_oeb(\mgmt_io_oeb[36] ),
+    .mgmt_gpio_out(\mgmt_io_out[36] ),
+    .one(\mprj_io_one[36] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[36] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[36] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[36] ),
+    .pad_gpio_dm({ \mprj_io_dm[110] , \mprj_io_dm[109] , \mprj_io_dm[108]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[36] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[36] ),
+    .pad_gpio_in(\mprj_io_in[36] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[36] ),
+    .pad_gpio_out(\mprj_io_out[36] ),
+    .pad_gpio_outenb(\mprj_io_oeb[36] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[36] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[36] ),
+    .resetn(\gpio_resetn_2[18] ),
+    .resetn_out(\gpio_resetn_2[17] ),
+    .serial_clock(\gpio_clock_2[18] ),
+    .serial_clock_out(\gpio_clock_2[17] ),
+    .serial_data_in(\gpio_serial_link_2[18] ),
+    .serial_data_out(\gpio_serial_link_2[17] ),
+    .serial_load(\gpio_load_2[18] ),
+    .serial_load_out(\gpio_load_2[17] ),
+    .user_gpio_in(\user_io_in[36] ),
+    .user_gpio_oeb(\user_io_oeb[36] ),
+    .user_gpio_out(\user_io_out[36] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_bidir_2[2]  (
+    .gpio_defaults({ \gpio_defaults[493] , \gpio_defaults[492] , \gpio_defaults[491] , \gpio_defaults[490] , \gpio_defaults[489] , \gpio_defaults[488] , \gpio_defaults[487] , \gpio_defaults[486] , \gpio_defaults[485] , \gpio_defaults[484] , \gpio_defaults[483] , \gpio_defaults[482] , \gpio_defaults[481]  }),
+    .mgmt_gpio_in(\mgmt_io_in[37] ),
+    .mgmt_gpio_oeb(\mgmt_io_oeb[37] ),
+    .mgmt_gpio_out(\mgmt_io_out[37] ),
+    .one(\mprj_io_one[37] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[37] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[37] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[37] ),
+    .pad_gpio_dm({ \mprj_io_dm[113] , \mprj_io_dm[112] , \mprj_io_dm[111]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[37] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[37] ),
+    .pad_gpio_in(\mprj_io_in[37] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[37] ),
+    .pad_gpio_out(\mprj_io_out[37] ),
+    .pad_gpio_outenb(\mprj_io_oeb[37] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[37] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[37] ),
+    .resetn(\gpio_resetn_2_shifted[18] ),
+    .resetn_out(\gpio_resetn_2[18] ),
+    .serial_clock(\gpio_clock_2_shifted[18] ),
+    .serial_clock_out(\gpio_clock_2[18] ),
+    .serial_data_in(\gpio_serial_link_2_shifted[18] ),
+    .serial_data_out(\gpio_serial_link_2[18] ),
+    .serial_load(\gpio_load_2_shifted[18] ),
+    .serial_load_out(\gpio_load_2[18] ),
+    .user_gpio_in(\user_io_in[37] ),
+    .user_gpio_oeb(\user_io_oeb[37] ),
+    .user_gpio_out(\user_io_out[37] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[0]  (
+    .gpio_defaults({ \gpio_defaults[116] , \gpio_defaults[115] , \gpio_defaults[114] , \gpio_defaults[113] , \gpio_defaults[112] , \gpio_defaults[111] , \gpio_defaults[110] , \gpio_defaults[109] , \gpio_defaults[108] , \gpio_defaults[107] , \gpio_defaults[106] , \gpio_defaults[105] , \gpio_defaults[104]  }),
+    .mgmt_gpio_in(\mgmt_io_in[8] ),
+    .mgmt_gpio_oeb(\mprj_io_one[8] ),
+    .mgmt_gpio_out(\mgmt_io_out[8] ),
+    .one(\mprj_io_one[8] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[8] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[8] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[8] ),
+    .pad_gpio_dm({ \mprj_io_dm[26] , \mprj_io_dm[25] , \mprj_io_dm[24]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[8] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[8] ),
+    .pad_gpio_in(\mprj_io_in[8] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[8] ),
+    .pad_gpio_out(\mprj_io_out[8] ),
+    .pad_gpio_outenb(\mprj_io_oeb[8] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[8] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[8] ),
+    .resetn(\gpio_resetn_1[7] ),
+    .resetn_out(\gpio_resetn_1[8] ),
+    .serial_clock(\gpio_clock_1[7] ),
+    .serial_clock_out(\gpio_clock_1[8] ),
+    .serial_data_in(\gpio_serial_link_1[7] ),
+    .serial_data_out(\gpio_serial_link_1[8] ),
+    .serial_load(\gpio_load_1[7] ),
+    .serial_load_out(\gpio_load_1[8] ),
+    .user_gpio_in(\user_io_in[8] ),
+    .user_gpio_oeb(\user_io_oeb[8] ),
+    .user_gpio_out(\user_io_out[8] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[10]  (
+    .gpio_defaults({ \gpio_defaults[246] , \gpio_defaults[245] , \gpio_defaults[244] , \gpio_defaults[243] , \gpio_defaults[242] , \gpio_defaults[241] , \gpio_defaults[240] , \gpio_defaults[239] , \gpio_defaults[238] , \gpio_defaults[237] , \gpio_defaults[236] , \gpio_defaults[235] , \gpio_defaults[234]  }),
+    .mgmt_gpio_in(\mgmt_io_in[18] ),
+    .mgmt_gpio_oeb(\mprj_io_one[18] ),
+    .mgmt_gpio_out(\mgmt_io_out[18] ),
+    .one(\mprj_io_one[18] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[18] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[18] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[18] ),
+    .pad_gpio_dm({ \mprj_io_dm[56] , \mprj_io_dm[55] , \mprj_io_dm[54]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[18] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[18] ),
+    .pad_gpio_in(\mprj_io_in[18] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[18] ),
+    .pad_gpio_out(\mprj_io_out[18] ),
+    .pad_gpio_outenb(\mprj_io_oeb[18] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[18] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[18] ),
+    .resetn(\gpio_resetn_1[17] ),
+    .resetn_out(\gpio_resetn_1[18] ),
+    .serial_clock(\gpio_clock_1[17] ),
+    .serial_clock_out(\gpio_clock_1[18] ),
+    .serial_data_in(\gpio_serial_link_1[17] ),
+    .serial_data_out(\gpio_serial_link_1[18] ),
+    .serial_load(\gpio_load_1[17] ),
+    .serial_load_out(\gpio_load_1[18] ),
+    .user_gpio_in(\user_io_in[18] ),
+    .user_gpio_oeb(\user_io_oeb[18] ),
+    .user_gpio_out(\user_io_out[18] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[1]  (
+    .gpio_defaults({ \gpio_defaults[129] , \gpio_defaults[128] , \gpio_defaults[127] , \gpio_defaults[126] , \gpio_defaults[125] , \gpio_defaults[124] , \gpio_defaults[123] , \gpio_defaults[122] , \gpio_defaults[121] , \gpio_defaults[120] , \gpio_defaults[119] , \gpio_defaults[118] , \gpio_defaults[117]  }),
+    .mgmt_gpio_in(\mgmt_io_in[9] ),
+    .mgmt_gpio_oeb(\mprj_io_one[9] ),
+    .mgmt_gpio_out(\mgmt_io_out[9] ),
+    .one(\mprj_io_one[9] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[9] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[9] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[9] ),
+    .pad_gpio_dm({ \mprj_io_dm[29] , \mprj_io_dm[28] , \mprj_io_dm[27]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[9] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[9] ),
+    .pad_gpio_in(\mprj_io_in[9] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[9] ),
+    .pad_gpio_out(\mprj_io_out[9] ),
+    .pad_gpio_outenb(\mprj_io_oeb[9] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[9] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[9] ),
+    .resetn(\gpio_resetn_1[8] ),
+    .resetn_out(\gpio_resetn_1[9] ),
+    .serial_clock(\gpio_clock_1[8] ),
+    .serial_clock_out(\gpio_clock_1[9] ),
+    .serial_data_in(\gpio_serial_link_1[8] ),
+    .serial_data_out(\gpio_serial_link_1[9] ),
+    .serial_load(\gpio_load_1[8] ),
+    .serial_load_out(\gpio_load_1[9] ),
+    .user_gpio_in(\user_io_in[9] ),
+    .user_gpio_oeb(\user_io_oeb[9] ),
+    .user_gpio_out(\user_io_out[9] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[2]  (
+    .gpio_defaults({ \gpio_defaults[142] , \gpio_defaults[141] , \gpio_defaults[140] , \gpio_defaults[139] , \gpio_defaults[138] , \gpio_defaults[137] , \gpio_defaults[136] , \gpio_defaults[135] , \gpio_defaults[134] , \gpio_defaults[133] , \gpio_defaults[132] , \gpio_defaults[131] , \gpio_defaults[130]  }),
+    .mgmt_gpio_in(\mgmt_io_in[10] ),
+    .mgmt_gpio_oeb(\mprj_io_one[10] ),
+    .mgmt_gpio_out(\mgmt_io_out[10] ),
+    .one(\mprj_io_one[10] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[10] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[10] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[10] ),
+    .pad_gpio_dm({ \mprj_io_dm[32] , \mprj_io_dm[31] , \mprj_io_dm[30]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[10] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[10] ),
+    .pad_gpio_in(\mprj_io_in[10] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[10] ),
+    .pad_gpio_out(\mprj_io_out[10] ),
+    .pad_gpio_outenb(\mprj_io_oeb[10] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[10] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[10] ),
+    .resetn(\gpio_resetn_1[9] ),
+    .resetn_out(\gpio_resetn_1[10] ),
+    .serial_clock(\gpio_clock_1[9] ),
+    .serial_clock_out(\gpio_clock_1[10] ),
+    .serial_data_in(\gpio_serial_link_1[9] ),
+    .serial_data_out(\gpio_serial_link_1[10] ),
+    .serial_load(\gpio_load_1[9] ),
+    .serial_load_out(\gpio_load_1[10] ),
+    .user_gpio_in(\user_io_in[10] ),
+    .user_gpio_oeb(\user_io_oeb[10] ),
+    .user_gpio_out(\user_io_out[10] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[3]  (
+    .gpio_defaults({ \gpio_defaults[155] , \gpio_defaults[154] , \gpio_defaults[153] , \gpio_defaults[152] , \gpio_defaults[151] , \gpio_defaults[150] , \gpio_defaults[149] , \gpio_defaults[148] , \gpio_defaults[147] , \gpio_defaults[146] , \gpio_defaults[145] , \gpio_defaults[144] , \gpio_defaults[143]  }),
+    .mgmt_gpio_in(\mgmt_io_in[11] ),
+    .mgmt_gpio_oeb(\mprj_io_one[11] ),
+    .mgmt_gpio_out(\mgmt_io_out[11] ),
+    .one(\mprj_io_one[11] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[11] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[11] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[11] ),
+    .pad_gpio_dm({ \mprj_io_dm[35] , \mprj_io_dm[34] , \mprj_io_dm[33]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[11] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[11] ),
+    .pad_gpio_in(\mprj_io_in[11] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[11] ),
+    .pad_gpio_out(\mprj_io_out[11] ),
+    .pad_gpio_outenb(\mprj_io_oeb[11] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[11] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[11] ),
+    .resetn(\gpio_resetn_1[10] ),
+    .resetn_out(\gpio_resetn_1[11] ),
+    .serial_clock(\gpio_clock_1[10] ),
+    .serial_clock_out(\gpio_clock_1[11] ),
+    .serial_data_in(\gpio_serial_link_1[10] ),
+    .serial_data_out(\gpio_serial_link_1[11] ),
+    .serial_load(\gpio_load_1[10] ),
+    .serial_load_out(\gpio_load_1[11] ),
+    .user_gpio_in(\user_io_in[11] ),
+    .user_gpio_oeb(\user_io_oeb[11] ),
+    .user_gpio_out(\user_io_out[11] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[4]  (
+    .gpio_defaults({ \gpio_defaults[168] , \gpio_defaults[167] , \gpio_defaults[166] , \gpio_defaults[165] , \gpio_defaults[164] , \gpio_defaults[163] , \gpio_defaults[162] , \gpio_defaults[161] , \gpio_defaults[160] , \gpio_defaults[159] , \gpio_defaults[158] , \gpio_defaults[157] , \gpio_defaults[156]  }),
+    .mgmt_gpio_in(\mgmt_io_in[12] ),
+    .mgmt_gpio_oeb(\mprj_io_one[12] ),
+    .mgmt_gpio_out(\mgmt_io_out[12] ),
+    .one(\mprj_io_one[12] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[12] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[12] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[12] ),
+    .pad_gpio_dm({ \mprj_io_dm[38] , \mprj_io_dm[37] , \mprj_io_dm[36]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[12] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[12] ),
+    .pad_gpio_in(\mprj_io_in[12] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[12] ),
+    .pad_gpio_out(\mprj_io_out[12] ),
+    .pad_gpio_outenb(\mprj_io_oeb[12] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[12] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[12] ),
+    .resetn(\gpio_resetn_1[11] ),
+    .resetn_out(\gpio_resetn_1[12] ),
+    .serial_clock(\gpio_clock_1[11] ),
+    .serial_clock_out(\gpio_clock_1[12] ),
+    .serial_data_in(\gpio_serial_link_1[11] ),
+    .serial_data_out(\gpio_serial_link_1[12] ),
+    .serial_load(\gpio_load_1[11] ),
+    .serial_load_out(\gpio_load_1[12] ),
+    .user_gpio_in(\user_io_in[12] ),
+    .user_gpio_oeb(\user_io_oeb[12] ),
+    .user_gpio_out(\user_io_out[12] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[5]  (
+    .gpio_defaults({ \gpio_defaults[181] , \gpio_defaults[180] , \gpio_defaults[179] , \gpio_defaults[178] , \gpio_defaults[177] , \gpio_defaults[176] , \gpio_defaults[175] , \gpio_defaults[174] , \gpio_defaults[173] , \gpio_defaults[172] , \gpio_defaults[171] , \gpio_defaults[170] , \gpio_defaults[169]  }),
+    .mgmt_gpio_in(\mgmt_io_in[13] ),
+    .mgmt_gpio_oeb(\mprj_io_one[13] ),
+    .mgmt_gpio_out(\mgmt_io_out[13] ),
+    .one(\mprj_io_one[13] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[13] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[13] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[13] ),
+    .pad_gpio_dm({ \mprj_io_dm[41] , \mprj_io_dm[40] , \mprj_io_dm[39]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[13] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[13] ),
+    .pad_gpio_in(\mprj_io_in[13] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[13] ),
+    .pad_gpio_out(\mprj_io_out[13] ),
+    .pad_gpio_outenb(\mprj_io_oeb[13] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[13] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[13] ),
+    .resetn(\gpio_resetn_1[12] ),
+    .resetn_out(\gpio_resetn_1[13] ),
+    .serial_clock(\gpio_clock_1[12] ),
+    .serial_clock_out(\gpio_clock_1[13] ),
+    .serial_data_in(\gpio_serial_link_1[12] ),
+    .serial_data_out(\gpio_serial_link_1[13] ),
+    .serial_load(\gpio_load_1[12] ),
+    .serial_load_out(\gpio_load_1[13] ),
+    .user_gpio_in(\user_io_in[13] ),
+    .user_gpio_oeb(\user_io_oeb[13] ),
+    .user_gpio_out(\user_io_out[13] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[6]  (
+    .gpio_defaults({ \gpio_defaults[194] , \gpio_defaults[193] , \gpio_defaults[192] , \gpio_defaults[191] , \gpio_defaults[190] , \gpio_defaults[189] , \gpio_defaults[188] , \gpio_defaults[187] , \gpio_defaults[186] , \gpio_defaults[185] , \gpio_defaults[184] , \gpio_defaults[183] , \gpio_defaults[182]  }),
+    .mgmt_gpio_in(\mgmt_io_in[14] ),
+    .mgmt_gpio_oeb(\mprj_io_one[14] ),
+    .mgmt_gpio_out(\mgmt_io_out[14] ),
+    .one(\mprj_io_one[14] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[14] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[14] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[14] ),
+    .pad_gpio_dm({ \mprj_io_dm[44] , \mprj_io_dm[43] , \mprj_io_dm[42]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[14] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[14] ),
+    .pad_gpio_in(\mprj_io_in[14] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[14] ),
+    .pad_gpio_out(\mprj_io_out[14] ),
+    .pad_gpio_outenb(\mprj_io_oeb[14] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[14] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[14] ),
+    .resetn(\gpio_resetn_1[13] ),
+    .resetn_out(\gpio_resetn_1[14] ),
+    .serial_clock(\gpio_clock_1[13] ),
+    .serial_clock_out(\gpio_clock_1[14] ),
+    .serial_data_in(\gpio_serial_link_1[13] ),
+    .serial_data_out(\gpio_serial_link_1[14] ),
+    .serial_load(\gpio_load_1[13] ),
+    .serial_load_out(\gpio_load_1[14] ),
+    .user_gpio_in(\user_io_in[14] ),
+    .user_gpio_oeb(\user_io_oeb[14] ),
+    .user_gpio_out(\user_io_out[14] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[7]  (
+    .gpio_defaults({ \gpio_defaults[207] , \gpio_defaults[206] , \gpio_defaults[205] , \gpio_defaults[204] , \gpio_defaults[203] , \gpio_defaults[202] , \gpio_defaults[201] , \gpio_defaults[200] , \gpio_defaults[199] , \gpio_defaults[198] , \gpio_defaults[197] , \gpio_defaults[196] , \gpio_defaults[195]  }),
+    .mgmt_gpio_in(\mgmt_io_in[15] ),
+    .mgmt_gpio_oeb(\mprj_io_one[15] ),
+    .mgmt_gpio_out(\mgmt_io_out[15] ),
+    .one(\mprj_io_one[15] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[15] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[15] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[15] ),
+    .pad_gpio_dm({ \mprj_io_dm[47] , \mprj_io_dm[46] , \mprj_io_dm[45]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[15] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[15] ),
+    .pad_gpio_in(\mprj_io_in[15] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[15] ),
+    .pad_gpio_out(\mprj_io_out[15] ),
+    .pad_gpio_outenb(\mprj_io_oeb[15] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[15] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[15] ),
+    .resetn(\gpio_resetn_1[14] ),
+    .resetn_out(\gpio_resetn_1[15] ),
+    .serial_clock(\gpio_clock_1[14] ),
+    .serial_clock_out(\gpio_clock_1[15] ),
+    .serial_data_in(\gpio_serial_link_1[14] ),
+    .serial_data_out(\gpio_serial_link_1[15] ),
+    .serial_load(\gpio_load_1[14] ),
+    .serial_load_out(\gpio_load_1[15] ),
+    .user_gpio_in(\user_io_in[15] ),
+    .user_gpio_oeb(\user_io_oeb[15] ),
+    .user_gpio_out(\user_io_out[15] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[8]  (
+    .gpio_defaults({ \gpio_defaults[220] , \gpio_defaults[219] , \gpio_defaults[218] , \gpio_defaults[217] , \gpio_defaults[216] , \gpio_defaults[215] , \gpio_defaults[214] , \gpio_defaults[213] , \gpio_defaults[212] , \gpio_defaults[211] , \gpio_defaults[210] , \gpio_defaults[209] , \gpio_defaults[208]  }),
+    .mgmt_gpio_in(\mgmt_io_in[16] ),
+    .mgmt_gpio_oeb(\mprj_io_one[16] ),
+    .mgmt_gpio_out(\mgmt_io_out[16] ),
+    .one(\mprj_io_one[16] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[16] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[16] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[16] ),
+    .pad_gpio_dm({ \mprj_io_dm[50] , \mprj_io_dm[49] , \mprj_io_dm[48]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[16] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[16] ),
+    .pad_gpio_in(\mprj_io_in[16] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[16] ),
+    .pad_gpio_out(\mprj_io_out[16] ),
+    .pad_gpio_outenb(\mprj_io_oeb[16] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[16] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[16] ),
+    .resetn(\gpio_resetn_1[15] ),
+    .resetn_out(\gpio_resetn_1[16] ),
+    .serial_clock(\gpio_clock_1[15] ),
+    .serial_clock_out(\gpio_clock_1[16] ),
+    .serial_data_in(\gpio_serial_link_1[15] ),
+    .serial_data_out(\gpio_serial_link_1[16] ),
+    .serial_load(\gpio_load_1[15] ),
+    .serial_load_out(\gpio_load_1[16] ),
+    .user_gpio_in(\user_io_in[16] ),
+    .user_gpio_oeb(\user_io_oeb[16] ),
+    .user_gpio_out(\user_io_out[16] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[9]  (
+    .gpio_defaults({ \gpio_defaults[233] , \gpio_defaults[232] , \gpio_defaults[231] , \gpio_defaults[230] , \gpio_defaults[229] , \gpio_defaults[228] , \gpio_defaults[227] , \gpio_defaults[226] , \gpio_defaults[225] , \gpio_defaults[224] , \gpio_defaults[223] , \gpio_defaults[222] , \gpio_defaults[221]  }),
+    .mgmt_gpio_in(\mgmt_io_in[17] ),
+    .mgmt_gpio_oeb(\mprj_io_one[17] ),
+    .mgmt_gpio_out(\mgmt_io_out[17] ),
+    .one(\mprj_io_one[17] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[17] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[17] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[17] ),
+    .pad_gpio_dm({ \mprj_io_dm[53] , \mprj_io_dm[52] , \mprj_io_dm[51]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[17] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[17] ),
+    .pad_gpio_in(\mprj_io_in[17] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[17] ),
+    .pad_gpio_out(\mprj_io_out[17] ),
+    .pad_gpio_outenb(\mprj_io_oeb[17] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[17] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[17] ),
+    .resetn(\gpio_resetn_1[16] ),
+    .resetn_out(\gpio_resetn_1[17] ),
+    .serial_clock(\gpio_clock_1[16] ),
+    .serial_clock_out(\gpio_clock_1[17] ),
+    .serial_data_in(\gpio_serial_link_1[16] ),
+    .serial_data_out(\gpio_serial_link_1[17] ),
+    .serial_load(\gpio_load_1[16] ),
+    .serial_load_out(\gpio_load_1[17] ),
+    .user_gpio_in(\user_io_in[17] ),
+    .user_gpio_oeb(\user_io_oeb[17] ),
+    .user_gpio_out(\user_io_out[17] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1a[0]  (
+    .gpio_defaults({ \gpio_defaults[38] , \gpio_defaults[37] , \gpio_defaults[36] , \gpio_defaults[35] , \gpio_defaults[34] , \gpio_defaults[33] , \gpio_defaults[32] , \gpio_defaults[31] , \gpio_defaults[30] , \gpio_defaults[29] , \gpio_defaults[28] , \gpio_defaults[27] , \gpio_defaults[26]  }),
+    .mgmt_gpio_in(\mgmt_io_in[2] ),
+    .mgmt_gpio_oeb(\mprj_io_one[2] ),
+    .mgmt_gpio_out(\mgmt_io_out[2] ),
+    .one(\mprj_io_one[2] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[2] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[2] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[2] ),
+    .pad_gpio_dm({ \mprj_io_dm[8] , \mprj_io_dm[7] , \mprj_io_dm[6]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[2] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[2] ),
+    .pad_gpio_in(\mprj_io_in[2] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[2] ),
+    .pad_gpio_out(\mprj_io_out[2] ),
+    .pad_gpio_outenb(\mprj_io_oeb[2] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[2] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[2] ),
+    .resetn(\gpio_resetn_1[1] ),
+    .resetn_out(\gpio_resetn_1[2] ),
+    .serial_clock(\gpio_clock_1[1] ),
+    .serial_clock_out(\gpio_clock_1[2] ),
+    .serial_data_in(\gpio_serial_link_1[1] ),
+    .serial_data_out(\gpio_serial_link_1[2] ),
+    .serial_load(\gpio_load_1[1] ),
+    .serial_load_out(\gpio_load_1[2] ),
+    .user_gpio_in(\user_io_in[2] ),
+    .user_gpio_oeb(\user_io_oeb[2] ),
+    .user_gpio_out(\user_io_out[2] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1a[1]  (
+    .gpio_defaults({ \gpio_defaults[51] , \gpio_defaults[50] , \gpio_defaults[49] , \gpio_defaults[48] , \gpio_defaults[47] , \gpio_defaults[46] , \gpio_defaults[45] , \gpio_defaults[44] , \gpio_defaults[43] , \gpio_defaults[42] , \gpio_defaults[41] , \gpio_defaults[40] , \gpio_defaults[39]  }),
+    .mgmt_gpio_in(\mgmt_io_in[3] ),
+    .mgmt_gpio_oeb(\mprj_io_one[3] ),
+    .mgmt_gpio_out(\mgmt_io_out[3] ),
+    .one(\mprj_io_one[3] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[3] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[3] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[3] ),
+    .pad_gpio_dm({ \mprj_io_dm[11] , \mprj_io_dm[10] , \mprj_io_dm[9]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[3] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[3] ),
+    .pad_gpio_in(\mprj_io_in[3] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[3] ),
+    .pad_gpio_out(\mprj_io_out[3] ),
+    .pad_gpio_outenb(\mprj_io_oeb[3] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[3] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[3] ),
+    .resetn(\gpio_resetn_1[2] ),
+    .resetn_out(\gpio_resetn_1[3] ),
+    .serial_clock(\gpio_clock_1[2] ),
+    .serial_clock_out(\gpio_clock_1[3] ),
+    .serial_data_in(\gpio_serial_link_1[2] ),
+    .serial_data_out(\gpio_serial_link_1[3] ),
+    .serial_load(\gpio_load_1[2] ),
+    .serial_load_out(\gpio_load_1[3] ),
+    .user_gpio_in(\user_io_in[3] ),
+    .user_gpio_oeb(\user_io_oeb[3] ),
+    .user_gpio_out(\user_io_out[3] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1a[2]  (
+    .gpio_defaults({ \gpio_defaults[64] , \gpio_defaults[63] , \gpio_defaults[62] , \gpio_defaults[61] , \gpio_defaults[60] , \gpio_defaults[59] , \gpio_defaults[58] , \gpio_defaults[57] , \gpio_defaults[56] , \gpio_defaults[55] , \gpio_defaults[54] , \gpio_defaults[53] , \gpio_defaults[52]  }),
+    .mgmt_gpio_in(\mgmt_io_in[4] ),
+    .mgmt_gpio_oeb(\mprj_io_one[4] ),
+    .mgmt_gpio_out(\mgmt_io_out[4] ),
+    .one(\mprj_io_one[4] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[4] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[4] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[4] ),
+    .pad_gpio_dm({ \mprj_io_dm[14] , \mprj_io_dm[13] , \mprj_io_dm[12]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[4] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[4] ),
+    .pad_gpio_in(\mprj_io_in[4] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[4] ),
+    .pad_gpio_out(\mprj_io_out[4] ),
+    .pad_gpio_outenb(\mprj_io_oeb[4] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[4] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[4] ),
+    .resetn(\gpio_resetn_1[3] ),
+    .resetn_out(\gpio_resetn_1[4] ),
+    .serial_clock(\gpio_clock_1[3] ),
+    .serial_clock_out(\gpio_clock_1[4] ),
+    .serial_data_in(\gpio_serial_link_1[3] ),
+    .serial_data_out(\gpio_serial_link_1[4] ),
+    .serial_load(\gpio_load_1[3] ),
+    .serial_load_out(\gpio_load_1[4] ),
+    .user_gpio_in(\user_io_in[4] ),
+    .user_gpio_oeb(\user_io_oeb[4] ),
+    .user_gpio_out(\user_io_out[4] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1a[3]  (
+    .gpio_defaults({ \gpio_defaults[77] , \gpio_defaults[76] , \gpio_defaults[75] , \gpio_defaults[74] , \gpio_defaults[73] , \gpio_defaults[72] , \gpio_defaults[71] , \gpio_defaults[70] , \gpio_defaults[69] , \gpio_defaults[68] , \gpio_defaults[67] , \gpio_defaults[66] , \gpio_defaults[65]  }),
+    .mgmt_gpio_in(\mgmt_io_in[5] ),
+    .mgmt_gpio_oeb(\mprj_io_one[5] ),
+    .mgmt_gpio_out(\mgmt_io_out[5] ),
+    .one(\mprj_io_one[5] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[5] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[5] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[5] ),
+    .pad_gpio_dm({ \mprj_io_dm[17] , \mprj_io_dm[16] , \mprj_io_dm[15]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[5] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[5] ),
+    .pad_gpio_in(\mprj_io_in[5] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[5] ),
+    .pad_gpio_out(\mprj_io_out[5] ),
+    .pad_gpio_outenb(\mprj_io_oeb[5] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[5] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[5] ),
+    .resetn(\gpio_resetn_1[4] ),
+    .resetn_out(\gpio_resetn_1[5] ),
+    .serial_clock(\gpio_clock_1[4] ),
+    .serial_clock_out(\gpio_clock_1[5] ),
+    .serial_data_in(\gpio_serial_link_1[4] ),
+    .serial_data_out(\gpio_serial_link_1[5] ),
+    .serial_load(\gpio_load_1[4] ),
+    .serial_load_out(\gpio_load_1[5] ),
+    .user_gpio_in(\user_io_in[5] ),
+    .user_gpio_oeb(\user_io_oeb[5] ),
+    .user_gpio_out(\user_io_out[5] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1a[4]  (
+    .gpio_defaults({ \gpio_defaults[90] , \gpio_defaults[89] , \gpio_defaults[88] , \gpio_defaults[87] , \gpio_defaults[86] , \gpio_defaults[85] , \gpio_defaults[84] , \gpio_defaults[83] , \gpio_defaults[82] , \gpio_defaults[81] , \gpio_defaults[80] , \gpio_defaults[79] , \gpio_defaults[78]  }),
+    .mgmt_gpio_in(\mgmt_io_in[6] ),
+    .mgmt_gpio_oeb(\mprj_io_one[6] ),
+    .mgmt_gpio_out(\mgmt_io_out[6] ),
+    .one(\mprj_io_one[6] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[6] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[6] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[6] ),
+    .pad_gpio_dm({ \mprj_io_dm[20] , \mprj_io_dm[19] , \mprj_io_dm[18]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[6] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[6] ),
+    .pad_gpio_in(\mprj_io_in[6] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[6] ),
+    .pad_gpio_out(\mprj_io_out[6] ),
+    .pad_gpio_outenb(\mprj_io_oeb[6] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[6] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[6] ),
+    .resetn(\gpio_resetn_1[5] ),
+    .resetn_out(\gpio_resetn_1[6] ),
+    .serial_clock(\gpio_clock_1[5] ),
+    .serial_clock_out(\gpio_clock_1[6] ),
+    .serial_data_in(\gpio_serial_link_1[5] ),
+    .serial_data_out(\gpio_serial_link_1[6] ),
+    .serial_load(\gpio_load_1[5] ),
+    .serial_load_out(\gpio_load_1[6] ),
+    .user_gpio_in(\user_io_in[6] ),
+    .user_gpio_oeb(\user_io_oeb[6] ),
+    .user_gpio_out(\user_io_out[6] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1a[5]  (
+    .gpio_defaults({ \gpio_defaults[103] , \gpio_defaults[102] , \gpio_defaults[101] , \gpio_defaults[100] , \gpio_defaults[99] , \gpio_defaults[98] , \gpio_defaults[97] , \gpio_defaults[96] , \gpio_defaults[95] , \gpio_defaults[94] , \gpio_defaults[93] , \gpio_defaults[92] , \gpio_defaults[91]  }),
+    .mgmt_gpio_in(\mgmt_io_in[7] ),
+    .mgmt_gpio_oeb(\mprj_io_one[7] ),
+    .mgmt_gpio_out(\mgmt_io_out[7] ),
+    .one(\mprj_io_one[7] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[7] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[7] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[7] ),
+    .pad_gpio_dm({ \mprj_io_dm[23] , \mprj_io_dm[22] , \mprj_io_dm[21]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[7] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[7] ),
+    .pad_gpio_in(\mprj_io_in[7] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[7] ),
+    .pad_gpio_out(\mprj_io_out[7] ),
+    .pad_gpio_outenb(\mprj_io_oeb[7] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[7] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[7] ),
+    .resetn(\gpio_resetn_1[6] ),
+    .resetn_out(\gpio_resetn_1[7] ),
+    .serial_clock(\gpio_clock_1[6] ),
+    .serial_clock_out(\gpio_clock_1[7] ),
+    .serial_data_in(\gpio_serial_link_1[6] ),
+    .serial_data_out(\gpio_serial_link_1[7] ),
+    .serial_load(\gpio_load_1[6] ),
+    .serial_load_out(\gpio_load_1[7] ),
+    .user_gpio_in(\user_io_in[7] ),
+    .user_gpio_oeb(\user_io_oeb[7] ),
+    .user_gpio_out(\user_io_out[7] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[0]  (
+    .gpio_defaults({ \gpio_defaults[259] , \gpio_defaults[258] , \gpio_defaults[257] , \gpio_defaults[256] , \gpio_defaults[255] , \gpio_defaults[254] , \gpio_defaults[253] , \gpio_defaults[252] , \gpio_defaults[251] , \gpio_defaults[250] , \gpio_defaults[249] , \gpio_defaults[248] , \gpio_defaults[247]  }),
+    .mgmt_gpio_in(\mgmt_io_in[19] ),
+    .mgmt_gpio_oeb(\mprj_io_one[19] ),
+    .mgmt_gpio_out(\mgmt_io_out[19] ),
+    .one(\mprj_io_one[19] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[19] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[19] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[19] ),
+    .pad_gpio_dm({ \mprj_io_dm[59] , \mprj_io_dm[58] , \mprj_io_dm[57]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[19] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[19] ),
+    .pad_gpio_in(\mprj_io_in[19] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[19] ),
+    .pad_gpio_out(\mprj_io_out[19] ),
+    .pad_gpio_outenb(\mprj_io_oeb[19] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[19] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[19] ),
+    .resetn(\gpio_resetn_2[1] ),
+    .resetn_out(\gpio_resetn_2[0] ),
+    .serial_clock(\gpio_clock_2[1] ),
+    .serial_clock_out(\gpio_clock_2[0] ),
+    .serial_data_in(\gpio_serial_link_2[1] ),
+    .serial_data_out(\gpio_serial_link_2[0] ),
+    .serial_load(\gpio_load_2[1] ),
+    .serial_load_out(\gpio_load_2[0] ),
+    .user_gpio_in(\user_io_in[19] ),
+    .user_gpio_oeb(\user_io_oeb[19] ),
+    .user_gpio_out(\user_io_out[19] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[10]  (
+    .gpio_defaults({ \gpio_defaults[389] , \gpio_defaults[388] , \gpio_defaults[387] , \gpio_defaults[386] , \gpio_defaults[385] , \gpio_defaults[384] , \gpio_defaults[383] , \gpio_defaults[382] , \gpio_defaults[381] , \gpio_defaults[380] , \gpio_defaults[379] , \gpio_defaults[378] , \gpio_defaults[377]  }),
+    .mgmt_gpio_in(\mgmt_io_in[29] ),
+    .mgmt_gpio_oeb(\mprj_io_one[29] ),
+    .mgmt_gpio_out(\mgmt_io_out[29] ),
+    .one(\mprj_io_one[29] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[29] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[29] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[29] ),
+    .pad_gpio_dm({ \mprj_io_dm[89] , \mprj_io_dm[88] , \mprj_io_dm[87]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[29] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[29] ),
+    .pad_gpio_in(\mprj_io_in[29] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[29] ),
+    .pad_gpio_out(\mprj_io_out[29] ),
+    .pad_gpio_outenb(\mprj_io_oeb[29] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[29] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[29] ),
+    .resetn(\gpio_resetn_2[11] ),
+    .resetn_out(\gpio_resetn_2[10] ),
+    .serial_clock(\gpio_clock_2[11] ),
+    .serial_clock_out(\gpio_clock_2[10] ),
+    .serial_data_in(\gpio_serial_link_2[11] ),
+    .serial_data_out(\gpio_serial_link_2[10] ),
+    .serial_load(\gpio_load_2[11] ),
+    .serial_load_out(\gpio_load_2[10] ),
+    .user_gpio_in(\user_io_in[29] ),
+    .user_gpio_oeb(\user_io_oeb[29] ),
+    .user_gpio_out(\user_io_out[29] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[11]  (
+    .gpio_defaults({ \gpio_defaults[402] , \gpio_defaults[401] , \gpio_defaults[400] , \gpio_defaults[399] , \gpio_defaults[398] , \gpio_defaults[397] , \gpio_defaults[396] , \gpio_defaults[395] , \gpio_defaults[394] , \gpio_defaults[393] , \gpio_defaults[392] , \gpio_defaults[391] , \gpio_defaults[390]  }),
+    .mgmt_gpio_in(\mgmt_io_in[30] ),
+    .mgmt_gpio_oeb(\mprj_io_one[30] ),
+    .mgmt_gpio_out(\mgmt_io_out[30] ),
+    .one(\mprj_io_one[30] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[30] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[30] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[30] ),
+    .pad_gpio_dm({ \mprj_io_dm[92] , \mprj_io_dm[91] , \mprj_io_dm[90]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[30] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[30] ),
+    .pad_gpio_in(\mprj_io_in[30] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[30] ),
+    .pad_gpio_out(\mprj_io_out[30] ),
+    .pad_gpio_outenb(\mprj_io_oeb[30] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[30] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[30] ),
+    .resetn(\gpio_resetn_2[12] ),
+    .resetn_out(\gpio_resetn_2[11] ),
+    .serial_clock(\gpio_clock_2[12] ),
+    .serial_clock_out(\gpio_clock_2[11] ),
+    .serial_data_in(\gpio_serial_link_2[12] ),
+    .serial_data_out(\gpio_serial_link_2[11] ),
+    .serial_load(\gpio_load_2[12] ),
+    .serial_load_out(\gpio_load_2[11] ),
+    .user_gpio_in(\user_io_in[30] ),
+    .user_gpio_oeb(\user_io_oeb[30] ),
+    .user_gpio_out(\user_io_out[30] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[12]  (
+    .gpio_defaults({ \gpio_defaults[415] , \gpio_defaults[414] , \gpio_defaults[413] , \gpio_defaults[412] , \gpio_defaults[411] , \gpio_defaults[410] , \gpio_defaults[409] , \gpio_defaults[408] , \gpio_defaults[407] , \gpio_defaults[406] , \gpio_defaults[405] , \gpio_defaults[404] , \gpio_defaults[403]  }),
+    .mgmt_gpio_in(\mgmt_io_in[31] ),
+    .mgmt_gpio_oeb(\mprj_io_one[31] ),
+    .mgmt_gpio_out(\mgmt_io_out[31] ),
+    .one(\mprj_io_one[31] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[31] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[31] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[31] ),
+    .pad_gpio_dm({ \mprj_io_dm[95] , \mprj_io_dm[94] , \mprj_io_dm[93]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[31] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[31] ),
+    .pad_gpio_in(\mprj_io_in[31] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[31] ),
+    .pad_gpio_out(\mprj_io_out[31] ),
+    .pad_gpio_outenb(\mprj_io_oeb[31] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[31] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[31] ),
+    .resetn(\gpio_resetn_2[13] ),
+    .resetn_out(\gpio_resetn_2[12] ),
+    .serial_clock(\gpio_clock_2[13] ),
+    .serial_clock_out(\gpio_clock_2[12] ),
+    .serial_data_in(\gpio_serial_link_2[13] ),
+    .serial_data_out(\gpio_serial_link_2[12] ),
+    .serial_load(\gpio_load_2[13] ),
+    .serial_load_out(\gpio_load_2[12] ),
+    .user_gpio_in(\user_io_in[31] ),
+    .user_gpio_oeb(\user_io_oeb[31] ),
+    .user_gpio_out(\user_io_out[31] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[13]  (
+    .gpio_defaults({ \gpio_defaults[428] , \gpio_defaults[427] , \gpio_defaults[426] , \gpio_defaults[425] , \gpio_defaults[424] , \gpio_defaults[423] , \gpio_defaults[422] , \gpio_defaults[421] , \gpio_defaults[420] , \gpio_defaults[419] , \gpio_defaults[418] , \gpio_defaults[417] , \gpio_defaults[416]  }),
+    .mgmt_gpio_in(\mgmt_io_in[32] ),
+    .mgmt_gpio_oeb(\mprj_io_one[32] ),
+    .mgmt_gpio_out(\mgmt_io_out[32] ),
+    .one(\mprj_io_one[32] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[32] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[32] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[32] ),
+    .pad_gpio_dm({ \mprj_io_dm[98] , \mprj_io_dm[97] , \mprj_io_dm[96]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[32] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[32] ),
+    .pad_gpio_in(\mprj_io_in[32] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[32] ),
+    .pad_gpio_out(\mprj_io_out[32] ),
+    .pad_gpio_outenb(\mprj_io_oeb[32] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[32] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[32] ),
+    .resetn(\gpio_resetn_2[14] ),
+    .resetn_out(\gpio_resetn_2[13] ),
+    .serial_clock(\gpio_clock_2[14] ),
+    .serial_clock_out(\gpio_clock_2[13] ),
+    .serial_data_in(\gpio_serial_link_2[14] ),
+    .serial_data_out(\gpio_serial_link_2[13] ),
+    .serial_load(\gpio_load_2[14] ),
+    .serial_load_out(\gpio_load_2[13] ),
+    .user_gpio_in(\user_io_in[32] ),
+    .user_gpio_oeb(\user_io_oeb[32] ),
+    .user_gpio_out(\user_io_out[32] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[14]  (
+    .gpio_defaults({ \gpio_defaults[441] , \gpio_defaults[440] , \gpio_defaults[439] , \gpio_defaults[438] , \gpio_defaults[437] , \gpio_defaults[436] , \gpio_defaults[435] , \gpio_defaults[434] , \gpio_defaults[433] , \gpio_defaults[432] , \gpio_defaults[431] , \gpio_defaults[430] , \gpio_defaults[429]  }),
+    .mgmt_gpio_in(\mgmt_io_in[33] ),
+    .mgmt_gpio_oeb(\mprj_io_one[33] ),
+    .mgmt_gpio_out(\mgmt_io_out[33] ),
+    .one(\mprj_io_one[33] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[33] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[33] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[33] ),
+    .pad_gpio_dm({ \mprj_io_dm[101] , \mprj_io_dm[100] , \mprj_io_dm[99]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[33] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[33] ),
+    .pad_gpio_in(\mprj_io_in[33] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[33] ),
+    .pad_gpio_out(\mprj_io_out[33] ),
+    .pad_gpio_outenb(\mprj_io_oeb[33] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[33] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[33] ),
+    .resetn(\gpio_resetn_2[15] ),
+    .resetn_out(\gpio_resetn_2[14] ),
+    .serial_clock(\gpio_clock_2[15] ),
+    .serial_clock_out(\gpio_clock_2[14] ),
+    .serial_data_in(\gpio_serial_link_2[15] ),
+    .serial_data_out(\gpio_serial_link_2[14] ),
+    .serial_load(\gpio_load_2[15] ),
+    .serial_load_out(\gpio_load_2[14] ),
+    .user_gpio_in(\user_io_in[33] ),
+    .user_gpio_oeb(\user_io_oeb[33] ),
+    .user_gpio_out(\user_io_out[33] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[15]  (
+    .gpio_defaults({ \gpio_defaults[454] , \gpio_defaults[453] , \gpio_defaults[452] , \gpio_defaults[451] , \gpio_defaults[450] , \gpio_defaults[449] , \gpio_defaults[448] , \gpio_defaults[447] , \gpio_defaults[446] , \gpio_defaults[445] , \gpio_defaults[444] , \gpio_defaults[443] , \gpio_defaults[442]  }),
+    .mgmt_gpio_in(\mgmt_io_in[34] ),
+    .mgmt_gpio_oeb(\mprj_io_one[34] ),
+    .mgmt_gpio_out(\mgmt_io_out[34] ),
+    .one(\mprj_io_one[34] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[34] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[34] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[34] ),
+    .pad_gpio_dm({ \mprj_io_dm[104] , \mprj_io_dm[103] , \mprj_io_dm[102]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[34] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[34] ),
+    .pad_gpio_in(\mprj_io_in[34] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[34] ),
+    .pad_gpio_out(\mprj_io_out[34] ),
+    .pad_gpio_outenb(\mprj_io_oeb[34] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[34] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[34] ),
+    .resetn(\gpio_resetn_2[16] ),
+    .resetn_out(\gpio_resetn_2[15] ),
+    .serial_clock(\gpio_clock_2[16] ),
+    .serial_clock_out(\gpio_clock_2[15] ),
+    .serial_data_in(\gpio_serial_link_2[16] ),
+    .serial_data_out(\gpio_serial_link_2[15] ),
+    .serial_load(\gpio_load_2[16] ),
+    .serial_load_out(\gpio_load_2[15] ),
+    .user_gpio_in(\user_io_in[34] ),
+    .user_gpio_oeb(\user_io_oeb[34] ),
+    .user_gpio_out(\user_io_out[34] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[1]  (
+    .gpio_defaults({ \gpio_defaults[272] , \gpio_defaults[271] , \gpio_defaults[270] , \gpio_defaults[269] , \gpio_defaults[268] , \gpio_defaults[267] , \gpio_defaults[266] , \gpio_defaults[265] , \gpio_defaults[264] , \gpio_defaults[263] , \gpio_defaults[262] , \gpio_defaults[261] , \gpio_defaults[260]  }),
+    .mgmt_gpio_in(\mgmt_io_in[20] ),
+    .mgmt_gpio_oeb(\mprj_io_one[20] ),
+    .mgmt_gpio_out(\mgmt_io_out[20] ),
+    .one(\mprj_io_one[20] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[20] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[20] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[20] ),
+    .pad_gpio_dm({ \mprj_io_dm[62] , \mprj_io_dm[61] , \mprj_io_dm[60]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[20] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[20] ),
+    .pad_gpio_in(\mprj_io_in[20] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[20] ),
+    .pad_gpio_out(\mprj_io_out[20] ),
+    .pad_gpio_outenb(\mprj_io_oeb[20] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[20] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[20] ),
+    .resetn(\gpio_resetn_2[2] ),
+    .resetn_out(\gpio_resetn_2[1] ),
+    .serial_clock(\gpio_clock_2[2] ),
+    .serial_clock_out(\gpio_clock_2[1] ),
+    .serial_data_in(\gpio_serial_link_2[2] ),
+    .serial_data_out(\gpio_serial_link_2[1] ),
+    .serial_load(\gpio_load_2[2] ),
+    .serial_load_out(\gpio_load_2[1] ),
+    .user_gpio_in(\user_io_in[20] ),
+    .user_gpio_oeb(\user_io_oeb[20] ),
+    .user_gpio_out(\user_io_out[20] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[2]  (
+    .gpio_defaults({ \gpio_defaults[285] , \gpio_defaults[284] , \gpio_defaults[283] , \gpio_defaults[282] , \gpio_defaults[281] , \gpio_defaults[280] , \gpio_defaults[279] , \gpio_defaults[278] , \gpio_defaults[277] , \gpio_defaults[276] , \gpio_defaults[275] , \gpio_defaults[274] , \gpio_defaults[273]  }),
+    .mgmt_gpio_in(\mgmt_io_in[21] ),
+    .mgmt_gpio_oeb(\mprj_io_one[21] ),
+    .mgmt_gpio_out(\mgmt_io_out[21] ),
+    .one(\mprj_io_one[21] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[21] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[21] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[21] ),
+    .pad_gpio_dm({ \mprj_io_dm[65] , \mprj_io_dm[64] , \mprj_io_dm[63]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[21] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[21] ),
+    .pad_gpio_in(\mprj_io_in[21] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[21] ),
+    .pad_gpio_out(\mprj_io_out[21] ),
+    .pad_gpio_outenb(\mprj_io_oeb[21] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[21] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[21] ),
+    .resetn(\gpio_resetn_2[3] ),
+    .resetn_out(\gpio_resetn_2[2] ),
+    .serial_clock(\gpio_clock_2[3] ),
+    .serial_clock_out(\gpio_clock_2[2] ),
+    .serial_data_in(\gpio_serial_link_2[3] ),
+    .serial_data_out(\gpio_serial_link_2[2] ),
+    .serial_load(\gpio_load_2[3] ),
+    .serial_load_out(\gpio_load_2[2] ),
+    .user_gpio_in(\user_io_in[21] ),
+    .user_gpio_oeb(\user_io_oeb[21] ),
+    .user_gpio_out(\user_io_out[21] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[3]  (
+    .gpio_defaults({ \gpio_defaults[298] , \gpio_defaults[297] , \gpio_defaults[296] , \gpio_defaults[295] , \gpio_defaults[294] , \gpio_defaults[293] , \gpio_defaults[292] , \gpio_defaults[291] , \gpio_defaults[290] , \gpio_defaults[289] , \gpio_defaults[288] , \gpio_defaults[287] , \gpio_defaults[286]  }),
+    .mgmt_gpio_in(\mgmt_io_in[22] ),
+    .mgmt_gpio_oeb(\mprj_io_one[22] ),
+    .mgmt_gpio_out(\mgmt_io_out[22] ),
+    .one(\mprj_io_one[22] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[22] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[22] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[22] ),
+    .pad_gpio_dm({ \mprj_io_dm[68] , \mprj_io_dm[67] , \mprj_io_dm[66]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[22] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[22] ),
+    .pad_gpio_in(\mprj_io_in[22] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[22] ),
+    .pad_gpio_out(\mprj_io_out[22] ),
+    .pad_gpio_outenb(\mprj_io_oeb[22] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[22] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[22] ),
+    .resetn(\gpio_resetn_2[4] ),
+    .resetn_out(\gpio_resetn_2[3] ),
+    .serial_clock(\gpio_clock_2[4] ),
+    .serial_clock_out(\gpio_clock_2[3] ),
+    .serial_data_in(\gpio_serial_link_2[4] ),
+    .serial_data_out(\gpio_serial_link_2[3] ),
+    .serial_load(\gpio_load_2[4] ),
+    .serial_load_out(\gpio_load_2[3] ),
+    .user_gpio_in(\user_io_in[22] ),
+    .user_gpio_oeb(\user_io_oeb[22] ),
+    .user_gpio_out(\user_io_out[22] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[4]  (
+    .gpio_defaults({ \gpio_defaults[311] , \gpio_defaults[310] , \gpio_defaults[309] , \gpio_defaults[308] , \gpio_defaults[307] , \gpio_defaults[306] , \gpio_defaults[305] , \gpio_defaults[304] , \gpio_defaults[303] , \gpio_defaults[302] , \gpio_defaults[301] , \gpio_defaults[300] , \gpio_defaults[299]  }),
+    .mgmt_gpio_in(\mgmt_io_in[23] ),
+    .mgmt_gpio_oeb(\mprj_io_one[23] ),
+    .mgmt_gpio_out(\mgmt_io_out[23] ),
+    .one(\mprj_io_one[23] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[23] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[23] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[23] ),
+    .pad_gpio_dm({ \mprj_io_dm[71] , \mprj_io_dm[70] , \mprj_io_dm[69]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[23] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[23] ),
+    .pad_gpio_in(\mprj_io_in[23] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[23] ),
+    .pad_gpio_out(\mprj_io_out[23] ),
+    .pad_gpio_outenb(\mprj_io_oeb[23] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[23] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[23] ),
+    .resetn(\gpio_resetn_2[5] ),
+    .resetn_out(\gpio_resetn_2[4] ),
+    .serial_clock(\gpio_clock_2[5] ),
+    .serial_clock_out(\gpio_clock_2[4] ),
+    .serial_data_in(\gpio_serial_link_2[5] ),
+    .serial_data_out(\gpio_serial_link_2[4] ),
+    .serial_load(\gpio_load_2[5] ),
+    .serial_load_out(\gpio_load_2[4] ),
+    .user_gpio_in(\user_io_in[23] ),
+    .user_gpio_oeb(\user_io_oeb[23] ),
+    .user_gpio_out(\user_io_out[23] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[5]  (
+    .gpio_defaults({ \gpio_defaults[324] , \gpio_defaults[323] , \gpio_defaults[322] , \gpio_defaults[321] , \gpio_defaults[320] , \gpio_defaults[319] , \gpio_defaults[318] , \gpio_defaults[317] , \gpio_defaults[316] , \gpio_defaults[315] , \gpio_defaults[314] , \gpio_defaults[313] , \gpio_defaults[312]  }),
+    .mgmt_gpio_in(\mgmt_io_in[24] ),
+    .mgmt_gpio_oeb(\mprj_io_one[24] ),
+    .mgmt_gpio_out(\mgmt_io_out[24] ),
+    .one(\mprj_io_one[24] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[24] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[24] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[24] ),
+    .pad_gpio_dm({ \mprj_io_dm[74] , \mprj_io_dm[73] , \mprj_io_dm[72]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[24] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[24] ),
+    .pad_gpio_in(\mprj_io_in[24] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[24] ),
+    .pad_gpio_out(\mprj_io_out[24] ),
+    .pad_gpio_outenb(\mprj_io_oeb[24] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[24] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[24] ),
+    .resetn(\gpio_resetn_2[6] ),
+    .resetn_out(\gpio_resetn_2[5] ),
+    .serial_clock(\gpio_clock_2[6] ),
+    .serial_clock_out(\gpio_clock_2[5] ),
+    .serial_data_in(\gpio_serial_link_2[6] ),
+    .serial_data_out(\gpio_serial_link_2[5] ),
+    .serial_load(\gpio_load_2[6] ),
+    .serial_load_out(\gpio_load_2[5] ),
+    .user_gpio_in(\user_io_in[24] ),
+    .user_gpio_oeb(\user_io_oeb[24] ),
+    .user_gpio_out(\user_io_out[24] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[6]  (
+    .gpio_defaults({ \gpio_defaults[337] , \gpio_defaults[336] , \gpio_defaults[335] , \gpio_defaults[334] , \gpio_defaults[333] , \gpio_defaults[332] , \gpio_defaults[331] , \gpio_defaults[330] , \gpio_defaults[329] , \gpio_defaults[328] , \gpio_defaults[327] , \gpio_defaults[326] , \gpio_defaults[325]  }),
+    .mgmt_gpio_in(\mgmt_io_in[25] ),
+    .mgmt_gpio_oeb(\mprj_io_one[25] ),
+    .mgmt_gpio_out(\mgmt_io_out[25] ),
+    .one(\mprj_io_one[25] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[25] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[25] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[25] ),
+    .pad_gpio_dm({ \mprj_io_dm[77] , \mprj_io_dm[76] , \mprj_io_dm[75]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[25] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[25] ),
+    .pad_gpio_in(\mprj_io_in[25] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[25] ),
+    .pad_gpio_out(\mprj_io_out[25] ),
+    .pad_gpio_outenb(\mprj_io_oeb[25] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[25] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[25] ),
+    .resetn(\gpio_resetn_2[7] ),
+    .resetn_out(\gpio_resetn_2[6] ),
+    .serial_clock(\gpio_clock_2[7] ),
+    .serial_clock_out(\gpio_clock_2[6] ),
+    .serial_data_in(\gpio_serial_link_2[7] ),
+    .serial_data_out(\gpio_serial_link_2[6] ),
+    .serial_load(\gpio_load_2[7] ),
+    .serial_load_out(\gpio_load_2[6] ),
+    .user_gpio_in(\user_io_in[25] ),
+    .user_gpio_oeb(\user_io_oeb[25] ),
+    .user_gpio_out(\user_io_out[25] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[7]  (
+    .gpio_defaults({ \gpio_defaults[350] , \gpio_defaults[349] , \gpio_defaults[348] , \gpio_defaults[347] , \gpio_defaults[346] , \gpio_defaults[345] , \gpio_defaults[344] , \gpio_defaults[343] , \gpio_defaults[342] , \gpio_defaults[341] , \gpio_defaults[340] , \gpio_defaults[339] , \gpio_defaults[338]  }),
+    .mgmt_gpio_in(\mgmt_io_in[26] ),
+    .mgmt_gpio_oeb(\mprj_io_one[26] ),
+    .mgmt_gpio_out(\mgmt_io_out[26] ),
+    .one(\mprj_io_one[26] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[26] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[26] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[26] ),
+    .pad_gpio_dm({ \mprj_io_dm[80] , \mprj_io_dm[79] , \mprj_io_dm[78]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[26] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[26] ),
+    .pad_gpio_in(\mprj_io_in[26] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[26] ),
+    .pad_gpio_out(\mprj_io_out[26] ),
+    .pad_gpio_outenb(\mprj_io_oeb[26] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[26] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[26] ),
+    .resetn(\gpio_resetn_2[8] ),
+    .resetn_out(\gpio_resetn_2[7] ),
+    .serial_clock(\gpio_clock_2[8] ),
+    .serial_clock_out(\gpio_clock_2[7] ),
+    .serial_data_in(\gpio_serial_link_2[8] ),
+    .serial_data_out(\gpio_serial_link_2[7] ),
+    .serial_load(\gpio_load_2[8] ),
+    .serial_load_out(\gpio_load_2[7] ),
+    .user_gpio_in(\user_io_in[26] ),
+    .user_gpio_oeb(\user_io_oeb[26] ),
+    .user_gpio_out(\user_io_out[26] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[8]  (
+    .gpio_defaults({ \gpio_defaults[363] , \gpio_defaults[362] , \gpio_defaults[361] , \gpio_defaults[360] , \gpio_defaults[359] , \gpio_defaults[358] , \gpio_defaults[357] , \gpio_defaults[356] , \gpio_defaults[355] , \gpio_defaults[354] , \gpio_defaults[353] , \gpio_defaults[352] , \gpio_defaults[351]  }),
+    .mgmt_gpio_in(\mgmt_io_in[27] ),
+    .mgmt_gpio_oeb(\mprj_io_one[27] ),
+    .mgmt_gpio_out(\mgmt_io_out[27] ),
+    .one(\mprj_io_one[27] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[27] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[27] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[27] ),
+    .pad_gpio_dm({ \mprj_io_dm[83] , \mprj_io_dm[82] , \mprj_io_dm[81]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[27] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[27] ),
+    .pad_gpio_in(\mprj_io_in[27] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[27] ),
+    .pad_gpio_out(\mprj_io_out[27] ),
+    .pad_gpio_outenb(\mprj_io_oeb[27] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[27] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[27] ),
+    .resetn(\gpio_resetn_2[9] ),
+    .resetn_out(\gpio_resetn_2[8] ),
+    .serial_clock(\gpio_clock_2[9] ),
+    .serial_clock_out(\gpio_clock_2[8] ),
+    .serial_data_in(\gpio_serial_link_2[9] ),
+    .serial_data_out(\gpio_serial_link_2[8] ),
+    .serial_load(\gpio_load_2[9] ),
+    .serial_load_out(\gpio_load_2[8] ),
+    .user_gpio_in(\user_io_in[27] ),
+    .user_gpio_oeb(\user_io_oeb[27] ),
+    .user_gpio_out(\user_io_out[27] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[9]  (
+    .gpio_defaults({ \gpio_defaults[376] , \gpio_defaults[375] , \gpio_defaults[374] , \gpio_defaults[373] , \gpio_defaults[372] , \gpio_defaults[371] , \gpio_defaults[370] , \gpio_defaults[369] , \gpio_defaults[368] , \gpio_defaults[367] , \gpio_defaults[366] , \gpio_defaults[365] , \gpio_defaults[364]  }),
+    .mgmt_gpio_in(\mgmt_io_in[28] ),
+    .mgmt_gpio_oeb(\mprj_io_one[28] ),
+    .mgmt_gpio_out(\mgmt_io_out[28] ),
+    .one(\mprj_io_one[28] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[28] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[28] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[28] ),
+    .pad_gpio_dm({ \mprj_io_dm[86] , \mprj_io_dm[85] , \mprj_io_dm[84]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[28] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[28] ),
+    .pad_gpio_in(\mprj_io_in[28] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[28] ),
+    .pad_gpio_out(\mprj_io_out[28] ),
+    .pad_gpio_outenb(\mprj_io_oeb[28] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[28] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[28] ),
+    .resetn(\gpio_resetn_2[10] ),
+    .resetn_out(\gpio_resetn_2[9] ),
+    .serial_clock(\gpio_clock_2[10] ),
+    .serial_clock_out(\gpio_clock_2[9] ),
+    .serial_data_in(\gpio_serial_link_2[10] ),
+    .serial_data_out(\gpio_serial_link_2[9] ),
+    .serial_load(\gpio_load_2[10] ),
+    .serial_load_out(\gpio_load_2[9] ),
+    .user_gpio_in(\user_io_in[28] ),
+    .user_gpio_oeb(\user_io_oeb[28] ),
+    .user_gpio_out(\user_io_out[28] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_defaults_block_1803 gpio_defaults_block_0 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[12] , \gpio_defaults[11] , \gpio_defaults[10] , \gpio_defaults[9] , \gpio_defaults[8] , \gpio_defaults[7] , \gpio_defaults[6] , \gpio_defaults[5] , \gpio_defaults[4] , \gpio_defaults[3] , \gpio_defaults[2] , \gpio_defaults[1] , \gpio_defaults[0]  })
+  );
+  gpio_defaults_block_1803 gpio_defaults_block_1 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[25] , \gpio_defaults[24] , \gpio_defaults[23] , \gpio_defaults[22] , \gpio_defaults[21] , \gpio_defaults[20] , \gpio_defaults[19] , \gpio_defaults[18] , \gpio_defaults[17] , \gpio_defaults[16] , \gpio_defaults[15] , \gpio_defaults[14] , \gpio_defaults[13]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_10 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[142] , \gpio_defaults[141] , \gpio_defaults[140] , \gpio_defaults[139] , \gpio_defaults[138] , \gpio_defaults[137] , \gpio_defaults[136] , \gpio_defaults[135] , \gpio_defaults[134] , \gpio_defaults[133] , \gpio_defaults[132] , \gpio_defaults[131] , \gpio_defaults[130]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_11 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[155] , \gpio_defaults[154] , \gpio_defaults[153] , \gpio_defaults[152] , \gpio_defaults[151] , \gpio_defaults[150] , \gpio_defaults[149] , \gpio_defaults[148] , \gpio_defaults[147] , \gpio_defaults[146] , \gpio_defaults[145] , \gpio_defaults[144] , \gpio_defaults[143]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_12 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[168] , \gpio_defaults[167] , \gpio_defaults[166] , \gpio_defaults[165] , \gpio_defaults[164] , \gpio_defaults[163] , \gpio_defaults[162] , \gpio_defaults[161] , \gpio_defaults[160] , \gpio_defaults[159] , \gpio_defaults[158] , \gpio_defaults[157] , \gpio_defaults[156]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_13 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[181] , \gpio_defaults[180] , \gpio_defaults[179] , \gpio_defaults[178] , \gpio_defaults[177] , \gpio_defaults[176] , \gpio_defaults[175] , \gpio_defaults[174] , \gpio_defaults[173] , \gpio_defaults[172] , \gpio_defaults[171] , \gpio_defaults[170] , \gpio_defaults[169]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_14 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[194] , \gpio_defaults[193] , \gpio_defaults[192] , \gpio_defaults[191] , \gpio_defaults[190] , \gpio_defaults[189] , \gpio_defaults[188] , \gpio_defaults[187] , \gpio_defaults[186] , \gpio_defaults[185] , \gpio_defaults[184] , \gpio_defaults[183] , \gpio_defaults[182]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_15 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[207] , \gpio_defaults[206] , \gpio_defaults[205] , \gpio_defaults[204] , \gpio_defaults[203] , \gpio_defaults[202] , \gpio_defaults[201] , \gpio_defaults[200] , \gpio_defaults[199] , \gpio_defaults[198] , \gpio_defaults[197] , \gpio_defaults[196] , \gpio_defaults[195]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_16 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[220] , \gpio_defaults[219] , \gpio_defaults[218] , \gpio_defaults[217] , \gpio_defaults[216] , \gpio_defaults[215] , \gpio_defaults[214] , \gpio_defaults[213] , \gpio_defaults[212] , \gpio_defaults[211] , \gpio_defaults[210] , \gpio_defaults[209] , \gpio_defaults[208]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_17 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[233] , \gpio_defaults[232] , \gpio_defaults[231] , \gpio_defaults[230] , \gpio_defaults[229] , \gpio_defaults[228] , \gpio_defaults[227] , \gpio_defaults[226] , \gpio_defaults[225] , \gpio_defaults[224] , \gpio_defaults[223] , \gpio_defaults[222] , \gpio_defaults[221]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_18 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[246] , \gpio_defaults[245] , \gpio_defaults[244] , \gpio_defaults[243] , \gpio_defaults[242] , \gpio_defaults[241] , \gpio_defaults[240] , \gpio_defaults[239] , \gpio_defaults[238] , \gpio_defaults[237] , \gpio_defaults[236] , \gpio_defaults[235] , \gpio_defaults[234]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_19 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[259] , \gpio_defaults[258] , \gpio_defaults[257] , \gpio_defaults[256] , \gpio_defaults[255] , \gpio_defaults[254] , \gpio_defaults[253] , \gpio_defaults[252] , \gpio_defaults[251] , \gpio_defaults[250] , \gpio_defaults[249] , \gpio_defaults[248] , \gpio_defaults[247]  })
+  );
+  gpio_defaults_block_0403 gpio_defaults_block_2 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[38] , \gpio_defaults[37] , \gpio_defaults[36] , \gpio_defaults[35] , \gpio_defaults[34] , \gpio_defaults[33] , \gpio_defaults[32] , \gpio_defaults[31] , \gpio_defaults[30] , \gpio_defaults[29] , \gpio_defaults[28] , \gpio_defaults[27] , \gpio_defaults[26]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_20 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[272] , \gpio_defaults[271] , \gpio_defaults[270] , \gpio_defaults[269] , \gpio_defaults[268] , \gpio_defaults[267] , \gpio_defaults[266] , \gpio_defaults[265] , \gpio_defaults[264] , \gpio_defaults[263] , \gpio_defaults[262] , \gpio_defaults[261] , \gpio_defaults[260]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_21 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[285] , \gpio_defaults[284] , \gpio_defaults[283] , \gpio_defaults[282] , \gpio_defaults[281] , \gpio_defaults[280] , \gpio_defaults[279] , \gpio_defaults[278] , \gpio_defaults[277] , \gpio_defaults[276] , \gpio_defaults[275] , \gpio_defaults[274] , \gpio_defaults[273]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_22 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[298] , \gpio_defaults[297] , \gpio_defaults[296] , \gpio_defaults[295] , \gpio_defaults[294] , \gpio_defaults[293] , \gpio_defaults[292] , \gpio_defaults[291] , \gpio_defaults[290] , \gpio_defaults[289] , \gpio_defaults[288] , \gpio_defaults[287] , \gpio_defaults[286]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_23 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[311] , \gpio_defaults[310] , \gpio_defaults[309] , \gpio_defaults[308] , \gpio_defaults[307] , \gpio_defaults[306] , \gpio_defaults[305] , \gpio_defaults[304] , \gpio_defaults[303] , \gpio_defaults[302] , \gpio_defaults[301] , \gpio_defaults[300] , \gpio_defaults[299]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_24 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[324] , \gpio_defaults[323] , \gpio_defaults[322] , \gpio_defaults[321] , \gpio_defaults[320] , \gpio_defaults[319] , \gpio_defaults[318] , \gpio_defaults[317] , \gpio_defaults[316] , \gpio_defaults[315] , \gpio_defaults[314] , \gpio_defaults[313] , \gpio_defaults[312]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_25 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[337] , \gpio_defaults[336] , \gpio_defaults[335] , \gpio_defaults[334] , \gpio_defaults[333] , \gpio_defaults[332] , \gpio_defaults[331] , \gpio_defaults[330] , \gpio_defaults[329] , \gpio_defaults[328] , \gpio_defaults[327] , \gpio_defaults[326] , \gpio_defaults[325]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_26 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[350] , \gpio_defaults[349] , \gpio_defaults[348] , \gpio_defaults[347] , \gpio_defaults[346] , \gpio_defaults[345] , \gpio_defaults[344] , \gpio_defaults[343] , \gpio_defaults[342] , \gpio_defaults[341] , \gpio_defaults[340] , \gpio_defaults[339] , \gpio_defaults[338]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_27 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[363] , \gpio_defaults[362] , \gpio_defaults[361] , \gpio_defaults[360] , \gpio_defaults[359] , \gpio_defaults[358] , \gpio_defaults[357] , \gpio_defaults[356] , \gpio_defaults[355] , \gpio_defaults[354] , \gpio_defaults[353] , \gpio_defaults[352] , \gpio_defaults[351]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_28 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[376] , \gpio_defaults[375] , \gpio_defaults[374] , \gpio_defaults[373] , \gpio_defaults[372] , \gpio_defaults[371] , \gpio_defaults[370] , \gpio_defaults[369] , \gpio_defaults[368] , \gpio_defaults[367] , \gpio_defaults[366] , \gpio_defaults[365] , \gpio_defaults[364]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_29 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[389] , \gpio_defaults[388] , \gpio_defaults[387] , \gpio_defaults[386] , \gpio_defaults[385] , \gpio_defaults[384] , \gpio_defaults[383] , \gpio_defaults[382] , \gpio_defaults[381] , \gpio_defaults[380] , \gpio_defaults[379] , \gpio_defaults[378] , \gpio_defaults[377]  })
+  );
+  gpio_defaults_block_0801 gpio_defaults_block_3 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[51] , \gpio_defaults[50] , \gpio_defaults[49] , \gpio_defaults[48] , \gpio_defaults[47] , \gpio_defaults[46] , \gpio_defaults[45] , \gpio_defaults[44] , \gpio_defaults[43] , \gpio_defaults[42] , \gpio_defaults[41] , \gpio_defaults[40] , \gpio_defaults[39]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_30 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[402] , \gpio_defaults[401] , \gpio_defaults[400] , \gpio_defaults[399] , \gpio_defaults[398] , \gpio_defaults[397] , \gpio_defaults[396] , \gpio_defaults[395] , \gpio_defaults[394] , \gpio_defaults[393] , \gpio_defaults[392] , \gpio_defaults[391] , \gpio_defaults[390]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_31 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[415] , \gpio_defaults[414] , \gpio_defaults[413] , \gpio_defaults[412] , \gpio_defaults[411] , \gpio_defaults[410] , \gpio_defaults[409] , \gpio_defaults[408] , \gpio_defaults[407] , \gpio_defaults[406] , \gpio_defaults[405] , \gpio_defaults[404] , \gpio_defaults[403]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_32 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[428] , \gpio_defaults[427] , \gpio_defaults[426] , \gpio_defaults[425] , \gpio_defaults[424] , \gpio_defaults[423] , \gpio_defaults[422] , \gpio_defaults[421] , \gpio_defaults[420] , \gpio_defaults[419] , \gpio_defaults[418] , \gpio_defaults[417] , \gpio_defaults[416]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_33 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[441] , \gpio_defaults[440] , \gpio_defaults[439] , \gpio_defaults[438] , \gpio_defaults[437] , \gpio_defaults[436] , \gpio_defaults[435] , \gpio_defaults[434] , \gpio_defaults[433] , \gpio_defaults[432] , \gpio_defaults[431] , \gpio_defaults[430] , \gpio_defaults[429]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_34 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[454] , \gpio_defaults[453] , \gpio_defaults[452] , \gpio_defaults[451] , \gpio_defaults[450] , \gpio_defaults[449] , \gpio_defaults[448] , \gpio_defaults[447] , \gpio_defaults[446] , \gpio_defaults[445] , \gpio_defaults[444] , \gpio_defaults[443] , \gpio_defaults[442]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_35 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[467] , \gpio_defaults[466] , \gpio_defaults[465] , \gpio_defaults[464] , \gpio_defaults[463] , \gpio_defaults[462] , \gpio_defaults[461] , \gpio_defaults[460] , \gpio_defaults[459] , \gpio_defaults[458] , \gpio_defaults[457] , \gpio_defaults[456] , \gpio_defaults[455]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_36 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[480] , \gpio_defaults[479] , \gpio_defaults[478] , \gpio_defaults[477] , \gpio_defaults[476] , \gpio_defaults[475] , \gpio_defaults[474] , \gpio_defaults[473] , \gpio_defaults[472] , \gpio_defaults[471] , \gpio_defaults[470] , \gpio_defaults[469] , \gpio_defaults[468]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_37 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[493] , \gpio_defaults[492] , \gpio_defaults[491] , \gpio_defaults[490] , \gpio_defaults[489] , \gpio_defaults[488] , \gpio_defaults[487] , \gpio_defaults[486] , \gpio_defaults[485] , \gpio_defaults[484] , \gpio_defaults[483] , \gpio_defaults[482] , \gpio_defaults[481]  })
+  );
+  gpio_defaults_block_0403 gpio_defaults_block_4 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[64] , \gpio_defaults[63] , \gpio_defaults[62] , \gpio_defaults[61] , \gpio_defaults[60] , \gpio_defaults[59] , \gpio_defaults[58] , \gpio_defaults[57] , \gpio_defaults[56] , \gpio_defaults[55] , \gpio_defaults[54] , \gpio_defaults[53] , \gpio_defaults[52]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_5 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[77] , \gpio_defaults[76] , \gpio_defaults[75] , \gpio_defaults[74] , \gpio_defaults[73] , \gpio_defaults[72] , \gpio_defaults[71] , \gpio_defaults[70] , \gpio_defaults[69] , \gpio_defaults[68] , \gpio_defaults[67] , \gpio_defaults[66] , \gpio_defaults[65]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_6 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[90] , \gpio_defaults[89] , \gpio_defaults[88] , \gpio_defaults[87] , \gpio_defaults[86] , \gpio_defaults[85] , \gpio_defaults[84] , \gpio_defaults[83] , \gpio_defaults[82] , \gpio_defaults[81] , \gpio_defaults[80] , \gpio_defaults[79] , \gpio_defaults[78]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_7 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[103] , \gpio_defaults[102] , \gpio_defaults[101] , \gpio_defaults[100] , \gpio_defaults[99] , \gpio_defaults[98] , \gpio_defaults[97] , \gpio_defaults[96] , \gpio_defaults[95] , \gpio_defaults[94] , \gpio_defaults[93] , \gpio_defaults[92] , \gpio_defaults[91]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_8 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[116] , \gpio_defaults[115] , \gpio_defaults[114] , \gpio_defaults[113] , \gpio_defaults[112] , \gpio_defaults[111] , \gpio_defaults[110] , \gpio_defaults[109] , \gpio_defaults[108] , \gpio_defaults[107] , \gpio_defaults[106] , \gpio_defaults[105] , \gpio_defaults[104]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_9 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[129] , \gpio_defaults[128] , \gpio_defaults[127] , \gpio_defaults[126] , \gpio_defaults[125] , \gpio_defaults[124] , \gpio_defaults[123] , \gpio_defaults[122] , \gpio_defaults[121] , \gpio_defaults[120] , \gpio_defaults[119] , \gpio_defaults[118] , \gpio_defaults[117]  })
+  );
+  housekeeping housekeeping (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .debug_in(debug_in),
+    .debug_mode(debug_mode),
+    .debug_oeb(debug_oeb),
+    .debug_out(debug_out),
+    .irq({ \irq_spi[2] , \irq_spi[1] , \irq_spi[0]  }),
+    .mask_rev_in({ \mask_rev[31] , \mask_rev[30] , \mask_rev[29] , \mask_rev[28] , \mask_rev[27] , \mask_rev[26] , \mask_rev[25] , \mask_rev[24] , \mask_rev[23] , \mask_rev[22] , \mask_rev[21] , \mask_rev[20] , \mask_rev[19] , \mask_rev[18] , \mask_rev[17] , \mask_rev[16] , \mask_rev[15] , \mask_rev[14] , \mask_rev[13] , \mask_rev[12] , \mask_rev[11] , \mask_rev[10] , \mask_rev[9] , \mask_rev[8] , \mask_rev[7] , \mask_rev[6] , \mask_rev[5] , \mask_rev[4] , \mask_rev[3] , \mask_rev[2] , \mask_rev[1] , \mask_rev[0]  }),
+    .mgmt_gpio_in({ \mgmt_io_in_hk[37] , \mgmt_io_in_hk[36] , \mgmt_io_in_hk[35] , \mgmt_io_in_hk[34] , \mgmt_io_in_hk[33] , \mgmt_io_in_hk[32] , \mgmt_io_in_hk[31] , \mgmt_io_in_hk[30] , \mgmt_io_in_hk[29] , \mgmt_io_in_hk[28] , \mgmt_io_in_hk[27] , \mgmt_io_in_hk[26] , \mgmt_io_in_hk[25] , \mgmt_io_in_hk[24] , \mgmt_io_in_hk[23] , \mgmt_io_in_hk[22] , \mgmt_io_in_hk[21] , \mgmt_io_in_hk[20] , \mgmt_io_in_hk[19] , \mgmt_io_in_hk[18] , \mgmt_io_in_hk[17] , \mgmt_io_in_hk[16] , \mgmt_io_in_hk[15] , \mgmt_io_in_hk[14] , \mgmt_io_in_hk[13] , \mgmt_io_in_hk[12] , \mgmt_io_in_hk[11] , \mgmt_io_in_hk[10] , \mgmt_io_in_hk[9] , \mgmt_io_in_hk[8] , \mgmt_io_in_hk[7] , \mgmt_io_in[6] , \mgmt_io_in[5] , \mgmt_io_in[4] , \mgmt_io_in[3] , \mgmt_io_in[2] , \mgmt_io_in[1] , \mgmt_io_in[0]  }),
+    .mgmt_gpio_oeb({ \mgmt_io_oeb_hk[37] , \mgmt_io_oeb_hk[36] , \mgmt_io_oeb_hk[35] , \mgmt_io_oeb[34] , \mgmt_io_oeb[33] , \mgmt_io_oeb[32] , \mgmt_io_oeb[31] , \mgmt_io_oeb[30] , \mgmt_io_oeb[29] , \mgmt_io_oeb[28] , \mgmt_io_oeb[27] , \mgmt_io_oeb[26] , \mgmt_io_oeb[25] , \mgmt_io_oeb[24] , \mgmt_io_oeb[23] , \mgmt_io_oeb[22] , \mgmt_io_oeb[21] , \mgmt_io_oeb[20] , \mgmt_io_oeb[19] , \mgmt_io_oeb[18] , \mgmt_io_oeb[17] , \mgmt_io_oeb[16] , \mgmt_io_oeb[15] , \mgmt_io_oeb[14] , \mgmt_io_oeb[13] , \mgmt_io_oeb[12] , \mgmt_io_oeb[11] , \mgmt_io_oeb[10] , \mgmt_io_oeb[9] , \mgmt_io_oeb[8] , \mgmt_io_oeb[7] , \mgmt_io_oeb[6] , \mgmt_io_oeb[5] , \mgmt_io_oeb[4] , \mgmt_io_oeb[3] , \mgmt_io_oeb[2] , \mgmt_io_oeb[1] , \mgmt_io_oeb[0]  }),
+    .mgmt_gpio_out({ \mgmt_io_out_hk[37] , \mgmt_io_out_hk[36] , \mgmt_io_out_hk[35] , \mgmt_io_out_hk[34] , \mgmt_io_out_hk[33] , \mgmt_io_out_hk[32] , \mgmt_io_out_hk[31] , \mgmt_io_out_hk[30] , \mgmt_io_out_hk[29] , \mgmt_io_out_hk[28] , \mgmt_io_out_hk[27] , \mgmt_io_out_hk[26] , \mgmt_io_out_hk[25] , \mgmt_io_out_hk[24] , \mgmt_io_out_hk[23] , \mgmt_io_out_hk[22] , \mgmt_io_out_hk[21] , \mgmt_io_out_hk[20] , \mgmt_io_out_hk[19] , \mgmt_io_out_hk[18] , \mgmt_io_out_hk[17] , \mgmt_io_out_hk[16] , \mgmt_io_out_hk[15] , \mgmt_io_out_hk[14] , \mgmt_io_out_hk[13] , \mgmt_io_out_hk[12] , \mgmt_io_out_hk[11] , \mgmt_io_out_hk[10] , \mgmt_io_out_hk[9] , \mgmt_io_out_hk[8] , \mgmt_io_out_hk[7] , \mgmt_io_out[6] , \mgmt_io_out[5] , \mgmt_io_out[4] , \mgmt_io_out[3] , \mgmt_io_out[2] , \mgmt_io_out[1] , \mgmt_io_out[0]  }),
+    .pad_flash_clk(flash_clk_frame),
+    .pad_flash_clk_oeb(flash_clk_oeb),
+    .pad_flash_csb(flash_csb_frame),
+    .pad_flash_csb_oeb(flash_csb_oeb),
+    .pad_flash_io0_di(flash_io0_di_buf),
+    .pad_flash_io0_do(flash_io0_do),
+    .pad_flash_io0_ieb(flash_io0_ieb),
+    .pad_flash_io0_oeb(flash_io0_oeb),
+    .pad_flash_io1_di(flash_io1_di_buf),
+    .pad_flash_io1_do(flash_io1_do),
+    .pad_flash_io1_ieb(flash_io1_ieb),
+    .pad_flash_io1_oeb(flash_io1_oeb),
+    .pll90_sel({ \spi_pll90_sel[2] , \spi_pll90_sel[1] , \spi_pll90_sel[0]  }),
+    .pll_bypass(ext_clk_sel),
+    .pll_dco_ena(spi_pll_dco_ena),
+    .pll_div({ \spi_pll_div[4] , \spi_pll_div[3] , \spi_pll_div[2] , \spi_pll_div[1] , \spi_pll_div[0]  }),
+    .pll_ena(spi_pll_ena),
+    .pll_sel({ \spi_pll_sel[2] , \spi_pll_sel[1] , \spi_pll_sel[0]  }),
+    .pll_trim({ \spi_pll_trim[25] , \spi_pll_trim[24] , \spi_pll_trim[23] , \spi_pll_trim[22] , \spi_pll_trim[21] , \spi_pll_trim[20] , \spi_pll_trim[19] , \spi_pll_trim[18] , \spi_pll_trim[17] , \spi_pll_trim[16] , \spi_pll_trim[15] , \spi_pll_trim[14] , \spi_pll_trim[13] , \spi_pll_trim[12] , \spi_pll_trim[11] , \spi_pll_trim[10] , \spi_pll_trim[9] , \spi_pll_trim[8] , \spi_pll_trim[7] , \spi_pll_trim[6] , \spi_pll_trim[5] , \spi_pll_trim[4] , \spi_pll_trim[3] , \spi_pll_trim[2] , \spi_pll_trim[1] , \spi_pll_trim[0]  }),
+    .porb(porb_l),
+    .pwr_ctrl_out({ \pwr_ctrl_nc[3] , \pwr_ctrl_nc[2] , \pwr_ctrl_nc[1] , \pwr_ctrl_nc[0]  }),
+    .qspi_enabled(qspi_enabled),
+    .reset(ext_reset),
+    .ser_rx(ser_rx),
+    .ser_tx(ser_tx),
+    .serial_clock(\gpio_clock_1_shifted[0] ),
+    .serial_data_1(\gpio_serial_link_1_shifted[0] ),
+    .serial_data_2(mprj_io_loader_data_2),
+    .serial_load(\gpio_load_1_shifted[0] ),
+    .serial_resetn(\gpio_resetn_1_shifted[0] ),
+    .spi_csb(spi_csb),
+    .spi_enabled(spi_enabled),
+    .spi_sck(spi_sck),
+    .spi_sdi(spi_sdi),
+    .spi_sdo(spi_sdo),
+    .spi_sdoenb(spi_sdoenb),
+    .spimemio_flash_clk(flash_clk_core),
+    .spimemio_flash_csb(flash_csb_core),
+    .spimemio_flash_io0_di(flash_io0_di_core),
+    .spimemio_flash_io0_do(flash_io0_do_core),
+    .spimemio_flash_io0_oeb(flash_io0_oeb_core),
+    .spimemio_flash_io1_di(flash_io1_di_core),
+    .spimemio_flash_io1_do(flash_io1_do_core),
+    .spimemio_flash_io1_oeb(flash_io1_oeb_core),
+    .spimemio_flash_io2_di(flash_io2_di_core),
+    .spimemio_flash_io2_do(flash_io2_do_core),
+    .spimemio_flash_io2_oeb(flash_io2_oeb_core),
+    .spimemio_flash_io3_di(flash_io3_di_core),
+    .spimemio_flash_io3_do(flash_io3_do_core),
+    .spimemio_flash_io3_oeb(flash_io3_oeb_core),
+    .trap(trap),
+    .uart_enabled(uart_enabled),
+    .user_clock(caravel_clk2),
+    .usr1_vcc_pwrgood(mprj_vcc_pwrgood),
+    .usr1_vdd_pwrgood(mprj_vdd_pwrgood),
+    .usr2_vcc_pwrgood(mprj2_vcc_pwrgood),
+    .usr2_vdd_pwrgood(mprj2_vdd_pwrgood),
+    .wb_ack_o(hk_ack_i),
+    .wb_adr_i({ \mprj_adr_o_core[31] , \mprj_adr_o_core[30] , \mprj_adr_o_core[29] , \mprj_adr_o_core[28] , \mprj_adr_o_core[27] , \mprj_adr_o_core[26] , \mprj_adr_o_core[25] , \mprj_adr_o_core[24] , \mprj_adr_o_core[23] , \mprj_adr_o_core[22] , \mprj_adr_o_core[21] , \mprj_adr_o_core[20] , \mprj_adr_o_core[19] , \mprj_adr_o_core[18] , \mprj_adr_o_core[17] , \mprj_adr_o_core[16] , \mprj_adr_o_core[15] , \mprj_adr_o_core[14] , \mprj_adr_o_core[13] , \mprj_adr_o_core[12] , \mprj_adr_o_core[11] , \mprj_adr_o_core[10] , \mprj_adr_o_core[9] , \mprj_adr_o_core[8] , \mprj_adr_o_core[7] , \mprj_adr_o_core[6] , \mprj_adr_o_core[5] , \mprj_adr_o_core[4] , \mprj_adr_o_core[3] , \mprj_adr_o_core[2] , \mprj_adr_o_core[1] , \mprj_adr_o_core[0]  }),
+    .wb_clk_i(caravel_clk),
+    .wb_cyc_i(hk_cyc_o),
+    .wb_dat_i({ \mprj_dat_o_core[31] , \mprj_dat_o_core[30] , \mprj_dat_o_core[29] , \mprj_dat_o_core[28] , \mprj_dat_o_core[27] , \mprj_dat_o_core[26] , \mprj_dat_o_core[25] , \mprj_dat_o_core[24] , \mprj_dat_o_core[23] , \mprj_dat_o_core[22] , \mprj_dat_o_core[21] , \mprj_dat_o_core[20] , \mprj_dat_o_core[19] , \mprj_dat_o_core[18] , \mprj_dat_o_core[17] , \mprj_dat_o_core[16] , \mprj_dat_o_core[15] , \mprj_dat_o_core[14] , \mprj_dat_o_core[13] , \mprj_dat_o_core[12] , \mprj_dat_o_core[11] , \mprj_dat_o_core[10] , \mprj_dat_o_core[9] , \mprj_dat_o_core[8] , \mprj_dat_o_core[7] , \mprj_dat_o_core[6] , \mprj_dat_o_core[5] , \mprj_dat_o_core[4] , \mprj_dat_o_core[3] , \mprj_dat_o_core[2] , \mprj_dat_o_core[1] , \mprj_dat_o_core[0]  }),
+    .wb_dat_o({ \hk_dat_i[31] , \hk_dat_i[30] , \hk_dat_i[29] , \hk_dat_i[28] , \hk_dat_i[27] , \hk_dat_i[26] , \hk_dat_i[25] , \hk_dat_i[24] , \hk_dat_i[23] , \hk_dat_i[22] , \hk_dat_i[21] , \hk_dat_i[20] , \hk_dat_i[19] , \hk_dat_i[18] , \hk_dat_i[17] , \hk_dat_i[16] , \hk_dat_i[15] , \hk_dat_i[14] , \hk_dat_i[13] , \hk_dat_i[12] , \hk_dat_i[11] , \hk_dat_i[10] , \hk_dat_i[9] , \hk_dat_i[8] , \hk_dat_i[7] , \hk_dat_i[6] , \hk_dat_i[5] , \hk_dat_i[4] , \hk_dat_i[3] , \hk_dat_i[2] , \hk_dat_i[1] , \hk_dat_i[0]  }),
+    .wb_rstn_i(caravel_rstn),
+    .wb_sel_i({ \mprj_sel_o_core[3] , \mprj_sel_o_core[2] , \mprj_sel_o_core[1] , \mprj_sel_o_core[0]  }),
+    .wb_stb_i(hk_stb_o),
+    .wb_we_i(mprj_we_o_core)
+  );
+  mgmt_protect mgmt_buffers (
+    .caravel_clk(clk_passthru),
+    .caravel_clk2(caravel_clk2),
+    .caravel_rstn(resetn_passthru),
+    .la_data_in_core({ \la_data_in_user[127] , \la_data_in_user[126] , \la_data_in_user[125] , \la_data_in_user[124] , \la_data_in_user[123] , \la_data_in_user[122] , \la_data_in_user[121] , \la_data_in_user[120] , \la_data_in_user[119] , \la_data_in_user[118] , \la_data_in_user[117] , \la_data_in_user[116] , \la_data_in_user[115] , \la_data_in_user[114] , \la_data_in_user[113] , \la_data_in_user[112] , \la_data_in_user[111] , \la_data_in_user[110] , \la_data_in_user[109] , \la_data_in_user[108] , \la_data_in_user[107] , \la_data_in_user[106] , \la_data_in_user[105] , \la_data_in_user[104] , \la_data_in_user[103] , \la_data_in_user[102] , \la_data_in_user[101] , \la_data_in_user[100] , \la_data_in_user[99] , \la_data_in_user[98] , \la_data_in_user[97] , \la_data_in_user[96] , \la_data_in_user[95] , \la_data_in_user[94] , \la_data_in_user[93] , \la_data_in_user[92] , \la_data_in_user[91] , \la_data_in_user[90] , \la_data_in_user[89] , \la_data_in_user[88] , \la_data_in_user[87] , \la_data_in_user[86] , \la_data_in_user[85] , \la_data_in_user[84] , \la_data_in_user[83] , \la_data_in_user[82] , \la_data_in_user[81] , \la_data_in_user[80] , \la_data_in_user[79] , \la_data_in_user[78] , \la_data_in_user[77] , \la_data_in_user[76] , \la_data_in_user[75] , \la_data_in_user[74] , \la_data_in_user[73] , \la_data_in_user[72] , \la_data_in_user[71] , \la_data_in_user[70] , \la_data_in_user[69] , \la_data_in_user[68] , \la_data_in_user[67] , \la_data_in_user[66] , \la_data_in_user[65] , \la_data_in_user[64] , \la_data_in_user[63] , \la_data_in_user[62] , \la_data_in_user[61] , \la_data_in_user[60] , \la_data_in_user[59] , \la_data_in_user[58] , \la_data_in_user[57] , \la_data_in_user[56] , \la_data_in_user[55] , \la_data_in_user[54] , \la_data_in_user[53] , \la_data_in_user[52] , \la_data_in_user[51] , \la_data_in_user[50] , \la_data_in_user[49] , \la_data_in_user[48] , \la_data_in_user[47] , \la_data_in_user[46] , \la_data_in_user[45] , \la_data_in_user[44] , \la_data_in_user[43] , \la_data_in_user[42] , \la_data_in_user[41] , \la_data_in_user[40] , \la_data_in_user[39] , \la_data_in_user[38] , \la_data_in_user[37] , \la_data_in_user[36] , \la_data_in_user[35] , \la_data_in_user[34] , \la_data_in_user[33] , \la_data_in_user[32] , \la_data_in_user[31] , \la_data_in_user[30] , \la_data_in_user[29] , \la_data_in_user[28] , \la_data_in_user[27] , \la_data_in_user[26] , \la_data_in_user[25] , \la_data_in_user[24] , \la_data_in_user[23] , \la_data_in_user[22] , \la_data_in_user[21] , \la_data_in_user[20] , \la_data_in_user[19] , \la_data_in_user[18] , \la_data_in_user[17] , \la_data_in_user[16] , \la_data_in_user[15] , \la_data_in_user[14] , \la_data_in_user[13] , \la_data_in_user[12] , \la_data_in_user[11] , \la_data_in_user[10] , \la_data_in_user[9] , \la_data_in_user[8] , \la_data_in_user[7] , \la_data_in_user[6] , \la_data_in_user[5] , \la_data_in_user[4] , \la_data_in_user[3] , \la_data_in_user[2] , \la_data_in_user[1] , \la_data_in_user[0]  }),
+    .la_data_in_mprj({ \la_data_in_mprj[127] , \la_data_in_mprj[126] , \la_data_in_mprj[125] , \la_data_in_mprj[124] , \la_data_in_mprj[123] , \la_data_in_mprj[122] , \la_data_in_mprj[121] , \la_data_in_mprj[120] , \la_data_in_mprj[119] , \la_data_in_mprj[118] , \la_data_in_mprj[117] , \la_data_in_mprj[116] , \la_data_in_mprj[115] , \la_data_in_mprj[114] , \la_data_in_mprj[113] , \la_data_in_mprj[112] , \la_data_in_mprj[111] , \la_data_in_mprj[110] , \la_data_in_mprj[109] , \la_data_in_mprj[108] , \la_data_in_mprj[107] , \la_data_in_mprj[106] , \la_data_in_mprj[105] , \la_data_in_mprj[104] , \la_data_in_mprj[103] , \la_data_in_mprj[102] , \la_data_in_mprj[101] , \la_data_in_mprj[100] , \la_data_in_mprj[99] , \la_data_in_mprj[98] , \la_data_in_mprj[97] , \la_data_in_mprj[96] , \la_data_in_mprj[95] , \la_data_in_mprj[94] , \la_data_in_mprj[93] , \la_data_in_mprj[92] , \la_data_in_mprj[91] , \la_data_in_mprj[90] , \la_data_in_mprj[89] , \la_data_in_mprj[88] , \la_data_in_mprj[87] , \la_data_in_mprj[86] , \la_data_in_mprj[85] , \la_data_in_mprj[84] , \la_data_in_mprj[83] , \la_data_in_mprj[82] , \la_data_in_mprj[81] , \la_data_in_mprj[80] , \la_data_in_mprj[79] , \la_data_in_mprj[78] , \la_data_in_mprj[77] , \la_data_in_mprj[76] , \la_data_in_mprj[75] , \la_data_in_mprj[74] , \la_data_in_mprj[73] , \la_data_in_mprj[72] , \la_data_in_mprj[71] , \la_data_in_mprj[70] , \la_data_in_mprj[69] , \la_data_in_mprj[68] , \la_data_in_mprj[67] , \la_data_in_mprj[66] , \la_data_in_mprj[65] , \la_data_in_mprj[64] , \la_data_in_mprj[63] , \la_data_in_mprj[62] , \la_data_in_mprj[61] , \la_data_in_mprj[60] , \la_data_in_mprj[59] , \la_data_in_mprj[58] , \la_data_in_mprj[57] , \la_data_in_mprj[56] , \la_data_in_mprj[55] , \la_data_in_mprj[54] , \la_data_in_mprj[53] , \la_data_in_mprj[52] , \la_data_in_mprj[51] , \la_data_in_mprj[50] , \la_data_in_mprj[49] , \la_data_in_mprj[48] , \la_data_in_mprj[47] , \la_data_in_mprj[46] , \la_data_in_mprj[45] , \la_data_in_mprj[44] , \la_data_in_mprj[43] , \la_data_in_mprj[42] , \la_data_in_mprj[41] , \la_data_in_mprj[40] , \la_data_in_mprj[39] , \la_data_in_mprj[38] , \la_data_in_mprj[37] , \la_data_in_mprj[36] , \la_data_in_mprj[35] , \la_data_in_mprj[34] , \la_data_in_mprj[33] , \la_data_in_mprj[32] , \la_data_in_mprj[31] , \la_data_in_mprj[30] , \la_data_in_mprj[29] , \la_data_in_mprj[28] , \la_data_in_mprj[27] , \la_data_in_mprj[26] , \la_data_in_mprj[25] , \la_data_in_mprj[24] , \la_data_in_mprj[23] , \la_data_in_mprj[22] , \la_data_in_mprj[21] , \la_data_in_mprj[20] , \la_data_in_mprj[19] , \la_data_in_mprj[18] , \la_data_in_mprj[17] , \la_data_in_mprj[16] , \la_data_in_mprj[15] , \la_data_in_mprj[14] , \la_data_in_mprj[13] , \la_data_in_mprj[12] , \la_data_in_mprj[11] , \la_data_in_mprj[10] , \la_data_in_mprj[9] , \la_data_in_mprj[8] , \la_data_in_mprj[7] , \la_data_in_mprj[6] , \la_data_in_mprj[5] , \la_data_in_mprj[4] , \la_data_in_mprj[3] , \la_data_in_mprj[2] , \la_data_in_mprj[1] , \la_data_in_mprj[0]  }),
+    .la_data_out_core({ \la_data_out_user[127] , \la_data_out_user[126] , \la_data_out_user[125] , \la_data_out_user[124] , \la_data_out_user[123] , \la_data_out_user[122] , \la_data_out_user[121] , \la_data_out_user[120] , \la_data_out_user[119] , \la_data_out_user[118] , \la_data_out_user[117] , \la_data_out_user[116] , \la_data_out_user[115] , \la_data_out_user[114] , \la_data_out_user[113] , \la_data_out_user[112] , \la_data_out_user[111] , \la_data_out_user[110] , \la_data_out_user[109] , \la_data_out_user[108] , \la_data_out_user[107] , \la_data_out_user[106] , \la_data_out_user[105] , \la_data_out_user[104] , \la_data_out_user[103] , \la_data_out_user[102] , \la_data_out_user[101] , \la_data_out_user[100] , \la_data_out_user[99] , \la_data_out_user[98] , \la_data_out_user[97] , \la_data_out_user[96] , \la_data_out_user[95] , \la_data_out_user[94] , \la_data_out_user[93] , \la_data_out_user[92] , \la_data_out_user[91] , \la_data_out_user[90] , \la_data_out_user[89] , \la_data_out_user[88] , \la_data_out_user[87] , \la_data_out_user[86] , \la_data_out_user[85] , \la_data_out_user[84] , \la_data_out_user[83] , \la_data_out_user[82] , \la_data_out_user[81] , \la_data_out_user[80] , \la_data_out_user[79] , \la_data_out_user[78] , \la_data_out_user[77] , \la_data_out_user[76] , \la_data_out_user[75] , \la_data_out_user[74] , \la_data_out_user[73] , \la_data_out_user[72] , \la_data_out_user[71] , \la_data_out_user[70] , \la_data_out_user[69] , \la_data_out_user[68] , \la_data_out_user[67] , \la_data_out_user[66] , \la_data_out_user[65] , \la_data_out_user[64] , \la_data_out_user[63] , \la_data_out_user[62] , \la_data_out_user[61] , \la_data_out_user[60] , \la_data_out_user[59] , \la_data_out_user[58] , \la_data_out_user[57] , \la_data_out_user[56] , \la_data_out_user[55] , \la_data_out_user[54] , \la_data_out_user[53] , \la_data_out_user[52] , \la_data_out_user[51] , \la_data_out_user[50] , \la_data_out_user[49] , \la_data_out_user[48] , \la_data_out_user[47] , \la_data_out_user[46] , \la_data_out_user[45] , \la_data_out_user[44] , \la_data_out_user[43] , \la_data_out_user[42] , \la_data_out_user[41] , \la_data_out_user[40] , \la_data_out_user[39] , \la_data_out_user[38] , \la_data_out_user[37] , \la_data_out_user[36] , \la_data_out_user[35] , \la_data_out_user[34] , \la_data_out_user[33] , \la_data_out_user[32] , \la_data_out_user[31] , \la_data_out_user[30] , \la_data_out_user[29] , \la_data_out_user[28] , \la_data_out_user[27] , \la_data_out_user[26] , \la_data_out_user[25] , \la_data_out_user[24] , \la_data_out_user[23] , \la_data_out_user[22] , \la_data_out_user[21] , \la_data_out_user[20] , \la_data_out_user[19] , \la_data_out_user[18] , \la_data_out_user[17] , \la_data_out_user[16] , \la_data_out_user[15] , \la_data_out_user[14] , \la_data_out_user[13] , \la_data_out_user[12] , \la_data_out_user[11] , \la_data_out_user[10] , \la_data_out_user[9] , \la_data_out_user[8] , \la_data_out_user[7] , \la_data_out_user[6] , \la_data_out_user[5] , \la_data_out_user[4] , \la_data_out_user[3] , \la_data_out_user[2] , \la_data_out_user[1] , \la_data_out_user[0]  }),
+    .la_data_out_mprj({ \la_data_out_mprj[127] , \la_data_out_mprj[126] , \la_data_out_mprj[125] , \la_data_out_mprj[124] , \la_data_out_mprj[123] , \la_data_out_mprj[122] , \la_data_out_mprj[121] , \la_data_out_mprj[120] , \la_data_out_mprj[119] , \la_data_out_mprj[118] , \la_data_out_mprj[117] , \la_data_out_mprj[116] , \la_data_out_mprj[115] , \la_data_out_mprj[114] , \la_data_out_mprj[113] , \la_data_out_mprj[112] , \la_data_out_mprj[111] , \la_data_out_mprj[110] , \la_data_out_mprj[109] , \la_data_out_mprj[108] , \la_data_out_mprj[107] , \la_data_out_mprj[106] , \la_data_out_mprj[105] , \la_data_out_mprj[104] , \la_data_out_mprj[103] , \la_data_out_mprj[102] , \la_data_out_mprj[101] , \la_data_out_mprj[100] , \la_data_out_mprj[99] , \la_data_out_mprj[98] , \la_data_out_mprj[97] , \la_data_out_mprj[96] , \la_data_out_mprj[95] , \la_data_out_mprj[94] , \la_data_out_mprj[93] , \la_data_out_mprj[92] , \la_data_out_mprj[91] , \la_data_out_mprj[90] , \la_data_out_mprj[89] , \la_data_out_mprj[88] , \la_data_out_mprj[87] , \la_data_out_mprj[86] , \la_data_out_mprj[85] , \la_data_out_mprj[84] , \la_data_out_mprj[83] , \la_data_out_mprj[82] , \la_data_out_mprj[81] , \la_data_out_mprj[80] , \la_data_out_mprj[79] , \la_data_out_mprj[78] , \la_data_out_mprj[77] , \la_data_out_mprj[76] , \la_data_out_mprj[75] , \la_data_out_mprj[74] , \la_data_out_mprj[73] , \la_data_out_mprj[72] , \la_data_out_mprj[71] , \la_data_out_mprj[70] , \la_data_out_mprj[69] , \la_data_out_mprj[68] , \la_data_out_mprj[67] , \la_data_out_mprj[66] , \la_data_out_mprj[65] , \la_data_out_mprj[64] , \la_data_out_mprj[63] , \la_data_out_mprj[62] , \la_data_out_mprj[61] , \la_data_out_mprj[60] , \la_data_out_mprj[59] , \la_data_out_mprj[58] , \la_data_out_mprj[57] , \la_data_out_mprj[56] , \la_data_out_mprj[55] , \la_data_out_mprj[54] , \la_data_out_mprj[53] , \la_data_out_mprj[52] , \la_data_out_mprj[51] , \la_data_out_mprj[50] , \la_data_out_mprj[49] , \la_data_out_mprj[48] , \la_data_out_mprj[47] , \la_data_out_mprj[46] , \la_data_out_mprj[45] , \la_data_out_mprj[44] , \la_data_out_mprj[43] , \la_data_out_mprj[42] , \la_data_out_mprj[41] , \la_data_out_mprj[40] , \la_data_out_mprj[39] , \la_data_out_mprj[38] , \la_data_out_mprj[37] , \la_data_out_mprj[36] , \la_data_out_mprj[35] , \la_data_out_mprj[34] , \la_data_out_mprj[33] , \la_data_out_mprj[32] , \la_data_out_mprj[31] , \la_data_out_mprj[30] , \la_data_out_mprj[29] , \la_data_out_mprj[28] , \la_data_out_mprj[27] , \la_data_out_mprj[26] , \la_data_out_mprj[25] , \la_data_out_mprj[24] , \la_data_out_mprj[23] , \la_data_out_mprj[22] , \la_data_out_mprj[21] , \la_data_out_mprj[20] , \la_data_out_mprj[19] , \la_data_out_mprj[18] , \la_data_out_mprj[17] , \la_data_out_mprj[16] , \la_data_out_mprj[15] , \la_data_out_mprj[14] , \la_data_out_mprj[13] , \la_data_out_mprj[12] , \la_data_out_mprj[11] , \la_data_out_mprj[10] , \la_data_out_mprj[9] , \la_data_out_mprj[8] , \la_data_out_mprj[7] , \la_data_out_mprj[6] , \la_data_out_mprj[5] , \la_data_out_mprj[4] , \la_data_out_mprj[3] , \la_data_out_mprj[2] , \la_data_out_mprj[1] , \la_data_out_mprj[0]  }),
+    .la_iena_mprj({ \la_iena_mprj[127] , \la_iena_mprj[126] , \la_iena_mprj[125] , \la_iena_mprj[124] , \la_iena_mprj[123] , \la_iena_mprj[122] , \la_iena_mprj[121] , \la_iena_mprj[120] , \la_iena_mprj[119] , \la_iena_mprj[118] , \la_iena_mprj[117] , \la_iena_mprj[116] , \la_iena_mprj[115] , \la_iena_mprj[114] , \la_iena_mprj[113] , \la_iena_mprj[112] , \la_iena_mprj[111] , \la_iena_mprj[110] , \la_iena_mprj[109] , \la_iena_mprj[108] , \la_iena_mprj[107] , \la_iena_mprj[106] , \la_iena_mprj[105] , \la_iena_mprj[104] , \la_iena_mprj[103] , \la_iena_mprj[102] , \la_iena_mprj[101] , \la_iena_mprj[100] , \la_iena_mprj[99] , \la_iena_mprj[98] , \la_iena_mprj[97] , \la_iena_mprj[96] , \la_iena_mprj[95] , \la_iena_mprj[94] , \la_iena_mprj[93] , \la_iena_mprj[92] , \la_iena_mprj[91] , \la_iena_mprj[90] , \la_iena_mprj[89] , \la_iena_mprj[88] , \la_iena_mprj[87] , \la_iena_mprj[86] , \la_iena_mprj[85] , \la_iena_mprj[84] , \la_iena_mprj[83] , \la_iena_mprj[82] , \la_iena_mprj[81] , \la_iena_mprj[80] , \la_iena_mprj[79] , \la_iena_mprj[78] , \la_iena_mprj[77] , \la_iena_mprj[76] , \la_iena_mprj[75] , \la_iena_mprj[74] , \la_iena_mprj[73] , \la_iena_mprj[72] , \la_iena_mprj[71] , \la_iena_mprj[70] , \la_iena_mprj[69] , \la_iena_mprj[68] , \la_iena_mprj[67] , \la_iena_mprj[66] , \la_iena_mprj[65] , \la_iena_mprj[64] , \la_iena_mprj[63] , \la_iena_mprj[62] , \la_iena_mprj[61] , \la_iena_mprj[60] , \la_iena_mprj[59] , \la_iena_mprj[58] , \la_iena_mprj[57] , \la_iena_mprj[56] , \la_iena_mprj[55] , \la_iena_mprj[54] , \la_iena_mprj[53] , \la_iena_mprj[52] , \la_iena_mprj[51] , \la_iena_mprj[50] , \la_iena_mprj[49] , \la_iena_mprj[48] , \la_iena_mprj[47] , \la_iena_mprj[46] , \la_iena_mprj[45] , \la_iena_mprj[44] , \la_iena_mprj[43] , \la_iena_mprj[42] , \la_iena_mprj[41] , \la_iena_mprj[40] , \la_iena_mprj[39] , \la_iena_mprj[38] , \la_iena_mprj[37] , \la_iena_mprj[36] , \la_iena_mprj[35] , \la_iena_mprj[34] , \la_iena_mprj[33] , \la_iena_mprj[32] , \la_iena_mprj[31] , \la_iena_mprj[30] , \la_iena_mprj[29] , \la_iena_mprj[28] , \la_iena_mprj[27] , \la_iena_mprj[26] , \la_iena_mprj[25] , \la_iena_mprj[24] , \la_iena_mprj[23] , \la_iena_mprj[22] , \la_iena_mprj[21] , \la_iena_mprj[20] , \la_iena_mprj[19] , \la_iena_mprj[18] , \la_iena_mprj[17] , \la_iena_mprj[16] , \la_iena_mprj[15] , \la_iena_mprj[14] , \la_iena_mprj[13] , \la_iena_mprj[12] , \la_iena_mprj[11] , \la_iena_mprj[10] , \la_iena_mprj[9] , \la_iena_mprj[8] , \la_iena_mprj[7] , \la_iena_mprj[6] , \la_iena_mprj[5] , \la_iena_mprj[4] , \la_iena_mprj[3] , \la_iena_mprj[2] , \la_iena_mprj[1] , \la_iena_mprj[0]  }),
+    .la_oenb_core({ \la_oenb_user[127] , \la_oenb_user[126] , \la_oenb_user[125] , \la_oenb_user[124] , \la_oenb_user[123] , \la_oenb_user[122] , \la_oenb_user[121] , \la_oenb_user[120] , \la_oenb_user[119] , \la_oenb_user[118] , \la_oenb_user[117] , \la_oenb_user[116] , \la_oenb_user[115] , \la_oenb_user[114] , \la_oenb_user[113] , \la_oenb_user[112] , \la_oenb_user[111] , \la_oenb_user[110] , \la_oenb_user[109] , \la_oenb_user[108] , \la_oenb_user[107] , \la_oenb_user[106] , \la_oenb_user[105] , \la_oenb_user[104] , \la_oenb_user[103] , \la_oenb_user[102] , \la_oenb_user[101] , \la_oenb_user[100] , \la_oenb_user[99] , \la_oenb_user[98] , \la_oenb_user[97] , \la_oenb_user[96] , \la_oenb_user[95] , \la_oenb_user[94] , \la_oenb_user[93] , \la_oenb_user[92] , \la_oenb_user[91] , \la_oenb_user[90] , \la_oenb_user[89] , \la_oenb_user[88] , \la_oenb_user[87] , \la_oenb_user[86] , \la_oenb_user[85] , \la_oenb_user[84] , \la_oenb_user[83] , \la_oenb_user[82] , \la_oenb_user[81] , \la_oenb_user[80] , \la_oenb_user[79] , \la_oenb_user[78] , \la_oenb_user[77] , \la_oenb_user[76] , \la_oenb_user[75] , \la_oenb_user[74] , \la_oenb_user[73] , \la_oenb_user[72] , \la_oenb_user[71] , \la_oenb_user[70] , \la_oenb_user[69] , \la_oenb_user[68] , \la_oenb_user[67] , \la_oenb_user[66] , \la_oenb_user[65] , \la_oenb_user[64] , \la_oenb_user[63] , \la_oenb_user[62] , \la_oenb_user[61] , \la_oenb_user[60] , \la_oenb_user[59] , \la_oenb_user[58] , \la_oenb_user[57] , \la_oenb_user[56] , \la_oenb_user[55] , \la_oenb_user[54] , \la_oenb_user[53] , \la_oenb_user[52] , \la_oenb_user[51] , \la_oenb_user[50] , \la_oenb_user[49] , \la_oenb_user[48] , \la_oenb_user[47] , \la_oenb_user[46] , \la_oenb_user[45] , \la_oenb_user[44] , \la_oenb_user[43] , \la_oenb_user[42] , \la_oenb_user[41] , \la_oenb_user[40] , \la_oenb_user[39] , \la_oenb_user[38] , \la_oenb_user[37] , \la_oenb_user[36] , \la_oenb_user[35] , \la_oenb_user[34] , \la_oenb_user[33] , \la_oenb_user[32] , \la_oenb_user[31] , \la_oenb_user[30] , \la_oenb_user[29] , \la_oenb_user[28] , \la_oenb_user[27] , \la_oenb_user[26] , \la_oenb_user[25] , \la_oenb_user[24] , \la_oenb_user[23] , \la_oenb_user[22] , \la_oenb_user[21] , \la_oenb_user[20] , \la_oenb_user[19] , \la_oenb_user[18] , \la_oenb_user[17] , \la_oenb_user[16] , \la_oenb_user[15] , \la_oenb_user[14] , \la_oenb_user[13] , \la_oenb_user[12] , \la_oenb_user[11] , \la_oenb_user[10] , \la_oenb_user[9] , \la_oenb_user[8] , \la_oenb_user[7] , \la_oenb_user[6] , \la_oenb_user[5] , \la_oenb_user[4] , \la_oenb_user[3] , \la_oenb_user[2] , \la_oenb_user[1] , \la_oenb_user[0]  }),
+    .la_oenb_mprj({ \la_oenb_mprj[127] , \la_oenb_mprj[126] , \la_oenb_mprj[125] , \la_oenb_mprj[124] , \la_oenb_mprj[123] , \la_oenb_mprj[122] , \la_oenb_mprj[121] , \la_oenb_mprj[120] , \la_oenb_mprj[119] , \la_oenb_mprj[118] , \la_oenb_mprj[117] , \la_oenb_mprj[116] , \la_oenb_mprj[115] , \la_oenb_mprj[114] , \la_oenb_mprj[113] , \la_oenb_mprj[112] , \la_oenb_mprj[111] , \la_oenb_mprj[110] , \la_oenb_mprj[109] , \la_oenb_mprj[108] , \la_oenb_mprj[107] , \la_oenb_mprj[106] , \la_oenb_mprj[105] , \la_oenb_mprj[104] , \la_oenb_mprj[103] , \la_oenb_mprj[102] , \la_oenb_mprj[101] , \la_oenb_mprj[100] , \la_oenb_mprj[99] , \la_oenb_mprj[98] , \la_oenb_mprj[97] , \la_oenb_mprj[96] , \la_oenb_mprj[95] , \la_oenb_mprj[94] , \la_oenb_mprj[93] , \la_oenb_mprj[92] , \la_oenb_mprj[91] , \la_oenb_mprj[90] , \la_oenb_mprj[89] , \la_oenb_mprj[88] , \la_oenb_mprj[87] , \la_oenb_mprj[86] , \la_oenb_mprj[85] , \la_oenb_mprj[84] , \la_oenb_mprj[83] , \la_oenb_mprj[82] , \la_oenb_mprj[81] , \la_oenb_mprj[80] , \la_oenb_mprj[79] , \la_oenb_mprj[78] , \la_oenb_mprj[77] , \la_oenb_mprj[76] , \la_oenb_mprj[75] , \la_oenb_mprj[74] , \la_oenb_mprj[73] , \la_oenb_mprj[72] , \la_oenb_mprj[71] , \la_oenb_mprj[70] , \la_oenb_mprj[69] , \la_oenb_mprj[68] , \la_oenb_mprj[67] , \la_oenb_mprj[66] , \la_oenb_mprj[65] , \la_oenb_mprj[64] , \la_oenb_mprj[63] , \la_oenb_mprj[62] , \la_oenb_mprj[61] , \la_oenb_mprj[60] , \la_oenb_mprj[59] , \la_oenb_mprj[58] , \la_oenb_mprj[57] , \la_oenb_mprj[56] , \la_oenb_mprj[55] , \la_oenb_mprj[54] , \la_oenb_mprj[53] , \la_oenb_mprj[52] , \la_oenb_mprj[51] , \la_oenb_mprj[50] , \la_oenb_mprj[49] , \la_oenb_mprj[48] , \la_oenb_mprj[47] , \la_oenb_mprj[46] , \la_oenb_mprj[45] , \la_oenb_mprj[44] , \la_oenb_mprj[43] , \la_oenb_mprj[42] , \la_oenb_mprj[41] , \la_oenb_mprj[40] , \la_oenb_mprj[39] , \la_oenb_mprj[38] , \la_oenb_mprj[37] , \la_oenb_mprj[36] , \la_oenb_mprj[35] , \la_oenb_mprj[34] , \la_oenb_mprj[33] , \la_oenb_mprj[32] , \la_oenb_mprj[31] , \la_oenb_mprj[30] , \la_oenb_mprj[29] , \la_oenb_mprj[28] , \la_oenb_mprj[27] , \la_oenb_mprj[26] , \la_oenb_mprj[25] , \la_oenb_mprj[24] , \la_oenb_mprj[23] , \la_oenb_mprj[22] , \la_oenb_mprj[21] , \la_oenb_mprj[20] , \la_oenb_mprj[19] , \la_oenb_mprj[18] , \la_oenb_mprj[17] , \la_oenb_mprj[16] , \la_oenb_mprj[15] , \la_oenb_mprj[14] , \la_oenb_mprj[13] , \la_oenb_mprj[12] , \la_oenb_mprj[11] , \la_oenb_mprj[10] , \la_oenb_mprj[9] , \la_oenb_mprj[8] , \la_oenb_mprj[7] , \la_oenb_mprj[6] , \la_oenb_mprj[5] , \la_oenb_mprj[4] , \la_oenb_mprj[3] , \la_oenb_mprj[2] , \la_oenb_mprj[1] , \la_oenb_mprj[0]  }),
+    .mprj_ack_i_core(mprj_ack_i_core),
+    .mprj_ack_i_user(mprj_ack_i_user),
+    .mprj_adr_o_core({ \mprj_adr_o_core[31] , \mprj_adr_o_core[30] , \mprj_adr_o_core[29] , \mprj_adr_o_core[28] , \mprj_adr_o_core[27] , \mprj_adr_o_core[26] , \mprj_adr_o_core[25] , \mprj_adr_o_core[24] , \mprj_adr_o_core[23] , \mprj_adr_o_core[22] , \mprj_adr_o_core[21] , \mprj_adr_o_core[20] , \mprj_adr_o_core[19] , \mprj_adr_o_core[18] , \mprj_adr_o_core[17] , \mprj_adr_o_core[16] , \mprj_adr_o_core[15] , \mprj_adr_o_core[14] , \mprj_adr_o_core[13] , \mprj_adr_o_core[12] , \mprj_adr_o_core[11] , \mprj_adr_o_core[10] , \mprj_adr_o_core[9] , \mprj_adr_o_core[8] , \mprj_adr_o_core[7] , \mprj_adr_o_core[6] , \mprj_adr_o_core[5] , \mprj_adr_o_core[4] , \mprj_adr_o_core[3] , \mprj_adr_o_core[2] , \mprj_adr_o_core[1] , \mprj_adr_o_core[0]  }),
+    .mprj_adr_o_user({ \mprj_adr_o_user[31] , \mprj_adr_o_user[30] , \mprj_adr_o_user[29] , \mprj_adr_o_user[28] , \mprj_adr_o_user[27] , \mprj_adr_o_user[26] , \mprj_adr_o_user[25] , \mprj_adr_o_user[24] , \mprj_adr_o_user[23] , \mprj_adr_o_user[22] , \mprj_adr_o_user[21] , \mprj_adr_o_user[20] , \mprj_adr_o_user[19] , \mprj_adr_o_user[18] , \mprj_adr_o_user[17] , \mprj_adr_o_user[16] , \mprj_adr_o_user[15] , \mprj_adr_o_user[14] , \mprj_adr_o_user[13] , \mprj_adr_o_user[12] , \mprj_adr_o_user[11] , \mprj_adr_o_user[10] , \mprj_adr_o_user[9] , \mprj_adr_o_user[8] , \mprj_adr_o_user[7] , \mprj_adr_o_user[6] , \mprj_adr_o_user[5] , \mprj_adr_o_user[4] , \mprj_adr_o_user[3] , \mprj_adr_o_user[2] , \mprj_adr_o_user[1] , \mprj_adr_o_user[0]  }),
+    .mprj_cyc_o_core(mprj_cyc_o_core),
+    .mprj_cyc_o_user(mprj_cyc_o_user),
+    .mprj_dat_i_core({ \mprj_dat_i_core[31] , \mprj_dat_i_core[30] , \mprj_dat_i_core[29] , \mprj_dat_i_core[28] , \mprj_dat_i_core[27] , \mprj_dat_i_core[26] , \mprj_dat_i_core[25] , \mprj_dat_i_core[24] , \mprj_dat_i_core[23] , \mprj_dat_i_core[22] , \mprj_dat_i_core[21] , \mprj_dat_i_core[20] , \mprj_dat_i_core[19] , \mprj_dat_i_core[18] , \mprj_dat_i_core[17] , \mprj_dat_i_core[16] , \mprj_dat_i_core[15] , \mprj_dat_i_core[14] , \mprj_dat_i_core[13] , \mprj_dat_i_core[12] , \mprj_dat_i_core[11] , \mprj_dat_i_core[10] , \mprj_dat_i_core[9] , \mprj_dat_i_core[8] , \mprj_dat_i_core[7] , \mprj_dat_i_core[6] , \mprj_dat_i_core[5] , \mprj_dat_i_core[4] , \mprj_dat_i_core[3] , \mprj_dat_i_core[2] , \mprj_dat_i_core[1] , \mprj_dat_i_core[0]  }),
+    .mprj_dat_i_user({ \mprj_dat_i_user[31] , \mprj_dat_i_user[30] , \mprj_dat_i_user[29] , \mprj_dat_i_user[28] , \mprj_dat_i_user[27] , \mprj_dat_i_user[26] , \mprj_dat_i_user[25] , \mprj_dat_i_user[24] , \mprj_dat_i_user[23] , \mprj_dat_i_user[22] , \mprj_dat_i_user[21] , \mprj_dat_i_user[20] , \mprj_dat_i_user[19] , \mprj_dat_i_user[18] , \mprj_dat_i_user[17] , \mprj_dat_i_user[16] , \mprj_dat_i_user[15] , \mprj_dat_i_user[14] , \mprj_dat_i_user[13] , \mprj_dat_i_user[12] , \mprj_dat_i_user[11] , \mprj_dat_i_user[10] , \mprj_dat_i_user[9] , \mprj_dat_i_user[8] , \mprj_dat_i_user[7] , \mprj_dat_i_user[6] , \mprj_dat_i_user[5] , \mprj_dat_i_user[4] , \mprj_dat_i_user[3] , \mprj_dat_i_user[2] , \mprj_dat_i_user[1] , \mprj_dat_i_user[0]  }),
+    .mprj_dat_o_core({ \mprj_dat_o_core[31] , \mprj_dat_o_core[30] , \mprj_dat_o_core[29] , \mprj_dat_o_core[28] , \mprj_dat_o_core[27] , \mprj_dat_o_core[26] , \mprj_dat_o_core[25] , \mprj_dat_o_core[24] , \mprj_dat_o_core[23] , \mprj_dat_o_core[22] , \mprj_dat_o_core[21] , \mprj_dat_o_core[20] , \mprj_dat_o_core[19] , \mprj_dat_o_core[18] , \mprj_dat_o_core[17] , \mprj_dat_o_core[16] , \mprj_dat_o_core[15] , \mprj_dat_o_core[14] , \mprj_dat_o_core[13] , \mprj_dat_o_core[12] , \mprj_dat_o_core[11] , \mprj_dat_o_core[10] , \mprj_dat_o_core[9] , \mprj_dat_o_core[8] , \mprj_dat_o_core[7] , \mprj_dat_o_core[6] , \mprj_dat_o_core[5] , \mprj_dat_o_core[4] , \mprj_dat_o_core[3] , \mprj_dat_o_core[2] , \mprj_dat_o_core[1] , \mprj_dat_o_core[0]  }),
+    .mprj_dat_o_user({ \mprj_dat_o_user[31] , \mprj_dat_o_user[30] , \mprj_dat_o_user[29] , \mprj_dat_o_user[28] , \mprj_dat_o_user[27] , \mprj_dat_o_user[26] , \mprj_dat_o_user[25] , \mprj_dat_o_user[24] , \mprj_dat_o_user[23] , \mprj_dat_o_user[22] , \mprj_dat_o_user[21] , \mprj_dat_o_user[20] , \mprj_dat_o_user[19] , \mprj_dat_o_user[18] , \mprj_dat_o_user[17] , \mprj_dat_o_user[16] , \mprj_dat_o_user[15] , \mprj_dat_o_user[14] , \mprj_dat_o_user[13] , \mprj_dat_o_user[12] , \mprj_dat_o_user[11] , \mprj_dat_o_user[10] , \mprj_dat_o_user[9] , \mprj_dat_o_user[8] , \mprj_dat_o_user[7] , \mprj_dat_o_user[6] , \mprj_dat_o_user[5] , \mprj_dat_o_user[4] , \mprj_dat_o_user[3] , \mprj_dat_o_user[2] , \mprj_dat_o_user[1] , \mprj_dat_o_user[0]  }),
+    .mprj_iena_wb(mprj_iena_wb),
+    .mprj_sel_o_core({ \mprj_sel_o_core[3] , \mprj_sel_o_core[2] , \mprj_sel_o_core[1] , \mprj_sel_o_core[0]  }),
+    .mprj_sel_o_user({ \mprj_sel_o_user[3] , \mprj_sel_o_user[2] , \mprj_sel_o_user[1] , \mprj_sel_o_user[0]  }),
+    .mprj_stb_o_core(mprj_stb_o_core),
+    .mprj_stb_o_user(mprj_stb_o_user),
+    .mprj_we_o_core(mprj_we_o_core),
+    .mprj_we_o_user(mprj_we_o_user),
+    .user1_vcc_powergood(mprj_vcc_pwrgood),
+    .user1_vdd_powergood(mprj_vdd_pwrgood),
+    .user2_vcc_powergood(mprj2_vcc_pwrgood),
+    .user2_vdd_powergood(mprj2_vdd_pwrgood),
+    .user_clock(mprj_clock),
+    .user_clock2(mprj_clock2),
+    .user_irq({ \user_irq[2] , \user_irq[1] , \user_irq[0]  }),
+    .user_irq_core({ \user_irq_core[2] , \user_irq_core[1] , \user_irq_core[0]  }),
+    .user_irq_ena({ \user_irq_ena[2] , \user_irq_ena[1] , \user_irq_ena[0]  }),
+    .user_reset(mprj_reset),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vccd2(vccd2_core),
+    .vdda1(vdda1_core),
+    .vdda2(vdda2_core),
+    .vssa1(vssa1_core),
+    .vssa2(vssa2_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .vssd2(vssd2_core)
+  );
+  user_project_wrapper mprj (
+    .analog_io({ \user_analog_io[28] , \user_analog_io[27] , \user_analog_io[26] , \user_analog_io[25] , \user_analog_io[24] , \user_analog_io[23] , \user_analog_io[22] , \user_analog_io[21] , \user_analog_io[20] , \user_analog_io[19] , \user_analog_io[18] , \user_analog_io[17] , \user_analog_io[16] , \user_analog_io[15] , \user_analog_io[14] , \user_analog_io[13] , \user_analog_io[12] , \user_analog_io[11] , \user_analog_io[10] , \user_analog_io[9] , \user_analog_io[8] , \user_analog_io[7] , \user_analog_io[6] , \user_analog_io[5] , \user_analog_io[4] , \user_analog_io[3] , \user_analog_io[2] , \user_analog_io[1] , \user_analog_io[0]  }),
+    .io_in({ \user_io_in[37] , \user_io_in[36] , \user_io_in[35] , \user_io_in[34] , \user_io_in[33] , \user_io_in[32] , \user_io_in[31] , \user_io_in[30] , \user_io_in[29] , \user_io_in[28] , \user_io_in[27] , \user_io_in[26] , \user_io_in[25] , \user_io_in[24] , \user_io_in[23] , \user_io_in[22] , \user_io_in[21] , \user_io_in[20] , \user_io_in[19] , \user_io_in[18] , \user_io_in[17] , \user_io_in[16] , \user_io_in[15] , \user_io_in[14] , \user_io_in[13] , \user_io_in[12] , \user_io_in[11] , \user_io_in[10] , \user_io_in[9] , \user_io_in[8] , \user_io_in[7] , \user_io_in[6] , \user_io_in[5] , \user_io_in[4] , \user_io_in[3] , \user_io_in[2] , \user_io_in[1] , \user_io_in[0]  }),
+    .io_oeb({ \user_io_oeb[37] , \user_io_oeb[36] , \user_io_oeb[35] , \user_io_oeb[34] , \user_io_oeb[33] , \user_io_oeb[32] , \user_io_oeb[31] , \user_io_oeb[30] , \user_io_oeb[29] , \user_io_oeb[28] , \user_io_oeb[27] , \user_io_oeb[26] , \user_io_oeb[25] , \user_io_oeb[24] , \user_io_oeb[23] , \user_io_oeb[22] , \user_io_oeb[21] , \user_io_oeb[20] , \user_io_oeb[19] , \user_io_oeb[18] , \user_io_oeb[17] , \user_io_oeb[16] , \user_io_oeb[15] , \user_io_oeb[14] , \user_io_oeb[13] , \user_io_oeb[12] , \user_io_oeb[11] , \user_io_oeb[10] , \user_io_oeb[9] , \user_io_oeb[8] , \user_io_oeb[7] , \user_io_oeb[6] , \user_io_oeb[5] , \user_io_oeb[4] , \user_io_oeb[3] , \user_io_oeb[2] , \user_io_oeb[1] , \user_io_oeb[0]  }),
+    .io_out({ \user_io_out[37] , \user_io_out[36] , \user_io_out[35] , \user_io_out[34] , \user_io_out[33] , \user_io_out[32] , \user_io_out[31] , \user_io_out[30] , \user_io_out[29] , \user_io_out[28] , \user_io_out[27] , \user_io_out[26] , \user_io_out[25] , \user_io_out[24] , \user_io_out[23] , \user_io_out[22] , \user_io_out[21] , \user_io_out[20] , \user_io_out[19] , \user_io_out[18] , \user_io_out[17] , \user_io_out[16] , \user_io_out[15] , \user_io_out[14] , \user_io_out[13] , \user_io_out[12] , \user_io_out[11] , \user_io_out[10] , \user_io_out[9] , \user_io_out[8] , \user_io_out[7] , \user_io_out[6] , \user_io_out[5] , \user_io_out[4] , \user_io_out[3] , \user_io_out[2] , \user_io_out[1] , \user_io_out[0]  }),
+    .la_data_in({ \la_data_in_user[127] , \la_data_in_user[126] , \la_data_in_user[125] , \la_data_in_user[124] , \la_data_in_user[123] , \la_data_in_user[122] , \la_data_in_user[121] , \la_data_in_user[120] , \la_data_in_user[119] , \la_data_in_user[118] , \la_data_in_user[117] , \la_data_in_user[116] , \la_data_in_user[115] , \la_data_in_user[114] , \la_data_in_user[113] , \la_data_in_user[112] , \la_data_in_user[111] , \la_data_in_user[110] , \la_data_in_user[109] , \la_data_in_user[108] , \la_data_in_user[107] , \la_data_in_user[106] , \la_data_in_user[105] , \la_data_in_user[104] , \la_data_in_user[103] , \la_data_in_user[102] , \la_data_in_user[101] , \la_data_in_user[100] , \la_data_in_user[99] , \la_data_in_user[98] , \la_data_in_user[97] , \la_data_in_user[96] , \la_data_in_user[95] , \la_data_in_user[94] , \la_data_in_user[93] , \la_data_in_user[92] , \la_data_in_user[91] , \la_data_in_user[90] , \la_data_in_user[89] , \la_data_in_user[88] , \la_data_in_user[87] , \la_data_in_user[86] , \la_data_in_user[85] , \la_data_in_user[84] , \la_data_in_user[83] , \la_data_in_user[82] , \la_data_in_user[81] , \la_data_in_user[80] , \la_data_in_user[79] , \la_data_in_user[78] , \la_data_in_user[77] , \la_data_in_user[76] , \la_data_in_user[75] , \la_data_in_user[74] , \la_data_in_user[73] , \la_data_in_user[72] , \la_data_in_user[71] , \la_data_in_user[70] , \la_data_in_user[69] , \la_data_in_user[68] , \la_data_in_user[67] , \la_data_in_user[66] , \la_data_in_user[65] , \la_data_in_user[64] , \la_data_in_user[63] , \la_data_in_user[62] , \la_data_in_user[61] , \la_data_in_user[60] , \la_data_in_user[59] , \la_data_in_user[58] , \la_data_in_user[57] , \la_data_in_user[56] , \la_data_in_user[55] , \la_data_in_user[54] , \la_data_in_user[53] , \la_data_in_user[52] , \la_data_in_user[51] , \la_data_in_user[50] , \la_data_in_user[49] , \la_data_in_user[48] , \la_data_in_user[47] , \la_data_in_user[46] , \la_data_in_user[45] , \la_data_in_user[44] , \la_data_in_user[43] , \la_data_in_user[42] , \la_data_in_user[41] , \la_data_in_user[40] , \la_data_in_user[39] , \la_data_in_user[38] , \la_data_in_user[37] , \la_data_in_user[36] , \la_data_in_user[35] , \la_data_in_user[34] , \la_data_in_user[33] , \la_data_in_user[32] , \la_data_in_user[31] , \la_data_in_user[30] , \la_data_in_user[29] , \la_data_in_user[28] , \la_data_in_user[27] , \la_data_in_user[26] , \la_data_in_user[25] , \la_data_in_user[24] , \la_data_in_user[23] , \la_data_in_user[22] , \la_data_in_user[21] , \la_data_in_user[20] , \la_data_in_user[19] , \la_data_in_user[18] , \la_data_in_user[17] , \la_data_in_user[16] , \la_data_in_user[15] , \la_data_in_user[14] , \la_data_in_user[13] , \la_data_in_user[12] , \la_data_in_user[11] , \la_data_in_user[10] , \la_data_in_user[9] , \la_data_in_user[8] , \la_data_in_user[7] , \la_data_in_user[6] , \la_data_in_user[5] , \la_data_in_user[4] , \la_data_in_user[3] , \la_data_in_user[2] , \la_data_in_user[1] , \la_data_in_user[0]  }),
+    .la_data_out({ \la_data_out_user[127] , \la_data_out_user[126] , \la_data_out_user[125] , \la_data_out_user[124] , \la_data_out_user[123] , \la_data_out_user[122] , \la_data_out_user[121] , \la_data_out_user[120] , \la_data_out_user[119] , \la_data_out_user[118] , \la_data_out_user[117] , \la_data_out_user[116] , \la_data_out_user[115] , \la_data_out_user[114] , \la_data_out_user[113] , \la_data_out_user[112] , \la_data_out_user[111] , \la_data_out_user[110] , \la_data_out_user[109] , \la_data_out_user[108] , \la_data_out_user[107] , \la_data_out_user[106] , \la_data_out_user[105] , \la_data_out_user[104] , \la_data_out_user[103] , \la_data_out_user[102] , \la_data_out_user[101] , \la_data_out_user[100] , \la_data_out_user[99] , \la_data_out_user[98] , \la_data_out_user[97] , \la_data_out_user[96] , \la_data_out_user[95] , \la_data_out_user[94] , \la_data_out_user[93] , \la_data_out_user[92] , \la_data_out_user[91] , \la_data_out_user[90] , \la_data_out_user[89] , \la_data_out_user[88] , \la_data_out_user[87] , \la_data_out_user[86] , \la_data_out_user[85] , \la_data_out_user[84] , \la_data_out_user[83] , \la_data_out_user[82] , \la_data_out_user[81] , \la_data_out_user[80] , \la_data_out_user[79] , \la_data_out_user[78] , \la_data_out_user[77] , \la_data_out_user[76] , \la_data_out_user[75] , \la_data_out_user[74] , \la_data_out_user[73] , \la_data_out_user[72] , \la_data_out_user[71] , \la_data_out_user[70] , \la_data_out_user[69] , \la_data_out_user[68] , \la_data_out_user[67] , \la_data_out_user[66] , \la_data_out_user[65] , \la_data_out_user[64] , \la_data_out_user[63] , \la_data_out_user[62] , \la_data_out_user[61] , \la_data_out_user[60] , \la_data_out_user[59] , \la_data_out_user[58] , \la_data_out_user[57] , \la_data_out_user[56] , \la_data_out_user[55] , \la_data_out_user[54] , \la_data_out_user[53] , \la_data_out_user[52] , \la_data_out_user[51] , \la_data_out_user[50] , \la_data_out_user[49] , \la_data_out_user[48] , \la_data_out_user[47] , \la_data_out_user[46] , \la_data_out_user[45] , \la_data_out_user[44] , \la_data_out_user[43] , \la_data_out_user[42] , \la_data_out_user[41] , \la_data_out_user[40] , \la_data_out_user[39] , \la_data_out_user[38] , \la_data_out_user[37] , \la_data_out_user[36] , \la_data_out_user[35] , \la_data_out_user[34] , \la_data_out_user[33] , \la_data_out_user[32] , \la_data_out_user[31] , \la_data_out_user[30] , \la_data_out_user[29] , \la_data_out_user[28] , \la_data_out_user[27] , \la_data_out_user[26] , \la_data_out_user[25] , \la_data_out_user[24] , \la_data_out_user[23] , \la_data_out_user[22] , \la_data_out_user[21] , \la_data_out_user[20] , \la_data_out_user[19] , \la_data_out_user[18] , \la_data_out_user[17] , \la_data_out_user[16] , \la_data_out_user[15] , \la_data_out_user[14] , \la_data_out_user[13] , \la_data_out_user[12] , \la_data_out_user[11] , \la_data_out_user[10] , \la_data_out_user[9] , \la_data_out_user[8] , \la_data_out_user[7] , \la_data_out_user[6] , \la_data_out_user[5] , \la_data_out_user[4] , \la_data_out_user[3] , \la_data_out_user[2] , \la_data_out_user[1] , \la_data_out_user[0]  }),
+    .la_oenb({ \la_oenb_user[127] , \la_oenb_user[126] , \la_oenb_user[125] , \la_oenb_user[124] , \la_oenb_user[123] , \la_oenb_user[122] , \la_oenb_user[121] , \la_oenb_user[120] , \la_oenb_user[119] , \la_oenb_user[118] , \la_oenb_user[117] , \la_oenb_user[116] , \la_oenb_user[115] , \la_oenb_user[114] , \la_oenb_user[113] , \la_oenb_user[112] , \la_oenb_user[111] , \la_oenb_user[110] , \la_oenb_user[109] , \la_oenb_user[108] , \la_oenb_user[107] , \la_oenb_user[106] , \la_oenb_user[105] , \la_oenb_user[104] , \la_oenb_user[103] , \la_oenb_user[102] , \la_oenb_user[101] , \la_oenb_user[100] , \la_oenb_user[99] , \la_oenb_user[98] , \la_oenb_user[97] , \la_oenb_user[96] , \la_oenb_user[95] , \la_oenb_user[94] , \la_oenb_user[93] , \la_oenb_user[92] , \la_oenb_user[91] , \la_oenb_user[90] , \la_oenb_user[89] , \la_oenb_user[88] , \la_oenb_user[87] , \la_oenb_user[86] , \la_oenb_user[85] , \la_oenb_user[84] , \la_oenb_user[83] , \la_oenb_user[82] , \la_oenb_user[81] , \la_oenb_user[80] , \la_oenb_user[79] , \la_oenb_user[78] , \la_oenb_user[77] , \la_oenb_user[76] , \la_oenb_user[75] , \la_oenb_user[74] , \la_oenb_user[73] , \la_oenb_user[72] , \la_oenb_user[71] , \la_oenb_user[70] , \la_oenb_user[69] , \la_oenb_user[68] , \la_oenb_user[67] , \la_oenb_user[66] , \la_oenb_user[65] , \la_oenb_user[64] , \la_oenb_user[63] , \la_oenb_user[62] , \la_oenb_user[61] , \la_oenb_user[60] , \la_oenb_user[59] , \la_oenb_user[58] , \la_oenb_user[57] , \la_oenb_user[56] , \la_oenb_user[55] , \la_oenb_user[54] , \la_oenb_user[53] , \la_oenb_user[52] , \la_oenb_user[51] , \la_oenb_user[50] , \la_oenb_user[49] , \la_oenb_user[48] , \la_oenb_user[47] , \la_oenb_user[46] , \la_oenb_user[45] , \la_oenb_user[44] , \la_oenb_user[43] , \la_oenb_user[42] , \la_oenb_user[41] , \la_oenb_user[40] , \la_oenb_user[39] , \la_oenb_user[38] , \la_oenb_user[37] , \la_oenb_user[36] , \la_oenb_user[35] , \la_oenb_user[34] , \la_oenb_user[33] , \la_oenb_user[32] , \la_oenb_user[31] , \la_oenb_user[30] , \la_oenb_user[29] , \la_oenb_user[28] , \la_oenb_user[27] , \la_oenb_user[26] , \la_oenb_user[25] , \la_oenb_user[24] , \la_oenb_user[23] , \la_oenb_user[22] , \la_oenb_user[21] , \la_oenb_user[20] , \la_oenb_user[19] , \la_oenb_user[18] , \la_oenb_user[17] , \la_oenb_user[16] , \la_oenb_user[15] , \la_oenb_user[14] , \la_oenb_user[13] , \la_oenb_user[12] , \la_oenb_user[11] , \la_oenb_user[10] , \la_oenb_user[9] , \la_oenb_user[8] , \la_oenb_user[7] , \la_oenb_user[6] , \la_oenb_user[5] , \la_oenb_user[4] , \la_oenb_user[3] , \la_oenb_user[2] , \la_oenb_user[1] , \la_oenb_user[0]  }),
+    .user_clock2(mprj_clock2),
+    .user_irq({ \user_irq_core[2] , \user_irq_core[1] , \user_irq_core[0]  }),
+    .vccd1(vccd1_core),
+    .vccd2(vccd2_core),
+    .vdda1(vdda1_core),
+    .vdda2(vdda2_core),
+    .vssa1(vssa1_core),
+    .vssa2(vssa2_core),
+    .vssd1(vssd1_core),
+    .vssd2(vssd2_core),
+    .wb_clk_i(mprj_clock),
+    .wb_rst_i(mprj_reset),
+    .wbs_ack_o(mprj_ack_i_user),
+    .wbs_adr_i({ \mprj_adr_o_user[31] , \mprj_adr_o_user[30] , \mprj_adr_o_user[29] , \mprj_adr_o_user[28] , \mprj_adr_o_user[27] , \mprj_adr_o_user[26] , \mprj_adr_o_user[25] , \mprj_adr_o_user[24] , \mprj_adr_o_user[23] , \mprj_adr_o_user[22] , \mprj_adr_o_user[21] , \mprj_adr_o_user[20] , \mprj_adr_o_user[19] , \mprj_adr_o_user[18] , \mprj_adr_o_user[17] , \mprj_adr_o_user[16] , \mprj_adr_o_user[15] , \mprj_adr_o_user[14] , \mprj_adr_o_user[13] , \mprj_adr_o_user[12] , \mprj_adr_o_user[11] , \mprj_adr_o_user[10] , \mprj_adr_o_user[9] , \mprj_adr_o_user[8] , \mprj_adr_o_user[7] , \mprj_adr_o_user[6] , \mprj_adr_o_user[5] , \mprj_adr_o_user[4] , \mprj_adr_o_user[3] , \mprj_adr_o_user[2] , \mprj_adr_o_user[1] , \mprj_adr_o_user[0]  }),
+    .wbs_cyc_i(mprj_cyc_o_user),
+    .wbs_dat_i({ \mprj_dat_o_user[31] , \mprj_dat_o_user[30] , \mprj_dat_o_user[29] , \mprj_dat_o_user[28] , \mprj_dat_o_user[27] , \mprj_dat_o_user[26] , \mprj_dat_o_user[25] , \mprj_dat_o_user[24] , \mprj_dat_o_user[23] , \mprj_dat_o_user[22] , \mprj_dat_o_user[21] , \mprj_dat_o_user[20] , \mprj_dat_o_user[19] , \mprj_dat_o_user[18] , \mprj_dat_o_user[17] , \mprj_dat_o_user[16] , \mprj_dat_o_user[15] , \mprj_dat_o_user[14] , \mprj_dat_o_user[13] , \mprj_dat_o_user[12] , \mprj_dat_o_user[11] , \mprj_dat_o_user[10] , \mprj_dat_o_user[9] , \mprj_dat_o_user[8] , \mprj_dat_o_user[7] , \mprj_dat_o_user[6] , \mprj_dat_o_user[5] , \mprj_dat_o_user[4] , \mprj_dat_o_user[3] , \mprj_dat_o_user[2] , \mprj_dat_o_user[1] , \mprj_dat_o_user[0]  }),
+    .wbs_dat_o({ \mprj_dat_i_user[31] , \mprj_dat_i_user[30] , \mprj_dat_i_user[29] , \mprj_dat_i_user[28] , \mprj_dat_i_user[27] , \mprj_dat_i_user[26] , \mprj_dat_i_user[25] , \mprj_dat_i_user[24] , \mprj_dat_i_user[23] , \mprj_dat_i_user[22] , \mprj_dat_i_user[21] , \mprj_dat_i_user[20] , \mprj_dat_i_user[19] , \mprj_dat_i_user[18] , \mprj_dat_i_user[17] , \mprj_dat_i_user[16] , \mprj_dat_i_user[15] , \mprj_dat_i_user[14] , \mprj_dat_i_user[13] , \mprj_dat_i_user[12] , \mprj_dat_i_user[11] , \mprj_dat_i_user[10] , \mprj_dat_i_user[9] , \mprj_dat_i_user[8] , \mprj_dat_i_user[7] , \mprj_dat_i_user[6] , \mprj_dat_i_user[5] , \mprj_dat_i_user[4] , \mprj_dat_i_user[3] , \mprj_dat_i_user[2] , \mprj_dat_i_user[1] , \mprj_dat_i_user[0]  }),
+    .wbs_sel_i({ \mprj_sel_o_user[3] , \mprj_sel_o_user[2] , \mprj_sel_o_user[1] , \mprj_sel_o_user[0]  }),
+    .wbs_stb_i(mprj_stb_o_user),
+    .wbs_we_i(mprj_we_o_user)
+  );
+  chip_io padframe (
+    .clock(clock),
+    .clock_core(clock_core),
+    .flash_clk(flash_clk),
+    .flash_clk_core(flash_clk_frame_buf),
+    .flash_clk_oeb_core(flash_clk_oeb_buf),
+    .flash_csb(flash_csb),
+    .flash_csb_core(flash_csb_frame_buf),
+    .flash_csb_oeb_core(flash_csb_oeb_buf),
+    .flash_io0(flash_io0),
+    .flash_io0_di_core(flash_io0_di),
+    .flash_io0_do_core(flash_io0_do_buf),
+    .flash_io0_ieb_core(flash_io0_ieb_buf),
+    .flash_io0_oeb_core(flash_io0_oeb_buf),
+    .flash_io1(flash_io1),
+    .flash_io1_di_core(flash_io1_di),
+    .flash_io1_do_core(flash_io1_do_buf),
+    .flash_io1_ieb_core(flash_io1_ieb_buf),
+    .flash_io1_oeb_core(flash_io1_oeb_buf),
+    .gpio(gpio),
+    .gpio_in_core(gpio_in_core),
+    .gpio_inenb_core(gpio_inenb_core),
+    .gpio_mode0_core(gpio_mode0_core),
+    .gpio_mode1_core(gpio_mode1_core),
+    .gpio_out_core(gpio_out_core),
+    .gpio_outenb_core(gpio_outenb_core),
+    .mprj_analog_io({ \user_analog_io[28] , \user_analog_io[27] , \user_analog_io[26] , \user_analog_io[25] , \user_analog_io[24] , \user_analog_io[23] , \user_analog_io[22] , \user_analog_io[21] , \user_analog_io[20] , \user_analog_io[19] , \user_analog_io[18] , \user_analog_io[17] , \user_analog_io[16] , \user_analog_io[15] , \user_analog_io[14] , \user_analog_io[13] , \user_analog_io[12] , \user_analog_io[11] , \user_analog_io[10] , \user_analog_io[9] , \user_analog_io[8] , \user_analog_io[7] , \user_analog_io[6] , \user_analog_io[5] , \user_analog_io[4] , \user_analog_io[3] , \user_analog_io[2] , \user_analog_io[1] , \user_analog_io[0]  }),
+    .mprj_io(mprj_io),
+    .mprj_io_analog_en({ \mprj_io_analog_en[37] , \mprj_io_analog_en[36] , \mprj_io_analog_en[35] , \mprj_io_analog_en[34] , \mprj_io_analog_en[33] , \mprj_io_analog_en[32] , \mprj_io_analog_en[31] , \mprj_io_analog_en[30] , \mprj_io_analog_en[29] , \mprj_io_analog_en[28] , \mprj_io_analog_en[27] , \mprj_io_analog_en[26] , \mprj_io_analog_en[25] , \mprj_io_analog_en[24] , \mprj_io_analog_en[23] , \mprj_io_analog_en[22] , \mprj_io_analog_en[21] , \mprj_io_analog_en[20] , \mprj_io_analog_en[19] , \mprj_io_analog_en[18] , \mprj_io_analog_en[17] , \mprj_io_analog_en[16] , \mprj_io_analog_en[15] , \mprj_io_analog_en[14] , \mprj_io_analog_en[13] , \mprj_io_analog_en[12] , \mprj_io_analog_en[11] , \mprj_io_analog_en[10] , \mprj_io_analog_en[9] , \mprj_io_analog_en[8] , \mprj_io_analog_en[7] , \mprj_io_analog_en[6] , \mprj_io_analog_en[5] , \mprj_io_analog_en[4] , \mprj_io_analog_en[3] , \mprj_io_analog_en[2] , \mprj_io_analog_en[1] , \mprj_io_analog_en[0]  }),
+    .mprj_io_analog_pol({ \mprj_io_analog_pol[37] , \mprj_io_analog_pol[36] , \mprj_io_analog_pol[35] , \mprj_io_analog_pol[34] , \mprj_io_analog_pol[33] , \mprj_io_analog_pol[32] , \mprj_io_analog_pol[31] , \mprj_io_analog_pol[30] , \mprj_io_analog_pol[29] , \mprj_io_analog_pol[28] , \mprj_io_analog_pol[27] , \mprj_io_analog_pol[26] , \mprj_io_analog_pol[25] , \mprj_io_analog_pol[24] , \mprj_io_analog_pol[23] , \mprj_io_analog_pol[22] , \mprj_io_analog_pol[21] , \mprj_io_analog_pol[20] , \mprj_io_analog_pol[19] , \mprj_io_analog_pol[18] , \mprj_io_analog_pol[17] , \mprj_io_analog_pol[16] , \mprj_io_analog_pol[15] , \mprj_io_analog_pol[14] , \mprj_io_analog_pol[13] , \mprj_io_analog_pol[12] , \mprj_io_analog_pol[11] , \mprj_io_analog_pol[10] , \mprj_io_analog_pol[9] , \mprj_io_analog_pol[8] , \mprj_io_analog_pol[7] , \mprj_io_analog_pol[6] , \mprj_io_analog_pol[5] , \mprj_io_analog_pol[4] , \mprj_io_analog_pol[3] , \mprj_io_analog_pol[2] , \mprj_io_analog_pol[1] , \mprj_io_analog_pol[0]  }),
+    .mprj_io_analog_sel({ \mprj_io_analog_sel[37] , \mprj_io_analog_sel[36] , \mprj_io_analog_sel[35] , \mprj_io_analog_sel[34] , \mprj_io_analog_sel[33] , \mprj_io_analog_sel[32] , \mprj_io_analog_sel[31] , \mprj_io_analog_sel[30] , \mprj_io_analog_sel[29] , \mprj_io_analog_sel[28] , \mprj_io_analog_sel[27] , \mprj_io_analog_sel[26] , \mprj_io_analog_sel[25] , \mprj_io_analog_sel[24] , \mprj_io_analog_sel[23] , \mprj_io_analog_sel[22] , \mprj_io_analog_sel[21] , \mprj_io_analog_sel[20] , \mprj_io_analog_sel[19] , \mprj_io_analog_sel[18] , \mprj_io_analog_sel[17] , \mprj_io_analog_sel[16] , \mprj_io_analog_sel[15] , \mprj_io_analog_sel[14] , \mprj_io_analog_sel[13] , \mprj_io_analog_sel[12] , \mprj_io_analog_sel[11] , \mprj_io_analog_sel[10] , \mprj_io_analog_sel[9] , \mprj_io_analog_sel[8] , \mprj_io_analog_sel[7] , \mprj_io_analog_sel[6] , \mprj_io_analog_sel[5] , \mprj_io_analog_sel[4] , \mprj_io_analog_sel[3] , \mprj_io_analog_sel[2] , \mprj_io_analog_sel[1] , \mprj_io_analog_sel[0]  }),
+    .mprj_io_dm({ \mprj_io_dm[113] , \mprj_io_dm[112] , \mprj_io_dm[111] , \mprj_io_dm[110] , \mprj_io_dm[109] , \mprj_io_dm[108] , \mprj_io_dm[107] , \mprj_io_dm[106] , \mprj_io_dm[105] , \mprj_io_dm[104] , \mprj_io_dm[103] , \mprj_io_dm[102] , \mprj_io_dm[101] , \mprj_io_dm[100] , \mprj_io_dm[99] , \mprj_io_dm[98] , \mprj_io_dm[97] , \mprj_io_dm[96] , \mprj_io_dm[95] , \mprj_io_dm[94] , \mprj_io_dm[93] , \mprj_io_dm[92] , \mprj_io_dm[91] , \mprj_io_dm[90] , \mprj_io_dm[89] , \mprj_io_dm[88] , \mprj_io_dm[87] , \mprj_io_dm[86] , \mprj_io_dm[85] , \mprj_io_dm[84] , \mprj_io_dm[83] , \mprj_io_dm[82] , \mprj_io_dm[81] , \mprj_io_dm[80] , \mprj_io_dm[79] , \mprj_io_dm[78] , \mprj_io_dm[77] , \mprj_io_dm[76] , \mprj_io_dm[75] , \mprj_io_dm[74] , \mprj_io_dm[73] , \mprj_io_dm[72] , \mprj_io_dm[71] , \mprj_io_dm[70] , \mprj_io_dm[69] , \mprj_io_dm[68] , \mprj_io_dm[67] , \mprj_io_dm[66] , \mprj_io_dm[65] , \mprj_io_dm[64] , \mprj_io_dm[63] , \mprj_io_dm[62] , \mprj_io_dm[61] , \mprj_io_dm[60] , \mprj_io_dm[59] , \mprj_io_dm[58] , \mprj_io_dm[57] , \mprj_io_dm[56] , \mprj_io_dm[55] , \mprj_io_dm[54] , \mprj_io_dm[53] , \mprj_io_dm[52] , \mprj_io_dm[51] , \mprj_io_dm[50] , \mprj_io_dm[49] , \mprj_io_dm[48] , \mprj_io_dm[47] , \mprj_io_dm[46] , \mprj_io_dm[45] , \mprj_io_dm[44] , \mprj_io_dm[43] , \mprj_io_dm[42] , \mprj_io_dm[41] , \mprj_io_dm[40] , \mprj_io_dm[39] , \mprj_io_dm[38] , \mprj_io_dm[37] , \mprj_io_dm[36] , \mprj_io_dm[35] , \mprj_io_dm[34] , \mprj_io_dm[33] , \mprj_io_dm[32] , \mprj_io_dm[31] , \mprj_io_dm[30] , \mprj_io_dm[29] , \mprj_io_dm[28] , \mprj_io_dm[27] , \mprj_io_dm[26] , \mprj_io_dm[25] , \mprj_io_dm[24] , \mprj_io_dm[23] , \mprj_io_dm[22] , \mprj_io_dm[21] , \mprj_io_dm[20] , \mprj_io_dm[19] , \mprj_io_dm[18] , \mprj_io_dm[17] , \mprj_io_dm[16] , \mprj_io_dm[15] , \mprj_io_dm[14] , \mprj_io_dm[13] , \mprj_io_dm[12] , \mprj_io_dm[11] , \mprj_io_dm[10] , \mprj_io_dm[9] , \mprj_io_dm[8] , \mprj_io_dm[7] , \mprj_io_dm[6] , \mprj_io_dm[5] , \mprj_io_dm[4] , \mprj_io_dm[3] , \mprj_io_dm[2] , \mprj_io_dm[1] , \mprj_io_dm[0]  }),
+    .mprj_io_holdover({ \mprj_io_holdover[37] , \mprj_io_holdover[36] , \mprj_io_holdover[35] , \mprj_io_holdover[34] , \mprj_io_holdover[33] , \mprj_io_holdover[32] , \mprj_io_holdover[31] , \mprj_io_holdover[30] , \mprj_io_holdover[29] , \mprj_io_holdover[28] , \mprj_io_holdover[27] , \mprj_io_holdover[26] , \mprj_io_holdover[25] , \mprj_io_holdover[24] , \mprj_io_holdover[23] , \mprj_io_holdover[22] , \mprj_io_holdover[21] , \mprj_io_holdover[20] , \mprj_io_holdover[19] , \mprj_io_holdover[18] , \mprj_io_holdover[17] , \mprj_io_holdover[16] , \mprj_io_holdover[15] , \mprj_io_holdover[14] , \mprj_io_holdover[13] , \mprj_io_holdover[12] , \mprj_io_holdover[11] , \mprj_io_holdover[10] , \mprj_io_holdover[9] , \mprj_io_holdover[8] , \mprj_io_holdover[7] , \mprj_io_holdover[6] , \mprj_io_holdover[5] , \mprj_io_holdover[4] , \mprj_io_holdover[3] , \mprj_io_holdover[2] , \mprj_io_holdover[1] , \mprj_io_holdover[0]  }),
+    .mprj_io_ib_mode_sel({ \mprj_io_ib_mode_sel[37] , \mprj_io_ib_mode_sel[36] , \mprj_io_ib_mode_sel[35] , \mprj_io_ib_mode_sel[34] , \mprj_io_ib_mode_sel[33] , \mprj_io_ib_mode_sel[32] , \mprj_io_ib_mode_sel[31] , \mprj_io_ib_mode_sel[30] , \mprj_io_ib_mode_sel[29] , \mprj_io_ib_mode_sel[28] , \mprj_io_ib_mode_sel[27] , \mprj_io_ib_mode_sel[26] , \mprj_io_ib_mode_sel[25] , \mprj_io_ib_mode_sel[24] , \mprj_io_ib_mode_sel[23] , \mprj_io_ib_mode_sel[22] , \mprj_io_ib_mode_sel[21] , \mprj_io_ib_mode_sel[20] , \mprj_io_ib_mode_sel[19] , \mprj_io_ib_mode_sel[18] , \mprj_io_ib_mode_sel[17] , \mprj_io_ib_mode_sel[16] , \mprj_io_ib_mode_sel[15] , \mprj_io_ib_mode_sel[14] , \mprj_io_ib_mode_sel[13] , \mprj_io_ib_mode_sel[12] , \mprj_io_ib_mode_sel[11] , \mprj_io_ib_mode_sel[10] , \mprj_io_ib_mode_sel[9] , \mprj_io_ib_mode_sel[8] , \mprj_io_ib_mode_sel[7] , \mprj_io_ib_mode_sel[6] , \mprj_io_ib_mode_sel[5] , \mprj_io_ib_mode_sel[4] , \mprj_io_ib_mode_sel[3] , \mprj_io_ib_mode_sel[2] , \mprj_io_ib_mode_sel[1] , \mprj_io_ib_mode_sel[0]  }),
+    .mprj_io_in({ \mprj_io_in[37] , \mprj_io_in[36] , \mprj_io_in[35] , \mprj_io_in[34] , \mprj_io_in[33] , \mprj_io_in[32] , \mprj_io_in[31] , \mprj_io_in[30] , \mprj_io_in[29] , \mprj_io_in[28] , \mprj_io_in[27] , \mprj_io_in[26] , \mprj_io_in[25] , \mprj_io_in[24] , \mprj_io_in[23] , \mprj_io_in[22] , \mprj_io_in[21] , \mprj_io_in[20] , \mprj_io_in[19] , \mprj_io_in[18] , \mprj_io_in[17] , \mprj_io_in[16] , \mprj_io_in[15] , \mprj_io_in[14] , \mprj_io_in[13] , \mprj_io_in[12] , \mprj_io_in[11] , \mprj_io_in[10] , \mprj_io_in[9] , \mprj_io_in[8] , \mprj_io_in[7] , \mprj_io_in[6] , \mprj_io_in[5] , \mprj_io_in[4] , \mprj_io_in[3] , \mprj_io_in[2] , \mprj_io_in[1] , \mprj_io_in[0]  }),
+    .mprj_io_inp_dis({ \mprj_io_inp_dis[37] , \mprj_io_inp_dis[36] , \mprj_io_inp_dis[35] , \mprj_io_inp_dis[34] , \mprj_io_inp_dis[33] , \mprj_io_inp_dis[32] , \mprj_io_inp_dis[31] , \mprj_io_inp_dis[30] , \mprj_io_inp_dis[29] , \mprj_io_inp_dis[28] , \mprj_io_inp_dis[27] , \mprj_io_inp_dis[26] , \mprj_io_inp_dis[25] , \mprj_io_inp_dis[24] , \mprj_io_inp_dis[23] , \mprj_io_inp_dis[22] , \mprj_io_inp_dis[21] , \mprj_io_inp_dis[20] , \mprj_io_inp_dis[19] , \mprj_io_inp_dis[18] , \mprj_io_inp_dis[17] , \mprj_io_inp_dis[16] , \mprj_io_inp_dis[15] , \mprj_io_inp_dis[14] , \mprj_io_inp_dis[13] , \mprj_io_inp_dis[12] , \mprj_io_inp_dis[11] , \mprj_io_inp_dis[10] , \mprj_io_inp_dis[9] , \mprj_io_inp_dis[8] , \mprj_io_inp_dis[7] , \mprj_io_inp_dis[6] , \mprj_io_inp_dis[5] , \mprj_io_inp_dis[4] , \mprj_io_inp_dis[3] , \mprj_io_inp_dis[2] , \mprj_io_inp_dis[1] , \mprj_io_inp_dis[0]  }),
+    .mprj_io_oeb({ \mprj_io_oeb[37] , \mprj_io_oeb[36] , \mprj_io_oeb[35] , \mprj_io_oeb[34] , \mprj_io_oeb[33] , \mprj_io_oeb[32] , \mprj_io_oeb[31] , \mprj_io_oeb[30] , \mprj_io_oeb[29] , \mprj_io_oeb[28] , \mprj_io_oeb[27] , \mprj_io_oeb[26] , \mprj_io_oeb[25] , \mprj_io_oeb[24] , \mprj_io_oeb[23] , \mprj_io_oeb[22] , \mprj_io_oeb[21] , \mprj_io_oeb[20] , \mprj_io_oeb[19] , \mprj_io_oeb[18] , \mprj_io_oeb[17] , \mprj_io_oeb[16] , \mprj_io_oeb[15] , \mprj_io_oeb[14] , \mprj_io_oeb[13] , \mprj_io_oeb[12] , \mprj_io_oeb[11] , \mprj_io_oeb[10] , \mprj_io_oeb[9] , \mprj_io_oeb[8] , \mprj_io_oeb[7] , \mprj_io_oeb[6] , \mprj_io_oeb[5] , \mprj_io_oeb[4] , \mprj_io_oeb[3] , \mprj_io_oeb[2] , \mprj_io_oeb[1] , \mprj_io_oeb[0]  }),
+    .mprj_io_one({ \mprj_io_one[37] , \mprj_io_one[36] , \mprj_io_one[35] , \mprj_io_one[34] , \mprj_io_one[33] , \mprj_io_one[32] , \mprj_io_one[31] , \mprj_io_one[30] , \mprj_io_one[29] , \mprj_io_one[28] , \mprj_io_one[27] , \mprj_io_one[26] , \mprj_io_one[25] , \mprj_io_one[24] , \mprj_io_one[23] , \mprj_io_one[22] , \mprj_io_one[21] , \mprj_io_one[20] , \mprj_io_one[19] , \mprj_io_one[18] , \mprj_io_one[17] , \mprj_io_one[16] , \mprj_io_one[15] , \mprj_io_one[14] , \mprj_io_one[13] , \mprj_io_one[12] , \mprj_io_one[11] , \mprj_io_one[10] , \mprj_io_one[9] , \mprj_io_one[8] , \mprj_io_one[7] , \mprj_io_one[6] , \mprj_io_one[5] , \mprj_io_one[4] , \mprj_io_one[3] , \mprj_io_one[2] , \mprj_io_one[1] , \mprj_io_one[0]  }),
+    .mprj_io_out({ \mprj_io_out[37] , \mprj_io_out[36] , \mprj_io_out[35] , \mprj_io_out[34] , \mprj_io_out[33] , \mprj_io_out[32] , \mprj_io_out[31] , \mprj_io_out[30] , \mprj_io_out[29] , \mprj_io_out[28] , \mprj_io_out[27] , \mprj_io_out[26] , \mprj_io_out[25] , \mprj_io_out[24] , \mprj_io_out[23] , \mprj_io_out[22] , \mprj_io_out[21] , \mprj_io_out[20] , \mprj_io_out[19] , \mprj_io_out[18] , \mprj_io_out[17] , \mprj_io_out[16] , \mprj_io_out[15] , \mprj_io_out[14] , \mprj_io_out[13] , \mprj_io_out[12] , \mprj_io_out[11] , \mprj_io_out[10] , \mprj_io_out[9] , \mprj_io_out[8] , \mprj_io_out[7] , \mprj_io_out[6] , \mprj_io_out[5] , \mprj_io_out[4] , \mprj_io_out[3] , \mprj_io_out[2] , \mprj_io_out[1] , \mprj_io_out[0]  }),
+    .mprj_io_slow_sel({ \mprj_io_slow_sel[37] , \mprj_io_slow_sel[36] , \mprj_io_slow_sel[35] , \mprj_io_slow_sel[34] , \mprj_io_slow_sel[33] , \mprj_io_slow_sel[32] , \mprj_io_slow_sel[31] , \mprj_io_slow_sel[30] , \mprj_io_slow_sel[29] , \mprj_io_slow_sel[28] , \mprj_io_slow_sel[27] , \mprj_io_slow_sel[26] , \mprj_io_slow_sel[25] , \mprj_io_slow_sel[24] , \mprj_io_slow_sel[23] , \mprj_io_slow_sel[22] , \mprj_io_slow_sel[21] , \mprj_io_slow_sel[20] , \mprj_io_slow_sel[19] , \mprj_io_slow_sel[18] , \mprj_io_slow_sel[17] , \mprj_io_slow_sel[16] , \mprj_io_slow_sel[15] , \mprj_io_slow_sel[14] , \mprj_io_slow_sel[13] , \mprj_io_slow_sel[12] , \mprj_io_slow_sel[11] , \mprj_io_slow_sel[10] , \mprj_io_slow_sel[9] , \mprj_io_slow_sel[8] , \mprj_io_slow_sel[7] , \mprj_io_slow_sel[6] , \mprj_io_slow_sel[5] , \mprj_io_slow_sel[4] , \mprj_io_slow_sel[3] , \mprj_io_slow_sel[2] , \mprj_io_slow_sel[1] , \mprj_io_slow_sel[0]  }),
+    .mprj_io_vtrip_sel({ \mprj_io_vtrip_sel[37] , \mprj_io_vtrip_sel[36] , \mprj_io_vtrip_sel[35] , \mprj_io_vtrip_sel[34] , \mprj_io_vtrip_sel[33] , \mprj_io_vtrip_sel[32] , \mprj_io_vtrip_sel[31] , \mprj_io_vtrip_sel[30] , \mprj_io_vtrip_sel[29] , \mprj_io_vtrip_sel[28] , \mprj_io_vtrip_sel[27] , \mprj_io_vtrip_sel[26] , \mprj_io_vtrip_sel[25] , \mprj_io_vtrip_sel[24] , \mprj_io_vtrip_sel[23] , \mprj_io_vtrip_sel[22] , \mprj_io_vtrip_sel[21] , \mprj_io_vtrip_sel[20] , \mprj_io_vtrip_sel[19] , \mprj_io_vtrip_sel[18] , \mprj_io_vtrip_sel[17] , \mprj_io_vtrip_sel[16] , \mprj_io_vtrip_sel[15] , \mprj_io_vtrip_sel[14] , \mprj_io_vtrip_sel[13] , \mprj_io_vtrip_sel[12] , \mprj_io_vtrip_sel[11] , \mprj_io_vtrip_sel[10] , \mprj_io_vtrip_sel[9] , \mprj_io_vtrip_sel[8] , \mprj_io_vtrip_sel[7] , \mprj_io_vtrip_sel[6] , \mprj_io_vtrip_sel[5] , \mprj_io_vtrip_sel[4] , \mprj_io_vtrip_sel[3] , \mprj_io_vtrip_sel[2] , \mprj_io_vtrip_sel[1] , \mprj_io_vtrip_sel[0]  }),
+    .por(por_l_buf),
+    .porb_h(porb_h),
+    .resetb(resetb),
+    .resetb_core_h(rstb_h),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vccd1_pad(vccd1),
+    .vccd2(vccd2_core),
+    .vccd2_pad(vccd2),
+    .vccd_pad(vccd),
+    .vdda(vdda_core),
+    .vdda1(vdda1_core),
+    .vdda1_pad(vdda1),
+    .vdda1_pad2(vdda1_2),
+    .vdda2(vdda2_core),
+    .vdda2_pad(vdda2),
+    .vdda_pad(vdda),
+    .vddio(vddio_core),
+    .vddio_pad(vddio),
+    .vddio_pad2(vddio_2),
+    .vssa(vssa_core),
+    .vssa1(vssa1_core),
+    .vssa1_pad(vssa1),
+    .vssa1_pad2(vssa1_2),
+    .vssa2(vssa2_core),
+    .vssa2_pad(vssa2),
+    .vssa_pad(vssa),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .vssd1_pad(vssd1),
+    .vssd2(vssd2_core),
+    .vssd2_pad(vssd2),
+    .vssd_pad(vssd),
+    .vssio(vssio_core),
+    .vssio_pad(vssio),
+    .vssio_pad2(vssio_2)
+  );
+  digital_pll pll (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .clockp({ pll_clk, pll_clk90 }),
+    .dco(spi_pll_dco_ena),
+    .div({ \spi_pll_div[4] , \spi_pll_div[3] , \spi_pll_div[2] , \spi_pll_div[1] , \spi_pll_div[0]  }),
+    .enable(spi_pll_ena),
+    .ext_trim({ \spi_pll_trim[25] , \spi_pll_trim[24] , \spi_pll_trim[23] , \spi_pll_trim[22] , \spi_pll_trim[21] , \spi_pll_trim[20] , \spi_pll_trim[19] , \spi_pll_trim[18] , \spi_pll_trim[17] , \spi_pll_trim[16] , \spi_pll_trim[15] , \spi_pll_trim[14] , \spi_pll_trim[13] , \spi_pll_trim[12] , \spi_pll_trim[11] , \spi_pll_trim[10] , \spi_pll_trim[9] , \spi_pll_trim[8] , \spi_pll_trim[7] , \spi_pll_trim[6] , \spi_pll_trim[5] , \spi_pll_trim[4] , \spi_pll_trim[3] , \spi_pll_trim[2] , \spi_pll_trim[1] , \spi_pll_trim[0]  }),
+    .osc(clock_core_buf),
+    .resetb(rstb_l_buf)
+  );
+  simple_por por (
+    .por_l(por_l),
+    .porb_h(porb_h),
+    .porb_l(porb_l),
+    .vdd1v8(vccd_core),
+    .vdd3v3(vddio_core),
+    .vss1v8(vssd_core),
+    .vss3v3(vssio_core)
+  );
+  xres_buf rstb_level (
+    .A(rstb_h),
+    .LVGND(vssd_core),
+    .LVPWR(vccd_core),
+    .VGND(vssio_core),
+    .VPWR(vddio_core),
+    .X(rstb_l)
+  );
+  gpio_signal_buffering sigbuf (
+    .mgmt_io_in_buf({ \mgmt_io_in_hk[37] , \mgmt_io_in_hk[36] , \mgmt_io_in_hk[35] , \mgmt_io_in_hk[34] , \mgmt_io_in_hk[33] , \mgmt_io_in_hk[32] , \mgmt_io_in_hk[31] , \mgmt_io_in_hk[30] , \mgmt_io_in_hk[29] , \mgmt_io_in_hk[28] , \mgmt_io_in_hk[27] , \mgmt_io_in_hk[26] , \mgmt_io_in_hk[25] , \mgmt_io_in_hk[24] , \mgmt_io_in_hk[23] , \mgmt_io_in_hk[22] , \mgmt_io_in_hk[21] , \mgmt_io_in_hk[20] , \mgmt_io_in_hk[19] , \mgmt_io_in_hk[18] , \mgmt_io_in_hk[17] , \mgmt_io_in_hk[16] , \mgmt_io_in_hk[15] , \mgmt_io_in_hk[14] , \mgmt_io_in_hk[13] , \mgmt_io_in_hk[12] , \mgmt_io_in_hk[11] , \mgmt_io_in_hk[10] , \mgmt_io_in_hk[9] , \mgmt_io_in_hk[8] , \mgmt_io_in_hk[7]  }),
+    .mgmt_io_in_unbuf({ \mgmt_io_in[37] , \mgmt_io_in[36] , \mgmt_io_in[35] , \mgmt_io_in[34] , \mgmt_io_in[33] , \mgmt_io_in[32] , \mgmt_io_in[31] , \mgmt_io_in[30] , \mgmt_io_in[29] , \mgmt_io_in[28] , \mgmt_io_in[27] , \mgmt_io_in[26] , \mgmt_io_in[25] , \mgmt_io_in[24] , \mgmt_io_in[23] , \mgmt_io_in[22] , \mgmt_io_in[21] , \mgmt_io_in[20] , \mgmt_io_in[19] , \mgmt_io_in[18] , \mgmt_io_in[17] , \mgmt_io_in[16] , \mgmt_io_in[15] , \mgmt_io_in[14] , \mgmt_io_in[13] , \mgmt_io_in[12] , \mgmt_io_in[11] , \mgmt_io_in[10] , \mgmt_io_in[9] , \mgmt_io_in[8] , \mgmt_io_in[7]  }),
+    .mgmt_io_oeb_buf({ \mgmt_io_oeb[37] , \mgmt_io_oeb[36] , \mgmt_io_oeb[35]  }),
+    .mgmt_io_oeb_unbuf({ \mgmt_io_oeb_hk[37] , \mgmt_io_oeb_hk[36] , \mgmt_io_oeb_hk[35]  }),
+    .mgmt_io_out_buf({ \mgmt_io_out[37] , \mgmt_io_out[36] , \mgmt_io_out[35] , \mgmt_io_out[34] , \mgmt_io_out[33] , \mgmt_io_out[32] , \mgmt_io_out[31] , \mgmt_io_out[30] , \mgmt_io_out[29] , \mgmt_io_out[28] , \mgmt_io_out[27] , \mgmt_io_out[26] , \mgmt_io_out[25] , \mgmt_io_out[24] , \mgmt_io_out[23] , \mgmt_io_out[22] , \mgmt_io_out[21] , \mgmt_io_out[20] , \mgmt_io_out[19] , \mgmt_io_out[18] , \mgmt_io_out[17] , \mgmt_io_out[16] , \mgmt_io_out[15] , \mgmt_io_out[14] , \mgmt_io_out[13] , \mgmt_io_out[12] , \mgmt_io_out[11] , \mgmt_io_out[10] , \mgmt_io_out[9] , \mgmt_io_out[8] , \mgmt_io_out[7]  }),
+    .mgmt_io_out_unbuf({ \mgmt_io_out_hk[37] , \mgmt_io_out_hk[36] , \mgmt_io_out_hk[35] , \mgmt_io_out_hk[34] , \mgmt_io_out_hk[33] , \mgmt_io_out_hk[32] , \mgmt_io_out_hk[31] , \mgmt_io_out_hk[30] , \mgmt_io_out_hk[29] , \mgmt_io_out_hk[28] , \mgmt_io_out_hk[27] , \mgmt_io_out_hk[26] , \mgmt_io_out_hk[25] , \mgmt_io_out_hk[24] , \mgmt_io_out_hk[23] , \mgmt_io_out_hk[22] , \mgmt_io_out_hk[21] , \mgmt_io_out_hk[20] , \mgmt_io_out_hk[19] , \mgmt_io_out_hk[18] , \mgmt_io_out_hk[17] , \mgmt_io_out_hk[16] , \mgmt_io_out_hk[15] , \mgmt_io_out_hk[14] , \mgmt_io_out_hk[13] , \mgmt_io_out_hk[12] , \mgmt_io_out_hk[11] , \mgmt_io_out_hk[10] , \mgmt_io_out_hk[9] , \mgmt_io_out_hk[8] , \mgmt_io_out_hk[7]  }),
+    .vccd(vccd_core),
+    .vssd(vssd_core)
+  );
+  mgmt_core_wrapper soc (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .clk_in(caravel_clk_buf),
+    .clk_out(clk_passthru),
+    .core_clk(caravel_clk_buf),
+    .core_rstn(caravel_rstn_buf),
+    .debug_in(debug_in),
+    .debug_mode(debug_mode),
+    .debug_oeb(debug_oeb),
+    .debug_out(debug_out),
+    .flash_clk(flash_clk_core),
+    .flash_csb(flash_csb_core),
+    .flash_io0_di(flash_io0_di_core),
+    .flash_io0_do(flash_io0_do_core),
+    .flash_io0_oeb(flash_io0_oeb_core),
+    .flash_io1_di(flash_io1_di_core),
+    .flash_io1_do(flash_io1_do_core),
+    .flash_io1_oeb(flash_io1_oeb_core),
+    .flash_io2_di(flash_io2_di_core),
+    .flash_io2_do(flash_io2_do_core),
+    .flash_io2_oeb(flash_io2_oeb_core),
+    .flash_io3_di(flash_io3_di_core),
+    .flash_io3_do(flash_io3_do_core),
+    .flash_io3_oeb(flash_io3_oeb_core),
+    .gpio_in_pad(gpio_in_core),
+    .gpio_inenb_pad(gpio_inenb_core),
+    .gpio_mode0_pad(gpio_mode0_core),
+    .gpio_mode1_pad(gpio_mode1_core),
+    .gpio_out_pad(gpio_out_core),
+    .gpio_outenb_pad(gpio_outenb_core),
+    .hk_ack_i(hk_ack_i),
+    .hk_cyc_o(hk_cyc_o),
+    .hk_dat_i({ \hk_dat_i[31] , \hk_dat_i[30] , \hk_dat_i[29] , \hk_dat_i[28] , \hk_dat_i[27] , \hk_dat_i[26] , \hk_dat_i[25] , \hk_dat_i[24] , \hk_dat_i[23] , \hk_dat_i[22] , \hk_dat_i[21] , \hk_dat_i[20] , \hk_dat_i[19] , \hk_dat_i[18] , \hk_dat_i[17] , \hk_dat_i[16] , \hk_dat_i[15] , \hk_dat_i[14] , \hk_dat_i[13] , \hk_dat_i[12] , \hk_dat_i[11] , \hk_dat_i[10] , \hk_dat_i[9] , \hk_dat_i[8] , \hk_dat_i[7] , \hk_dat_i[6] , \hk_dat_i[5] , \hk_dat_i[4] , \hk_dat_i[3] , \hk_dat_i[2] , \hk_dat_i[1] , \hk_dat_i[0]  }),
+    .hk_stb_o(hk_stb_o),
+    .irq({ \irq_spi[2] , \irq_spi[1] , \irq_spi[0] , \user_irq[2] , \user_irq[1] , \user_irq[0]  }),
+    .la_iena({ \la_iena_mprj[127] , \la_iena_mprj[126] , \la_iena_mprj[125] , \la_iena_mprj[124] , \la_iena_mprj[123] , \la_iena_mprj[122] , \la_iena_mprj[121] , \la_iena_mprj[120] , \la_iena_mprj[119] , \la_iena_mprj[118] , \la_iena_mprj[117] , \la_iena_mprj[116] , \la_iena_mprj[115] , \la_iena_mprj[114] , \la_iena_mprj[113] , \la_iena_mprj[112] , \la_iena_mprj[111] , \la_iena_mprj[110] , \la_iena_mprj[109] , \la_iena_mprj[108] , \la_iena_mprj[107] , \la_iena_mprj[106] , \la_iena_mprj[105] , \la_iena_mprj[104] , \la_iena_mprj[103] , \la_iena_mprj[102] , \la_iena_mprj[101] , \la_iena_mprj[100] , \la_iena_mprj[99] , \la_iena_mprj[98] , \la_iena_mprj[97] , \la_iena_mprj[96] , \la_iena_mprj[95] , \la_iena_mprj[94] , \la_iena_mprj[93] , \la_iena_mprj[92] , \la_iena_mprj[91] , \la_iena_mprj[90] , \la_iena_mprj[89] , \la_iena_mprj[88] , \la_iena_mprj[87] , \la_iena_mprj[86] , \la_iena_mprj[85] , \la_iena_mprj[84] , \la_iena_mprj[83] , \la_iena_mprj[82] , \la_iena_mprj[81] , \la_iena_mprj[80] , \la_iena_mprj[79] , \la_iena_mprj[78] , \la_iena_mprj[77] , \la_iena_mprj[76] , \la_iena_mprj[75] , \la_iena_mprj[74] , \la_iena_mprj[73] , \la_iena_mprj[72] , \la_iena_mprj[71] , \la_iena_mprj[70] , \la_iena_mprj[69] , \la_iena_mprj[68] , \la_iena_mprj[67] , \la_iena_mprj[66] , \la_iena_mprj[65] , \la_iena_mprj[64] , \la_iena_mprj[63] , \la_iena_mprj[62] , \la_iena_mprj[61] , \la_iena_mprj[60] , \la_iena_mprj[59] , \la_iena_mprj[58] , \la_iena_mprj[57] , \la_iena_mprj[56] , \la_iena_mprj[55] , \la_iena_mprj[54] , \la_iena_mprj[53] , \la_iena_mprj[52] , \la_iena_mprj[51] , \la_iena_mprj[50] , \la_iena_mprj[49] , \la_iena_mprj[48] , \la_iena_mprj[47] , \la_iena_mprj[46] , \la_iena_mprj[45] , \la_iena_mprj[44] , \la_iena_mprj[43] , \la_iena_mprj[42] , \la_iena_mprj[41] , \la_iena_mprj[40] , \la_iena_mprj[39] , \la_iena_mprj[38] , \la_iena_mprj[37] , \la_iena_mprj[36] , \la_iena_mprj[35] , \la_iena_mprj[34] , \la_iena_mprj[33] , \la_iena_mprj[32] , \la_iena_mprj[31] , \la_iena_mprj[30] , \la_iena_mprj[29] , \la_iena_mprj[28] , \la_iena_mprj[27] , \la_iena_mprj[26] , \la_iena_mprj[25] , \la_iena_mprj[24] , \la_iena_mprj[23] , \la_iena_mprj[22] , \la_iena_mprj[21] , \la_iena_mprj[20] , \la_iena_mprj[19] , \la_iena_mprj[18] , \la_iena_mprj[17] , \la_iena_mprj[16] , \la_iena_mprj[15] , \la_iena_mprj[14] , \la_iena_mprj[13] , \la_iena_mprj[12] , \la_iena_mprj[11] , \la_iena_mprj[10] , \la_iena_mprj[9] , \la_iena_mprj[8] , \la_iena_mprj[7] , \la_iena_mprj[6] , \la_iena_mprj[5] , \la_iena_mprj[4] , \la_iena_mprj[3] , \la_iena_mprj[2] , \la_iena_mprj[1] , \la_iena_mprj[0]  }),
+    .la_input({ \la_data_in_mprj[127] , \la_data_in_mprj[126] , \la_data_in_mprj[125] , \la_data_in_mprj[124] , \la_data_in_mprj[123] , \la_data_in_mprj[122] , \la_data_in_mprj[121] , \la_data_in_mprj[120] , \la_data_in_mprj[119] , \la_data_in_mprj[118] , \la_data_in_mprj[117] , \la_data_in_mprj[116] , \la_data_in_mprj[115] , \la_data_in_mprj[114] , \la_data_in_mprj[113] , \la_data_in_mprj[112] , \la_data_in_mprj[111] , \la_data_in_mprj[110] , \la_data_in_mprj[109] , \la_data_in_mprj[108] , \la_data_in_mprj[107] , \la_data_in_mprj[106] , \la_data_in_mprj[105] , \la_data_in_mprj[104] , \la_data_in_mprj[103] , \la_data_in_mprj[102] , \la_data_in_mprj[101] , \la_data_in_mprj[100] , \la_data_in_mprj[99] , \la_data_in_mprj[98] , \la_data_in_mprj[97] , \la_data_in_mprj[96] , \la_data_in_mprj[95] , \la_data_in_mprj[94] , \la_data_in_mprj[93] , \la_data_in_mprj[92] , \la_data_in_mprj[91] , \la_data_in_mprj[90] , \la_data_in_mprj[89] , \la_data_in_mprj[88] , \la_data_in_mprj[87] , \la_data_in_mprj[86] , \la_data_in_mprj[85] , \la_data_in_mprj[84] , \la_data_in_mprj[83] , \la_data_in_mprj[82] , \la_data_in_mprj[81] , \la_data_in_mprj[80] , \la_data_in_mprj[79] , \la_data_in_mprj[78] , \la_data_in_mprj[77] , \la_data_in_mprj[76] , \la_data_in_mprj[75] , \la_data_in_mprj[74] , \la_data_in_mprj[73] , \la_data_in_mprj[72] , \la_data_in_mprj[71] , \la_data_in_mprj[70] , \la_data_in_mprj[69] , \la_data_in_mprj[68] , \la_data_in_mprj[67] , \la_data_in_mprj[66] , \la_data_in_mprj[65] , \la_data_in_mprj[64] , \la_data_in_mprj[63] , \la_data_in_mprj[62] , \la_data_in_mprj[61] , \la_data_in_mprj[60] , \la_data_in_mprj[59] , \la_data_in_mprj[58] , \la_data_in_mprj[57] , \la_data_in_mprj[56] , \la_data_in_mprj[55] , \la_data_in_mprj[54] , \la_data_in_mprj[53] , \la_data_in_mprj[52] , \la_data_in_mprj[51] , \la_data_in_mprj[50] , \la_data_in_mprj[49] , \la_data_in_mprj[48] , \la_data_in_mprj[47] , \la_data_in_mprj[46] , \la_data_in_mprj[45] , \la_data_in_mprj[44] , \la_data_in_mprj[43] , \la_data_in_mprj[42] , \la_data_in_mprj[41] , \la_data_in_mprj[40] , \la_data_in_mprj[39] , \la_data_in_mprj[38] , \la_data_in_mprj[37] , \la_data_in_mprj[36] , \la_data_in_mprj[35] , \la_data_in_mprj[34] , \la_data_in_mprj[33] , \la_data_in_mprj[32] , \la_data_in_mprj[31] , \la_data_in_mprj[30] , \la_data_in_mprj[29] , \la_data_in_mprj[28] , \la_data_in_mprj[27] , \la_data_in_mprj[26] , \la_data_in_mprj[25] , \la_data_in_mprj[24] , \la_data_in_mprj[23] , \la_data_in_mprj[22] , \la_data_in_mprj[21] , \la_data_in_mprj[20] , \la_data_in_mprj[19] , \la_data_in_mprj[18] , \la_data_in_mprj[17] , \la_data_in_mprj[16] , \la_data_in_mprj[15] , \la_data_in_mprj[14] , \la_data_in_mprj[13] , \la_data_in_mprj[12] , \la_data_in_mprj[11] , \la_data_in_mprj[10] , \la_data_in_mprj[9] , \la_data_in_mprj[8] , \la_data_in_mprj[7] , \la_data_in_mprj[6] , \la_data_in_mprj[5] , \la_data_in_mprj[4] , \la_data_in_mprj[3] , \la_data_in_mprj[2] , \la_data_in_mprj[1] , \la_data_in_mprj[0]  }),
+    .la_oenb({ \la_oenb_mprj[127] , \la_oenb_mprj[126] , \la_oenb_mprj[125] , \la_oenb_mprj[124] , \la_oenb_mprj[123] , \la_oenb_mprj[122] , \la_oenb_mprj[121] , \la_oenb_mprj[120] , \la_oenb_mprj[119] , \la_oenb_mprj[118] , \la_oenb_mprj[117] , \la_oenb_mprj[116] , \la_oenb_mprj[115] , \la_oenb_mprj[114] , \la_oenb_mprj[113] , \la_oenb_mprj[112] , \la_oenb_mprj[111] , \la_oenb_mprj[110] , \la_oenb_mprj[109] , \la_oenb_mprj[108] , \la_oenb_mprj[107] , \la_oenb_mprj[106] , \la_oenb_mprj[105] , \la_oenb_mprj[104] , \la_oenb_mprj[103] , \la_oenb_mprj[102] , \la_oenb_mprj[101] , \la_oenb_mprj[100] , \la_oenb_mprj[99] , \la_oenb_mprj[98] , \la_oenb_mprj[97] , \la_oenb_mprj[96] , \la_oenb_mprj[95] , \la_oenb_mprj[94] , \la_oenb_mprj[93] , \la_oenb_mprj[92] , \la_oenb_mprj[91] , \la_oenb_mprj[90] , \la_oenb_mprj[89] , \la_oenb_mprj[88] , \la_oenb_mprj[87] , \la_oenb_mprj[86] , \la_oenb_mprj[85] , \la_oenb_mprj[84] , \la_oenb_mprj[83] , \la_oenb_mprj[82] , \la_oenb_mprj[81] , \la_oenb_mprj[80] , \la_oenb_mprj[79] , \la_oenb_mprj[78] , \la_oenb_mprj[77] , \la_oenb_mprj[76] , \la_oenb_mprj[75] , \la_oenb_mprj[74] , \la_oenb_mprj[73] , \la_oenb_mprj[72] , \la_oenb_mprj[71] , \la_oenb_mprj[70] , \la_oenb_mprj[69] , \la_oenb_mprj[68] , \la_oenb_mprj[67] , \la_oenb_mprj[66] , \la_oenb_mprj[65] , \la_oenb_mprj[64] , \la_oenb_mprj[63] , \la_oenb_mprj[62] , \la_oenb_mprj[61] , \la_oenb_mprj[60] , \la_oenb_mprj[59] , \la_oenb_mprj[58] , \la_oenb_mprj[57] , \la_oenb_mprj[56] , \la_oenb_mprj[55] , \la_oenb_mprj[54] , \la_oenb_mprj[53] , \la_oenb_mprj[52] , \la_oenb_mprj[51] , \la_oenb_mprj[50] , \la_oenb_mprj[49] , \la_oenb_mprj[48] , \la_oenb_mprj[47] , \la_oenb_mprj[46] , \la_oenb_mprj[45] , \la_oenb_mprj[44] , \la_oenb_mprj[43] , \la_oenb_mprj[42] , \la_oenb_mprj[41] , \la_oenb_mprj[40] , \la_oenb_mprj[39] , \la_oenb_mprj[38] , \la_oenb_mprj[37] , \la_oenb_mprj[36] , \la_oenb_mprj[35] , \la_oenb_mprj[34] , \la_oenb_mprj[33] , \la_oenb_mprj[32] , \la_oenb_mprj[31] , \la_oenb_mprj[30] , \la_oenb_mprj[29] , \la_oenb_mprj[28] , \la_oenb_mprj[27] , \la_oenb_mprj[26] , \la_oenb_mprj[25] , \la_oenb_mprj[24] , \la_oenb_mprj[23] , \la_oenb_mprj[22] , \la_oenb_mprj[21] , \la_oenb_mprj[20] , \la_oenb_mprj[19] , \la_oenb_mprj[18] , \la_oenb_mprj[17] , \la_oenb_mprj[16] , \la_oenb_mprj[15] , \la_oenb_mprj[14] , \la_oenb_mprj[13] , \la_oenb_mprj[12] , \la_oenb_mprj[11] , \la_oenb_mprj[10] , \la_oenb_mprj[9] , \la_oenb_mprj[8] , \la_oenb_mprj[7] , \la_oenb_mprj[6] , \la_oenb_mprj[5] , \la_oenb_mprj[4] , \la_oenb_mprj[3] , \la_oenb_mprj[2] , \la_oenb_mprj[1] , \la_oenb_mprj[0]  }),
+    .la_output({ \la_data_out_mprj[127] , \la_data_out_mprj[126] , \la_data_out_mprj[125] , \la_data_out_mprj[124] , \la_data_out_mprj[123] , \la_data_out_mprj[122] , \la_data_out_mprj[121] , \la_data_out_mprj[120] , \la_data_out_mprj[119] , \la_data_out_mprj[118] , \la_data_out_mprj[117] , \la_data_out_mprj[116] , \la_data_out_mprj[115] , \la_data_out_mprj[114] , \la_data_out_mprj[113] , \la_data_out_mprj[112] , \la_data_out_mprj[111] , \la_data_out_mprj[110] , \la_data_out_mprj[109] , \la_data_out_mprj[108] , \la_data_out_mprj[107] , \la_data_out_mprj[106] , \la_data_out_mprj[105] , \la_data_out_mprj[104] , \la_data_out_mprj[103] , \la_data_out_mprj[102] , \la_data_out_mprj[101] , \la_data_out_mprj[100] , \la_data_out_mprj[99] , \la_data_out_mprj[98] , \la_data_out_mprj[97] , \la_data_out_mprj[96] , \la_data_out_mprj[95] , \la_data_out_mprj[94] , \la_data_out_mprj[93] , \la_data_out_mprj[92] , \la_data_out_mprj[91] , \la_data_out_mprj[90] , \la_data_out_mprj[89] , \la_data_out_mprj[88] , \la_data_out_mprj[87] , \la_data_out_mprj[86] , \la_data_out_mprj[85] , \la_data_out_mprj[84] , \la_data_out_mprj[83] , \la_data_out_mprj[82] , \la_data_out_mprj[81] , \la_data_out_mprj[80] , \la_data_out_mprj[79] , \la_data_out_mprj[78] , \la_data_out_mprj[77] , \la_data_out_mprj[76] , \la_data_out_mprj[75] , \la_data_out_mprj[74] , \la_data_out_mprj[73] , \la_data_out_mprj[72] , \la_data_out_mprj[71] , \la_data_out_mprj[70] , \la_data_out_mprj[69] , \la_data_out_mprj[68] , \la_data_out_mprj[67] , \la_data_out_mprj[66] , \la_data_out_mprj[65] , \la_data_out_mprj[64] , \la_data_out_mprj[63] , \la_data_out_mprj[62] , \la_data_out_mprj[61] , \la_data_out_mprj[60] , \la_data_out_mprj[59] , \la_data_out_mprj[58] , \la_data_out_mprj[57] , \la_data_out_mprj[56] , \la_data_out_mprj[55] , \la_data_out_mprj[54] , \la_data_out_mprj[53] , \la_data_out_mprj[52] , \la_data_out_mprj[51] , \la_data_out_mprj[50] , \la_data_out_mprj[49] , \la_data_out_mprj[48] , \la_data_out_mprj[47] , \la_data_out_mprj[46] , \la_data_out_mprj[45] , \la_data_out_mprj[44] , \la_data_out_mprj[43] , \la_data_out_mprj[42] , \la_data_out_mprj[41] , \la_data_out_mprj[40] , \la_data_out_mprj[39] , \la_data_out_mprj[38] , \la_data_out_mprj[37] , \la_data_out_mprj[36] , \la_data_out_mprj[35] , \la_data_out_mprj[34] , \la_data_out_mprj[33] , \la_data_out_mprj[32] , \la_data_out_mprj[31] , \la_data_out_mprj[30] , \la_data_out_mprj[29] , \la_data_out_mprj[28] , \la_data_out_mprj[27] , \la_data_out_mprj[26] , \la_data_out_mprj[25] , \la_data_out_mprj[24] , \la_data_out_mprj[23] , \la_data_out_mprj[22] , \la_data_out_mprj[21] , \la_data_out_mprj[20] , \la_data_out_mprj[19] , \la_data_out_mprj[18] , \la_data_out_mprj[17] , \la_data_out_mprj[16] , \la_data_out_mprj[15] , \la_data_out_mprj[14] , \la_data_out_mprj[13] , \la_data_out_mprj[12] , \la_data_out_mprj[11] , \la_data_out_mprj[10] , \la_data_out_mprj[9] , \la_data_out_mprj[8] , \la_data_out_mprj[7] , \la_data_out_mprj[6] , \la_data_out_mprj[5] , \la_data_out_mprj[4] , \la_data_out_mprj[3] , \la_data_out_mprj[2] , \la_data_out_mprj[1] , \la_data_out_mprj[0]  }),
+    .mprj_ack_i(mprj_ack_i_core),
+    .mprj_adr_o({ \mprj_adr_o_core[31] , \mprj_adr_o_core[30] , \mprj_adr_o_core[29] , \mprj_adr_o_core[28] , \mprj_adr_o_core[27] , \mprj_adr_o_core[26] , \mprj_adr_o_core[25] , \mprj_adr_o_core[24] , \mprj_adr_o_core[23] , \mprj_adr_o_core[22] , \mprj_adr_o_core[21] , \mprj_adr_o_core[20] , \mprj_adr_o_core[19] , \mprj_adr_o_core[18] , \mprj_adr_o_core[17] , \mprj_adr_o_core[16] , \mprj_adr_o_core[15] , \mprj_adr_o_core[14] , \mprj_adr_o_core[13] , \mprj_adr_o_core[12] , \mprj_adr_o_core[11] , \mprj_adr_o_core[10] , \mprj_adr_o_core[9] , \mprj_adr_o_core[8] , \mprj_adr_o_core[7] , \mprj_adr_o_core[6] , \mprj_adr_o_core[5] , \mprj_adr_o_core[4] , \mprj_adr_o_core[3] , \mprj_adr_o_core[2] , \mprj_adr_o_core[1] , \mprj_adr_o_core[0]  }),
+    .mprj_cyc_o(mprj_cyc_o_core),
+    .mprj_dat_i({ \mprj_dat_i_core[31] , \mprj_dat_i_core[30] , \mprj_dat_i_core[29] , \mprj_dat_i_core[28] , \mprj_dat_i_core[27] , \mprj_dat_i_core[26] , \mprj_dat_i_core[25] , \mprj_dat_i_core[24] , \mprj_dat_i_core[23] , \mprj_dat_i_core[22] , \mprj_dat_i_core[21] , \mprj_dat_i_core[20] , \mprj_dat_i_core[19] , \mprj_dat_i_core[18] , \mprj_dat_i_core[17] , \mprj_dat_i_core[16] , \mprj_dat_i_core[15] , \mprj_dat_i_core[14] , \mprj_dat_i_core[13] , \mprj_dat_i_core[12] , \mprj_dat_i_core[11] , \mprj_dat_i_core[10] , \mprj_dat_i_core[9] , \mprj_dat_i_core[8] , \mprj_dat_i_core[7] , \mprj_dat_i_core[6] , \mprj_dat_i_core[5] , \mprj_dat_i_core[4] , \mprj_dat_i_core[3] , \mprj_dat_i_core[2] , \mprj_dat_i_core[1] , \mprj_dat_i_core[0]  }),
+    .mprj_dat_o({ \mprj_dat_o_core[31] , \mprj_dat_o_core[30] , \mprj_dat_o_core[29] , \mprj_dat_o_core[28] , \mprj_dat_o_core[27] , \mprj_dat_o_core[26] , \mprj_dat_o_core[25] , \mprj_dat_o_core[24] , \mprj_dat_o_core[23] , \mprj_dat_o_core[22] , \mprj_dat_o_core[21] , \mprj_dat_o_core[20] , \mprj_dat_o_core[19] , \mprj_dat_o_core[18] , \mprj_dat_o_core[17] , \mprj_dat_o_core[16] , \mprj_dat_o_core[15] , \mprj_dat_o_core[14] , \mprj_dat_o_core[13] , \mprj_dat_o_core[12] , \mprj_dat_o_core[11] , \mprj_dat_o_core[10] , \mprj_dat_o_core[9] , \mprj_dat_o_core[8] , \mprj_dat_o_core[7] , \mprj_dat_o_core[6] , \mprj_dat_o_core[5] , \mprj_dat_o_core[4] , \mprj_dat_o_core[3] , \mprj_dat_o_core[2] , \mprj_dat_o_core[1] , \mprj_dat_o_core[0]  }),
+    .mprj_sel_o({ \mprj_sel_o_core[3] , \mprj_sel_o_core[2] , \mprj_sel_o_core[1] , \mprj_sel_o_core[0]  }),
+    .mprj_stb_o(mprj_stb_o_core),
+    .mprj_wb_iena(mprj_iena_wb),
+    .mprj_we_o(mprj_we_o_core),
+    .por_l_in(por_l),
+    .por_l_out(por_l_buf),
+    .porb_h_in(por_l),
+    .porb_h_out(porb_h_out_nc),
+    .qspi_enabled(qspi_enabled),
+    .resetn_in(caravel_rstn_buf),
+    .resetn_out(resetn_passthru),
+    .rstb_l_in(rstb_l),
+    .rstb_l_out(rstb_l_buf),
+    .ser_rx(ser_rx),
+    .ser_tx(ser_tx),
+    .serial_clock_in(\gpio_clock_1_shifted[0] ),
+    .serial_clock_out(\gpio_clock_2_shifted[18] ),
+    .serial_data_2_in(mprj_io_loader_data_2),
+    .serial_data_2_out(\gpio_serial_link_2_shifted[18] ),
+    .serial_load_in(\gpio_load_1_shifted[0] ),
+    .serial_load_out(\gpio_load_2_shifted[18] ),
+    .serial_resetn_in(\gpio_resetn_1_shifted[0] ),
+    .serial_resetn_out(\gpio_resetn_2_shifted[18] ),
+    .spi_csb(spi_csb),
+    .spi_enabled(spi_enabled),
+    .spi_sck(spi_sck),
+    .spi_sdi(spi_sdi),
+    .spi_sdo(spi_sdo),
+    .spi_sdoenb(spi_sdoenb),
+    .trap(trap),
+    .uart_enabled(uart_enabled),
+    .user_irq_ena({ \user_irq_ena[2] , \user_irq_ena[1] , \user_irq_ena[0]  })
+  );
+  spare_logic_block \spare_logic[0]  (
+    .spare_xfq({ \spare_xfq_nc[1] , \spare_xfq_nc[0]  }),
+    .spare_xfqn({ \spare_xfqn_nc[1] , \spare_xfqn_nc[0]  }),
+    .spare_xi({ \spare_xi_nc[3] , \spare_xi_nc[2] , \spare_xi_nc[1] , \spare_xi_nc[0]  }),
+    .spare_xib(\spare_xib_nc[0] ),
+    .spare_xmx({ \spare_xmx_nc[1] , \spare_xmx_nc[0]  }),
+    .spare_xna({ \spare_xna_nc[1] , \spare_xna_nc[0]  }),
+    .spare_xno({ \spare_xno_nc[1] , \spare_xno_nc[0]  }),
+    .spare_xz({ \spare_xz_nc[26] , \spare_xz_nc[25] , \spare_xz_nc[24] , \spare_xz_nc[23] , \spare_xz_nc[22] , \spare_xz_nc[21] , \spare_xz_nc[20] , \spare_xz_nc[19] , \spare_xz_nc[18] , \spare_xz_nc[17] , \spare_xz_nc[16] , \spare_xz_nc[15] , \spare_xz_nc[14] , \spare_xz_nc[13] , \spare_xz_nc[12] , \spare_xz_nc[11] , \spare_xz_nc[10] , \spare_xz_nc[9] , \spare_xz_nc[8] , \spare_xz_nc[7] , \spare_xz_nc[6] , \spare_xz_nc[5] , \spare_xz_nc[4] , \spare_xz_nc[3] , \spare_xz_nc[2] , \spare_xz_nc[1] , \spare_xz_nc[0]  }),
+    .vccd(vccd_core),
+    .vssd(vssd_core)
+  );
+  spare_logic_block \spare_logic[1]  (
+    .spare_xfq({ \spare_xfq_nc[3] , \spare_xfq_nc[2]  }),
+    .spare_xfqn({ \spare_xfqn_nc[3] , \spare_xfqn_nc[2]  }),
+    .spare_xi({ \spare_xi_nc[7] , \spare_xi_nc[6] , \spare_xi_nc[5] , \spare_xi_nc[4]  }),
+    .spare_xib(\spare_xib_nc[1] ),
+    .spare_xmx({ \spare_xmx_nc[3] , \spare_xmx_nc[2]  }),
+    .spare_xna({ \spare_xna_nc[3] , \spare_xna_nc[2]  }),
+    .spare_xno({ \spare_xno_nc[3] , \spare_xno_nc[2]  }),
+    .spare_xz({ \spare_xz_nc[53] , \spare_xz_nc[52] , \spare_xz_nc[51] , \spare_xz_nc[50] , \spare_xz_nc[49] , \spare_xz_nc[48] , \spare_xz_nc[47] , \spare_xz_nc[46] , \spare_xz_nc[45] , \spare_xz_nc[44] , \spare_xz_nc[43] , \spare_xz_nc[42] , \spare_xz_nc[41] , \spare_xz_nc[40] , \spare_xz_nc[39] , \spare_xz_nc[38] , \spare_xz_nc[37] , \spare_xz_nc[36] , \spare_xz_nc[35] , \spare_xz_nc[34] , \spare_xz_nc[33] , \spare_xz_nc[32] , \spare_xz_nc[31] , \spare_xz_nc[30] , \spare_xz_nc[29] , \spare_xz_nc[28] , \spare_xz_nc[27]  }),
+    .vccd(vccd_core),
+    .vssd(vssd_core)
+  );
+  spare_logic_block \spare_logic[2]  (
+    .spare_xfq({ \spare_xfq_nc[5] , \spare_xfq_nc[4]  }),
+    .spare_xfqn({ \spare_xfqn_nc[5] , \spare_xfqn_nc[4]  }),
+    .spare_xi({ \spare_xi_nc[11] , \spare_xi_nc[10] , \spare_xi_nc[9] , \spare_xi_nc[8]  }),
+    .spare_xib(\spare_xib_nc[2] ),
+    .spare_xmx({ \spare_xmx_nc[5] , \spare_xmx_nc[4]  }),
+    .spare_xna({ \spare_xna_nc[5] , \spare_xna_nc[4]  }),
+    .spare_xno({ \spare_xno_nc[5] , \spare_xno_nc[4]  }),
+    .spare_xz({ \spare_xz_nc[80] , \spare_xz_nc[79] , \spare_xz_nc[78] , \spare_xz_nc[77] , \spare_xz_nc[76] , \spare_xz_nc[75] , \spare_xz_nc[74] , \spare_xz_nc[73] , \spare_xz_nc[72] , \spare_xz_nc[71] , \spare_xz_nc[70] , \spare_xz_nc[69] , \spare_xz_nc[68] , \spare_xz_nc[67] , \spare_xz_nc[66] , \spare_xz_nc[65] , \spare_xz_nc[64] , \spare_xz_nc[63] , \spare_xz_nc[62] , \spare_xz_nc[61] , \spare_xz_nc[60] , \spare_xz_nc[59] , \spare_xz_nc[58] , \spare_xz_nc[57] , \spare_xz_nc[56] , \spare_xz_nc[55] , \spare_xz_nc[54]  }),
+    .vccd(vccd_core),
+    .vssd(vssd_core)
+  );
+  spare_logic_block \spare_logic[3]  (
+    .spare_xfq({ \spare_xfq_nc[7] , \spare_xfq_nc[6]  }),
+    .spare_xfqn({ \spare_xfqn_nc[7] , \spare_xfqn_nc[6]  }),
+    .spare_xi({ \spare_xi_nc[15] , \spare_xi_nc[14] , \spare_xi_nc[13] , \spare_xi_nc[12]  }),
+    .spare_xib(\spare_xib_nc[3] ),
+    .spare_xmx({ \spare_xmx_nc[7] , \spare_xmx_nc[6]  }),
+    .spare_xna({ \spare_xna_nc[7] , \spare_xna_nc[6]  }),
+    .spare_xno({ \spare_xno_nc[7] , \spare_xno_nc[6]  }),
+    .spare_xz({ \spare_xz_nc[107] , \spare_xz_nc[106] , \spare_xz_nc[105] , \spare_xz_nc[104] , \spare_xz_nc[103] , \spare_xz_nc[102] , \spare_xz_nc[101] , \spare_xz_nc[100] , \spare_xz_nc[99] , \spare_xz_nc[98] , \spare_xz_nc[97] , \spare_xz_nc[96] , \spare_xz_nc[95] , \spare_xz_nc[94] , \spare_xz_nc[93] , \spare_xz_nc[92] , \spare_xz_nc[91] , \spare_xz_nc[90] , \spare_xz_nc[89] , \spare_xz_nc[88] , \spare_xz_nc[87] , \spare_xz_nc[86] , \spare_xz_nc[85] , \spare_xz_nc[84] , \spare_xz_nc[83] , \spare_xz_nc[82] , \spare_xz_nc[81]  }),
+    .vccd(vccd_core),
+    .vssd(vssd_core)
+  );
+  user_id_programming user_id_value (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .mask_rev({ \mask_rev[31] , \mask_rev[30] , \mask_rev[29] , \mask_rev[28] , \mask_rev[27] , \mask_rev[26] , \mask_rev[25] , \mask_rev[24] , \mask_rev[23] , \mask_rev[22] , \mask_rev[21] , \mask_rev[20] , \mask_rev[19] , \mask_rev[18] , \mask_rev[17] , \mask_rev[16] , \mask_rev[15] , \mask_rev[14] , \mask_rev[13] , \mask_rev[12] , \mask_rev[11] , \mask_rev[10] , \mask_rev[9] , \mask_rev[8] , \mask_rev[7] , \mask_rev[6] , \mask_rev[5] , \mask_rev[4] , \mask_rev[3] , \mask_rev[2] , \mask_rev[1] , \mask_rev[0]  })
+  );
+  assign \gpio_serial_link_1_shifted[18]  = \gpio_serial_link_1[17] ;
+  assign \gpio_serial_link_1_shifted[17]  = \gpio_serial_link_1[16] ;
+  assign \gpio_serial_link_1_shifted[16]  = \gpio_serial_link_1[15] ;
+  assign \gpio_serial_link_1_shifted[15]  = \gpio_serial_link_1[14] ;
+  assign \gpio_serial_link_1_shifted[14]  = \gpio_serial_link_1[13] ;
+  assign \gpio_serial_link_1_shifted[13]  = \gpio_serial_link_1[12] ;
+  assign \gpio_serial_link_1_shifted[12]  = \gpio_serial_link_1[11] ;
+  assign \gpio_serial_link_1_shifted[11]  = \gpio_serial_link_1[10] ;
+  assign \gpio_serial_link_1_shifted[10]  = \gpio_serial_link_1[9] ;
+  assign \gpio_serial_link_1_shifted[9]  = \gpio_serial_link_1[8] ;
+  assign \gpio_serial_link_1_shifted[8]  = \gpio_serial_link_1[7] ;
+  assign \gpio_serial_link_1_shifted[7]  = \gpio_serial_link_1[6] ;
+  assign \gpio_serial_link_1_shifted[6]  = \gpio_serial_link_1[5] ;
+  assign \gpio_serial_link_1_shifted[5]  = \gpio_serial_link_1[4] ;
+  assign \gpio_serial_link_1_shifted[4]  = \gpio_serial_link_1[3] ;
+  assign \gpio_serial_link_1_shifted[3]  = \gpio_serial_link_1[2] ;
+  assign \gpio_serial_link_1_shifted[2]  = \gpio_serial_link_1[1] ;
+  assign \gpio_serial_link_1_shifted[1]  = \gpio_serial_link_1[0] ;
+  assign \gpio_load_2_shifted[17]  = \gpio_load_2[18] ;
+  assign \gpio_load_2_shifted[16]  = \gpio_load_2[17] ;
+  assign \gpio_load_2_shifted[15]  = \gpio_load_2[16] ;
+  assign \gpio_load_2_shifted[14]  = \gpio_load_2[15] ;
+  assign \gpio_load_2_shifted[13]  = \gpio_load_2[14] ;
+  assign \gpio_load_2_shifted[12]  = \gpio_load_2[13] ;
+  assign \gpio_load_2_shifted[11]  = \gpio_load_2[12] ;
+  assign \gpio_load_2_shifted[10]  = \gpio_load_2[11] ;
+  assign \gpio_load_2_shifted[9]  = \gpio_load_2[10] ;
+  assign \gpio_load_2_shifted[8]  = \gpio_load_2[9] ;
+  assign \gpio_load_2_shifted[7]  = \gpio_load_2[8] ;
+  assign \gpio_load_2_shifted[6]  = \gpio_load_2[7] ;
+  assign \gpio_load_2_shifted[5]  = \gpio_load_2[6] ;
+  assign \gpio_load_2_shifted[4]  = \gpio_load_2[5] ;
+  assign \gpio_load_2_shifted[3]  = \gpio_load_2[4] ;
+  assign \gpio_load_2_shifted[2]  = \gpio_load_2[3] ;
+  assign \gpio_load_2_shifted[1]  = \gpio_load_2[2] ;
+  assign \gpio_load_2_shifted[0]  = \gpio_load_2[1] ;
+  assign \gpio_clock_1_shifted[18]  = \gpio_clock_1[17] ;
+  assign \gpio_clock_1_shifted[17]  = \gpio_clock_1[16] ;
+  assign \gpio_clock_1_shifted[16]  = \gpio_clock_1[15] ;
+  assign \gpio_clock_1_shifted[15]  = \gpio_clock_1[14] ;
+  assign \gpio_clock_1_shifted[14]  = \gpio_clock_1[13] ;
+  assign \gpio_clock_1_shifted[13]  = \gpio_clock_1[12] ;
+  assign \gpio_clock_1_shifted[12]  = \gpio_clock_1[11] ;
+  assign \gpio_clock_1_shifted[11]  = \gpio_clock_1[10] ;
+  assign \gpio_clock_1_shifted[10]  = \gpio_clock_1[9] ;
+  assign \gpio_clock_1_shifted[9]  = \gpio_clock_1[8] ;
+  assign \gpio_clock_1_shifted[8]  = \gpio_clock_1[7] ;
+  assign \gpio_clock_1_shifted[7]  = \gpio_clock_1[6] ;
+  assign \gpio_clock_1_shifted[6]  = \gpio_clock_1[5] ;
+  assign \gpio_clock_1_shifted[5]  = \gpio_clock_1[4] ;
+  assign \gpio_clock_1_shifted[4]  = \gpio_clock_1[3] ;
+  assign \gpio_clock_1_shifted[3]  = \gpio_clock_1[2] ;
+  assign \gpio_clock_1_shifted[2]  = \gpio_clock_1[1] ;
+  assign \gpio_clock_1_shifted[1]  = \gpio_clock_1[0] ;
+  assign \gpio_resetn_1_shifted[18]  = \gpio_resetn_1[17] ;
+  assign \gpio_resetn_1_shifted[17]  = \gpio_resetn_1[16] ;
+  assign \gpio_resetn_1_shifted[16]  = \gpio_resetn_1[15] ;
+  assign \gpio_resetn_1_shifted[15]  = \gpio_resetn_1[14] ;
+  assign \gpio_resetn_1_shifted[14]  = \gpio_resetn_1[13] ;
+  assign \gpio_resetn_1_shifted[13]  = \gpio_resetn_1[12] ;
+  assign \gpio_resetn_1_shifted[12]  = \gpio_resetn_1[11] ;
+  assign \gpio_resetn_1_shifted[11]  = \gpio_resetn_1[10] ;
+  assign \gpio_resetn_1_shifted[10]  = \gpio_resetn_1[9] ;
+  assign \gpio_resetn_1_shifted[9]  = \gpio_resetn_1[8] ;
+  assign \gpio_resetn_1_shifted[8]  = \gpio_resetn_1[7] ;
+  assign \gpio_resetn_1_shifted[7]  = \gpio_resetn_1[6] ;
+  assign \gpio_resetn_1_shifted[6]  = \gpio_resetn_1[5] ;
+  assign \gpio_resetn_1_shifted[5]  = \gpio_resetn_1[4] ;
+  assign \gpio_resetn_1_shifted[4]  = \gpio_resetn_1[3] ;
+  assign \gpio_resetn_1_shifted[3]  = \gpio_resetn_1[2] ;
+  assign \gpio_resetn_1_shifted[2]  = \gpio_resetn_1[1] ;
+  assign \gpio_resetn_1_shifted[1]  = \gpio_resetn_1[0] ;
+  assign \gpio_clock_2_shifted[17]  = \gpio_clock_2[18] ;
+  assign \gpio_clock_2_shifted[16]  = \gpio_clock_2[17] ;
+  assign \gpio_clock_2_shifted[15]  = \gpio_clock_2[16] ;
+  assign \gpio_clock_2_shifted[14]  = \gpio_clock_2[15] ;
+  assign \gpio_clock_2_shifted[13]  = \gpio_clock_2[14] ;
+  assign \gpio_clock_2_shifted[12]  = \gpio_clock_2[13] ;
+  assign \gpio_clock_2_shifted[11]  = \gpio_clock_2[12] ;
+  assign \gpio_clock_2_shifted[10]  = \gpio_clock_2[11] ;
+  assign \gpio_clock_2_shifted[9]  = \gpio_clock_2[10] ;
+  assign \gpio_clock_2_shifted[8]  = \gpio_clock_2[9] ;
+  assign \gpio_clock_2_shifted[7]  = \gpio_clock_2[8] ;
+  assign \gpio_clock_2_shifted[6]  = \gpio_clock_2[7] ;
+  assign \gpio_clock_2_shifted[5]  = \gpio_clock_2[6] ;
+  assign \gpio_clock_2_shifted[4]  = \gpio_clock_2[5] ;
+  assign \gpio_clock_2_shifted[3]  = \gpio_clock_2[4] ;
+  assign \gpio_clock_2_shifted[2]  = \gpio_clock_2[3] ;
+  assign \gpio_clock_2_shifted[1]  = \gpio_clock_2[2] ;
+  assign \gpio_clock_2_shifted[0]  = \gpio_clock_2[1] ;
+  assign \gpio_load_1_shifted[18]  = \gpio_load_1[17] ;
+  assign \gpio_load_1_shifted[17]  = \gpio_load_1[16] ;
+  assign \gpio_load_1_shifted[16]  = \gpio_load_1[15] ;
+  assign \gpio_load_1_shifted[15]  = \gpio_load_1[14] ;
+  assign \gpio_load_1_shifted[14]  = \gpio_load_1[13] ;
+  assign \gpio_load_1_shifted[13]  = \gpio_load_1[12] ;
+  assign \gpio_load_1_shifted[12]  = \gpio_load_1[11] ;
+  assign \gpio_load_1_shifted[11]  = \gpio_load_1[10] ;
+  assign \gpio_load_1_shifted[10]  = \gpio_load_1[9] ;
+  assign \gpio_load_1_shifted[9]  = \gpio_load_1[8] ;
+  assign \gpio_load_1_shifted[8]  = \gpio_load_1[7] ;
+  assign \gpio_load_1_shifted[7]  = \gpio_load_1[6] ;
+  assign \gpio_load_1_shifted[6]  = \gpio_load_1[5] ;
+  assign \gpio_load_1_shifted[5]  = \gpio_load_1[4] ;
+  assign \gpio_load_1_shifted[4]  = \gpio_load_1[3] ;
+  assign \gpio_load_1_shifted[3]  = \gpio_load_1[2] ;
+  assign \gpio_load_1_shifted[2]  = \gpio_load_1[1] ;
+  assign \gpio_load_1_shifted[1]  = \gpio_load_1[0] ;
+  assign \gpio_serial_link_2_shifted[17]  = \gpio_serial_link_2[18] ;
+  assign \gpio_serial_link_2_shifted[16]  = \gpio_serial_link_2[17] ;
+  assign \gpio_serial_link_2_shifted[15]  = \gpio_serial_link_2[16] ;
+  assign \gpio_serial_link_2_shifted[14]  = \gpio_serial_link_2[15] ;
+  assign \gpio_serial_link_2_shifted[13]  = \gpio_serial_link_2[14] ;
+  assign \gpio_serial_link_2_shifted[12]  = \gpio_serial_link_2[13] ;
+  assign \gpio_serial_link_2_shifted[11]  = \gpio_serial_link_2[12] ;
+  assign \gpio_serial_link_2_shifted[10]  = \gpio_serial_link_2[11] ;
+  assign \gpio_serial_link_2_shifted[9]  = \gpio_serial_link_2[10] ;
+  assign \gpio_serial_link_2_shifted[8]  = \gpio_serial_link_2[9] ;
+  assign \gpio_serial_link_2_shifted[7]  = \gpio_serial_link_2[8] ;
+  assign \gpio_serial_link_2_shifted[6]  = \gpio_serial_link_2[7] ;
+  assign \gpio_serial_link_2_shifted[5]  = \gpio_serial_link_2[6] ;
+  assign \gpio_serial_link_2_shifted[4]  = \gpio_serial_link_2[5] ;
+  assign \gpio_serial_link_2_shifted[3]  = \gpio_serial_link_2[4] ;
+  assign \gpio_serial_link_2_shifted[2]  = \gpio_serial_link_2[3] ;
+  assign \gpio_serial_link_2_shifted[1]  = \gpio_serial_link_2[2] ;
+  assign \gpio_serial_link_2_shifted[0]  = \gpio_serial_link_2[1] ;
+  assign \gpio_resetn_2_shifted[17]  = \gpio_resetn_2[18] ;
+  assign \gpio_resetn_2_shifted[16]  = \gpio_resetn_2[17] ;
+  assign \gpio_resetn_2_shifted[15]  = \gpio_resetn_2[16] ;
+  assign \gpio_resetn_2_shifted[14]  = \gpio_resetn_2[15] ;
+  assign \gpio_resetn_2_shifted[13]  = \gpio_resetn_2[14] ;
+  assign \gpio_resetn_2_shifted[12]  = \gpio_resetn_2[13] ;
+  assign \gpio_resetn_2_shifted[11]  = \gpio_resetn_2[12] ;
+  assign \gpio_resetn_2_shifted[10]  = \gpio_resetn_2[11] ;
+  assign \gpio_resetn_2_shifted[9]  = \gpio_resetn_2[10] ;
+  assign \gpio_resetn_2_shifted[8]  = \gpio_resetn_2[9] ;
+  assign \gpio_resetn_2_shifted[7]  = \gpio_resetn_2[8] ;
+  assign \gpio_resetn_2_shifted[6]  = \gpio_resetn_2[7] ;
+  assign \gpio_resetn_2_shifted[5]  = \gpio_resetn_2[6] ;
+  assign \gpio_resetn_2_shifted[4]  = \gpio_resetn_2[5] ;
+  assign \gpio_resetn_2_shifted[3]  = \gpio_resetn_2[4] ;
+  assign \gpio_resetn_2_shifted[2]  = \gpio_resetn_2[3] ;
+  assign \gpio_resetn_2_shifted[1]  = \gpio_resetn_2[2] ;
+  assign \gpio_resetn_2_shifted[0]  = \gpio_resetn_2[1] ;
+  assign \mgmt_io_in_hk[6]  = \mgmt_io_in[6] ;
+  assign \mgmt_io_in_hk[5]  = \mgmt_io_in[5] ;
+  assign \mgmt_io_in_hk[4]  = \mgmt_io_in[4] ;
+  assign \mgmt_io_in_hk[3]  = \mgmt_io_in[3] ;
+  assign \mgmt_io_in_hk[2]  = \mgmt_io_in[2] ;
+  assign \mgmt_io_in_hk[1]  = \mgmt_io_in[1] ;
+  assign \mgmt_io_in_hk[0]  = \mgmt_io_in[0] ;
+  assign \mgmt_io_out_hk[6]  = \mgmt_io_out[6] ;
+  assign \mgmt_io_out_hk[5]  = \mgmt_io_out[5] ;
+  assign \mgmt_io_out_hk[4]  = \mgmt_io_out[4] ;
+  assign \mgmt_io_out_hk[3]  = \mgmt_io_out[3] ;
+  assign \mgmt_io_out_hk[2]  = \mgmt_io_out[2] ;
+  assign \mgmt_io_out_hk[1]  = \mgmt_io_out[1] ;
+  assign \mgmt_io_out_hk[0]  = \mgmt_io_out[0] ;
+  assign \mgmt_io_oeb_hk[34]  = \mgmt_io_oeb[34] ;
+  assign \mgmt_io_oeb_hk[33]  = \mgmt_io_oeb[33] ;
+  assign \mgmt_io_oeb_hk[32]  = \mgmt_io_oeb[32] ;
+  assign \mgmt_io_oeb_hk[31]  = \mgmt_io_oeb[31] ;
+  assign \mgmt_io_oeb_hk[30]  = \mgmt_io_oeb[30] ;
+  assign \mgmt_io_oeb_hk[29]  = \mgmt_io_oeb[29] ;
+  assign \mgmt_io_oeb_hk[28]  = \mgmt_io_oeb[28] ;
+  assign \mgmt_io_oeb_hk[27]  = \mgmt_io_oeb[27] ;
+  assign \mgmt_io_oeb_hk[26]  = \mgmt_io_oeb[26] ;
+  assign \mgmt_io_oeb_hk[25]  = \mgmt_io_oeb[25] ;
+  assign \mgmt_io_oeb_hk[24]  = \mgmt_io_oeb[24] ;
+  assign \mgmt_io_oeb_hk[23]  = \mgmt_io_oeb[23] ;
+  assign \mgmt_io_oeb_hk[22]  = \mgmt_io_oeb[22] ;
+  assign \mgmt_io_oeb_hk[21]  = \mgmt_io_oeb[21] ;
+  assign \mgmt_io_oeb_hk[20]  = \mgmt_io_oeb[20] ;
+  assign \mgmt_io_oeb_hk[19]  = \mgmt_io_oeb[19] ;
+  assign \mgmt_io_oeb_hk[18]  = \mgmt_io_oeb[18] ;
+  assign \mgmt_io_oeb_hk[17]  = \mgmt_io_oeb[17] ;
+  assign \mgmt_io_oeb_hk[16]  = \mgmt_io_oeb[16] ;
+  assign \mgmt_io_oeb_hk[15]  = \mgmt_io_oeb[15] ;
+  assign \mgmt_io_oeb_hk[14]  = \mgmt_io_oeb[14] ;
+  assign \mgmt_io_oeb_hk[13]  = \mgmt_io_oeb[13] ;
+  assign \mgmt_io_oeb_hk[12]  = \mgmt_io_oeb[12] ;
+  assign \mgmt_io_oeb_hk[11]  = \mgmt_io_oeb[11] ;
+  assign \mgmt_io_oeb_hk[10]  = \mgmt_io_oeb[10] ;
+  assign \mgmt_io_oeb_hk[9]  = \mgmt_io_oeb[9] ;
+  assign \mgmt_io_oeb_hk[8]  = \mgmt_io_oeb[8] ;
+  assign \mgmt_io_oeb_hk[7]  = \mgmt_io_oeb[7] ;
+  assign \mgmt_io_oeb_hk[6]  = \mgmt_io_oeb[6] ;
+  assign \mgmt_io_oeb_hk[5]  = \mgmt_io_oeb[5] ;
+  assign \mgmt_io_oeb_hk[4]  = \mgmt_io_oeb[4] ;
+  assign \mgmt_io_oeb_hk[3]  = \mgmt_io_oeb[3] ;
+  assign \mgmt_io_oeb_hk[2]  = \mgmt_io_oeb[2] ;
+  assign \mgmt_io_oeb_hk[1]  = \mgmt_io_oeb[1] ;
+  assign \mgmt_io_oeb_hk[0]  = \mgmt_io_oeb[0] ;
+  assign mprj_io_loader_data_2_buf = \gpio_serial_link_2_shifted[18] ;
+  assign mprj_io_loader_resetn_buf = \gpio_resetn_2_shifted[18] ;
+  assign mprj_io_loader_strobe_buf = \gpio_load_2_shifted[18] ;
+  assign mprj_io_loader_clock_buf = \gpio_clock_2_shifted[18] ;
+  assign mprj_io_loader_data_1 = \gpio_serial_link_1_shifted[0] ;
+  assign mprj_io_loader_strobe = \gpio_load_1_shifted[0] ;
+  assign mprj_io_loader_clock = \gpio_clock_1_shifted[0] ;
+  assign mprj_io_loader_resetn = \gpio_resetn_1_shifted[0] ;
+endmodule
diff --git a/tapeout/outputs/verilog/gl/gpio_defaults_block_0403.v b/tapeout/outputs/verilog/gl/gpio_defaults_block_0403.v
new file mode 100644
index 0000000..33fbfde
--- /dev/null
+++ b/tapeout/outputs/verilog/gl/gpio_defaults_block_0403.v
@@ -0,0 +1,260 @@
+module gpio_defaults_block_0403 (VGND,
+    VPWR,
+    gpio_defaults);
+ input VGND;
+ input VPWR;
+ output [12:0] gpio_defaults;
+
+ wire \gpio_defaults_low[0] ;
+ wire \gpio_defaults_high[10] ;
+ wire \gpio_defaults_low[11] ;
+ wire \gpio_defaults_low[12] ;
+ wire \gpio_defaults_high[1] ;
+ wire \gpio_defaults_low[2] ;
+ wire \gpio_defaults_low[3] ;
+ wire \gpio_defaults_low[4] ;
+ wire \gpio_defaults_low[5] ;
+ wire \gpio_defaults_low[6] ;
+ wire \gpio_defaults_low[7] ;
+ wire \gpio_defaults_low[8] ;
+ wire \gpio_defaults_low[9] ;
+ wire \gpio_defaults_high[0] ;
+ wire \gpio_defaults_high[11] ;
+ wire \gpio_defaults_high[12] ;
+ wire \gpio_defaults_high[2] ;
+ wire \gpio_defaults_high[3] ;
+ wire \gpio_defaults_high[4] ;
+ wire \gpio_defaults_high[5] ;
+ wire \gpio_defaults_high[6] ;
+ wire \gpio_defaults_high[7] ;
+ wire \gpio_defaults_high[8] ;
+ wire \gpio_defaults_high[9] ;
+ wire \gpio_defaults_low[10] ;
+ wire \gpio_defaults_low[1] ;
+
+ sky130_fd_sc_hd__fill_1 FILLER_0_29 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_0_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_33 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_38 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_43 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_48 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_55 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_60 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_9 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_15 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_27 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_39 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_1_51 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_55 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_1_57 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_61 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_15 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_27 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_29 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_41 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_2_53 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_2_57 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_61 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_10 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_6 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_7 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_8 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_9 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[0]  (.HI(\gpio_defaults_high[0] ),
+    .LO(\gpio_defaults_low[0] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[10]  (.HI(\gpio_defaults_high[10] ),
+    .LO(\gpio_defaults_low[10] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[11]  (.HI(\gpio_defaults_high[11] ),
+    .LO(\gpio_defaults_low[11] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[12]  (.HI(\gpio_defaults_high[12] ),
+    .LO(\gpio_defaults_low[12] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[1]  (.HI(\gpio_defaults_high[1] ),
+    .LO(\gpio_defaults_low[1] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[2]  (.HI(\gpio_defaults_high[2] ),
+    .LO(\gpio_defaults_low[2] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[3]  (.HI(\gpio_defaults_high[3] ),
+    .LO(\gpio_defaults_low[3] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[4]  (.HI(\gpio_defaults_high[4] ),
+    .LO(\gpio_defaults_low[4] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[5]  (.HI(\gpio_defaults_high[5] ),
+    .LO(\gpio_defaults_low[5] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[6]  (.HI(\gpio_defaults_high[6] ),
+    .LO(\gpio_defaults_low[6] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[7]  (.HI(\gpio_defaults_high[7] ),
+    .LO(\gpio_defaults_low[7] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[8]  (.HI(\gpio_defaults_high[8] ),
+    .LO(\gpio_defaults_low[8] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[9]  (.HI(\gpio_defaults_high[9] ),
+    .LO(\gpio_defaults_low[9] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ assign gpio_defaults[0] = \gpio_defaults_high[0] ;
+ assign gpio_defaults[1] = \gpio_defaults_high[1] ;
+ assign gpio_defaults[2] = \gpio_defaults_low[2] ;
+ assign gpio_defaults[3] = \gpio_defaults_low[3] ;
+ assign gpio_defaults[4] = \gpio_defaults_low[4] ;
+ assign gpio_defaults[5] = \gpio_defaults_low[5] ;
+ assign gpio_defaults[6] = \gpio_defaults_low[6] ;
+ assign gpio_defaults[7] = \gpio_defaults_low[7] ;
+ assign gpio_defaults[8] = \gpio_defaults_low[8] ;
+ assign gpio_defaults[9] = \gpio_defaults_low[9] ;
+ assign gpio_defaults[10] = \gpio_defaults_high[10] ;
+ assign gpio_defaults[11] = \gpio_defaults_low[11] ;
+ assign gpio_defaults[12] = \gpio_defaults_low[12] ;
+endmodule
diff --git a/tapeout/outputs/verilog/gl/gpio_defaults_block_0801.v b/tapeout/outputs/verilog/gl/gpio_defaults_block_0801.v
new file mode 100644
index 0000000..379ba1c
--- /dev/null
+++ b/tapeout/outputs/verilog/gl/gpio_defaults_block_0801.v
@@ -0,0 +1,260 @@
+module gpio_defaults_block_0801 (VGND,
+    VPWR,
+    gpio_defaults);
+ input VGND;
+ input VPWR;
+ output [12:0] gpio_defaults;
+
+ wire \gpio_defaults_low[0] ;
+ wire \gpio_defaults_high[10] ;
+ wire \gpio_defaults_low[11] ;
+ wire \gpio_defaults_low[12] ;
+ wire \gpio_defaults_high[1] ;
+ wire \gpio_defaults_low[2] ;
+ wire \gpio_defaults_low[3] ;
+ wire \gpio_defaults_low[4] ;
+ wire \gpio_defaults_low[5] ;
+ wire \gpio_defaults_low[6] ;
+ wire \gpio_defaults_low[7] ;
+ wire \gpio_defaults_low[8] ;
+ wire \gpio_defaults_low[9] ;
+ wire \gpio_defaults_high[0] ;
+ wire \gpio_defaults_high[11] ;
+ wire \gpio_defaults_high[12] ;
+ wire \gpio_defaults_high[2] ;
+ wire \gpio_defaults_high[3] ;
+ wire \gpio_defaults_high[4] ;
+ wire \gpio_defaults_high[5] ;
+ wire \gpio_defaults_high[6] ;
+ wire \gpio_defaults_high[7] ;
+ wire \gpio_defaults_high[8] ;
+ wire \gpio_defaults_high[9] ;
+ wire \gpio_defaults_low[10] ;
+ wire \gpio_defaults_low[1] ;
+
+ sky130_fd_sc_hd__fill_1 FILLER_0_29 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_0_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_33 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_38 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_43 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_48 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_55 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_60 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_9 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_15 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_27 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_39 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_1_51 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_55 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_1_57 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_61 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_15 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_27 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_29 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_41 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_2_53 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_2_57 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_61 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_10 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_6 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_7 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_8 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_9 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[0]  (.HI(\gpio_defaults_high[0] ),
+    .LO(\gpio_defaults_low[0] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[10]  (.HI(\gpio_defaults_high[10] ),
+    .LO(\gpio_defaults_low[10] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[11]  (.HI(\gpio_defaults_high[11] ),
+    .LO(\gpio_defaults_low[11] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[12]  (.HI(\gpio_defaults_high[12] ),
+    .LO(\gpio_defaults_low[12] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[1]  (.HI(\gpio_defaults_high[1] ),
+    .LO(\gpio_defaults_low[1] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[2]  (.HI(\gpio_defaults_high[2] ),
+    .LO(\gpio_defaults_low[2] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[3]  (.HI(\gpio_defaults_high[3] ),
+    .LO(\gpio_defaults_low[3] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[4]  (.HI(\gpio_defaults_high[4] ),
+    .LO(\gpio_defaults_low[4] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[5]  (.HI(\gpio_defaults_high[5] ),
+    .LO(\gpio_defaults_low[5] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[6]  (.HI(\gpio_defaults_high[6] ),
+    .LO(\gpio_defaults_low[6] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[7]  (.HI(\gpio_defaults_high[7] ),
+    .LO(\gpio_defaults_low[7] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[8]  (.HI(\gpio_defaults_high[8] ),
+    .LO(\gpio_defaults_low[8] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[9]  (.HI(\gpio_defaults_high[9] ),
+    .LO(\gpio_defaults_low[9] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ assign gpio_defaults[0] = \gpio_defaults_high[0] ;
+ assign gpio_defaults[1] = \gpio_defaults_low[1] ;
+ assign gpio_defaults[2] = \gpio_defaults_low[2] ;
+ assign gpio_defaults[3] = \gpio_defaults_low[3] ;
+ assign gpio_defaults[4] = \gpio_defaults_low[4] ;
+ assign gpio_defaults[5] = \gpio_defaults_low[5] ;
+ assign gpio_defaults[6] = \gpio_defaults_low[6] ;
+ assign gpio_defaults[7] = \gpio_defaults_low[7] ;
+ assign gpio_defaults[8] = \gpio_defaults_low[8] ;
+ assign gpio_defaults[9] = \gpio_defaults_low[9] ;
+ assign gpio_defaults[10] = \gpio_defaults_low[10] ;
+ assign gpio_defaults[11] = \gpio_defaults_high[11] ;
+ assign gpio_defaults[12] = \gpio_defaults_low[12] ;
+endmodule
diff --git a/tapeout/outputs/verilog/gl/gpio_defaults_block_1800.v b/tapeout/outputs/verilog/gl/gpio_defaults_block_1800.v
new file mode 100644
index 0000000..bdb0ae2
--- /dev/null
+++ b/tapeout/outputs/verilog/gl/gpio_defaults_block_1800.v
@@ -0,0 +1,260 @@
+module gpio_defaults_block_1800 (VGND,
+    VPWR,
+    gpio_defaults);
+ input VGND;
+ input VPWR;
+ output [12:0] gpio_defaults;
+
+ wire \gpio_defaults_low[0] ;
+ wire \gpio_defaults_high[10] ;
+ wire \gpio_defaults_low[11] ;
+ wire \gpio_defaults_low[12] ;
+ wire \gpio_defaults_high[1] ;
+ wire \gpio_defaults_low[2] ;
+ wire \gpio_defaults_low[3] ;
+ wire \gpio_defaults_low[4] ;
+ wire \gpio_defaults_low[5] ;
+ wire \gpio_defaults_low[6] ;
+ wire \gpio_defaults_low[7] ;
+ wire \gpio_defaults_low[8] ;
+ wire \gpio_defaults_low[9] ;
+ wire \gpio_defaults_high[0] ;
+ wire \gpio_defaults_high[11] ;
+ wire \gpio_defaults_high[12] ;
+ wire \gpio_defaults_high[2] ;
+ wire \gpio_defaults_high[3] ;
+ wire \gpio_defaults_high[4] ;
+ wire \gpio_defaults_high[5] ;
+ wire \gpio_defaults_high[6] ;
+ wire \gpio_defaults_high[7] ;
+ wire \gpio_defaults_high[8] ;
+ wire \gpio_defaults_high[9] ;
+ wire \gpio_defaults_low[10] ;
+ wire \gpio_defaults_low[1] ;
+
+ sky130_fd_sc_hd__fill_1 FILLER_0_29 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_0_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_33 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_38 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_43 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_48 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_55 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_60 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_9 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_15 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_27 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_39 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_1_51 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_55 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_1_57 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_61 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_15 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_27 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_29 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_41 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_2_53 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_2_57 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_61 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_10 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_6 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_7 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_8 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_9 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[0]  (.HI(\gpio_defaults_high[0] ),
+    .LO(\gpio_defaults_low[0] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[10]  (.HI(\gpio_defaults_high[10] ),
+    .LO(\gpio_defaults_low[10] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[11]  (.HI(\gpio_defaults_high[11] ),
+    .LO(\gpio_defaults_low[11] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[12]  (.HI(\gpio_defaults_high[12] ),
+    .LO(\gpio_defaults_low[12] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[1]  (.HI(\gpio_defaults_high[1] ),
+    .LO(\gpio_defaults_low[1] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[2]  (.HI(\gpio_defaults_high[2] ),
+    .LO(\gpio_defaults_low[2] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[3]  (.HI(\gpio_defaults_high[3] ),
+    .LO(\gpio_defaults_low[3] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[4]  (.HI(\gpio_defaults_high[4] ),
+    .LO(\gpio_defaults_low[4] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[5]  (.HI(\gpio_defaults_high[5] ),
+    .LO(\gpio_defaults_low[5] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[6]  (.HI(\gpio_defaults_high[6] ),
+    .LO(\gpio_defaults_low[6] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[7]  (.HI(\gpio_defaults_high[7] ),
+    .LO(\gpio_defaults_low[7] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[8]  (.HI(\gpio_defaults_high[8] ),
+    .LO(\gpio_defaults_low[8] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[9]  (.HI(\gpio_defaults_high[9] ),
+    .LO(\gpio_defaults_low[9] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ assign gpio_defaults[0] = \gpio_defaults_low[0] ;
+ assign gpio_defaults[1] = \gpio_defaults_low[1] ;
+ assign gpio_defaults[2] = \gpio_defaults_low[2] ;
+ assign gpio_defaults[3] = \gpio_defaults_low[3] ;
+ assign gpio_defaults[4] = \gpio_defaults_low[4] ;
+ assign gpio_defaults[5] = \gpio_defaults_low[5] ;
+ assign gpio_defaults[6] = \gpio_defaults_low[6] ;
+ assign gpio_defaults[7] = \gpio_defaults_low[7] ;
+ assign gpio_defaults[8] = \gpio_defaults_low[8] ;
+ assign gpio_defaults[9] = \gpio_defaults_low[9] ;
+ assign gpio_defaults[10] = \gpio_defaults_low[10] ;
+ assign gpio_defaults[11] = \gpio_defaults_high[11] ;
+ assign gpio_defaults[12] = \gpio_defaults_high[12] ;
+endmodule
diff --git a/tapeout/outputs/verilog/gl/gpio_defaults_block_1803.v b/tapeout/outputs/verilog/gl/gpio_defaults_block_1803.v
new file mode 100644
index 0000000..13ad29a
--- /dev/null
+++ b/tapeout/outputs/verilog/gl/gpio_defaults_block_1803.v
@@ -0,0 +1,260 @@
+module gpio_defaults_block_1803 (VGND,
+    VPWR,
+    gpio_defaults);
+ input VGND;
+ input VPWR;
+ output [12:0] gpio_defaults;
+
+ wire \gpio_defaults_low[0] ;
+ wire \gpio_defaults_high[10] ;
+ wire \gpio_defaults_low[11] ;
+ wire \gpio_defaults_low[12] ;
+ wire \gpio_defaults_high[1] ;
+ wire \gpio_defaults_low[2] ;
+ wire \gpio_defaults_low[3] ;
+ wire \gpio_defaults_low[4] ;
+ wire \gpio_defaults_low[5] ;
+ wire \gpio_defaults_low[6] ;
+ wire \gpio_defaults_low[7] ;
+ wire \gpio_defaults_low[8] ;
+ wire \gpio_defaults_low[9] ;
+ wire \gpio_defaults_high[0] ;
+ wire \gpio_defaults_high[11] ;
+ wire \gpio_defaults_high[12] ;
+ wire \gpio_defaults_high[2] ;
+ wire \gpio_defaults_high[3] ;
+ wire \gpio_defaults_high[4] ;
+ wire \gpio_defaults_high[5] ;
+ wire \gpio_defaults_high[6] ;
+ wire \gpio_defaults_high[7] ;
+ wire \gpio_defaults_high[8] ;
+ wire \gpio_defaults_high[9] ;
+ wire \gpio_defaults_low[10] ;
+ wire \gpio_defaults_low[1] ;
+
+ sky130_fd_sc_hd__fill_1 FILLER_0_29 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_0_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_33 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_38 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_43 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_48 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_55 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_60 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_9 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_15 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_27 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_39 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_1_51 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_55 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_1_57 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_61 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_15 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_27 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_29 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_41 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_2_53 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_2_57 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_61 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_10 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_6 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_7 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_8 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_9 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[0]  (.HI(\gpio_defaults_high[0] ),
+    .LO(\gpio_defaults_low[0] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[10]  (.HI(\gpio_defaults_high[10] ),
+    .LO(\gpio_defaults_low[10] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[11]  (.HI(\gpio_defaults_high[11] ),
+    .LO(\gpio_defaults_low[11] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[12]  (.HI(\gpio_defaults_high[12] ),
+    .LO(\gpio_defaults_low[12] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[1]  (.HI(\gpio_defaults_high[1] ),
+    .LO(\gpio_defaults_low[1] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[2]  (.HI(\gpio_defaults_high[2] ),
+    .LO(\gpio_defaults_low[2] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[3]  (.HI(\gpio_defaults_high[3] ),
+    .LO(\gpio_defaults_low[3] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[4]  (.HI(\gpio_defaults_high[4] ),
+    .LO(\gpio_defaults_low[4] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[5]  (.HI(\gpio_defaults_high[5] ),
+    .LO(\gpio_defaults_low[5] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[6]  (.HI(\gpio_defaults_high[6] ),
+    .LO(\gpio_defaults_low[6] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[7]  (.HI(\gpio_defaults_high[7] ),
+    .LO(\gpio_defaults_low[7] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[8]  (.HI(\gpio_defaults_high[8] ),
+    .LO(\gpio_defaults_low[8] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[9]  (.HI(\gpio_defaults_high[9] ),
+    .LO(\gpio_defaults_low[9] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ assign gpio_defaults[0] = \gpio_defaults_high[0] ;
+ assign gpio_defaults[1] = \gpio_defaults_high[1] ;
+ assign gpio_defaults[2] = \gpio_defaults_low[2] ;
+ assign gpio_defaults[3] = \gpio_defaults_low[3] ;
+ assign gpio_defaults[4] = \gpio_defaults_low[4] ;
+ assign gpio_defaults[5] = \gpio_defaults_low[5] ;
+ assign gpio_defaults[6] = \gpio_defaults_low[6] ;
+ assign gpio_defaults[7] = \gpio_defaults_low[7] ;
+ assign gpio_defaults[8] = \gpio_defaults_low[8] ;
+ assign gpio_defaults[9] = \gpio_defaults_low[9] ;
+ assign gpio_defaults[10] = \gpio_defaults_low[10] ;
+ assign gpio_defaults[11] = \gpio_defaults_high[11] ;
+ assign gpio_defaults[12] = \gpio_defaults_high[12] ;
+endmodule
diff --git a/tapeout/outputs/verilog/gl/user_id_programming.v b/tapeout/outputs/verilog/gl/user_id_programming.v
new file mode 100644
index 0000000..c0c2142
--- /dev/null
+++ b/tapeout/outputs/verilog/gl/user_id_programming.v
@@ -0,0 +1,786 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
+
+module user_id_programming(VPWR, VGND, mask_rev);
+  input VGND;
+  input VPWR;
+  output [31:0] mask_rev;
+  wire \user_proj_id_high[0] ;
+  wire \user_proj_id_high[10] ;
+  wire \user_proj_id_high[11] ;
+  wire \user_proj_id_low[12] ;
+  wire \user_proj_id_high[13] ;
+  wire \user_proj_id_high[14] ;
+  wire \user_proj_id_high[15] ;
+  wire \user_proj_id_low[16] ;
+  wire \user_proj_id_high[17] ;
+  wire \user_proj_id_high[18] ;
+  wire \user_proj_id_high[19] ;
+  wire \user_proj_id_high[1] ;
+  wire \user_proj_id_low[20] ;
+  wire \user_proj_id_high[21] ;
+  wire \user_proj_id_low[22] ;
+  wire \user_proj_id_low[23] ;
+  wire \user_proj_id_low[24] ;
+  wire \user_proj_id_low[25] ;
+  wire \user_proj_id_high[26] ;
+  wire \user_proj_id_high[27] ;
+  wire \user_proj_id_low[28] ;
+  wire \user_proj_id_high[29] ;
+  wire \user_proj_id_high[2] ;
+  wire \user_proj_id_low[30] ;
+  wire \user_proj_id_high[31] ;
+  wire \user_proj_id_high[3] ;
+  wire \user_proj_id_high[4] ;
+  wire \user_proj_id_high[5] ;
+  wire \user_proj_id_high[6] ;
+  wire \user_proj_id_high[7] ;
+  wire \user_proj_id_high[8] ;
+  wire \user_proj_id_high[9] ;
+  sky130_fd_sc_hd__decap_3 FILLER_0_15 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_8 FILLER_0_21 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__fill_2 FILLER_0_29 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__fill_1 FILLER_0_3 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_4 FILLER_0_32 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_8 FILLER_0_39 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 FILLER_0_47 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_8 FILLER_0_7 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__fill_2 FILLER_1_12 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__fill_1 FILLER_1_20 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_6 FILLER_1_24 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_12 FILLER_1_33 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__fill_2 FILLER_1_45 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 FILLER_1_6 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_12 FILLER_2_15 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_4 FILLER_2_27 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_12 FILLER_2_3 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_6 FILLER_2_32 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_6 FILLER_2_44 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_12 FILLER_3_18 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_12 FILLER_3_30 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_8 FILLER_3_42 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_12 FILLER_3_6 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_4 FILLER_4_10 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__fill_1 FILLER_4_14 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__fill_2 FILLER_4_18 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_4 FILLER_4_26 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__fill_1 FILLER_4_3 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__fill_1 FILLER_4_30 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 FILLER_4_35 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__fill_2 FILLER_4_41 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_4 FILLER_4_46 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_12 FILLER_5_11 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_8 FILLER_5_23 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 FILLER_5_31 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_6 FILLER_5_40 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__fill_1 FILLER_5_49 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__fill_2 FILLER_5_6 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_8 FILLER_6_12 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__fill_1 FILLER_6_20 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__fill_1 FILLER_6_24 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 FILLER_6_28 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_6 FILLER_6_3 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_4 FILLER_6_32 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__fill_1 FILLER_6_36 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_8 FILLER_6_40 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__fill_2 FILLER_6_48 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_12 FILLER_7_15 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_6 FILLER_7_27 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_12 FILLER_7_3 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_6 FILLER_7_36 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__fill_1 FILLER_7_42 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_4 FILLER_7_46 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_12 FILLER_8_15 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_4 FILLER_8_27 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_12 FILLER_8_3 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_12 FILLER_8_32 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_6 FILLER_8_44 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_0 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_1 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_10 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_11 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_12 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_13 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_14 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_15 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_16 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_17 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_18 (
+    .VGND(VGND),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_19 (
+    .VGND(VGND),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_2 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_20 (
+    .VGND(VGND),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_21 (
+    .VGND(VGND),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_22 (
+    .VGND(VGND),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_3 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_4 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_5 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_6 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_7 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_8 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_9 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[0]  (
+    .HI(\user_proj_id_high[0] ),
+    .LO(mask_rev[0]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[10]  (
+    .HI(\user_proj_id_high[10] ),
+    .LO(mask_rev[10]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[11]  (
+    .HI(\user_proj_id_high[11] ),
+    .LO(mask_rev[11]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[12]  (
+    .LO(\user_proj_id_low[12] ),
+    .HI(mask_rev[12]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[13]  (
+    .HI(\user_proj_id_high[13] ),
+    .LO(mask_rev[13]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[14]  (
+    .HI(\user_proj_id_high[14] ),
+    .LO(mask_rev[14]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[15]  (
+    .HI(\user_proj_id_high[15] ),
+    .LO(mask_rev[15]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[16]  (
+    .LO(\user_proj_id_low[16] ),
+    .HI(mask_rev[16]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[17]  (
+    .HI(\user_proj_id_high[17] ),
+    .LO(mask_rev[17]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[18]  (
+    .HI(\user_proj_id_high[18] ),
+    .LO(mask_rev[18]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[19]  (
+    .HI(\user_proj_id_high[19] ),
+    .LO(mask_rev[19]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[1]  (
+    .HI(\user_proj_id_high[1] ),
+    .LO(mask_rev[1]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[20]  (
+    .LO(\user_proj_id_low[20] ),
+    .HI(mask_rev[20]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[21]  (
+    .HI(\user_proj_id_high[21] ),
+    .LO(mask_rev[21]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[22]  (
+    .LO(\user_proj_id_low[22] ),
+    .HI(mask_rev[22]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[23]  (
+    .LO(\user_proj_id_low[23] ),
+    .HI(mask_rev[23]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[24]  (
+    .LO(\user_proj_id_low[24] ),
+    .HI(mask_rev[24]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[25]  (
+    .LO(\user_proj_id_low[25] ),
+    .HI(mask_rev[25]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[26]  (
+    .HI(\user_proj_id_high[26] ),
+    .LO(mask_rev[26]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[27]  (
+    .HI(\user_proj_id_high[27] ),
+    .LO(mask_rev[27]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[28]  (
+    .LO(\user_proj_id_low[28] ),
+    .HI(mask_rev[28]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[29]  (
+    .HI(\user_proj_id_high[29] ),
+    .LO(mask_rev[29]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[2]  (
+    .HI(\user_proj_id_high[2] ),
+    .LO(mask_rev[2]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[30]  (
+    .LO(\user_proj_id_low[30] ),
+    .HI(mask_rev[30]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[31]  (
+    .HI(\user_proj_id_high[31] ),
+    .LO(mask_rev[31]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[3]  (
+    .HI(\user_proj_id_high[3] ),
+    .LO(mask_rev[3]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[4]  (
+    .HI(\user_proj_id_high[4] ),
+    .LO(mask_rev[4]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[5]  (
+    .HI(\user_proj_id_high[5] ),
+    .LO(mask_rev[5]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[6]  (
+    .HI(\user_proj_id_high[6] ),
+    .LO(mask_rev[6]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[7]  (
+    .HI(\user_proj_id_high[7] ),
+    .LO(mask_rev[7]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[8]  (
+    .HI(\user_proj_id_high[8] ),
+    .LO(mask_rev[8]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[9]  (
+    .HI(\user_proj_id_high[9] ),
+    .LO(mask_rev[9]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+endmodule
diff --git a/tapeout/outputs/verilog/rtl/caravel.v b/tapeout/outputs/verilog/rtl/caravel.v
new file mode 100644
index 0000000..518b8a9
--- /dev/null
+++ b/tapeout/outputs/verilog/rtl/caravel.v
@@ -0,0 +1,1635 @@
+ `ifdef SIM
+ `default_nettype wire
+ `endif
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+/*--------------------------------------------------------------*/
+/* caravel, a project harness for the Google/SkyWater sky130	*/
+/* fabrication process and open source PDK			*/
+/*                                                          	*/
+/* Copyright 2020 efabless, Inc.                            	*/
+/* Written by Tim Edwards, December 2019                    	*/
+/* and Mohamed Shalan, August 2020			    	*/
+/* This file is open source hardware released under the     	*/
+/* Apache 2.0 license.  See file LICENSE.                   	*/
+/*								*/
+/* Updated 10/15/2021:  Revised using the housekeeping module	*/
+/* from housekeeping.v (refactoring a number of functions from	*/
+/* the management SoC).						*/
+/*                                                          	*/
+/*--------------------------------------------------------------*/
+
+module caravel (
+
+    // All top-level I/O are package-facing pins
+
+    inout vddio,	// Common 3.3V padframe/ESD power
+    inout vddio_2,	// Common 3.3V padframe/ESD power
+    inout vssio,	// Common padframe/ESD ground
+    inout vssio_2,	// Common padframe/ESD ground
+    inout vdda,		// Management 3.3V power
+    inout vssa,		// Common analog ground
+    inout vccd,		// Management/Common 1.8V power
+    inout vssd,		// Common digital ground
+    inout vdda1,	// User area 1 3.3V power
+    inout vdda1_2,	// User area 1 3.3V power
+    inout vdda2,	// User area 2 3.3V power
+    inout vssa1,	// User area 1 analog ground
+    inout vssa1_2,	// User area 1 analog ground
+    inout vssa2,	// User area 2 analog ground
+    inout vccd1,	// User area 1 1.8V power
+    inout vccd2,	// User area 2 1.8V power
+    inout vssd1,	// User area 1 digital ground
+    inout vssd2,	// User area 2 digital ground
+
+    inout gpio,		// Used for external LDO control
+    inout [`MPRJ_IO_PADS-1:0] mprj_io,
+    input clock,    	// CMOS core clock input, not a crystal
+    input resetb,	// Reset input (sense inverted)
+
+    // Note that only two flash data pins are dedicated to the
+    // management SoC wrapper.  The management SoC exports the
+    // quad SPI mode status to make use of the top two mprj_io
+    // pins for io2 and io3.
+
+    output flash_csb,
+    output flash_clk,
+    output flash_io0,
+    output flash_io1
+);
+
+    //------------------------------------------------------------
+    // This value is uniquely defined for each user project.
+    //------------------------------------------------------------
+    parameter USER_PROJECT_ID = 32'h00088bca;
+
+    /*
+     *--------------------------------------------------------------------
+     *
+     * These pins are overlaid on mprj_io space.  They have the function
+     * below when the management processor is in reset, or in the default
+     * configuration.  They are assigned to uses in the user space by the
+     * configuration program running off of the SPI flash.  Note that even
+     * when the user has taken control of these pins, they can be restored
+     * to the original use by setting the resetb pin low.  The SPI pins and
+     * UART pins can be connected directly to an FTDI chip as long as the
+     * FTDI chip sets these lines to high impedence (input function) at
+     * all times except when holding the chip in reset.
+     *
+     * JTAG       = mprj_io[0]		(inout)
+     * SDO 	  = mprj_io[1]		(output)
+     * SDI 	  = mprj_io[2]		(input)
+     * CSB 	  = mprj_io[3]		(input)
+     * SCK	  = mprj_io[4]		(input)
+     * ser_rx     = mprj_io[5]		(input)
+     * ser_tx     = mprj_io[6]		(output)
+     * irq 	  = mprj_io[7]		(input)
+     *
+     * spi_sck    = mprj_io[32]		(output)
+     * spi_csb    = mprj_io[33]		(output)
+     * spi_sdi    = mprj_io[34]		(input)
+     * spi_sdo    = mprj_io[35]		(output)
+     * flash_io2  = mprj_io[36]		(inout) 
+     * flash_io3  = mprj_io[37]		(inout) 
+     *
+     * These pins are reserved for any project that wants to incorporate
+     * its own processor and flash controller.  While a user project can
+     * technically use any available I/O pins for the purpose, these
+     * four pins connect to a pass-through mode from the SPI slave (pins
+     * 1-4 above) so that any SPI flash connected to these specific pins
+     * can be accessed through the SPI slave even when the processor is in
+     * reset.
+     *
+     * user_flash_csb = mprj_io[8]
+     * user_flash_sck = mprj_io[9]
+     * user_flash_io0 = mprj_io[10]
+     * user_flash_io1 = mprj_io[11]
+     *
+     *--------------------------------------------------------------------
+     */
+
+    // One-bit GPIO dedicated to management SoC (outside of user control)
+    wire gpio_out_core;
+    wire gpio_in_core;
+    wire gpio_mode0_core;
+    wire gpio_mode1_core;
+    wire gpio_outenb_core;
+    wire gpio_inenb_core;
+
+    // User Project Control (pad-facing)
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_inp_dis;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_oeb;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_vtrip_sel;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_slow_sel;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_holdover;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_en;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_sel;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol;
+    wire [`MPRJ_IO_PADS*3-1:0] mprj_io_dm;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_in;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_out;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_one;
+
+    // User Project Control (user-facing)
+    wire [`MPRJ_IO_PADS-1:0] user_io_oeb;
+    wire [`MPRJ_IO_PADS-1:0] user_io_in;
+    wire [`MPRJ_IO_PADS-1:0] user_io_out;
+    wire [`MPRJ_IO_PADS-10:0] user_analog_io;
+
+    /* Padframe control signals */
+    wire [`MPRJ_IO_PADS_1-1:0] gpio_serial_link_1;
+    wire [`MPRJ_IO_PADS_2-1:0] gpio_serial_link_2;
+    wire mprj_io_loader_resetn;
+    wire mprj_io_loader_clock;
+    wire mprj_io_loader_strobe;
+    wire mprj_io_loader_data_1;		/* user1 side serial loader */
+    wire mprj_io_loader_data_2;		/* user2 side serial loader */
+
+    // User Project Control management I/O
+    // There are two types of GPIO connections:
+    // (1) Full Bidirectional: Management connects to in, out, and oeb
+    //     Uses:  JTAG and SDO
+    // (2) Selectable bidirectional:  Management connects to in and out,
+    //	   which are tied together.  oeb is grounded (oeb from the
+    //	   configuration is used)
+
+    // SDI 	 = mprj_io[2]		(input)
+    // CSB 	 = mprj_io[3]		(input)
+    // SCK	 = mprj_io[4]		(input)
+    // ser_rx    = mprj_io[5]		(input)
+    // ser_tx    = mprj_io[6]		(output)
+    // irq 	 = mprj_io[7]		(input)
+
+    wire [`MPRJ_IO_PADS-1:0] mgmt_io_in;	/* two- and three-pin data in	*/
+    wire [`MPRJ_IO_PADS-1:0] mgmt_io_out;	/* two- and three-pin data out	*/
+    wire [`MPRJ_IO_PADS-1:0] mgmt_io_oeb;	/* output enable, used only by	*/
+						/* the three-pin interfaces	*/
+    wire [`MPRJ_PWR_PADS-1:0] pwr_ctrl_nc;	/* no-connects */
+
+    /* Buffers are placed between housekeeping and gpio_control_block		*/
+    /* instances to mitigate timing issues on very long (> 1.5mm) wires.	*/
+    wire [`MPRJ_IO_PADS-1:0] mgmt_io_in_hk;	/* mgmt_io_in at housekeeping	*/
+    wire [`MPRJ_IO_PADS-1:0] mgmt_io_out_hk;	/* mgmt_io_out at housekeeping	*/
+    wire [`MPRJ_IO_PADS-1:0] mgmt_io_oeb_hk;	/* mgmt_io_oeb at housekeeping	*/
+    
+    wire clock_core;
+
+    // Power-on-reset signal.  The reset pad generates the sense-inverted
+    // reset at 3.3V.  The 1.8V signal and the inverted 1.8V signal are
+    // derived.
+
+    wire porb_h;
+    wire porb_l;
+    wire por_l;
+
+    wire rstb_h;
+    wire rstb_l;
+
+    // Flash SPI communication (management SoC to housekeeping)
+    wire flash_clk_core,     flash_csb_core;
+    wire flash_clk_oeb_core, flash_csb_oeb_core;
+    wire flash_io0_oeb_core, flash_io1_oeb_core;
+    wire flash_io2_oeb_core, flash_io3_oeb_core;
+    wire flash_io0_ieb_core, flash_io1_ieb_core;
+    wire flash_io2_ieb_core, flash_io3_ieb_core;
+    wire flash_io0_do_core,  flash_io1_do_core;
+    wire flash_io2_do_core,  flash_io3_do_core;
+    wire flash_io0_di_core,  flash_io1_di_core;
+    wire flash_io2_di_core,  flash_io3_di_core;
+
+    // Flash SPI communication (
+    wire flash_clk_frame;
+    wire flash_csb_frame;
+    wire flash_clk_oeb, flash_csb_oeb;
+    wire flash_clk_ieb, flash_csb_ieb;
+    wire flash_io0_oeb, flash_io1_oeb;
+    wire flash_io0_ieb, flash_io1_ieb;
+    wire flash_io0_do,  flash_io1_do;
+    wire flash_io0_di,  flash_io1_di;
+
+	// Flash buffered signals
+    wire flash_clk_frame_buf;
+    wire flash_csb_frame_buf;
+    wire flash_clk_ieb_buf, flash_csb_ieb_buf;
+    wire flash_io0_oeb_buf, flash_io1_oeb_buf;
+    wire flash_io0_ieb_buf, flash_io1_ieb_buf;
+    wire flash_io0_do_buf,  flash_io1_do_buf;
+    wire flash_io0_di_buf,  flash_io1_di_buf;
+	
+	// Clock and reset buffered signals
+	wire caravel_clk_buf;
+	wire caravel_rstn_buf;
+	wire clock_core_buf;
+
+	// SoC pass through buffered signals
+	wire mprj_io_loader_clock_buf;
+	wire mprj_io_loader_strobe_buf;
+	wire mprj_io_loader_resetn_buf;
+	wire mprj_io_loader_data_2_buf;
+	wire rstb_l_buf;
+	wire por_l_buf;
+	wire porb_h_buf;
+	
+
+    // SoC core
+    wire caravel_clk;
+    wire caravel_clk2;
+    wire caravel_rstn;
+	
+	// top-level buffers
+	buff_flash_clkrst flash_clkrst_buffers (
+	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+	`endif
+	.in_n({
+		caravel_clk,
+		caravel_rstn,
+		flash_clk_frame, 
+		flash_csb_frame, 
+		flash_clk_oeb, 
+		flash_csb_oeb, 
+		flash_io0_oeb, 
+		flash_io1_oeb,
+		flash_io0_ieb, 
+		flash_io1_ieb,
+		flash_io0_do,  
+		flash_io1_do }), 
+	.in_s({
+		clock_core,
+		flash_io1_di, 
+		flash_io0_di }),
+	.out_s({ 
+		caravel_clk_buf,
+		caravel_rstn_buf,
+		flash_clk_frame_buf, 
+		flash_csb_frame_buf, 
+		flash_clk_oeb_buf, 
+		flash_csb_oeb_buf, 
+		flash_io0_oeb_buf, 
+		flash_io1_oeb_buf,
+		flash_io0_ieb_buf, 
+		flash_io1_ieb_buf,
+		flash_io0_do_buf,  
+		flash_io1_do_buf }), 
+	.out_n({
+		clock_core_buf,
+		flash_io1_di_buf, 
+		flash_io0_di_buf })
+	);
+
+	`ifdef NO_TOP_LEVEL_BUFFERING
+		assign mgmt_io_in_hk = mgmt_io_in;
+		assign mgmt_io_out = mgmt_io_out_hk;
+		assign mgmt_io_oeb = mgmt_io_oeb_hk;
+	`else
+
+		/* NOTE: The first 7 GPIO are unbuffered, and all
+		 * OEB lines except the last three are unbuffered
+		 * (most of these end up being no-connects from
+		 * housekeeping).
+		 */
+		assign mgmt_io_in_hk[6:0] = mgmt_io_in[6:0];
+		assign mgmt_io_out[6:0] = mgmt_io_out_hk[6:0];
+		assign mgmt_io_oeb[34:0] = mgmt_io_oeb_hk[34:0];
+
+		gpio_signal_buffering sigbuf (
+		`ifdef USE_POWER_PINS
+			.vccd(vccd_core),
+			.vssd(vssd_core),
+		`endif
+		.mgmt_io_in_unbuf(mgmt_io_in[37:7]),
+		.mgmt_io_out_unbuf(mgmt_io_out_hk[37:7]),
+		.mgmt_io_oeb_unbuf(mgmt_io_oeb_hk[37:35]),
+		.mgmt_io_in_buf(mgmt_io_in_hk[37:7]),
+		.mgmt_io_out_buf(mgmt_io_out[37:7]),
+		.mgmt_io_oeb_buf(mgmt_io_oeb[37:35])
+		);
+	`endif
+
+	chip_io padframe(
+	`ifndef TOP_ROUTING
+		// Package Pins
+		.vddio_pad	(vddio),		// Common padframe/ESD supply
+		.vddio_pad2	(vddio_2),
+		.vssio_pad	(vssio),		// Common padframe/ESD ground
+		.vssio_pad2	(vssio_2),
+		.vccd_pad	(vccd),			// Common 1.8V supply
+		.vssd_pad	(vssd),			// Common digital ground
+		.vdda_pad	(vdda),			// Management analog 3.3V supply
+		.vssa_pad	(vssa),			// Management analog ground
+		.vdda1_pad	(vdda1),		// User area 1 3.3V supply
+		.vdda1_pad2	(vdda1_2),		
+		.vdda2_pad	(vdda2),		// User area 2 3.3V supply
+		.vssa1_pad	(vssa1),		// User area 1 analog ground
+		.vssa1_pad2	(vssa1_2),
+		.vssa2_pad	(vssa2),		// User area 2 analog ground
+		.vccd1_pad	(vccd1),		// User area 1 1.8V supply
+		.vccd2_pad	(vccd2),		// User area 2 1.8V supply
+		.vssd1_pad	(vssd1),		// User area 1 digital ground
+		.vssd2_pad	(vssd2),		// User area 2 digital ground
+        .vddio	(vddio_core),
+        .vssio	(vssio_core),
+        .vdda	(vdda_core),
+        .vssa	(vssa_core),
+        .vccd	(vccd_core),
+        .vssd	(vssd_core),
+        .vdda1	(vdda1_core),
+        .vdda2	(vdda2_core),
+        .vssa1	(vssa1_core),
+        .vssa2	(vssa2_core),
+        .vccd1	(vccd1_core),
+        .vccd2	(vccd2_core),
+        .vssd1	(vssd1_core),
+        .vssd2	(vssd2_core),
+	`endif
+	// Core Side Pins
+	.gpio(gpio),
+	.mprj_io(mprj_io),
+	.clock(clock),
+	.resetb(resetb),
+	.flash_csb(flash_csb),
+	.flash_clk(flash_clk),
+	.flash_io0(flash_io0),
+	.flash_io1(flash_io1),
+	// SoC Core Interface
+	.porb_h(porb_h),
+	.por(por_l_buf),
+	.resetb_core_h(rstb_h),
+	.clock_core(clock_core),
+	.gpio_out_core(gpio_out_core),
+	.gpio_in_core(gpio_in_core),
+	.gpio_mode0_core(gpio_mode0_core),
+	.gpio_mode1_core(gpio_mode1_core),
+	.gpio_outenb_core(gpio_outenb_core),
+	.gpio_inenb_core(gpio_inenb_core),
+	.flash_csb_core(flash_csb_frame_buf),
+	.flash_clk_core(flash_clk_frame_buf),
+	.flash_csb_oeb_core(flash_csb_oeb_buf),
+	.flash_clk_oeb_core(flash_clk_oeb_buf),
+	.flash_io0_oeb_core(flash_io0_oeb_buf),
+	.flash_io1_oeb_core(flash_io1_oeb_buf),
+	.flash_io0_ieb_core(flash_io0_ieb_buf),
+	.flash_io1_ieb_core(flash_io1_ieb_buf),
+	.flash_io0_do_core(flash_io0_do_buf),
+	.flash_io1_do_core(flash_io1_do_buf),
+	.flash_io0_di_core(flash_io0_di),
+	.flash_io1_di_core(flash_io1_di),
+	.mprj_io_one(mprj_io_one),
+	.mprj_io_in(mprj_io_in),
+	.mprj_io_out(mprj_io_out),
+	.mprj_io_oeb(mprj_io_oeb),
+	.mprj_io_inp_dis(mprj_io_inp_dis),
+	.mprj_io_ib_mode_sel(mprj_io_ib_mode_sel),
+	.mprj_io_vtrip_sel(mprj_io_vtrip_sel),
+	.mprj_io_slow_sel(mprj_io_slow_sel),
+	.mprj_io_holdover(mprj_io_holdover),
+	.mprj_io_analog_en(mprj_io_analog_en),
+	.mprj_io_analog_sel(mprj_io_analog_sel),
+	.mprj_io_analog_pol(mprj_io_analog_pol),
+	.mprj_io_dm(mprj_io_dm),
+	.mprj_analog_io(user_analog_io)
+    );
+
+
+    // Logic analyzer signals
+    wire [127:0] la_data_in_user;  // From CPU to MPRJ
+    wire [127:0] la_data_in_mprj;  // From MPRJ to CPU
+    wire [127:0] la_data_out_mprj; // From CPU to MPRJ
+    wire [127:0] la_data_out_user; // From MPRJ to CPU
+    wire [127:0] la_oenb_user;     // From CPU to MPRJ
+    wire [127:0] la_oenb_mprj;     // From CPU to MPRJ
+    wire [127:0] la_iena_mprj;     // From CPU only
+
+    wire [2:0]   user_irq;	  // From MRPJ to CPU
+    wire [2:0]   user_irq_core;
+    wire [2:0]   user_irq_ena;
+    wire [2:0]	 irq_spi;	  // From SPI and external pins
+
+    // Exported Wishbone Bus (processor facing)
+    wire mprj_iena_wb;
+    wire mprj_cyc_o_core;
+    wire mprj_stb_o_core;
+    wire mprj_we_o_core;
+    wire [3:0] mprj_sel_o_core;
+    wire [31:0] mprj_adr_o_core;
+    wire [31:0] mprj_dat_o_core;
+    wire mprj_ack_i_core;
+    wire [31:0] mprj_dat_i_core;
+
+    wire [31:0] hk_dat_i;
+    wire hk_ack_i;
+    wire hk_stb_o;
+    wire hk_cyc_o;
+
+    // Exported Wishbone Bus (user area facing)
+    wire 	mprj_cyc_o_user;
+    wire 	mprj_stb_o_user;
+    wire 	mprj_we_o_user;
+    wire [3:0]  mprj_sel_o_user;
+    wire [31:0] mprj_adr_o_user;
+    wire [31:0] mprj_dat_o_user;
+    wire [31:0] mprj_dat_i_user;
+    wire	mprj_ack_i_user;
+
+    // Mask revision
+    wire [31:0] mask_rev;
+
+    wire 	mprj_clock;
+    wire 	mprj_clock2;
+    wire 	mprj_reset;
+
+    // Power monitoring 
+    wire	mprj_vcc_pwrgood;
+    wire	mprj2_vcc_pwrgood;
+    wire	mprj_vdd_pwrgood;
+    wire	mprj2_vdd_pwrgood;
+
+`ifdef USE_SRAM_RO_INTERFACE
+    // SRAM read-only access from housekeeping
+    wire 	hkspi_sram_clk;
+    wire 	hkspi_sram_csb;
+    wire [7:0]	hkspi_sram_addr;
+    wire [31:0]	hkspi_sram_data;
+`endif
+
+    // Management processor (wrapper).  Any management core
+    // implementation must match this pinout.
+
+    // Pass thru clock and reset
+    wire 	clk_passthru;
+    wire 	resetn_passthru;
+
+	// NC passthru signal porb_h 
+	wire porb_h_in_nc;
+	wire porb_h_out_nc;
+
+    mgmt_core_wrapper soc (
+	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+	`endif
+
+	// SoC pass through buffered signals
+	.serial_clock_in(mprj_io_loader_clock),
+	.serial_clock_out(mprj_io_loader_clock_buf),
+	.serial_load_in(mprj_io_loader_strobe),
+	.serial_load_out(mprj_io_loader_strobe_buf),
+	.serial_resetn_in(mprj_io_loader_resetn),
+	.serial_resetn_out(mprj_io_loader_resetn_buf),
+	.serial_data_2_in(mprj_io_loader_data_2),
+	.serial_data_2_out(mprj_io_loader_data_2_buf),
+	.rstb_l_in(rstb_l),
+	.rstb_l_out(rstb_l_buf),
+	.porb_h_in(porb_h_in_nc),
+	.porb_h_out(porb_h_out_nc),
+	.por_l_in(por_l),
+	.por_l_out(por_l_buf),
+
+	// Clock and reset
+	.core_clk(caravel_clk_buf),
+	.core_rstn(caravel_rstn_buf),
+
+    // Pass thru Clock and reset
+	.clk_in(caravel_clk_buf),
+	.resetn_in(caravel_rstn_buf),
+	.clk_out(clk_passthru),
+	.resetn_out(resetn_passthru),
+
+	// GPIO (1 pin)
+	.gpio_out_pad(gpio_out_core),
+	.gpio_in_pad(gpio_in_core),
+	.gpio_mode0_pad(gpio_mode0_core),
+	.gpio_mode1_pad(gpio_mode1_core),
+	.gpio_outenb_pad(gpio_outenb_core),
+	.gpio_inenb_pad(gpio_inenb_core),
+
+	// Primary SPI flash controller
+	.flash_csb(flash_csb_core),
+	.flash_clk(flash_clk_core),
+	.flash_io0_oeb(flash_io0_oeb_core),
+	.flash_io0_di(flash_io0_di_core),
+	.flash_io0_do(flash_io0_do_core),
+	.flash_io1_oeb(flash_io1_oeb_core),
+	.flash_io1_di(flash_io1_di_core),
+	.flash_io1_do(flash_io1_do_core),
+	.flash_io2_oeb(flash_io2_oeb_core),
+	.flash_io2_di(flash_io2_di_core),
+	.flash_io2_do(flash_io2_do_core),
+	.flash_io3_oeb(flash_io3_oeb_core),
+	.flash_io3_di(flash_io3_di_core),
+	.flash_io3_do(flash_io3_do_core),
+
+	// Exported Wishbone Bus
+	.mprj_wb_iena(mprj_iena_wb),
+	.mprj_cyc_o(mprj_cyc_o_core),
+	.mprj_stb_o(mprj_stb_o_core),
+	.mprj_we_o(mprj_we_o_core),
+	.mprj_sel_o(mprj_sel_o_core),
+	.mprj_adr_o(mprj_adr_o_core),
+	.mprj_dat_o(mprj_dat_o_core),
+	.mprj_ack_i(mprj_ack_i_core),
+	.mprj_dat_i(mprj_dat_i_core),
+
+	.hk_stb_o(hk_stb_o),
+	.hk_cyc_o(hk_cyc_o),
+	.hk_dat_i(hk_dat_i),
+	.hk_ack_i(hk_ack_i),
+
+	// IRQ
+	.irq({irq_spi, user_irq}),
+	.user_irq_ena(user_irq_ena),
+
+	// Module status (these may or may not be implemented)
+	.qspi_enabled(qspi_enabled),
+	.uart_enabled(uart_enabled),
+	.spi_enabled(spi_enabled),
+	.debug_mode(debug_mode),
+
+	// Module I/O (these may or may not be implemented)
+	// UART
+	.ser_tx(ser_tx),
+	.ser_rx(ser_rx),
+	// SPI master
+	.spi_sdi(spi_sdi),
+	.spi_csb(spi_csb),
+	.spi_sck(spi_sck),
+	.spi_sdo(spi_sdo),
+	.spi_sdoenb(spi_sdoenb),
+	// Debug
+	.debug_in(debug_in),
+	.debug_out(debug_out),
+	.debug_oeb(debug_oeb),
+	// Logic analyzer
+	.la_input(la_data_in_mprj),
+	.la_output(la_data_out_mprj),
+	.la_oenb(la_oenb_mprj),
+	.la_iena(la_iena_mprj),
+
+`ifdef USE_SRAM_RO_INTERFACE
+	// SRAM Read-only access from housekeeping
+	.sram_ro_clk(hkspi_sram_clk),
+	.sram_ro_csb(hkspi_sram_csb),
+	.sram_ro_addr(hkspi_sram_addr),
+	.sram_ro_data(hkspi_sram_data),
+`endif
+
+	// Trap status
+	.trap(trap)
+    );
+
+    /* Clock and reset to user space are passed through a tristate	*/
+    /* buffer like the above, but since they are intended to be		*/
+    /* always active, connect the enable to the logic-1 output from	*/
+    /* the vccd1 domain.						*/
+
+    mgmt_protect mgmt_buffers (
+	`ifdef USE_POWER_PINS
+ 	    .vccd(vccd_core),
+	    .vssd(vssd_core),
+	    .vccd1(vccd1_core),
+	    .vssd1(vssd1_core),
+	    .vccd2(vccd2_core),
+	    .vssd2(vssd2_core),
+	    .vdda1(vdda1_core),
+	    .vssa1(vssa1_core),
+	    .vdda2(vdda2_core),
+	    .vssa2(vssa2_core),
+	`endif
+	.caravel_clk(clk_passthru),
+	.caravel_clk2(caravel_clk2),
+	.caravel_rstn(resetn_passthru),
+	.mprj_iena_wb(mprj_iena_wb),
+	.mprj_cyc_o_core(mprj_cyc_o_core),
+	.mprj_stb_o_core(mprj_stb_o_core),
+	.mprj_we_o_core(mprj_we_o_core),
+	.mprj_sel_o_core(mprj_sel_o_core),
+	.mprj_adr_o_core(mprj_adr_o_core),
+	.mprj_dat_o_core(mprj_dat_o_core),
+	.mprj_ack_i_core(mprj_ack_i_core),
+	.mprj_dat_i_core(mprj_dat_i_core),
+	.user_irq_core(user_irq_core),
+	.user_irq_ena(user_irq_ena),
+	.la_data_out_core(la_data_out_user),
+	.la_data_out_mprj(la_data_out_mprj),
+	.la_data_in_core(la_data_in_user),
+	.la_data_in_mprj(la_data_in_mprj),
+	.la_oenb_mprj(la_oenb_mprj),
+	.la_oenb_core(la_oenb_user),
+	.la_iena_mprj(la_iena_mprj),
+
+	.user_clock(mprj_clock),
+	.user_clock2(mprj_clock2),
+	.user_reset(mprj_reset),
+	.mprj_cyc_o_user(mprj_cyc_o_user),
+	.mprj_stb_o_user(mprj_stb_o_user),
+	.mprj_we_o_user(mprj_we_o_user),
+	.mprj_sel_o_user(mprj_sel_o_user),
+	.mprj_adr_o_user(mprj_adr_o_user),
+	.mprj_dat_o_user(mprj_dat_o_user),
+	.mprj_dat_i_user(mprj_dat_i_user),
+	.mprj_ack_i_user(mprj_ack_i_user),
+	.user_irq(user_irq),
+	.user1_vcc_powergood(mprj_vcc_pwrgood),
+	.user2_vcc_powergood(mprj2_vcc_pwrgood),
+	.user1_vdd_powergood(mprj_vdd_pwrgood),
+	.user2_vdd_powergood(mprj2_vdd_pwrgood)
+    );
+
+    /*--------------------------------------------------*/
+    /* Wrapper module around the user project 		*/
+    /*--------------------------------------------------*/
+
+    user_project_wrapper mprj ( 
+        `ifdef USE_POWER_PINS
+	    .vdda1(vdda1_core),		// User area 1 3.3V power
+	    .vdda2(vdda2_core),		// User area 2 3.3V power
+	    .vssa1(vssa1_core),		// User area 1 analog ground
+	    .vssa2(vssa2_core),		// User area 2 analog ground
+	    .vccd1(vccd1_core),		// User area 1 1.8V power
+	    .vccd2(vccd2_core),		// User area 2 1.8V power
+	    .vssd1(vssd1_core),		// User area 1 digital ground
+	    .vssd2(vssd2_core),		// User area 2 digital ground
+    	`endif
+
+    	.wb_clk_i(mprj_clock),
+    	.wb_rst_i(mprj_reset),
+
+	// Management SoC Wishbone bus (exported)
+	.wbs_cyc_i(mprj_cyc_o_user),
+	.wbs_stb_i(mprj_stb_o_user),
+	.wbs_we_i(mprj_we_o_user),
+	.wbs_sel_i(mprj_sel_o_user),
+	.wbs_adr_i(mprj_adr_o_user),
+	.wbs_dat_i(mprj_dat_o_user),
+	.wbs_ack_o(mprj_ack_i_user),
+	.wbs_dat_o(mprj_dat_i_user),
+
+	// GPIO pad 3-pin interface (plus analog)
+	.io_in (user_io_in),
+    	.io_out(user_io_out),
+    	.io_oeb(user_io_oeb),
+	.analog_io(user_analog_io),
+
+	// Logic analyzer
+	.la_data_in(la_data_in_user),
+	.la_data_out(la_data_out_user),
+	.la_oenb(la_oenb_user),
+
+	// Independent clock
+	.user_clock2(mprj_clock2),
+
+	// IRQ
+	.user_irq(user_irq_core)
+    );
+
+    /*------------------------------------------*/
+    /* End user project instantiation		*/
+    /*------------------------------------------*/
+
+    wire [`MPRJ_IO_PADS_1-1:0] gpio_serial_link_1_shifted;
+    wire [`MPRJ_IO_PADS_2-1:0] gpio_serial_link_2_shifted;
+
+    assign gpio_serial_link_1_shifted = {gpio_serial_link_1[`MPRJ_IO_PADS_1-2:0],
+					 mprj_io_loader_data_1};
+    // Note that serial_link_2 is backwards compared to serial_link_1, so it
+    // shifts in the other direction.
+    assign gpio_serial_link_2_shifted = {mprj_io_loader_data_2_buf,
+					 gpio_serial_link_2[`MPRJ_IO_PADS_2-1:1]};
+
+    // Propagating clock and reset to mitigate timing and fanout issues
+    wire [`MPRJ_IO_PADS_1-1:0] gpio_clock_1;
+    wire [`MPRJ_IO_PADS_2-1:0] gpio_clock_2;
+    wire [`MPRJ_IO_PADS_1-1:0] gpio_resetn_1;
+    wire [`MPRJ_IO_PADS_2-1:0] gpio_resetn_2;
+    wire [`MPRJ_IO_PADS_1-1:0] gpio_load_1;
+    wire [`MPRJ_IO_PADS_2-1:0] gpio_load_2;
+    wire [`MPRJ_IO_PADS_1-1:0] gpio_clock_1_shifted;
+    wire [`MPRJ_IO_PADS_2-1:0] gpio_clock_2_shifted;
+    wire [`MPRJ_IO_PADS_1-1:0] gpio_resetn_1_shifted;
+    wire [`MPRJ_IO_PADS_2-1:0] gpio_resetn_2_shifted;
+    wire [`MPRJ_IO_PADS_1-1:0] gpio_load_1_shifted;
+    wire [`MPRJ_IO_PADS_2-1:0] gpio_load_2_shifted;
+
+    assign gpio_clock_1_shifted = {gpio_clock_1[`MPRJ_IO_PADS_1-2:0],
+					 mprj_io_loader_clock};
+    assign gpio_clock_2_shifted = {mprj_io_loader_clock_buf,
+					gpio_clock_2[`MPRJ_IO_PADS_2-1:1]};
+    assign gpio_resetn_1_shifted = {gpio_resetn_1[`MPRJ_IO_PADS_1-2:0],
+					 mprj_io_loader_resetn};
+    assign gpio_resetn_2_shifted = {mprj_io_loader_resetn_buf,
+					gpio_resetn_2[`MPRJ_IO_PADS_2-1:1]};
+    assign gpio_load_1_shifted = {gpio_load_1[`MPRJ_IO_PADS_1-2:0],
+					 mprj_io_loader_strobe};
+    assign gpio_load_2_shifted = {mprj_io_loader_strobe_buf,
+					gpio_load_2[`MPRJ_IO_PADS_2-1:1]};
+
+    wire [2:0] spi_pll_sel;
+    wire [2:0] spi_pll90_sel;
+    wire [4:0] spi_pll_div;
+    wire [25:0] spi_pll_trim;
+
+    // Clocking control
+
+    caravel_clocking clock_ctrl (
+    `ifdef USE_POWER_PINS
+		.VPWR(vccd_core),
+		.VGND(vssd_core),
+    `endif
+        .ext_clk_sel(ext_clk_sel),
+        .ext_clk(clock_core_buf),
+        .pll_clk(pll_clk),
+        .pll_clk90(pll_clk90),
+        .resetb(rstb_l_buf),
+        .sel(spi_pll_sel),
+        .sel2(spi_pll90_sel),
+        .ext_reset(ext_reset),  // From housekeeping SPI
+        .core_clk(caravel_clk),
+        .user_clk(caravel_clk2),
+        .resetb_sync(caravel_rstn)
+    );
+
+    // DCO/Digital Locked Loop
+
+    digital_pll pll (
+    `ifdef USE_POWER_PINS
+		.VPWR(vccd_core),
+		.VGND(vssd_core),
+    `endif
+        .resetb(rstb_l_buf),
+        .enable(spi_pll_ena),
+        .osc(clock_core_buf),
+        .clockp({pll_clk, pll_clk90}),
+        .div(spi_pll_div),
+        .dco(spi_pll_dco_ena),
+        .ext_trim(spi_pll_trim)
+    );
+
+    // Housekeeping interface
+
+    housekeeping housekeeping (
+    `ifdef USE_POWER_PINS
+		.VPWR(vccd_core),
+		.VGND(vssd_core),
+    `endif
+
+        .wb_clk_i(caravel_clk),
+        .wb_rstn_i(caravel_rstn),
+
+        .wb_adr_i(mprj_adr_o_core),
+        .wb_dat_i(mprj_dat_o_core),
+        .wb_sel_i(mprj_sel_o_core),
+        .wb_we_i(mprj_we_o_core),
+        .wb_cyc_i(hk_cyc_o),
+        .wb_stb_i(hk_stb_o),
+        .wb_ack_o(hk_ack_i),
+        .wb_dat_o(hk_dat_i),
+
+        .porb(porb_l),
+
+        .pll_ena(spi_pll_ena),
+        .pll_dco_ena(spi_pll_dco_ena),
+        .pll_div(spi_pll_div),
+        .pll_sel(spi_pll_sel),
+        .pll90_sel(spi_pll90_sel),
+        .pll_trim(spi_pll_trim),
+        .pll_bypass(ext_clk_sel),
+
+	.qspi_enabled(qspi_enabled),
+	.uart_enabled(uart_enabled),
+	.spi_enabled(spi_enabled),
+	.debug_mode(debug_mode),
+
+	.ser_tx(ser_tx),
+	.ser_rx(ser_rx),
+
+	.spi_sdi(spi_sdi),
+	.spi_csb(spi_csb),
+	.spi_sck(spi_sck),
+	.spi_sdo(spi_sdo),
+	.spi_sdoenb(spi_sdoenb),
+
+	.debug_in(debug_in),
+	.debug_out(debug_out),
+	.debug_oeb(debug_oeb),
+
+        .irq(irq_spi),
+        .reset(ext_reset),
+
+        .serial_clock(mprj_io_loader_clock),
+        .serial_load(mprj_io_loader_strobe),
+        .serial_resetn(mprj_io_loader_resetn),
+        .serial_data_1(mprj_io_loader_data_1),
+        .serial_data_2(mprj_io_loader_data_2),
+
+	.mgmt_gpio_in(mgmt_io_in_hk),
+	.mgmt_gpio_out(mgmt_io_out_hk),
+	.mgmt_gpio_oeb(mgmt_io_oeb_hk),
+
+	.pwr_ctrl_out(pwr_ctrl_nc),	/* Not used in this version */
+
+        .trap(trap),
+
+	.user_clock(caravel_clk2),
+
+        .mask_rev_in(mask_rev),
+
+	.spimemio_flash_csb(flash_csb_core),
+	.spimemio_flash_clk(flash_clk_core),
+	.spimemio_flash_io0_oeb(flash_io0_oeb_core),
+	.spimemio_flash_io1_oeb(flash_io1_oeb_core),
+	.spimemio_flash_io2_oeb(flash_io2_oeb_core),
+	.spimemio_flash_io3_oeb(flash_io3_oeb_core),
+	.spimemio_flash_io0_do(flash_io0_do_core),
+	.spimemio_flash_io1_do(flash_io1_do_core),
+	.spimemio_flash_io2_do(flash_io2_do_core),
+	.spimemio_flash_io3_do(flash_io3_do_core),
+	.spimemio_flash_io0_di(flash_io0_di_core),
+	.spimemio_flash_io1_di(flash_io1_di_core),
+	.spimemio_flash_io2_di(flash_io2_di_core),
+	.spimemio_flash_io3_di(flash_io3_di_core),
+
+	.pad_flash_csb(flash_csb_frame),
+	.pad_flash_csb_oeb(flash_csb_oeb),
+	.pad_flash_clk(flash_clk_frame),
+	.pad_flash_clk_oeb(flash_clk_oeb),
+	.pad_flash_io0_oeb(flash_io0_oeb),
+	.pad_flash_io1_oeb(flash_io1_oeb),
+	.pad_flash_io0_ieb(flash_io0_ieb),
+	.pad_flash_io1_ieb(flash_io1_ieb),
+	.pad_flash_io0_do(flash_io0_do),
+	.pad_flash_io1_do(flash_io1_do),
+	.pad_flash_io0_di(flash_io0_di_buf),
+	.pad_flash_io1_di(flash_io1_di_buf),
+
+`ifdef USE_SRAM_RO_INTERFACE
+	.sram_ro_clk(hkspi_sram_clk),
+	.sram_ro_csb(hkspi_sram_csb),
+	.sram_ro_addr(hkspi_sram_addr),
+	.sram_ro_data(hkspi_sram_data),
+`endif
+
+	.usr1_vcc_pwrgood(mprj_vcc_pwrgood),
+	.usr2_vcc_pwrgood(mprj2_vcc_pwrgood),
+	.usr1_vdd_pwrgood(mprj_vdd_pwrgood),
+	.usr2_vdd_pwrgood(mprj2_vdd_pwrgood)
+    );
+
+    /* GPIO defaults (via programmed) */
+    wire [`MPRJ_IO_PADS*13-1:0] gpio_defaults;
+
+    /* Fixed defaults for the first 5 GPIO pins */
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(13'h1803)
+    ) gpio_defaults_block_0 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[12:0])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(13'h1803)
+    ) gpio_defaults_block_1 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[25:13])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(13'h0403)
+    ) gpio_defaults_block_2 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[38:26])
+    );
+
+    // CSB pin is set as an internal pull-up
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(13'h0801)
+    ) gpio_defaults_block_3 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[51:39])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(13'h0403)
+    ) gpio_defaults_block_4 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[64:52])
+    );
+
+    /* Via-programmable defaults for the rest of the GPIO pins */
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_5_INIT)
+    ) gpio_defaults_block_5 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[77:65])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_6_INIT)
+    ) gpio_defaults_block_6 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[90:78])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_7_INIT)
+    ) gpio_defaults_block_7 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[103:91])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_8_INIT)
+    ) gpio_defaults_block_8 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[116:104])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_9_INIT)
+    ) gpio_defaults_block_9 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[129:117])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_10_INIT)
+    ) gpio_defaults_block_10 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[142:130])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_11_INIT)
+    ) gpio_defaults_block_11 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[155:143])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_12_INIT)
+    ) gpio_defaults_block_12 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[168:156])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_13_INIT)
+    ) gpio_defaults_block_13 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[181:169])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_14_INIT)
+    ) gpio_defaults_block_14 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[194:182])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_15_INIT)
+    ) gpio_defaults_block_15 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[207:195])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_16_INIT)
+    ) gpio_defaults_block_16 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[220:208])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_17_INIT)
+    ) gpio_defaults_block_17 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[233:221])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_18_INIT)
+    ) gpio_defaults_block_18 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[246:234])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_19_INIT)
+    ) gpio_defaults_block_19 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[259:247])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_20_INIT)
+    ) gpio_defaults_block_20 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[272:260])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_21_INIT)
+    ) gpio_defaults_block_21 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[285:273])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_22_INIT)
+    ) gpio_defaults_block_22 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[298:286])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_23_INIT)
+    ) gpio_defaults_block_23 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[311:299])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_24_INIT)
+    ) gpio_defaults_block_24 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[324:312])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_25_INIT)
+    ) gpio_defaults_block_25 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[337:325])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_26_INIT)
+    ) gpio_defaults_block_26 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[350:338])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_27_INIT)
+    ) gpio_defaults_block_27 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[363:351])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_28_INIT)
+    ) gpio_defaults_block_28 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[376:364])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_29_INIT)
+    ) gpio_defaults_block_29 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[389:377])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_30_INIT)
+    ) gpio_defaults_block_30 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[402:390])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_31_INIT)
+    ) gpio_defaults_block_31 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[415:403])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_32_INIT)
+    ) gpio_defaults_block_32 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[428:416])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_33_INIT)
+    ) gpio_defaults_block_33 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[441:429])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_34_INIT)
+    ) gpio_defaults_block_34 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[454:442])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_35_INIT)
+    ) gpio_defaults_block_35 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[467:455])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_36_INIT)
+    ) gpio_defaults_block_36 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[480:468])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_37_INIT)
+    ) gpio_defaults_block_37 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[493:481])
+    );
+
+    // Each control block sits next to an I/O pad in the user area.
+    // It gets input through a serial chain from the previous control
+    // block and passes it to the next control block.  Due to the nature
+    // of the shift register, bits are presented in reverse, as the first
+    // bit in ends up as the last bit of the last I/O pad control block.
+
+    // There are two types of block;  the first two and the last two
+    // are configured to be full bidirectional under control of the
+    // management Soc (JTAG and SDO for the first two;  flash_io2 and
+    // flash_io3 for the last two).  The rest are configured to be default
+    // (input).  Note that the first two and last two are the ones closest
+    // to the management SoC on either side, which minimizes the wire length
+    // of the extra signals those pads need.
+
+    /* First two GPIOs (JTAG and SDO) */
+
+    gpio_control_block gpio_control_bidir_1 [1:0] (
+    	`ifdef USE_POWER_PINS
+	    .vccd(vccd_core),
+	    .vssd(vssd_core),
+	    .vccd1(vccd1_core),
+	    .vssd1(vssd1_core),
+        `endif
+
+	.gpio_defaults(gpio_defaults[25:0]),
+
+    	// Management Soc-facing signals
+
+    	.resetn(gpio_resetn_1_shifted[1:0]),
+    	.serial_clock(gpio_clock_1_shifted[1:0]),
+    	.serial_load(gpio_load_1_shifted[1:0]),
+
+    	.resetn_out(gpio_resetn_1[1:0]),
+    	.serial_clock_out(gpio_clock_1[1:0]),
+    	.serial_load_out(gpio_load_1[1:0]),
+
+    	.mgmt_gpio_in(mgmt_io_in[1:0]),
+	.mgmt_gpio_out(mgmt_io_out[1:0]),
+	.mgmt_gpio_oeb(mgmt_io_oeb[1:0]),
+
+        .one(mprj_io_one[1:0]),
+        .zero(),
+
+    	// Serial data chain for pad configuration
+    	.serial_data_in(gpio_serial_link_1_shifted[1:0]),
+    	.serial_data_out(gpio_serial_link_1[1:0]),
+
+    	// User-facing signals
+    	.user_gpio_out(user_io_out[1:0]),
+    	.user_gpio_oeb(user_io_oeb[1:0]),
+    	.user_gpio_in(user_io_in[1:0]),
+
+    	// Pad-facing signals (Pad GPIOv2)
+    	.pad_gpio_inenb(mprj_io_inp_dis[1:0]),
+    	.pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[1:0]),
+    	.pad_gpio_vtrip_sel(mprj_io_vtrip_sel[1:0]),
+    	.pad_gpio_slow_sel(mprj_io_slow_sel[1:0]),
+    	.pad_gpio_holdover(mprj_io_holdover[1:0]),
+    	.pad_gpio_ana_en(mprj_io_analog_en[1:0]),
+    	.pad_gpio_ana_sel(mprj_io_analog_sel[1:0]),
+    	.pad_gpio_ana_pol(mprj_io_analog_pol[1:0]),
+    	.pad_gpio_dm(mprj_io_dm[5:0]),
+    	.pad_gpio_outenb(mprj_io_oeb[1:0]),
+    	.pad_gpio_out(mprj_io_out[1:0]),
+    	.pad_gpio_in(mprj_io_in[1:0])
+    );
+
+    /* Section 1 GPIOs (GPIO 2 to 7) that start up under management control */
+
+    gpio_control_block gpio_control_in_1a [5:0] (
+        `ifdef USE_POWER_PINS
+            .vccd(vccd_core),
+	    .vssd(vssd_core),
+	    .vccd1(vccd1_core),
+	    .vssd1(vssd1_core),
+        `endif
+
+	.gpio_defaults(gpio_defaults[103:26]),
+
+    	// Management Soc-facing signals
+
+    	.resetn(gpio_resetn_1_shifted[7:2]),
+    	.serial_clock(gpio_clock_1_shifted[7:2]),
+    	.serial_load(gpio_load_1_shifted[7:2]),
+
+    	.resetn_out(gpio_resetn_1[7:2]),
+    	.serial_clock_out(gpio_clock_1[7:2]),
+    	.serial_load_out(gpio_load_1[7:2]),
+
+	.mgmt_gpio_in(mgmt_io_in[7:2]),
+	.mgmt_gpio_out(mgmt_io_out[7:2]),
+	.mgmt_gpio_oeb(mprj_io_one[7:2]),
+
+        .one(mprj_io_one[7:2]),
+        .zero(),
+
+    	// Serial data chain for pad configuration
+    	.serial_data_in(gpio_serial_link_1_shifted[7:2]),
+    	.serial_data_out(gpio_serial_link_1[7:2]),
+
+    	// User-facing signals
+    	.user_gpio_out(user_io_out[7:2]),
+    	.user_gpio_oeb(user_io_oeb[7:2]),
+    	.user_gpio_in(user_io_in[7:2]),
+
+    	// Pad-facing signals (Pad GPIOv2)
+    	.pad_gpio_inenb(mprj_io_inp_dis[7:2]),
+    	.pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[7:2]),
+    	.pad_gpio_vtrip_sel(mprj_io_vtrip_sel[7:2]),
+    	.pad_gpio_slow_sel(mprj_io_slow_sel[7:2]),
+    	.pad_gpio_holdover(mprj_io_holdover[7:2]),
+    	.pad_gpio_ana_en(mprj_io_analog_en[7:2]),
+    	.pad_gpio_ana_sel(mprj_io_analog_sel[7:2]),
+    	.pad_gpio_ana_pol(mprj_io_analog_pol[7:2]),
+    	.pad_gpio_dm(mprj_io_dm[23:6]),
+    	.pad_gpio_outenb(mprj_io_oeb[7:2]),
+    	.pad_gpio_out(mprj_io_out[7:2]),
+    	.pad_gpio_in(mprj_io_in[7:2])
+    );
+
+    /* Section 1 GPIOs (GPIO 8 to 18) */
+
+    gpio_control_block gpio_control_in_1 [`MPRJ_IO_PADS_1-9:0] (
+        `ifdef USE_POWER_PINS
+            .vccd(vccd_core),
+	    .vssd(vssd_core),
+	    .vccd1(vccd1_core),
+	    .vssd1(vssd1_core),
+        `endif
+
+	.gpio_defaults(gpio_defaults[(`MPRJ_IO_PADS_1*13-1):104]),
+
+    	// Management Soc-facing signals
+
+    	.resetn(gpio_resetn_1_shifted[(`MPRJ_IO_PADS_1-1):8]),
+    	.serial_clock(gpio_clock_1_shifted[(`MPRJ_IO_PADS_1-1):8]),
+    	.serial_load(gpio_load_1_shifted[(`MPRJ_IO_PADS_1-1):8]),
+
+    	.resetn_out(gpio_resetn_1[(`MPRJ_IO_PADS_1-1):8]),
+    	.serial_clock_out(gpio_clock_1[(`MPRJ_IO_PADS_1-1):8]),
+    	.serial_load_out(gpio_load_1[(`MPRJ_IO_PADS_1-1):8]),
+
+	.mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS_1-1):8]),
+	.mgmt_gpio_out(mgmt_io_out[(`MPRJ_IO_PADS_1-1):8]),
+	.mgmt_gpio_oeb(mprj_io_one[(`MPRJ_IO_PADS_1-1):8]),
+  
+        .one(mprj_io_one[(`MPRJ_IO_PADS_1-1):8]),
+        .zero(),
+
+    	// Serial data chain for pad configuration
+    	.serial_data_in(gpio_serial_link_1_shifted[(`MPRJ_IO_PADS_1-1):8]),
+    	.serial_data_out(gpio_serial_link_1[(`MPRJ_IO_PADS_1-1):8]),
+
+    	// User-facing signals
+    	.user_gpio_out(user_io_out[(`MPRJ_IO_PADS_1-1):8]),
+    	.user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS_1-1):8]),
+    	.user_gpio_in(user_io_in[(`MPRJ_IO_PADS_1-1):8]),
+
+    	// Pad-facing signals (Pad GPIOv2)
+    	.pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS_1-1):8]),
+    	.pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS_1-1):8]),
+    	.pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS_1-1):8]),
+    	.pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS_1-1):8]),
+    	.pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS_1-1):8]),
+    	.pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS_1-1):8]),
+    	.pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS_1-1):8]),
+    	.pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS_1-1):8]),
+    	.pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS_1*3-1):24]),
+    	.pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS_1-1):8]),
+    	.pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS_1-1):8]),
+    	.pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS_1-1):8])
+    );
+
+    /* Last three GPIOs (spi_sdo, flash_io2, and flash_io3) */
+
+    gpio_control_block gpio_control_bidir_2 [2:0] (
+    	`ifdef USE_POWER_PINS
+	    .vccd(vccd_core),
+	    .vssd(vssd_core),
+	    .vccd1(vccd1_core),
+	    .vssd1(vssd1_core),
+        `endif
+
+	.gpio_defaults(gpio_defaults[(`MPRJ_IO_PADS*13-1):(`MPRJ_IO_PADS*13-39)]),
+
+    	// Management Soc-facing signals
+
+    	.resetn(gpio_resetn_2_shifted[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+    	.serial_clock(gpio_clock_2_shifted[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+    	.serial_load(gpio_load_2_shifted[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+
+    	.resetn_out(gpio_resetn_2[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+    	.serial_clock_out(gpio_clock_2[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+    	.serial_load_out(gpio_load_2[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+
+    	.mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+	.mgmt_gpio_out(mgmt_io_out[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+	.mgmt_gpio_oeb(mgmt_io_oeb[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+
+        .one(mprj_io_one[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+        .zero(),
+
+    	// Serial data chain for pad configuration
+    	.serial_data_in(gpio_serial_link_2_shifted[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+    	.serial_data_out(gpio_serial_link_2[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+
+    	// User-facing signals
+    	.user_gpio_out(user_io_out[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.user_gpio_in(user_io_in[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+
+    	// Pad-facing signals (Pad GPIOv2)
+    	.pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS*3-1):(`MPRJ_IO_PADS*3-9)]),
+    	.pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)])
+    );
+
+    /* Section 2 GPIOs (GPIO 19 to 34) */
+
+    gpio_control_block gpio_control_in_2 [`MPRJ_IO_PADS_2-4:0] (
+    	`ifdef USE_POWER_PINS
+            .vccd(vccd_core),
+	    .vssd(vssd_core),
+	    .vccd1(vccd1_core),
+	    .vssd1(vssd1_core),
+        `endif
+
+	.gpio_defaults(gpio_defaults[(`MPRJ_IO_PADS*13-40):(`MPRJ_IO_PADS_1*13)]),
+
+    	// Management Soc-facing signals
+
+    	.resetn(gpio_resetn_2_shifted[(`MPRJ_IO_PADS_2-4):0]),
+    	.serial_clock(gpio_clock_2_shifted[(`MPRJ_IO_PADS_2-4):0]),
+    	.serial_load(gpio_load_2_shifted[(`MPRJ_IO_PADS_2-4):0]),
+
+    	.resetn_out(gpio_resetn_2[(`MPRJ_IO_PADS_2-4):0]),
+    	.serial_clock_out(gpio_clock_2[(`MPRJ_IO_PADS_2-4):0]),
+    	.serial_load_out(gpio_load_2[(`MPRJ_IO_PADS_2-4):0]),
+
+	.mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+	.mgmt_gpio_out(mgmt_io_out[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+	.mgmt_gpio_oeb(mprj_io_one[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+
+
+        .one(mprj_io_one[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+        .zero(),
+
+    	// Serial data chain for pad configuration
+    	.serial_data_in(gpio_serial_link_2_shifted[(`MPRJ_IO_PADS_2-4):0]),
+    	.serial_data_out(gpio_serial_link_2[(`MPRJ_IO_PADS_2-4):0]),
+
+    	// User-facing signals
+    	.user_gpio_out(user_io_out[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.user_gpio_in(user_io_in[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+
+    	// Pad-facing signals (Pad GPIOv2)
+    	.pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS*3-10):(`MPRJ_IO_PADS_1*3)]),
+    	.pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)])
+    );
+
+    user_id_programming #(
+	.USER_PROJECT_ID(USER_PROJECT_ID)
+    ) user_id_value (
+	`ifdef USE_POWER_PINS
+		.VPWR(vccd_core),
+		.VGND(vssd_core),
+	`endif
+	.mask_rev(mask_rev)
+    );
+
+    // Power-on-reset circuit
+    simple_por por (
+	`ifdef USE_POWER_PINS
+		.vdd3v3(vddio_core),
+		.vdd1v8(vccd_core),
+		.vss3v3(vssio_core),
+		.vss1v8(vssd_core),
+	`endif
+		.porb_h(porb_h),
+		.porb_l(porb_l),
+		.por_l(por_l)
+    );
+
+    // XRES (chip input pin reset) reset level converter
+    xres_buf rstb_level (
+	`ifdef USE_POWER_PINS
+		.VPWR(vddio_core),
+		.LVPWR(vccd_core),
+		.LVGND(vssd_core),
+		.VGND(vssio_core),
+	`endif
+		.A(rstb_h),
+		.X(rstb_l)
+    );
+
+    /* Spare logic for metal mask fixes */
+    // `define NUM_SPARE_BLOCKS (`MPRJ_IO_PADS+4)
+    `define NUM_SPARE_BLOCKS 4
+
+    wire [(27*`NUM_SPARE_BLOCKS)-1:0] spare_xz_nc;
+    wire [(4*`NUM_SPARE_BLOCKS)-1:0] spare_xi_nc;
+    wire [(1*`NUM_SPARE_BLOCKS)-1:0] spare_xib_nc;
+    wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xna_nc;
+    wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xno_nc;
+    wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xmx_nc;
+    wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xfq_nc;
+    wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xfqn_nc;
+
+    // Four spare logic blocks above the processor and one per GPIO
+    // control block.
+    spare_logic_block spare_logic [`NUM_SPARE_BLOCKS-1:0] (
+	`ifdef USE_POWER_PINS
+		.vccd(vccd_core),
+		.vssd(vssd_core),
+	`endif
+		.spare_xz(spare_xz_nc),
+		.spare_xi(spare_xi_nc),
+		.spare_xib(spare_xib_nc),
+		.spare_xna(spare_xna_nc),
+		.spare_xno(spare_xno_nc),
+		.spare_xmx(spare_xmx_nc),
+		.spare_xfq(spare_xfq_nc),
+		.spare_xfqn(spare_xfqn_nc)
+    );
+
+    `ifdef TOP_ROUTING
+    caravel_power_routing caravel_power_routing();
+    copyright_block copyright_block();
+    caravel_logo caravel_logo();
+    caravel_motto caravel_motto();
+    open_source open_source();
+    user_id_textblock user_id_textblock();
+    `endif
+
+endmodule
+// `default_nettype wire