diff --git a/Makefile b/Makefile
index df39874..b89e69f 100644
--- a/Makefile
+++ b/Makefile
@@ -13,24 +13,33 @@
 # limitations under the License.
 #
 # SPDX-License-Identifier: Apache-2.0
+MAKEFLAGS+=--warn-undefined-variables
 
 CARAVEL_ROOT?=$(PWD)/caravel
 PRECHECK_ROOT?=${HOME}/mpw_precheck
-SIM ?= RTL
-DUMP ?= OFF
+MCW_ROOT?=$(PWD)/mgmt_core_wrapper
+SIM?=RTL
+DUMP?=OFF
 RISC_CORE ?=0
 
+export SKYWATER_COMMIT=c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+export OPEN_PDKS_COMMIT=7519dfb04400f224f140749cda44ee7de6f5e095
+export PDK_MAGIC_COMMIT=7d601628e4e05fd17fcb80c3552dacb64e9f6e7b
+export OPENLANE_TAG=2022.02.23_02.50.41
+
 # Install lite version of caravel, (1): caravel-lite, (0): caravel
 CARAVEL_LITE?=1
 
-ifeq ($(CARAVEL_LITE),1) 
+MPW_TAG ?= mpw-5c
+
+ifeq ($(CARAVEL_LITE),1)
 	CARAVEL_NAME := caravel-lite
-	CARAVEL_REPO := https://github.com/efabless/caravel-lite 
-	CARAVEL_TAG := 'mpw-5a'
+	CARAVEL_REPO := https://github.com/efabless/caravel-lite
+	CARAVEL_TAG := $(MPW_TAG)
 else
 	CARAVEL_NAME := caravel
-	CARAVEL_REPO := https://github.com/efabless/caravel 
-	CARAVEL_TAG := 'mpw-5a'
+	CARAVEL_REPO := https://github.com/efabless/caravel
+	CARAVEL_TAG := $(MPW_TAG)
 endif
 
 # Install caravel as submodule, (1): submodule, (0): clone
@@ -51,60 +60,99 @@
 
 # Include Caravel Makefile Targets
 .PHONY: % : check-caravel
-%: 
+%:
 	export CARAVEL_ROOT=$(CARAVEL_ROOT) && $(MAKE) -f $(CARAVEL_ROOT)/Makefile $@
 
-# Verify Target for running simulations
-.PHONY: verify
-verify:
-	cd ./verilog/dv/ && \
-	export SIM=${SIM} DUMP=${DUMP} RISC_CORE=${RISC_CORE} && \
-		$(MAKE) -j$(THREADS)
+.PHONY: install
+install:
+	if [ -d "$(CARAVEL_ROOT)" ]; then\
+		echo "Deleting exisiting $(CARAVEL_ROOT)" && \
+		rm -rf $(CARAVEL_ROOT) && sleep 2;\
+	fi
+	echo "Installing $(CARAVEL_NAME).."
+	git clone -b $(CARAVEL_TAG) $(CARAVEL_REPO) $(CARAVEL_ROOT) --depth=1
 
 # Install DV setup
 .PHONY: simenv
 simenv:
 	docker pull riscduino/dv_setup:latest
 
-PATTERNS=$(shell cd verilog/dv && find * -maxdepth 0 -type d)
-DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
-TARGET_PATH=$(shell pwd)
-PDK_PATH=${PDK_ROOT}/sky130A
-VERIFY_COMMAND="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} DUMP=${DUMP} RISC_CORE=${RISC_CORE} && make"
-$(DV_PATTERNS): verify-% : ./verilog/dv/% check-coremark_repo check-riscv_comp_repo check-riscv_test_repo
-	docker run -v ${TARGET_PATH}:${TARGET_PATH} \
-                -e TARGET_PATH=${TARGET_PATH}  \
-		-v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \
-		-e CARAVEL_ROOT=${CARAVEL_ROOT} \
-                -u $(id -u $$USER):$(id -g $$USER) riscduino/dv_setup:mpw5 \
-                sh -c $(VERIFY_COMMAND)
-				
-# Openlane Makefile Targets
-BLOCKS = $(shell cd openlane && find * -maxdepth 0 -type d)
-.PHONY: $(BLOCKS)
-$(BLOCKS): %:
+.PHONY: setup
+setup: install check-env install_mcw pdk openlane
+
+# Openlane
+blocks=$(shell cd openlane && find * -maxdepth 0 -type d)
+.PHONY: $(blocks)
+$(blocks): % :
 	export CARAVEL_ROOT=$(CARAVEL_ROOT) && cd openlane && $(MAKE) $*
 
-# Install caravel
-.PHONY: install
-install:
-ifeq ($(SUBMODULE),1)
-	@echo "Installing $(CARAVEL_NAME) as a submodule.."
-# Convert CARAVEL_ROOT to relative path because .gitmodules doesn't accept '/'
-	$(eval CARAVEL_PATH := $(shell realpath --relative-to=$(shell pwd) $(CARAVEL_ROOT)))
-	@if [ ! -d $(CARAVEL_ROOT) ]; then git submodule add --name $(CARAVEL_NAME) $(CARAVEL_REPO) $(CARAVEL_PATH); fi
-	@git submodule update --init
-	@cd $(CARAVEL_ROOT); git checkout $(CARAVEL_BRANCH)
-	$(MAKE) simlink
-else
-	@echo "Installing $(CARAVEL_NAME).."
-	@git clone -b $(CARAVEL_TAG) $(CARAVEL_REPO) $(CARAVEL_ROOT)
-endif
+dv_patterns=$(shell cd verilog/dv && find * -maxdepth 0 -type d)
+dv-targets-rtl=$(dv_patterns:%=verify-%-rtl)
+dv-targets-gl=$(dv_patterns:%=verify-%-gl)
+dv-targets-gl-sdf=$(dv_patterns:%=verify-%-gl-sdf)
+
+TARGET_PATH=$(shell pwd)
+verify_command="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} DUMP=${DUMP} RISC_CORE=${RISC_CORE} && make"
+dv_base_dependencies= ./verilog/dv/% check-coremark_repo check-riscv_comp_repo check-riscv_test_repo
+docker_run_verify=\
+	docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \
+		-v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \
+		-e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} \
+		-e CARAVEL_ROOT=${CARAVEL_ROOT} \
+		-e TOOLS=/opt/riscv64i \
+		-e DESIGNS=$(TARGET_PATH) \
+		-e CORE_VERILOG_PATH=$(CARAVEL_ROOT)/mgmt_core_wrapper/verilog \
+		-e GCC_PREFIX=riscv64-unknown-elf \
+		-e MCW_ROOT=$(MCW_ROOT) \
+		-u $$(id -u $$USER):$$(id -g $$USER) riscduino/dv_setup:latest \
+		sh -c $(verify_command)
+
+.PHONY: harden
+harden: $(blocks)
+
+.PHONY: verify
+verify: $(dv-targets)
+
+$(dv-targets-rtl): SIM=RTL
+$(dv-targets-rtl): verify-%-rtl: $(dv_base_dependencies)
+	$(docker_run_verify)
+
+$(dv-targets-gl): SIM=GL
+$(dv-targets-gl): verify-%-gl: $(dv_base_dependencies)
+	$(docker_run_verify)
+
+$(dv-targets-gl-sdf): SIM=GL_SDF
+$(dv-targets-gl-sdf): verify-%-gl-sdf: $(dv_base_dependencies)
+	$(docker_run_verify)
+
+clean-targets=$(blocks:%=clean-%)
+.PHONY: $(clean-targets)
+$(clean-targets): clean-% :
+	rm -f ./verilog/gl/$*.v
+	rm -f ./spef/$*.spef
+	rm -f ./sdc/$*.sdc
+	rm -f ./sdf/$*.sdf
+	rm -f ./gds/$*.gds
+	rm -f ./mag/$*.mag
+	rm -f ./lef/$*.lef
+	rm -f ./maglef/*.maglef
+
+make_what=setup $(blocks) $(dv-targets-rtl) $(dv-targets-gl) $(dv-targets-gl-sdf) $(clean-targets)
+.PHONY: what
+what:
+	# $(make_what)
+
+# Install Openlane
+.PHONY: openlane
+openlane:
+	cd openlane && $(MAKE) openlane
+
+#### Not sure if the targets following are of any use
 
 # Create symbolic links to caravel's main files
 .PHONY: simlink
 simlink: check-caravel
-### Symbolic links relative path to $CARAVEL_ROOT 
+### Symbolic links relative path to $CARAVEL_ROOT
 	$(eval MAKEFILE_PATH := $(shell realpath --relative-to=openlane $(CARAVEL_ROOT)/openlane/Makefile))
 	$(eval PIN_CFG_PATH  := $(shell realpath --relative-to=openlane/user_project_wrapper $(CARAVEL_ROOT)/openlane/user_project_wrapper_empty/pin_order.cfg))
 	mkdir -p openlane
@@ -121,29 +169,26 @@
 
 # Uninstall Caravel
 .PHONY: uninstall
-uninstall: 
+uninstall:
 	rm -rf $(CARAVEL_ROOT)
 
-# Install Openlane
-.PHONY: openlane
-openlane: 
-	cd openlane && $(MAKE) openlane
 
 # Install Pre-check
 # Default installs to the user home directory, override by "export PRECHECK_ROOT=<precheck-installation-path>"
 .PHONY: precheck
 precheck:
-	@git clone --depth=1 --branch mpw-5 https://github.com/efabless/mpw_precheck.git $(PRECHECK_ROOT)
-	@docker pull efabless/mpw_precheck:mpw5
+	@git clone --depth=1 --branch mpw-5a https://github.com/efabless/mpw_precheck.git $(PRECHECK_ROOT)
+	@docker pull efabless/mpw_precheck:latest
 
 .PHONY: run-precheck
-run-precheck: check-precheck check-pdk check-caravel
+run-precheck: check-pdk check-precheck
 	$(eval INPUT_DIRECTORY := $(shell pwd))
 	cd $(PRECHECK_ROOT) && \
-	docker run -e INPUT_DIRECTORY=$(INPUT_DIRECTORY) -e PDK_ROOT=$(PDK_ROOT) -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) -v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) -v $(PDK_ROOT):$(PDK_ROOT) \
-	-u $(shell id -u $(USER)):$(shell id -g $(USER)) efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --pdk_root $(PDK_ROOT) --input_directory $(INPUT_DIRECTORY)"
+	docker run -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) -v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) -v $(PDK_ROOT):$(PDK_ROOT) -e INPUT_DIRECTORY=$(INPUT_DIRECTORY) -e PDK_ROOT=$(PDK_ROOT) \
+	-u $(shell id -u $(USER)):$(shell id -g $(USER)) efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --input_directory $(INPUT_DIRECTORY) --pdk_root $(PDK_ROOT)"
 
-# Clean 
+
+
 .PHONY: clean
 clean:
 	cd ./verilog/dv/ && \
@@ -208,5 +253,5 @@
 
 .PHONY: help
 help:
-	cd $(CARAVEL_ROOT) && $(MAKE) help 
+	cd $(CARAVEL_ROOT) && $(MAKE) help
 	@$(MAKE) -pRrq -f $(lastword $(MAKEFILE_LIST)) : 2>/dev/null | awk -v RS= -F: '/^# File/,/^# Finished Make data base/ {if ($$1 !~ "^[#.]") {print $$1}}' | sort | egrep -v -e '^[^[:alnum:]]' -e '^$@$$'
diff --git a/openlane/Makefile b/openlane/Makefile
index efd2b9b..e2e91a5 100644
--- a/openlane/Makefile
+++ b/openlane/Makefile
@@ -35,12 +35,12 @@
 	@sleep 1
 
 	@if [ -f ./$*/interactive.tcl ]; then\
-		docker run -it -v $(OPENLANE_ROOT):/openLANE_flow \
+		docker run -it  \
 		-v $(PWD)/..:/project \
 		-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
 		$(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_INTERACTIVE_COMMAND);\
 	else\
-		docker run -it -v $(OPENLANE_ROOT):/openLANE_flow \
+		docker run -it  \
 		-v $(PWD)/..:/project \
 		-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
 		$(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_BASIC_COMMAND);\
diff --git a/openlane/pinmux/config.tcl b/openlane/pinmux/config.tcl
index f082733..68f6db6 100755
--- a/openlane/pinmux/config.tcl
+++ b/openlane/pinmux/config.tcl
@@ -46,11 +46,12 @@
      $script_dir/../../verilog/rtl/pinmux/src/pinmux_reg.sv \
      $script_dir/../../verilog/rtl/pinmux/src/gpio_intr.sv  \
      $script_dir/../../verilog/rtl/pinmux/src/pwm.sv        \
+     $script_dir/../../verilog/rtl/pinmux/src/timer.sv        \
      $script_dir/../../verilog/rtl/lib/pulse_gen_type1.sv   \
      $script_dir/../../verilog/rtl/lib/pulse_gen_type2.sv   \
-     $script_dir/../../verilog/rtl/lib/ser_inf_32b.sv       \
      $script_dir/../../verilog/rtl/lib/registers.v          \
      $script_dir/../../verilog/rtl/lib/ctech_cells.sv     \
+     $script_dir/../../verilog/rtl/lib/reset_sync.sv     \
      "
 
 
diff --git a/openlane/pinmux/pin_order.cfg b/openlane/pinmux/pin_order.cfg
index 42c2cac..4c64993 100644
--- a/openlane/pinmux/pin_order.cfg
+++ b/openlane/pinmux/pin_order.cfg
@@ -91,38 +91,6 @@
 irq_lines\[2\]     
 irq_lines\[1\]     
 irq_lines\[0\]     
-fuse_mhartid\[31\] 
-fuse_mhartid\[30\] 
-fuse_mhartid\[29\] 
-fuse_mhartid\[28\] 
-fuse_mhartid\[27\] 
-fuse_mhartid\[26\] 
-fuse_mhartid\[25\] 
-fuse_mhartid\[24\] 
-fuse_mhartid\[23\] 
-fuse_mhartid\[22\] 
-fuse_mhartid\[21\] 
-fuse_mhartid\[20\] 
-fuse_mhartid\[19\] 
-fuse_mhartid\[18\] 
-fuse_mhartid\[17\] 
-fuse_mhartid\[16\] 
-fuse_mhartid\[15\] 
-fuse_mhartid\[14\] 
-fuse_mhartid\[13\] 
-fuse_mhartid\[12\] 
-fuse_mhartid\[11\] 
-fuse_mhartid\[10\] 
-fuse_mhartid\[9\] 
-fuse_mhartid\[8\] 
-fuse_mhartid\[7\] 
-fuse_mhartid\[6\] 
-fuse_mhartid\[5\] 
-fuse_mhartid\[4\] 
-fuse_mhartid\[3\] 
-fuse_mhartid\[2\] 
-fuse_mhartid\[1\] 
-fuse_mhartid\[0\] 
 
 cfg_cska_pinmux\[3\]  
 cfg_cska_pinmux\[2\]
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
index d0ccab1..097c11b 100755
--- a/openlane/wb_interconnect/config.tcl
+++ b/openlane/wb_interconnect/config.tcl
@@ -51,7 +51,7 @@
 set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
 
 set ::env(SYNTH_PARAMS) "CH_CLK_WD 4,\
-	                 CH_DATA_WD 69 \
+	                 CH_DATA_WD 37 \
 			 "
 
 set ::env(SYNTH_READ_BLACKBOX_LIB) 1
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg
index e722a83..f4bd653 100644
--- a/openlane/wb_interconnect/pin_order.cfg
+++ b/openlane/wb_interconnect/pin_order.cfg
@@ -147,39 +147,7 @@
 
 
 #W
-ch_data_out\[68\]   0750 0 2
-ch_data_out\[67\] 
-ch_data_out\[66\] 
-ch_data_out\[65\] 
-ch_data_out\[64\] 
-ch_data_out\[63\] 
-ch_data_out\[62\] 
-ch_data_out\[61\] 
-ch_data_out\[60\] 
-ch_data_out\[59\] 
-ch_data_out\[58\] 
-ch_data_out\[57\] 
-ch_data_out\[56\] 
-ch_data_out\[55\] 
-ch_data_out\[54\] 
-ch_data_out\[53\] 
-ch_data_out\[52\] 
-ch_data_out\[51\] 
-ch_data_out\[50\] 
-ch_data_out\[49\] 
-ch_data_out\[48\] 
-ch_data_out\[47\] 
-ch_data_out\[46\] 
-ch_data_out\[45\] 
-ch_data_out\[44\] 
-ch_data_out\[43\] 
-ch_data_out\[42\] 
-ch_data_out\[41\] 
-ch_data_out\[40\] 
-ch_data_out\[39\] 
-ch_data_out\[38\] 
-ch_data_out\[37\] 
-ch_data_out\[36\] 
+ch_data_out\[36\]   0750 0 2
 ch_data_out\[35\] 
 ch_data_out\[34\] 
 ch_data_out\[33\] 
@@ -732,39 +700,7 @@
 s1_wbd_ack_i        
 s1_wbd_cyc_o  
 
-ch_data_in\[68\]  1400 0 2  
-ch_data_in\[67\]
-ch_data_in\[66\]
-ch_data_in\[65\]
-ch_data_in\[64\]
-ch_data_in\[63\]
-ch_data_in\[62\]
-ch_data_in\[61\]
-ch_data_in\[60\]
-ch_data_in\[59\]
-ch_data_in\[58\]
-ch_data_in\[57\]
-ch_data_in\[56\]
-ch_data_in\[55\]
-ch_data_in\[54\]
-ch_data_in\[53\]
-ch_data_in\[52\]
-ch_data_in\[51\]
-ch_data_in\[50\]
-ch_data_in\[49\]
-ch_data_in\[48\]
-ch_data_in\[47\]
-ch_data_in\[46\]
-ch_data_in\[45\]
-ch_data_in\[44\]
-ch_data_in\[43\]
-ch_data_in\[42\]
-ch_data_in\[41\]
-ch_data_in\[40\]
-ch_data_in\[39\]
-ch_data_in\[38\]
-ch_data_in\[37\]
-ch_data_in\[36\]
+ch_data_in\[36\]  1400 0 2  
 ch_data_in\[35\]
 ch_data_in\[34\]
 ch_data_in\[33\]
diff --git a/openlane/ycr2_mintf/config.tcl b/openlane/ycr2_mintf/config.tcl
index 84b97fb..a829fc4 100644
--- a/openlane/ycr2_mintf/config.tcl
+++ b/openlane/ycr2_mintf/config.tcl
@@ -74,10 +74,11 @@
 ## Floorplan
 set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 800 700 "
+set ::env(DIE_AREA) "0 0 830 700 "
 
 set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
 set ::env(PL_TARGET_DENSITY) 0.36
+set ::env(CELL_PAD) "4"
 
 
 set ::env(RT_MAX_LAYER) {met4}
diff --git a/openlane/ycr2_mintf/pin_order.cfg b/openlane/ycr2_mintf/pin_order.cfg
index cf834b7..7cae03b 100644
--- a/openlane/ycr2_mintf/pin_order.cfg
+++ b/openlane/ycr2_mintf/pin_order.cfg
@@ -751,7 +751,8 @@
 
 
 #N
-core0_uid                000  0  2
+core0_uid\[1\]             000  0  2
+core0_uid\[0\]             
 cpu_core_rst_n_sync\[0\]   
 core0_imem_req_ack       
 core0_imem_req
@@ -980,7 +981,8 @@
 core0_debug\[1\]
 core0_debug\[0\]
 
-core1_uid             400 0 2
+core1_uid\[1\]       400 0 2
+core1_uid\[0\]        
 cpu_core_rst_n_sync\[1\]   
 core1_imem_req_ack    
 core1_imem_req
@@ -1279,4 +1281,7 @@
 rst_n_sync
 test_mode
 test_rst_n
-
+core2_uid\[1\]
+core2_uid\[0\]
+core3_uid\[1\]
+core3_uid\[0\]
diff --git a/openlane/ycr_core/pin_order.cfg b/openlane/ycr_core/pin_order.cfg
index c4f8e53..f8769e9 100644
--- a/openlane/ycr_core/pin_order.cfg
+++ b/openlane/ycr_core/pin_order.cfg
@@ -1,7 +1,8 @@
 #BUS_SORT
 #MANUAL_PLACE
 #S
-core_fuse_mhartid_i\[0\]   0000 00 2
+core_uid\[1\]   0000 00 2
+core_uid\[0\]   
 cpu_rst_n
 imem2core_req_ack_i
 core2imem_req_o
@@ -302,38 +303,6 @@
 test_rst_n
 
 
-core_fuse_mhartid_i\[31\]
-core_fuse_mhartid_i\[30\]
-core_fuse_mhartid_i\[29\]
-core_fuse_mhartid_i\[28\]
-core_fuse_mhartid_i\[27\]
-core_fuse_mhartid_i\[26\]
-core_fuse_mhartid_i\[25\]
-core_fuse_mhartid_i\[24\]
-core_fuse_mhartid_i\[23\]
-core_fuse_mhartid_i\[22\]
-core_fuse_mhartid_i\[21\]
-core_fuse_mhartid_i\[20\]
-core_fuse_mhartid_i\[19\]
-core_fuse_mhartid_i\[18\]
-core_fuse_mhartid_i\[17\]
-core_fuse_mhartid_i\[16\]
-core_fuse_mhartid_i\[15\]
-core_fuse_mhartid_i\[14\]
-core_fuse_mhartid_i\[13\]
-core_fuse_mhartid_i\[12\]
-core_fuse_mhartid_i\[11\]
-core_fuse_mhartid_i\[10\]
-core_fuse_mhartid_i\[9\]
-core_fuse_mhartid_i\[8\]
-core_fuse_mhartid_i\[7\]
-core_fuse_mhartid_i\[6\]
-core_fuse_mhartid_i\[5\]
-core_fuse_mhartid_i\[4\]
-core_fuse_mhartid_i\[3\]
-core_fuse_mhartid_i\[2\]
-core_fuse_mhartid_i\[1\]
-
 core_irq_lines_i\[15\]
 core_irq_lines_i\[14\]
 core_irq_lines_i\[13\]
diff --git a/signoff/pinmux/final_summary_report.csv b/signoff/pinmux/final_summary_report.csv
index 26af28c..eaac07f 100644
--- a/signoff/pinmux/final_summary_report.csv
+++ b/signoff/pinmux/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/pinmux,pinmux,pinmux,flow completed,0h10m48s0ms,0h7m26s0ms,43806.06060606061,0.2475,21903.030303030304,26.1,905.55,5421,0,0,0,0,0,0,0,-1,0,-1,-1,434767,55285,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,340566414.0,0.0,57.97,42.44,31.07,19.09,-1,3480,8519,562,5601,0,0,0,4063,123,107,40,77,933,109,14,285,1086,1034,11,314,3259,0,3573,100.0,10.0,10,AREA 0,4,50,1,100,100,0.3,0.3,sky130_fd_sc_hd,4,4
+0,/project/openlane/pinmux,pinmux,pinmux,flow completed,0h9m45s0ms,0h6m26s0ms,49349.494949494954,0.2475,24674.747474747477,29.39,954.58,6107,0,0,0,0,0,0,0,-1,0,-1,-1,458162,60438,-9.79,-17.09,-1,0.0,0.0,-11322.82,-19478.71,-1,0.0,0.0,363642601.0,0.0,61.71,47.76,26.72,20.99,-1,4043,9507,808,6272,0,0,0,4590,151,83,49,96,1013,154,18,283,1206,1171,12,314,3259,0,3573,100.0,10.0,10,AREA 0,4,50,1,100,100,0.3,0.3,sky130_fd_sc_hd,4,4
diff --git a/signoff/qspim_top/final_summary_report.csv b/signoff/qspim_top/final_summary_report.csv
index 498e1be..65d79bc 100644
--- a/signoff/qspim_top/final_summary_report.csv
+++ b/signoff/qspim_top/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/qspim_top,qspim_top,qspim_top,flow completed,0h14m56s0ms,0h11m42s0ms,65696.9696969697,0.2475,32848.48484848485,37.92,1024.62,8130,0,0,0,0,0,0,0,-1,0,-1,-1,419590,71747,-0.55,-5.04,-1,0.0,0.0,-21.45,-1943.78,-1,0.0,0.0,256460720.0,0.0,50.47,49.05,23.05,22.36,-1,7374,11038,803,4466,0,0,0,8348,263,96,195,114,1420,214,34,1460,1553,1517,17,388,3234,0,3622,100.0,10.0,10,AREA 0,4,50,1,100,100,0.42,0.3,sky130_fd_sc_hd,4,4
+0,/project/openlane/qspim_top,qspim_top,qspim_top,flow completed,0h12m26s0ms,0h9m19s0ms,65696.9696969697,0.2475,32848.48484848485,37.92,1104.07,8130,0,0,0,0,0,0,0,-1,0,-1,-1,419590,71747,-0.55,-5.04,-1,0.0,0.0,-21.45,-1943.78,-1,0.0,0.0,256460720.0,0.0,50.47,49.05,23.05,22.36,-1,7374,11038,803,4466,0,0,0,8348,263,96,195,114,1420,214,34,1460,1553,1517,17,388,3234,0,3622,100.0,10.0,10,AREA 0,4,50,1,100,100,0.42,0.3,sky130_fd_sc_hd,4,4
diff --git a/signoff/uart_i2cm_usb_spi_top/final_summary_report.csv b/signoff/uart_i2cm_usb_spi_top/final_summary_report.csv
index 13c3d45..0ddfd92 100644
--- a/signoff/uart_i2cm_usb_spi_top/final_summary_report.csv
+++ b/signoff/uart_i2cm_usb_spi_top/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/uart_i2cm_usb_spi_top,uart_i2c_usb_spi_top,uart_i2cm_usb_spi_top,flow completed,0h17m16s0ms,0h12m43s0ms,69285.71428571429,0.35,34642.857142857145,39.21,1441.0,12125,0,0,0,0,0,0,0,-1,0,-1,-1,594439,103896,0.0,0.0,0.0,0.0,-0.02,0.0,0.0,0.0,0.0,-0.02,369917177.0,0.0,51.11,51.47,19.26,22.98,-1,8702,13067,1552,5853,0,0,0,9824,392,189,256,272,2200,354,88,807,2409,2348,18,498,4643,0,5141,99.8003992015968,10.02,10,AREA 0,4,50,1,100,100,0.45,0.3,sky130_fd_sc_hd,4,4
+0,/project/openlane/uart_i2cm_usb_spi_top,uart_i2c_usb_spi_top,uart_i2cm_usb_spi_top,flow completed,0h30m53s0ms,0h23m11s0ms,69285.71428571429,0.35,34642.857142857145,39.21,1367.28,12125,0,0,0,0,0,0,0,-1,0,-1,-1,594439,103896,0.0,0.0,0.0,0.0,-0.02,0.0,0.0,0.0,0.0,-0.02,369917177.0,0.0,51.11,51.47,19.26,22.98,-1,8702,13067,1552,5853,0,0,0,9824,392,189,256,272,2200,354,88,807,2409,2348,18,498,4643,0,5141,99.8003992015968,10.02,10,AREA 0,4,50,1,100,100,0.45,0.3,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 989b5d9..9cd6bea 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,0h45m53s0ms,0h5m7s0ms,-2.0,-1,-1,-1,604.22,11,0,0,0,0,0,0,-1,0,0,-1,-1,2428216,19156,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,8.39,11.89,3.14,2.75,0.0,318,3364,318,3364,0,0,0,11,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,100,0.55,0.3,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,0h48m45s0ms,0h5m14s0ms,-2.0,-1,-1,-1,602.58,11,0,0,0,0,0,0,-1,0,0,-1,-1,2385046,17217,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,8.06,11.83,2.96,3.32,0.0,317,3274,317,3274,0,0,0,11,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,100,0.55,0.3,sky130_fd_sc_hd,4,0
diff --git a/signoff/wb_host/final_summary_report.csv b/signoff/wb_host/final_summary_report.csv
index 54ac79b..898c873 100644
--- a/signoff/wb_host/final_summary_report.csv
+++ b/signoff/wb_host/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_host,wb_host,wb_host,flow completed,0h7m24s0ms,0h5m1s0ms,61297.47899159664,0.14875,30648.73949579832,37.15,769.93,4559,0,0,0,0,0,0,0,12,0,0,-1,209244,37027,0.0,-0.21,0.0,0.0,0.0,0.0,-17.73,0.0,0.0,0.0,158619913.0,0.0,46.06,48.87,4.05,12.29,-1,3513,6206,1009,3558,0,0,0,3833,380,52,75,186,650,146,23,466,1022,997,11,296,1950,0,2246,100.0,10.0,10,AREA 0,4,50,1,100,100,0.38,0.3,sky130_fd_sc_hd,4,4
+0,/project/openlane/wb_host,wb_host,wb_host,flow completed,0h5m10s0ms,0h3m26s0ms,61700.84033613445,0.14875,30850.420168067227,37.22,773.21,4589,0,0,0,0,0,0,0,11,0,0,-1,205225,36945,0.0,-0.19,0.0,0.0,0.0,0.0,-23.16,0.0,0.0,0.0,155719018.0,0.0,46.7,45.31,3.63,15.99,-1,3577,6294,1049,3622,0,0,0,3856,373,52,77,183,651,146,23,461,1023,1001,12,296,1950,0,2246,100.0,10.0,10,AREA 0,4,50,1,100,100,0.38,0.3,sky130_fd_sc_hd,4,4
diff --git a/signoff/wb_interconnect/final_summary_report.csv b/signoff/wb_interconnect/final_summary_report.csv
index c0d17f6..0106066 100644
--- a/signoff/wb_interconnect/final_summary_report.csv
+++ b/signoff/wb_interconnect/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow completed,0h46m54s0ms,0h40m26s0ms,37937.5,0.5760000000000001,18968.75,16.98,1608.16,10926,0,0,0,0,0,0,0,-1,0,-1,-1,1075525,94792,-1.53,-3.34,-1,-2.98,-3.4,-106.67,-233.97,-1,-293.74,-303.87,834639052.0,0.0,25.33,47.4,4.97,27.65,-1,3846,12928,637,9716,0,0,0,5341,269,12,304,131,626,98,13,1402,1753,1688,16,1306,7532,0,8838,74.6268656716418,13.4,10,AREA 0,2,50,1,153.6,153.18,0.2,0,sky130_fd_sc_hd,10,4
+0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow completed,0h39m31s0ms,0h29m40s0ms,37826.38888888888,0.5760000000000001,18913.19444444444,16.95,1333.09,10894,0,0,0,0,0,0,0,-1,0,-1,-1,1010027,91907,-1.53,-3.35,-1,-3.07,-3.34,-106.67,-240.35,-1,-319.27,-324.23,794830726.0,0.0,23.63,45.8,2.76,26.56,-1,3846,12864,637,9652,0,0,0,5341,269,12,304,131,626,98,13,1402,1753,1688,16,1306,7532,0,8838,74.96251874062969,13.34,10,AREA 0,2,50,1,153.6,153.18,0.2,0,sky130_fd_sc_hd,10,4
diff --git a/signoff/ycr2_mintf/final_summary_report.csv b/signoff/ycr2_mintf/final_summary_report.csv
index 098dfda..3115988 100644
--- a/signoff/ycr2_mintf/final_summary_report.csv
+++ b/signoff/ycr2_mintf/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/ycr2_mintf,ycr2_mintf,ycr2_mintf,flow_completed,0h55m36s,-1,59950.0,0.56,29975.0,34.63,1318.32,16786,0,-1,-1,-1,-1,0,0,-1,0,0,-1,1417781,196456,-10.62,-28.82,-1,0.0,-1,-17949.18,-46631.03,-1,0.0,-1,1008802804.0,17.72,59.07,49.55,18.1,3.02,-1,12554,26414,1451,14949,0,0,0,15249,0,0,0,0,0,0,0,4,4400,4298,34,498,7655,0,8153,90.9090909090909,11,10,AREA 0,4,50,1,153.6,153.18,0.36,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/ycr2_mintf,ycr2_mintf,ycr2_mintf,flow_completed,0h48m5s,-1,57793.4595524957,0.581,28896.72977624785,33.36,1340.78,16789,0,-1,-1,-1,-1,0,0,-1,0,0,-1,1408277,195540,-10.62,-28.88,-1,0.0,-1,-17949.18,-47210.0,-1,0.0,-1,1013309764.0,10.14,57.98,47.13,16.49,2.06,-1,12552,26416,1453,14955,0,0,0,15245,0,0,0,0,0,0,0,4,4400,4298,34,498,7906,0,8404,90.9090909090909,11,10,AREA 0,4,50,1,153.6,153.18,0.36,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/ycr_core/final_summary_report.csv b/signoff/ycr_core/final_summary_report.csv
index e9b99da..bbb41ad 100644
--- a/signoff/ycr_core/final_summary_report.csv
+++ b/signoff/ycr_core/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/ycr_core,ycr_core_top,ycr_core,flow completed,0h21m21s0ms,0h12m57s0ms,68215.12605042018,0.595,34107.56302521009,34.04,2244.03,20294,0,0,0,0,0,0,0,56,0,0,-1,1315671,191055,-23.39,-45.73,-1,0.0,0.0,-25027.54,-49475.34,-1,0.0,0.0,971204312.0,0.0,59.17,62.72,31.36,43.72,-1,16419,22655,510,6646,0,0,0,19197,693,255,524,595,2870,895,265,4812,2529,2405,42,608,8109,0,8717,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.36,0.3,sky130_fd_sc_hd,4,4
+0,/project/openlane/ycr_core,ycr_core_top,ycr_core,flow completed,0h38m41s0ms,0h24m58s0ms,67717.64705882354,0.595,33858.82352941177,33.84,2318.47,20146,0,0,0,0,0,0,0,20,0,0,-1,1259376,186378,-23.43,-45.2,-1,0.0,0.0,-25026.44,-48972.85,-1,0.0,0.0,953528811.0,0.0,58.17,60.96,27.8,39.99,-1,16362,22599,511,6648,0,0,0,19139,686,255,523,601,2871,897,265,4812,2499,2405,43,608,8109,0,8717,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.36,0.3,sky130_fd_sc_hd,4,4
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index ddbf7d0..384be25 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@
 .SUFFIXES:
 .SILENT: clean all
 
-PATTERNS = wb_port risc_boot user_risc_boot user_uart user_qspi user_i2cm riscv_regress user_basic user_usb user_uart_master uart_master
+PATTERNS = wb_port risc_boot user_risc_boot user_uart user_qspi user_i2cm riscv_regress user_basic user_usb user_pwm user_timer user_uart_master uart_master
 
 all:  ${PATTERNS}
 	for i in ${PATTERNS}; do \
diff --git a/verilog/dv/c_func/inc/pwm.h b/verilog/dv/c_func/inc/pwm.h
new file mode 100644
index 0000000..580a9a8
--- /dev/null
+++ b/verilog/dv/c_func/inc/pwm.h
@@ -0,0 +1,8 @@
+
+void	InitTimers         ();
+void	InitTimersSafe     ();     //doesn't init timers responsible for time keeping functions
+void	pwmWrite           (uint8_t pin, uint8_t val);
+void	pwmWriteHR         (uint8_t pin, uint16_t val);   //accepts a 16 bit value and maps it down to the timer for maximum resolution
+bool	SetPinFrequency    (int8_t pin, uint32_t frequency);
+bool	SetPinFrequencySafe(int8_t pin, uint32_t frequency);	//does not set timers responsible for time keeping functions
+float	GetPinResolution(uint8_t pin);  //gets the PWM resolution of a pin in base 2, 0 is returned if the pin is not connected to a timer
diff --git a/verilog/dv/c_func/inc/user_reg_map.h b/verilog/dv/c_func/inc/user_reg_map.h
new file mode 100644
index 0000000..4508fb2
--- /dev/null
+++ b/verilog/dv/c_func/inc/user_reg_map.h
@@ -0,0 +1,38 @@
+
+
+//-------------------------------------
+// PinMux Register
+// ------------------------------------
+#define reg_pinmux_chip_id           (*(volatile uint32_t*)0x30020000)  // reg_0  - Chip ID
+#define reg_pinmux_gbl_cfg0          (*(volatile uint32_t*)0x30020004)  // reg_1  - Global Config-2
+#define reg_pinmux_gbl_cfg1          (*(volatile uint32_t*)0x30020008)  // reg_2  - Global Config-1
+#define reg_pinmux_gbl_intr_msk      (*(volatile uint32_t*)0x3002000C)  // reg_3  - Global Interrupt Mask
+#define reg_pinmux_gbl_intr          (*(volatile uint32_t*)0x30020010)  // reg_4  - Global Interrupt
+#define reg_pinmux_gpio_idata        (*(volatile uint32_t*)0x30020014)  // reg_5  - GPIO Data In
+#define reg_pinmux_gpio_odata        (*(volatile uint32_t*)0x30020018)  // reg_6  - GPIO Data Out
+#define reg_pinmux_gpio_dsel         (*(volatile uint32_t*)0x3002001C)  // reg_7  - GPIO Direction Select
+#define reg_pinmux_gpio_type         (*(volatile uint32_t*)0x30020020)  // reg_8  - GPIO TYPE - Static/Waveform
+#define reg_pinmux_gpio_intr_stat    (*(volatile uint32_t*)0x30020024)  // reg_9  - GPIO Interrupt status
+#define reg_pinmux_gpio_intr_clr     (*(volatile uint32_t*)0x30020024)  // reg_9  - GPIO Interrupt Clear
+#define reg_pinmux_gpio_intr_set     (*(volatile uint32_t*)0x30020028)  // reg_10 - GPIO Interrupt Set
+#define reg_pinmux_gpio_intr_mask    (*(volatile uint32_t*)0x3002002C)  // reg_11 - GPIO Interrupt Mask
+#define reg_pinmux_gpio_pos_intr     (*(volatile uint32_t*)0x30020030)  // reg_12 - GPIO Posedge Interrupt
+#define reg_pinmux_gpio_neg_intr     (*(volatile uint32_t*)0x30020034)  // reg_13 - GPIO Neg Interrupt
+#define reg_pinmux_gpio_multi_func   (*(volatile uint32_t*)0x30020038)  // reg_14 - GPIO Multi Function
+#define reg_pinmux_soft_reg_0        (*(volatile uint32_t*)0x3002003C)  // reg_15 - Soft Register
+#define reg_pinmux_cfg_pwm0          (*(volatile uint32_t*)0x30020040)  // reg_16 - PWM Reg-0
+#define reg_pinmux_cfg_pwm1          (*(volatile uint32_t*)0x30020044)  // reg_17 - PWM Reg-1
+#define reg_pinmux_cfg_pwm2          (*(volatile uint32_t*)0x30020048)  // reg_18 - PWM Reg-2
+#define reg_pinmux_cfg_pwm3          (*(volatile uint32_t*)0x3002004C)  // reg_19 - PWM Reg-3
+#define reg_pinmux_cfg_pwm4          (*(volatile uint32_t*)0x30020050)  // reg_20 - PWM Reg-4
+#define reg_pinmux_cfg_pwm5          (*(volatile uint32_t*)0x30020054)  // reg_21 - PWM Reg-5
+#define reg_pinmux_soft_reg_1        (*(volatile uint32_t*)0x30020058)  // reg_22 - Sof Register
+#define reg_pinmux_soft_reg_2        (*(volatile uint32_t*)0x3002005C)  // reg_23 - Sof Register
+#define reg_pinmux_soft_reg_3        (*(volatile uint32_t*)0x30020060)  // reg_24 - Sof Register
+#define reg_pinmux_soft_reg_4        (*(volatile uint32_t*)0x30020064)  // reg_25 - Sof Register
+#define reg_pinmux_soft_reg_5        (*(volatile uint32_t*)0x30020068)  // reg_26 - Sof Register
+#define reg_pinmux_soft_reg_6        (*(volatile uint32_t*)0x3002006C)  // reg_27 - Sof Register
+#define reg_pinmux_cfg_timer0        (*(volatile uint32_t*)0x30020070)  // reg_28 - Timer-0
+#define reg_pinmux_cfg_timer1        (*(volatile uint32_t*)0x30020074)  // reg_28 - Timer-1
+#define reg_pinmux_cfg_timer2        (*(volatile uint32_t*)0x30020078)  // reg_28 - Timer-2
+
diff --git a/verilog/dv/risc_boot/Makefile b/verilog/dv/risc_boot/Makefile
index 2aab7ff..8df6ef7 100644
--- a/verilog/dv/risc_boot/Makefile
+++ b/verilog/dv/risc_boot/Makefile
@@ -14,100 +14,225 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 
-## PDK 
-PDK_PATH = $(PDK_ROOT)/sky130A
 
-## Caravel Pointers
-CARAVEL_ROOT ?= ../../../caravel
-CARAVEL_PATH ?= $(CARAVEL_ROOT)
-CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
-CARAVEL_VERILOG_PATH  = $(CARAVEL_PATH)/verilog
-CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
-CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+ 
+PWDD := $(shell pwd)
+BLOCKS := $(shell basename $(PWDD))
 
-## User Project Pointers
-UPRJ_VERILOG_PATH ?= ../../../verilog
-UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
-UPRJ_BEHAVIOURAL_MODELS = ../model
-UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr2c/src/includes
-UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
-UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
-UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
-UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include
+# ---- Include Partitioned Makefiles ----
 
-## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware
-## RISCV GCC 
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-GCC64_PREFIX?=riscv64-unknown-elf
+CONFIG = caravel_user_project
 
-## Simulation mode: RTL/GL
-SIM_DEFINES = -DFUNCTIONAL -DSIM
+########################################################
+#include $(MCW_ROOT)/verilog/dv/make/env.makefile
+########################################################
+#######################################################################
+## Global Environment Variables for local repo  
+#######################################################################
+
+export PDK_PATH =      $(PDK_ROOT)/sky130A
+export VIP_PATH =      $(CORE_VERILOG_PATH)/dv/vip
+export FIRMWARE_PATH = $(CORE_VERILOG_PATH)/dv/firmware
+
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+export CARAVEL_VERILOG_PATH ?=  $(CARAVEL_ROOT)/verilog
+export CORE_VERILOG_PATH    ?=  $(CARAVEL_ROOT)/mgmt_core_wrapper/verilog
+export USER_PROJECT_VERILOG ?=  $(DESIGNS)/verilog
+
+export CARAVEL_PATH = $(CARAVEL_VERILOG_PATH)
+export VERILOG_PATH = $(CORE_VERILOG_PATH)
+
+#######################################################################
+## Compiler Information 
+#######################################################################
+
+export TOOLS     ?=  /opt/riscv64i 
+export GCC_PATH  ?=  $(TOOLS)/bin
+export GCC_PREFIX?=  riscv32-unknown-linux-gnu
+
+
+############## USER SPECIFIC DEFINE ##################
+
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+
+######################################################
+
+
+
+
+
+########################################################
+#include $(MCW_ROOT)/verilog/dv/make/var.makefile
+########################################################
+
+CPU=vexriscv
+CPUFAMILY=riscv
+CPUFLAGS=-march=rv32i      -mabi=ilp32 -D__vexriscv__
+CPUENDIANNESS=little
+CLANG=0
+
+
+######################################################
+# include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
+######################################################
+
+ifeq ($(CPU),picorv32)
+	LINKER_SCRIPT=$(FIRMWARE_PATH)/sections.lds
+	SOURCE_FILES=$(FIRMWARE_PATH)/start.s 
+	VERILOG_FILES=
+endif
+
+ifeq ($(CPU),ibex)
+	LINKER_SCRIPT=$(FIRMWARE_PATH)/link_ibex.ld
+	SOURCE_FILES=$(FIRMWARE_PATH)/crt0_ibex.S $(FIRMWARE_PATH)/simple_system_common.c
+# 	VERILOG_FILES=../ibex/*
+	VERILOG_FILES=
+endif
+
+ifeq ($(CPU),vexriscv)
+# 	LINKER_SCRIPT=$(FIRMWARE_PATH)/sections_vexriscv.lds
+# 	SOURCE_FILES=$(FIRMWARE_PATH)/start_caravel_vexriscv.s
+	LINKER_SCRIPT=$(FIRMWARE_PATH)/sections.lds
+	SOURCE_FILES=$(FIRMWARE_PATH)/crt0_vex.S $(FIRMWARE_PATH)/isr.c
+	VERILOG_FILES=
+endif
+
+
+
+#####################################################
+#include $(MCW_ROOT)/verilog/dv/make/sim.makefile
+######################################################
+
+export IVERILOG_DUMPER = fst
+
+# RTL/GL/GL_SDF
 SIM?=RTL
 DUMP?=OFF
 
+
 .SUFFIXES:
 
-PATTERN = risc_boot
 
-all:  ${PATTERN:=.vcd}
+all:  ${BLOCKS:=.vcd} ${BLOCKS:=.lst}
 
-hex:  ${PATTERN:=.hex}
+hex:  ${BLOCKS:=.hex}
 
-vvp:  ${PATTERN:=.vvp}
+#.SUFFIXES:
 
-%.vvp: %_tb.v %.hex
-	${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -c -I./ -I$(YIFIVE_FIRMWARE_PATH)  user_uart.c -o user_uart.o
-	${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH)  $(YIFIVE_FIRMWARE_PATH)/crt.S -o crt.o
-	${GCC64_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -T $(YIFIVE_FIRMWARE_PATH)/link.ld user_uart.o crt.o -nostartfiles -nostdlib -lc -lgcc -o user_uart.elf -N
-	${GCC64_PREFIX}-objcopy -O verilog user_uart.elf user_uart.hex
-	${GCC64_PREFIX}-objdump -D user_uart.elf > user_uart.dump
-	rm crt.o user_uart.o
-ifeq ($(SIM),RTL)
-   ifeq ($(DUMP),OFF)
-	iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH)  \
-	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
-	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
-	-I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \
-	$< -o $@ 
-   else
-	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH)  \
-	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
-	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
-	-I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \
-	$< -o $@ 
-   endif
-else  
-	iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
-	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH)   -I $(UPRJ_VERILOG_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
-	$< -o $@ 
-endif
+##############################################################################
+# Comiple firmeware
+##############################################################################
+%.elf: %.c $(LINKER_SCRIPT) $(SOURCE_FILES)
+	${GCC_PATH}/${GCC_PREFIX}-gcc -g \
+	-I$(FIRMWARE_PATH) \
+	-I$(VERILOG_PATH)/dv/generated \
+	-I$(VERILOG_PATH)/dv/ \
+	-I$(VERILOG_PATH)/common \
+	  $(CPUFLAGS) \
+	-Wl,-Bstatic,-T,$(LINKER_SCRIPT),--strip-debug \
+	-ffreestanding -nostdlib -o $@ $(SOURCE_FILES) $<
 
-%.vcd: %.vvp
-	vvp $<
-
-%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s
-	${GCC64_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
+%.lst: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objdump -d -S $< > $@
 
 %.hex: %.elf
-	${GCC64_PREFIX}-objcopy -O verilog $< $@ 
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
 	# to fix flash base address
-	sed -i 's/@10000000/@00000000/g' $@
+	sed -ie 's/@10/@00/g' $@
 
 %.bin: %.elf
 	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+	
+	
+##############################################################################
+# Runing the simulations
+##############################################################################
+
+%.vvp: %_tb.v %.hex
+	${GCC_PATH}/${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -c -I./ -I$(YIFIVE_FIRMWARE_PATH)  user_uart.c -o user_uart.o
+	${GCC_PATH}/${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH)  $(YIFIVE_FIRMWARE_PATH)/crt.S -o crt.o
+	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -T $(YIFIVE_FIRMWARE_PATH)/link.ld user_uart.o crt.o -nostartfiles -nostdlib -lc -lgcc -o user_uart.elf -N
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog user_uart.elf user_uart.hex
+	${GCC_PATH}/${GCC_PREFIX}-objdump -D user_uart.elf > user_uart.dump
+	rm crt.o user_uart.o
+
+## RTL
+ifeq ($(SIM),RTL)
+   ifeq ($(DUMP),OFF)
+	iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+        -f$(VERILOG_PATH)/includes/includes.rtl.caravel \
+        -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $<
+    else  
+	iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+        -f$(VERILOG_PATH)/includes/includes.rtl.caravel \
+        -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $<
+   endif
+endif 
+
+## GL
+ifeq ($(SIM),GL)
+    ifeq ($(CONFIG),caravel_user_project)
+		iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+        -f$(VERILOG_PATH)/includes/includes.gl.caravel \
+        -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $<
+    else
+		iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+        -f$(VERILOG_PATH)/includes/includes.gl.$(CONFIG) \
+		-f$(CARAVEL_PATH)/gl/__user_project_wrapper.v -o $@ $<
+    endif
+endif 
+
+## GL+SDF
+ifeq ($(SIM),GL_SDF)
+    ifeq ($(CONFIG),caravel_user_project)
+		cvc64  +interp \
+		+define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY +define+ENABLE_SDF \
+		+change_port_type +dump2fst +fst+parallel2=on   +nointeractive +notimingchecks +mipdopt \
+		-f $(VERILOG_PATH)/includes/includes.gl+sdf.caravel \
+		-f $(USER_PROJECT_VERILOG)/includes/includes.gl+sdf.$(CONFIG) $<
+	else
+		cvc64  +interp \
+		+define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY +define+ENABLE_SDF \
+		+change_port_type +dump2fst +fst+parallel2=on   +nointeractive +notimingchecks +mipdopt \
+		-f $(VERILOG_PATH)/includes/includes.gl+sdf.$(CONFIG) \
+		-f $CARAVEL_PATH/gl/__user_project_wrapper.v $<
+    endif
+endif
+
+%.vcd: %.vvp
+	vvp  $<
+
+# twinwave: RTL-%.vcd GL-%.vcd
+#     twinwave RTL-$@ * + GL-$@ *
+
+check-env:
+ifndef PDK_ROOT
+	$(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+	$(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+	$(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+
 
 # ---- Clean ----
 
 clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump
+	\rm  -f *.elf *.hex *.bin *.vvp *.log *.vcd *.lst *.hexe
 
 .PHONY: clean hex all
+
+
+
+
+
+
diff --git a/verilog/dv/risc_boot/risc_boot.c b/verilog/dv/risc_boot/risc_boot.c
index 3e42aaa..bc41e1b 100644
--- a/verilog/dv/risc_boot/risc_boot.c
+++ b/verilog/dv/risc_boot/risc_boot.c
@@ -16,29 +16,13 @@
  */
 
 // This include is relative to $CARAVEL_PATH (see Makefile)
-#include "verilog/dv/caravel/defs.h"
-#include "verilog/dv/caravel/stub.c"
+#include <defs.h>
+#include <stub.c>
+#include "../c_func/inc/user_reg_map.h"
 
 // User Project Slaves (0x3000_0000)
 
-#define reg_mprj_wbhost_reg0 (*(volatile uint32_t*)0x30800000)
-
-#define reg_mprj_globl_reg0  (*(volatile uint32_t*)0x30020000)
-#define reg_mprj_globl_reg1  (*(volatile uint32_t*)0x30020004)
-#define reg_mprj_globl_reg2  (*(volatile uint32_t*)0x30020008)
-#define reg_mprj_globl_reg3  (*(volatile uint32_t*)0x3002000C)
-#define reg_mprj_globl_reg4  (*(volatile uint32_t*)0x30020010)
-#define reg_mprj_globl_reg5  (*(volatile uint32_t*)0x30020014)
-#define reg_mprj_globl_reg6  (*(volatile uint32_t*)0x30020018)
-#define reg_mprj_globl_reg7  (*(volatile uint32_t*)0x3002001C)
-#define reg_mprj_globl_reg8  (*(volatile uint32_t*)0x30020020)
-#define reg_mprj_globl_reg9  (*(volatile uint32_t*)0x30020024)
-#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x30020028)
-#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x3002002C)
-#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x30020030)
-#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x30020034)
-#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x30020038)
-#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x3002003C)
+#define reg_mprj_wbhost_reg0 (*(volatile uint32_t*)0x30080000)
 
 #define reg_mprj_uart_reg0 (*(volatile uint32_t*)0x30010000)
 #define reg_mprj_uart_reg1 (*(volatile uint32_t*)0x30010004)
@@ -52,7 +36,6 @@
 
 #define GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP   0x1C00
 
-#define SC_SIM_OUTPORT (0xf0000000)
 
 /*
          RiscV Hello World test.
@@ -80,38 +63,36 @@
 	Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
 	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
 	| 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
-
-	Input: 0000_0001_0000_1111 (0x1800) = GPIO_MODE_USER_STD_BIDIRECTIONAL
-	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
-	| 110    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 0     | 0       |
 	*/
 
 	/* Set up the housekeeping SPI to be connected internally so	*/
 	/* that external pin changes don't affect it.			*/
 
-	reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
+    reg_spi_enable = 1;
+    reg_wb_enable = 1;
+	// reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
                                         // connect to housekeeping SPI
 
 	// Connect the housekeeping SPI to the SPI master
 	// so that the CSB line is not left floating.  This allows
 	// all of the GPIO pins to be used for user functions.
-        reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
 
+    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
 
      /* Apply configuration */
     reg_mprj_xfer = 1;
@@ -178,11 +159,11 @@
 
 
     // Remove All Reset
-    reg_mprj_globl_reg2 = 0x11F;
+    reg_pinmux_gbl_cfg0 = 0x11F;
 
     // Enable UART Multi Functional Ports
 
-    reg_mprj_globl_reg14 = 0x100;
+    reg_pinmux_gpio_multi_func = 0x100;
 
     // configure the user uart
     reg_mprj_uart_reg0  = 0x7;
diff --git a/verilog/dv/risc_boot/risc_boot_tb.v b/verilog/dv/risc_boot/risc_boot_tb.v
index 766e403..e879f99 100644
--- a/verilog/dv/risc_boot/risc_boot_tb.v
+++ b/verilog/dv/risc_boot/risc_boot_tb.v
@@ -71,13 +71,6 @@
 
 `timescale 1 ns / 1 ps
 
-`define FULL_CHIP_SIM
-
-`include "s25fl256s.sv"
-`include "uprj_netlists.v"
-`include "caravel_netlists.v"
-`include "spiflash.v"
-`include "mt48lc8m8a2.v"
 `include "uart_agent.v"
 
 module risc_boot_tb;
@@ -133,15 +126,35 @@
         begin
            $dumpfile("simx.vcd");
            $dumpvars(1,risc_boot_tb);
-           $dumpvars(1,risc_boot_tb.u_spi_flash_256mb);
+           //$dumpvars(1,risc_boot_tb.u_spi_flash_256mb);
            //$dumpvars(2,risc_boot_tb.uut);
-           $dumpvars(4,risc_boot_tb.uut.mprj);
-           $dumpvars(0,risc_boot_tb.tb_uart);
+           $dumpvars(1,risc_boot_tb.uut.mprj);
+           $dumpvars(0,risc_boot_tb.uut.mprj.u_wb_host);
+           $dumpvars(1,risc_boot_tb.uut.mprj.u_riscv_top);
+           //$dumpvars(0,risc_boot_tb.tb_uart);
            //$dumpvars(0,risc_boot_tb.u_user_spiflash);
 	   $display("Waveform Dump started");
         end
         `endif
 
+	initial begin
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (80) begin
+			repeat (2000) @(posedge clock);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		$display ("##########################################################");
+		`ifdef GL
+			$display ("Monitor: Timeout, Test Risc Boot (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test Risc Boot (RTL) Failed");
+		`endif
+		$display ("##########################################################");
+		$display("%c[0m",27);
+		$finish;
+	end
 
         initial
         begin
@@ -156,40 +169,37 @@
         
            #200; // Wait for reset removal
 
-           fork
-	   begin
-          
-	      // Wait for Managment core to boot up 
-	      wait(checkbits == 16'h AB60);
-	      $display("Monitor: Test User Risc Boot Started");
-       
-	      // Wait for user risc core to boot up 
-              repeat (30000) @(posedge clock);  
-              tb_uart.uart_init;
-              tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, 
-                                             uart_stick_parity, uart_timeout, uart_divisor);
-              
-              for (i=0; i<40; i=i+1)
-              	uart_write_data[i] = $random;
-              
-              
-              
-              fork
-                 begin
-                    for (i=0; i<40; i=i+1)
-                    begin
-                      $display ("\n... UART Agent Writing char %x ...", uart_write_data[i]);
-                       tb_uart.write_char (uart_write_data[i]);
-                    end
-                 end
-              
-                 begin
-                    for (j=0; j<40; j=j+1)
-                    begin
-                      tb_uart.read_char_chk(uart_write_data[j]);
-                    end
-                 end
-                 join
+		// Wait for Managment core to boot up 
+		wait(checkbits == 16'h AB60);
+		$display("Monitor: Test User Risc Boot Started");
+
+		// Wait for user risc core to boot up 
+		repeat (50000) @(posedge clock);  
+		tb_uart.uart_init;
+		tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, 
+					     uart_stick_parity, uart_timeout, uart_divisor);
+
+		for (i=0; i<40; i=i+1)
+		uart_write_data[i] = $random;
+
+
+
+		fork
+		 begin
+		    for (i=0; i<40; i=i+1)
+		    begin
+		      $display ("\n... UART Agent Writing char %x ...", uart_write_data[i]);
+		       tb_uart.write_char (uart_write_data[i]);
+		    end
+		 end
+
+		 begin
+		    for (j=0; j<40; j=j+1)
+		    begin
+		      tb_uart.read_char_chk(uart_write_data[j]);
+		    end
+		 end
+		 join
               
                  #100
                  tb_uart.report_status(uart_rx_nu, uart_tx_nu);
@@ -204,28 +214,19 @@
                  if(uart_rx_nu != 40) test_fail = 1;
                  if(tb_uart.err_cnt != 0) test_fail = 1;
         
-	      end
-	      begin
-                   // Loop for TimeOut
-                   repeat (60000) @(posedge clock);
-                		// $display("+1000 cycles");
-                   test_fail = 1;
-              end
-              join_any
-              disable fork; //disable pending fork activity
 
               $display("###################################################");
               if(test_fail == 0) begin
                  `ifdef GL
-                     $display("Monitor: Standalone User UART Test (GL) Passed");
+                     $display("Monitor: Standalone User Risc Boot Test (GL) Passed");
                  `else
-                     $display("Monitor: Standalone User UART Test (RTL) Passed");
+                     $display("Monitor: Standalone User Risc Boot Test (RTL) Passed");
                  `endif
               end else begin
                   `ifdef GL
-                      $display("Monitor: Standalone User UART Test (GL) Failed");
+                      $display("Monitor: Standalone User Risc Boot Test (GL) Failed");
                   `else
-                      $display("Monitor: Standalone User UART Test (RTL) Failed");
+                      $display("Monitor: Standalone User Risc Boot Test (RTL) Failed");
                   `endif
                end
               $display("###################################################");
@@ -358,34 +359,7 @@
 initial begin
 end
 `endif    
-
-
-/**
-//-----------------------------------------------------------------------------
-// RISC IMEM amd DMEM Monitoring TASK
-//-----------------------------------------------------------------------------
-logic [`SCR1_DMEM_AWIDTH-1:0]           core2imem_addr_o_r;           // DMEM address
-logic [`SCR1_DMEM_AWIDTH-1:0]           core2dmem_addr_o_r;           // DMEM address
-logic                                   core2dmem_cmd_o_r;
-
-`define RISC_CORE  test_tb.uut.mprj.u_core.u_riscv_top.i_core_top
-
-always@(posedge `RISC_CORE.clk) begin
-    if(`RISC_CORE.imem2core_req_ack_i && `RISC_CORE.core2imem_req_o)
-          core2imem_addr_o_r <= `RISC_CORE.core2imem_addr_o;
-
-    if(`RISC_CORE.dmem2core_req_ack_i && `RISC_CORE.core2dmem_req_o) begin
-          core2dmem_addr_o_r <= `RISC_CORE.core2dmem_addr_o;
-          core2dmem_cmd_o_r  <= `RISC_CORE.core2dmem_cmd_o;
-    end
-
-    if(`RISC_CORE.imem2core_resp_i !=0)
-          $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x Resonse: %x", core2imem_addr_o_r,`RISC_CORE.imem2core_rdata_i,`RISC_CORE.imem2core_resp_i);
-    if((`RISC_CORE.dmem2core_resp_i !=0) && core2dmem_cmd_o_r)
-          $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", core2dmem_addr_o_r,`RISC_CORE.core2dmem_wdata_o,`RISC_CORE.dmem2core_resp_i);
-    if((`RISC_CORE.dmem2core_resp_i !=0) && !core2dmem_cmd_o_r)
-          $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", core2dmem_addr_o_r,`RISC_CORE.dmem2core_rdata_i,`RISC_CORE.dmem2core_resp_i);
-end
-*/
 endmodule
+// SSFLASH has 1ps/1ps time scale
+`include "s25fl256s.sv"
 `default_nettype wire
diff --git a/verilog/dv/riscv_regress/tests/isr_sample/isr_sample.S b/verilog/dv/riscv_regress/tests/isr_sample/isr_sample.S
index 19f8703..db5057f 100644
--- a/verilog/dv/riscv_regress/tests/isr_sample/isr_sample.S
+++ b/verilog/dv/riscv_regress/tests/isr_sample/isr_sample.S
@@ -11,9 +11,10 @@
 #define MCAUSE_TMR_IRQ              (1 << 31 | IRQ_M_TIMER)
 
 // IPIC
-#define IRQ_LINES_ADDR              0x10020020      // simulation
-#define TRIG_EXT_IRQ_ADDR           0x10020020      // external irq is triggered when tb memory is set to non-zero // Bit [15:0]
-#define TRIG_SW_IRQ_ADDR            0x10020020      // software irq is triggered when tb memory is set to non-zero // Bit [16]
+#define IRQ_LINES_MASK              0x1002000C      // Interrupt Mask
+#define IRQ_LINES_ADDR              0x10020010      // simulation
+#define TRIG_EXT_IRQ_ADDR           0x10020010      // external irq is triggered when tb memory is set to non-zero // Bit [15:0]
+#define TRIG_SW_IRQ_ADDR            0x10020010      // software irq is triggered when tb memory is set to non-zero // Bit [16]
 
 #define IPIC_EOI                    0xBF4           // end of interrupt
 #define IPIC_SOI                    0xBF5           // start of interrupt
@@ -28,7 +29,7 @@
 #define IPIC_ICSR_IS                (1 << 4)        // in service
 
 //  Interrupt lines in use 
-#define IPIC_IRQ_LINE9              9
+#define IPIC_IRQ_LINE7              7
 #define EXT_IRQ_LINE_COMMON         0
 
 #include "timer.h"
@@ -154,8 +155,11 @@
     csrw                mie, zero                      // disable all interrupts
     li                  t0, IRQ_LINES_ADDR
     sh                  zero, (t0)                     // set all exterinal interrupt lines low
+    li                  t0, IRQ_LINES_MASK
+    li                  t1, 0xFFFFF
+    sw                  t1, (t0)                     // Enable Interrupt Mask
     #ifdef IPIC_ENABLED
-        li                  t0, IPIC_IRQ_LINE9
+        li                  t0, IPIC_IRQ_LINE7
         csrw                IPIC_IDX, t0               // set IPIC to expect interupt on line 9...
         li                  t0, (IPIC_ICSR_IE | IPIC_ICSR_IM)
         csrw                IPIC_ICSR, t0              //  ....enable interrupt,set edge interrupt mode
@@ -164,7 +168,7 @@
     csrs                mie, t0                        // enable external interrupt 
     li                  t0, TRIG_EXT_IRQ_ADDR
     #ifdef IPIC_ENABLED          
-        li                  t1, (1 << IPIC_IRQ_LINE9)
+        li                  t1, (1 << IPIC_IRQ_LINE7)
     #else
         li                  t1, (1 << EXT_IRQ_LINE_COMMON)
     #endif
diff --git a/verilog/dv/riscv_regress/user_risc_regress_tb.v b/verilog/dv/riscv_regress/user_risc_regress_tb.v
index eac26f5..d915a3d 100644
--- a/verilog/dv/riscv_regress/user_risc_regress_tb.v
+++ b/verilog/dv/riscv_regress/user_risc_regress_tb.v
@@ -73,13 +73,12 @@
 
 `timescale 1 ns / 1 ns
 
-`include "s25fl256s.sv"
 `include "uprj_netlists.v"
 `include "mt48lc8m8a2.v"
 `include "is62wvs1288.v"
+`include "user_reg_map.v"
 
 
-`define ADDR_SPACE_PINMUX  32'h3002_0000
 
 localparam [31:0]      YCR1_SIM_EXIT_ADDR      = 32'h0000_00F8;
 localparam [31:0]      YCR1_SIM_PRINT_ADDR     = 32'hF000_0000;
@@ -284,35 +283,35 @@
 		$display("Monitor: Core reset removal");
 
 		// Remove Wb Reset
-		wb_user_core_write('h3080_0000,'h1);
+		wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
 	        repeat (2) @(posedge clock);
 		#1;
 		//------------ fuse_mhartid= 0x00
-                wb_user_core_write('h3002_0004,'h0);
+                //wb_user_core_write('h3002_0004,'h0);
 
 
 	        repeat (2) @(posedge clock);
 		#1;
 		// Remove WB and SPI Reset, Keep SDARM and CORE under Reset
-               if(d_risc_id == 0) begin
-                    $display("STATUS: Working with Risc core 0");
-                    wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h11F);
-               end else begin
-                    $display("STATUS: Working with Risc core 1");
-                    wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h21F);
-               end
+                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h01F);
 
 		// CS#2 Switch to QSPI Mode
-                wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10
-		wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100});
-		wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h38});
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h0);
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h38});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0);
 
 		// Enable the DCACHE Remap to SRAM region
 		//wb_user_core_write('h3080_000C,{4'b0000,4'b1111, 24'h0});
 		//
 		// Remove all the reset
-                wb_user_core_write('h3080_0000,'h8F);
+               if(d_risc_id == 0) begin
+                    $display("STATUS: Working with Risc core 0");
+                    wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
+               end else begin
+                    $display("STATUS: Working with Risc core 1");
+                    wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
+               end
 
 	end
 
@@ -545,4 +544,5 @@
 `endif
 **/
 endmodule
+`include "s25fl256s.sv"
 `default_nettype wire
diff --git a/verilog/dv/uart_master/uart_master_tb.v b/verilog/dv/uart_master/uart_master_tb.v
index aa4d9f6..1442c8c 100644
--- a/verilog/dv/uart_master/uart_master_tb.v
+++ b/verilog/dv/uart_master/uart_master_tb.v
@@ -23,6 +23,7 @@
 `include "caravel_netlists.v"
 `include "spiflash.v"
 `include "uart_agent.v"
+`include "user_reg_map.v"
 
 module uart_master_tb;
 	reg clock;
@@ -88,8 +89,6 @@
 
 	initial begin
 
-		$display("Test Started ...");
-		$dumpon;
 		// Repeat cycles of 1000 clock edges as needed to complete testbench
 		repeat (400) begin
 			repeat (1000) @(posedge clock);
@@ -135,7 +134,7 @@
 
 
            // Remove Wb Reset
-           uartm_reg_write('h3080_0000,'h1);
+           uartm_reg_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
 
            repeat (2) @(posedge clock);
            #1;
@@ -143,19 +142,19 @@
            $display("Monitor: Writing  expected value");
            
            test_fail = 0;
-           uartm_reg_write(32'h30020058,32'h11223344);
-           uartm_reg_write(32'h3002005C,32'h22334455);
-           uartm_reg_write(32'h30020060,32'h33445566);
-           uartm_reg_write(32'h30020064,32'h44556677);
-           uartm_reg_write(32'h30020068,32'h55667788);
-           uartm_reg_write(32'h3002006C,32'h66778899);
+           uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,32'h11223344);
+           uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,32'h22334455);
+           uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,32'h33445566);
+           uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,32'h44556677);
+           uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,32'h55667788);
+           uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,32'h66778899);
 
-           uartm_reg_read_check(32'h30020058,32'h11223344);
-           uartm_reg_read_check(32'h3002005C,32'h22334455);
-           uartm_reg_read_check(32'h30020060,32'h33445566);
-           uartm_reg_read_check(32'h30020064,32'h44556677);
-           uartm_reg_read_check(32'h30020068,32'h55667788);
-           uartm_reg_read_check(32'h3002006C,32'h66778899);
+           uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,32'h11223344);
+           uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,32'h22334455);
+           uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,32'h33445566);
+           uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,32'h44556677);
+           uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,32'h55667788);
+           uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,32'h66778899);
 
            $display("###################################################");
            if(test_fail == 0) begin
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
index dedd260..9ee701c 100644
--- a/verilog/dv/user_basic/user_basic_tb.v
+++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -75,6 +75,7 @@
 `timescale 1 ns/10 ps
 
 `include "uprj_netlists.v"
+`include "user_reg_map.v"
 
 
 module user_basic_tb;
@@ -182,67 +183,67 @@
           // cfg_usb_clk_ctrl     = reg_0[31:24];
 	  $display("Step-1, CPU: CLOCK1, RTC: CLOCK2 *2, USB: CLOCK2, WBS:CLOCK1");
 	  test_step = 1;
-          wb_user_core_write('h3080_0000,{8'h0,4'h0,8'h0,4'h0,8'h00});
+          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h0,4'h0,8'h0,4'h0,8'h00});
 	  clock_monitor(CLK1_PERIOD,CLK2_PERIOD*2,CLK2_PERIOD,CLK1_PERIOD);
 
 	  $display("Step-2, CPU: CLOCK2, RTC: CLOCK2/(2+1), USB: CLOCK2/2, WBS:CLOCK2");
 	  test_step = 2;
-          wb_user_core_write('h3080_0000,{8'h80,4'h8,8'h1,4'h8,8'h00});
+          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h80,4'h8,8'h1,4'h8,8'h00});
 	  clock_monitor(CLK2_PERIOD,(3)*CLK2_PERIOD,2*CLK2_PERIOD,CLK2_PERIOD);
 
 	  $display("Step-3, CPU: CLOCK1/2, RTC: CLOCK2/(2+2), USB: CLOCK2/(2+1), WBS:CLOCK1/2");
 	  test_step = 3;
-          wb_user_core_write('h3080_0000,{8'h81,4'h4,8'h2,4'h4,8'h00});
+          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h81,4'h4,8'h2,4'h4,8'h00});
 	  clock_monitor(2*CLK1_PERIOD,(4)*CLK2_PERIOD,3*CLK2_PERIOD,2*CLK1_PERIOD);
 
 	  $display("Step-4, CPU: CLOCK1/3, RTC: CLOCK2/(2+3), USB: CLOCK2/(2+2), WBS:CLOCK1/3");
 	  test_step = 4;
-          wb_user_core_write('h3080_0000,{8'h82,4'h5,8'h3,4'h5,8'h00});
+          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h82,4'h5,8'h3,4'h5,8'h00});
 	  clock_monitor(3*CLK1_PERIOD,5*CLK2_PERIOD,4*CLK2_PERIOD,3*CLK1_PERIOD);
 
 	  $display("Step-5, CPU: CLOCK1/4, RTC: CLOCK2/(2+4), USB: CLOCK2/(2+3), WBS:CLOCK1/4");
 	  test_step = 5;
-          wb_user_core_write('h3080_0000,{8'h83,4'h6,8'h4,4'h6,8'h00});
+          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h83,4'h6,8'h4,4'h6,8'h00});
 	  clock_monitor(4*CLK1_PERIOD,6*CLK2_PERIOD,5*CLK2_PERIOD,4*CLK1_PERIOD);
 
 	  $display("Step-6, CPU: CLOCK1/(2+3), RTC: CLOCK2/(2+5), USB: CLOCK2/(2+4), WBS:CLOCK1/(2+3)");
 	  test_step = 6;
-          wb_user_core_write('h3080_0000,{8'h84,4'h7,8'h5,4'h7,8'h00});
+          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h84,4'h7,8'h5,4'h7,8'h00});
 	  clock_monitor(5*CLK1_PERIOD,7*CLK2_PERIOD,6*CLK2_PERIOD,5*CLK1_PERIOD);
 
 	  $display("Step-7, CPU: CLOCK2/(2), RTC: CLOCK2/(2+6), USB: CLOCK2/(2+5), WBS:CLOCK2/(2)");
 	  test_step = 7;
-          wb_user_core_write('h3080_0000,{8'h85,4'hC,8'h6,4'hC,8'h00});
+          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h85,4'hC,8'h6,4'hC,8'h00});
 	  clock_monitor(2*CLK2_PERIOD,8*CLK2_PERIOD,7*CLK2_PERIOD,2*CLK2_PERIOD);
 
 	  $display("Step-8, CPU: CLOCK2/3, RTC: CLOCK2/(2+7), USB: CLOCK2/(2+6), WBS:CLOCK2/3");
 	  test_step = 8;
-          wb_user_core_write('h3080_0000,{8'h86,4'hD,8'h7,4'hD,8'h00});
+          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h86,4'hD,8'h7,4'hD,8'h00});
 	  clock_monitor(3*CLK2_PERIOD,9*CLK2_PERIOD,8*CLK2_PERIOD,3*CLK2_PERIOD);
 
 	  $display("Step-9, CPU: CLOCK2/4, RTC: CLOCK2/(2+8), USB: CLOCK2/(2+7), WBS:CLOCK2/4");
 	  test_step = 9;
-          wb_user_core_write('h3080_0000,{8'h87,4'hE,8'h8,4'hE,8'h00});
+          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h87,4'hE,8'h8,4'hE,8'h00});
 	  clock_monitor(4*CLK2_PERIOD,10*CLK2_PERIOD,9*CLK2_PERIOD,4*CLK2_PERIOD);
 
 	  $display("Step-10, CPU: CLOCK2/(2+3), RTC: CLOCK2/(2+128), USB: CLOCK2/(2+8), WBS:CLOCK1/(2+3)");
 	  test_step = 10;
-          wb_user_core_write('h3080_0000,{8'h88,4'hF,8'h80,4'hF,8'h00});
+          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h88,4'hF,8'h80,4'hF,8'h00});
 	  clock_monitor(5*CLK2_PERIOD,130*CLK2_PERIOD,10*CLK2_PERIOD,5*CLK2_PERIOD);
 
 	  $display("Step-10, CPU: CLOCK2/(2+3), RTC: CLOCK2/(2+255), USB: CLOCK2/(2+9), WBS:CLOCK2/(2+3)");
 	  test_step = 10;
-          wb_user_core_write('h3080_0000,{8'h89,4'hF,8'hFF,4'hF,8'h00});
+          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h89,4'hF,8'hFF,4'hF,8'h00});
 	  clock_monitor(5*CLK2_PERIOD,257*CLK2_PERIOD,11*CLK2_PERIOD,5*CLK2_PERIOD);
 
          $display("###################################################");
          $display("Monitor: Checking the chip signature :");
          // Remove Wb/PinMux Reset
-         wb_user_core_write('h3080_0000,'h1);
+         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
 
-	 wb_user_core_read_check(32'h30020058,read_data,32'h8273_8343);
-	 wb_user_core_read_check(32'h3002005C,read_data,32'h1003_2022);
-	 wb_user_core_read_check(32'h30020060,read_data,32'h0003_8000);
+	 wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h8273_8343);
+	 wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h1603_2022);
+	 wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h0003_9000);
 
       end
    
diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v
index f0bed30..c9bcd8b 100644
--- a/verilog/dv/user_i2cm/user_i2cm_tb.v
+++ b/verilog/dv/user_i2cm/user_i2cm_tb.v
@@ -65,16 +65,9 @@
 
 `timescale 1 ns / 1 ns
 
-`include "s25fl256s.sv"
 `include "uprj_netlists.v"
-`include "mt48lc8m8a2.v"
 `include "i2c_slave_model.v"
-
-
-`define ADDR_SPACE_UART  32'h3001_0000
-`define ADDR_SPACE_I2CM  32'h3001_0040
-`define ADDR_SPACE_PINMUX  32'h3002_0000
-
+`include "user_reg_map.v"
 
 module tb_top;
 
@@ -151,13 +144,13 @@
    repeat (10) @(posedge clock);
    #1;
    // Enable I2M Block & WB Reset and Enable I2CM Mux Select
-   wb_user_core_write('h3080_0000,'h01);
+   wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h01);
 
    // Enable I2C Multi Functional Ports
-   wb_user_core_write(`ADDR_SPACE_PINMUX+'h0038,'h200);
+   wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h200);
 
    // Remove i2m reset
-   wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h010);
+   wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h010);
 
    repeat (100) @(posedge clock);  
 
@@ -352,48 +345,6 @@
 
     end
 `endif    
-//------------------------------------------------------
-//  Integrate the Serial flash with qurd support to
-//  user core using the gpio pads
-//  ----------------------------------------------------
-
-   wire flash_clk = io_out[24];
-   wire flash_csb = io_out[25];
-   // Creating Pad Delay
-   wire #1 io_oeb_29 = io_oeb[29];
-   wire #1 io_oeb_30 = io_oeb[30];
-   wire #1 io_oeb_31 = io_oeb[31];
-   wire #1 io_oeb_32 = io_oeb[32];
-   tri  #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz;
-   tri  #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz;
-   tri  #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz;
-   tri  #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz;
-
-   assign io_in[29] = flash_io0;
-   assign io_in[30] = flash_io1;
-   assign io_in[31] = flash_io2;
-   assign io_in[32] = flash_io3;
-
-
-   // Quard flash
-     s25fl256s #(.mem_file_name("user_uart.hex"),
-	         .otp_file_name("none"), 
-                 .TimingModel("S25FL512SAGMFI010_F_30pF")) 
-		 u_spi_flash_256mb
-       (
-           // Data Inputs/Outputs
-       .SI      (flash_io0),
-       .SO      (flash_io1),
-       // Controls
-       .SCK     (flash_clk),
-       .CSNeg   (flash_csb),
-       .WPNeg   (flash_io2),
-       .HOLDNeg (flash_io3),
-       .RSTNeg  (!wb_rst_i)
-
-       );
-
-
 
 //---------------------------
 // I2C
diff --git a/verilog/dv/user_pwm/Makefile b/verilog/dv/user_pwm/Makefile
new file mode 100644
index 0000000..220c33c
--- /dev/null
+++ b/verilog/dv/user_pwm/Makefile
@@ -0,0 +1,97 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+## Caravel Pointers
+CARAVEL_ROOT ?= ../../../caravel
+CARAVEL_PATH ?= $(CARAVEL_ROOT)
+CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
+CARAVEL_VERILOG_PATH  = $(CARAVEL_PATH)/verilog
+CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
+CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+
+
+## User Project Pointers
+UPRJ_VERILOG_PATH ?= ../../../verilog
+UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
+UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
+UPRJ_BEHAVIOURAL_MODELS = ../model
+UPRJ_BEHAVIOURAL_AGENTS = ../agents
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
+UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/i2cm/src/includes
+UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
+
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware
+GCC64_PREFIX?=riscv64-unknown-elf
+
+## RISCV GCC 
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=/opt/pdk/sky130A
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+
+.SUFFIXES:
+
+PATTERN = user_pwm
+
+all:  ${PATTERN:=.vcd}
+
+
+vvp:  ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+ifeq ($(SIM),RTL)
+   ifeq ($(DUMP),OFF)
+	iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
+	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) \
+	-I $(UPRJ_INCLUDE_PATH3) \
+	$< -o $@ 
+    else  
+	iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
+	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) \
+	-I $(UPRJ_INCLUDE_PATH3) \
+	$< -o $@ 
+   endif
+else  
+	iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
+	$< -o $@ 
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+%.hex: 
+	echo @"This is user boot test, noting to compile the mangment core code"
+
+
+# ---- Clean ----
+
+clean:
+	rm -f *.vvp *.vcd *.log *.fst
+
+.PHONY: clean hex all
diff --git a/verilog/dv/user_pwm/user_pwm_tb.v b/verilog/dv/user_pwm/user_pwm_tb.v
new file mode 100644
index 0000000..575d604
--- /dev/null
+++ b/verilog/dv/user_pwm/user_pwm_tb.v
@@ -0,0 +1,454 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  Standalone User validation Test bench                       ////
+////                                                              ////
+////  This file is part of the YIFive cores project               ////
+////  https://github.com/dineshannayya/yifive_r0.git              ////
+////  http://www.opencores.org/cores/yifive/                      ////
+////                                                              ////
+////  Description                                                 ////
+////   This is a standalone test bench to validate the            ////
+////   pwm interfaface through External WB i/F.                  ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision :                                                  ////
+////    0.1 - 01 Oct 2021, Dinesh A                               ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+`default_nettype wire
+
+`timescale 1 ns / 1 ns
+
+
+`define TB_GLBL    user_pwm_tb
+
+`include "uprj_netlists.v"
+`include "user_reg_map.v"
+
+
+module user_pwm_tb;
+	reg clock;
+	reg wb_rst_i;
+	reg power1, power2;
+	reg power3, power4;
+
+        reg        wbd_ext_cyc_i;  // strobe/request
+        reg        wbd_ext_stb_i;  // strobe/request
+        reg [31:0] wbd_ext_adr_i;  // address
+        reg        wbd_ext_we_i;  // write
+        reg [31:0] wbd_ext_dat_i;  // data output
+        reg [3:0]  wbd_ext_sel_i;  // byte enable
+
+        wire [31:0] wbd_ext_dat_o;  // data input
+        wire        wbd_ext_ack_o;  // acknowlegement
+        wire        wbd_ext_err_o;  // error
+
+	// User I/O
+	wire [37:0] io_oeb;
+	wire [37:0] io_out;
+	wire [37:0] io_in;
+
+
+	reg [1:0] spi_chip_no;
+
+	wire gpio;
+	wire [37:0] mprj_io;
+	wire [7:0] mprj_io_0;
+	reg        test_fail;
+	reg [31:0] read_data;
+	reg [31:0] OneMsPeriod;
+        integer    test_step;
+        wire       clock_mon;
+
+
+	// External clock is used by default.  Make this artificially fast for the
+	// simulation.  Normally this would be a slow clock and the digital PLL
+	// would be the fast clock.
+
+	always #12.5 clock <= (clock === 1'b0);
+
+	initial begin
+		OneMsPeriod = 1000;
+		clock = 0;
+                wbd_ext_cyc_i ='h0;  // strobe/request
+                wbd_ext_stb_i ='h0;  // strobe/request
+                wbd_ext_adr_i ='h0;  // address
+                wbd_ext_we_i  ='h0;  // write
+                wbd_ext_dat_i ='h0;  // data output
+                wbd_ext_sel_i ='h0;  // byte enable
+	end
+
+	`ifdef WFDUMP
+	   initial begin
+	   	$dumpfile("simx.vcd");
+	   	$dumpvars(1, `TB_GLBL);
+	   	$dumpvars(0, `TB_GLBL.u_top.u_wb_host);
+	   	$dumpvars(0, `TB_GLBL.u_top.u_pinmux);
+	   	$dumpvars(0, `TB_GLBL.u_top.u_intercon);
+	   end
+       `endif
+
+	initial begin
+		$dumpon;
+
+		#200; // Wait for reset removal
+	        repeat (10) @(posedge clock);
+		$display("Monitor: Standalone User Risc Boot Test Started");
+
+		// Remove Wb Reset
+		wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+
+                // Enable PWM Multi Functional Ports
+                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h03F);
+
+	        repeat (2) @(posedge clock);
+		#1;
+
+                // Remove the reset
+		// Remove WB and SPI/UART Reset, Keep CORE under Reset
+                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h01F);
+
+		// config 1us based on system clock - 1000/25ns = 40 
+                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG1,39);
+
+		test_fail = 0;
+	        repeat (200) @(posedge clock);
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
+
+	        $display("Step-1, PWM-0: 1ms/2 = 500Hz; PWM-1: 1ms/3; PWM-2: 1ms/4, PWM-3: 1ms/5, PWM-4: 1ms/6, PWM-5: 1ms/7");
+	        test_step = 1;
+                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM0,'h0000_0000);
+                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM1,'h0000_0001);
+                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM2,'h0001_0001);
+                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM3,'h0001_0002);
+                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM4,'h0002_0002);
+                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM5,'h0002_0003);
+	        pwm_monitor(OneMsPeriod*2,OneMsPeriod*3,OneMsPeriod*4,OneMsPeriod*5,OneMsPeriod*6,OneMsPeriod*7);
+
+		repeat (100) @(posedge clock);
+			// $display("+1000 cycles");
+
+          	if(test_fail == 0) begin
+		   `ifdef GL
+	    	       $display("Monitor: PWM Mode (GL) Passed");
+		   `else
+		       $display("Monitor: PWM Mode (RTL) Passed");
+		   `endif
+	        end else begin
+		    `ifdef GL
+	    	        $display("Monitor: PWM Mode (GL) Failed");
+		    `else
+		        $display("Monitor: PWM Mode (RTL) Failed");
+		    `endif
+		 end
+	    	$display("###################################################");
+	        $finish;
+	end
+
+	initial begin
+		wb_rst_i <= 1'b1;
+		#100;
+		wb_rst_i <= 1'b0;	    	// Release reset
+	end
+wire USER_VDD1V8 = 1'b1;
+wire VSS = 1'b0;
+
+wire pwm0 = io_out[4];
+wire pwm1 = io_out[8];
+wire pwm2 = io_out[9];
+wire pwm3 = io_out[12];
+wire pwm4 = io_out[13];
+wire pwm5 = io_out[14];
+
+
+task pwm_monitor;
+input [31:0] pwm0_period;
+input [31:0] pwm1_period;
+input [31:0] pwm2_period;
+input [31:0] pwm3_period;
+input [31:0] pwm4_period;
+input [31:0] pwm5_period;
+begin
+   force clock_mon = pwm0;
+   check_clock_period("PWM0 Clock",pwm0_period);
+   release clock_mon;
+
+   force clock_mon = pwm1;
+   check_clock_period("PWM1 Clock",pwm1_period);
+   release clock_mon;
+
+   force clock_mon = pwm2;
+   check_clock_period("PWM2 Clock",pwm2_period);
+   release clock_mon;
+
+   force clock_mon = pwm3;
+   check_clock_period("PWM3 Clock",pwm3_period);
+   release clock_mon;
+
+   force clock_mon = pwm4;
+   check_clock_period("PWM4 Clock",pwm4_period);
+   release clock_mon;
+
+   force clock_mon = pwm5;
+   check_clock_period("PWM5 Clock",pwm5_period);
+   release clock_mon;
+end
+endtask
+
+
+//----------------------------------
+// Check the clock period
+//----------------------------------
+task check_clock_period;
+input [127:0] clk_name;
+input [31:0] clk_period; // in NS
+time prev_t, next_t, periodd;
+begin
+    $timeformat(-12,3,"ns",10);
+   repeat(1) @(posedge clock_mon);
+   repeat(1) @(posedge clock_mon);
+   prev_t  = $realtime;
+   repeat(2) @(posedge clock_mon);
+   next_t  = $realtime;
+   periodd = (next_t-prev_t)/2;
+   periodd = (periodd)/1e3;
+   if(clk_period != periodd) begin
+       $display("STATUS: FAIL => %s Exp Period: %d ms Rxd: %d ms",clk_name,clk_period,periodd);
+       test_fail = 1;
+   end else begin
+       $display("STATUS: PASS => %s  Period: %d ms ",clk_name,clk_period);
+   end
+end
+endtask
+
+user_project_wrapper u_top(
+`ifdef USE_POWER_PINS
+    .vccd1(USER_VDD1V8),	// User area 1 1.8V supply
+    .vssd1(VSS),	// User area 1 digital ground
+`endif
+    .wb_clk_i        (clock),  // System clock
+    .user_clock2     (1'b1),  // Real-time clock
+    .wb_rst_i        (wb_rst_i),  // Regular Reset signal
+
+    .wbs_cyc_i   (wbd_ext_cyc_i),  // strobe/request
+    .wbs_stb_i   (wbd_ext_stb_i),  // strobe/request
+    .wbs_adr_i   (wbd_ext_adr_i),  // address
+    .wbs_we_i    (wbd_ext_we_i),  // write
+    .wbs_dat_i   (wbd_ext_dat_i),  // data output
+    .wbs_sel_i   (wbd_ext_sel_i),  // byte enable
+
+    .wbs_dat_o   (wbd_ext_dat_o),  // data input
+    .wbs_ack_o   (wbd_ext_ack_o),  // acknowlegement
+
+ 
+    // Logic Analyzer Signals
+    .la_data_in      ('1) ,
+    .la_data_out     (),
+    .la_oenb         ('0),
+ 
+
+    // IOs
+    .io_in          (io_in)  ,
+    .io_out         (io_out) ,
+    .io_oeb         (io_oeb) ,
+
+    .user_irq       () 
+
+);
+
+`ifndef GL // Drive Power for Hold Fix Buf
+    // All standard cell need power hook-up for functionality work
+    initial begin
+
+    end
+`endif    
+
+
+
+//----------------------------------------------------
+//  Task
+// --------------------------------------------------
+task test_err;
+begin
+     test_fail = 1;
+end
+endtask
+
+task wb_user_core_write;
+input [31:0] address;
+input [31:0] data;
+begin
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_adr_i =address;  // address
+  wbd_ext_we_i  ='h1;  // write
+  wbd_ext_dat_i =data;  // data output
+  wbd_ext_sel_i ='hF;  // byte enable
+  wbd_ext_cyc_i ='h1;  // strobe/request
+  wbd_ext_stb_i ='h1;  // strobe/request
+  wait(wbd_ext_ack_o == 1);
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_cyc_i ='h0;  // strobe/request
+  wbd_ext_stb_i ='h0;  // strobe/request
+  wbd_ext_adr_i ='h0;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='h0;  // data output
+  wbd_ext_sel_i ='h0;  // byte enable
+  $display("STATUS: WB USER ACCESS WRITE Address : 0x%x, Data : 0x%x",address,data);
+  repeat (2) @(posedge clock);
+end
+endtask
+
+task  wb_user_core_read;
+input [31:0] address;
+output [31:0] data;
+reg    [31:0] data;
+begin
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_adr_i =address;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='0;  // data output
+  wbd_ext_sel_i ='hF;  // byte enable
+  wbd_ext_cyc_i ='h1;  // strobe/request
+  wbd_ext_stb_i ='h1;  // strobe/request
+  wait(wbd_ext_ack_o == 1);
+  data  = wbd_ext_dat_o;  
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_cyc_i ='h0;  // strobe/request
+  wbd_ext_stb_i ='h0;  // strobe/request
+  wbd_ext_adr_i ='h0;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='h0;  // data output
+  wbd_ext_sel_i ='h0;  // byte enable
+  //$display("STATUS: WB USER ACCESS READ  Address : 0x%x, Data : 0x%x",address,data);
+  repeat (2) @(posedge clock);
+end
+endtask
+
+task  wb_user_core_read_check;
+input [31:0] address;
+output [31:0] data;
+input [31:0] cmp_data;
+reg    [31:0] data;
+begin
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_adr_i =address;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='0;  // data output
+  wbd_ext_sel_i ='hF;  // byte enable
+  wbd_ext_cyc_i ='h1;  // strobe/request
+  wbd_ext_stb_i ='h1;  // strobe/request
+  wait(wbd_ext_ack_o == 1);
+  data  = wbd_ext_dat_o;  
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_cyc_i ='h0;  // strobe/request
+  wbd_ext_stb_i ='h0;  // strobe/request
+  wbd_ext_adr_i ='h0;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='h0;  // data output
+  wbd_ext_sel_i ='h0;  // byte enable
+  if(data !== cmp_data) begin
+     $display("ERROR : WB USER ACCESS READ  Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
+     `TB_GLBL.test_fail = 1;
+  end else begin
+     $display("STATUS: WB USER ACCESS READ  Address : 0x%x, Data : 0x%x",address,data);
+  end
+  repeat (2) @(posedge clock);
+end
+endtask
+
+
+`ifdef GL
+
+wire        wbd_spi_stb_i   = u_top.u_spi_master.wbd_stb_i;
+wire        wbd_spi_ack_o   = u_top.u_spi_master.wbd_ack_o;
+wire        wbd_spi_we_i    = u_top.u_spi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i   = u_top.u_spi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i   = u_top.u_spi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o   = u_top.u_spi_master.wbd_dat_o;
+wire [3:0]  wbd_spi_sel_i   = u_top.u_spi_master.wbd_sel_i;
+
+wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb.reg_cs;
+wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb.reg_ack;
+wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb.reg_wr;
+wire [7:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb.reg_addr;
+wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb.reg_wdata;
+wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb.reg_rdata;
+wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb.reg_be;
+
+`endif
+
+/**
+`ifdef GL
+//-----------------------------------------------------------------------------
+// RISC IMEM amd DMEM Monitoring TASK
+//-----------------------------------------------------------------------------
+
+`define RISC_CORE  user_uart_tb.u_top.u_core.u_riscv_top
+
+always@(posedge `RISC_CORE.wb_clk) begin
+    if(`RISC_CORE.wbd_imem_ack_i)
+          $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
+    if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
+          $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
+    if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
+          $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
+end
+
+`endif
+**/
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/user_qspi/user_qspi_tb.v b/verilog/dv/user_qspi/user_qspi_tb.v
index 4a35096..3b4d47a 100644
--- a/verilog/dv/user_qspi/user_qspi_tb.v
+++ b/verilog/dv/user_qspi/user_qspi_tb.v
@@ -79,29 +79,11 @@
 
 `timescale 1 ns / 1 ns
 
-`include "s25fl256s.sv"
 `include "uprj_netlists.v"
 `include "mt48lc8m8a2.v"
 `include "is62wvs1288.v"
+`include "user_reg_map.v"
 
- // REGISTER MAP
- `define QSPIM_GLBL_CTRL           32'h10000000
- `define QSPIM_DMEM_G0_RD_CTRL    32'h10000004
- `define QSPIM_DMEM_G0_WR_CTRL    32'h10000008
- `define QSPIM_DMEM_G1_RD_CTRL    32'h1000000C
- `define QSPIM_DMEM_G1_WR_CTRL    32'h10000010
-
- `define QSPIM_DMEM_CS_AMAP        32'h10000014
- `define QSPIM_DMEM_CA_AMASK       32'h10000018
-
- `define QSPIM_IMEM_CTRL1          32'h1000001C
- `define QSPIM_IMEM_CTRL2          32'h10000020
- `define QSPIM_IMEM_ADDR           32'h10000024
- `define QSPIM_IMEM_WDATA          32'h10000028
- `define QSPIM_IMEM_RDATA          32'h1000002C
- `define QSPIM_SPI_STATUS          32'h10000030
-
- `define ADDR_SPACE_PINMUX  32'h3002_0000
 
 module user_qspi_tb;
 	reg clock;
@@ -219,97 +201,97 @@
 		$display("Monitor: Standalone User Risc Boot Test Started");
 
 		// Remove Wb Reset
-		wb_user_core_write('h3080_0000,'h1);
+		wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
 
 	        repeat (2) @(posedge clock);
 		#1;
 		// Remove only WB and SPI Reset
-                wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h2);
+                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h2);
 
-                wb_user_core_write('h3080_0004,'h0); // Change the Bank Sel 0
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h0000); // Change the Bank Sel 0000
 
 
 		test_fail = 0;
 	        repeat (200) @(posedge clock);
-                wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
 		// CS#2 SSPI Indirect RAM READ ACCESS-
-		wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100});
-		wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h4,2'b00,2'b10,P_FSM_CADR,8'h00,8'h03});
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000000);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h03020100);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000004);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h07060504);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000008);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h0b0a0908);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h0000000C);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h0f0e0d0c);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h4,2'b00,2'b10,P_FSM_CADR,8'h00,8'h03});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000000);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h03020100);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000004);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h07060504);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000008);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h0b0a0908);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h0000000C);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h0f0e0d0c);
 
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000200);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h11111111);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000204);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h22222222);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000208);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h33333333);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h0000020C);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h44444444);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000200);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h11111111);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000204);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h22222222);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000208);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h33333333);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h0000020C);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h44444444);
 
 		// CS#2 SSPI Indiect Write DATA
-		wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100});
-		wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h10,2'b00,2'b10,P_FSM_CAW,8'h00,8'h02});
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000000);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00112233);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h44556677);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h8899AABB);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'hCCDDEEFF);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h10,2'b00,2'b10,P_FSM_CAW,8'h00,8'h02});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000000);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00112233);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h44556677);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h8899AABB);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'hCCDDEEFF);
 		
 		// CS#2 SSPI Indirect READ DATA
-		wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100});
-		wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h10,2'b00,2'b10,P_FSM_CADR,8'h00,8'h03});
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000000);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00112233);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h44556677);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h8899AABB);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'hCCDDEEFF);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h10,2'b00,2'b10,P_FSM_CADR,8'h00,8'h03});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000000);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00112233);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h44556677);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h8899AABB);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'hCCDDEEFF);
 
 
 		// CS#2 Switch to QSPI Mode
-		wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100});
-		wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h38});
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h0);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h38});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0);
 
 
 		// CS#2 QUAD Indirect Write DATA
-		wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_QUAD,P_QUAD,4'b0100});
-		wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h10,2'b00,2'b10,P_FSM_CAW,8'h00,8'h02});
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000000);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h01234557);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h89ABCDEF);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h12345678);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h9ABCDEF0);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_QUAD,P_QUAD,4'b0100});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h10,2'b00,2'b10,P_FSM_CAW,8'h00,8'h02});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000000);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h01234557);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h89ABCDEF);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h12345678);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h9ABCDEF0);
 
 
 		// CS#2 QUAD Indirect READ DATA
-		wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_QUAD,P_QUAD,4'b0100});
-		wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h10,2'b00,2'b10,P_FSM_CADR,8'h00,8'h03});
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000000);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h01234557);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h89ABCDEF);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h12345678);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h9ABCDEF0);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_QUAD,P_QUAD,4'b0100});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h10,2'b00,2'b10,P_FSM_CADR,8'h00,8'h03});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000000);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h01234557);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h89ABCDEF);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h12345678);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h9ABCDEF0);
 
 		// CS#2 Switch From QSPI to SSPI Mode
-		wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_QUAD,P_QUAD,4'b0100});
-		wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'hFF});
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h0);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_QUAD,P_QUAD,4'b0100});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'hFF});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0);
 		///////////////////// End of CS#1 Indirect Memory Access Testing ///////////////////////////////////
 
 		$display("#############################################");
 		$display("  Read Identification (RDID:0x9F)            ");
 		$display("#############################################");
-                wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10
-		wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,2'b00,P_SINGLE,P_SINGLE,4'b0001});
-		wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h4,2'b00,2'b00,P_FSM_CR,8'h00,8'h9F});
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00190201);
+                wb_user_core_write(`ADDR_SPACE_QSPI+`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,2'b00,P_SINGLE,P_SINGLE,4'b0001});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h4,2'b00,2'b00,P_FSM_CR,8'h00,8'h9F});
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00190201);
 		$display("#############################################");
 		$display("Testing Direct SPI Memory Read              ");
 		$display(" SPI Mode: QDDR (Dual 4 bit)                ");
@@ -317,25 +299,25 @@
 		$display("SEQ: Command -> Address -> Read Data        ");
 		$display("#############################################");
 		// QDDR Config
-                wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10
-		wb_user_core_write(`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAMDR,4'b0100,2'b10,P_MODE_SWITCH_AT_ADDR,P_QDDR,P_SINGLE,8'h00,8'hED});
-                wb_user_core_write('h3080_0004,'h00); // Change the Bank Sel 00
-		wb_user_core_read_check(32'h00000200,read_data,32'h00000093);
-		wb_user_core_read_check(32'h00000204,read_data,32'h00000113);
-		wb_user_core_read_check(32'h00000208,read_data,32'h00000193);
-		wb_user_core_read_check(32'h0000020C,read_data,32'h00000213);
-		wb_user_core_read_check(32'h00000210,read_data,32'h00000293);
-		wb_user_core_read_check(32'h00000214,read_data,32'h00000313);
-		wb_user_core_read_check(32'h00000218,read_data,32'h00000393);
-		wb_user_core_read_check(32'h0000021C,read_data,32'h00000413);
-		wb_user_core_read_check(32'h00000300,read_data,32'h0005A023);
-		wb_user_core_read_check(32'h00000304,read_data,32'h9DE30591);
-		wb_user_core_read_check(32'h00000308,read_data,32'h02B7FEE5);
-		wb_user_core_read_check(32'h0000030C,read_data,32'h43050049);
-		wb_user_core_read_check(32'h00000310,read_data,32'h0062A023);
-		wb_user_core_read_check(32'h00000314,read_data,32'h004902B7);
-		wb_user_core_read_check(32'h00000318,read_data,32'h03130291);
-		wb_user_core_read_check(32'h0000031C,read_data,32'ha0230630);
+                wb_user_core_write(`ADDR_SPACE_QSPI+`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAMDR,4'b0100,2'b10,P_MODE_SWITCH_AT_ADDR,P_QDDR,P_SINGLE,8'h00,8'hED});
+                wb_user_core_write(`ADDR_SPACE_QSPI+`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h0000); // Change the Bank Sel 0000
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000200,read_data,32'h00000093);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000204,read_data,32'h00000113);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000208,read_data,32'h00000193);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000020C,read_data,32'h00000213);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000210,read_data,32'h00000293);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000214,read_data,32'h00000313);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000218,read_data,32'h00000393);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000021C,read_data,32'h00000413);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000300,read_data,32'h0005A023);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000304,read_data,32'h9DE30591);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000308,read_data,32'h02B7FEE5);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000030C,read_data,32'h43050049);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000310,read_data,32'h0062A023);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000314,read_data,32'h004902B7);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000318,read_data,32'h03130291);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000031C,read_data,32'ha0230630);
 		$dumpoff;
 		$display("#############################################");
 		$display("Testing Direct SPI Memory Read              ");
@@ -343,50 +325,50 @@
 		$display("Prefetch : 1DW, OPCODE:READ(0x3)            ");
 		$display("SEQ: Command -> Address -> Read Data        ");
 		$display("#############################################");
-                wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10
-		wb_user_core_write(`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAR,4'b0000,2'b10,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,8'h00,8'h03});
-                wb_user_core_write('h3080_0004,'h00); // Change the Bank Sel 00
-		wb_user_core_read_check(32'h00000200,read_data,32'h00000093);
-		wb_user_core_read_check(32'h00000204,read_data,32'h00000113);
-		wb_user_core_read_check(32'h00000208,read_data,32'h00000193);
-		wb_user_core_read_check(32'h0000020C,read_data,32'h00000213);
-		wb_user_core_read_check(32'h00000210,read_data,32'h00000293);
-		wb_user_core_read_check(32'h00000214,read_data,32'h00000313);
-		wb_user_core_read_check(32'h00000218,read_data,32'h00000393);
-		wb_user_core_read_check(32'h0000021C,read_data,32'h00000413);
-		wb_user_core_read_check(32'h00000300,read_data,32'h0005A023);
-		wb_user_core_read_check(32'h00000304,read_data,32'h9DE30591);
-		wb_user_core_read_check(32'h00000308,read_data,32'h02B7FEE5);
-		wb_user_core_read_check(32'h0000030C,read_data,32'h43050049);
-		wb_user_core_read_check(32'h00000310,read_data,32'h0062A023);
-		wb_user_core_read_check(32'h00000314,read_data,32'h004902B7);
-		wb_user_core_read_check(32'h00000318,read_data,32'h03130291);
-		wb_user_core_read_check(32'h0000031C,read_data,32'ha0230630);
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAR,4'b0000,2'b10,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,8'h00,8'h03});
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h0000); // Change the Bank Sel 0000
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000200,read_data,32'h00000093);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000204,read_data,32'h00000113);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000208,read_data,32'h00000193);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000020C,read_data,32'h00000213);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000210,read_data,32'h00000293);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000214,read_data,32'h00000313);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000218,read_data,32'h00000393);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000021C,read_data,32'h00000413);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000300,read_data,32'h0005A023);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000304,read_data,32'h9DE30591);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000308,read_data,32'h02B7FEE5);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000030C,read_data,32'h43050049);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000310,read_data,32'h0062A023);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000314,read_data,32'h004902B7);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000318,read_data,32'h03130291);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000031C,read_data,32'ha0230630);
 		$display("#############################################");
 		$display("Testing Direct SPI Memory Read              ");
 		$display(" SPI Mode: Normal/Single Bit                ");
 		$display("Prefetch : 1DW, OPCODE:FASTREAD(0xB)        ");
 		$display("SEQ: Command -> Address -> Dummy -> Read Data");
 		$display("#############################################");
-                wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10
-		wb_user_core_write(`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CADR,4'b0000,2'b10,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,8'h00,8'h0B});
-                wb_user_core_write('h3080_0004,'h00); // Change the Bank Sel 00
-		wb_user_core_read_check(32'h00000200,read_data,32'h00000093);
-		wb_user_core_read_check(32'h00000204,read_data,32'h00000113);
-		wb_user_core_read_check(32'h00000208,read_data,32'h00000193);
-		wb_user_core_read_check(32'h0000020C,read_data,32'h00000213);
-		wb_user_core_read_check(32'h00000210,read_data,32'h00000293);
-		wb_user_core_read_check(32'h00000214,read_data,32'h00000313);
-		wb_user_core_read_check(32'h00000218,read_data,32'h00000393);
-		wb_user_core_read_check(32'h0000021C,read_data,32'h00000413);
-		wb_user_core_read_check(32'h00000300,read_data,32'h0005A023);
-		wb_user_core_read_check(32'h00000304,read_data,32'h9DE30591);
-		wb_user_core_read_check(32'h00000308,read_data,32'h02B7FEE5);
-		wb_user_core_read_check(32'h0000030C,read_data,32'h43050049);
-		wb_user_core_read_check(32'h00000310,read_data,32'h0062A023);
-		wb_user_core_read_check(32'h00000314,read_data,32'h004902B7);
-		wb_user_core_read_check(32'h00000318,read_data,32'h03130291);
-		wb_user_core_read_check(32'h0000031C,read_data,32'ha0230630);
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CADR,4'b0000,2'b10,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,8'h00,8'h0B});
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h0000); // Change the Bank Sel 0000
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000200,read_data,32'h00000093);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000204,read_data,32'h00000113);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000208,read_data,32'h00000193);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000020C,read_data,32'h00000213);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000210,read_data,32'h00000293);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000214,read_data,32'h00000313);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000218,read_data,32'h00000393);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000021C,read_data,32'h00000413);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000300,read_data,32'h0005A023);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000304,read_data,32'h9DE30591);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000308,read_data,32'h02B7FEE5);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000030C,read_data,32'h43050049);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000310,read_data,32'h0062A023);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000314,read_data,32'h004902B7);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000318,read_data,32'h03130291);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000031C,read_data,32'ha0230630);
 
 		$display("#############################################");
 		$display("Testing Direct SPI Memory Read              ");
@@ -394,25 +376,25 @@
 		$display("Prefetch : 1DW, OPCODE:DOR(0x3B)        ");
 		$display("SEQ: Command -> Address -> Dummy -> Read Data");
 		$display("#############################################");
-                wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10
-		wb_user_core_write(`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CADR,4'b0000,2'b10,P_MODE_SWITCH_AT_DATA,P_DOUBLE,P_SINGLE,8'h00,8'h3B});
-                wb_user_core_write('h3080_0004,'h00); // Change the Bank Sel 00
-		wb_user_core_read_check(32'h00000200,read_data,32'h00000093);
-		wb_user_core_read_check(32'h00000204,read_data,32'h00000113);
-		wb_user_core_read_check(32'h00000208,read_data,32'h00000193);
-		wb_user_core_read_check(32'h0000020C,read_data,32'h00000213);
-		wb_user_core_read_check(32'h00000210,read_data,32'h00000293);
-		wb_user_core_read_check(32'h00000214,read_data,32'h00000313);
-		wb_user_core_read_check(32'h00000218,read_data,32'h00000393);
-		wb_user_core_read_check(32'h0000021C,read_data,32'h00000413);
-		wb_user_core_read_check(32'h00000300,read_data,32'h0005A023);
-		wb_user_core_read_check(32'h00000304,read_data,32'h9DE30591);
-		wb_user_core_read_check(32'h00000308,read_data,32'h02B7FEE5);
-		wb_user_core_read_check(32'h0000030C,read_data,32'h43050049);
-		wb_user_core_read_check(32'h00000310,read_data,32'h0062A023);
-		wb_user_core_read_check(32'h00000314,read_data,32'h004902B7);
-		wb_user_core_read_check(32'h00000318,read_data,32'h03130291);
-		wb_user_core_read_check(32'h0000031C,read_data,32'ha0230630);
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CADR,4'b0000,2'b10,P_MODE_SWITCH_AT_DATA,P_DOUBLE,P_SINGLE,8'h00,8'h3B});
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h0000); // Change the Bank Sel 0000
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000200,read_data,32'h00000093);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000204,read_data,32'h00000113);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000208,read_data,32'h00000193);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000020C,read_data,32'h00000213);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000210,read_data,32'h00000293);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000214,read_data,32'h00000313);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000218,read_data,32'h00000393);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000021C,read_data,32'h00000413);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000300,read_data,32'h0005A023);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000304,read_data,32'h9DE30591);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000308,read_data,32'h02B7FEE5);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000030C,read_data,32'h43050049);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000310,read_data,32'h0062A023);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000314,read_data,32'h004902B7);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000318,read_data,32'h03130291);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000031C,read_data,32'ha0230630);
 
 		$display("#############################################");
 		$display("Testing Direct SPI Memory Read with Prefetch");
@@ -420,302 +402,302 @@
 		$display("Prefetch : 8DW, OPCODE:URAD READ(0xEB)      ");
 		$display("SEQ: Command -> Address -> Dummy -> Read Data");
 		$display("#############################################");
-                wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10
-		wb_user_core_write(`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAMDR,4'b0001,2'b10,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,8'h00,8'hEB});
-                wb_user_core_write('h3080_0004,'h00); // Change the Bank Sel 00
-		wb_user_core_read_check(32'h00000200,read_data,32'h00000093);
-		wb_user_core_read_check(32'h00000204,read_data,32'h00000113);
-		wb_user_core_read_check(32'h00000208,read_data,32'h00000193);
-		wb_user_core_read_check(32'h0000020C,read_data,32'h00000213);
-		wb_user_core_read_check(32'h00000210,read_data,32'h00000293);
-		wb_user_core_read_check(32'h00000214,read_data,32'h00000313);
-		wb_user_core_read_check(32'h00000218,read_data,32'h00000393);
-		wb_user_core_read_check(32'h0000021C,read_data,32'h00000413);
-		wb_user_core_read_check(32'h00000300,read_data,32'h0005A023);
-		wb_user_core_read_check(32'h00000304,read_data,32'h9DE30591);
-		wb_user_core_read_check(32'h00000308,read_data,32'h02B7FEE5);
-		wb_user_core_read_check(32'h0000030C,read_data,32'h43050049);
-		wb_user_core_read_check(32'h00000310,read_data,32'h0062A023);
-		wb_user_core_read_check(32'h00000314,read_data,32'h004902B7);
-		wb_user_core_read_check(32'h00000318,read_data,32'h03130291);
-		wb_user_core_read_check(32'h0000031C,read_data,32'ha0230630);
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAMDR,4'b0001,2'b10,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,8'h00,8'hEB});
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h0000); // Change the Bank Sel 0000
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000200,read_data,32'h00000093);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000204,read_data,32'h00000113);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000208,read_data,32'h00000193);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000020C,read_data,32'h00000213);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000210,read_data,32'h00000293);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000214,read_data,32'h00000313);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000218,read_data,32'h00000393);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000021C,read_data,32'h00000413);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000300,read_data,32'h0005A023);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000304,read_data,32'h9DE30591);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000308,read_data,32'h02B7FEE5);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000030C,read_data,32'h43050049);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000310,read_data,32'h0062A023);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000314,read_data,32'h004902B7);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000318,read_data,32'h03130291);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000031C,read_data,32'ha0230630);
 
 		$display("#############################################");
 		$display("Testing Direct SPI Memory Read with Prefetch:3DW");
 		$display("#############################################");
-                wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10
-		wb_user_core_write(`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAMDR,4'b0001,2'b10,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,8'h00,8'hEB});
-                wb_user_core_write('h3080_0004,'h00); // Change the Bank Sel 00
-		wb_user_core_read_check(32'h00000200,read_data,32'h00000093);
-		wb_user_core_read_check(32'h00000204,read_data,32'h00000113);
-		wb_user_core_read_check(32'h00000208,read_data,32'h00000193);
-		wb_user_core_read_check(32'h0000020C,read_data,32'h00000213);
-		wb_user_core_read_check(32'h00000210,read_data,32'h00000293);
-		wb_user_core_read_check(32'h00000214,read_data,32'h00000313);
-		wb_user_core_read_check(32'h00000218,read_data,32'h00000393);
-		wb_user_core_read_check(32'h0000021C,read_data,32'h00000413);
-		wb_user_core_read_check(32'h00000300,read_data,32'h0005A023);
-		wb_user_core_read_check(32'h00000304,read_data,32'h9DE30591);
-		wb_user_core_read_check(32'h00000308,read_data,32'h02B7FEE5);
-		wb_user_core_read_check(32'h0000030C,read_data,32'h43050049);
-		wb_user_core_read_check(32'h00000310,read_data,32'h0062A023);
-		wb_user_core_read_check(32'h00000314,read_data,32'h004902B7);
-		wb_user_core_read_check(32'h00000318,read_data,32'h03130291);
-		wb_user_core_read_check(32'h0000031C,read_data,32'ha0230630);
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAMDR,4'b0001,2'b10,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,8'h00,8'hEB});
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h0000); // Change the Bank Sel 0000
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000200,read_data,32'h00000093);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000204,read_data,32'h00000113);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000208,read_data,32'h00000193);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000020C,read_data,32'h00000213);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000210,read_data,32'h00000293);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000214,read_data,32'h00000313);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000218,read_data,32'h00000393);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000021C,read_data,32'h00000413);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000300,read_data,32'h0005A023);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000304,read_data,32'h9DE30591);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000308,read_data,32'h02B7FEE5);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000030C,read_data,32'h43050049);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000310,read_data,32'h0062A023);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000314,read_data,32'h004902B7);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000318,read_data,32'h03130291);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000031C,read_data,32'ha0230630);
 
 		$display("#############################################");
 		$display("Testing Direct SPI Memory Read with Prefetch:2DW");
 		$display("#############################################");
-                wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10
-		wb_user_core_write(`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAMDR,4'b0001,2'b10,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,8'h00,8'hEB});
-                wb_user_core_write('h3080_0004,'h00); // Change the Bank Sel 00
-		wb_user_core_read_check(32'h00000200,read_data,32'h00000093);
-		wb_user_core_read_check(32'h00000204,read_data,32'h00000113);
-		wb_user_core_read_check(32'h00000208,read_data,32'h00000193);
-		wb_user_core_read_check(32'h0000020C,read_data,32'h00000213);
-		wb_user_core_read_check(32'h00000210,read_data,32'h00000293);
-		wb_user_core_read_check(32'h00000214,read_data,32'h00000313);
-		wb_user_core_read_check(32'h00000218,read_data,32'h00000393);
-		wb_user_core_read_check(32'h0000021C,read_data,32'h00000413);
-		wb_user_core_read_check(32'h00000300,read_data,32'h0005A023);
-		wb_user_core_read_check(32'h00000304,read_data,32'h9DE30591);
-		wb_user_core_read_check(32'h00000308,read_data,32'h02B7FEE5);
-		wb_user_core_read_check(32'h0000030C,read_data,32'h43050049);
-		wb_user_core_read_check(32'h00000310,read_data,32'h0062A023);
-		wb_user_core_read_check(32'h00000314,read_data,32'h004902B7);
-		wb_user_core_read_check(32'h00000318,read_data,32'h03130291);
-		wb_user_core_read_check(32'h0000031C,read_data,32'ha0230630);
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAMDR,4'b0001,2'b10,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,8'h00,8'hEB});
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h0000); // Change the Bank Sel 0000
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000200,read_data,32'h00000093);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000204,read_data,32'h00000113);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000208,read_data,32'h00000193);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000020C,read_data,32'h00000213);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000210,read_data,32'h00000293);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000214,read_data,32'h00000313);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000218,read_data,32'h00000393);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000021C,read_data,32'h00000413);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000300,read_data,32'h0005A023);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000304,read_data,32'h9DE30591);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000308,read_data,32'h02B7FEE5);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000030C,read_data,32'h43050049);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000310,read_data,32'h0062A023);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000314,read_data,32'h004902B7);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000318,read_data,32'h03130291);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000031C,read_data,32'ha0230630);
 
 
 		$display("#############################################");
 		$display("Testing Direct SPI Memory Read with Prefetch:1DW");
 		$display("#############################################");
-                wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10
-		wb_user_core_write(`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAMDR,4'b0001,2'b10,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,8'h00,8'hEB});
-                wb_user_core_write('h3080_0004,'h00); // Change the Bank Sel 00
-		wb_user_core_read_check(32'h00000200,read_data,32'h00000093);
-		wb_user_core_read_check(32'h00000204,read_data,32'h00000113);
-		wb_user_core_read_check(32'h00000208,read_data,32'h00000193);
-		wb_user_core_read_check(32'h0000020C,read_data,32'h00000213);
-		wb_user_core_read_check(32'h00000210,read_data,32'h00000293);
-		wb_user_core_read_check(32'h00000214,read_data,32'h00000313);
-		wb_user_core_read_check(32'h00000218,read_data,32'h00000393);
-		wb_user_core_read_check(32'h0000021C,read_data,32'h00000413);
-		wb_user_core_read_check(32'h00000300,read_data,32'h0005A023);
-		wb_user_core_read_check(32'h00000304,read_data,32'h9DE30591);
-		wb_user_core_read_check(32'h00000308,read_data,32'h02B7FEE5);
-		wb_user_core_read_check(32'h0000030C,read_data,32'h43050049);
-		wb_user_core_read_check(32'h00000310,read_data,32'h0062A023);
-		wb_user_core_read_check(32'h00000314,read_data,32'h004902B7);
-		wb_user_core_read_check(32'h00000318,read_data,32'h03130291);
-		wb_user_core_read_check(32'h0000031C,read_data,32'ha0230630);
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAMDR,4'b0001,2'b10,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,8'h00,8'hEB});
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h0000); // Change the Bank Sel 0000
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000200,read_data,32'h00000093);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000204,read_data,32'h00000113);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000208,read_data,32'h00000193);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000020C,read_data,32'h00000213);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000210,read_data,32'h00000293);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000214,read_data,32'h00000313);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000218,read_data,32'h00000393);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000021C,read_data,32'h00000413);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000300,read_data,32'h0005A023);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000304,read_data,32'h9DE30591);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000308,read_data,32'h02B7FEE5);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000030C,read_data,32'h43050049);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000310,read_data,32'h0062A023);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000314,read_data,32'h004902B7);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000318,read_data,32'h03130291);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000031C,read_data,32'ha0230630);
 
 		$display("#############################################");
 		$display("Testing Direct SPI Memory Read with Prefetch:7DW");
 		$display("#############################################");
-                wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10
-		wb_user_core_write(`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAMDR,4'b0001,2'b10,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,8'h00,8'hEB});
-                wb_user_core_write('h3080_0004,'h00); // Change the Bank Sel 00
-		wb_user_core_read_check(32'h00000200,read_data,32'h00000093);
-		wb_user_core_read_check(32'h00000204,read_data,32'h00000113);
-		wb_user_core_read_check(32'h00000208,read_data,32'h00000193);
-		wb_user_core_read_check(32'h0000020C,read_data,32'h00000213);
-		wb_user_core_read_check(32'h00000210,read_data,32'h00000293);
-		wb_user_core_read_check(32'h00000214,read_data,32'h00000313);
-		wb_user_core_read_check(32'h00000218,read_data,32'h00000393);
-		wb_user_core_read_check(32'h0000021C,read_data,32'h00000413);
-		wb_user_core_read_check(32'h00000300,read_data,32'h0005A023);
-		wb_user_core_read_check(32'h00000304,read_data,32'h9DE30591);
-		wb_user_core_read_check(32'h00000308,read_data,32'h02B7FEE5);
-		wb_user_core_read_check(32'h0000030C,read_data,32'h43050049);
-		wb_user_core_read_check(32'h00000310,read_data,32'h0062A023);
-		wb_user_core_read_check(32'h00000314,read_data,32'h004902B7);
-		wb_user_core_read_check(32'h00000318,read_data,32'h03130291);
-		wb_user_core_read_check(32'h0000031C,read_data,32'ha0230630);
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAMDR,4'b0001,2'b10,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,8'h00,8'hEB});
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h0000); // Change the Bank Sel 0000
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000200,read_data,32'h00000093);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000204,read_data,32'h00000113);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000208,read_data,32'h00000193);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000020C,read_data,32'h00000213);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000210,read_data,32'h00000293);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000214,read_data,32'h00000313);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000218,read_data,32'h00000393);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000021C,read_data,32'h00000413);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000300,read_data,32'h0005A023);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000304,read_data,32'h9DE30591);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000308,read_data,32'h02B7FEE5);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000030C,read_data,32'h43050049);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000310,read_data,32'h0062A023);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000314,read_data,32'h004902B7);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000318,read_data,32'h03130291);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000031C,read_data,32'ha0230630);
 
 		$display("#############################################");
 		$display("  Testing Single Word Indirect SPI Memory Read");
 		$display("#############################################");
-                wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10
-		wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001});
-		wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h4,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB});
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000200);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000093);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000204);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000113);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000208);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000193);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h0000020C);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000213);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000210);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000293);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000214);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000313);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000218);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000393);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h0000021C);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000413);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000300);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h0005A023);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000304);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h9DE30591);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000308);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h02B7FEE5);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h0000030C);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h43050049);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000310);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h0062A023);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000314);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h004902B7);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000318);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h03130291);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h0000031C);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'ha0230630);
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h4,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000200);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000093);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000204);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000113);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000208);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000193);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h0000020C);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000213);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000210);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000293);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000214);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000313);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000218);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000393);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h0000021C);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000413);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000300);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h0005A023);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000304);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h9DE30591);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000308);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h02B7FEE5);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h0000030C);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h43050049);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000310);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h0062A023);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000314);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h004902B7);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000318);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h03130291);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h0000031C);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'ha0230630);
 		repeat (100) @(posedge clock);
 		$display("#############################################");
 		$display("  Testing Two Word Indirect SPI Memory Read");
 		$display("#############################################");
-                wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10
-		wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001});
-		wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h8,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB});
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000200);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000093);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000113);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000208);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000193);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000213);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000210);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000293);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000313);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000218);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000393);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000413);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000300);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h0005A023);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h9DE30591);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000308);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h02B7FEE5);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h43050049);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000310);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h0062A023);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h004902B7);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000318);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h03130291);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'ha0230630);
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h8,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000200);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000093);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000113);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000208);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000193);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000213);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000210);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000293);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000313);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000218);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000393);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000413);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000300);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h0005A023);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h9DE30591);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000308);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h02B7FEE5);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h43050049);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000310);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h0062A023);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h004902B7);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000318);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h03130291);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'ha0230630);
 		repeat (100) @(posedge clock);
 		$display("#############################################");
 		$display("  Testing Three Word Indirect SPI Memory Read");
 		$display("#############################################");
-                wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10
-		wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001});
-		wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'hC,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB});
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000200);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000093);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000113);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000193);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h0000020C);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000213);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000293);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000313);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000300);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h0005A023);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h9DE30591);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h02B7FEE5);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h0000030C);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h43050049);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h0062A023);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h004902B7);
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'hC,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000200);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000093);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000113);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000193);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h0000020C);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000213);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000293);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000313);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000300);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h0005A023);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h9DE30591);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h02B7FEE5);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h0000030C);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h43050049);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h0062A023);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h004902B7);
 		repeat (100) @(posedge clock);
 		$display("#############################################");
 		$display("  Testing Four Word Indirect SPI Memory Read");
 		$display("#############################################");
-                wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10
-		wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001});
-		wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h10,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB});
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000200);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000093);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000113);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000193);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000213);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000210);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000293);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000313);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000393);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000413);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000300);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h0005A023);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h9DE30591);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h02B7FEE5);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h43050049);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000310);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h0062A023);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h004902B7);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h03130291);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'ha0230630);
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h10,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000200);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000093);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000113);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000193);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000213);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000210);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000293);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000313);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000393);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000413);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000300);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h0005A023);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h9DE30591);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h02B7FEE5);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h43050049);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000310);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h0062A023);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h004902B7);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h03130291);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'ha0230630);
 		repeat (100) @(posedge clock);
 		$display("#############################################");
 		$display("  Testing Five Word Indirect SPI Memory Read");
 		$display("#############################################");
-                wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10
-		wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001});
-		wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h14,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB});
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000200);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000093);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000113);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000193);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000213);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000293);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000300);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h0005A023);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h9DE30591);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h02B7FEE5);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h43050049);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h0062A023);
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h14,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000200);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000093);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000113);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000193);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000213);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000293);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000300);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h0005A023);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h9DE30591);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h02B7FEE5);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h43050049);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h0062A023);
 		$display("#############################################");
 		$display("  Testing Eight Word Indirect SPI Memory Read");
 		$display("#############################################");
-                wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10
-		wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001});
-		wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h20,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB});
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000200);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000093);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000113);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000193);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000213);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000293);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000313);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000393);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000413);
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000300);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h0005A023);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h9DE30591);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h02B7FEE5);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h43050049);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h0062A023);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h004902B7);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h03130291);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'ha0230630);
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h20,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000200);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000093);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000113);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000193);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000213);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000293);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000313);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000393);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000413);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000300);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h0005A023);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h9DE30591);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h02B7FEE5);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h43050049);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h0062A023);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h004902B7);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h03130291);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'ha0230630);
 
 		$display("#############################################");
 		$display("  Sector Erase Command            ");
 		$display("#############################################");
-                wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
 		// WEN COMMAND
-		wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001});
-		wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h06});
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h0);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h06});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0);
                 // Sector Erase
-		wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001});
-		wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b10,P_FSM_CA,8'h00,8'hD8});
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000000);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h0);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b10,P_FSM_CA,8'h00,8'hD8});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000000);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0);
 
 		// RDSR
-		wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001});
-		wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h4,2'b00,2'b00,P_FSM_CR,8'h00,8'h05});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h4,2'b00,2'b00,P_FSM_CR,8'h00,8'h05});
 		read_data = 32'hFFFF_FFFF;
 		while (read_data[1:0] == 2'b11) begin
-		    wb_user_core_read(`QSPIM_IMEM_RDATA,read_data);
+		    wb_user_core_read(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data);
 		    repeat (10) @(posedge clock);
 		end
 
@@ -723,435 +705,435 @@
 		$display("  Page Write Command Address: 0x00          ");
 		$display("#############################################");
 		// WEN COMMAND
-		wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001});
-		wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h06});
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h0);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h06});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0);
 		 // Page Programing
-		wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001});
-		wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'hF0,2'b00,2'b10,P_FSM_CAW,8'h00,8'h02});
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000000);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010000);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010001);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010002);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010003);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010004);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010005);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010006);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010007);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010008);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010009);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010010);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010011);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010012);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010013);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010014);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010015);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010016);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010017);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010018);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010019);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010020);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010021);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010022);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010023);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010024);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010025);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010026);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010027);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010028);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010029);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010030);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010031);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010032);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010033);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010034);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010035);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010036);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010037);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010038);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010039);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010040);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010041);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010042);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010043);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010044);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010045);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010046);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010047);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010048);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010049);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010050);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010051);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010052);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010053);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010054);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010055);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010056);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010057);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010058);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010059);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'hF0,2'b00,2'b10,P_FSM_CAW,8'h00,8'h02});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000000);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010000);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010001);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010002);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010003);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010004);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010005);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010006);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010007);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010008);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010009);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010010);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010011);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010012);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010013);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010014);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010015);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010016);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010017);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010018);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010019);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010020);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010021);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010022);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010023);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010024);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010025);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010026);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010027);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010028);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010029);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010030);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010031);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010032);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010033);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010034);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010035);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010036);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010037);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010038);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010039);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010040);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010041);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010042);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010043);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010044);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010045);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010046);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010047);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010048);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010049);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010050);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010051);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010052);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010053);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010054);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010055);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010056);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010057);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010058);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010059);
 
 		// RDSR
-		wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001});
-		wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h4,2'b00,2'b00,P_FSM_CR,8'h00,8'h05});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h4,2'b00,2'b00,P_FSM_CR,8'h00,8'h05});
 		read_data = 32'hFFFF_FFFF;
 		while (read_data[1:0] == 2'b11) begin
-		    wb_user_core_read(`QSPIM_IMEM_RDATA,read_data);
+		    wb_user_core_read(`ADDR_SPACE_QSPI+`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data);
 		    repeat (10) @(posedge clock);
 		 end
 
 		$display("#############################################");
 		$display("  Page Read through Direct Access            ");
 		$display("#############################################");
-                wb_user_core_write('h3080_0004,'h00); // Change the Bank Sel 00
-		wb_user_core_read_check(32'h00000000,read_data,32'h00010000);
-		wb_user_core_read_check(32'h00000004,read_data,32'h00010001);
-		wb_user_core_read_check(32'h00000008,read_data,32'h00010002);
-		wb_user_core_read_check(32'h0000000C,read_data,32'h00010003);
-		wb_user_core_read_check(32'h00000010,read_data,32'h00010004);
-		wb_user_core_read_check(32'h00000014,read_data,32'h00010005);
-		wb_user_core_read_check(32'h00000018,read_data,32'h00010006);
-		wb_user_core_read_check(32'h0000001C,read_data,32'h00010007);
-		wb_user_core_read_check(32'h00000020,read_data,32'h00010008);
-		wb_user_core_read_check(32'h00000024,read_data,32'h00010009);
-		wb_user_core_read_check(32'h00000028,read_data,32'h00010010);
-		wb_user_core_read_check(32'h0000002C,read_data,32'h00010011);
-		wb_user_core_read_check(32'h00000030,read_data,32'h00010012);
-		wb_user_core_read_check(32'h00000034,read_data,32'h00010013);
-		wb_user_core_read_check(32'h00000038,read_data,32'h00010014);
-		wb_user_core_read_check(32'h0000003C,read_data,32'h00010015);
-		wb_user_core_read_check(32'h00000040,read_data,32'h00010016);
-		wb_user_core_read_check(32'h00000044,read_data,32'h00010017);
-		wb_user_core_read_check(32'h00000048,read_data,32'h00010018);
-		wb_user_core_read_check(32'h0000004C,read_data,32'h00010019);
-		wb_user_core_read_check(32'h00000050,read_data,32'h00010020);
-		wb_user_core_read_check(32'h00000054,read_data,32'h00010021);
-		wb_user_core_read_check(32'h00000058,read_data,32'h00010022);
-		wb_user_core_read_check(32'h0000005C,read_data,32'h00010023);
-		wb_user_core_read_check(32'h00000060,read_data,32'h00010024);
-		wb_user_core_read_check(32'h00000064,read_data,32'h00010025);
-		wb_user_core_read_check(32'h00000068,read_data,32'h00010026);
-		wb_user_core_read_check(32'h0000006C,read_data,32'h00010027);
-		wb_user_core_read_check(32'h00000070,read_data,32'h00010028);
-		wb_user_core_read_check(32'h00000074,read_data,32'h00010029);
-		wb_user_core_read_check(32'h00000078,read_data,32'h00010030);
-		wb_user_core_read_check(32'h0000007C,read_data,32'h00010031);
-		wb_user_core_read_check(32'h00000080,read_data,32'h00010032);
-		wb_user_core_read_check(32'h00000084,read_data,32'h00010033);
-		wb_user_core_read_check(32'h00000088,read_data,32'h00010034);
-		wb_user_core_read_check(32'h0000008C,read_data,32'h00010035);
-		wb_user_core_read_check(32'h00000090,read_data,32'h00010036);
-		wb_user_core_read_check(32'h00000094,read_data,32'h00010037);
-		wb_user_core_read_check(32'h00000098,read_data,32'h00010038);
-		wb_user_core_read_check(32'h0000009C,read_data,32'h00010039);
-		wb_user_core_read_check(32'h000000A0,read_data,32'h00010040);
-		wb_user_core_read_check(32'h000000A4,read_data,32'h00010041);
-		wb_user_core_read_check(32'h000000A8,read_data,32'h00010042);
-		wb_user_core_read_check(32'h000000AC,read_data,32'h00010043);
-		wb_user_core_read_check(32'h000000B0,read_data,32'h00010044);
-		wb_user_core_read_check(32'h000000B4,read_data,32'h00010045);
-		wb_user_core_read_check(32'h000000B8,read_data,32'h00010046);
-		wb_user_core_read_check(32'h000000BC,read_data,32'h00010047);
-		wb_user_core_read_check(32'h000000C0,read_data,32'h00010048);
-		wb_user_core_read_check(32'h000000C4,read_data,32'h00010049);
-		wb_user_core_read_check(32'h000000C8,read_data,32'h00010050);
-		wb_user_core_read_check(32'h000000CC,read_data,32'h00010051);
-		wb_user_core_read_check(32'h000000D0,read_data,32'h00010052);
-		wb_user_core_read_check(32'h000000D4,read_data,32'h00010053);
-		wb_user_core_read_check(32'h000000D8,read_data,32'h00010054);
-		wb_user_core_read_check(32'h000000DC,read_data,32'h00010055);
-		wb_user_core_read_check(32'h000000E0,read_data,32'h00010056);
-		wb_user_core_read_check(32'h000000E4,read_data,32'h00010057);
-		wb_user_core_read_check(32'h000000E8,read_data,32'h00010058);
-		wb_user_core_read_check(32'h000000EC,read_data,32'h00010059);
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h0000); // Change the Bank Sel 0000
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000000,read_data,32'h00010000);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000004,read_data,32'h00010001);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000008,read_data,32'h00010002);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000000C,read_data,32'h00010003);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000010,read_data,32'h00010004);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000014,read_data,32'h00010005);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000018,read_data,32'h00010006);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000001C,read_data,32'h00010007);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000020,read_data,32'h00010008);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000024,read_data,32'h00010009);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000028,read_data,32'h00010010);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000002C,read_data,32'h00010011);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000030,read_data,32'h00010012);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000034,read_data,32'h00010013);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000038,read_data,32'h00010014);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000003C,read_data,32'h00010015);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000040,read_data,32'h00010016);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000044,read_data,32'h00010017);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000048,read_data,32'h00010018);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000004C,read_data,32'h00010019);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000050,read_data,32'h00010020);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000054,read_data,32'h00010021);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000058,read_data,32'h00010022);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000005C,read_data,32'h00010023);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000060,read_data,32'h00010024);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000064,read_data,32'h00010025);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000068,read_data,32'h00010026);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000006C,read_data,32'h00010027);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000070,read_data,32'h00010028);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000074,read_data,32'h00010029);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000078,read_data,32'h00010030);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000007C,read_data,32'h00010031);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000080,read_data,32'h00010032);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000084,read_data,32'h00010033);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000088,read_data,32'h00010034);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000008C,read_data,32'h00010035);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000090,read_data,32'h00010036);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000094,read_data,32'h00010037);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000098,read_data,32'h00010038);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000009C,read_data,32'h00010039);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000A0,read_data,32'h00010040);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000A4,read_data,32'h00010041);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000A8,read_data,32'h00010042);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000AC,read_data,32'h00010043);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000B0,read_data,32'h00010044);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000B4,read_data,32'h00010045);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000B8,read_data,32'h00010046);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000BC,read_data,32'h00010047);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000C0,read_data,32'h00010048);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000C4,read_data,32'h00010049);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000C8,read_data,32'h00010050);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000CC,read_data,32'h00010051);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000D0,read_data,32'h00010052);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000D4,read_data,32'h00010053);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000D8,read_data,32'h00010054);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000DC,read_data,32'h00010055);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000E0,read_data,32'h00010056);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000E4,read_data,32'h00010057);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000E8,read_data,32'h00010058);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000EC,read_data,32'h00010059);
 
 		repeat (100) @(posedge clock);
 		$display("#############################################");
 		$display("  Page Read through Indirect Access           ");
 		$display("#############################################");
-                wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10
-		wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001});
-		wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'hF0,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB});
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000000);
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'hF0,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000000);
 
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010000);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010001);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010002);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010003);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010004);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010005);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010006);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010007);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010008);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010009);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010010);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010011);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010012);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010013);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010014);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010015);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010016);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010017);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010018);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010019);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010020);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010021);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010022);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010023);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010024);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010025);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010026);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010027);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010028);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010029);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010030);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010031);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010032);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010033);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010034);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010035);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010036);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010037);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010038);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010039);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010040);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010041);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010042);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010043);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010044);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010045);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010046);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010047);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010048);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010049);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010050);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010051);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010052);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010053);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010054);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010055);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010056);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010057);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010058);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010059);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010000);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010001);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010002);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010003);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010004);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010005);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010006);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010007);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010008);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010009);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010010);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010011);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010012);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010013);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010014);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010015);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010016);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010017);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010018);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010019);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010020);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010021);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010022);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010023);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010024);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010025);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010026);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010027);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010028);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010029);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010030);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010031);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010032);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010033);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010034);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010035);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010036);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010037);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010038);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010039);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010040);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010041);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010042);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010043);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010044);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010045);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010046);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010047);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010048);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010049);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010050);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010051);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010052);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010053);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010054);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010055);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010056);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010057);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010058);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010059);
 
 		repeat (100) @(posedge clock);
 		$display("#############################################");
 		$display("  Page Write Command Address: 0x200          ");
 		$display("#############################################");
-                wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
 		// WEN COMMAND
-		wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001});
-		wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h06});
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h0);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h06});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0);
 		 // Page Programing
-		wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001});
-		wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'hF0,2'b00,2'b10,P_FSM_CAW,8'h00,8'h02});
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000200);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020000);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020001);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020002);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020003);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020004);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020005);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020006);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020007);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020008);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020009);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020010);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020011);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020012);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020013);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020014);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020015);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020016);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020017);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020018);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020019);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020020);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020021);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020022);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020023);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020024);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020025);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020026);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020027);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020028);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020029);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020030);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020031);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020032);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020033);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020034);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020035);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020036);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020037);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020038);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020039);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020040);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020041);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020042);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020043);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020044);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020045);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020046);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020047);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020048);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020049);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020050);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020051);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020052);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020053);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020054);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020055);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020056);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020057);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020058);
-		wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020059);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'hF0,2'b00,2'b10,P_FSM_CAW,8'h00,8'h02});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000200);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020000);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020001);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020002);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020003);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020004);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020005);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020006);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020007);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020008);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020009);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020010);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020011);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020012);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020013);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020014);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020015);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020016);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020017);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020018);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020019);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020020);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020021);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020022);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020023);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020024);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020025);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020026);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020027);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020028);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020029);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020030);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020031);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020032);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020033);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020034);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020035);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020036);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020037);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020038);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020039);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020040);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020041);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020042);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020043);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020044);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020045);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020046);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020047);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020048);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020049);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020050);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020051);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020052);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020053);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020054);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020055);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020056);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020057);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020058);
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020059);
 
 		// RDSR
-		wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001});
-		wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h4,2'b00,2'b00,P_FSM_CR,8'h00,8'h05});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h4,2'b00,2'b00,P_FSM_CR,8'h00,8'h05});
 		read_data = 32'hFFFF_FFFF;
 		while (read_data[1:0] == 2'b11) begin
-		    wb_user_core_read(`QSPIM_IMEM_RDATA,read_data);
+		    wb_user_core_read(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data);
 		    repeat (10) @(posedge clock);
 		 end
 
 		$display("#############################################");
 		$display("  Page Read through Direct Access            ");
 		$display("#############################################");
-                wb_user_core_write('h3080_0004,'h00); // Change the Bank Sel 00
-		wb_user_core_read_check(32'h00000200,read_data,32'h00020000);
-		wb_user_core_read_check(32'h00000204,read_data,32'h00020001);
-		wb_user_core_read_check(32'h00000208,read_data,32'h00020002);
-		wb_user_core_read_check(32'h0000020C,read_data,32'h00020003);
-		wb_user_core_read_check(32'h00000210,read_data,32'h00020004);
-		wb_user_core_read_check(32'h00000214,read_data,32'h00020005);
-		wb_user_core_read_check(32'h00000218,read_data,32'h00020006);
-		wb_user_core_read_check(32'h0000021C,read_data,32'h00020007);
-		wb_user_core_read_check(32'h00000220,read_data,32'h00020008);
-		wb_user_core_read_check(32'h00000224,read_data,32'h00020009);
-		wb_user_core_read_check(32'h00000228,read_data,32'h00020010);
-		wb_user_core_read_check(32'h0000022C,read_data,32'h00020011);
-		wb_user_core_read_check(32'h00000230,read_data,32'h00020012);
-		wb_user_core_read_check(32'h00000234,read_data,32'h00020013);
-		wb_user_core_read_check(32'h00000238,read_data,32'h00020014);
-		wb_user_core_read_check(32'h0000023C,read_data,32'h00020015);
-		wb_user_core_read_check(32'h00000240,read_data,32'h00020016);
-		wb_user_core_read_check(32'h00000244,read_data,32'h00020017);
-		wb_user_core_read_check(32'h00000248,read_data,32'h00020018);
-		wb_user_core_read_check(32'h0000024C,read_data,32'h00020019);
-		wb_user_core_read_check(32'h00000250,read_data,32'h00020020);
-		wb_user_core_read_check(32'h00000254,read_data,32'h00020021);
-		wb_user_core_read_check(32'h00000258,read_data,32'h00020022);
-		wb_user_core_read_check(32'h0000025C,read_data,32'h00020023);
-		wb_user_core_read_check(32'h00000260,read_data,32'h00020024);
-		wb_user_core_read_check(32'h00000264,read_data,32'h00020025);
-		wb_user_core_read_check(32'h00000268,read_data,32'h00020026);
-		wb_user_core_read_check(32'h0000026C,read_data,32'h00020027);
-		wb_user_core_read_check(32'h00000270,read_data,32'h00020028);
-		wb_user_core_read_check(32'h00000274,read_data,32'h00020029);
-		wb_user_core_read_check(32'h00000278,read_data,32'h00020030);
-		wb_user_core_read_check(32'h0000027C,read_data,32'h00020031);
-		wb_user_core_read_check(32'h00000280,read_data,32'h00020032);
-		wb_user_core_read_check(32'h00000284,read_data,32'h00020033);
-		wb_user_core_read_check(32'h00000288,read_data,32'h00020034);
-		wb_user_core_read_check(32'h0000028C,read_data,32'h00020035);
-		wb_user_core_read_check(32'h00000290,read_data,32'h00020036);
-		wb_user_core_read_check(32'h00000294,read_data,32'h00020037);
-		wb_user_core_read_check(32'h00000298,read_data,32'h00020038);
-		wb_user_core_read_check(32'h0000029C,read_data,32'h00020039);
-		wb_user_core_read_check(32'h000002A0,read_data,32'h00020040);
-		wb_user_core_read_check(32'h000002A4,read_data,32'h00020041);
-		wb_user_core_read_check(32'h000002A8,read_data,32'h00020042);
-		wb_user_core_read_check(32'h000002AC,read_data,32'h00020043);
-		wb_user_core_read_check(32'h000002B0,read_data,32'h00020044);
-		wb_user_core_read_check(32'h000002B4,read_data,32'h00020045);
-		wb_user_core_read_check(32'h000002B8,read_data,32'h00020046);
-		wb_user_core_read_check(32'h000002BC,read_data,32'h00020047);
-		wb_user_core_read_check(32'h000002C0,read_data,32'h00020048);
-		wb_user_core_read_check(32'h000002C4,read_data,32'h00020049);
-		wb_user_core_read_check(32'h000002C8,read_data,32'h00020050);
-		wb_user_core_read_check(32'h000002CC,read_data,32'h00020051);
-		wb_user_core_read_check(32'h000002D0,read_data,32'h00020052);
-		wb_user_core_read_check(32'h000002D4,read_data,32'h00020053);
-		wb_user_core_read_check(32'h000002D8,read_data,32'h00020054);
-		wb_user_core_read_check(32'h000002DC,read_data,32'h00020055);
-		wb_user_core_read_check(32'h000002E0,read_data,32'h00020056);
-		wb_user_core_read_check(32'h000002E4,read_data,32'h00020057);
-		wb_user_core_read_check(32'h000002E8,read_data,32'h00020058);
-		wb_user_core_read_check(32'h000002EC,read_data,32'h00020059);
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h0000); // Change the Bank Sel 0000
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000200,read_data,32'h00020000);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000204,read_data,32'h00020001);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000208,read_data,32'h00020002);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000020C,read_data,32'h00020003);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000210,read_data,32'h00020004);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000214,read_data,32'h00020005);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000218,read_data,32'h00020006);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000021C,read_data,32'h00020007);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000220,read_data,32'h00020008);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000224,read_data,32'h00020009);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000228,read_data,32'h00020010);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000022C,read_data,32'h00020011);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000230,read_data,32'h00020012);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000234,read_data,32'h00020013);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000238,read_data,32'h00020014);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000023C,read_data,32'h00020015);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000240,read_data,32'h00020016);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000244,read_data,32'h00020017);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000248,read_data,32'h00020018);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000024C,read_data,32'h00020019);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000250,read_data,32'h00020020);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000254,read_data,32'h00020021);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000258,read_data,32'h00020022);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000025C,read_data,32'h00020023);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000260,read_data,32'h00020024);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000264,read_data,32'h00020025);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000268,read_data,32'h00020026);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000026C,read_data,32'h00020027);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000270,read_data,32'h00020028);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000274,read_data,32'h00020029);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000278,read_data,32'h00020030);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000027C,read_data,32'h00020031);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000280,read_data,32'h00020032);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000284,read_data,32'h00020033);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000288,read_data,32'h00020034);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000028C,read_data,32'h00020035);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000290,read_data,32'h00020036);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000294,read_data,32'h00020037);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000298,read_data,32'h00020038);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000029C,read_data,32'h00020039);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002A0,read_data,32'h00020040);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002A4,read_data,32'h00020041);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002A8,read_data,32'h00020042);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002AC,read_data,32'h00020043);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002B0,read_data,32'h00020044);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002B4,read_data,32'h00020045);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002B8,read_data,32'h00020046);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002BC,read_data,32'h00020047);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002C0,read_data,32'h00020048);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002C4,read_data,32'h00020049);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002C8,read_data,32'h00020050);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002CC,read_data,32'h00020051);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002D0,read_data,32'h00020052);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002D4,read_data,32'h00020053);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002D8,read_data,32'h00020054);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002DC,read_data,32'h00020055);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002E0,read_data,32'h00020056);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002E4,read_data,32'h00020057);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002E8,read_data,32'h00020058);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002EC,read_data,32'h00020059);
 
 		repeat (10) @(posedge clock);
 		$display("#############################################");
 		$display("  Page Read through Indirect Access           ");
 		$display("#############################################");
-                wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10
-		wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001});
-		wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'hF0,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB});
-		wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000200);
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'hF0,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000200);
 
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020000);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020001);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020002);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020003);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020004);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020005);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020006);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020007);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020008);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020009);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020010);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020011);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020012);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020013);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020014);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020015);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020016);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020017);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020018);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020019);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020020);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020021);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020022);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020023);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020024);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020025);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020026);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020027);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020028);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020029);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020030);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020031);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020032);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020033);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020034);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020035);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020036);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020037);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020038);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020039);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020040);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020041);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020042);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020043);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020044);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020045);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020046);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020047);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020048);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020049);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020050);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020051);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020052);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020053);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020054);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020055);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020056);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020057);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020058);
-		wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020059);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020000);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020001);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020002);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020003);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020004);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020005);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020006);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020007);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020008);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020009);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020010);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020011);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020012);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020013);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020014);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020015);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020016);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020017);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020018);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020019);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020020);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020021);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020022);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020023);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020024);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020025);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020026);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020027);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020028);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020029);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020030);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020031);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020032);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020033);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020034);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020035);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020036);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020037);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020038);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020039);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020040);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020041);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020042);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020043);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020044);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020045);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020046);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020047);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020048);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020049);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020050);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020051);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020052);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020053);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020054);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020055);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020056);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020057);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020058);
+		wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020059);
 
 		repeat (100) @(posedge clock);
 			// $display("+1000 cycles");
@@ -1415,4 +1397,5 @@
 `endif
 **/
 endmodule
+`include "s25fl256s.sv"
 `default_nettype wire
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
index 4d4e731..c9e68da 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v
+++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -74,9 +74,9 @@
 
 `timescale 1 ns / 1 ns
 
-`include "s25fl256s.sv"
 `include "uprj_netlists.v"
 `include "mt48lc8m8a2.v"
+`include "user_reg_map.v"
 
 `define ADDR_SPACE_PINMUX  32'h3002_0000
 module user_risc_boot_tb;
@@ -142,17 +142,17 @@
 		$display("Monitor: Standalone User Risc Boot Test Started");
 
 		// Remove Wb Reset
-		wb_user_core_write('h3080_0000,'h1);
+		wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
 
 	        repeat (2) @(posedge clock);
 		#1;
 		// Remove all the reset
 		if(d_risc_id == 0) begin
 		     $display("STATUS: Working with Risc core 0");
-                     wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h11F);
+                     wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
 		end else begin
 		     $display("STATUS: Working with Risc core 1");
-                     wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h21F);
+                     wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
 		end
 
 
@@ -174,22 +174,22 @@
                 // 0x3000002C = 0x66778899; 
 
                 test_fail = 0;
-		wb_user_core_read(32'h30020058,read_data);
+		wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data);
 		if(read_data != 32'h11223344) test_fail = 1;
 
-		wb_user_core_read(32'h3002005C,read_data);
+		wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data);
 		if(read_data != 32'h22334455) test_fail = 1;
 
-		wb_user_core_read(32'h30020060,read_data);
+		wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data);
 	        if(read_data != 32'h33445566) test_fail = 1;
 
-		wb_user_core_read(32'h30020064,read_data);
+		wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data);
                 if(read_data!= 32'h44556677) test_fail = 1;
 
-		wb_user_core_read(32'h30020068,read_data);
+		wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data);
                 if(read_data!= 32'h55667788) test_fail = 1;
 
-		wb_user_core_read(32'h3002006C,read_data) ;
+		wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data) ;
 	        if(read_data != 32'h66778899) test_fail = 1;
 
 	   
@@ -405,4 +405,5 @@
 `endif
 **/
 endmodule
+`include "s25fl256s.sv"
 `default_nettype wire
diff --git a/verilog/dv/user_sspi/user_sspi_tb.v b/verilog/dv/user_sspi/user_sspi_tb.v
index 8330de7..512e40d 100644
--- a/verilog/dv/user_sspi/user_sspi_tb.v
+++ b/verilog/dv/user_sspi/user_sspi_tb.v
@@ -66,16 +66,13 @@
 
 `timescale 1 ns / 1 ns
 
-// Note in caravel, 0x30XX_XXXX only come to user interface
-// So, using wb_host bank select we have changing MSB address [31:24] = 0x10
-`define ADDR_SPACE_UART    32'h3001_0000
-`define ADDR_SPACE_SSPI    32'h3001_00C0
-`define ADDR_SPACE_PINMUX  32'h3002_0000
 
 `define TB_GLBL    user_sspi_tb
 
 `include "uprj_netlists.v"
 `include "is62wvs1288.v"
+`include "user_reg_map.v"
+
 
 
 module user_sspi_tb;
@@ -141,23 +138,23 @@
 		$display("Monitor: Standalone User Risc Boot Test Started");
 
 		// Remove Wb Reset
-		wb_user_core_write('h3080_0000,'h1);
+		wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
 
                 // Enable SPI Multi Functional Ports
-                wb_user_core_write(`ADDR_SPACE_PINMUX+'h0038,'h400);
+                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h400);
 
 	        repeat (2) @(posedge clock);
 		#1;
 
                 // Remove the reset
 		// Remove WB and SPI/UART Reset, Keep CORE under Reset
-                wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h01F);
+                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h01F);
 
 
 		test_fail = 0;
 		sspi_init();
 	        repeat (200) @(posedge clock);
-                wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
                 $display("############################################");
                 $display("   Testing IS62/65WVS1288GALL SSRAM Read/Write Access       ");
                 $display("############################################");
diff --git a/verilog/dv/user_timer/Makefile b/verilog/dv/user_timer/Makefile
new file mode 100644
index 0000000..cda351b
--- /dev/null
+++ b/verilog/dv/user_timer/Makefile
@@ -0,0 +1,97 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+## Caravel Pointers
+CARAVEL_ROOT ?= ../../../caravel
+CARAVEL_PATH ?= $(CARAVEL_ROOT)
+CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
+CARAVEL_VERILOG_PATH  = $(CARAVEL_PATH)/verilog
+CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
+CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+
+
+## User Project Pointers
+UPRJ_VERILOG_PATH ?= ../../../verilog
+UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
+UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
+UPRJ_BEHAVIOURAL_MODELS = ../model
+UPRJ_BEHAVIOURAL_AGENTS = ../agents
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
+UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/i2cm/src/includes
+UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
+
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware
+GCC64_PREFIX?=riscv64-unknown-elf
+
+## RISCV GCC 
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=/opt/pdk/sky130A
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+
+.SUFFIXES:
+
+PATTERN = user_timer
+
+all:  ${PATTERN:=.vcd}
+
+
+vvp:  ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+ifeq ($(SIM),RTL)
+   ifeq ($(DUMP),OFF)
+	iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
+	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) \
+	-I $(UPRJ_INCLUDE_PATH3) \
+	$< -o $@ 
+    else  
+	iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
+	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) \
+	-I $(UPRJ_INCLUDE_PATH3) \
+	$< -o $@ 
+   endif
+else  
+	iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
+	$< -o $@ 
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+%.hex: 
+	echo @"This is user boot test, noting to compile the mangment core code"
+
+
+# ---- Clean ----
+
+clean:
+	rm -f *.vvp *.vcd *.log *.fst
+
+.PHONY: clean hex all
diff --git a/verilog/dv/user_timer/user_timer_tb.v b/verilog/dv/user_timer/user_timer_tb.v
new file mode 100644
index 0000000..f2d7f11
--- /dev/null
+++ b/verilog/dv/user_timer/user_timer_tb.v
@@ -0,0 +1,488 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  Standalone User validation Test bench                       ////
+////                                                              ////
+////  This file is part of the YIFive cores project               ////
+////  https://github.com/dineshannayya/yifive_r0.git              ////
+////  http://www.opencores.org/cores/yifive/                      ////
+////                                                              ////
+////  Description                                                 ////
+////   This is a standalone test bench to validate the            ////
+////   timer interfaface through External WB i/F.                 ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision :                                                  ////
+////    0.1 - 01 Oct 2021, Dinesh A                               ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+`default_nettype wire
+
+`timescale 1 ns / 1 ns
+
+`define TB_GLBL    user_timer_tb
+
+`include "uprj_netlists.v"
+`include "user_reg_map.v"
+
+
+module user_timer_tb;
+	reg clock;
+	reg wb_rst_i;
+	reg power1, power2;
+	reg power3, power4;
+
+        reg        wbd_ext_cyc_i;  // strobe/request
+        reg        wbd_ext_stb_i;  // strobe/request
+        reg [31:0] wbd_ext_adr_i;  // address
+        reg        wbd_ext_we_i;  // write
+        reg [31:0] wbd_ext_dat_i;  // data output
+        reg [3:0]  wbd_ext_sel_i;  // byte enable
+
+        wire [31:0] wbd_ext_dat_o;  // data input
+        wire        wbd_ext_ack_o;  // acknowlegement
+        wire        wbd_ext_err_o;  // error
+
+	// User I/O
+	wire [37:0] io_oeb;
+	wire [37:0] io_out;
+	wire [37:0] io_in;
+
+
+	reg [1:0] spi_chip_no;
+
+	wire gpio;
+	wire [37:0] mprj_io;
+	wire [7:0] mprj_io_0;
+	reg        test_fail;
+	reg [31:0] read_data;
+	reg [31:0] OneUsPeriod;
+        integer    test_step;
+        wire       clock_mon;
+
+
+	// External clock is used by default.  Make this artificially fast for the
+	// simulation.  Normally this would be a slow clock and the digital PLL
+	// would be the fast clock.
+
+	always #12.5 clock <= (clock === 1'b0);
+
+	initial begin
+		OneUsPeriod = 1;
+		clock = 0;
+                wbd_ext_cyc_i ='h0;  // strobe/request
+                wbd_ext_stb_i ='h0;  // strobe/request
+                wbd_ext_adr_i ='h0;  // address
+                wbd_ext_we_i  ='h0;  // write
+                wbd_ext_dat_i ='h0;  // data output
+                wbd_ext_sel_i ='h0;  // byte enable
+	end
+
+	`ifdef WFDUMP
+	   initial begin
+	   	$dumpfile("simx.vcd");
+	   	$dumpvars(1, `TB_GLBL);
+	   	$dumpvars(0, `TB_GLBL.u_top.u_pinmux);
+	   end
+       `endif
+
+	initial begin
+		$dumpon;
+
+		#200; // Wait for reset removal
+	        repeat (10) @(posedge clock);
+		$display("Monitor: Standalone User Risc Boot Test Started");
+
+		// Remove Wb Reset
+		wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+
+	        repeat (2) @(posedge clock);
+		#1;
+
+                // Remove the reset
+		// Remove WB and SPI/UART Reset, Keep CORE under Reset
+                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h01F);
+
+		// config 1us based on system clock - 1000/25ns = 40 
+                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG1,39);
+
+		// Enable Timer Interrupt
+                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR_MSK,'h700);
+
+		test_fail = 0;
+	        repeat (200) @(posedge clock);
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 10
+
+	        $display("Step-1, Timer-0: 1us * 100 = 100us; Timer-1: 200us; Timer-2: 300us");
+	        test_step = 1;
+                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER0,'h0001_0063);
+                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER1,'h0001_00C7);
+                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER2,'h0001_012B);
+	        timer_monitor(OneUsPeriod*100,OneUsPeriod*200,OneUsPeriod*300);
+
+		$display("Checking the Timer Interrupt generation and clearing");
+
+		// Disable the Timer - To avoid multiple interrupt generation
+		// during status check and interrupt clearing
+                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER0,'h0000_0063);
+                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER1,'h0000_00C7);
+                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER2,'h0000_012B);
+
+                wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data);
+		if((u_top.u_pinmux.irq_lines[10:8] == 3'b111) && (read_data[10:8] == 3'b111)) begin
+		    $display("STATUS: Timer Interrupt detected ");
+		    // Clearing the Timer Interrupt
+                    wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,'h700);
+                    wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data);
+		    if((u_top.u_pinmux.irq_lines[10:8] == 3'b111) && (read_data[10:8] == 3'b000)) begin
+		       $display("ERROR: Timer Interrupt not cleared ");
+		       test_fail = 1;
+		    end else begin
+		       $display("STATUS: Timer Interrupt cleared ");
+		    end
+	        end else begin
+		    $display("ERROR: Timer interrupt not detected ");
+		    test_fail = 1;
+	        end
+
+	        $display("Step-2, Timer-0: 1us * 200 = 200us; Timer-1: 300us; Timer-2: 400us");
+	        test_step = 2;
+                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER0,'h0001_00C7);
+                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER1,'h0001_012B);
+                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER2,'h0001_018F);
+	        timer_monitor(OneUsPeriod*200,OneUsPeriod*300,OneUsPeriod*400);
+
+		$display("Checking the Timer Interrupt generation and clearing");
+
+		// Disable the Timer - To avoid multiple interrupt generation
+		// during status check and interrupt clearing
+                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER0,'h0000_0063);
+                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER1,'h0000_00C7);
+                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER2,'h0000_012B);
+
+                wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data);
+		if((u_top.u_pinmux.irq_lines[10:8] == 3'b111) && (read_data[10:8] == 3'b111)) begin
+		    $display("STATUS: Timer Interrupt detected ");
+		    // Clearing the Timer Interrupt
+                    wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,'h700);
+                    wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data);
+		    if((u_top.u_pinmux.irq_lines[10:8] == 3'b111) && (read_data[10:8] == 3'b000)) begin
+		       $display("ERROR: Timer Interrupt not cleared ");
+		       test_fail = 1;
+		    end else begin
+		       $display("STATUS: Timer Interrupt cleared ");
+		    end
+	        end else begin
+		    $display("ERROR: Timer interrupt not detected ");
+		    test_fail = 1;
+	        end
+
+		repeat (100) @(posedge clock);
+			// $display("+1000 cycles");
+
+          	if(test_fail == 0) begin
+		   `ifdef GL
+	    	       $display("Monitor: Timer Mode (GL) Passed");
+		   `else
+		       $display("Monitor: Timer Mode (RTL) Passed");
+		   `endif
+	        end else begin
+		    `ifdef GL
+	    	        $display("Monitor: Timer Mode (GL) Failed");
+		    `else
+		        $display("Monitor: Timer Mode (RTL) Failed");
+		    `endif
+		 end
+	    	$display("###################################################");
+	        $finish;
+	end
+
+	initial begin
+		wb_rst_i <= 1'b1;
+		#100;
+		wb_rst_i <= 1'b0;	    	// Release reset
+	end
+wire USER_VDD1V8 = 1'b1;
+wire VSS = 1'b0;
+
+wire timer_intr0 = u_top.u_pinmux.timer_intr[0];
+wire timer_intr1 = u_top.u_pinmux.timer_intr[1];
+wire timer_intr2 = u_top.u_pinmux.timer_intr[2];
+
+// Monitor the Timer interrupt interval
+task timer_monitor;
+input [31:0] timer0_period;
+input [31:0] timer1_period;
+input [31:0] timer2_period;
+begin
+   force clock_mon = timer_intr0;
+   check_clock_period("Timer0",timer0_period);
+   release clock_mon;
+
+   force clock_mon = timer_intr1;
+   check_clock_period("Timer1",timer1_period);
+   release clock_mon;
+
+   force clock_mon = timer_intr2;
+   check_clock_period("Timer1",timer2_period);
+   release clock_mon;
+
+end
+endtask
+
+
+//----------------------------------
+// Check the clock period
+//----------------------------------
+task check_clock_period;
+input [127:0] clk_name;
+input [31:0] clk_period; // in NS
+time prev_t, next_t, periodd;
+begin
+    $timeformat(-12,3,"ns",10);
+   repeat(1) @(posedge clock_mon);
+   repeat(1) @(posedge clock_mon);
+   prev_t  = $realtime;
+   repeat(2) @(posedge clock_mon);
+   next_t  = $realtime;
+   periodd = (next_t-prev_t)/2;
+   periodd = (periodd)/1e3;
+   if(clk_period != periodd) begin
+       $display("STATUS: FAIL => %s Exp Period: %d us Rxd: %d us",clk_name,clk_period,periodd);
+       test_fail = 1;
+   end else begin
+       $display("STATUS: PASS => %s  Period: %d us ",clk_name,clk_period);
+   end
+end
+endtask
+
+user_project_wrapper u_top(
+`ifdef USE_POWER_PINS
+    .vccd1(USER_VDD1V8),	// User area 1 1.8V supply
+    .vssd1(VSS),	// User area 1 digital ground
+`endif
+    .wb_clk_i        (clock),  // System clock
+    .user_clock2     (1'b1),  // Real-time clock
+    .wb_rst_i        (wb_rst_i),  // Regular Reset signal
+
+    .wbs_cyc_i   (wbd_ext_cyc_i),  // strobe/request
+    .wbs_stb_i   (wbd_ext_stb_i),  // strobe/request
+    .wbs_adr_i   (wbd_ext_adr_i),  // address
+    .wbs_we_i    (wbd_ext_we_i),  // write
+    .wbs_dat_i   (wbd_ext_dat_i),  // data output
+    .wbs_sel_i   (wbd_ext_sel_i),  // byte enable
+
+    .wbs_dat_o   (wbd_ext_dat_o),  // data input
+    .wbs_ack_o   (wbd_ext_ack_o),  // acknowlegement
+
+ 
+    // Logic Analyzer Signals
+    .la_data_in      ('1) ,
+    .la_data_out     (),
+    .la_oenb         ('0),
+ 
+
+    // IOs
+    .io_in          (io_in)  ,
+    .io_out         (io_out) ,
+    .io_oeb         (io_oeb) ,
+
+    .user_irq       () 
+
+);
+
+`ifndef GL // Drive Power for Hold Fix Buf
+    // All standard cell need power hook-up for functionality work
+    initial begin
+
+    end
+`endif    
+
+
+
+//----------------------------------------------------
+//  Task
+// --------------------------------------------------
+task test_err;
+begin
+     test_fail = 1;
+end
+endtask
+
+task wb_user_core_write;
+input [31:0] address;
+input [31:0] data;
+begin
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_adr_i =address;  // address
+  wbd_ext_we_i  ='h1;  // write
+  wbd_ext_dat_i =data;  // data output
+  wbd_ext_sel_i ='hF;  // byte enable
+  wbd_ext_cyc_i ='h1;  // strobe/request
+  wbd_ext_stb_i ='h1;  // strobe/request
+  wait(wbd_ext_ack_o == 1);
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_cyc_i ='h0;  // strobe/request
+  wbd_ext_stb_i ='h0;  // strobe/request
+  wbd_ext_adr_i ='h0;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='h0;  // data output
+  wbd_ext_sel_i ='h0;  // byte enable
+  $display("STATUS: WB USER ACCESS WRITE Address : 0x%x, Data : 0x%x",address,data);
+  repeat (2) @(posedge clock);
+end
+endtask
+
+task  wb_user_core_read;
+input [31:0] address;
+output [31:0] data;
+reg    [31:0] data;
+begin
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_adr_i =address;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='0;  // data output
+  wbd_ext_sel_i ='hF;  // byte enable
+  wbd_ext_cyc_i ='h1;  // strobe/request
+  wbd_ext_stb_i ='h1;  // strobe/request
+  wait(wbd_ext_ack_o == 1);
+  data  = wbd_ext_dat_o;  
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_cyc_i ='h0;  // strobe/request
+  wbd_ext_stb_i ='h0;  // strobe/request
+  wbd_ext_adr_i ='h0;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='h0;  // data output
+  wbd_ext_sel_i ='h0;  // byte enable
+  //$display("STATUS: WB USER ACCESS READ  Address : 0x%x, Data : 0x%x",address,data);
+  repeat (2) @(posedge clock);
+end
+endtask
+
+task  wb_user_core_read_check;
+input [31:0] address;
+output [31:0] data;
+input [31:0] cmp_data;
+reg    [31:0] data;
+begin
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_adr_i =address;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='0;  // data output
+  wbd_ext_sel_i ='hF;  // byte enable
+  wbd_ext_cyc_i ='h1;  // strobe/request
+  wbd_ext_stb_i ='h1;  // strobe/request
+  wait(wbd_ext_ack_o == 1);
+  data  = wbd_ext_dat_o;  
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_cyc_i ='h0;  // strobe/request
+  wbd_ext_stb_i ='h0;  // strobe/request
+  wbd_ext_adr_i ='h0;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='h0;  // data output
+  wbd_ext_sel_i ='h0;  // byte enable
+  if(data !== cmp_data) begin
+     $display("ERROR : WB USER ACCESS READ  Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
+     `TB_GLBL.test_fail = 1;
+  end else begin
+     $display("STATUS: WB USER ACCESS READ  Address : 0x%x, Data : 0x%x",address,data);
+  end
+  repeat (2) @(posedge clock);
+end
+endtask
+
+
+`ifdef GL
+
+wire        wbd_spi_stb_i   = u_top.u_spi_master.wbd_stb_i;
+wire        wbd_spi_ack_o   = u_top.u_spi_master.wbd_ack_o;
+wire        wbd_spi_we_i    = u_top.u_spi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i   = u_top.u_spi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i   = u_top.u_spi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o   = u_top.u_spi_master.wbd_dat_o;
+wire [3:0]  wbd_spi_sel_i   = u_top.u_spi_master.wbd_sel_i;
+
+wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb.reg_cs;
+wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb.reg_ack;
+wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb.reg_wr;
+wire [7:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb.reg_addr;
+wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb.reg_wdata;
+wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb.reg_rdata;
+wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb.reg_be;
+
+`endif
+
+/**
+`ifdef GL
+//-----------------------------------------------------------------------------
+// RISC IMEM amd DMEM Monitoring TASK
+//-----------------------------------------------------------------------------
+
+`define RISC_CORE  user_uart_tb.u_top.u_core.u_riscv_top
+
+always@(posedge `RISC_CORE.wb_clk) begin
+    if(`RISC_CORE.wbd_imem_ack_i)
+          $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
+    if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
+          $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
+    if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
+          $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
+end
+
+`endif
+**/
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index 32abd1a..b4bfa74 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -74,14 +74,9 @@
 
 `timescale 1 ns / 1 ns
 
-`include "s25fl256s.sv"
 `include "uprj_netlists.v"
-`include "mt48lc8m8a2.v"
 `include "uart_agent.v"
-
-
-`define ADDR_SPACE_UART    32'h3001_0000
-`define ADDR_SPACE_PINMUX  32'h3002_0000
+`include "user_reg_map.v"
 
 
 module user_uart_tb;
@@ -180,20 +175,20 @@
    $display("Monitor: Standalone User Uart Test Started");
    
    // Remove Wb Reset
-   wb_user_core_write('h3080_0000,'h1);
+   wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
 
    // Enable UART Multi Functional Ports
-   wb_user_core_write(`ADDR_SPACE_PINMUX+'h0038,'h100);
+   wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h100);
    
    repeat (2) @(posedge clock);
    #1;
    // Remove all the reset
    if(d_risc_id == 0) begin
 	$display("STATUS: Working with Risc core 0");
-	wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h11F);
+	wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
    end else begin
 	$display("STATUS: Working with Risc core 1");
-	wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h21F);
+	wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
    end
 
    repeat (100) @(posedge clock);  // wait for Processor Get Ready
@@ -466,4 +461,5 @@
 `endif
 **/
 endmodule
+`include "s25fl256s.sv"
 `default_nettype wire
diff --git a/verilog/dv/user_uart_master/user_uart_master_tb.v b/verilog/dv/user_uart_master/user_uart_master_tb.v
index d41ff59..3f4f16e 100644
--- a/verilog/dv/user_uart_master/user_uart_master_tb.v
+++ b/verilog/dv/user_uart_master/user_uart_master_tb.v
@@ -68,6 +68,8 @@
 
 `include "uprj_netlists.v"
 `include "uart_agent.v"
+`include "user_reg_map.v"
+
 
 
 `define ADDR_SPACE_UART    32'h3001_0000
@@ -192,7 +194,7 @@
 
 
    // Remove Wb Reset
-   uartm_reg_write('h3080_0000,'h1);
+   uartm_reg_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
 
    repeat (2) @(posedge clock);
    #1;
@@ -200,19 +202,19 @@
    $display("Monitor: Writing  expected value");
    
    test_fail = 0;
-   uartm_reg_write(32'h30020058,32'h11223344);
-   uartm_reg_write(32'h3002005C,32'h22334455);
-   uartm_reg_write(32'h30020060,32'h33445566);
-   uartm_reg_write(32'h30020064,32'h44556677);
-   uartm_reg_write(32'h30020068,32'h55667788);
-   uartm_reg_write(32'h3002006C,32'h66778899);
+   uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,32'h11223344);
+   uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,32'h22334455);
+   uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,32'h33445566);
+   uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,32'h44556677);
+   uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,32'h55667788);
+   uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,32'h66778899);
 
-   uartm_reg_read_check(32'h30020058,32'h11223344);
-   uartm_reg_read_check(32'h3002005C,32'h22334455);
-   uartm_reg_read_check(32'h30020060,32'h33445566);
-   uartm_reg_read_check(32'h30020064,32'h44556677);
-   uartm_reg_read_check(32'h30020068,32'h55667788);
-   uartm_reg_read_check(32'h3002006C,32'h66778899);
+   uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,32'h11223344);
+   uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,32'h22334455);
+   uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,32'h33445566);
+   uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,32'h44556677);
+   uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,32'h55667788);
+   uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,32'h66778899);
    
    
    
diff --git a/verilog/dv/user_usb/user_usb_tb.v b/verilog/dv/user_usb/user_usb_tb.v
index 73e2b47..96f1446 100644
--- a/verilog/dv/user_usb/user_usb_tb.v
+++ b/verilog/dv/user_usb/user_usb_tb.v
@@ -40,16 +40,10 @@
 
 `timescale 1 ns / 1 ns
 
-// Note in caravel, 0x30XX_XXXX only come to user interface
-// So, using wb_host bank select we have changing MSB address [31:24] = 0x10
-`define ADDR_SPACE_UART    32'h3001_0000
-`define ADDR_SPACE_USB     32'h3001_0080
-`define ADDR_SPACE_SSPI    32'h3001_00C0
-`define ADDR_SPACE_PINMUX  32'h3002_0000
-
 `define TB_GLBL    user_usb_tb
 `define USB_BFM    u_usb_agent
 
+`include "user_reg_map.v"
 `include "uprj_netlists.v"
 `include "usb_agents.v"
 `include "test_control.v"
@@ -176,22 +170,22 @@
 		wb_user_core_write('h3080_0000,'h1);
 
                 // Enable SPI Multi Functional Ports
-                wb_user_core_write(`ADDR_SPACE_PINMUX+'h0038,'h400);
+                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h400);
 
 	        repeat (2) @(posedge clock);
 		#1;
          
 	        // Set USB clock : 192/4 = 48Mhz	
-                wb_user_core_write('h3080_0000,{8'h82,4'h0,8'h0,4'h0,8'h01});
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h82,4'h0,8'h0,4'h0,8'h01});
 
                 // Remove the reset
 		// Remove WB and SPI/UART Reset, Keep CORE under Reset
-                wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h03F);
+                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h03F);
 
 
 		test_fail = 0;
 	        repeat (200) @(posedge clock);
-                wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 10
 
 
 		//usb_test1;
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile
index 7b5585e..887f270 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/wb_port/Makefile
@@ -14,84 +14,188 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 
-## PDK 
-PDK_PATH = $(PDK_ROOT)/sky130A
 
-## Caravel Pointers
-CARAVEL_ROOT ?= ../../../caravel
-CARAVEL_PATH ?= $(CARAVEL_ROOT)
-CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
-CARAVEL_VERILOG_PATH  = $(CARAVEL_PATH)/verilog
-CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
-CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+ 
+PWDD := $(shell pwd)
+BLOCKS := $(shell basename $(PWDD))
 
-## User Project Pointers
-UPRJ_VERILOG_PATH ?= ../../../verilog
-UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
-UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
-UPRJ_BEHAVIOURAL_MODELS = ../
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr2c/src/includes
-UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
-UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
-UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
-UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include
-## RISCV GCC 
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-GCC64_PREFIX?=riscv64-unknown-elf
+# ---- Include Partitioned Makefiles ----
 
-## Simulation mode: RTL/GL
-SIM_DEFINES = -DFUNCTIONAL -DSIM
+CONFIG = caravel_user_project
+
+########################################################
+#include $(MCW_ROOT)/verilog/dv/make/env.makefile
+########################################################
+#######################################################################
+## Global Environment Variables for local repo  
+#######################################################################
+
+export PDK_PATH =      $(PDK_ROOT)/sky130A
+export VIP_PATH =      $(CORE_VERILOG_PATH)/dv/vip
+export FIRMWARE_PATH = $(CORE_VERILOG_PATH)/dv/firmware
+
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+export CARAVEL_VERILOG_PATH ?=  $(CARAVEL_ROOT)/verilog
+export CORE_VERILOG_PATH    ?=  $(CARAVEL_ROOT)/mgmt_core_wrapper/verilog
+export USER_PROJECT_VERILOG ?=  $(DESIGNS)/verilog
+
+export CARAVEL_PATH = $(CARAVEL_VERILOG_PATH)
+export VERILOG_PATH = $(CORE_VERILOG_PATH)
+
+#######################################################################
+## Compiler Information 
+#######################################################################
+
+export GCC_PATH?=      $(TOOLS)/bin
+export GCC_PREFIX?=    riscv32-unknown-linux-gnu
+
+
+
+
+
+
+
+
+########################################################
+#include $(MCW_ROOT)/verilog/dv/make/var.makefile
+########################################################
+
+CPU=vexriscv
+CPUFAMILY=riscv
+CPUFLAGS=-march=rv32i      -mabi=ilp32 -D__vexriscv__
+CPUENDIANNESS=little
+CLANG=0
+
+
+######################################################
+# include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
+######################################################
+
+ifeq ($(CPU),picorv32)
+	LINKER_SCRIPT=$(FIRMWARE_PATH)/sections.lds
+	SOURCE_FILES=$(FIRMWARE_PATH)/start.s 
+	VERILOG_FILES=
+endif
+
+ifeq ($(CPU),ibex)
+	LINKER_SCRIPT=$(FIRMWARE_PATH)/link_ibex.ld
+	SOURCE_FILES=$(FIRMWARE_PATH)/crt0_ibex.S $(FIRMWARE_PATH)/simple_system_common.c
+# 	VERILOG_FILES=../ibex/*
+	VERILOG_FILES=
+endif
+
+ifeq ($(CPU),vexriscv)
+# 	LINKER_SCRIPT=$(FIRMWARE_PATH)/sections_vexriscv.lds
+# 	SOURCE_FILES=$(FIRMWARE_PATH)/start_caravel_vexriscv.s
+	LINKER_SCRIPT=$(FIRMWARE_PATH)/sections.lds
+	SOURCE_FILES=$(FIRMWARE_PATH)/crt0_vex.S $(FIRMWARE_PATH)/isr.c
+	VERILOG_FILES=
+endif
+
+
+
+#####################################################
+#include $(MCW_ROOT)/verilog/dv/make/sim.makefile
+######################################################
+
+export IVERILOG_DUMPER = fst
+
+# RTL/GL/GL_SDF
 SIM?=RTL
 DUMP?=OFF
 
+
 .SUFFIXES:
 
-PATTERN = wb_port
 
-all:  ${PATTERN:=.vcd}
+all:  ${BLOCKS:=.vcd} ${BLOCKS:=.lst}
 
-hex:  ${PATTERN:=.hex}
+hex:  ${BLOCKS:=.hex}
 
-vvp:  ${PATTERN:=.vvp}
+#.SUFFIXES:
+
+##############################################################################
+# Comiple firmeware
+##############################################################################
+%.elf: %.c $(LINKER_SCRIPT) $(SOURCE_FILES)
+	${GCC_PATH}/${GCC_PREFIX}-gcc -g \
+	-I$(FIRMWARE_PATH) \
+	-I$(VERILOG_PATH)/dv/generated \
+	-I$(VERILOG_PATH)/dv/ \
+	-I$(VERILOG_PATH)/common \
+	  $(CPUFLAGS) \
+	-Wl,-Bstatic,-T,$(LINKER_SCRIPT),--strip-debug \
+	-ffreestanding -nostdlib -o $@ $(SOURCE_FILES) $<
+
+%.lst: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objdump -d -S $< > $@
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -ie 's/@10/@00/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+	
+	
+##############################################################################
+# Runing the simulations
+##############################################################################
 
 %.vvp: %_tb.v %.hex
+
+## RTL
 ifeq ($(SIM),RTL)
    ifeq ($(DUMP),OFF)
-	iverilog -g2005-sv $(SIM_DEFINES) -I $(PDK_PATH) \
-	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
-	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
-	-I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \
-	$< -o $@ 
+	iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+        -f$(VERILOG_PATH)/includes/includes.rtl.caravel \
+        -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $<
     else  
-	iverilog -g2005-sv -DWFDUMP $(SIM_DEFINES) -I $(PDK_PATH) \
-	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
-	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
-	-I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \
-	$< -o $@ 
+	iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+        -f$(VERILOG_PATH)/includes/includes.rtl.caravel \
+        -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $<
    endif
-else  
-	iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
-	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_GL_PATH)  -I$(UPRJ_RTL_PATH)  -I $(UPRJ_VERILOG_PATH) \
-	$< -o $@ 
+endif 
+
+## GL
+ifeq ($(SIM),GL)
+    ifeq ($(CONFIG),caravel_user_project)
+		iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+        -f$(VERILOG_PATH)/includes/includes.gl.caravel \
+        -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $<
+    else
+		iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+        -f$(VERILOG_PATH)/includes/includes.gl.$(CONFIG) \
+		-f$(CARAVEL_PATH)/gl/__user_project_wrapper.v -o $@ $<
+    endif
+endif 
+
+## GL+SDF
+ifeq ($(SIM),GL_SDF)
+    ifeq ($(CONFIG),caravel_user_project)
+		cvc64  +interp \
+		+define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY +define+ENABLE_SDF \
+		+change_port_type +dump2fst +fst+parallel2=on   +nointeractive +notimingchecks +mipdopt \
+		-f $(VERILOG_PATH)/includes/includes.gl+sdf.caravel \
+		-f $(USER_PROJECT_VERILOG)/includes/includes.gl+sdf.$(CONFIG) $<
+	else
+		cvc64  +interp \
+		+define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY +define+ENABLE_SDF \
+		+change_port_type +dump2fst +fst+parallel2=on   +nointeractive +notimingchecks +mipdopt \
+		-f $(VERILOG_PATH)/includes/includes.gl+sdf.$(CONFIG) \
+		-f $CARAVEL_PATH/gl/__user_project_wrapper.v $<
+    endif
 endif
 
 %.vcd: %.vvp
-	vvp $<
+	vvp  $<
 
-%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s 
-	${GCC64_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
-	${GCC64_PREFIX}-objcopy -O verilog $< $@ 
-	# to fix flash base address
-	sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
-	${GCC64_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+# twinwave: RTL-%.vcd GL-%.vcd
+#     twinwave RTL-$@ * + GL-$@ *
 
 check-env:
 ifndef PDK_ROOT
@@ -100,17 +204,24 @@
 ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
 	$(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
 endif
-#ifeq (,$(wildcard $(GCC64_PREFIX)-gcc ))
-#	$(error $(GCC64_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
-#endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+	$(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
 # check for efabless style installation
 ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
 SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
 endif
 
+
 # ---- Clean ----
 
 clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+	\rm  -f *.elf *.hex *.bin *.vvp *.log *.vcd *.lst *.hexe
 
 .PHONY: clean hex all
+
+
+
+
+
+
diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c
index fdddf4f..910e933 100644
--- a/verilog/dv/wb_port/wb_port.c
+++ b/verilog/dv/wb_port/wb_port.c
@@ -16,41 +16,16 @@
  */
 
 // This include is relative to $CARAVEL_PATH (see Makefile)
-#include "verilog/dv/caravel/defs.h"
-#include "verilog/dv/caravel/stub.c"
+#include <defs.h>
+#include <stub.c>
+#include "../c_func/inc/user_reg_map.h"
 
 // User Project Slaves (0x3000_0000)
 #define reg_mprj_slave (*(volatile uint32_t*)0x30000000)
 
-#define reg_mprj_wbhost_reg0 (*(volatile uint32_t*)0x30800000)
-#define reg_mprj_globl_reg0  (*(volatile uint32_t*)0x30020000)
-#define reg_mprj_globl_reg1  (*(volatile uint32_t*)0x30020004)
-#define reg_mprj_globl_reg2  (*(volatile uint32_t*)0x30020008)
-#define reg_mprj_globl_reg3  (*(volatile uint32_t*)0x3002000C)
-#define reg_mprj_globl_reg4  (*(volatile uint32_t*)0x30020010)
-#define reg_mprj_globl_reg5  (*(volatile uint32_t*)0x30020014)
-#define reg_mprj_globl_reg6  (*(volatile uint32_t*)0x30020018)
-#define reg_mprj_globl_reg7  (*(volatile uint32_t*)0x3002001C)
-#define reg_mprj_globl_reg8  (*(volatile uint32_t*)0x30020020)
-#define reg_mprj_globl_reg9  (*(volatile uint32_t*)0x30020024)
-#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x30020028)
-#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x3002002C)
-#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x30020030)
-#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x30020034)
-#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x30020038)
-#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x3002003C)
-#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x30020040)
-#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x30020044)
-#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x30020048)
-#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x3002004C)
-#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x30020050)
-#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x30020054)
-#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x30020058)
-#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x3002005C)
-#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x30020060)
-#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x30020064)
-#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x30020068)
-#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x3002006C)
+#define reg_mprj_wbhost_reg0 (*(volatile uint32_t*)0x30080000)
+
+
 
 
 /*
@@ -82,7 +57,9 @@
 	/* Set up the housekeeping SPI to be connected internally so	*/
 	/* that external pin changes don't affect it.			*/
 
-	reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
+    reg_spi_enable = 1;
+    reg_wb_enable = 1;
+	// reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
                                         // connect to housekeeping SPI
 
 	// Connect the housekeeping SPI to the SPI master
@@ -121,31 +98,30 @@
     reg_mprj_wbhost_reg0 = 0x1;
 
     // Remove Reset
-    reg_mprj_globl_reg2 = 0x01F;
+    reg_pinmux_gbl_cfg0 = 0x01f;
 
-    if (reg_mprj_globl_reg0 != 0x82682301) bFail = 1;
-    if (reg_mprj_globl_reg1 != 0xA55AA55A) bFail = 1;
+    if (reg_pinmux_chip_id != 0x82682301) bFail = 1;
 
-    // Write software Write & Read Register
-    reg_mprj_globl_reg22  = 0x11223344; 
-    reg_mprj_globl_reg23  = 0x22334455; 
-    reg_mprj_globl_reg24  = 0x33445566; 
-    reg_mprj_globl_reg25  = 0x44556677; 
-    reg_mprj_globl_reg26  = 0x55667788; 
-    reg_mprj_globl_reg27  = 0x66778899; 
+    // write software write & read Register
+    reg_pinmux_soft_reg_1  = 0x11223344; 
+    reg_pinmux_soft_reg_2  = 0x22334455; 
+    reg_pinmux_soft_reg_3  = 0x33445566; 
+    reg_pinmux_soft_reg_4  = 0x44556677; 
+    reg_pinmux_soft_reg_5  = 0x55667788; 
+    reg_pinmux_soft_reg_6  = 0x66778899; 
 
 
-    if (reg_mprj_globl_reg22  != 0x11223344) bFail = 1;
+    if (reg_pinmux_soft_reg_1  != 0x11223344) bFail = 1;
     if (bFail == 1) reg_mprj_datal = 0xAB610000;
-    if (reg_mprj_globl_reg23  != 0x22334455) bFail = 1;
+    if (reg_pinmux_soft_reg_2  != 0x22334455) bFail = 1;
     if (bFail == 1) reg_mprj_datal = 0xAB620000;
-    if (reg_mprj_globl_reg24  != 0x33445566) bFail = 1;
+    if (reg_pinmux_soft_reg_3  != 0x33445566) bFail = 1;
     if (bFail == 1) reg_mprj_datal = 0xAB630000;
-    if (reg_mprj_globl_reg25  != 0x44556677) bFail = 1;
+    if (reg_pinmux_soft_reg_4  != 0x44556677) bFail = 1;
     if (bFail == 1) reg_mprj_datal = 0xAB640000;
-    if (reg_mprj_globl_reg26 != 0x55667788) bFail = 1;
+    if (reg_pinmux_soft_reg_5 != 0x55667788) bFail = 1;
     if (bFail == 1) reg_mprj_datal = 0xAB650000;
-    if (reg_mprj_globl_reg27 != 0x66778899) bFail = 1;
+    if (reg_pinmux_soft_reg_6 != 0x66778899) bFail = 1;
     if (bFail == 1) reg_mprj_datal = 0xAB660000;
 
     if(bFail == 0) {
diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v
index 2f7099e..fdbbf92 100644
--- a/verilog/dv/wb_port/wb_port_tb.v
+++ b/verilog/dv/wb_port/wb_port_tb.v
@@ -17,12 +17,6 @@
 
 `timescale 1 ns / 1 ps
 
-`define FULL_CHIP_SIM
-
-`include "uprj_netlists.v"
-`include "caravel_netlists.v"
-`include "spiflash.v"
-
 module wb_port_tb;
 	reg clock;
 	reg RSTB;
@@ -53,7 +47,7 @@
 	initial begin
 		$dumpfile("simx.vcd");
 		$dumpvars(1, wb_port_tb);
-		$dumpvars(2, wb_port_tb.uut);
+		//$dumpvars(0, wb_port_tb.uut.soc);
 		//$dumpvars(1, wb_port_tb.uut.mprj);
 		$dumpvars(1, wb_port_tb.uut.mprj.u_wb_host);
 		$dumpvars(2, wb_port_tb.uut.mprj.u_pinmux);
@@ -64,7 +58,7 @@
 
 		// Repeat cycles of 1000 clock edges as needed to complete testbench
 		repeat (30) begin
-			repeat (1000) @(posedge clock);
+			repeat (2000) @(posedge clock);
 			// $display("+1000 cycles");
 		end
 		$display("%c[1;31m",27);
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
new file mode 100644
index 0000000..5d917ec
--- /dev/null
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -0,0 +1,111 @@
+# Caravel user project includes
++incdir+$(USER_PROJECT_VERILOG)/rtl/i2cm/src/includes
++incdir+$(USER_PROJECT_VERILOG)/rtl/usb1_host/src/includes
++incdir+$(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/includes
++incdir+$(USER_PROJECT_VERILOG)/dv/model
++incdir+$(USER_PROJECT_VERILOG)/dv/agents
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux_reg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/gpio_intr.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pwm.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/timer.sv
+-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type1.sv
+-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type2.sv
+-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_top.sv
+-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_if.sv
+-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_fifo.sv
+-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_regs.sv
+-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_clkgen.sv
+-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_ctrl.sv
+-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_rx.sv
+-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_tx.sv
+-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_core.sv
+-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_cfg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_rxfsm.sv
+-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_txfsm.sv
+-v $(USER_PROJECT_VERILOG)/rtl/lib/async_fifo_th.sv  
+-v $(USER_PROJECT_VERILOG)/rtl/lib/reset_sync.sv  
+-v $(USER_PROJECT_VERILOG)/rtl/lib/double_sync_low.v  
+-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_buf.v  
+-v $(USER_PROJECT_VERILOG)/rtl/i2cm/src/core/i2cm_bit_ctrl.v
+-v $(USER_PROJECT_VERILOG)/rtl/i2cm/src/core/i2cm_byte_ctrl.v
+-v $(USER_PROJECT_VERILOG)/rtl/i2cm/src/core/i2cm_top.v
+-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_core.sv
+-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_crc16.sv
+-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_crc5.sv
+-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_fifo.sv
+-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_sie.sv
+-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/phy/usb_fs_phy.v
+-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/phy/usb_transceiver.v
+-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/top/usb1_host.sv
+-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_top.sv  
+-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_ctl.sv  
+-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_if.sv
+-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_cfg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv
+-v $(USER_PROJECT_VERILOG)/rtl/lib/async_fifo.sv  
+-v $(USER_PROJECT_VERILOG)/rtl/lib/registers.v
+-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_ctl.v
+-v $(USER_PROJECT_VERILOG)/rtl/lib/ser_inf_32b.sv
+-v $(USER_PROJECT_VERILOG)/rtl/lib/ser_shift.sv
+-v $(USER_PROJECT_VERILOG)/rtl/digital_core/src/glbl_cfg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/wb_host/src/wb_host.sv
+-v $(USER_PROJECT_VERILOG)/rtl/lib/async_wb.sv
+-v $(USER_PROJECT_VERILOG)/rtl/lib/sync_wbb.sv
+-v $(USER_PROJECT_VERILOG)/rtl/lib/sync_fifo2.sv
+-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_arb.sv
+-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_slave_port.sv
+-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_interconnect.sv
+
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_hdu.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_tdu.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_ipic.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_csr.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_exu.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_ialu.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_idu.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_ifu.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_lsu.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_mprf.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_mul.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_div.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_top.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/primitives/ycr_reset_cells.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/primitives/ycr_cg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/ycr_clk_ctrl.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/ycr_tapc_shift_reg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/ycr_tapc.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/ycr_tapc_synchronizer.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/ycr_core_top.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/ycr_dm.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/ycr_dmi.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/ycr_scu.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_imem_router.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_dmem_router.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_dp_memory.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_tcm.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_timer.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_dmem_wb.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_imem_wb.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr2_mcore_router.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr2_intf.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr2_mintf.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr2_top_wb.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_icache_router.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_dcache_router.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/cache/src/core/icache_top.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/cache/src/core/icache_app_fsm.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/cache/src/core/icache_tag_fifo.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/cache/src/core/dcache_tag_fifo.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/cache/src/core/dcache_top.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/lib/ycr_async_wbb.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/lib/ycr_arb.sv
+
+-v $(USER_PROJECT_VERILOG)/rtl/lib/sync_fifo.sv
+-v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart2wb.sv 
+-v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart2_core.sv 
+-v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart_msg_handler.v 
+-v $(USER_PROJECT_VERILOG)/rtl/lib/async_reg_bus.sv
+-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v
+-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_skew_adjust.gv
+-v $(USER_PROJECT_VERILOG)/rtl/lib/ctech_cells.sv
diff --git a/verilog/rtl/lib/pulse_gen_type1.sv b/verilog/rtl/lib/pulse_gen_type1.sv
index 838fe03..a0c260f 100644
--- a/verilog/rtl/lib/pulse_gen_type1.sv
+++ b/verilog/rtl/lib/pulse_gen_type1.sv
@@ -5,7 +5,7 @@
 //------------------------------------------------------------------------
 
 module pulse_gen_type1(
-	output logic clk_pulse,
+	output logic clk_pulse_o,
 
 	input logic clk,
         input logic reset_n,
@@ -17,7 +17,7 @@
 
 logic [WD-1:0]  cnt;
 
-assign clk_pulse = (cnt == 0) && trigger;
+assign clk_pulse_o = (cnt == 0) && trigger;
 
 always @ (posedge clk or negedge reset_n)
 begin
diff --git a/verilog/rtl/lib/pulse_gen_type2.sv b/verilog/rtl/lib/pulse_gen_type2.sv
index 9bc759e..c438d34 100644
--- a/verilog/rtl/lib/pulse_gen_type2.sv
+++ b/verilog/rtl/lib/pulse_gen_type2.sv
@@ -5,7 +5,7 @@
 
 module pulse_gen_type2 #(parameter WD = 10)
     (
-	output logic           clk_pulse,
+	output logic           clk_pulse_o,
 
 	input logic            clk,
         input logic            reset_n,
@@ -19,15 +19,15 @@
 always @ (posedge clk or negedge reset_n)
 begin
    if (reset_n == 1'b0) begin 
-      cnt <= 'b0;
-      clk_pulse <= 'b0;
+      cnt             <= 'b0;
+      clk_pulse_o     <= 'b0;
    end else begin 
       if(cnt == cfg_max_cnt) begin
-          cnt       <= 0;
-          clk_pulse <= 1'b1;
+          cnt         <= 0;
+          clk_pulse_o <= 1'b1;
       end else begin
-          cnt       <= cnt +1;
-          clk_pulse <= 1'b0;
+          cnt         <= cnt +1;
+          clk_pulse_o   <= 1'b0;
       end
    end
 end
diff --git a/verilog/rtl/pinmux/src/gpio_intr.sv b/verilog/rtl/pinmux/src/gpio_intr.sv
index 331918d..9bcefee 100644
--- a/verilog/rtl/pinmux/src/gpio_intr.sv
+++ b/verilog/rtl/pinmux/src/gpio_intr.sv
@@ -1,6 +1,6 @@
 
 // GPIO Interrupt Generation
-module gpio_intr (
+module gpio_intr_gen (
    input  logic         mclk                     ,// System clk
    input  logic         h_reset_n                ,// system reset
    input  logic [31:0]  gpio_prev_indata         ,// previously captured GPIO I/P pins data
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv
index 4446c89..aed3a9d 100755
--- a/verilog/rtl/pinmux/src/pinmux.sv
+++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -73,7 +73,6 @@
                        output logic            reg_ack,
 
 		      // Risc configuration
-                       output logic [31:0]     fuse_mhartid,
                        output logic [15:0]     irq_lines,
                        output logic            soft_irq,
                        output logic [2:0]      user_irq,
@@ -135,13 +134,25 @@
 
 
 
+logic sreset_n;  // Sync Reset
    
 /* clock pulse */
 //********************************************************
-logic           pulse1u_mclk            ;// 1 UsSecond Pulse for waveform Generator
-logic           pulse1s_mclk            ;// 1Second Pulse for waveform Generator
-logic [9:0]     cfg_pulse_1us           ;// 1us pulse generation config
-                
+logic           pulse_1us               ; // 1 UsSecond Pulse for waveform Generator
+logic           pulse_1ms               ; // 1 UsSecond Pulse for waveform Generator
+logic           pulse_1s                ; // 1Second Pulse for waveform Generator
+logic [9:0]     cfg_pulse_1us           ; // 1us pulse generation config
+
+
+//---------------------------------------------------------
+// Timer Register                          
+// -------------------------------------------------------
+logic [2:0]    cfg_timer_update        ; // CPU write to timer register
+logic [31:0]   cfg_timer0              ; // Timer-0 register
+logic [31:0]   cfg_timer1              ; // Timer-1 register
+logic [31:0]   cfg_timer2              ; // Timer-2 register
+logic [2:0]    timer_intr              ;
+
 //---------------------------------------------------
 // 6 PWM variabled
 //---------------------------------------------------
@@ -218,11 +229,18 @@
 	       .clk_out    (wbd_clk_pinmux              ) 
        );
 
-gpio_intr u_gpio_intr (
+reset_sync  u_rst_sync (
+	      .scan_mode  (1'b0        ),
+              .dclk       (mclk        ), // Destination clock domain
+	      .arst_n     (h_reset_n   ), // active low async reset
+              .srst_n     (sreset_n    )
+          );
+
+gpio_intr_gen u_gpio_intr (
    // System Signals
    // Inputs
           .mclk                    (mclk                    ),
-          .h_reset_n               (h_reset_n               ),
+          .h_reset_n               (sreset_n                ),
 
    // GPIO cfg input pins
           .gpio_prev_indata        (gpio_prev_indata        ),
@@ -242,38 +260,102 @@
 // 1us pulse
 pulse_gen_type2  #(.WD(10)) u_pulse_1us (
 
-	.clk_pulse                 (pulse1u_mclk),
-	.clk                       (mclk        ),
-        .reset_n                   (h_reset_n   ),
-	.cfg_max_cnt               (cfg_pulse_1us)
+	.clk_pulse_o               (pulse_1us        ),
+	.clk                       (mclk             ),
+        .reset_n                   (sreset_n         ),
+	.cfg_max_cnt               (cfg_pulse_1us    )
 
      );
 
 // 1millisecond pulse
 pulse_gen_type1 u_pulse_1ms (
 
-	.clk_pulse   (pulse1m_mclk),
-	.clk         (mclk        ),
-        .reset_n     (h_reset_n   ),
-	.trigger     (pulse1u_mclk)
+	.clk_pulse_o               (pulse_1ms       ),
+	.clk                       (mclk            ),
+        .reset_n                   (sreset_n        ),
+	.trigger                   (pulse_1us       )
 
       );
 
 // 1 second pulse
-pulse_gen_type2 u_pulse_1s (
+pulse_gen_type1 u_pulse_1s (
 
-	.clk_pulse   (pulse1s_mclk),
-	.clk         (mclk        ),
-        .reset_n     (h_reset_n   ),
-	.cfg_max_cnt (cfg_pulse_1us)
+	.clk_pulse_o               (pulse_1s    ),
+	.clk                       (mclk        ),
+        .reset_n                   (sreset_n    ),
+	.trigger                   (pulse_1ms   )
 
        );
 
+
+// Timer
+
+wire       cfg_timer0_enb    = cfg_timer0[16];
+wire [1:0] cfg_timer0_clksel = cfg_timer0[18:17];
+wire [15:0] cfg_timer0_compare = cfg_timer0[15:0];
+
+timer  u_timer_0
+  (
+     .reset_n                      (sreset_n             ),// system syn reset
+     .mclk                         (mclk                 ),// master clock
+     .pulse_1us                    (pulse_1us            ),
+     .pulse_1ms                    (pulse_1ms            ),
+     .pulse_1s                     (pulse_1s             ),
+
+     .cfg_timer_update             (cfg_timer_update[0]  ), 
+     .cfg_timer_enb                (cfg_timer0_enb       ),     
+     .cfg_timer_compare            (cfg_timer0_compare   ),
+     .cfg_timer_clksel             (cfg_timer0_clksel    ),// to select the timer 1us/1ms reference clock
+
+     .timer_intr                   (timer_intr[0]         )
+   );
+
+// Timer
+wire       cfg_timer1_enb      = cfg_timer1[16];
+wire [1:0] cfg_timer1_clksel   = cfg_timer1[18:17];
+wire [15:0] cfg_timer1_compare = cfg_timer1[15:0];
+timer  u_timer_1
+  (
+     .reset_n                      (sreset_n             ),// system syn reset
+     .mclk                         (mclk                 ),// master clock
+     .pulse_1us                    (pulse_1us            ),
+     .pulse_1ms                    (pulse_1ms            ),
+     .pulse_1s                     (pulse_1s             ),
+
+     .cfg_timer_update             (cfg_timer_update[1]  ), 
+     .cfg_timer_enb                (cfg_timer1_enb       ),     
+     .cfg_timer_compare            (cfg_timer1_compare   ),
+     .cfg_timer_clksel             (cfg_timer1_clksel    ),// to select the timer 1us/1ms reference clock
+
+     .timer_intr                   (timer_intr[1]         )
+   );
+
+// Timer
+wire       cfg_timer2_enb    = cfg_timer2[16];
+wire [1:0] cfg_timer2_clksel = cfg_timer2[18:17];
+wire [15:0] cfg_timer2_compare = cfg_timer2[15:0];
+timer  u_timer_2
+  (
+     .reset_n                      (sreset_n             ),// system syn reset
+     .mclk                         (mclk                 ),// master clock
+     .pulse_1us                    (pulse_1us            ),
+     .pulse_1ms                    (pulse_1ms            ),
+     .pulse_1s                     (pulse_1s             ),
+
+     .cfg_timer_update             (cfg_timer_update[2]  ), 
+     .cfg_timer_enb                (cfg_timer2_enb       ),     
+     .cfg_timer_compare            (cfg_timer2_compare   ),
+     .cfg_timer_clksel             (cfg_timer2_clksel    ),// to select the timer 1us/1ms reference clock
+
+     .timer_intr                   (timer_intr[2]        )
+   );
+
+
 pinmux_reg u_pinmux_reg(
       // System Signals
       // Inputs
           .mclk                         (mclk                    ),
-          .h_reset_n                    (h_reset_n               ),
+          .h_reset_n                    (sreset_n                ),
 
           .cpu_core_rst_n               (cpu_core_rst_n          ),
           .cpu_intf_rst_n               (cpu_intf_rst_n          ),
@@ -298,7 +380,6 @@
 
 	  .ext_intr_in                  (ext_intr_in             ),
 
-	  .fuse_mhartid                 (fuse_mhartid            ),
 	  .irq_lines                    (irq_lines               ),
 	  .soft_irq                     (soft_irq                ),
 	  .user_irq                     (user_irq                ),
@@ -338,22 +419,13 @@
        // Outputs
           .gpio_prev_indata             (gpio_prev_indata        ) ,
 
-       // BIST I/F
-          .bist_en                      (                        ),
-          .bist_run                     (                        ),
-          .bist_load                    (                        ),
-          
-          .bist_sdi                     (                        ),
-          .bist_shift                   (                        ),
-          .bist_sdo                     ('b0                     ),
-          
-          .bist_done                    ('b0                     ),
-          .bist_error                   ('h0                     ),
-          .bist_correct                 ('h0                     ),
-          .bist_error_cnt0              ('h0                     ),
-          .bist_error_cnt1              ('h0                     ),
-          .bist_error_cnt2              ('h0                     ),
-          .bist_error_cnt3              ('h0                     )
+
+          .timer_intr                   (timer_intr             ),
+          .cfg_timer_update             (cfg_timer_update       ),
+          .cfg_timer0                   (cfg_timer0             ),
+          .cfg_timer1                   (cfg_timer1             ),
+          .cfg_timer2                   (cfg_timer2             )
+
 
    ); 
 
@@ -361,9 +433,9 @@
 // 6 PWM Waveform Generator
 pwm  u_pwm_0 (
 	  .waveform                    (pwm_wfm[0]         ), 
-	  .h_reset_n                   (h_reset_n          ),
+	  .h_reset_n                   (sreset_n           ),
 	  .mclk                        (mclk               ),
-	  .pulse1m_mclk                (pulse1m_mclk       ),
+	  .pulse1m_mclk                (pulse_1ms          ),
 	  .cfg_pwm_enb                 (cfg_pwm_enb[0]     ),
 	  .cfg_pwm_high                (cfg_pwm0_high      ),
 	  .cfg_pwm_low                 (cfg_pwm0_low       )
@@ -371,9 +443,9 @@
 
 pwm  u_pwm_1 (
 	  .waveform                    (pwm_wfm[1]         ), 
-	  .h_reset_n                   (h_reset_n          ),
+	  .h_reset_n                   (sreset_n           ),
 	  .mclk                        (mclk               ),
-	  .pulse1m_mclk                (pulse1m_mclk       ),
+	  .pulse1m_mclk                (pulse_1ms          ),
 	  .cfg_pwm_enb                 (cfg_pwm_enb[1]     ),
 	  .cfg_pwm_high                (cfg_pwm1_high      ),
 	  .cfg_pwm_low                 (cfg_pwm1_low       )
@@ -381,9 +453,9 @@
    
 pwm  u_pwm_2 (
 	  .waveform                    (pwm_wfm[2]         ), 
-	  .h_reset_n                   (h_reset_n          ),
+	  .h_reset_n                   (sreset_n           ),
 	  .mclk                        (mclk               ),
-	  .pulse1m_mclk                (pulse1m_mclk       ),
+	  .pulse1m_mclk                (pulse_1ms          ),
 	  .cfg_pwm_enb                 (cfg_pwm_enb[2]     ),
 	  .cfg_pwm_high                (cfg_pwm2_high      ),
 	  .cfg_pwm_low                 (cfg_pwm2_low       )
@@ -391,27 +463,27 @@
 
 pwm  u_pwm_3 (
 	  .waveform                    (pwm_wfm[3]         ), 
-	  .h_reset_n                   (h_reset_n          ),
+	  .h_reset_n                   (sreset_n           ),
 	  .mclk                        (mclk               ),
-	  .pulse1m_mclk                (pulse1m_mclk       ),
+	  .pulse1m_mclk                (pulse_1ms          ),
 	  .cfg_pwm_enb                 (cfg_pwm_enb[3]     ),
 	  .cfg_pwm_high                (cfg_pwm3_high      ),
 	  .cfg_pwm_low                 (cfg_pwm3_low       )
      );
 pwm  u_pwm_4 (
 	  .waveform                    (pwm_wfm[4]         ), 
-	  .h_reset_n                   (h_reset_n          ),
+	  .h_reset_n                   (sreset_n           ),
 	  .mclk                        (mclk               ),
-	  .pulse1m_mclk                (pulse1m_mclk       ),
+	  .pulse1m_mclk                (pulse_1ms          ),
 	  .cfg_pwm_enb                 (cfg_pwm_enb[4]     ),
 	  .cfg_pwm_high                (cfg_pwm4_high      ),
 	  .cfg_pwm_low                 (cfg_pwm4_low       )
      );
 pwm  u_pwm_5 (
 	  .waveform                    (pwm_wfm[5]         ), 
-	  .h_reset_n                   (h_reset_n          ),
+	  .h_reset_n                   (sreset_n           ),
 	  .mclk                        (mclk               ),
-	  .pulse1m_mclk                (pulse1m_mclk       ),
+	  .pulse1m_mclk                (pulse_1ms          ),
 	  .cfg_pwm_enb                 (cfg_pwm_enb[5]     ),
 	  .cfg_pwm_high                (cfg_pwm5_high      ),
 	  .cfg_pwm_low                 (cfg_pwm5_low       )
@@ -599,7 +671,7 @@
 
      //Pin-5        PD3/INT1/OC2B(PWM0)  digital_io[4]
      if(cfg_pwm_enb[0])              digital_io_out[4]   = pwm_wfm[0];
-     if(cfg_port_d_dir_sel[3])       digital_io_out[4]   = port_d_out[3];
+     else if(cfg_port_d_dir_sel[3])  digital_io_out[4]   = port_d_out[3];
 
      //Pin-6        PD4                 digital_io[5]
      if(cfg_port_d_dir_sel[4])       digital_io_out[5]   = port_d_out[4];
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv
index 64f99c7..d340fc6 100644
--- a/verilog/rtl/pinmux/src/pinmux_reg.sv
+++ b/verilog/rtl/pinmux/src/pinmux_reg.sv
@@ -65,7 +65,6 @@
 		       input  logic [1:0]      ext_intr_in,
 
 		      // Risc configuration
-                       output logic [31:0]     fuse_mhartid,
                        output logic [15:0]     irq_lines,
                        output logic            soft_irq,
                        output logic [2:0]      user_irq,
@@ -108,25 +107,13 @@
                        output  logic [31:0]     cfg_multi_func_sel       ,// multifunction pins
                         
                        // Outputs
-                       output logic [31:0]      gpio_prev_indata,       // prv data from GPIO I/P pins
+                       output logic [31:0]      gpio_prev_indata         ,// prv data from GPIO I/P pins
 
-		// BIST I/F
-	               output logic             bist_en,
-	               output logic             bist_run,
-	               output logic             bist_load,
-
-	               output logic             bist_sdi,
-	               output logic             bist_shift,
-	               input  logic             bist_sdo,
-
-	               input logic              bist_done,
-	               input logic [3:0]        bist_error,
-	               input logic [3:0]        bist_correct,
-	               input logic [3:0]        bist_error_cnt0,
-	               input logic [3:0]        bist_error_cnt1,
-	               input logic [3:0]        bist_error_cnt2,
-	               input logic [3:0]        bist_error_cnt3
-
+		       input   logic [2:0]      timer_intr               ,
+                       output  logic [2:0]      cfg_timer_update         ,
+                       output  logic [31:0]     cfg_timer0               ,      
+                       output  logic [31:0]     cfg_timer1               ,      
+                       output  logic [31:0]     cfg_timer2               
    ); 
 
 
@@ -170,6 +157,9 @@
 logic [31:0]    reg_25; // Software-Reg4
 logic [31:0]    reg_26; // Software-Reg5
 logic [31:0]    reg_27; // Software-Reg6
+logic [31:0]    reg_28; // Software-Reg6
+logic [31:0]    reg_29; // Software-Reg6
+logic [31:0]    reg_30; // Software-Reg6
 
 
 logic           cs_int;
@@ -205,23 +195,12 @@
 assign wb_req_pedge = (wb_req_d ==0) && (wb_req==1'b1);
 
 
-//-----------------------------------------------------------------
-// Reg 4/5 are BIST Serial I/F register and it takes minimum 32
-// cycle to respond ACK back
-// ----------------------------------------------------------------
-wire ser_acc     = sw_wr_en_30 | sw_rd_en_31;
-wire non_ser_acc = reg_cs ? !ser_acc : 1'b0;
-wire serial_ack;
-
 always @ (posedge mclk or negedge h_reset_n)
 begin : preg_out_Seq
    if (h_reset_n == 1'b0) begin
       reg_rdata  <= 'h0;
       reg_ack    <= 1'b0;
-   end else if (ser_acc && serial_ack)  begin
-      reg_rdata <= serail_dout ;
-      reg_ack   <= 1'b1;
-   end else if (non_ser_acc && !reg_ack) begin
+   end else if (reg_cs && !reg_ack) begin
       reg_rdata <= reg_out ;
       reg_ack   <= 1'b1;
    end else begin
@@ -278,6 +257,7 @@
 // Individual register assignments
 //-----------------------------------------------------------------------
 
+
 // Chip ID
 // chip-id[3:0] mapping
 //    0 -  YIFIVE (MPW-2)
@@ -293,11 +273,22 @@
 assign reg_0 = {manu_id,total_core,chip_id,chip_rev};
 
 
-//-----------------------------------------------------------------------
-//   reg-1, reset value = 32'hA55A_A55A
-//   -----------------------------------------------------------------
+//------------------------------------------
+// reg-2: GLBL_CFG_0
+//------------------------------------------
+wire [31:0] cfg_glb_ctrl = reg_1;
 
-gen_32b_reg  #(32'hA55A_A55A) u_reg_1	(
+ctech_buf u_buf_cpu_intf_rst  (.A(cfg_glb_ctrl[0]),.X(cpu_intf_rst_n));
+ctech_buf u_buf_qspim_rst     (.A(cfg_glb_ctrl[1]),.X(qspim_rst_n));
+ctech_buf u_buf_sspim_rst     (.A(cfg_glb_ctrl[2]),.X(sspim_rst_n));
+ctech_buf u_buf_uart_rst      (.A(cfg_glb_ctrl[3]),.X(uart_rst_n));
+ctech_buf u_buf_i2cm_rst      (.A(cfg_glb_ctrl[4]),.X(i2cm_rst_n));
+ctech_buf u_buf_usb_rst       (.A(cfg_glb_ctrl[5]),.X(usb_rst_n));
+
+ctech_buf u_buf_cpu0_rst      (.A(cfg_glb_ctrl[8]),.X(cpu_core_rst_n[0]));
+ctech_buf u_buf_cpu1_rst      (.A(cfg_glb_ctrl[9]),.X(cpu_core_rst_n[1]));
+
+gen_32b_reg  #(32'h0) u_reg_1	(
 	      //List of Inputs
 	      .reset_n    (h_reset_n     ),
 	      .clk        (mclk          ),
@@ -309,22 +300,9 @@
 	      .data_out   (reg_1         )
 	      );
 
-assign fuse_mhartid = reg_1;
-
-//------------------------------------------
+//----------------------------------------------
 // reg-2: GLBL_CFG_1
 //------------------------------------------
-wire [31:0] cfg_glb_ctrl = reg_2;
-
-ctech_buf u_buf_cpu_intf_rst  (.A(cfg_glb_ctrl[0]),.X(cpu_intf_rst_n));
-ctech_buf u_buf_qspim_rst     (.A(cfg_glb_ctrl[1]),.X(qspim_rst_n));
-ctech_buf u_buf_sspim_rst     (.A(cfg_glb_ctrl[2]),.X(sspim_rst_n));
-ctech_buf u_buf_uart_rst      (.A(cfg_glb_ctrl[3]),.X(uart_rst_n));
-ctech_buf u_buf_i2cm_rst      (.A(cfg_glb_ctrl[4]),.X(i2cm_rst_n));
-ctech_buf u_buf_usb_rst       (.A(cfg_glb_ctrl[5]),.X(usb_rst_n));
-
-ctech_buf u_buf_cpu0_rst      (.A(cfg_glb_ctrl[8]),.X(cpu_core_rst_n[0]));
-ctech_buf u_buf_cpu1_rst      (.A(cfg_glb_ctrl[9]),.X(cpu_core_rst_n[1]));
 
 gen_32b_reg  #(32'h0) u_reg_2	(
 	      //List of Inputs
@@ -338,9 +316,12 @@
 	      .data_out   (reg_2         )
 	      );
 
-//----------------------------------------------
-// reg-3: GLBL_CFG_1
-//------------------------------------------
+assign cfg_pulse_1us       = reg_2[9:0];
+assign cfg_riscv_debug_sel = reg_2[31:30];
+
+//-----------------------------------------------------------------------
+//   reg-3 : Global Interrupt Mask
+//-----------------------------------------------------------------------
 
 gen_32b_reg  #(32'h0) u_reg_3	(
 	      //List of Inputs
@@ -354,8 +335,58 @@
 	      .data_out   (reg_3         )
 	      );
 
-assign cfg_pulse_1us       = reg_3[9:0];
-assign cfg_riscv_debug_sel = reg_3[31:30];
+//-----------------------------------------------------------------------
+//   reg-4 : Global Interrupt Status
+//-----------------------------------------------------------------
+assign  irq_lines     = reg_3[15:0] & reg_4[15:0]; 
+assign  soft_irq      = reg_3[16]   & reg_4[16]; 
+assign  user_irq      = reg_3[19:17]& reg_4[19:17]; 
+
+
+generic_register #(8,0  ) u_reg4_be0 (
+	      .we            ({8{sw_wr_en_4 & 
+                                 wr_be[0]   }}   ),		 
+	      .data_in       (sw_reg_wdata[7:0]  ),
+	      .reset_n       (h_reset_n          ),
+	      .clk           (mclk               ),
+	      
+	      //List of Outs
+	      .data_out      (reg_4[7:0]         )
+          );
+
+
+wire [7:0] hware_intr_req = {gpio_intr, ext_intr_in[1:0], usb_intr, i2cm_intr,timer_intr[2:0]};
+
+generic_intr_stat_reg #(.WD(8),
+	                .RESET_DEFAULT(0)) u_reg4_be1 (
+		 //inputs
+		 .clk         (mclk              ),
+		 .reset_n     (h_reset_n         ),
+	         .reg_we      ({8{sw_wr_en_4 & reg_ack & 
+                                 wr_be[1]   }}  ),		 
+		 .reg_din    (sw_reg_wdata[15:8] ),
+		 .hware_req  (hware_intr_req     ),
+		 
+		 //outputs
+		 .data_out    (reg_4[15:8]       )
+	      );
+
+
+
+generic_register #(4,0  ) u_reg4_be2 (
+	      .we            ({4{sw_wr_en_4 & 
+                                 wr_be[2]   }}  ),		 
+	      .data_in       (sw_reg_wdata[19:16]),
+	      .reset_n       (h_reset_n           ),
+	      .clk           (mclk              ),
+	      
+	      //List of Outs
+	      .data_out      (reg_4[19:16]        )
+          );
+
+assign reg_4[31:20] = '0;
+
+
 //-----------------------------------------------------------------------
 // Logic for gpio_data_in 
 //-----------------------------------------------------------------------
@@ -365,41 +396,25 @@
 always @ (posedge mclk or negedge h_reset_n)
 begin 
   if (h_reset_n == 1'b0) begin
-    reg_4  <= 'h0 ;
+    reg_5  <= 'h0 ;
     gpio_in_data_s  <= 32'd0;
     gpio_in_data_ss <= 32'd0;
   end
   else begin
     gpio_in_data_s   <= gpio_in_data;
     gpio_in_data_ss <= gpio_in_data_s;
-    reg_4           <= gpio_in_data_ss;
+    reg_5           <= gpio_in_data_ss;
   end
 end
 
 
-assign cfg_gpio_data_in = reg_4[31:0]; // to be used for edge interrupt detect
+assign cfg_gpio_data_in = reg_5[31:0]; // to be used for edge interrupt detect
 assign gpio_prev_indata = gpio_in_data_ss;
 
 //-----------------------------------------------------------------------
 // Logic for cfg_gpio_out_data 
 //-----------------------------------------------------------------------
-assign cfg_gpio_out_data = reg_5[31:0]; // data to the GPIO control blk 
-
-gen_32b_reg  #(32'h0) u_reg_5	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_5    ),
-	      .we         (wr_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_5         )
-	      );
-//-----------------------------------------------------------------------
-// Logic for cfg_gpio_dir_sel 
-//-----------------------------------------------------------------------
-assign cfg_gpio_dir_sel = reg_6[31:0]; // data to the GPIO O/P pins 
+assign cfg_gpio_out_data = reg_6[31:0]; // data to the GPIO control blk 
 
 gen_32b_reg  #(32'h0) u_reg_6	(
 	      //List of Inputs
@@ -413,9 +428,9 @@
 	      .data_out   (reg_6         )
 	      );
 //-----------------------------------------------------------------------
-// Logic for cfg_gpio_out_type 
+// Logic for cfg_gpio_dir_sel 
 //-----------------------------------------------------------------------
-assign cfg_gpio_out_type = reg_7[31:0]; // to be used for read
+assign cfg_gpio_dir_sel = reg_7[31:0]; // data to the GPIO O/P pins 
 
 gen_32b_reg  #(32'h0) u_reg_7	(
 	      //List of Inputs
@@ -428,54 +443,23 @@
 	      //List of Outs
 	      .data_out   (reg_7         )
 	      );
-
-
 //-----------------------------------------------------------------------
-//   reg-8
-//-----------------------------------------------------------------
-assign  irq_lines     = reg_8[15:0]; 
-assign  soft_irq      = reg_8[16]; 
-assign  user_irq      = reg_8[19:17]; 
+// Logic for cfg_gpio_out_type 
+//-----------------------------------------------------------------------
+assign cfg_gpio_out_type = reg_8[31:0]; // to be used for read
 
-
-generic_register #(8,0  ) u_reg8_be0 (
-	      .we            ({8{sw_wr_en_8 & 
-                                 wr_be[0]   }}   ),		 
-	      .data_in       (sw_reg_wdata[7:0]  ),
-	      .reset_n       (h_reset_n          ),
-	      .clk           (mclk               ),
+gen_32b_reg  #(32'h0) u_reg_8	(
+	      //List of Inputs
+	      .reset_n    (h_reset_n     ),
+	      .clk        (mclk          ),
+	      .cs         (sw_wr_en_8    ),
+	      .we         (wr_be         ),		 
+	      .data_in    (sw_reg_wdata  ),
 	      
 	      //List of Outs
-	      .data_out      (reg_8[7:0]         )
-          );
+	      .data_out   (reg_8         )
+	      );
 
-generic_register #(3,0  ) u_reg8_be1_1 (
-	      .we            ({3{sw_wr_en_8 & 
-                                 wr_be[1]   }}   ),		 
-	      .data_in       (sw_reg_wdata[10:8] ),
-	      .reset_n       (h_reset_n          ),
-	      .clk           (mclk               ),
-	      
-	      //List of Outs
-	      .data_out      (reg_8[10:8]        )
-          );
-
-
-assign reg_8[15:11] = {gpio_intr, ext_intr_in[1:0], usb_intr, i2cm_intr};
-
-
-generic_register #(4,0  ) u_reg8_be2 (
-	      .we            ({4{sw_wr_en_8 & 
-                                 wr_be[2]   }}  ),		 
-	      .data_in       (sw_reg_wdata[19:16]),
-	      .reset_n       (h_reset_n           ),
-	      .clk           (mclk              ),
-	      
-	      //List of Outs
-	      .data_out      (reg_8[19:16]        )
-          );
-
-assign reg_8[31:20] = '0;
 
 
 //-----------------------------------------------------------------------
@@ -497,67 +481,29 @@
 //	    Interrupt posting is higher priority than int clear by host 
 //--------------------------------------------------------
 wire [31:0] gpio_int_status = reg_9;				      
-always @(posedge mclk or negedge h_reset_n)
-begin
-   if(~h_reset_n)
-   begin
-      reg_9[31:0]   <= 32'h0;
-   end
-   else
-   begin
-      if(sw_wr_en_9 && wr_be[0])
-      begin
-         reg_9[7:0] <=  ((~sw_reg_wdata[7:0] & gpio_int_status[7:0]) | gpio_int_event[7:0]);
-      end
-      else if(sw_wr_en_10 && wr_be[0]) 
-      begin
-         reg_9[7:0] <= ((sw_reg_wdata[7:0] | gpio_int_status[7:0]) | gpio_int_event[7:0]);
-      end
-      else
-      begin
-         reg_9[7:0] <=   (gpio_int_status[7:0] | gpio_int_event[7:0]);
-      end
 
-      if(sw_wr_en_9 && wr_be[1])
-      begin
-         reg_9[15:8] <=  ((~sw_reg_wdata[15:8] & gpio_int_status[15:8]) | gpio_int_event[15:8]);
-      end
-      else if(sw_wr_en_10 && wr_be[1]) 
-      begin
-         reg_9[15:8] <= ((sw_reg_wdata[15:8] | gpio_int_status[15:8]) | gpio_int_event[15:8]);
-      end
-      else
-      begin
-         reg_9[15:8] <=   (gpio_int_status[15:8] | gpio_int_event[15:8]);
-      end
-
-      if(sw_wr_en_9 && wr_be[2])
-      begin
-         reg_9[23:16] <=  ((~sw_reg_wdata[23:16] & gpio_int_status[23:16]) | gpio_int_event[23:16]);
-      end
-      else if(sw_wr_en_10 && wr_be[2]) 
-      begin
-         reg_9[23:16] <= ((sw_reg_wdata[23:16] | gpio_int_status[23:16]) | gpio_int_event[23:16]);
-      end
-      else
-      begin
-         reg_9[23:16] <=   (gpio_int_status[23:16] | gpio_int_event[23:16]);
-      end
-
-      if(sw_wr_en_9 && wr_be[3])
-      begin
-         reg_9[31:24] <=  ((~sw_reg_wdata[31:24] & gpio_int_status[31:24]) | gpio_int_event[31:24]);
-      end
-      else if(sw_wr_en_10 && wr_be[3]) 
-      begin
-         reg_9[31:24] <= ((sw_reg_wdata[31:24] | gpio_int_status[31:24]) | gpio_int_event[31:24]);
-      end
-      else
-      begin
-         reg_9[31:24] <=   (gpio_int_status[31:24] | gpio_int_event[31:24]);
-      end
-   end
-end
+generic_intr_stat_reg #(.WD(32),
+	                .RESET_DEFAULT(0))  u_reg_9 (
+		 //inputs
+		 .clk         (mclk              ),
+		 .reset_n     (h_reset_n         ),
+	         .reg_we      ({
+		               {8{sw_wr_en_9 & reg_ack & wr_be[2]}},
+		               {8{sw_wr_en_9 & reg_ack & wr_be[2]}},
+		               {8{sw_wr_en_9 & reg_ack & wr_be[1]}},
+		               {8{sw_wr_en_9 & reg_ack & wr_be[0]}}
+		               }  ),		 
+		 .reg_din    (sw_reg_wdata[31:0] ),
+		 .hware_req  (gpio_int_event | {
+		               {8{sw_wr_en_10 & reg_ack}} & sw_reg_wdata[31:24],
+		               {8{sw_wr_en_10 & reg_ack}} & sw_reg_wdata[23:16],
+		               {8{sw_wr_en_10 & reg_ack}} & sw_reg_wdata[15:8] ,
+		               {8{sw_wr_en_10 & reg_ack}} & sw_reg_wdata[7:0]   
+		               }     ),
+		 
+		 //outputs
+		 .data_out    (reg_9[31:0]       )
+	      );
 //-------------------------------------------------
 // Returns same value as interrupt status register
 //------------------------------------------------
@@ -769,7 +715,7 @@
 //-----------------------------------------
 // Software Reg-2, Release date: <DAY><MONTH><YEAR>
 // ----------------------------------------
-gen_32b_reg  #(32'h1003_2022) u_reg_23	(
+gen_32b_reg  #(32'h1603_2022) u_reg_23	(
 	      //List of Inputs
 	      .reset_n    (h_reset_n     ),
 	      .clk        (mclk          ),
@@ -782,9 +728,9 @@
 	      );
 
 //-----------------------------------------
-// Software Reg-3: Poject Revison 3.8 = 0003800
+// Software Reg-3: Poject Revison 3.9 = 0003900
 // ----------------------------------------
-gen_32b_reg  #(32'h0003_8000) u_reg_24	(
+gen_32b_reg  #(32'h0003_9000) u_reg_24	(
 	      //List of Inputs
 	      .reset_n    (h_reset_n     ),
 	      .clk        (mclk          ),
@@ -844,8 +790,12 @@
 
 //-----------------------------------------------------------------------
 //   reg-28
+// Assumption: wr_en is two cycle and reg_ack is asserted in second cycle
+//     In first cycle, local register will be updated
+//     In second cycle, update indication sent to timer block
 //   -----------------------------------------------------------------
-logic [31:0] cfg_bist_ctrl_1;
+assign cfg_timer0          = reg_28[18:0];
+assign cfg_timer_update[0] = sw_wr_en_28 & reg_ack; 
 
 gen_32b_reg  #(32'h0) u_reg_28	(
 	      //List of Inputs
@@ -856,61 +806,51 @@
 	      .data_in    (sw_reg_wdata  ),
 	      
 	      //List of Outs
-	      .data_out   (cfg_bist_ctrl_1[31:0]  )
+	      .data_out   (reg_28[31:0]  )
 	      );
 
-
-
-assign bist_en             = cfg_bist_ctrl_1[0];
-assign bist_run            = cfg_bist_ctrl_1[1];
-assign bist_load           = cfg_bist_ctrl_1[2];
-
-
 //-----------------------------------------------------------------------
 //   reg-29
-//-----------------------------------------------------------------
-logic [31:0] cfg_bist_status_1;
+// Assumption: wr_en is two cycle and reg_ack is asserted in second cycle
+//     In first cycle, local register will be updated
+//     In second cycle, update indication sent to timer block
+//   -----------------------------------------------------------------
+assign cfg_timer1          = reg_29[18:0];
+assign cfg_timer_update[1] = sw_wr_en_29 & reg_ack;
 
-assign cfg_bist_status_1 = {  bist_error_cnt3, 1'b0, bist_correct[3], bist_error[3], bist_done,
-	                      bist_error_cnt2, 1'b0, bist_correct[2], bist_error[2], bist_done,
-	                      bist_error_cnt1, 1'b0, bist_correct[1], bist_error[1], bist_done,
-	                      bist_error_cnt0, 1'b0, bist_correct[0], bist_error[0], bist_done
-			   };
+gen_32b_reg  #(32'h0) u_reg_29	(
+	      //List of Inputs
+	      .reset_n    (h_reset_n     ),
+	      .clk        (mclk          ),
+	      .cs         (sw_wr_en_29   ),
+	      .we         (wr_be         ),		 
+	      .data_in    (sw_reg_wdata  ),
+	      
+	      //List of Outs
+	      .data_out   (reg_29[31:0]  )
+	      );
+
 
 //-----------------------------------------------------------------------
-//   reg-30 => Write to Serail I/F
-//   reg-31 => READ  from Serail I/F
-//-----------------------------------------------------------------
-logic        bist_sdi_int;
-logic        bist_shift_int;
-logic        bist_sdo_int;
-logic [31:0] serail_dout;
+//   reg-30
+// Assumption: wr_en is two cycle and reg_ack is asserted in second cycle
+//     In first cycle, local register will be updated
+//     In second cycle, update indication sent to timer block
+//   -----------------------------------------------------------------
+assign cfg_timer2          = reg_30[18:0];
+assign cfg_timer_update[2] = sw_wr_en_30 & reg_ack;
 
-assign bist_sdo_int = bist_sdo;
-assign  bist_shift = bist_shift_int;
-assign  bist_sdi   = bist_sdi_int ;
-
-ser_inf_32b u_ser_intf
-       (
-
-    // Master Port
-       .rst_n       (h_reset_n),  // Regular Reset signal
-       .clk         (mclk),  // System clock
-       .reg_wr      (sw_wr_en_30 & wb_req_pedge),  // Write Request
-       .reg_rd      (sw_rd_en_31 & wb_req_pedge),  // Read Request
-       .reg_wdata   (sw_reg_wdata) ,  // data output
-       .reg_rdata   (serail_dout),  // data input
-       .reg_ack     (serial_ack),  // acknowlegement
-
-    // Slave Port
-       .sdi         (bist_sdi_int),    // Serial SDI
-       .shift       (bist_shift_int),  // Shift Signal
-       .sdo         (bist_sdo_int) // Serial SDO
-
-    );
-
-
-
+gen_32b_reg  #(32'h0) u_reg_30	(
+	      //List of Inputs
+	      .reset_n    (h_reset_n     ),
+	      .clk        (mclk          ),
+	      .cs         (sw_wr_en_30   ),
+	      .we         (wr_be         ),		 
+	      .data_in    (sw_reg_wdata  ),
+	      
+	      //List of Outs
+	      .data_out   (reg_30[31:0]  )
+	      );
 
 //-----------------------------------------------------------------------
 // Register Read Path Multiplexer instantiation
@@ -949,10 +889,10 @@
     5'b11001 : reg_out [31:0] = reg_25 [31:0];
     5'b11010 : reg_out [31:0] = reg_26 [31:0];
     5'b11011 : reg_out [31:0] = reg_27 [31:0];
-    5'b11100 : reg_out [31:0] = cfg_bist_ctrl_1 [31:0];
-    5'b11101 : reg_out [31:0] = cfg_bist_status_1 [31:0];
-    5'b11110 : reg_out [31:0] = serail_dout [31:0]; // Previous Shift Data
-    5'b11111 : reg_out [31:0] = serail_dout [31:0]; // Latest Shift Data
+    5'b11100 : reg_out [31:0] = reg_28 [31:0];
+    5'b11101 : reg_out [31:0] = reg_29 [31:0];
+    5'b11110 : reg_out [31:0] = reg_30 [31:0]; 
+    5'b11111 : reg_out [31:0] = 32'h0;
     default  : reg_out [31:0] = 32'h0;
   endcase
 end
diff --git a/verilog/rtl/pinmux/src/timer.sv b/verilog/rtl/pinmux/src/timer.sv
new file mode 100755
index 0000000..55b7349
--- /dev/null
+++ b/verilog/rtl/pinmux/src/timer.sv
@@ -0,0 +1,66 @@
+
+module timer
+  (
+     input logic	     reset_n,	// system syn reset
+     input logic	     mclk,		// master clock
+     input logic 	     pulse_1us,
+     input logic 	     pulse_1ms,
+     input logic 	     pulse_1s,
+
+     input logic             cfg_timer_enb,     
+     input logic             cfg_timer_update, 
+     input logic [15:0]      cfg_timer_compare,
+     input logic [1:0]       cfg_timer_clksel,	// to select the timer 1us/1ms reference clock
+
+     output logic  	     timer_intr
+
+   );
+
+
+
+
+reg 		timer_hit_s1;
+wire 		timer_hit;
+reg [15:0]      timer_counter;
+wire		timer_pulse;
+
+
+// select between 1us timer and 1ms timer
+assign timer_pulse = (cfg_timer_clksel == 2'b00) ? pulse_1us : 
+	             (cfg_timer_clksel == 2'b01) ? pulse_1ms : pulse_1s;
+  
+
+/************************************************
+	Timer Counter
+************************************************/
+always @(negedge reset_n or posedge mclk)
+begin
+   if (!reset_n)
+	timer_counter <= 16'b0;
+   else if (cfg_timer_update || (timer_pulse && timer_hit))
+	timer_counter <=  cfg_timer_compare;
+   else if (timer_pulse && cfg_timer_enb)
+	timer_counter <=  timer_counter - 1;
+end
+
+
+   
+/***********************************************
+	Timer Interrupt Generation
+***********************************************/
+   assign timer_hit = (timer_counter == 1'b0);
+
+   assign timer_intr = !timer_hit_s1 && timer_hit && cfg_timer_enb;
+
+   
+   always @(negedge reset_n or posedge mclk)
+     begin
+	if (!reset_n) begin
+	   timer_hit_s1 <= 1'b1;
+        end else begin
+	   timer_hit_s1 <= timer_hit;
+	end
+     end
+
+   
+endmodule
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 6eebbd8..8cff517 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -49,6 +49,7 @@
      `include "pinmux/src/pinmux_reg.sv"
      `include "pinmux/src/gpio_intr.sv"
      `include "pinmux/src/pwm.sv"
+     `include "pinmux/src/timer.sv"
      `include "lib/pulse_gen_type1.sv"
      `include "lib/pulse_gen_type2.sv"
 
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 95a32cc..1f9418b 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -190,6 +190,12 @@
 ////    3.8  Mar 10 2022, Dinesh A                                ////
 ////         1. usb chip select bug inside uart_* wrapper         ////
 ////         2. in wb_host, increased usb clk ctrl to 4 to 8 bit  ////
+////    3.9  Mar 16 2022, Dinesh A                                ////
+////         1. 3 Timer added                                     ////
+////         2. Pinmux Register address movement                  ////
+////         3. Risc fuse_mhartid is removed and internal tied    ////
+////            inside risc core                                  ////
+////         4. caravel wb addressing issue restrict to 0x300FFFFF////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
 //// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
@@ -433,7 +439,6 @@
 wire                           wbd_clk_pinmux                         ;
 wire                           wbd_int_rst_n                          ;
 
-wire [31:0]                    fuse_mhartid                           ;
 wire [15:0]                    irq_lines                              ;
 wire                           soft_irq                               ;
 
@@ -457,7 +462,6 @@
 wire [3:0]                     cfg_cska_pinmux_rp                     ; // clock skew adjust for pinmux
 wire [3:0]                     cfg_cska_qspi_co_rp                    ; // clock skew adjust for global reg
 
-wire [31:0]                    fuse_mhartid_rp                        ; // Repeater
 wire [15:0]                    irq_lines_rp                           ; // Repeater
 wire                           soft_irq_rp                            ; // Repeater
 
@@ -678,8 +682,6 @@
           .core_clk                (cpu_clk                 ),
           .rtc_clk                 (rtc_clk                 ),
 
-    // Fuses
-          .fuse_mhartid            (fuse_mhartid_rp         ),
 
     // IRQ
           .irq_lines               (irq_lines_rp            ), 
@@ -930,7 +932,7 @@
 wb_interconnect  #(
 	`ifndef SYNTHESIS
           .CH_CLK_WD               (4                       ),
-	  .CH_DATA_WD              (69                      )
+	  .CH_DATA_WD              (37                      )
         `endif
 	) u_intercon (
 `ifdef USE_POWER_PINS
@@ -951,7 +953,6 @@
 			 
 	                              soft_irq,
 			              irq_lines[15:0],
-			              fuse_mhartid[31:0],
 
 			              cfg_cska_qspi_co[3:0],
 		                      cfg_cska_pinmux[3:0],
@@ -963,7 +964,6 @@
 
 	                              soft_irq_rp,
 			              irq_lines_rp[15:0],
-			              fuse_mhartid_rp[31:0],
 
 			              cfg_cska_qspi_co_rp[3:0],
 		                      cfg_cska_pinmux_rp[3:0],
@@ -1166,7 +1166,6 @@
 
 
        // Risc configuration
-          .fuse_mhartid            (fuse_mhartid            ),
           .irq_lines               (irq_lines               ),
           .soft_irq                (soft_irq                ),
           .user_irq                (user_irq                ),
diff --git a/verilog/rtl/user_reg_map.v b/verilog/rtl/user_reg_map.v
new file mode 100644
index 0000000..1926c76
--- /dev/null
+++ b/verilog/rtl/user_reg_map.v
@@ -0,0 +1,76 @@
+
+// Note in caravel, 0x300X_XXXX only come to user interface
+// So, using wb_host bank select we have changing MSB address [31:16] = 0x1000
+//
+`define ADDR_SPACE_QSPI    32'h3000_0000
+`define ADDR_SPACE_UART    32'h3001_0000
+`define ADDR_SPACE_I2CM    32'h3001_0040
+`define ADDR_SPACE_USB     32'h3001_0080
+`define ADDR_SPACE_SSPI    32'h3001_00C0
+`define ADDR_SPACE_PINMUX  32'h3002_0000
+`define ADDR_SPACE_WBHOST  32'h3008_0000
+
+//--------------------------------------------------
+//  WB Host Register
+//--------------------------------------------------
+`define WBHOST_GLBL_CFG           8'h00  // reg_0  - Global Config
+`define WBHOST_BANK_SEL           8'h04  // reg_1  - Bank Select
+`define WBHOST_CLK_CTRL1          8'h08  // reg_2  - Clock Control-1
+`define WBHOST_CLK_CTRL2          8'h0C  // reg_3  - Clock Control-2
+
+//--------------------------------------------------
+// Pinmux Register
+// -------------------------------------------------
+
+`define PINMUX_CHIP_ID           8'h00  // reg_0  - Chip ID
+`define PINMUX_GBL_CFG0          8'h04  // reg_1  - Global Config-2
+`define PINMUX_GBL_CFG1          8'h08  // reg_2  - Global Config-1
+`define PINMUX_GBL_INTR_MSK      8'h0C  // reg_3  - Global Interrupt Mask
+`define PINMUX_GBL_INTR          8'h10  // reg_4  - Global Interrupt
+`define PINMUX_GPIO_IDATA        8'h14  // reg_5  - GPIO Data In
+`define PINMUX_GPIO_ODATA        8'h18  // reg_6  - GPIO Data Out
+`define PINMUX_GPIO_DSEL         8'h1C  // reg_7  - GPIO Direction Select
+`define PINMUX_GPIO_TYPE         8'h20  // reg_8  - GPIO TYPE - Static/Waveform
+`define PINMUX_GPIO_INTR_STAT    8'h24  // reg_9  - GPIO Interrupt status
+`define PINMUX_GPIO_INTR_CLR     8'h24  // reg_9  - GPIO Interrupt Clear
+`define PINMUX_GPIO_INTR_SET     8'h28  // reg_10 - GPIO Interrupt Set
+`define PINMUX_GPIO_INTR_MASK    8'h2C  // reg_11 - GPIO Interrupt Mask
+`define PINMUX_GPIO_POS_INTR     8'h30  // reg_12 - GPIO Posedge Interrupt
+`define PINMUX_GPIO_NEG_INTR     8'h34  // reg_13 - GPIO Neg Interrupt
+`define PINMUX_GPIO_MULTI_FUNC   8'h38  // reg_14 - GPIO Multi Function
+`define PINMUX_SOFT_REG_0        8'h3C  // reg_15 - Soft Register
+`define PINMUX_CFG_PWM0          8'h40  // reg_16 - PWM Reg-0
+`define PINMUX_CFG_PWM1          8'h44  // reg_17 - PWM Reg-1
+`define PINMUX_CFG_PWM2          8'h48  // reg_18 - PWM Reg-2
+`define PINMUX_CFG_PWM3          8'h4C  // reg_19 - PWM Reg-3
+`define PINMUX_CFG_PWM4          8'h50  // reg_20 - PWM Reg-4
+`define PINMUX_CFG_PWM5          8'h54  // reg_21 - PWM Reg-5
+`define PINMUX_SOFT_REG_1        8'h58  // reg_22 - Sof Register
+`define PINMUX_SOFT_REG_2        8'h5C  // reg_23 - Sof Register
+`define PINMUX_SOFT_REG_3        8'h60  // reg_24 - Sof Register
+`define PINMUX_SOFT_REG_4        8'h64  // reg_25 - Sof Register
+`define PINMUX_SOFT_REG_5        8'h68  // reg_26 - Sof Register
+`define PINMUX_SOFT_REG_6        8'h6C  // reg_27 - Sof Register
+`define PINMUX_CFG_TIMER0        8'h70  // reg_28 - Timer-0
+`define PINMUX_CFG_TIMER1        8'h74  // reg_28 - Timer-1
+`define PINMUX_CFG_TIMER2        8'h78  // reg_28 - Timer-2
+
+//----------------------------------------------------------
+// QSPI Register Map
+//----------------------------------------------------------
+`define QSPIM_GLBL_CTRL          8'h00
+`define QSPIM_DMEM_G0_RD_CTRL    8'h04
+`define QSPIM_DMEM_G0_WR_CTRL    8'h08
+`define QSPIM_DMEM_G1_RD_CTRL    8'h0C
+`define QSPIM_DMEM_G1_WR_CTRL    8'h10
+
+`define QSPIM_DMEM_CS_AMAP       8'h14
+`define QSPIM_DMEM_CA_AMASK      8'h18
+
+`define QSPIM_IMEM_CTRL1         8'h1C
+`define QSPIM_IMEM_CTRL2         8'h20
+`define QSPIM_IMEM_ADDR          8'h24
+`define QSPIM_IMEM_WDATA         8'h28
+`define QSPIM_IMEM_RDATA         8'h2C
+`define QSPIM_SPI_STATUS         8'h30
+
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv
index eef549a..a5738c8 100644
--- a/verilog/rtl/wb_host/src/wb_host.sv
+++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -41,6 +41,16 @@
 ////          u_cpuclk,u_rtcclk,u_usbclk                          ////
 ////    0.3 - Nov 16 2021, Dinesh A                               ////
 ////          Wishbone out are register for better timing         ////   
+////    0.4 - Mar 15 2021, Dinesh A                               ////
+////          1. To fix the bug in caravel mgmt soc address range ////
+////          reduction to 0x3000_0000 to 0x300F_FFFF             ////
+////          Address Map has changes as follows                  ////
+////          0x3008_0000 to 0x3008_00FF - Local Wishbone Reg     ////
+////          0x3000_0000 to 0x3007_FFFF - SOC access with        ////
+////              indirect Map {Bank_Sel[15:3], wbm_adr_i[18:0]}  ////
+////          2.wbm_cyc_i need to qualified with wbm_stb_i        //// 
+////                                                              ////
+////                                                              //// 
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
 //// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
@@ -146,7 +156,7 @@
 logic               sw_wr_en_1;
 logic               sw_wr_en_2;
 logic               sw_wr_en_3;
-logic [7:0]         cfg_bank_sel;
+logic [15:0]        cfg_bank_sel;
 logic [31:0]        reg_0;  // Software_Reg_0
 
 logic  [3:0]        cfg_wb_clk_ctrl;
@@ -245,13 +255,13 @@
 wb_arb u_arb(
 	.clk      (wbm_clk_i), 
 	.rstn     (wbm_rst_n), 
-	.req      ({1'b0,wbm_uart_stb_i,wbm_stb_i}), 
+	.req      ({2'b0,wbm_uart_stb_i,(wbm_stb_i & wbm_cyc_i)}), 
 	.gnt      (grnt)
         );
 
 // Select  the master based on the grant
-assign wb_cyc_i = (grnt == 2'b00) ? wbm_cyc_i : wbm_uart_cyc_i; 
-assign wb_stb_i = (grnt == 2'b00) ? wbm_stb_i : wbm_uart_stb_i; 
+assign wb_cyc_i = (grnt == 2'b00) ? wbm_cyc_i               : wbm_uart_cyc_i; 
+assign wb_stb_i = (grnt == 2'b00) ? (wbm_cyc_i & wbm_stb_i) : wbm_uart_stb_i; 
 assign wb_adr_i = (grnt == 2'b00) ? wbm_adr_i : wbm_uart_adr_i; 
 assign wb_we_i  = (grnt == 2'b00) ? wbm_we_i  : wbm_uart_we_i; 
 assign wb_dat_i = (grnt == 2'b00) ? wbm_dat_i : wbm_uart_dat_i; 
@@ -312,19 +322,19 @@
 
 
 //-----------------------------------------------------------------------
-// Local register decide based on address[31] == 1
+// Local register decide based on address[19] == 1
 //
 // Locally there register are define to control the reset and clock for user
 // area
 //-----------------------------------------------------------------------
-// caravel user space is 0x3000_0000 to 0x30FF_FFFF
+// caravel user space is 0x3000_0000 to 0x3007_FFFF
 // So we have allocated 
-// 0x3080_0000 - 0x3080_00FF - Assigned to WB Host Address Space
+// 0x3008_0000 - 0x3008_00FF - Assigned to WB Host Address Space
 // Since We need more than 16MB Address space to access SDRAM/SPI we have
 // added indirect MSB 8 bit address select option
-// So Address will be {Bank_Sel[7:0], wbm_adr_i[23:0}
+// So Address will be {Bank_Sel[15:3], wbm_adr_i[18:0]}
 // ---------------------------------------------------------------------
-assign reg_sel       = wb_req & (wb_adr_i[23] == 1'b1);
+assign reg_sel       = wb_req & (wb_adr_i[19] == 1'b1);
 
 assign sw_addr       = wb_adr_i [3:2];
 assign sw_rd_en      = reg_sel & !wb_we_i;
@@ -372,7 +382,7 @@
 
   case (sw_addr [1:0])
     2'b00 :   reg_out [31:0] = reg_0;
-    2'b01 :   reg_out [31:0] = {24'h0,cfg_bank_sel [7:0]};     
+    2'b01 :   reg_out [31:0] = {16'h0,cfg_bank_sel [15:0]};     
     2'b10 :   reg_out [31:0] = cfg_clk_ctrl1 [31:0];    
     2'b11 :   reg_out [31:0] = cfg_clk_ctrl2 [31:0];     
     default : reg_out [31:0] = 'h0;
@@ -391,14 +401,14 @@
 	      .data_out      (reg_0[31:0])
           );
 
-generic_register #(8,8'h10 ) u_bank_sel (
-	      .we            ({8{sw_wr_en_1}}   ),		 
-	      .data_in       (wb_dat_i[7:0]    ),
+generic_register #(16,16'h1000 ) u_bank_sel (
+	      .we            ({16{sw_wr_en_1}}   ),		 
+	      .data_in       (wb_dat_i[15:0]    ),
 	      .reset_n       (wbm_rst_n         ),
 	      .clk           (wbm_clk_i         ),
 	      
 	      //List of Outs
-	      .data_out      (cfg_bank_sel[7:0] )
+	      .data_out      (cfg_bank_sel[15:0] )
           );
 
 
@@ -427,7 +437,7 @@
 
 // Since design need more than 16MB address space, we have implemented
 // indirect access
-assign wb_adr_int = {cfg_bank_sel[7:0],wb_adr_i[23:0]};  
+assign wb_adr_int = {cfg_bank_sel[15:3],wb_adr_i[18:0]};  
 
 async_wb u_async_wb(
 // Master Port
diff --git a/verilog/rtl/yifive/ycr2c b/verilog/rtl/yifive/ycr2c
index 5ed3623..4705007 160000
--- a/verilog/rtl/yifive/ycr2c
+++ b/verilog/rtl/yifive/ycr2c
@@ -1 +1 @@
-Subproject commit 5ed36234610007cd65e054f1f89ce6f1db7b188c
+Subproject commit 47050074fbe8e3c452e8072ef40e4270488575e6