)]}'
{
  "commit": "fe78a4cf0e1a22bdfb26dc3c449a72796dde084f",
  "tree": "0f8795c425336b65a4fa18136898035564425911",
  "parents": [
    "b4a599eed4556955f5796c0f0d40c5b50bb996c1"
  ],
  "author": {
    "name": "dineshannayya",
    "email": "dinesh.annayya@gmail.com",
    "time": "Fri Jul 08 10:03:52 2022 +0530"
  },
  "committer": {
    "name": "dineshannayya",
    "email": "dinesh.annayya@gmail.com",
    "time": "Fri Jul 08 10:03:52 2022 +0530"
  },
  "message": "riscv binary changed from 64bit to 32 bit\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "53869ecfa2f4b4897d1a09c891dbe291172a1b64",
      "old_mode": 33188,
      "old_path": "Makefile",
      "new_id": "ff82bc40252795b2d017d9d4ebfd406bf6633b56",
      "new_mode": 33188,
      "new_path": "Makefile"
    },
    {
      "type": "modify",
      "old_id": "b42b3e9b25ccf9821dfcc8e7522d663eb1899ff5",
      "old_mode": 33188,
      "old_path": "README.md",
      "new_id": "9197bf1bb7c763bdece8b62baa104f5c976d180c",
      "new_mode": 33188,
      "new_path": "README.md"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "a30009c5fd68ca20b6dbef296a72cc381af5601f",
      "new_mode": 33188,
      "new_path": "docs/source/_static/Riscduino_Integration.png"
    },
    {
      "type": "modify",
      "old_id": "b636250f470c8f93d2080e3970dd15b8cf9975e1",
      "old_mode": 33188,
      "old_path": "verilog/dv/arduino_ascii_table/Makefile",
      "new_id": "30b4cfe33d4d1bc68e2a54a7cf1feb9e511c039a",
      "new_mode": 33188,
      "new_path": "verilog/dv/arduino_ascii_table/Makefile"
    },
    {
      "type": "modify",
      "old_id": "0f7f6231979165fb61e812205d4979c196f279aa",
      "old_mode": 33188,
      "old_path": "verilog/dv/arduino_hello_world/Makefile",
      "new_id": "3eed1a1ae07d03d3088e7641eccf1b61909bc96c",
      "new_mode": 33188,
      "new_path": "verilog/dv/arduino_hello_world/Makefile"
    },
    {
      "type": "modify",
      "old_id": "6a11a0cae729f7ba8f072ce05c30a5ecf9bcb01f",
      "old_mode": 33188,
      "old_path": "verilog/dv/arduino_multi_serial/Makefile",
      "new_id": "8c1fa0112e6a96a3a9426077af436969d0393d4d",
      "new_mode": 33188,
      "new_path": "verilog/dv/arduino_multi_serial/Makefile"
    },
    {
      "type": "modify",
      "old_id": "a85da521dc86b81115c9b5f925353ec29831350f",
      "old_mode": 33188,
      "old_path": "verilog/dv/arduino_risc_boot/Makefile",
      "new_id": "5c074b3974f416cc60b75138ce6f06878c9cec6d",
      "new_mode": 33188,
      "new_path": "verilog/dv/arduino_risc_boot/Makefile"
    },
    {
      "type": "modify",
      "old_id": "8d465115ab786541fb0fb9ab9a7b882c33c1b0ff",
      "old_mode": 33188,
      "old_path": "verilog/dv/risc_boot/Makefile",
      "new_id": "a4e04d47d8e8f42c2e52f9aa07c3ccdb55a2a7f0",
      "new_mode": 33188,
      "new_path": "verilog/dv/risc_boot/Makefile"
    },
    {
      "type": "modify",
      "old_id": "15194cc782d33e7ecb3740e1c59b4b1e506a9b57",
      "old_mode": 33188,
      "old_path": "verilog/dv/riscv_regress/Makefile",
      "new_id": "609b7fef5c3c86bb575f8dd0c24cc5940d331d48",
      "new_mode": 33188,
      "new_path": "verilog/dv/riscv_regress/Makefile"
    },
    {
      "type": "modify",
      "old_id": "3a6398155f5b30d1482d12cc1bfa2b356b10323d",
      "old_mode": 33188,
      "old_path": "verilog/dv/uart_master/Makefile",
      "new_id": "7bcd2b739eb8ba8bbb14e8f069529a20a965b001",
      "new_mode": 33188,
      "new_path": "verilog/dv/uart_master/Makefile"
    },
    {
      "type": "modify",
      "old_id": "c674de14a9edcd0840eada5df7cc92e47ffb6e2f",
      "old_mode": 33188,
      "old_path": "verilog/dv/user_aes/Makefile",
      "new_id": "1ba7631eb72781426ea9ceeffbaf67b5fc060942",
      "new_mode": 33188,
      "new_path": "verilog/dv/user_aes/Makefile"
    },
    {
      "type": "modify",
      "old_id": "eb7f108abe3a7324fc9c51fb4c46d414a6383410",
      "old_mode": 33188,
      "old_path": "verilog/dv/user_cache_bypass/Makefile",
      "new_id": "7ecacbf756810c387592eabfccb7ed5b359df5f0",
      "new_mode": 33188,
      "new_path": "verilog/dv/user_cache_bypass/Makefile"
    },
    {
      "type": "modify",
      "old_id": "6c8a24bfc9ca0f404d9b0c6d983969a9993c2413",
      "old_mode": 33188,
      "old_path": "verilog/dv/user_gpio/Makefile",
      "new_id": "c5090eef9f31ee73901616eba33439d90127d4d3",
      "new_mode": 33188,
      "new_path": "verilog/dv/user_gpio/Makefile"
    },
    {
      "type": "modify",
      "old_id": "f01c09d703aa9ddbe5f475eaf956cb3e42f6efef",
      "old_mode": 33188,
      "old_path": "verilog/dv/user_i2cm/Makefile",
      "new_id": "b2bfe321e92cfcd4d2e9c5929d3714e8170a3bf9",
      "new_mode": 33188,
      "new_path": "verilog/dv/user_i2cm/Makefile"
    },
    {
      "type": "modify",
      "old_id": "a0795af68ba5e191e31e20973365e0b6516a0eea",
      "old_mode": 33188,
      "old_path": "verilog/dv/user_mcore/Makefile",
      "new_id": "f635413aa6f38bfb38416b394ff5f5f696386a3e",
      "new_mode": 33188,
      "new_path": "verilog/dv/user_mcore/Makefile"
    },
    {
      "type": "modify",
      "old_id": "c521c74fe58a58ba7fa89c05e1bf70379a7d73be",
      "old_mode": 33188,
      "old_path": "verilog/dv/user_pwm/Makefile",
      "new_id": "b15037f79d6b034afb98cdc62ca844aae2f974de",
      "new_mode": 33188,
      "new_path": "verilog/dv/user_pwm/Makefile"
    },
    {
      "type": "modify",
      "old_id": "6b87fce34f474bed7f7f4c0a3b19bb7b119de040",
      "old_mode": 33188,
      "old_path": "verilog/dv/user_qspi/Makefile",
      "new_id": "edf4cf1bfbcb76497b60981d07f60fd1f06c5fe6",
      "new_mode": 33188,
      "new_path": "verilog/dv/user_qspi/Makefile"
    },
    {
      "type": "modify",
      "old_id": "da70cabde7d4ff7932b5fa94d5b3c0f37d07d74f",
      "old_mode": 33188,
      "old_path": "verilog/dv/user_risc_boot/Makefile",
      "new_id": "0417a18473eed59539c8da8d37e6150f3f68bc07",
      "new_mode": 33188,
      "new_path": "verilog/dv/user_risc_boot/Makefile"
    },
    {
      "type": "modify",
      "old_id": "44f56abf6df89b717231dac014ace88ca4264ae9",
      "old_mode": 33188,
      "old_path": "verilog/dv/user_sram_exec/Makefile",
      "new_id": "6e2a6cd98d07328f738823c66a3dc046fba7c948",
      "new_mode": 33188,
      "new_path": "verilog/dv/user_sram_exec/Makefile"
    },
    {
      "type": "modify",
      "old_id": "f16f2a794bb4b534ccc435ede82062f0b15c5081",
      "old_mode": 33188,
      "old_path": "verilog/dv/user_sspi/Makefile",
      "new_id": "ddc25497ed531d9e5db98f62998df500b6a57cbc",
      "new_mode": 33188,
      "new_path": "verilog/dv/user_sspi/Makefile"
    },
    {
      "type": "modify",
      "old_id": "077652affaa6239b4d53b10ca65dcdbc14a3753b",
      "old_mode": 33188,
      "old_path": "verilog/dv/user_timer/Makefile",
      "new_id": "64791205c14439b047eb0f08a54b0dcccac342e8",
      "new_mode": 33188,
      "new_path": "verilog/dv/user_timer/Makefile"
    },
    {
      "type": "modify",
      "old_id": "0c7484880a13e3599f218bdf33f07288eb497bf3",
      "old_mode": 33188,
      "old_path": "verilog/dv/user_uart/Makefile",
      "new_id": "1ca5cd8bb3a16f41455e54e1293ee756ad788ca9",
      "new_mode": 33188,
      "new_path": "verilog/dv/user_uart/Makefile"
    },
    {
      "type": "modify",
      "old_id": "7f299a14fc7420117fcc8b1b9fa998cd0dc504eb",
      "old_mode": 33188,
      "old_path": "verilog/dv/user_uart1/Makefile",
      "new_id": "c6bc3585d4986f319634ffd230a1da85f1ac1a37",
      "new_mode": 33188,
      "new_path": "verilog/dv/user_uart1/Makefile"
    },
    {
      "type": "modify",
      "old_id": "800f73a2fd0496a8dbbb9517531c9e05c71a2bb5",
      "old_mode": 33188,
      "old_path": "verilog/dv/user_uart_master/Makefile",
      "new_id": "b54f4573b401be1bda24ad495bae3f06911edc2a",
      "new_mode": 33188,
      "new_path": "verilog/dv/user_uart_master/Makefile"
    },
    {
      "type": "modify",
      "old_id": "d8eee80837304858a028cb002fc575c921900199",
      "old_mode": 33188,
      "old_path": "verilog/dv/user_usb/Makefile",
      "new_id": "4422ccde32b8d44d0fca1e526708b943b9182116",
      "new_mode": 33188,
      "new_path": "verilog/dv/user_usb/Makefile"
    },
    {
      "type": "modify",
      "old_id": "0a94555c49d6619a00489e4cfab0c4fd82866660",
      "old_mode": 33188,
      "old_path": "verilog/dv/wb_port/Makefile",
      "new_id": "5ae86238ac4340938e8ee0dd5babf6ce33d2999b",
      "new_mode": 33188,
      "new_path": "verilog/dv/wb_port/Makefile"
    }
  ]
}
