| |
| |
| current_design digital_pll |
| |
| create_clock [get_pins {"ringosc.ibufp01/Y"} ] -name "pll_control_clock" -period 6.6666666666667 |
| |
| set_propagated_clock [get_clocks {pll_control_clock}] |
| |
| set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)] |
| set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)] |
| puts "\[INFO\]: Setting output delay to: $output_delay_value" |
| puts "\[INFO\]: Setting input delay to: $input_delay_value" |
| |
| set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_inputs] |
| set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs] |
| |
| # TODO set this as parameter |
| set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs] |
| set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0] |
| puts "\[INFO\]: Setting load to: $cap_load" |
| set_load $cap_load [all_outputs] |
| |
| puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %" |
| set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}] |
| set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}] |
| |
| puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINITY)" |
| set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks {pll_control_clock}] |
| |
| puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)" |
| set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {pll_control_clock}] |
| |
| |
| set_max_transition 1.00 [current_design] |
| set_max_capacitance 0.2 [current_design] |
| set_max_fanout 10 [current_design] |
