diff --git a/verilog/dv/agents/user_tasks.sv b/verilog/dv/agents/user_tasks.sv
index a2c16ab..2cbdfc6 100644
--- a/verilog/dv/agents/user_tasks.sv
+++ b/verilog/dv/agents/user_tasks.sv
@@ -97,6 +97,35 @@
   end
 endtask
 
+task         apply_strap;
+input [15:0] strap;
+begin
+
+   repeat (10) @(posedge clock);
+   //#1 - Apply Reset
+   wb_rst_i = 1; 
+   //#2 - Apply Strap
+   force u_top.io_in[36:29] = strap[15:8];
+   force u_top.io_in[20:13] = strap[7:0];
+   repeat (10) @(posedge clock);
+    
+   //#3 - Remove Reset
+   wb_rst_i = 0; // Remove Reset
+
+   //#4 - Wait for Power on reset removal
+   wait(u_top.p_reset_n == 1);          
+
+   // #5 - Release the Strap
+   release u_top.io_in[36:29];
+   release u_top.io_in[20:13];
+
+   // #6 - Wait for system reset removal
+   wait(u_top.s_reset_n == 1);          // Wait for system reset removal
+   repeat (10) @(posedge clock);
+
+end
+endtask
+
 genvar gCnt;
 generate
  for(gCnt=0; gCnt<16; gCnt++) begin : g_strap
diff --git a/verilog/dv/arduino_digital_port_control/Makefile b/verilog/dv/arduino_digital_port_control/Makefile
index bd1353c..7d035ec 100644
--- a/verilog/dv/arduino_digital_port_control/Makefile
+++ b/verilog/dv/arduino_digital_port_control/Makefile
@@ -106,24 +106,24 @@
 	rm *.o *.a
 ifeq ($(SIM),RTL)
    ifeq ($(DUMP),OFF)
-	iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	iverilog -g2012 -DFUNCTIONAL -DSIM -DRISC_BOOT -I $(PDK_PATH) \
 	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
 	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
 	$< -o $@ 
     else  
-	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DRISC_BOOT -DSIM -I $(PDK_PATH) \
 	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
 	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
 	$< -o $@ 
    endif
 else  
    ifeq ($(DUMP),OFF)
-	iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \
 	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
 	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
 	$< -o $@ 
     else  
-	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \
 	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
 	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
 	$< -o $@ 
diff --git a/verilog/dv/arduino_digital_port_control/arduino_digital_port_control.ino.cpp b/verilog/dv/arduino_digital_port_control/arduino_digital_port_control.ino.cpp
index d4dd6f5..ba6c295 100644
--- a/verilog/dv/arduino_digital_port_control/arduino_digital_port_control.ino.cpp
+++ b/verilog/dv/arduino_digital_port_control/arduino_digital_port_control.ino.cpp
@@ -49,16 +49,16 @@
   // go through the six channels of the digital pot:
   for (int channel = 0; channel < 6; channel++) {
     // change the resistance on this channel from min to max:
-    for (int level = 0; level < 255; level++) {
+    for (int level = 0; level < 64; level++) {
       digitalPotWrite(channel, level);
-      delayMicroseconds(10);
+      delayMicroseconds(5);
     }
     // wait a second at the top:
-    delayMicroseconds(100);
+    delayMicroseconds(20);
     // change the resistance on this channel from max to min:
-    for (int level = 0; level < 255; level++) {
-      digitalPotWrite(channel, 255 - level);
-      delayMicroseconds(10);
+    for (int level = 0; level < 64; level++) {
+      digitalPotWrite(channel, 64 - level);
+      delayMicroseconds(5);
     }
   }
 
diff --git a/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v b/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v
index 07d7b46..e91855d 100644
--- a/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v
+++ b/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v
@@ -166,31 +166,34 @@
        
 
 	initial begin
+		$value$plusargs("risc_core_id=%d", d_risc_id);
 
 		#200; // Wait for reset removal
 	        repeat (10) @(posedge clock);
 		$display("Monitor: Standalone User Risc Boot Test Started");
+   
+       init();
+       wait_riscv_boot();
 
-		$value$plusargs("risc_core_id=%d", d_risc_id);
 		// Remove Wb Reset
-		wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+		//wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
 
 	    repeat (2) @(posedge clock);
 		#1;
 
         // Remove WB and SPI Reset and CORE under Reset
-        wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F);
+        //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F);
 
 		// QSPI SRAM:CS#2 Switch to QSPI Mode
-        wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
-		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100});
-		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h38});
-		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0);
+        //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
+		//wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100});
+		//wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h38});
+		//wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0);
 
         // Remove all the reset
         if(d_risc_id == 0) begin
              $display("STATUS: Working with Risc core 0");
-             wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
+             //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
         end else if(d_risc_id == 1) begin
              $display("STATUS: Working with Risc core 1");
              wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
@@ -205,27 +208,27 @@
         repeat (100) @(posedge clock);  // wait for Processor Get Ready
 
 
-        repeat (20000) @(posedge clock);  // wait for Processor Get Ready
+        repeat (1000) @(posedge clock);  // wait for Processor Get Ready
         flag = 1;
 
       fork
       begin
-          for (channel = 0; channel < 1; channel = channel+1) begin
+          for (channel = 0; channel < 6; channel = channel+1) begin
             // change the resistance on this channel from min to max:
-            for (level = 0; level < 255; level = level+1) begin
+            for (level = 0; level < 64; level = level+1) begin
                 wait(u_ad5205.channel == channel && u_ad5205.position ==  level);
                 $display("Channel: %x and Position: %x",u_ad5205.channel,u_ad5205.position);
             end
             // change the resistance on this channel from min to max:
-            for (level = 0; level < 255; level = level+1) begin
-                wait((u_ad5205.channel == channel) && (u_ad5205.position ==  (255 -level)));
+            for (level = 0; level < 64; level = level+1) begin
+                wait((u_ad5205.channel == channel) && (u_ad5205.position ==  (64 -level)));
                 $display("Channel: %x and Position: %x",u_ad5205.channel,u_ad5205.position);
             end
           end
           test_fail = 0;
       end
       begin
-         repeat (6000000) @(posedge clock);  // wait for Processor Get Ready
+         repeat (1000000) @(posedge clock);  // wait for Processor Get Ready
          test_fail = 1;
       end
       join_any
@@ -251,11 +254,6 @@
 	    $finish;
 	end
 
-	initial begin
-		wb_rst_i <= 1'b1;
-		#100;
-		wb_rst_i <= 1'b0;	    	// Release reset
-	end
 wire USER_VDD1V8 = 1'b1;
 wire VSS = 1'b0;
 
@@ -509,6 +507,7 @@
 
 `endif
 **/
+`include "user_tasks.sv"
 endmodule
 `include "s25fl256s.sv"
 `default_nettype wire
diff --git a/verilog/dv/common/riscduino_board b/verilog/dv/common/riscduino_board
index 5b5dd05..ec9ef12 160000
--- a/verilog/dv/common/riscduino_board
+++ b/verilog/dv/common/riscduino_board
@@ -1 +1 @@
-Subproject commit 5b5dd057677b00948b02288291ad2141f0543108
+Subproject commit ec9ef12933c2435d28bb91d4f653bfc99377f151
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
index f6c36e5..3317eab 100644
--- a/verilog/dv/user_basic/user_basic_tb.v
+++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -260,12 +260,6 @@
    repeat (2) @(posedge clock);
 
    test_fail=0;
-   // Run in Fast Sim Mode
-   `ifdef GL
-       force u_top.u_wb_host._8654_.Q= 1'b1; 
-   `else
-       force u_top.u_wb_host.u_fastsim_buf.X = 1'b1; 
-    `endif
 
    fork
    begin
@@ -273,34 +267,10 @@
        $display("Step-1, Checking the Strap Loading");
        test_id = 1;
        for(i = 0; i < 16; i = i+1) begin
-          //#1 - Apply Reset
-          wb_rst_i = 1; 
-          test_step = 1;
-          //#2 - Apply Strap
-          strap_in = 1 << i; 
-          force u_top.io_in[36:29] = strap_in[15:8];
-          force u_top.io_in[20:13] = strap_in[7:0];
-          repeat (10) @(posedge clock);
-          test_step = 2;
-         
-          //#3 - Remove Reset
-          wb_rst_i = 0; // Remove Reset
-          test_step = 3;
-
-          //#4 - Wait for Power on reset removal
-          wait(u_top.p_reset_n == 1);          
-          test_step = 4;
-
-          // #5 - Release the Strap
-          release u_top.io_in[36:29];
-          release u_top.io_in[20:13];
-          test_step = 5;
-
-          // #6 - Wait for system reset removal
-          wait(u_top.s_reset_n == 1);          // Wait for system reset removal
-          repeat (10) @(posedge clock);
-          test_step = 6;
-
+          strap_in = 0;
+          strap_in = 1 << i;
+          apply_strap(strap_in);
+     
           //#7 - Check the strap reg value
           wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_PAD_STRAP,read_data,strap_in);
           wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_STRAP_STICKY,read_data,strap_sticky);
@@ -318,29 +288,10 @@
        $display("Step-2, Checking the Clock Skew Configuration");
        test_id = 2;
        for(i = 0; i < 4; i = i+1) begin
-          //#1 - Apply Reset
-          wb_rst_i = 1; 
-          //#2 - Apply Strap
           strap_in = 0;
           strap_in[12:11] = i;
           strap_skew = i;
-          force u_top.io_in[36:29] = strap_in[15:8];
-          force u_top.io_in[20:13] = strap_in[7:0];
-          repeat (10) @(posedge clock);
-         
-          //#3 - Remove Reset
-          wb_rst_i = 0; // Remove Reset
-
-          //#4 - Wait for Power on reset removal
-          wait(u_top.p_reset_n == 1);          
-
-          // #5 - Release the Strap
-          release u_top.io_in[36:29];
-          release u_top.io_in[20:13];
-
-          // #6 - Wait for system reset removal
-          wait(u_top.s_reset_n == 1);          // Wait for system reset removal
-          repeat (10) @(posedge clock);
+          apply_strap(strap_in);
 
           //#7 - Check the strap reg value
           wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_PAD_STRAP,read_data,strap_in);
@@ -358,37 +309,16 @@
        test_id = 3;
        for(i = 0; i < 4; i = i+1) begin
           for(j = 0; j < 4; j = j+1) begin
-              //#1 - Apply Reset
-              wb_rst_i = 1; 
-              //#2 - Apply Strap
               strap_in = 0;
-
               strap_in[1:0] = i;
               cpu_clk_cfg[1:0]=i;
               wbs_clk_cfg[1:0]=i;
-
               strap_in[3:2] = j;
               cpu_clk_cfg[3:2]=j;
               wbs_clk_cfg[3:2]=j;
-
               strap_in[3:2] = j;
-              force u_top.io_in[36:29] = strap_in[15:8];
-              force u_top.io_in[20:13] = strap_in[7:0];
-              repeat (10) @(posedge clock);
-         
-              //#3 - Remove Reset
-              wb_rst_i = 0; // Remove Reset
-
-              //#4 - Wait for Power on reset removal
-              wait(u_top.p_reset_n == 1);          
-
-              // #5 - Release the Strap
-              release u_top.io_in[36:29];
-              release u_top.io_in[20:13];
-
-              // #6 - Wait for system reset removal
-              wait(u_top.s_reset_n == 1);          // Wait for system reset removal
-              repeat (10) @(posedge clock);
+ 
+              apply_strap(strap_in);
 
               //#7 - Check the strap reg value
               wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_PAD_STRAP,read_data,strap_in);
@@ -430,7 +360,21 @@
           $display("STATUS: Step-4, Checking the soft reboot sequence - PASSED");
        end
        $display("##########################################################");
+       /****
+       $display("Step-5, Checking the uart Master baud-16x clock is 9600* 16");
+       test_id = 5;
 
+       apply_strap(16'h10); // [4] -  // uart master config control - constant value based on system clock selection
+
+       uartm_clock_monitor(6510); // 1/(9600*16) = 6510 ns
+
+       if(test_fail == 1) begin
+          $display("ERROR: Step-5,  Checking the uart Master baud-16x clock - FAILED");
+       end else begin
+          $display("STATUS: Step-5,  Checking the uart Master baud-16x clock - PASSED");
+       end
+       $display("##########################################################");
+       ***/
        /*** 
        `ifndef GL  
        $display("###################################################");
@@ -486,8 +430,8 @@
         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
 
          wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h8273_8343);
-         wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,32'h2608_2022);
-         wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,32'h0005_2000);
+         wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,32'h0309_2022);
+         wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,32'h0005_3000);
          if(test_fail == 1) begin
             $display("ERROR: Step-7,Monitor: Checking the chip signature - FAILED");
          end else begin
@@ -664,6 +608,15 @@
 end
 endtask
 
+task uartm_clock_monitor;
+input real exp_period;
+begin
+   force clock_mon = u_top.u_wb_host.u_uart2wb.u_core.line_clk_16x;
+   check_clock_period("UART CLock",exp_period);
+   release clock_mon;
+end
+endtask
+
 
 wire dbg_clk_mon = io_out[33];
 
@@ -867,5 +820,6 @@
 
 `endif
 **/
+`include "user_tasks.sv"
 endmodule
 `default_nettype wire
diff --git a/verilog/dv/user_uart/user_uart.c b/verilog/dv/user_uart/user_uart.c
index e75590d..b19a157 100644
--- a/verilog/dv/user_uart/user_uart.c
+++ b/verilog/dv/user_uart/user_uart.c
@@ -26,6 +26,7 @@
 {
 
    reg_glbl_cfg0 |= 0x1F;       // Remove Reset for UART
+   reg_glbl_multi_func &=0x7FFFFFFF; // Disable UART Master Bit[31] = 0
    reg_glbl_multi_func |=0x100; // Enable UART Multi func
    reg_uart0_ctrl = 0x07;       // Enable Uart Access {3'h0,2'b00,1'b1,1'b1,1'b1}
 
diff --git a/verilog/dv/user_uart_master/user_uart_master_tb.v b/verilog/dv/user_uart_master/user_uart_master_tb.v
index 5d9006b..2d909f4 100644
--- a/verilog/dv/user_uart_master/user_uart_master_tb.v
+++ b/verilog/dv/user_uart_master/user_uart_master_tb.v
@@ -68,6 +68,7 @@
 
 `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
 `include "uart_agent.v"
+`include "user_params.svh"
 
 module user_uart_master_tb;
 
@@ -100,10 +101,10 @@
 // Uart Configuration
 // ---------------------------------
 reg [1:0]      uart_data_bit        ;
-reg	       uart_stop_bits       ; // 0: 1 stop bit; 1: 2 stop bit;
-reg	       uart_stick_parity    ; // 1: force even parity
-reg	       uart_parity_en       ; // parity enable
-reg	       uart_even_odd_parity ; // 0: odd parity; 1: even parity
+reg	           uart_stop_bits       ; // 0: 1 stop bit; 1: 2 stop bit;
+reg	           uart_stick_parity    ; // 1: force even parity
+reg	           uart_parity_en       ; // parity enable
+reg	           uart_even_odd_parity ; // 0: odd parity; 1: even parity
 
 reg [7:0]      uart_data            ;
 reg [15:0]     uart_divisor         ;	// divided by n * 16
@@ -115,7 +116,8 @@
 reg 	       uart_fifo_enable     ;	// fifo mode disable
 
 reg  [127:0]   la_data_in;
-reg       flag;
+reg            flag;
+reg  [15:0]    strap_in;
 
 
 integer i,j;
@@ -149,7 +151,10 @@
 	end
 initial
 begin
-   init();
+   strap_in = 0;
+   strap_in[`PSTRAP_UARTM_CFG] = 0; // uart master config control - load from LA
+   apply_strap(strap_in);
+
    uart_data_bit           = 2'b11;
    uart_stop_bits          = 1; // 0: 1 stop bit; 1: 2 stop bit;
    uart_stick_parity       = 0; // 1: force even parity
@@ -269,7 +274,8 @@
 
 );
 // SSPI Slave I/F
-assign io_in[0]  = 1'b1; // RESET
+assign io_in[5]  = 1'b1; // RESET
+assign io_in[21] = 1'b0; // CLOCK
 
 `ifndef GL // Drive Power for Hold Fix Buf
     // All standard cell need power hook-up for functionality work
@@ -283,8 +289,8 @@
 // --------------------------
 wire uart_txd,uart_rxd;
 
-assign uart_txd   = io_out[23];
-assign io_in[22]  = uart_rxd ;
+assign uart_txd   = io_out[7];
+assign io_in[6]  = uart_rxd ;
  
 uart_agent tb_master_uart(
 	.mclk                (clock              ),
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv
index 652305d..f8143ed 100755
--- a/verilog/rtl/pinmux/src/pinmux.sv
+++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -44,8 +44,8 @@
 * Pin Mapping    Arduino              ATMGE CONFIG
 *   ATMEGA328     Port                                                      caravel Pin Mapping
 *   Pin-1         22            PC6/WS[0]/RESET*                            digital_io[5]
-*   Pin-2         0             PD0/WS[0]/RXD[0]                            digital_io[6]
-*   Pin-3         1             PD1/WS[0]/TXD[0]                            digital_io[7]
+*   Pin-2         0             PD0/WS[0]/MRXD/RXD[0]                       digital_io[6]
+*   Pin-3         1             PD1/WS[0]/MRXD/TXD[0]                       digital_io[7]
 *   Pin-4         2             PD2/WS[0]/RXD[1]/INT0                       digital_io[8]
 *   Pin-5         3             PD3/WS[1]INT1/OC2B(PWM0)                    digital_io[9]
 *   Pin-6         4             PD4/WS[1]TXD[1]                             digital_io[10]
@@ -65,8 +65,8 @@
 *   Pin-20                      AVCC                -
 *   Pin-21                      AREF                                        analog_io[10]
 *   Pin-22                      GND                 -
-*   Pin-23        14            PC0/uartm_rxd/ADC0                          digital_io[22]/analog_io[11]
-*   Pin-24        15            PC1/uartm_txd/ADC1                          digital_io[23]/analog_io[12]
+*   Pin-23        14            PC0/ADC0                          digital_io[22]/analog_io[11]
+*   Pin-24        15            PC1/ADC1                          digital_io[23]/analog_io[12]
 *   Pin-25        16            PC2/usb_dp/ADC2                             digital_io[24]/analog_io[13]
 *   Pin-26        17            PC3/usb_dn/ADC3                             digital_io[25]/analog_io[14]
 *   Pin-27        18            PC4/ADC4/SDA                                digital_io[26]/analog_io[15]
@@ -236,21 +236,23 @@
      port_b_in = 'h0;
      port_c_in = 'h0;
      port_d_in = 'h0;
-     uart_rxd   = 'h0;
+     uart_rxd   = 'b1;
      ext_intr_in= 'h0;
      spim_mosi  = 'h0;
      i2cm_data_i= 'h0;
      i2cm_clk_i = 'h0;
+     uartm_rxd  = 'b1;
 
      //Pin-1        PC6/RESET*          digital_io[5]
      port_c_in[6] = digital_io_in[5];
      pin_resetn   = digital_io_in[5];
 
-     //Pin-2        PD0/RXD[0]             digital_io[6]
+     //Pin-2        PD0/MRXD/RXD[0]             digital_io[6]
      port_d_in[0] = digital_io_in[6];
-     if(cfg_uart_enb[0])  uart_rxd[0]   = digital_io_in[6];
+     if (cfg_muart_enb)        uartm_rxd     = digital_io_in[6];
+     else if(cfg_uart_enb[0])  uart_rxd[0]   = digital_io_in[6];
   
-     //Pin-3        PD1/TXD[0]             digital_io[7]
+     //Pin-3        PD1/MTXD/TXD[0]             digital_io[7]
      port_d_in[1] = digital_io_in[7];
 
 
@@ -302,11 +304,10 @@
      port_b_in[5]= digital_io_in[21];
      spis_sck    = (spis_boot) ? digital_io_in[21] : 1'b1;   // SPIM SCK (Output) = SPIS SCK (Input)
      
-     //Pin-23       PC0/ADC0            digital_io[22]/uartm_rxd/analog_io[11]
-     uartm_rxd    = (cfg_muart_enb) ?  digital_io_in[22]: 1'b1;
+     //Pin-23       PC0/ADC0            digital_io[22]/analog_io[11]
      port_c_in[0] = digital_io_in[22];
 
-     //Pin-24       PC1/ADC1            digital_io[23]/uartm_txd/analog_io[12]
+     //Pin-24       PC1/ADC1            digital_io[23]/analog_io[12]
      port_c_in[1] = digital_io_in[23];
 
      //Pin-25       PC2/ADC2            digital_io[24]/usb_dp/analog_io[13]
@@ -345,12 +346,13 @@
      if(cfg_port_c_port_type[6])       digital_io_out[5]   = ws_txd[0];
      else if(cfg_port_c_dir_sel[6])    digital_io_out[5]   = port_c_out[6];
 
-     //Pin-2        PD0/WS[0]/RXD[0]       digital_io[6]
+     //Pin-2        PD0/WS[0]/MRXD/RXD[0]       digital_io[6]
      if(cfg_port_d_port_type[0])       digital_io_out[6]   = ws_txd[0];
      else if(cfg_port_d_dir_sel[0])    digital_io_out[6]   = port_d_out[0];
   
-     //Pin-3        PD1/WS[0]/TXD[0]       digital_io[7]
-     if     (cfg_uart_enb[0])         digital_io_out[7]  = uart_txd[0];
+     //Pin-3        PD1/WS[0]/MTXD/TXD[0]       digital_io[7]
+     if     (cfg_muart_enb)           digital_io_out[7]  = uartm_txd;
+     else if(cfg_uart_enb[0])         digital_io_out[7]  = uart_txd[0];
      else if(cfg_port_d_port_type[1]) digital_io_out[7]  = ws_txd[0];
      else if(cfg_port_d_dir_sel[1])   digital_io_out[7]  = port_d_out[1];
 
@@ -426,13 +428,11 @@
      if(cfg_spim_enb)             digital_io_out[21]  = spim_sck;      // SPIM SCK (Output) = SPIS SCK (Input)
      else if(cfg_port_b_dir_sel[5])  digital_io_out[21]  = port_b_out[5];
      
-     //Pin-23       PC0/MRXD/ADC0    digital_io[22]/analog_io[11]
-     if(cfg_muart_enb)               digital_io_out[22]  = 1'b1;
-     else if(cfg_port_c_dir_sel[0])  digital_io_out[22]  = port_c_out[0];
+     //Pin-23       PC0/ADC0    digital_io[22]/analog_io[11]
+     if(cfg_port_c_dir_sel[0])  digital_io_out[22]  = port_c_out[0];
 
-     //Pin-24       PC1/MTXD/ADC1    digital_io[23]/analog_io[12]
-     if(cfg_muart_enb)               digital_io_out[23]  = uartm_txd;
-     else if(cfg_port_c_dir_sel[1])  digital_io_out[23]  = port_c_out[1];
+     //Pin-24       PC1/ADC1    digital_io[23]/analog_io[12]
+     if(cfg_port_c_dir_sel[1])  digital_io_out[23]  = port_c_out[1];
 
      //Pin-25       PC2/USB_DP/ADC2  digital_io[24]/analog_io[13]
      if(cfg_usb_enb)                 digital_io_out[24]  = usb_dp_o;
@@ -479,13 +479,15 @@
      if(cfg_port_c_port_type[6])       digital_io_oen[5]   = 1'b1;
      else if(cfg_port_c_dir_sel[6])    digital_io_oen[5]   = 1'b0;
 
-     //Pin-2        PD0/WS[0]/RXD[0]          digital_io[6]
-     if     (cfg_uart_enb[0])        digital_io_oen[6]   = 1'b1;
+     //Pin-2        PD0/WS[0]/MRXD/RXD[0]          digital_io[6]
+     if     (cfg_muart_enb)          digital_io_oen[6]   = 1'b1;
+     else if(cfg_uart_enb[0])        digital_io_oen[6]   = 1'b1;
      else if(cfg_port_d_port_type[0])digital_io_oen[6]   = 1'b1;
      else if(cfg_port_d_dir_sel[0])  digital_io_oen[6]   = 1'b0;
 
-     //Pin-3        PD1/WS[0]/TXD[0]          digital_io[7]
-     if     (cfg_uart_enb[0])        digital_io_oen[7]   = 1'b0;
+     //Pin-3        PD1/WS[0]/MTXD/TXD[0]          digital_io[7]
+     if     (cfg_muart_enb)          digital_io_oen[7]   = 1'b0;
+     else if(cfg_uart_enb[0])        digital_io_oen[7]   = 1'b0;
      else if(cfg_port_d_port_type[1])digital_io_oen[7]   = 1'b1;
      else if(cfg_port_d_dir_sel[1])  digital_io_oen[7]   = 1'b0;
 
@@ -572,12 +574,10 @@
      else if(cfg_port_b_dir_sel[5])  digital_io_oen[21]  = 1'b0;
      else if(spis_boot)              digital_io_oen[21]  = 1'b1; // SPIS SCK (Input)
      
-     //Pin-23       PC0/MRXD/ADC0    digital_io[22]/analog_io[11]
-     if(cfg_muart_enb)               digital_io_oen[22]  = 1'b1; 
-     else if(cfg_port_c_dir_sel[0])  digital_io_oen[22]  = 1'b0;
+     //Pin-23       PC0/ADC0    digital_io[22]/analog_io[11]
+     if(cfg_port_c_dir_sel[0])       digital_io_oen[22]  = 1'b0;
 
-     //Pin-24       PC1/MTXD/ADC1    digital_io[23]/analog_io[12]
-     if(cfg_muart_enb)               digital_io_oen[23]  = 1'b0; 
+     //Pin-24       PC1/ADC1    digital_io[23]/analog_io[12]
      if(cfg_port_c_dir_sel[1])       digital_io_oen[23]  = 1'b0;
 
      //Pin-25       PC2/USB_DP/ADC2  digital_io[24]/analog_io[13]
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv
index 766a87d..df3c656 100644
--- a/verilog/rtl/wb_host/src/wb_host.sv
+++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -320,11 +320,11 @@
 
 wire strap_uart_cfg_mode = system_strap[`STRAP_UARTM_CFG];
 
-wire       cfg_uartm_tx_enable   = (strap_uart_cfg_mode) ? la_data_in[1]     : 1'b1;
-wire       cfg_uartm_rx_enable   = (strap_uart_cfg_mode) ? la_data_in[2]     : 1'b1;
-wire       cfg_uartm_stop_bit    = (strap_uart_cfg_mode) ? la_data_in[3]     : 1'b1;
-wire [11:0]cfg_uart_baud_16x     = (strap_uart_cfg_mode) ? la_data_in[15:4]  : 259;
-wire [1:0] cfg_uartm_cfg_pri_mod = (strap_uart_cfg_mode) ? la_data_in[17:16] : 2'b0;
+wire       cfg_uartm_tx_enable   = (strap_uart_cfg_mode==0) ? la_data_in[1]     : 1'b1;
+wire       cfg_uartm_rx_enable   = (strap_uart_cfg_mode==0) ? la_data_in[2]     : 1'b1;
+wire       cfg_uartm_stop_bit    = (strap_uart_cfg_mode==0) ? la_data_in[3]     : 1'b1;
+wire [11:0]cfg_uart_baud_16x     = (strap_uart_cfg_mode==0) ? la_data_in[15:4]  : 258;
+wire [1:0] cfg_uartm_cfg_pri_mod = (strap_uart_cfg_mode==0) ? la_data_in[17:16] : 2'b0;
 
 
 // UART Master