diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index 84ee8f8..141381b 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@
 .SUFFIXES:
 .SILENT: clean all
 
-PATTERNS = wb_port risc_boot user_risc_boot user_uart user_uart1 user_qspi user_i2cm riscv_regress user_basic user_usb user_pwm user_timer user_uart_master uart_master user_mcore user_sram_exec user_cache_bypass user_gpio arduino_risc_boot arduino_hello_world arduino_ascii_table arduino_multi_serial user_spi_isp
+PATTERNS = wb_port risc_boot user_risc_boot user_uart user_uart1 user_qspi user_i2cm riscv_regress user_basic user_usb user_pwm user_timer user_uart_master uart_master user_sram_exec user_cache_bypass user_gpio user_spi_isp arduino_risc_boot arduino_hello_world arduino_ascii_table arduino_multi_serial arduino_arrays arduino_switchCase2 arduino_character_analysis arduino_string arduino_digital_port_control user_sspi user_aes user_sema user_mcore_test1 user_mcore_test2
 
 all:  ${PATTERNS}
 	for i in ${PATTERNS}; do \
diff --git a/verilog/dv/arduino_arrays/Makefile b/verilog/dv/arduino_arrays/Makefile
new file mode 100644
index 0000000..dad099c
--- /dev/null
+++ b/verilog/dv/arduino_arrays/Makefile
@@ -0,0 +1,140 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+ 
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+DESIGNS?=../../..
+TOOLS?=/opt/riscv32i/
+
+export USER_PROJECT_VERILOG ?=  $(DESIGNS)/verilog
+export RISCDUINO_BOARD ?=  $(USER_PROJECT_VERILOG)/dv/common/riscduino_board/custom_board/riscduino
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+GCC_PREFIX?=riscv32-unknown-elf
+
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+RISC_CORE?=0
+
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
+.SUFFIXES:
+
+PATTERN = arduino_arrays
+
+all:  ${PATTERN:=.vcd}
+
+
+vvp:  ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${PATTERN}.ino.cpp -o ${PATTERN}.ino.cpp.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/Print.cpp -o Print.cpp.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WMath.cpp -o WMath.cpp.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WString.cpp -o WString.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WInterrupts.c -o WInterrupts.c.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/fe300prci/fe300prci_driver.c -o fe300prci_driver.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/abi.cpp -o abi.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/plic/plic_driver.c -o plic_driver.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/UARTClass.cpp -o UARTClass.cpp.o
+	${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/entry.S -o entry.S.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/hooks.c -o hooks.c.o
+	${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/init.S -o init.S.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/itoa.c -o itoa.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/main.cpp -o main.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/malloc.c -o malloc.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/new.cpp -o new.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/sbrk.c -o sbrk.c.o
+	${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/start.S -o start.S.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring.c -o wiring.c.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_analog.c -o wiring_analog.c.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_digital.c -o wiring_digital.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_pulse.cpp -o wiring_pulse.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_shift.c -o wiring_shift.c.o
+	${GCC_PREFIX}-ar rcs core.a Print.cpp.o
+	${GCC_PREFIX}-ar rcs core.a UARTClass.cpp.o
+	${GCC_PREFIX}-ar rcs core.a WInterrupts.c.o
+	${GCC_PREFIX}-ar rcs core.a WMath.cpp.o
+	${GCC_PREFIX}-ar rcs core.a WString.cpp.o
+	${GCC_PREFIX}-ar rcs core.a abi.cpp.o
+	${GCC_PREFIX}-ar rcs core.a fe300prci_driver.c.o
+	${GCC_PREFIX}-ar rcs core.a plic_driver.c.o
+	${GCC_PREFIX}-ar rcs core.a entry.S.o
+	${GCC_PREFIX}-ar rcs core.a hooks.c.o
+	${GCC_PREFIX}-ar rcs core.a init.S.o
+	${GCC_PREFIX}-ar rcs core.a itoa.c.o
+	${GCC_PREFIX}-ar rcs core.a main.cpp.o
+	${GCC_PREFIX}-ar rcs core.a malloc.c.o
+	${GCC_PREFIX}-ar rcs core.a new.cpp.o
+	${GCC_PREFIX}-ar rcs core.a sbrk.c.o
+	${GCC_PREFIX}-ar rcs core.a start.S.o
+	${GCC_PREFIX}-ar rcs core.a wiring.c.o
+	${GCC_PREFIX}-ar rcs core.a wiring_analog.c.o
+	${GCC_PREFIX}-ar rcs core.a wiring_digital.c.o
+	${GCC_PREFIX}-ar rcs core.a wiring_pulse.cpp.o
+	${GCC_PREFIX}-ar rcs core.a wiring_shift.c.o
+	${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf
+	${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.ino.elf ${PATTERN}.ino.bin
+	${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.ino.elf ${PATTERN}.ino.hex
+	${GCC_PREFIX}-objdump -D  ${PATTERN}.ino.elf >   ${PATTERN}.ino.dump
+	rm *.o *.a
+ifeq ($(SIM),RTL)
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
+	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
+	$< -o $@ 
+   endif
+else  
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+   endif
+endif
+
+%.vcd: %.vvp
+	vvp $< +risc_core_id=$(RISC_CORE)
+
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump *.a *.o
+
+.PHONY: clean hex all
diff --git a/verilog/dv/arduino_arrays/arduino_arrays.ino b/verilog/dv/arduino_arrays/arduino_arrays.ino
new file mode 100644
index 0000000..dbbb4b4
--- /dev/null
+++ b/verilog/dv/arduino_arrays/arduino_arrays.ino
@@ -0,0 +1,56 @@
+/*
+  Arrays
+
+  Demonstrates the use of an array to hold pin numbers in order to iterate over
+  the pins in a sequence. Lights multiple LEDs in sequence, then in reverse.
+
+  Unlike the For Loop tutorial, where the pins have to be contiguous, here the
+  pins can be in any random order.
+
+  The circuit:
+  - LEDs from pins 2 through 7 to ground
+
+  created 2006
+  by David A. Mellis
+  modified 30 Aug 2011
+  by Tom Igoe
+
+  This example code is in the public domain.
+
+  https://www.arduino.cc/en/Tutorial/BuiltInExamples/Arrays
+*/
+
+int timer = 100;           // The higher the number, the slower the timing.
+int ledPins[] = {
+  2, 7, 4, 6, 5, 3
+};       // an array of pin numbers to which LEDs are attached
+int pinCount = 6;           // the number of pins (i.e. the length of the array)
+
+void setup() {
+  // the array elements are numbered from 0 to (pinCount - 1).
+  // use a for loop to initialize each pin as an output:
+  for (int thisPin = 0; thisPin < pinCount; thisPin++) {
+    pinMode(ledPins[thisPin], OUTPUT);
+  }
+}
+
+void loop() {
+  // loop from the lowest pin to the highest:
+  for (int thisPin = 0; thisPin < pinCount; thisPin++) {
+    // turn the pin on:
+    digitalWrite(ledPins[thisPin], HIGH);
+    delay(timer);
+    // turn the pin off:
+    digitalWrite(ledPins[thisPin], LOW);
+
+  }
+
+  // loop from the highest pin to the lowest:
+  for (int thisPin = pinCount - 1; thisPin >= 0; thisPin--) {
+    // turn the pin on:
+    digitalWrite(ledPins[thisPin], HIGH);
+    delay(timer);
+    // turn the pin off:
+    digitalWrite(ledPins[thisPin], LOW);
+  }
+}
diff --git a/verilog/dv/arduino_arrays/arduino_arrays.ino.cpp b/verilog/dv/arduino_arrays/arduino_arrays.ino.cpp
new file mode 100644
index 0000000..ebcb90b
--- /dev/null
+++ b/verilog/dv/arduino_arrays/arduino_arrays.ino.cpp
@@ -0,0 +1,63 @@
+#include <Arduino.h>
+/*
+  Arrays
+
+  Demonstrates the use of an array to hold pin numbers in order to iterate over
+  the pins in a sequence. Lights multiple LEDs in sequence, then in reverse.
+
+  Unlike the For Loop tutorial, where the pins have to be contiguous, here the
+  pins can be in any random order.
+
+  The circuit:
+  - LEDs from pins 2 through 7 to ground
+
+  created 2006
+  by David A. Mellis
+  modified 30 Aug 2011
+  by Tom Igoe
+
+  This example code is in the public domain.
+
+  https://www.arduino.cc/en/Tutorial/BuiltInExamples/Arrays
+*/
+
+int timer = 10; // In Milli Second  - The higher the number, the slower the timing.
+int ledPins[] = {
+  2, 7, 4, 6, 5, 3
+};       // an array of pin numbers to which LEDs are attached
+int pinCount = 6;           // the number of pins (i.e. the length of the array)
+
+void setup();
+void loop();
+void setup() {
+  // the array elements are numbered from 0 to (pinCount - 1).
+  // use a for loop to initialize each pin as an output:
+  for (int thisPin = 0; thisPin < pinCount; thisPin++) {
+    pinMode(ledPins[thisPin], OUTPUT);
+  }
+}
+
+void loop() {
+  // loop from the lowest pin to the highest:
+  for (int thisPin = 0; thisPin < pinCount; thisPin++) {
+    // turn the pin on:
+    digitalWrite(ledPins[thisPin], HIGH);
+    //delay(timer);
+    delayMicroseconds(timer);
+    // turn the pin off:
+    digitalWrite(ledPins[thisPin], LOW);
+    delayMicroseconds(timer);
+
+  }
+
+  // loop from the highest pin to the lowest:
+  for (int thisPin = pinCount - 1; thisPin >= 0; thisPin--) {
+    // turn the pin on:
+    digitalWrite(ledPins[thisPin], HIGH);
+    delayMicroseconds(timer);
+    // turn the pin off:
+    digitalWrite(ledPins[thisPin], LOW);
+    delayMicroseconds(timer);
+  }
+}
+
diff --git a/verilog/dv/user_mcore/user_mcore_tb.v b/verilog/dv/arduino_arrays/arduino_arrays_tb.v
similarity index 65%
copy from verilog/dv/user_mcore/user_mcore_tb.v
copy to verilog/dv/arduino_arrays/arduino_arrays_tb.v
index b43dcba..169337d 100644
--- a/verilog/dv/user_mcore/user_mcore_tb.v
+++ b/verilog/dv/arduino_arrays/arduino_arrays_tb.v
@@ -18,20 +18,23 @@
 ////                                                              ////
 ////  Standalone User validation Test bench                       ////
 ////                                                              ////
-////  This file is part of the riscduino cores project            ////
+////  This file is part of the riscdunio cores project            ////
+////  https://github.com/dineshannayya/riscdunio.git              ////
 ////                                                              ////
 ////  Description                                                 ////
 ////   This is a standalone test bench to validate the            ////
-////   Digital core multi-core behaviour.                         ////
+////   Digital core.                                              ////
+////   This test bench to valid Arduino example:                  ////
+////     <example><05.control><Arrays>                            ////
 ////                                                              ////
 ////  To Do:                                                      ////
 ////    nothing                                                   ////
 ////                                                              ////
 ////  Author(s):                                                  ////
-////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////      - Dinesh Annayya, dinesh.annayya@gmail.com              ////
 ////                                                              ////
 ////  Revision :                                                  ////
-////    0.1 - 16th Feb 2021, Dinesh A                             ////
+////    0.1 - 29th July 2022, Dinesh A                            ////
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
@@ -65,7 +68,9 @@
 `timescale 1 ns / 1 ns
 
 `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
-module user_mcore_tb;
+`include "is62wvs1288.v"
+
+module arduino_arrays_tb;
 	reg clock;
 	reg wb_rst_i;
 	reg power1, power2;
@@ -92,18 +97,48 @@
 	wire [7:0] mprj_io_0;
 	reg         test_fail;
 	reg [31:0] read_data;
+	reg            flag                 ;
+
+parameter P_FSM_C      = 4'b0000; // Command Phase Only
+parameter P_FSM_CW     = 4'b0001; // Command + Write DATA Phase Only
+parameter P_FSM_CA     = 4'b0010; // Command -> Address Phase Only
+
+parameter P_FSM_CAR    = 4'b0011; // Command -> Address -> Read Data
+parameter P_FSM_CADR   = 4'b0100; // Command -> Address -> Dummy -> Read Data
+parameter P_FSM_CAMR   = 4'b0101; // Command -> Address -> Mode -> Read Data
+parameter P_FSM_CAMDR  = 4'b0110; // Command -> Address -> Mode -> Dummy -> Read Data
+
+parameter P_FSM_CAW    = 4'b0111; // Command -> Address ->Write Data
+parameter P_FSM_CADW   = 4'b1000; // Command -> Address -> DUMMY + Write Data
+parameter P_FSM_CAMW   = 4'b1001; // Command -> Address -> MODE + Write Data
+
+parameter P_FSM_CDR    = 4'b1010; // COMMAND -> DUMMY -> READ
+parameter P_FSM_CDW    = 4'b1011; // COMMAND -> DUMMY -> WRITE
+parameter P_FSM_CR     = 4'b1100;  // COMMAND -> READ
+
+parameter P_MODE_SWITCH_IDLE     = 2'b00;
+parameter P_MODE_SWITCH_AT_ADDR  = 2'b01;
+parameter P_MODE_SWITCH_AT_DATA  = 2'b10;
+
+parameter P_SINGLE = 2'b00;
+parameter P_DOUBLE = 2'b01;
+parameter P_QUAD   = 2'b10;
+parameter P_QDDR   = 2'b11;
+
+        
 	integer    d_risc_id;
 
+         integer i,j;
 
 
-	// External clock is used by default.  Make this artificially fast for the
-	// simulation.  Normally this would be a slow clock and the digital PLL
-	// would be the fast clock.
 
-	always #12.5 clock <= (clock === 1'b0);
+
+	// 50Mhz CLock
+	always #10 clock <= (clock === 1'b0);
 
 	initial begin
 		clock = 0;
+	        flag  = 0;
                 wbd_ext_cyc_i ='h0;  // strobe/request
                 wbd_ext_stb_i ='h0;  // strobe/request
                 wbd_ext_adr_i ='h0;  // address
@@ -115,69 +150,125 @@
 	`ifdef WFDUMP
 	   initial begin
 	   	$dumpfile("simx.vcd");
-	   	$dumpvars(1, user_mcore_tb);
-	   	$dumpvars(1, user_mcore_tb.u_top);
-	   	$dumpvars(0, user_mcore_tb.u_top.u_riscv_top);
+	   	$dumpvars(3, arduino_arrays_tb);
+	   	//$dumpvars(0, arduino_arrays_tb.u_top.u_riscv_top.i_core_top_0);
+	   	//$dumpvars(0, arduino_arrays_tb.u_top.u_riscv_top.u_connect);
+	   	//$dumpvars(0, arduino_arrays_tb.u_top.u_riscv_top.u_intf);
+	   	$dumpvars(0, arduino_arrays_tb.u_top.u_pinmux);
 	   end
        `endif
 
-	initial begin
+     /************* Port-D Mapping **********************************
+      *             Arduino-No
+      *   Pin-2        0         PD0/RXD[0]                digital_io[1]
+      *   Pin-3        1         PD1/TXD[0]                digital_io[2]
+      *   Pin-4        2         PD2/RXD[1]/INT0           digital_io[3]
+      *   Pin-5        3         PD3/INT1/OC2B(PWM0)       digital_io[4]
+      *   Pin-6        4         PD4/TXD[1]                digital_io[5]
+      *   Pin-11       5         PD5/SS[3]/OC0B(PWM1)/T1   digital_io[8]
+      *   Pin-12       6         PD6/SS[2]/OC0A(PWM2)/AIN0 digital_io[9]/analog_io[2]
+      *   Pin-13       7         PD7/A1N1                  digital_io[10]/analog_io[3]
+      *   ********************************************************/
 
-		$value$plusargs("risc_core_id=%d", d_risc_id);
+     wire [7:0]  port_d_in = {  io_out[10],
+		                        io_out[9],
+		                        io_out[8],
+		                        io_out[5],
+			                    io_out[4],
+			                    io_out[3],
+		                        io_out[2],
+		                        io_out[1]
+			                };
+       
+
+	initial begin
 
 		#200; // Wait for reset removal
 	        repeat (10) @(posedge clock);
 		$display("Monitor: Standalone User Risc Boot Test Started");
 
+		$value$plusargs("risc_core_id=%d", d_risc_id);
 		// Remove Wb Reset
 		wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
 
-	        repeat (2) @(posedge clock);
+	    repeat (2) @(posedge clock);
 		#1;
-		// Remove all the reset
-		$display("STATUS: Working with Both core Risc core 0 & 1 ");
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h31F);
+
+        // Remove WB and SPI Reset and CORE under Reset
+        wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F);
+
+		// QSPI SRAM:CS#2 Switch to QSPI Mode
+        wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h38});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0);
+
+        // Remove all the reset
+        if(d_risc_id == 0) begin
+             $display("STATUS: Working with Risc core 0");
+             wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
+        end else if(d_risc_id == 1) begin
+             $display("STATUS: Working with Risc core 1");
+             wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
+        end else if(d_risc_id == 2) begin
+             $display("STATUS: Working with Risc core 2");
+             wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F);
+        end else if(d_risc_id == 3) begin
+             $display("STATUS: Working with Risc core 3");
+             wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
+        end
+
+        repeat (100) @(posedge clock);  // wait for Processor Get Ready
 
 
-		// Repeat cycles of 1000 clock edges as needed to complete testbench
-		repeat (22) begin
-			repeat (1000) @(posedge clock);
-			// $display("+1000 cycles");
-		end
+        repeat (20000) @(posedge clock);  // wait for Processor Get Ready
+        flag = 1;
 
+   fork
+      begin
+         // Refer C code,
+         // Wait for toggle in following sequency 2,7,4,6,5,3
+      
+         portd_detect_pin_toggle(2);
+         portd_detect_pin_toggle(7);
+         portd_detect_pin_toggle(4);
+         portd_detect_pin_toggle(6);
+         portd_detect_pin_toggle(5);
+         portd_detect_pin_toggle(3);
+         
+        
+         // Wait for toggle in following sequency 3,5,6,4,7,2
+         portd_detect_pin_toggle(3);
+         portd_detect_pin_toggle(5);
+         portd_detect_pin_toggle(6);
+         portd_detect_pin_toggle(4);
+         portd_detect_pin_toggle(7);
+         portd_detect_pin_toggle(2);
+      
+          test_fail = 0;
+      end
+      begin
+         repeat (30000) @(posedge clock);  // wait for Processor Get Ready
+         test_fail = 1;
+      end
+      join_any
 
-		$display("Monitor: Reading Back the expected value");
-		// User RISC core expect to write these value in global
-		// register, read back and decide on pass fail
-		// 0x30000018  = 0x11223344; 
-                // 0x3000001C  = 0x22334455; 
-                // 0x30000020  = 0x33445566; 
-                // 0x30000024  = 0x44556677; 
-                // 0x30000028 = 0x55667788; 
-                // 0x3000002C = 0x66778899; 
-
-                test_fail = 0;
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h11223344);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h22334455);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h33445566);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32'h44556677);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32'h55667788);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32'h66778899);
+           #100
 
 
 	   
 	    	$display("###################################################");
           	if(test_fail == 0) begin
 		   `ifdef GL
-	    	       $display("Monitor: Standalone User Risc Boot (GL) Passed");
+	    	       $display("Monitor: Ardunio arrays  (GL) Passed");
 		   `else
-		       $display("Monitor: Standalone User Risc Boot (RTL) Passed");
+		       $display("Monitor: Ardunio arrays (RTL) Passed");
 		   `endif
 	        end else begin
 		    `ifdef GL
-	    	        $display("Monitor: Standalone User Risc Boot (GL) Failed");
+	    	        $display("Monitor: Ardunio arrays (GL) Failed");
 		    `else
-		        $display("Monitor: Standalone User Risc Boot (RTL) Failed");
+		        $display("Monitor: Ardunio arrays (RTL) Failed");
 		    `endif
 		 end
 	    	$display("###################################################");
@@ -257,7 +348,7 @@
    assign io_in[32] = flash_io3;
 
    // Quard flash
-     s25fl256s #(.mem_file_name("user_mcore.hex"),
+     s25fl256s #(.mem_file_name("arduino_arrays.ino.hex"),
 	         .otp_file_name("none"),
                  .TimingModel("S25FL512SAGMFI010_F_30pF")) 
 		 u_spi_flash_256mb (
@@ -273,7 +364,32 @@
 
        );
 
+   wire spiram_csb = io_out[27];
 
+   is62wvs1288 #(.mem_file_name("none"))
+	u_sram (
+         // Data Inputs/Outputs
+           .io0     (flash_io0),
+           .io1     (flash_io1),
+           // Controls
+           .clk    (flash_clk),
+           .csb    (spiram_csb),
+           .io2    (flash_io2),
+           .io3    (flash_io3)
+    );
+
+//-------------------------------------
+
+// detect pin toggle
+task portd_detect_pin_toggle;
+input [7:0] pin_n;
+begin
+   wait(port_d_in[pin_n] == 1'b1);
+   wait(port_d_in[pin_n] == 1'b0);
+   $display("PORT-D Pin : %x Toggle Detected",pin_n);
+
+end
+endtask
 
 
 task wb_user_core_write;
diff --git a/verilog/dv/arduino_ascii_table/arduino_ascii_table.ino.cpp b/verilog/dv/arduino_ascii_table/arduino_ascii_table.ino.cpp
index 07a49d4..a2d7001 100644
--- a/verilog/dv/arduino_ascii_table/arduino_ascii_table.ino.cpp
+++ b/verilog/dv/arduino_ascii_table/arduino_ascii_table.ino.cpp
@@ -1,5 +1,4 @@
 #include <Arduino.h>
-#line 1 "/tmp/.arduinoIDE-unsaved202265-51666-197w8ma.2pxu/ASCIITable/ASCIITable.ino"
 /*
   ASCII table
 
@@ -21,11 +20,8 @@
   https://www.arduino.cc/en/Tutorial/BuiltInExamples/ASCIITable
 */
 
-#line 22 "/tmp/.arduinoIDE-unsaved202265-51666-197w8ma.2pxu/ASCIITable/ASCIITable.ino"
 void setup();
-#line 39 "/tmp/.arduinoIDE-unsaved202265-51666-197w8ma.2pxu/ASCIITable/ASCIITable.ino"
 void loop();
-#line 22 "/tmp/.arduinoIDE-unsaved202265-51666-197w8ma.2pxu/ASCIITable/ASCIITable.ino"
 // first visible ASCIIcharacter '!' is number 33:
 int thisByte = 33;
 void setup() {
diff --git a/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v b/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v
index af4e082..e6fa954 100644
--- a/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v
+++ b/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v
@@ -18,30 +18,23 @@
 ////                                                              ////
 ////  Standalone User validation Test bench                       ////
 ////                                                              ////
-////  This file is part of the YIFive cores project               ////
-////  https://github.com/dineshannayya/yifive_r0.git              ////
-////  http://www.opencores.org/cores/yifive/                      ////
+////  This file is part of the riscdunio cores project            ////
+////  https://github.com/dineshannayya/riscdunio.git              ////
 ////                                                              ////
 ////  Description                                                 ////
 ////   This is a standalone test bench to validate the            ////
 ////   Digital core.                                              ////
-////   1. User Risc core is booted using  compiled code of        ////
-////      user_risc_boot.c                                        ////
-////   2. User Risc core uses Serial Flash and SDRAM to boot      ////
-////   3. After successful boot, Risc core will  write signature  ////
-////      in to  user register from 0x1003_0058 to 0x1003_006C    ////
-////   4. Through the External Wishbone Interface we read back    ////
-////       from 0x3003_0058 to 0x3003_006C                        ////
-////       and validate the user register to declared pass fail   ////
+////   This test bench to valid Arduino example:                  ////
+////     <example><04.Communication><ASCIITable>                  ////
 ////                                                              ////
 ////  To Do:                                                      ////
 ////    nothing                                                   ////
 ////                                                              ////
 ////  Author(s):                                                  ////
-////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////      - Dinesh Annayya, dinesh.annayya@gmail.com              ////
 ////                                                              ////
 ////  Revision :                                                  ////
-////    0.1 - 16th Feb 2021, Dinesh A                             ////
+////    0.1 - 29th July 2022, Dinesh A                            ////
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
@@ -188,14 +181,14 @@
        
 
 	initial begin
-               uart_data_bit           = 2'b11;
-               uart_stop_bits          = 0; // 0: 1 stop bit; 1: 2 stop bit;
-               uart_stick_parity       = 0; // 1: force even parity
-               uart_parity_en          = 0; // parity enable
-               uart_even_odd_parity    = 1; // 0: odd parity; 1: even parity
-	       tb_set_uart_baud(50000000,1152000,uart_divisor);// 50Mhz Ref clock, Baud Rate: 230400
-               uart_timeout            = 2000;// wait time limit
-               uart_fifo_enable        = 0;	// fifo mode disable
+        uart_data_bit           = 2'b11;
+        uart_stop_bits          = 0; // 0: 1 stop bit; 1: 2 stop bit;
+        uart_stick_parity       = 0; // 1: force even parity
+        uart_parity_en          = 0; // parity enable
+        uart_even_odd_parity    = 1; // 0: odd parity; 1: even parity
+	    tb_set_uart_baud(50000000,1152000,uart_divisor);// 50Mhz Ref clock, Baud Rate: 230400
+        uart_timeout            = 2000;// wait time limit
+        uart_fifo_enable        = 0;	// fifo mode disable
 
 		$value$plusargs("risc_core_id=%d", d_risc_id);
 
@@ -208,61 +201,59 @@
 
 	        repeat (2) @(posedge clock);
 		#1;
-                // Remove all the reset
-                if(d_risc_id == 0) begin
-                     $display("STATUS: Working with Risc core 0");
-                     wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
-                end else if(d_risc_id == 1) begin
-                     $display("STATUS: Working with Risc core 1");
-                     wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
-                end else if(d_risc_id == 2) begin
-                     $display("STATUS: Working with Risc core 2");
-                     wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h41F);
-                end else if(d_risc_id == 3) begin
-                     $display("STATUS: Working with Risc core 3");
-                     wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h81F);
-                end
+        // Remove all the reset
+        if(d_risc_id == 0) begin
+             $display("STATUS: Working with Risc core 0");
+             wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
+        end else if(d_risc_id == 1) begin
+             $display("STATUS: Working with Risc core 1");
+             wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
+        end else if(d_risc_id == 2) begin
+             $display("STATUS: Working with Risc core 2");
+             wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F);
+        end else if(d_risc_id == 3) begin
+             $display("STATUS: Working with Risc core 3");
+             wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
+        end
 
-                repeat (100) @(posedge clock);  // wait for Processor Get Ready
+        repeat (100) @(posedge clock);  // wait for Processor Get Ready
 
-	        tb_uart.debug_mode = 0; // disable debug display
-                tb_uart.uart_init;
-                tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, 
-                                               uart_stick_parity, uart_timeout, uart_divisor);
+	    tb_uart.debug_mode = 0; // disable debug display
+        tb_uart.uart_init;
+        tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, uart_stick_parity, uart_timeout, uart_divisor);
 
-                repeat (45000) @(posedge clock);  // wait for Processor Get Ready
-	        flag  = 0;
+        repeat (45000) @(posedge clock);  // wait for Processor Get Ready
+	    flag  = 0;
 		check_sum = 0;
-                
-                
-                fork
-                   begin
-                      while(flag == 0)
-                      begin
-                         tb_uart.read_char(read_data,flag);
-			 if(flag == 0)  begin
-			    $write ("%c",read_data);
-			    check_sum = check_sum+read_data;
+            
+        fork
+           begin
+              while(flag == 0)
+              begin
+                 tb_uart.read_char(read_data,flag);
+		         if(flag == 0)  begin
+		            $write ("%c",read_data);
+		            check_sum = check_sum+read_data;
 		         end
-                      end
-                   end
-                   begin
-                      repeat (3000000) @(posedge clock);  // wait for Processor Get Ready
-                   end
-                   join_any
-                
-                   #100
-                   tb_uart.report_status(uart_rx_nu, uart_tx_nu);
-                
-                   test_fail = 0;
+              end
+           end
+           begin
+              repeat (3000000) @(posedge clock);  // wait for Processor Get Ready
+           end
+           join_any
+            
+           #100
+           tb_uart.report_status(uart_rx_nu, uart_tx_nu);
+            
 
+           test_fail = 0;
 		   $display("Total Rx Char: %d Check Sum : %x ",uart_rx_nu, check_sum);
-                   // Check 
-                   // if all the 4224 byte received
-                   // if no error 
-                   if(uart_rx_nu != 4224) test_fail = 1;
-                   if(check_sum != 32'h3f01b) test_fail = 1;
-                   if(tb_uart.err_cnt != 0) test_fail = 1;
+             // Check 
+             // if all the 4224 byte received
+             // if no error 
+             if(uart_rx_nu != 4224) test_fail = 1;
+             if(check_sum != 32'h3f01b) test_fail = 1;
+             if(tb_uart.err_cnt != 0) test_fail = 1;
 
 	   
 	    	$display("###################################################");
diff --git a/verilog/dv/arduino_character_analysis/Makefile b/verilog/dv/arduino_character_analysis/Makefile
new file mode 100644
index 0000000..9293db4
--- /dev/null
+++ b/verilog/dv/arduino_character_analysis/Makefile
@@ -0,0 +1,140 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+ 
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+DESIGNS?=../../..
+TOOLS?=/opt/riscv32i/
+
+export USER_PROJECT_VERILOG ?=  $(DESIGNS)/verilog
+export RISCDUINO_BOARD ?=  $(USER_PROJECT_VERILOG)/dv/common/riscduino_board/custom_board/riscduino
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+GCC_PREFIX?=riscv32-unknown-elf
+
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+RISC_CORE?=0
+
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
+.SUFFIXES:
+
+PATTERN = arduino_character_analysis
+
+all:  ${PATTERN:=.vcd}
+
+
+vvp:  ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${PATTERN}.ino.cpp -o ${PATTERN}.ino.cpp.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/Print.cpp -o Print.cpp.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WMath.cpp -o WMath.cpp.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WString.cpp -o WString.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WInterrupts.c -o WInterrupts.c.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/fe300prci/fe300prci_driver.c -o fe300prci_driver.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/abi.cpp -o abi.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/plic/plic_driver.c -o plic_driver.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/UARTClass.cpp -o UARTClass.cpp.o
+	${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/entry.S -o entry.S.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/hooks.c -o hooks.c.o
+	${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/init.S -o init.S.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/itoa.c -o itoa.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/main.cpp -o main.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/malloc.c -o malloc.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/new.cpp -o new.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/sbrk.c -o sbrk.c.o
+	${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/start.S -o start.S.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring.c -o wiring.c.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_analog.c -o wiring_analog.c.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_digital.c -o wiring_digital.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_pulse.cpp -o wiring_pulse.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_shift.c -o wiring_shift.c.o
+	${GCC_PREFIX}-ar rcs core.a Print.cpp.o
+	${GCC_PREFIX}-ar rcs core.a UARTClass.cpp.o
+	${GCC_PREFIX}-ar rcs core.a WInterrupts.c.o
+	${GCC_PREFIX}-ar rcs core.a WMath.cpp.o
+	${GCC_PREFIX}-ar rcs core.a WString.cpp.o
+	${GCC_PREFIX}-ar rcs core.a abi.cpp.o
+	${GCC_PREFIX}-ar rcs core.a fe300prci_driver.c.o
+	${GCC_PREFIX}-ar rcs core.a plic_driver.c.o
+	${GCC_PREFIX}-ar rcs core.a entry.S.o
+	${GCC_PREFIX}-ar rcs core.a hooks.c.o
+	${GCC_PREFIX}-ar rcs core.a init.S.o
+	${GCC_PREFIX}-ar rcs core.a itoa.c.o
+	${GCC_PREFIX}-ar rcs core.a main.cpp.o
+	${GCC_PREFIX}-ar rcs core.a malloc.c.o
+	${GCC_PREFIX}-ar rcs core.a new.cpp.o
+	${GCC_PREFIX}-ar rcs core.a sbrk.c.o
+	${GCC_PREFIX}-ar rcs core.a start.S.o
+	${GCC_PREFIX}-ar rcs core.a wiring.c.o
+	${GCC_PREFIX}-ar rcs core.a wiring_analog.c.o
+	${GCC_PREFIX}-ar rcs core.a wiring_digital.c.o
+	${GCC_PREFIX}-ar rcs core.a wiring_pulse.cpp.o
+	${GCC_PREFIX}-ar rcs core.a wiring_shift.c.o
+	${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf
+	${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.ino.elf ${PATTERN}.ino.bin
+	${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.ino.elf ${PATTERN}.ino.hex
+	${GCC_PREFIX}-objdump -D  ${PATTERN}.ino.elf >   ${PATTERN}.ino.dump
+	rm *.o *.a
+ifeq ($(SIM),RTL)
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
+	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
+	$< -o $@ 
+   endif
+else  
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+   endif
+endif
+
+%.vcd: %.vvp
+	vvp $< +risc_core_id=$(RISC_CORE)
+
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump *.a *.o
+
+.PHONY: clean hex all
diff --git a/verilog/dv/arduino_character_analysis/arduino_character_analysis.ino b/verilog/dv/arduino_character_analysis/arduino_character_analysis.ino
new file mode 100644
index 0000000..e7a3c23
--- /dev/null
+++ b/verilog/dv/arduino_character_analysis/arduino_character_analysis.ino
@@ -0,0 +1,85 @@
+/*
+  Character analysis operators
+
+  Examples using the character analysis operators.
+  Send any byte and the sketch will tell you about it.
+
+  created 29 Nov 2010
+  modified 2 Apr 2012
+  by Tom Igoe
+
+  This example code is in the public domain.
+
+  https://www.arduino.cc/en/Tutorial/BuiltInExamples/CharacterAnalysis
+*/
+
+void setup() {
+  // Open serial communications and wait for port to open:
+  Serial.begin(9600);
+  while (!Serial) {
+    ; // wait for serial port to connect. Needed for native USB port only
+  }
+
+  // send an intro:
+  Serial.println("send any byte and I'll tell you everything I can about it");
+  Serial.println();
+}
+
+void loop() {
+  // get any incoming bytes:
+  if (Serial.available() > 0) {
+    int thisChar = Serial.read();
+
+    // say what was sent:
+    Serial.print("You sent me: \'");
+    Serial.write(thisChar);
+    Serial.print("\'  ASCII Value: ");
+    Serial.println(thisChar);
+
+    // analyze what was sent:
+    if (isAlphaNumeric(thisChar)) {
+      Serial.println("it's alphanumeric");
+    }
+    if (isAlpha(thisChar)) {
+      Serial.println("it's alphabetic");
+    }
+    if (isAscii(thisChar)) {
+      Serial.println("it's ASCII");
+    }
+    if (isWhitespace(thisChar)) {
+      Serial.println("it's whitespace");
+    }
+    if (isControl(thisChar)) {
+      Serial.println("it's a control character");
+    }
+    if (isDigit(thisChar)) {
+      Serial.println("it's a numeric digit");
+    }
+    if (isGraph(thisChar)) {
+      Serial.println("it's a printable character that's not whitespace");
+    }
+    if (isLowerCase(thisChar)) {
+      Serial.println("it's lower case");
+    }
+    if (isPrintable(thisChar)) {
+      Serial.println("it's printable");
+    }
+    if (isPunct(thisChar)) {
+      Serial.println("it's punctuation");
+    }
+    if (isSpace(thisChar)) {
+      Serial.println("it's a space character");
+    }
+    if (isUpperCase(thisChar)) {
+      Serial.println("it's upper case");
+    }
+    if (isHexadecimalDigit(thisChar)) {
+      Serial.println("it's a valid hexadecimaldigit (i.e. 0 - 9, a - F, or A - F)");
+    }
+
+    // add some space and ask for another byte:
+    Serial.println();
+    Serial.println("Give me another byte:");
+    Serial.println();
+  }
+}
diff --git a/verilog/dv/arduino_character_analysis/arduino_character_analysis.ino.cpp b/verilog/dv/arduino_character_analysis/arduino_character_analysis.ino.cpp
new file mode 100644
index 0000000..ff39e85
--- /dev/null
+++ b/verilog/dv/arduino_character_analysis/arduino_character_analysis.ino.cpp
@@ -0,0 +1,89 @@
+#include <Arduino.h>
+/*
+  Character analysis operators
+
+  Examples using the character analysis operators.
+  Send any byte and the sketch will tell you about it.
+
+  created 29 Nov 2010
+  modified 2 Apr 2012
+  by Tom Igoe
+
+  This example code is in the public domain.
+
+  https://www.arduino.cc/en/Tutorial/BuiltInExamples/CharacterAnalysis
+*/
+
+void setup();
+void loop();
+void setup() {
+  // Open serial communications and wait for port to open:
+  Serial.begin(1152000);
+  while (!Serial) {
+    ; // wait for serial port to connect. Needed for native USB port only
+  }
+
+  // send an intro:
+  Serial.println("send any byte and I'll tell you everything I can about it");
+  Serial.println();
+}
+
+void loop() {
+  // get any incoming bytes:
+  if (Serial.available() > 0) {
+    int thisChar = Serial.read();
+
+    // say what was sent:
+    Serial.print("You sent me: \'");
+    Serial.write(thisChar);
+    Serial.print("\'  ASCII Value: ");
+    Serial.println(thisChar);
+
+    // analyze what was sent:
+    if (isAlphaNumeric(thisChar)) {
+      Serial.println("it's alphanumeric");
+    }
+    if (isAlpha(thisChar)) {
+      Serial.println("it's alphabetic");
+    }
+    if (isAscii(thisChar)) {
+      Serial.println("it's ASCII");
+    }
+    if (isWhitespace(thisChar)) {
+      Serial.println("it's whitespace");
+    }
+    if (isControl(thisChar)) {
+      Serial.println("it's a control character");
+    }
+    if (isDigit(thisChar)) {
+      Serial.println("it's a numeric digit");
+    }
+    if (isGraph(thisChar)) {
+      Serial.println("it's a printable character that's not whitespace");
+    }
+    if (isLowerCase(thisChar)) {
+      Serial.println("it's lower case");
+    }
+    if (isPrintable(thisChar)) {
+      Serial.println("it's printable");
+    }
+    if (isPunct(thisChar)) {
+      Serial.println("it's punctuation");
+    }
+    if (isSpace(thisChar)) {
+      Serial.println("it's a space character");
+    }
+    if (isUpperCase(thisChar)) {
+      Serial.println("it's upper case");
+    }
+    if (isHexadecimalDigit(thisChar)) {
+      Serial.println("it's a valid hexadecimaldigit (i.e. 0 - 9, a - F, or A - F)");
+    }
+
+    // add some space and ask for another byte:
+    Serial.println();
+    Serial.println("Give me another byte:");
+    Serial.println();
+  }
+}
+
diff --git a/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v b/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v
new file mode 100644
index 0000000..af8c31f
--- /dev/null
+++ b/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v
@@ -0,0 +1,571 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  Standalone User validation Test bench                       ////
+////                                                              ////
+////  This file is part of the riscdunio cores project            ////
+////  https://github.com/dineshannayya/riscdunio.git              ////
+////                                                              ////
+////  Description                                                 ////
+////   This is a standalone test bench to validate the            ////
+////   Digital core.                                              ////
+////   This test bench to valid Arduino example:                  ////
+////     <example><08.strings><CharacterAnalysis>                 ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesh.annayya@gmail.com              ////
+////                                                              ////
+////  Revision :                                                  ////
+////    0.1 - 29th July 2022, Dinesh A                            ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+`default_nettype wire
+
+`timescale 1 ns / 1 ns
+
+`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+`include "uart_agent.v"
+`include "is62wvs1288.v"
+
+module arduino_character_analysis;
+	reg clock;
+	reg wb_rst_i;
+	reg power1, power2;
+	reg power3, power4;
+
+        reg        wbd_ext_cyc_i;  // strobe/request
+        reg        wbd_ext_stb_i;  // strobe/request
+        reg [31:0] wbd_ext_adr_i;  // address
+        reg        wbd_ext_we_i;  // write
+        reg [31:0] wbd_ext_dat_i;  // data output
+        reg [3:0]  wbd_ext_sel_i;  // byte enable
+
+        wire [31:0] wbd_ext_dat_o;  // data input
+        wire        wbd_ext_ack_o;  // acknowlegement
+        wire        wbd_ext_err_o;  // error
+
+	// User I/O
+	wire [37:0] io_oeb;
+	wire [37:0] io_out;
+	wire [37:0] io_in;
+
+	wire gpio;
+	wire [37:0] mprj_io;
+	wire [7:0] mprj_io_0;
+	reg         test_fail;
+	reg [31:0] read_data;
+        //----------------------------------
+        // Uart Configuration
+        // ---------------------------------
+        reg [1:0]      uart_data_bit        ;
+        reg	       uart_stop_bits       ; // 0: 1 stop bit; 1: 2 stop bit;
+        reg	       uart_stick_parity    ; // 1: force even parity
+        reg	       uart_parity_en       ; // parity enable
+        reg	       uart_even_odd_parity ; // 0: odd parity; 1: even parity
+        
+        reg [7:0]      uart_data            ;
+        reg [15:0]     uart_divisor         ;	// divided by n * 16
+        reg [15:0]     uart_timeout         ;// wait time limit
+        
+        reg [15:0]     uart_rx_nu           ;
+        reg [15:0]     uart_tx_nu           ;
+        reg [7:0]      uart_write_data [0:39];
+        reg 	       uart_fifo_enable     ;	// fifo mode disable
+	reg            flag                 ;
+
+	reg [31:0]     check_sum            ;
+        
+	integer    d_risc_id;
+
+         integer i,j;
+
+parameter P_FSM_C      = 4'b0000; // Command Phase Only
+parameter P_FSM_CW     = 4'b0001; // Command + Write DATA Phase Only
+parameter P_FSM_CA     = 4'b0010; // Command -> Address Phase Only
+
+parameter P_FSM_CAR    = 4'b0011; // Command -> Address -> Read Data
+parameter P_FSM_CADR   = 4'b0100; // Command -> Address -> Dummy -> Read Data
+parameter P_FSM_CAMR   = 4'b0101; // Command -> Address -> Mode -> Read Data
+parameter P_FSM_CAMDR  = 4'b0110; // Command -> Address -> Mode -> Dummy -> Read Data
+
+parameter P_FSM_CAW    = 4'b0111; // Command -> Address ->Write Data
+parameter P_FSM_CADW   = 4'b1000; // Command -> Address -> DUMMY + Write Data
+parameter P_FSM_CAMW   = 4'b1001; // Command -> Address -> MODE + Write Data
+
+parameter P_FSM_CDR    = 4'b1010; // COMMAND -> DUMMY -> READ
+parameter P_FSM_CDW    = 4'b1011; // COMMAND -> DUMMY -> WRITE
+parameter P_FSM_CR     = 4'b1100;  // COMMAND -> READ
+
+parameter P_MODE_SWITCH_IDLE     = 2'b00;
+parameter P_MODE_SWITCH_AT_ADDR  = 2'b01;
+parameter P_MODE_SWITCH_AT_DATA  = 2'b10;
+
+parameter P_SINGLE = 2'b00;
+parameter P_DOUBLE = 2'b01;
+parameter P_QUAD   = 2'b10;
+parameter P_QDDR   = 2'b11;
+
+
+
+	// 50Mhz CLock
+	always #10 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	        flag  = 0;
+                wbd_ext_cyc_i ='h0;  // strobe/request
+                wbd_ext_stb_i ='h0;  // strobe/request
+                wbd_ext_adr_i ='h0;  // address
+                wbd_ext_we_i  ='h0;  // write
+                wbd_ext_dat_i ='h0;  // data output
+                wbd_ext_sel_i ='h0;  // byte enable
+	end
+
+	`ifdef WFDUMP
+	   initial begin
+	   	$dumpfile("simx.vcd");
+	   	$dumpvars(3, arduino_character_analysis);
+	   	$dumpvars(0, arduino_character_analysis.u_top.u_riscv_top.i_core_top_0);
+	   	$dumpvars(0, arduino_character_analysis.u_top.u_riscv_top.u_connect);
+	   	$dumpvars(0, arduino_character_analysis.u_top.u_riscv_top.u_intf);
+	   	$dumpvars(0, arduino_character_analysis.u_top.u_uart_i2c_usb_spi.u_uart0_core);
+	   end
+       `endif
+
+       /*************************************************************************
+       * This is Baud Rate to clock divider conversion for Test Bench
+       * Note: DUT uses 16x baud clock, where are test bench uses directly
+       * baud clock, Due to 16x Baud clock requirement at RTL, there will be
+       * some resolution loss, we expect at lower baud rate this resolution
+       * loss will be less. For Quick simulation perpose higher baud rate used
+       * *************************************************************************/
+       task tb_set_uart_baud;
+       input [31:0] ref_clk;
+       input [31:0] baud_rate;
+       output [31:0] baud_div;
+       reg   [31:0] baud_div;
+       begin
+	  // for 230400 Baud = (50Mhz/230400) = 216.7
+	  baud_div = ref_clk/baud_rate; // Get the Bit Baud rate
+	  // Baud 16x = 216/16 = 13
+          baud_div = baud_div/16; // To find the RTL baud 16x div value to find similar resolution loss in test bench
+	  // Test bench baud clock , 16x of above value
+	  // 13 * 16 = 208,  
+	  // (Note if you see original value was 216, now it's 208 )
+          baud_div = baud_div * 16;
+	  // Test bench half cycle counter to toggle it 
+	  // 208/2 = 104
+           baud_div = baud_div/2;
+	  //As counter run's from 0 , substract from 1
+	   baud_div = baud_div-1;
+       end
+       endtask
+       
+
+	initial begin
+        uart_data_bit           = 2'b11;
+        uart_stop_bits          = 0; // 0: 1 stop bit; 1: 2 stop bit;
+        uart_stick_parity       = 0; // 1: force even parity
+        uart_parity_en          = 0; // parity enable
+        uart_even_odd_parity    = 1; // 0: odd parity; 1: even parity
+	    tb_set_uart_baud(50000000,1152000,uart_divisor);// 50Mhz Ref clock, Baud Rate: 230400
+        uart_timeout            = 2000;// wait time limit
+        uart_fifo_enable        = 0;	// fifo mode disable
+
+		$value$plusargs("risc_core_id=%d", d_risc_id);
+
+		#200; // Wait for reset removal
+	    repeat (10) @(posedge clock);
+		$display("Monitor: Standalone User Risc Boot Test Started");
+
+		// Remove Wb Reset
+		wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+
+	        repeat (2) @(posedge clock);
+		#1;
+        // Remove WB and SPI Reset and CORE under Reset
+        wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F);
+
+		// QSPI SRAM:CS#2 Switch to QSPI Mode
+        wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h38});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0);
+        // Remove all the reset
+        if(d_risc_id == 0) begin
+             $display("STATUS: Working with Risc core 0");
+             wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
+        end else if(d_risc_id == 1) begin
+             $display("STATUS: Working with Risc core 1");
+             wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
+        end else if(d_risc_id == 2) begin
+             $display("STATUS: Working with Risc core 2");
+             wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F);
+        end else if(d_risc_id == 3) begin
+             $display("STATUS: Working with Risc core 3");
+             wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
+        end
+
+        repeat (100) @(posedge clock);  // wait for Processor Get Ready
+
+	    tb_uart.debug_mode = 0; // disable debug display
+        tb_uart.uart_init;
+        tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, 
+                                           uart_stick_parity, uart_timeout, uart_divisor);
+
+        repeat (40000) @(posedge clock);  // wait for Processor Get Ready
+	    flag  = 0;
+		check_sum = 0;
+        fork
+        begin 
+           fork
+           begin
+               tb_uart.write_char ("A");
+               tb_uart.write_char (" ");
+               tb_uart.write_char ("\n");
+               tb_uart.write_char ("b");
+               tb_uart.write_char (";");
+               tb_uart.write_char ("F");
+           end
+           begin
+              while(flag == 0)
+              begin
+                 tb_uart.read_char(read_data,flag);
+		         if(flag == 0)  begin
+		            $write ("%c",read_data);
+		            check_sum = check_sum+read_data;
+		         end
+              end
+           end
+           join
+        end
+        begin
+           repeat (3000000) @(posedge clock);  // wait for Processor Get Ready
+        end
+        join_any
+                
+           #100
+           tb_uart.report_status(uart_rx_nu, uart_tx_nu);
+           
+           test_fail = 0;
+
+		   $display("Total Rx Char: %d Check Sum : %x ",uart_rx_nu, check_sum);
+           // Check 
+           // if all the 4224 byte received
+           // if no error 
+           if(uart_rx_nu != 1236) test_fail = 1;
+           if(check_sum != 32'h180b7) test_fail = 1;
+           if(tb_uart.err_cnt != 0) test_fail = 1;
+
+	    	$display("###################################################");
+          	if(test_fail == 0) begin
+		   `ifdef GL
+	    	   $display("Monitor: character_analysis (GL) Passed");
+		   `else
+		       $display("Monitor: character_analysis (RTL) Passed");
+		   `endif
+	        end else begin
+		    `ifdef GL
+	    	   $display("Monitor: character_analysis (GL) Failed");
+		    `else
+		       $display("Monitor: character_analysis (RTL) Failed");
+		    `endif
+		 end
+	    	$display("###################################################");
+	    $finish;
+	end
+
+	initial begin
+		wb_rst_i <= 1'b1;
+		#100;
+		wb_rst_i <= 1'b0;	    	// Release reset
+	end
+wire USER_VDD1V8 = 1'b1;
+wire VSS = 1'b0;
+
+user_project_wrapper u_top(
+`ifdef USE_POWER_PINS
+    .vccd1(USER_VDD1V8),	// User area 1 1.8V supply
+    .vssd1(VSS),	// User area 1 digital ground
+`endif
+    .wb_clk_i        (clock),  // System clock
+    .user_clock2     (1'b1),  // Real-time clock
+    .wb_rst_i        (wb_rst_i),  // Regular Reset signal
+
+    .wbs_cyc_i   (wbd_ext_cyc_i),  // strobe/request
+    .wbs_stb_i   (wbd_ext_stb_i),  // strobe/request
+    .wbs_adr_i   (wbd_ext_adr_i),  // address
+    .wbs_we_i    (wbd_ext_we_i),  // write
+    .wbs_dat_i   (wbd_ext_dat_i),  // data output
+    .wbs_sel_i   (wbd_ext_sel_i),  // byte enable
+
+    .wbs_dat_o   (wbd_ext_dat_o),  // data input
+    .wbs_ack_o   (wbd_ext_ack_o),  // acknowlegement
+
+ 
+    // Logic Analyzer Signals
+    .la_data_in      ('1) ,
+    .la_data_out     (),
+    .la_oenb         ('0),
+ 
+
+    // IOs
+    .io_in          (io_in)  ,
+    .io_out         (io_out) ,
+    .io_oeb         (io_oeb) ,
+
+    .user_irq       () 
+
+);
+
+`ifndef GL // Drive Power for Hold Fix Buf
+    // All standard cell need power hook-up for functionality work
+    initial begin
+
+    end
+`endif    
+
+//------------------------------------------------------
+//  Integrate the Serial flash with qurd support to
+//  user core using the gpio pads
+//  ----------------------------------------------------
+
+   wire flash_clk = io_out[24];
+   wire flash_csb = io_out[25];
+   // Creating Pad Delay
+   wire #1 io_oeb_29 = io_oeb[29];
+   wire #1 io_oeb_30 = io_oeb[30];
+   wire #1 io_oeb_31 = io_oeb[31];
+   wire #1 io_oeb_32 = io_oeb[32];
+   tri  #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz;
+   tri  #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz;
+   tri  #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz;
+   tri  #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz;
+
+   assign io_in[29] = flash_io0;
+   assign io_in[30] = flash_io1;
+   assign io_in[31] = flash_io2;
+   assign io_in[32] = flash_io3;
+
+   // Quard flash
+     s25fl256s #(.mem_file_name("arduino_character_analysis.ino.hex"),
+	         .otp_file_name("none"),
+                 .TimingModel("S25FL512SAGMFI010_F_30pF")) 
+		 u_spi_flash_256mb (
+           // Data Inputs/Outputs
+       .SI      (flash_io0),
+       .SO      (flash_io1),
+       // Controls
+       .SCK     (flash_clk),
+       .CSNeg   (flash_csb),
+       .WPNeg   (flash_io2),
+       .HOLDNeg (flash_io3),
+       .RSTNeg  (!wb_rst_i)
+
+       );
+
+   wire spiram_csb = io_out[27];
+
+   is62wvs1288 #(.mem_file_name("none"))
+	u_sram (
+         // Data Inputs/Outputs
+           .io0     (flash_io0),
+           .io1     (flash_io1),
+           // Controls
+           .clk    (flash_clk),
+           .csb    (spiram_csb),
+           .io2    (flash_io2),
+           .io3    (flash_io3)
+    );
+
+//---------------------------
+//  UART Agent integration
+// --------------------------
+wire uart_txd,uart_rxd;
+
+assign uart_txd   = io_out[2];
+assign io_in[1]  = uart_rxd ;
+ 
+uart_agent tb_uart(
+	.mclk                (clock              ),
+	.txd                 (uart_rxd           ),
+	.rxd                 (uart_txd           )
+	);
+
+
+task wb_user_core_write;
+input [31:0] address;
+input [31:0] data;
+begin
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_adr_i =address;  // address
+  wbd_ext_we_i  ='h1;  // write
+  wbd_ext_dat_i =data;  // data output
+  wbd_ext_sel_i ='hF;  // byte enable
+  wbd_ext_cyc_i ='h1;  // strobe/request
+  wbd_ext_stb_i ='h1;  // strobe/request
+  wait(wbd_ext_ack_o == 1);
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_cyc_i ='h0;  // strobe/request
+  wbd_ext_stb_i ='h0;  // strobe/request
+  wbd_ext_adr_i ='h0;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='h0;  // data output
+  wbd_ext_sel_i ='h0;  // byte enable
+  $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
+  repeat (2) @(posedge clock);
+end
+endtask
+
+task  wb_user_core_read;
+input [31:0] address;
+output [31:0] data;
+reg    [31:0] data;
+begin
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_adr_i =address;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='0;  // data output
+  wbd_ext_sel_i ='hF;  // byte enable
+  wbd_ext_cyc_i ='h1;  // strobe/request
+  wbd_ext_stb_i ='h1;  // strobe/request
+  wait(wbd_ext_ack_o == 1);
+  repeat (1) @(negedge clock);
+  data  = wbd_ext_dat_o;  
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_cyc_i ='h0;  // strobe/request
+  wbd_ext_stb_i ='h0;  // strobe/request
+  wbd_ext_adr_i ='h0;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='h0;  // data output
+  wbd_ext_sel_i ='h0;  // byte enable
+  $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
+  repeat (2) @(posedge clock);
+end
+endtask
+
+task  wb_user_core_read_check;
+input [31:0] address;
+output [31:0] data;
+input [31:0] cmp_data;
+reg    [31:0] data;
+begin
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_adr_i =address;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='0;  // data output
+  wbd_ext_sel_i ='hF;  // byte enable
+  wbd_ext_cyc_i ='h1;  // strobe/request
+  wbd_ext_stb_i ='h1;  // strobe/request
+  wait(wbd_ext_ack_o == 1);
+  repeat (1) @(negedge clock);
+  data  = wbd_ext_dat_o;  
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_cyc_i ='h0;  // strobe/request
+  wbd_ext_stb_i ='h0;  // strobe/request
+  wbd_ext_adr_i ='h0;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='h0;  // data output
+  wbd_ext_sel_i ='h0;  // byte enable
+  if(data !== cmp_data) begin
+     $display("ERROR : WB USER ACCESS READ  Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
+     test_fail = 1;
+  end else begin
+     $display("STATUS: WB USER ACCESS READ  Address : 0x%x, Data : 0x%x",address,data);
+  end
+  repeat (2) @(posedge clock);
+end
+endtask
+
+`ifdef GL
+
+wire        wbd_spi_stb_i   = u_top.u_qspi_master.wbd_stb_i;
+wire        wbd_spi_ack_o   = u_top.u_qspi_master.wbd_ack_o;
+wire        wbd_spi_we_i    = u_top.u_qspi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i   = u_top.u_qspi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i   = u_top.u_qspi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o   = u_top.u_qspi_master.wbd_dat_o;
+wire [3:0]  wbd_spi_sel_i   = u_top.u_qspi_master.wbd_sel_i;
+
+wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb_spi.reg_cs;
+wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb_spi.reg_ack;
+wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb_spi.reg_wr;
+wire [8:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb_spi.reg_addr;
+wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb_spi.reg_wdata;
+wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb_spi.reg_rdata;
+wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb_spi.reg_be;
+
+`endif
+
+/**
+`ifdef GL
+//-----------------------------------------------------------------------------
+// RISC IMEM amd DMEM Monitoring TASK
+//-----------------------------------------------------------------------------
+
+`define RISC_CORE  user_uart_tb.u_top.u_core.u_riscv_top
+
+always@(posedge `RISC_CORE.wb_clk) begin
+    if(`RISC_CORE.wbd_imem_ack_i)
+          $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
+    if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
+          $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
+    if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
+          $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
+end
+
+`endif
+**/
+endmodule
+`include "s25fl256s.sv"
+`default_nettype wire
diff --git a/verilog/dv/arduino_digital_port_control/Makefile b/verilog/dv/arduino_digital_port_control/Makefile
new file mode 100644
index 0000000..7168229
--- /dev/null
+++ b/verilog/dv/arduino_digital_port_control/Makefile
@@ -0,0 +1,142 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+ 
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+DESIGNS?=../../..
+TOOLS?=/opt/riscv32i/
+
+export USER_PROJECT_VERILOG ?=  $(DESIGNS)/verilog
+export RISCDUINO_BOARD ?=  $(USER_PROJECT_VERILOG)/dv/common/riscduino_board/custom_board/riscduino
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+GCC_PREFIX?=riscv32-unknown-elf
+
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+RISC_CORE?=0
+
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
+.SUFFIXES:
+
+PATTERN = arduino_digital_port_control
+
+all:  ${PATTERN:=.vcd}
+
+
+vvp:  ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard -I${RISCDUINO_BOARD}/libraries/SPI/src ${PATTERN}.ino.cpp -o ${PATTERN}.ino.cpp.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard -I${RISCDUINO_BOARD}/libraries/SPI/src ${RISCDUINO_BOARD}/libraries/SPI/src/SPI.cpp -o SPI.cpp.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/Print.cpp -o Print.cpp.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WMath.cpp -o WMath.cpp.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WString.cpp -o WString.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WInterrupts.c -o WInterrupts.c.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/fe300prci/fe300prci_driver.c -o fe300prci_driver.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/abi.cpp -o abi.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/plic/plic_driver.c -o plic_driver.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/UARTClass.cpp -o UARTClass.cpp.o
+	${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/entry.S -o entry.S.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/hooks.c -o hooks.c.o
+	${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/init.S -o init.S.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/itoa.c -o itoa.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/main.cpp -o main.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/malloc.c -o malloc.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/new.cpp -o new.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/sbrk.c -o sbrk.c.o
+	${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/start.S -o start.S.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring.c -o wiring.c.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_analog.c -o wiring_analog.c.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_digital.c -o wiring_digital.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_pulse.cpp -o wiring_pulse.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_shift.c -o wiring_shift.c.o
+	${GCC_PREFIX}-ar rcs core.a Print.cpp.o
+	${GCC_PREFIX}-ar rcs core.a UARTClass.cpp.o
+	${GCC_PREFIX}-ar rcs core.a WInterrupts.c.o
+	${GCC_PREFIX}-ar rcs core.a WMath.cpp.o
+	${GCC_PREFIX}-ar rcs core.a WString.cpp.o
+	${GCC_PREFIX}-ar rcs core.a abi.cpp.o
+	${GCC_PREFIX}-ar rcs core.a fe300prci_driver.c.o
+	${GCC_PREFIX}-ar rcs core.a plic_driver.c.o
+	${GCC_PREFIX}-ar rcs core.a entry.S.o
+	${GCC_PREFIX}-ar rcs core.a hooks.c.o
+	${GCC_PREFIX}-ar rcs core.a init.S.o
+	${GCC_PREFIX}-ar rcs core.a itoa.c.o
+	${GCC_PREFIX}-ar rcs core.a main.cpp.o
+	${GCC_PREFIX}-ar rcs core.a malloc.c.o
+	${GCC_PREFIX}-ar rcs core.a new.cpp.o
+	${GCC_PREFIX}-ar rcs core.a sbrk.c.o
+	${GCC_PREFIX}-ar rcs core.a start.S.o
+	${GCC_PREFIX}-ar rcs core.a wiring.c.o
+	${GCC_PREFIX}-ar rcs core.a wiring_analog.c.o
+	${GCC_PREFIX}-ar rcs core.a wiring_digital.c.o
+	${GCC_PREFIX}-ar rcs core.a wiring_pulse.cpp.o
+	${GCC_PREFIX}-ar rcs core.a wiring_shift.c.o
+	${GCC_PREFIX}-ar rcs core.a SPI.cpp.o
+	${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf
+	${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.ino.elf ${PATTERN}.ino.bin
+	${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.ino.elf ${PATTERN}.ino.hex
+	${GCC_PREFIX}-objdump -D  ${PATTERN}.ino.elf >   ${PATTERN}.ino.dump
+	rm *.o *.a
+ifeq ($(SIM),RTL)
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
+	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
+	$< -o $@ 
+   endif
+else  
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+   endif
+endif
+
+%.vcd: %.vvp
+	vvp $< +risc_core_id=$(RISC_CORE)
+
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump *.a *.o
+
+.PHONY: clean hex all
diff --git a/verilog/dv/arduino_digital_port_control/arduino_digital_port_control.ino b/verilog/dv/arduino_digital_port_control/arduino_digital_port_control.ino
new file mode 100644
index 0000000..c7afcc0
--- /dev/null
+++ b/verilog/dv/arduino_digital_port_control/arduino_digital_port_control.ino
@@ -0,0 +1,71 @@
+/*
+  Digital Pot Control
+
+  This example controls an Analog Devices AD5206 digital potentiometer.
+  The AD5206 has 6 potentiometer channels. Each channel's pins are labeled
+  A - connect this to voltage
+  W - this is the pot's wiper, which changes when you set it
+  B - connect this to ground.
+
+ The AD5206 is SPI-compatible,and to command it, you send two bytes,
+ one with the channel number (0 - 5) and one with the resistance value for the
+ channel (0 - 255).
+
+ The circuit:
+  * All A pins  of AD5206 connected to +5V
+  * All B pins of AD5206 connected to ground
+  * An LED and a 220-ohm resisor in series connected from each W pin to ground
+  * CS - to digital pin 10  (SS pin)
+  * SDI - to digital pin 11 (MOSI pin)
+  * CLK - to digital pin 13 (SCK pin)
+
+ created 10 Aug 2010
+ by Tom Igoe
+
+ Thanks to Heather Dewey-Hagborg for the original tutorial, 2005
+
+*/
+
+
+// inslude the SPI library:
+#include <SPI.h>
+
+
+// set pin 10 as the slave select for the digital pot:
+const int slaveSelectPin = 10;
+
+void setup() {
+  // set the slaveSelectPin as an output:
+  pinMode(slaveSelectPin, OUTPUT);
+  // initialize SPI:
+  SPI.begin();
+}
+
+void loop() {
+  // go through the six channels of the digital pot:
+  for (int channel = 0; channel < 6; channel++) {
+    // change the resistance on this channel from min to max:
+    for (int level = 0; level < 255; level++) {
+      digitalPotWrite(channel, level);
+      delay(10);
+    }
+    // wait a second at the top:
+    delay(100);
+    // change the resistance on this channel from max to min:
+    for (int level = 0; level < 255; level++) {
+      digitalPotWrite(channel, 255 - level);
+      delay(10);
+    }
+  }
+
+}
+
+void digitalPotWrite(int address, int value) {
+  // take the SS pin low to select the chip:
+  digitalWrite(slaveSelectPin, LOW);
+  //  send in the address and value via SPI:
+  SPI.transfer(address);
+  SPI.transfer(value);
+  // take the SS pin high to de-select the chip:
+  digitalWrite(slaveSelectPin, HIGH);
+}
diff --git a/verilog/dv/arduino_digital_port_control/arduino_digital_port_control.ino.cpp b/verilog/dv/arduino_digital_port_control/arduino_digital_port_control.ino.cpp
new file mode 100644
index 0000000..d4dd6f5
--- /dev/null
+++ b/verilog/dv/arduino_digital_port_control/arduino_digital_port_control.ino.cpp
@@ -0,0 +1,76 @@
+#include <Arduino.h>
+/*
+  Digital Pot Control
+
+  This example controls an Analog Devices AD5206 digital potentiometer.
+  The AD5206 has 6 potentiometer channels. Each channel's pins are labeled
+  A - connect this to voltage
+  W - this is the pot's wiper, which changes when you set it
+  B - connect this to ground.
+
+ The AD5206 is SPI-compatible,and to command it, you send two bytes,
+ one with the channel number (0 - 5) and one with the resistance value for the
+ channel (0 - 255).
+
+ The circuit:
+  * All A pins  of AD5206 connected to +5V
+  * All B pins of AD5206 connected to ground
+  * An LED and a 220-ohm resisor in series connected from each W pin to ground
+  * CS - to digital pin 10  (SS pin)
+  * SDI - to digital pin 11 (MOSI pin)
+  * CLK - to digital pin 13 (SCK pin)
+
+ created 10 Aug 2010
+ by Tom Igoe
+
+ Thanks to Heather Dewey-Hagborg for the original tutorial, 2005
+
+*/
+
+
+// inslude the SPI library:
+#include <SPI.h>
+
+
+// set pin 10 as the slave select for the digital pot:
+const int slaveSelectPin = 10;
+
+void setup();
+void loop();
+void digitalPotWrite(int address, int value);
+void setup() {
+  // set the slaveSelectPin as an output:
+  pinMode(slaveSelectPin, OUTPUT);
+  // initialize SPI:
+  SPI.begin();
+}
+
+void loop() {
+  // go through the six channels of the digital pot:
+  for (int channel = 0; channel < 6; channel++) {
+    // change the resistance on this channel from min to max:
+    for (int level = 0; level < 255; level++) {
+      digitalPotWrite(channel, level);
+      delayMicroseconds(10);
+    }
+    // wait a second at the top:
+    delayMicroseconds(100);
+    // change the resistance on this channel from max to min:
+    for (int level = 0; level < 255; level++) {
+      digitalPotWrite(channel, 255 - level);
+      delayMicroseconds(10);
+    }
+  }
+
+}
+
+void digitalPotWrite(int address, int value) {
+  // take the SS pin low to select the chip:
+  digitalWrite(slaveSelectPin, LOW);
+  //  send in the address and value via SPI:
+  SPI.transfer(address);
+  SPI.transfer(value);
+  // take the SS pin high to de-select the chip:
+  digitalWrite(slaveSelectPin, HIGH);
+}
+
diff --git a/verilog/dv/user_mcore/user_mcore_tb.v b/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v
similarity index 64%
copy from verilog/dv/user_mcore/user_mcore_tb.v
copy to verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v
index b43dcba..1b1cbe1 100644
--- a/verilog/dv/user_mcore/user_mcore_tb.v
+++ b/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v
@@ -18,20 +18,23 @@
 ////                                                              ////
 ////  Standalone User validation Test bench                       ////
 ////                                                              ////
-////  This file is part of the riscduino cores project            ////
+////  This file is part of the riscdunio cores project            ////
+////  https://github.com/dineshannayya/riscdunio.git              ////
 ////                                                              ////
 ////  Description                                                 ////
 ////   This is a standalone test bench to validate the            ////
-////   Digital core multi-core behaviour.                         ////
+////   Digital core.                                              ////
+////   This test bench to valid Arduino example:                  ////
+////     <example><SPi><DigitalPortControl>                       ////
 ////                                                              ////
 ////  To Do:                                                      ////
 ////    nothing                                                   ////
 ////                                                              ////
 ////  Author(s):                                                  ////
-////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////      - Dinesh Annayya, dinesh.annayya@gmail.com              ////
 ////                                                              ////
 ////  Revision :                                                  ////
-////    0.1 - 16th Feb 2021, Dinesh A                             ////
+////    0.1 - 29th July 2022, Dinesh A                            ////
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
@@ -65,7 +68,10 @@
 `timescale 1 ns / 1 ns
 
 `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
-module user_mcore_tb;
+`include "is62wvs1288.v"
+`include "bfm_ad5205.sv"
+
+module arduino_digital_port_control_tb;
 	reg clock;
 	reg wb_rst_i;
 	reg power1, power2;
@@ -92,18 +98,49 @@
 	wire [7:0] mprj_io_0;
 	reg         test_fail;
 	reg [31:0] read_data;
+	reg            flag                 ;
+
+parameter P_FSM_C      = 4'b0000; // Command Phase Only
+parameter P_FSM_CW     = 4'b0001; // Command + Write DATA Phase Only
+parameter P_FSM_CA     = 4'b0010; // Command -> Address Phase Only
+
+parameter P_FSM_CAR    = 4'b0011; // Command -> Address -> Read Data
+parameter P_FSM_CADR   = 4'b0100; // Command -> Address -> Dummy -> Read Data
+parameter P_FSM_CAMR   = 4'b0101; // Command -> Address -> Mode -> Read Data
+parameter P_FSM_CAMDR  = 4'b0110; // Command -> Address -> Mode -> Dummy -> Read Data
+
+parameter P_FSM_CAW    = 4'b0111; // Command -> Address ->Write Data
+parameter P_FSM_CADW   = 4'b1000; // Command -> Address -> DUMMY + Write Data
+parameter P_FSM_CAMW   = 4'b1001; // Command -> Address -> MODE + Write Data
+
+parameter P_FSM_CDR    = 4'b1010; // COMMAND -> DUMMY -> READ
+parameter P_FSM_CDW    = 4'b1011; // COMMAND -> DUMMY -> WRITE
+parameter P_FSM_CR     = 4'b1100;  // COMMAND -> READ
+
+parameter P_MODE_SWITCH_IDLE     = 2'b00;
+parameter P_MODE_SWITCH_AT_ADDR  = 2'b01;
+parameter P_MODE_SWITCH_AT_DATA  = 2'b10;
+
+parameter P_SINGLE = 2'b00;
+parameter P_DOUBLE = 2'b01;
+parameter P_QUAD   = 2'b10;
+parameter P_QDDR   = 2'b11;
+
+        
 	integer    d_risc_id;
+    integer    channel,level;
+
+         integer i,j;
 
 
 
-	// External clock is used by default.  Make this artificially fast for the
-	// simulation.  Normally this would be a slow clock and the digital PLL
-	// would be the fast clock.
 
-	always #12.5 clock <= (clock === 1'b0);
+	// 50Mhz CLock
+	always #10 clock <= (clock === 1'b0);
 
 	initial begin
 		clock = 0;
+	        flag  = 0;
                 wbd_ext_cyc_i ='h0;  // strobe/request
                 wbd_ext_stb_i ='h0;  // strobe/request
                 wbd_ext_adr_i ='h0;  // address
@@ -115,72 +152,100 @@
 	`ifdef WFDUMP
 	   initial begin
 	   	$dumpfile("simx.vcd");
-	   	$dumpvars(1, user_mcore_tb);
-	   	$dumpvars(1, user_mcore_tb.u_top);
-	   	$dumpvars(0, user_mcore_tb.u_top.u_riscv_top);
+	   	$dumpvars(3, arduino_digital_port_control_tb);
+	   	//$dumpvars(0, arduino_digital_port_control_tb.u_top.u_riscv_top.i_core_top_0);
+	   	//$dumpvars(0, arduino_digital_port_control_tb.u_top.u_riscv_top.u_connect);
+	   	//$dumpvars(0, arduino_digital_port_control_tb.u_top.u_riscv_top.u_intf);
+	   	$dumpvars(0, arduino_digital_port_control_tb.u_top.u_pinmux);
+	   	$dumpvars(0, arduino_digital_port_control_tb.u_top.u_uart_i2c_usb_spi);
 	   end
        `endif
 
-	initial begin
+       
 
-		$value$plusargs("risc_core_id=%d", d_risc_id);
+	initial begin
 
 		#200; // Wait for reset removal
 	        repeat (10) @(posedge clock);
 		$display("Monitor: Standalone User Risc Boot Test Started");
 
+		$value$plusargs("risc_core_id=%d", d_risc_id);
 		// Remove Wb Reset
 		wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
 
-	        repeat (2) @(posedge clock);
+	    repeat (2) @(posedge clock);
 		#1;
-		// Remove all the reset
-		$display("STATUS: Working with Both core Risc core 0 & 1 ");
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h31F);
+
+        // Remove WB and SPI Reset and CORE under Reset
+        wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F);
+
+		// QSPI SRAM:CS#2 Switch to QSPI Mode
+        wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h38});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0);
+
+        // Remove all the reset
+        if(d_risc_id == 0) begin
+             $display("STATUS: Working with Risc core 0");
+             wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
+        end else if(d_risc_id == 1) begin
+             $display("STATUS: Working with Risc core 1");
+             wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
+        end else if(d_risc_id == 2) begin
+             $display("STATUS: Working with Risc core 2");
+             wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F);
+        end else if(d_risc_id == 3) begin
+             $display("STATUS: Working with Risc core 3");
+             wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
+        end
+
+        repeat (100) @(posedge clock);  // wait for Processor Get Ready
 
 
-		// Repeat cycles of 1000 clock edges as needed to complete testbench
-		repeat (22) begin
-			repeat (1000) @(posedge clock);
-			// $display("+1000 cycles");
-		end
+        repeat (20000) @(posedge clock);  // wait for Processor Get Ready
+        flag = 1;
 
+      fork
+      begin
+          for (channel = 0; channel < 1; channel = channel+1) begin
+            // change the resistance on this channel from min to max:
+            for (level = 0; level < 255; level = level+1) begin
+                wait(u_ad5205.channel == channel && u_ad5205.position ==  level);
+                $display("Channel: %x and Position: %x",u_ad5205.channel,u_ad5205.position);
+            end
+            // change the resistance on this channel from min to max:
+            for (level = 0; level < 255; level = level+1) begin
+                wait((u_ad5205.channel == channel) && (u_ad5205.position ==  (255 -level)));
+                $display("Channel: %x and Position: %x",u_ad5205.channel,u_ad5205.position);
+            end
+          end
+          test_fail = 0;
+      end
+      begin
+         repeat (6000000) @(posedge clock);  // wait for Processor Get Ready
+         test_fail = 1;
+      end
+      join_any
 
-		$display("Monitor: Reading Back the expected value");
-		// User RISC core expect to write these value in global
-		// register, read back and decide on pass fail
-		// 0x30000018  = 0x11223344; 
-                // 0x3000001C  = 0x22334455; 
-                // 0x30000020  = 0x33445566; 
-                // 0x30000024  = 0x44556677; 
-                // 0x30000028 = 0x55667788; 
-                // 0x3000002C = 0x66778899; 
+      #100
 
-                test_fail = 0;
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h11223344);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h22334455);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h33445566);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32'h44556677);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32'h55667788);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32'h66778899);
-
-
-	   
-	    	$display("###################################################");
-          	if(test_fail == 0) begin
-		   `ifdef GL
-	    	       $display("Monitor: Standalone User Risc Boot (GL) Passed");
-		   `else
-		       $display("Monitor: Standalone User Risc Boot (RTL) Passed");
-		   `endif
-	        end else begin
-		    `ifdef GL
-	    	        $display("Monitor: Standalone User Risc Boot (GL) Failed");
-		    `else
-		        $display("Monitor: Standalone User Risc Boot (RTL) Failed");
-		    `endif
-		 end
-	    	$display("###################################################");
+	  $display("###################################################");
+      if(test_fail == 0) begin
+	    `ifdef GL
+	           $display("Monitor: Ardunio Digital Port Control  (GL) Passed");
+	    `else
+	       $display("Monitor: Ardunio Digital Port Control (RTL) Passed");
+	    `endif
+	  end else begin
+	  `ifdef GL
+	      $display("Monitor: Ardunio Digital Port Control (GL) Failed");
+	  `else
+	      $display("Monitor: Ardunio Digital Port Control (RTL) Failed");
+	  `endif
+	  end
+	    $display("###################################################");
+      #100
 	    $finish;
 	end
 
@@ -227,6 +292,26 @@
 
 );
 
+//-------------------------------------------------------------------------------------
+//  Integrate the Serial SPI to ad5204/5206 (4-/6-Channel Digital Potentiometers)
+//  https://www.analog.com/media/en/technical-documentation/data-sheets/ad5204_5206.pdf
+//  -----------------------------------------------------------------------------------
+   wire sspi_sck = io_out[16];
+   wire sspi_sdi = io_out[15];
+   wire sspi_ssn = io_out[13];
+
+   wire [2:0]      p_channel; // potentiometer channel
+   wire [7:0]      p_position; // potentiometer position
+
+   bfm_ad5205 u_ad5205(
+              .sck      (sspi_sck    ),
+              .sdi      (sspi_sdi    ),
+              .ssn      (sspi_ssn    ),
+
+              .channel  (p_channel   ),
+              .position (p_position  )
+             );
+
 `ifndef GL // Drive Power for Hold Fix Buf
     // All standard cell need power hook-up for functionality work
     initial begin
@@ -257,7 +342,7 @@
    assign io_in[32] = flash_io3;
 
    // Quard flash
-     s25fl256s #(.mem_file_name("user_mcore.hex"),
+     s25fl256s #(.mem_file_name("arduino_digital_port_control.ino.hex"),
 	         .otp_file_name("none"),
                  .TimingModel("S25FL512SAGMFI010_F_30pF")) 
 		 u_spi_flash_256mb (
@@ -273,6 +358,21 @@
 
        );
 
+   wire spiram_csb = io_out[27];
+
+   is62wvs1288 #(.mem_file_name("none"))
+	u_sram (
+         // Data Inputs/Outputs
+           .io0     (flash_io0),
+           .io1     (flash_io1),
+           // Controls
+           .clk    (flash_clk),
+           .csb    (spiram_csb),
+           .io2    (flash_io2),
+           .io3    (flash_io3)
+    );
+
+//-------------------------------------
 
 
 
diff --git a/verilog/dv/arduino_hello_world/Makefile b/verilog/dv/arduino_hello_world/Makefile
index 3eed1a1..497a39e 100644
--- a/verilog/dv/arduino_hello_world/Makefile
+++ b/verilog/dv/arduino_hello_world/Makefile
@@ -52,6 +52,7 @@
 vvp:  ${PATTERN:=.vvp}
 
 %.vvp: %_tb.v
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${PATTERN}.ino.cpp -o ${PATTERN}.ino.cpp.o
 	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/Print.cpp -o Print.cpp.o
 	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WMath.cpp -o WMath.cpp.o
 	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WString.cpp -o WString.cpp.o
diff --git a/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v b/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v
index 051b224..344e480 100644
--- a/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v
+++ b/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v
@@ -18,30 +18,23 @@
 ////                                                              ////
 ////  Standalone User validation Test bench                       ////
 ////                                                              ////
-////  This file is part of the YIFive cores project               ////
-////  https://github.com/dineshannayya/yifive_r0.git              ////
-////  http://www.opencores.org/cores/yifive/                      ////
+////  This file is part of the riscdunio cores project            ////
+////  https://github.com/dineshannayya/riscdunio.git              ////
 ////                                                              ////
 ////  Description                                                 ////
 ////   This is a standalone test bench to validate the            ////
 ////   Digital core.                                              ////
-////   1. User Risc core is booted using  compiled code of        ////
-////      user_risc_boot.c                                        ////
-////   2. User Risc core uses Serial Flash and SDRAM to boot      ////
-////   3. After successful boot, Risc core will  write signature  ////
-////      in to  user register from 0x1003_0058 to 0x1003_006C    ////
-////   4. Through the External Wishbone Interface we read back    ////
-////       from 0x3003_0058 to 0x3003_006C                        ////
-////       and validate the user register to declared pass fail   ////
+////   This test bench to valid Arduino example:                  ////
+////                                                              ////
 ////                                                              ////
 ////  To Do:                                                      ////
 ////    nothing                                                   ////
 ////                                                              ////
 ////  Author(s):                                                  ////
-////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////      - Dinesh Annayya, dinesh.annayya@gmail.com              ////
 ////                                                              ////
 ////  Revision :                                                  ////
-////    0.1 - 16th Feb 2021, Dinesh A                             ////
+////    0.1 - 29th July 2022, Dinesh A                            ////
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
@@ -209,16 +202,16 @@
                 // Remove all the reset
                 if(d_risc_id == 0) begin
                      $display("STATUS: Working with Risc core 0");
-                     wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
+                     wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
                 end else if(d_risc_id == 1) begin
                      $display("STATUS: Working with Risc core 1");
-                     wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
+                     wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
                 end else if(d_risc_id == 2) begin
                      $display("STATUS: Working with Risc core 2");
-                     wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h41F);
+                     wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F);
                 end else if(d_risc_id == 3) begin
                      $display("STATUS: Working with Risc core 3");
-                     wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h81F);
+                     wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
                 end
 
                 repeat (100) @(posedge clock);  // wait for Processor Get Ready
diff --git a/verilog/dv/arduino_i2c_scaner/Makefile b/verilog/dv/arduino_i2c_scaner/Makefile
new file mode 100644
index 0000000..e6d5947
--- /dev/null
+++ b/verilog/dv/arduino_i2c_scaner/Makefile
@@ -0,0 +1,142 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+ 
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+DESIGNS?=../../..
+TOOLS?=/opt/riscv32i/
+
+export USER_PROJECT_VERILOG ?=  $(DESIGNS)/verilog
+export RISCDUINO_BOARD ?=  $(USER_PROJECT_VERILOG)/dv/common/riscduino_board/custom_board/riscduino
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+GCC_PREFIX?=riscv32-unknown-elf
+
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+RISC_CORE?=0
+
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
+.SUFFIXES:
+
+PATTERN = arduino_i2c_scaner
+
+all:  ${PATTERN:=.vcd}
+
+
+vvp:  ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard -I${RISCDUINO_BOARD}/libraries/Wire ${PATTERN}.ino.cpp -o ${PATTERN}.ino.cpp.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard -I${RISCDUINO_BOARD}/libraries/Wire -I${RISCDUINO_BOARD}/libraries/Wire/utility ${RISCDUINO_BOARD}/libraries/Wire/Wire.cpp -o Wire.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard -I${RISCDUINO_BOARD}/libraries/Wire -I${RISCDUINO_BOARD}/libraries/Wire/utility ${RISCDUINO_BOARD}/libraries/Wire/utility/twi.c -o twi.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/Print.cpp -o Print.cpp.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WMath.cpp -o WMath.cpp.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WString.cpp -o WString.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WInterrupts.c -o WInterrupts.c.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/fe300prci/fe300prci_driver.c -o fe300prci_driver.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/abi.cpp -o abi.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/plic/plic_driver.c -o plic_driver.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/UARTClass.cpp -o UARTClass.cpp.o
+	${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/entry.S -o entry.S.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/hooks.c -o hooks.c.o
+	${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/init.S -o init.S.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/itoa.c -o itoa.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/main.cpp -o main.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/malloc.c -o malloc.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/new.cpp -o new.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/sbrk.c -o sbrk.c.o
+	${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/start.S -o start.S.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring.c -o wiring.c.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_analog.c -o wiring_analog.c.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_digital.c -o wiring_digital.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_pulse.cpp -o wiring_pulse.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_shift.c -o wiring_shift.c.o
+	${GCC_PREFIX}-ar rcs core.a Print.cpp.o
+	${GCC_PREFIX}-ar rcs core.a UARTClass.cpp.o
+	${GCC_PREFIX}-ar rcs core.a WInterrupts.c.o
+	${GCC_PREFIX}-ar rcs core.a WMath.cpp.o
+	${GCC_PREFIX}-ar rcs core.a WString.cpp.o
+	${GCC_PREFIX}-ar rcs core.a abi.cpp.o
+	${GCC_PREFIX}-ar rcs core.a fe300prci_driver.c.o
+	${GCC_PREFIX}-ar rcs core.a plic_driver.c.o
+	${GCC_PREFIX}-ar rcs core.a entry.S.o
+	${GCC_PREFIX}-ar rcs core.a hooks.c.o
+	${GCC_PREFIX}-ar rcs core.a init.S.o
+	${GCC_PREFIX}-ar rcs core.a itoa.c.o
+	${GCC_PREFIX}-ar rcs core.a main.cpp.o
+	${GCC_PREFIX}-ar rcs core.a malloc.c.o
+	${GCC_PREFIX}-ar rcs core.a new.cpp.o
+	${GCC_PREFIX}-ar rcs core.a sbrk.c.o
+	${GCC_PREFIX}-ar rcs core.a start.S.o
+	${GCC_PREFIX}-ar rcs core.a wiring.c.o
+	${GCC_PREFIX}-ar rcs core.a wiring_analog.c.o
+	${GCC_PREFIX}-ar rcs core.a wiring_digital.c.o
+	${GCC_PREFIX}-ar rcs core.a wiring_pulse.cpp.o
+	${GCC_PREFIX}-ar rcs core.a wiring_shift.c.o
+	${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o  Wire.cpp.o twi.c.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf
+	${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.ino.elf ${PATTERN}.ino.bin
+	${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.ino.elf ${PATTERN}.ino.hex
+	${GCC_PREFIX}-objdump -D  ${PATTERN}.ino.elf >   ${PATTERN}.ino.dump
+	rm *.o *.a
+ifeq ($(SIM),RTL)
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
+	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
+	$< -o $@ 
+   endif
+else  
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+   endif
+endif
+
+%.vcd: %.vvp
+	vvp $< +risc_core_id=$(RISC_CORE)
+
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump *.a *.o
+
+.PHONY: clean hex all
diff --git a/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner.ino b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner.ino
new file mode 100644
index 0000000..295edf7
--- /dev/null
+++ b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner.ino
@@ -0,0 +1,75 @@
+// --------------------------------------
+// i2c_scanner
+//
+// Version 1
+//    This program (or code that looks like it)
+//    can be found in many places.
+//    For example on the Arduino.cc forum.
+//    The original author is not known.
+// Version 2, Juni 2012, Using Arduino 1.0.1
+//     Adapted to be as simple as possible by Arduino.cc user Krodal
+// Version 3, Feb 26  2013
+//    V3 by louarnold
+// Version 4, March 3, 2013, Using Arduino 1.0.3
+//    by Arduino.cc user Krodal.
+//    Changes by louarnold removed.
+//    Scanning addresses changed from 0...127 to 1...119,
+//    according to the i2c scanner by Nick Gammon
+//    https://www.gammon.com.au/forum/?id=10896
+// Version 5, March 28, 2013
+//    As version 4, but address scans now to 127.
+//    A sensor seems to use address 120.
+// Version 6, November 27, 2015.
+//    Added waiting for the Leonardo serial communication.
+//
+//
+// This sketch tests the standard 7-bit addresses
+// Devices with higher bit address might not be seen properly.
+//
+
+#include <Wire.h>
+
+void setup() {
+  Wire.begin();
+
+  Serial.begin(9600);
+  while (!Serial); // Leonardo: wait for Serial Monitor
+  Serial.println("\nI2C Scanner");
+}
+
+void loop() {
+  int nDevices = 0;
+
+  Serial.println("Scanning...");
+
+  for (byte address = 1; address < 127; ++address) {
+    // The i2c_scanner uses the return value of
+    // the Wire.endTransmission to see if
+    // a device did acknowledge to the address.
+    Wire.beginTransmission(address);
+    byte error = Wire.endTransmission();
+
+    if (error == 0) {
+      Serial.print("I2C device found at address 0x");
+      if (address < 16) {
+        Serial.print("0");
+      }
+      Serial.print(address, HEX);
+      Serial.println("  !");
+
+      ++nDevices;
+    } else if (error == 4) {
+      Serial.print("Unknown error at address 0x");
+      if (address < 16) {
+        Serial.print("0");
+      }
+      Serial.println(address, HEX);
+    }
+  }
+  if (nDevices == 0) {
+    Serial.println("No I2C devices found\n");
+  } else {
+    Serial.println("done\n");
+  }
+  delay(5000); // Wait 5 seconds for next scan
+}
diff --git a/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner.ino.cpp b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner.ino.cpp
new file mode 100644
index 0000000..dc656cb
--- /dev/null
+++ b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner.ino.cpp
@@ -0,0 +1,79 @@
+#include <Arduino.h>
+// --------------------------------------
+// i2c_scanner
+//
+// Version 1
+//    This program (or code that looks like it)
+//    can be found in many places.
+//    For example on the Arduino.cc forum.
+//    The original author is not known.
+// Version 2, Juni 2012, Using Arduino 1.0.1
+//     Adapted to be as simple as possible by Arduino.cc user Krodal
+// Version 3, Feb 26  2013
+//    V3 by louarnold
+// Version 4, March 3, 2013, Using Arduino 1.0.3
+//    by Arduino.cc user Krodal.
+//    Changes by louarnold removed.
+//    Scanning addresses changed from 0...127 to 1...119,
+//    according to the i2c scanner by Nick Gammon
+//    https://www.gammon.com.au/forum/?id=10896
+// Version 5, March 28, 2013
+//    As version 4, but address scans now to 127.
+//    A sensor seems to use address 120.
+// Version 6, November 27, 2015.
+//    Added waiting for the Leonardo serial communication.
+//
+//
+// This sketch tests the standard 7-bit addresses
+// Devices with higher bit address might not be seen properly.
+//
+
+#include <Wire.h>
+
+void setup();
+void loop();
+void setup() {
+  Wire.begin();
+
+  Serial.begin(1152000);
+  while (!Serial); // Leonardo: wait for Serial Monitor
+  Serial.println("\nI2C Scanner");
+}
+
+void loop() {
+  int nDevices = 0;
+
+  Serial.println("Scanning...");
+
+  for (byte address = 1; address < 127; ++address) {
+    // The i2c_scanner uses the return value of
+    // the Wire.endTransmission to see if
+    // a device did acknowledge to the address.
+    Wire.beginTransmission(address);
+    byte error = Wire.endTransmission();
+
+    if (error == 0) {
+      Serial.print("I2C device found at address 0x");
+      if (address < 16) {
+        Serial.print("0");
+      }
+      Serial.print(address, HEX);
+      Serial.println("  !");
+
+      ++nDevices;
+    } else if (error == 4) {
+      Serial.print("Unknown error at address 0x");
+      if (address < 16) {
+        Serial.print("0");
+      }
+      Serial.println(address, HEX);
+    }
+  }
+  if (nDevices == 0) {
+    Serial.println("No I2C devices found\n");
+  } else {
+    Serial.println("done\n");
+  }
+  delay(5000); // Wait 5 seconds for next scan
+}
+
diff --git a/verilog/dv/user_mcore/user_mcore_tb.v b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v
similarity index 61%
copy from verilog/dv/user_mcore/user_mcore_tb.v
copy to verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v
index b43dcba..98948a9 100644
--- a/verilog/dv/user_mcore/user_mcore_tb.v
+++ b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v
@@ -18,20 +18,23 @@
 ////                                                              ////
 ////  Standalone User validation Test bench                       ////
 ////                                                              ////
-////  This file is part of the riscduino cores project            ////
+////  This file is part of the riscdunio cores project            ////
+////  https://github.com/dineshannayya/riscdunio.git              ////
 ////                                                              ////
 ////  Description                                                 ////
 ////   This is a standalone test bench to validate the            ////
-////   Digital core multi-core behaviour.                         ////
+////   Digital core.                                              ////
+////   This test bench to valid Arduino example:                  ////
+////     <example><Wire><i2c_scanner>                             ////
 ////                                                              ////
 ////  To Do:                                                      ////
 ////    nothing                                                   ////
 ////                                                              ////
 ////  Author(s):                                                  ////
-////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////      - Dinesh Annayya, dinesh.annayya@gmail.com              ////
 ////                                                              ////
 ////  Revision :                                                  ////
-////    0.1 - 16th Feb 2021, Dinesh A                             ////
+////    0.1 - 29th July 2022, Dinesh A                            ////
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
@@ -65,7 +68,10 @@
 `timescale 1 ns / 1 ns
 
 `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
-module user_mcore_tb;
+`include "uart_agent.v"
+`include "i2c_slave_model.v"
+
+module arduino_i2c_scaner_tb;
 	reg clock;
 	reg wb_rst_i;
 	reg power1, power2;
@@ -92,92 +98,182 @@
 	wire [7:0] mprj_io_0;
 	reg         test_fail;
 	reg [31:0] read_data;
+    //----------------------------------
+    // Uart Configuration
+    // ---------------------------------
+    reg [1:0]      uart_data_bit        ;
+    reg	       uart_stop_bits       ; // 0: 1 stop bit; 1: 2 stop bit;
+    reg	       uart_stick_parity    ; // 1: force even parity
+    reg	       uart_parity_en       ; // parity enable
+    reg	       uart_even_odd_parity ; // 0: odd parity; 1: even parity
+    
+    reg [7:0]      uart_data            ;
+    reg [15:0]     uart_divisor         ;	// divided by n * 16
+    reg [15:0]     uart_timeout         ;// wait time limit
+    
+    reg [15:0]     uart_rx_nu           ;
+    reg [15:0]     uart_tx_nu           ;
+    reg [7:0]      uart_write_data [0:39];
+    reg 	       uart_fifo_enable     ;	// fifo mode disable
+	reg            flag                 ;
+    reg            compare_start        ; // User Need to make sure that compare start match with RiscV core completing initial booting
+
+	reg [31:0]     check_sum            ;
+        
 	integer    d_risc_id;
 
+         integer i,j;
 
 
-	// External clock is used by default.  Make this artificially fast for the
-	// simulation.  Normally this would be a slow clock and the digital PLL
-	// would be the fast clock.
 
-	always #12.5 clock <= (clock === 1'b0);
+
+	// 50Mhz CLock
+	always #10 clock <= (clock === 1'b0);
 
 	initial begin
 		clock = 0;
-                wbd_ext_cyc_i ='h0;  // strobe/request
-                wbd_ext_stb_i ='h0;  // strobe/request
-                wbd_ext_adr_i ='h0;  // address
-                wbd_ext_we_i  ='h0;  // write
-                wbd_ext_dat_i ='h0;  // data output
-                wbd_ext_sel_i ='h0;  // byte enable
+	    flag  = 0;
+        compare_start = 0;
+        wbd_ext_cyc_i ='h0;  // strobe/request
+        wbd_ext_stb_i ='h0;  // strobe/request
+        wbd_ext_adr_i ='h0;  // address
+        wbd_ext_we_i  ='h0;  // write
+        wbd_ext_dat_i ='h0;  // data output
+        wbd_ext_sel_i ='h0;  // byte enable
 	end
 
 	`ifdef WFDUMP
 	   initial begin
 	   	$dumpfile("simx.vcd");
-	   	$dumpvars(1, user_mcore_tb);
-	   	$dumpvars(1, user_mcore_tb.u_top);
-	   	$dumpvars(0, user_mcore_tb.u_top.u_riscv_top);
+	   	$dumpvars(3, arduino_i2c_scaner_tb);
+	   	$dumpvars(0, arduino_i2c_scaner_tb.u_top.u_riscv_top.i_core_top_0);
+	   	$dumpvars(0, arduino_i2c_scaner_tb.u_top.u_riscv_top.u_connect);
+	   	$dumpvars(0, arduino_i2c_scaner_tb.u_top.u_riscv_top.u_intf);
+	   	$dumpvars(0, arduino_i2c_scaner_tb.u_top.u_uart_i2c_usb_spi.u_uart0_core);
+	   	$dumpvars(0, arduino_i2c_scaner_tb.u_top.u_uart_i2c_usb_spi.u_i2cm);
 	   end
        `endif
 
+       /*************************************************************************
+       * This is Baud Rate to clock divider conversion for Test Bench
+       * Note: DUT uses 16x baud clock, where are test bench uses directly
+       * baud clock, Due to 16x Baud clock requirement at RTL, there will be
+       * some resolution loss, we expect at lower baud rate this resolution
+       * loss will be less. For Quick simulation perpose higher baud rate used
+       * *************************************************************************/
+       task tb_set_uart_baud;
+       input [31:0] ref_clk;
+       input [31:0] baud_rate;
+       output [31:0] baud_div;
+       reg   [31:0] baud_div;
+       begin
+	  // for 230400 Baud = (50Mhz/230400) = 216.7
+	  baud_div = ref_clk/baud_rate; // Get the Bit Baud rate
+	  // Baud 16x = 216/16 = 13
+          baud_div = baud_div/16; // To find the RTL baud 16x div value to find similar resolution loss in test bench
+	  // Test bench baud clock , 16x of above value
+	  // 13 * 16 = 208,  
+	  // (Note if you see original value was 216, now it's 208 )
+          baud_div = baud_div * 16;
+	  // Test bench half cycle counter to toggle it 
+	  // 208/2 = 104
+           baud_div = baud_div/2;
+	  //As counter run's from 0 , substract from 1
+	   baud_div = baud_div-1;
+       end
+       endtask
+       
+
 	initial begin
+        uart_data_bit           = 2'b11;
+        uart_stop_bits          = 0; // 0: 1 stop bit; 1: 2 stop bit;
+        uart_stick_parity       = 0; // 1: force even parity
+        uart_parity_en          = 0; // parity enable
+        uart_even_odd_parity    = 1; // 0: odd parity; 1: even parity
+	    tb_set_uart_baud(50000000,1152000,uart_divisor);// 50Mhz Ref clock, Baud Rate: 230400
+        uart_timeout            = 2000;// wait time limit
+        uart_fifo_enable        = 0;	// fifo mode disable
 
 		$value$plusargs("risc_core_id=%d", d_risc_id);
 
 		#200; // Wait for reset removal
-	        repeat (10) @(posedge clock);
+	    repeat (10) @(posedge clock);
 		$display("Monitor: Standalone User Risc Boot Test Started");
 
 		// Remove Wb Reset
 		wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
 
-	        repeat (2) @(posedge clock);
+	    repeat (2) @(posedge clock);
 		#1;
-		// Remove all the reset
-		$display("STATUS: Working with Both core Risc core 0 & 1 ");
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h31F);
+        // Remove all the reset
+        if(d_risc_id == 0) begin
+             $display("STATUS: Working with Risc core 0");
+             wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
+        end else if(d_risc_id == 1) begin
+             $display("STATUS: Working with Risc core 1");
+             wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
+        end else if(d_risc_id == 2) begin
+             $display("STATUS: Working with Risc core 2");
+             wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h41F);
+        end else if(d_risc_id == 3) begin
+             $display("STATUS: Working with Risc core 3");
+             wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h81F);
+        end
 
+        repeat (100) @(posedge clock);  // wait for Processor Get Ready
 
-		// Repeat cycles of 1000 clock edges as needed to complete testbench
-		repeat (22) begin
-			repeat (1000) @(posedge clock);
-			// $display("+1000 cycles");
-		end
+	    tb_uart.debug_mode = 0; // disable debug display
+        tb_uart.uart_init;
+        tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, 
+                                       uart_stick_parity, uart_timeout, uart_divisor);
 
+        repeat (45000) @(posedge clock);  // wait for Processor Get Ready
+	    flag  = 0;
+		check_sum = 0;
+        compare_start = 1;
+        
+        fork
+           begin
+              while(flag == 0)
+              begin
+                 tb_uart.read_char(read_data,flag);
+		         if(flag == 0)  begin
+		            $write ("%c",read_data);
+		            check_sum = check_sum+read_data;
+		         end
+              end
+           end
+           begin
+              repeat (200000) @(posedge clock);  // wait for Processor Get Ready
+           end
+           join_any
+        
+           #100
+           tb_uart.report_status(uart_rx_nu, uart_tx_nu);
+        
+           test_fail = 0;
 
-		$display("Monitor: Reading Back the expected value");
-		// User RISC core expect to write these value in global
-		// register, read back and decide on pass fail
-		// 0x30000018  = 0x11223344; 
-                // 0x3000001C  = 0x22334455; 
-                // 0x30000020  = 0x33445566; 
-                // 0x30000024  = 0x44556677; 
-                // 0x30000028 = 0x55667788; 
-                // 0x3000002C = 0x66778899; 
-
-                test_fail = 0;
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h11223344);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h22334455);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h33445566);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32'h44556677);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32'h55667788);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32'h66778899);
-
+		   $display("Total Rx Char: %d Check Sum : %x ",uart_rx_nu, check_sum);
+           // Check 
+           // if all the 102 byte received
+           // if no error 
+           if(uart_rx_nu != 102) test_fail = 1;
+           if(check_sum != 32'h1fab) test_fail = 1;
+           if(tb_uart.err_cnt != 0) test_fail = 1;
 
 	   
 	    	$display("###################################################");
           	if(test_fail == 0) begin
 		   `ifdef GL
-	    	       $display("Monitor: Standalone User Risc Boot (GL) Passed");
+	    	       $display("Monitor: Standalone String (GL) Passed");
 		   `else
-		       $display("Monitor: Standalone User Risc Boot (RTL) Passed");
+		       $display("Monitor: Standalone String (RTL) Passed");
 		   `endif
 	        end else begin
 		    `ifdef GL
-	    	        $display("Monitor: Standalone User Risc Boot (GL) Failed");
+	    	        $display("Monitor: Standalone String (GL) Failed");
 		    `else
-		        $display("Monitor: Standalone User Risc Boot (RTL) Failed");
+		        $display("Monitor: Standalone String (RTL) Failed");
 		    `endif
 		 end
 	    	$display("###################################################");
@@ -227,6 +323,25 @@
 
 );
 
+//---------------------------
+// I2C
+// --------------------------
+tri scl,sda;
+
+assign sda  =  (io_oeb[22] == 1'b0) ? io_out[22] : 1'bz;
+assign scl   = (io_oeb[23] == 1'b0) ? io_out[23]: 1'bz;
+assign io_in[22]  =  sda;
+assign io_in[23]  =  scl;
+
+pullup p1(scl); // pullup scl line
+pullup p2(sda); // pullup sda line
+
+ 
+i2c_slave_model  #(.I2C_ADR(7'h4)) u_i2c_slave (
+	.scl   (scl), 
+	.sda   (sda)
+       );
+
 `ifndef GL // Drive Power for Hold Fix Buf
     // All standard cell need power hook-up for functionality work
     initial begin
@@ -257,8 +372,8 @@
    assign io_in[32] = flash_io3;
 
    // Quard flash
-     s25fl256s #(.mem_file_name("user_mcore.hex"),
-	         .otp_file_name("none"),
+     s25fl256s #(.mem_file_name("arduino_i2c_scaner.ino.hex"),
+	             .otp_file_name("none"),
                  .TimingModel("S25FL512SAGMFI010_F_30pF")) 
 		 u_spi_flash_256mb (
            // Data Inputs/Outputs
@@ -274,6 +389,19 @@
        );
 
 
+//---------------------------
+//  UART Agent integration
+// --------------------------
+wire uart_txd,uart_rxd;
+
+assign uart_txd   = io_out[2];
+assign io_in[1]  = uart_rxd ;
+ 
+uart_agent tb_uart(
+	.mclk                (clock              ),
+	.txd                 (uart_rxd           ),
+	.rxd                 (uart_txd           )
+	);
 
 
 task wb_user_core_write;
diff --git a/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v b/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v
index f0cf862..6ad86a1 100644
--- a/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v
+++ b/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v
@@ -18,30 +18,24 @@
 ////                                                              ////
 ////  Standalone User validation Test bench                       ////
 ////                                                              ////
-////  This file is part of the YIFive cores project               ////
-////  https://github.com/dineshannayya/yifive_r0.git              ////
-////  http://www.opencores.org/cores/yifive/                      ////
+////  This file is part of the riscdunio cores project            ////
+////  https://github.com/dineshannayya/riscdunio.git              ////
 ////                                                              ////
 ////  Description                                                 ////
 ////   This is a standalone test bench to validate the            ////
 ////   Digital core.                                              ////
-////   1. User Risc core is booted using  compiled code of        ////
-////      user_risc_boot.c                                        ////
-////   2. User Risc core uses Serial Flash and SDRAM to boot      ////
-////   3. After successful boot, Risc core will  write signature  ////
-////      in to  user register from 0x1003_0058 to 0x1003_006C    ////
-////   4. Through the External Wishbone Interface we read back    ////
-////       from 0x3003_0058 to 0x3003_006C                        ////
-////       and validate the user register to declared pass fail   ////
+////   This test bench to valid Arduino example:                  ////
+////     <example><04.Communication><MultiSerial>                 ////
+////                                                              ////
 ////                                                              ////
 ////  To Do:                                                      ////
 ////    nothing                                                   ////
 ////                                                              ////
 ////  Author(s):                                                  ////
-////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////      - Dinesh Annayya, dinesh.annayya@gmail.com              ////
 ////                                                              ////
 ////  Revision :                                                  ////
-////    0.1 - 16th Feb 2021, Dinesh A                             ////
+////    0.1 - 29th July 2022, Dinesh A                            ////
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
@@ -213,16 +207,16 @@
                 // Remove all the reset
                 if(d_risc_id == 0) begin
                      $display("STATUS: Working with Risc core 0");
-                     wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
+                     wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
                 end else if(d_risc_id == 1) begin
                      $display("STATUS: Working with Risc core 1");
-                     wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
+                     wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
                 end else if(d_risc_id == 2) begin
                      $display("STATUS: Working with Risc core 2");
-                     wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h41F);
+                     wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F);
                 end else if(d_risc_id == 3) begin
                      $display("STATUS: Working with Risc core 3");
-                     wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h81F);
+                     wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
                 end
 
                 repeat (100) @(posedge clock);  // wait for Processor Get Ready
diff --git a/verilog/dv/arduino_risc_boot/arduino_risc_boot.ino.cpp b/verilog/dv/arduino_risc_boot/arduino_risc_boot.ino.cpp
index ca5efa0..c663a26 100644
--- a/verilog/dv/arduino_risc_boot/arduino_risc_boot.ino.cpp
+++ b/verilog/dv/arduino_risc_boot/arduino_risc_boot.ino.cpp
@@ -1,34 +1,18 @@
 #include <Arduino.h>
 #define uint32_t  long
 
-#define reg_mprj_globl_reg0  (*(volatile uint32_t*)0x10020000)
-#define reg_mprj_globl_reg1  (*(volatile uint32_t*)0x10020004)
-#define reg_mprj_globl_reg2  (*(volatile uint32_t*)0x10020008)
-#define reg_mprj_globl_reg3  (*(volatile uint32_t*)0x1002000C)
-#define reg_mprj_globl_reg4  (*(volatile uint32_t*)0x10020010)
-#define reg_mprj_globl_reg5  (*(volatile uint32_t*)0x10020014)
-#define reg_mprj_globl_reg6  (*(volatile uint32_t*)0x10020018)
-#define reg_mprj_globl_reg7  (*(volatile uint32_t*)0x1002001C)
-#define reg_mprj_globl_reg8  (*(volatile uint32_t*)0x10020020)
-#define reg_mprj_globl_reg9  (*(volatile uint32_t*)0x10020024)
-#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x10020028)
-#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x1002002C)
-#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x10020030)
-#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x10020034)
-#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x10020038)
-#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x1002003C)
-#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x10020040)
-#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x10020044)
-#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x10020048)
-#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x1002004C)
-#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x10020050)
-#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x10020054)
-#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x10020058)
-#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x1002005C)
-#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x10020060)
-#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x10020064)
-#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x10020068)
-#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x1002006C)
+#define reg_mprj_globl_reg0   (*(volatile uint32_t*)0x10020000) // Chip ID
+#define reg_mprj_globl_reg1   (*(volatile uint32_t*)0x10020004) // Global Config-0
+#define reg_mprj_globl_reg2   (*(volatile uint32_t*)0x10020008) // Global Config-1
+#define reg_mprj_globl_reg3   (*(volatile uint32_t*)0x1002000C) // Global Interrupt Mask
+#define reg_mprj_globl_reg4   (*(volatile uint32_t*)0x10020010) // Global Interrupt
+#define reg_mprj_globl_reg5   (*(volatile uint32_t*)0x10020014) // Multi functional sel
+#define reg_mprj_globl_soft0  (*(volatile uint32_t*)0x10020018) // Sof Register-0
+#define reg_mprj_globl_soft1  (*(volatile uint32_t*)0x1002001C) // Sof Register-1
+#define reg_mprj_globl_soft2  (*(volatile uint32_t*)0x10020020) // Sof Register-2
+#define reg_mprj_globl_soft3  (*(volatile uint32_t*)0x10020024) // Sof Register-3
+#define reg_mprj_globl_soft4  (*(volatile uint32_t*)0x10020028) // Sof Register-4
+#define reg_mprj_globl_soft5  (*(volatile uint32_t*)0x1002002C) // Sof Register-5
 
 
 
@@ -36,12 +20,12 @@
 void loop();
 void setup() {
   // put your setup code here, to run once:
-    reg_mprj_globl_reg22  = 0x11223344; 
-    reg_mprj_globl_reg23  = 0x22334455; 
-    reg_mprj_globl_reg24  = 0x33445566; 
-    reg_mprj_globl_reg25  = 0x44556677; 
-    reg_mprj_globl_reg26 = 0x55667788; 
-    reg_mprj_globl_reg27 = 0x66778899; 
+    reg_mprj_globl_soft0  = 0x11223344; 
+    reg_mprj_globl_soft1  = 0x22334455; 
+    reg_mprj_globl_soft2  = 0x33445566; 
+    reg_mprj_globl_soft3  = 0x44556677; 
+    reg_mprj_globl_soft4  = 0x55667788; 
+    reg_mprj_globl_soft5  = 0x66778899; 
 
 }
 
diff --git a/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v b/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v
index c435c40..0349606 100644
--- a/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v
+++ b/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v
@@ -18,30 +18,22 @@
 ////                                                              ////
 ////  Standalone User validation Test bench                       ////
 ////                                                              ////
-////  This file is part of the YIFive cores project               ////
-////  https://github.com/dineshannayya/yifive_r0.git              ////
-////  http://www.opencores.org/cores/yifive/                      ////
+////  This file is part of the riscdunio cores project            ////
+////  https://github.com/dineshannayya/riscdunio.git              ////
 ////                                                              ////
 ////  Description                                                 ////
 ////   This is a standalone test bench to validate the            ////
 ////   Digital core.                                              ////
-////   1. User Risc core is booted using  compiled code of        ////
-////      user_risc_boot.c                                        ////
-////   2. User Risc core uses Serial Flash and SDRAM to boot      ////
-////   3. After successful boot, Risc core will  write signature  ////
-////      in to  user register from 0x1003_0058 to 0x1003_006C    ////
-////   4. Through the External Wishbone Interface we read back    ////
-////       from 0x3003_0058 to 0x3003_006C                        ////
-////       and validate the user register to declared pass fail   ////
+////   This test bench to valid Arduino example:                  ////
 ////                                                              ////
 ////  To Do:                                                      ////
 ////    nothing                                                   ////
 ////                                                              ////
 ////  Author(s):                                                  ////
-////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////      - Dinesh Annayya, dinesh.annayya@gmail.com              ////
 ////                                                              ////
 ////  Revision :                                                  ////
-////    0.1 - 16th Feb 2021, Dinesh A                             ////
+////    0.1 - 29th July 2022, Dinesh A                            ////
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
@@ -145,10 +137,10 @@
 		// Remove all the reset
 		if(d_risc_id == 0) begin
 		     $display("STATUS: Working with Risc core 0");
-                     wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
+                     wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
 		end else if(d_risc_id == 1) begin
 		     $display("STATUS: Working with Risc core 1");
-                     wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
+                     wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
 		end
 
 
@@ -170,12 +162,12 @@
                 // 0x3000002C = 0x66778899; 
 
                 test_fail = 0;
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h11223344);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h22334455);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h33445566);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32'h44556677);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32'h55667788);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32'h66778899);
+		wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h11223344);
+		wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,32'h22334455);
+		wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,32'h33445566);
+		wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,read_data,32'h44556677);
+		wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,read_data,32'h55667788);
+		wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,read_data,32'h66778899);
 
 
 	   
diff --git a/verilog/dv/arduino_string/Makefile b/verilog/dv/arduino_string/Makefile
new file mode 100644
index 0000000..78fc16e
--- /dev/null
+++ b/verilog/dv/arduino_string/Makefile
@@ -0,0 +1,140 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+ 
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+DESIGNS?=../../..
+TOOLS?=/opt/riscv32i/
+
+export USER_PROJECT_VERILOG ?=  $(DESIGNS)/verilog
+export RISCDUINO_BOARD ?=  $(USER_PROJECT_VERILOG)/dv/common/riscduino_board/custom_board/riscduino
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+GCC_PREFIX?=riscv32-unknown-elf
+
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+RISC_CORE?=0
+
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
+.SUFFIXES:
+
+PATTERN = arduino_string
+
+all:  ${PATTERN:=.vcd}
+
+
+vvp:  ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${PATTERN}.ino.cpp -o ${PATTERN}.ino.cpp.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/Print.cpp -o Print.cpp.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WMath.cpp -o WMath.cpp.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WString.cpp -o WString.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WInterrupts.c -o WInterrupts.c.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/fe300prci/fe300prci_driver.c -o fe300prci_driver.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/abi.cpp -o abi.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/plic/plic_driver.c -o plic_driver.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/UARTClass.cpp -o UARTClass.cpp.o
+	${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/entry.S -o entry.S.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/hooks.c -o hooks.c.o
+	${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/init.S -o init.S.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/itoa.c -o itoa.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/main.cpp -o main.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/malloc.c -o malloc.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/new.cpp -o new.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/sbrk.c -o sbrk.c.o
+	${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/start.S -o start.S.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring.c -o wiring.c.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_analog.c -o wiring_analog.c.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_digital.c -o wiring_digital.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_pulse.cpp -o wiring_pulse.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_shift.c -o wiring_shift.c.o
+	${GCC_PREFIX}-ar rcs core.a Print.cpp.o
+	${GCC_PREFIX}-ar rcs core.a UARTClass.cpp.o
+	${GCC_PREFIX}-ar rcs core.a WInterrupts.c.o
+	${GCC_PREFIX}-ar rcs core.a WMath.cpp.o
+	${GCC_PREFIX}-ar rcs core.a WString.cpp.o
+	${GCC_PREFIX}-ar rcs core.a abi.cpp.o
+	${GCC_PREFIX}-ar rcs core.a fe300prci_driver.c.o
+	${GCC_PREFIX}-ar rcs core.a plic_driver.c.o
+	${GCC_PREFIX}-ar rcs core.a entry.S.o
+	${GCC_PREFIX}-ar rcs core.a hooks.c.o
+	${GCC_PREFIX}-ar rcs core.a init.S.o
+	${GCC_PREFIX}-ar rcs core.a itoa.c.o
+	${GCC_PREFIX}-ar rcs core.a main.cpp.o
+	${GCC_PREFIX}-ar rcs core.a malloc.c.o
+	${GCC_PREFIX}-ar rcs core.a new.cpp.o
+	${GCC_PREFIX}-ar rcs core.a sbrk.c.o
+	${GCC_PREFIX}-ar rcs core.a start.S.o
+	${GCC_PREFIX}-ar rcs core.a wiring.c.o
+	${GCC_PREFIX}-ar rcs core.a wiring_analog.c.o
+	${GCC_PREFIX}-ar rcs core.a wiring_digital.c.o
+	${GCC_PREFIX}-ar rcs core.a wiring_pulse.cpp.o
+	${GCC_PREFIX}-ar rcs core.a wiring_shift.c.o
+	${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf
+	${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.ino.elf ${PATTERN}.ino.bin
+	${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.ino.elf ${PATTERN}.ino.hex
+	${GCC_PREFIX}-objdump -D  ${PATTERN}.ino.elf >   ${PATTERN}.ino.dump
+	rm *.o *.a
+ifeq ($(SIM),RTL)
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
+	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
+	$< -o $@ 
+   endif
+else  
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+   endif
+endif
+
+%.vcd: %.vvp
+	vvp $< +risc_core_id=$(RISC_CORE)
+
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump *.a *.o
+
+.PHONY: clean hex all
diff --git a/verilog/dv/arduino_string/arduino_string.ino b/verilog/dv/arduino_string/arduino_string.ino
new file mode 100644
index 0000000..3a4ea08
--- /dev/null
+++ b/verilog/dv/arduino_string/arduino_string.ino
@@ -0,0 +1,28 @@
+void setup() {
+  String my_str = "This is my string.";
+  
+  Serial.begin(9600);
+  
+  // (1) print the string
+  Serial.println(my_str);
+  
+  // (2) change the string to upper-case
+  my_str.toUpperCase();
+  Serial.println(my_str);
+  
+  // (3) overwrite the string
+  my_str = "My new string.";
+  Serial.println(my_str);
+  
+  // (4) replace a word in the string
+  my_str.replace("string", "Arduino sketch");
+  Serial.println(my_str);
+  
+  // (5) get the length of the string
+  Serial.print("String length is: ");
+  Serial.println(my_str.length());
+}
+
+void loop() {
+}
+
diff --git a/verilog/dv/arduino_string/arduino_string.ino.cpp b/verilog/dv/arduino_string/arduino_string.ino.cpp
new file mode 100644
index 0000000..6cdd523
--- /dev/null
+++ b/verilog/dv/arduino_string/arduino_string.ino.cpp
@@ -0,0 +1,32 @@
+#include <Arduino.h>
+void setup();
+void loop();
+void setup() {
+  String my_str = "This is my string.";
+  
+  Serial.begin(1152000);
+  
+  // (1) print the string
+  Serial.println(my_str);
+  
+  // (2) change the string to upper-case
+  my_str.toUpperCase();
+  Serial.println(my_str);
+  
+  // (3) overwrite the string
+  my_str = "My new string.";
+  Serial.println(my_str);
+  
+  // (4) replace a word in the string
+  my_str.replace("string", "Arduino sketch");
+  Serial.println(my_str);
+  
+  // (5) get the length of the string
+  Serial.print("String length is: ");
+  Serial.println(my_str.length());
+}
+
+void loop() {
+}
+
+
diff --git a/verilog/dv/user_mcore/user_mcore_tb.v b/verilog/dv/arduino_string/arduino_string_tb.v
similarity index 63%
copy from verilog/dv/user_mcore/user_mcore_tb.v
copy to verilog/dv/arduino_string/arduino_string_tb.v
index b43dcba..1bd4b91 100644
--- a/verilog/dv/user_mcore/user_mcore_tb.v
+++ b/verilog/dv/arduino_string/arduino_string_tb.v
@@ -18,20 +18,23 @@
 ////                                                              ////
 ////  Standalone User validation Test bench                       ////
 ////                                                              ////
-////  This file is part of the riscduino cores project            ////
+////  This file is part of the riscdunio cores project            ////
+////  https://github.com/dineshannayya/riscdunio.git              ////
 ////                                                              ////
 ////  Description                                                 ////
 ////   This is a standalone test bench to validate the            ////
-////   Digital core multi-core behaviour.                         ////
+////   Digital core.                                              ////
+////   This test bench to valid Arduino example:                  ////
+////     <example><04.Communication><String>                      ////
 ////                                                              ////
 ////  To Do:                                                      ////
 ////    nothing                                                   ////
 ////                                                              ////
 ////  Author(s):                                                  ////
-////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////      - Dinesh Annayya, dinesh.annayya@gmail.com              ////
 ////                                                              ////
 ////  Revision :                                                  ////
-////    0.1 - 16th Feb 2021, Dinesh A                             ////
+////    0.1 - 29th July 2022, Dinesh A                            ////
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
@@ -65,7 +68,9 @@
 `timescale 1 ns / 1 ns
 
 `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
-module user_mcore_tb;
+`include "uart_agent.v"
+
+module arduino_string_tb;
 	reg clock;
 	reg wb_rst_i;
 	reg power1, power2;
@@ -92,92 +97,181 @@
 	wire [7:0] mprj_io_0;
 	reg         test_fail;
 	reg [31:0] read_data;
+    //----------------------------------
+    // Uart Configuration
+    // ---------------------------------
+    reg [1:0]      uart_data_bit        ;
+    reg	       uart_stop_bits       ; // 0: 1 stop bit; 1: 2 stop bit;
+    reg	       uart_stick_parity    ; // 1: force even parity
+    reg	       uart_parity_en       ; // parity enable
+    reg	       uart_even_odd_parity ; // 0: odd parity; 1: even parity
+    
+    reg [7:0]      uart_data            ;
+    reg [15:0]     uart_divisor         ;	// divided by n * 16
+    reg [15:0]     uart_timeout         ;// wait time limit
+    
+    reg [15:0]     uart_rx_nu           ;
+    reg [15:0]     uart_tx_nu           ;
+    reg [7:0]      uart_write_data [0:39];
+    reg 	       uart_fifo_enable     ;	// fifo mode disable
+	reg            flag                 ;
+    reg            compare_start        ; // User Need to make sure that compare start match with RiscV core completing initial booting
+
+	reg [31:0]     check_sum            ;
+        
 	integer    d_risc_id;
 
+         integer i,j;
 
 
-	// External clock is used by default.  Make this artificially fast for the
-	// simulation.  Normally this would be a slow clock and the digital PLL
-	// would be the fast clock.
 
-	always #12.5 clock <= (clock === 1'b0);
+
+	// 50Mhz CLock
+	always #10 clock <= (clock === 1'b0);
 
 	initial begin
 		clock = 0;
-                wbd_ext_cyc_i ='h0;  // strobe/request
-                wbd_ext_stb_i ='h0;  // strobe/request
-                wbd_ext_adr_i ='h0;  // address
-                wbd_ext_we_i  ='h0;  // write
-                wbd_ext_dat_i ='h0;  // data output
-                wbd_ext_sel_i ='h0;  // byte enable
+	    flag  = 0;
+        compare_start = 0;
+        wbd_ext_cyc_i ='h0;  // strobe/request
+        wbd_ext_stb_i ='h0;  // strobe/request
+        wbd_ext_adr_i ='h0;  // address
+        wbd_ext_we_i  ='h0;  // write
+        wbd_ext_dat_i ='h0;  // data output
+        wbd_ext_sel_i ='h0;  // byte enable
 	end
 
 	`ifdef WFDUMP
 	   initial begin
 	   	$dumpfile("simx.vcd");
-	   	$dumpvars(1, user_mcore_tb);
-	   	$dumpvars(1, user_mcore_tb.u_top);
-	   	$dumpvars(0, user_mcore_tb.u_top.u_riscv_top);
+	   	$dumpvars(3, arduino_string_tb);
+	   	$dumpvars(0, arduino_string_tb.u_top.u_riscv_top.i_core_top_0);
+	   	$dumpvars(0, arduino_string_tb.u_top.u_riscv_top.u_connect);
+	   	$dumpvars(0, arduino_string_tb.u_top.u_riscv_top.u_intf);
+	   	$dumpvars(0, arduino_string_tb.u_top.u_uart_i2c_usb_spi.u_uart0_core);
 	   end
        `endif
 
+       /*************************************************************************
+       * This is Baud Rate to clock divider conversion for Test Bench
+       * Note: DUT uses 16x baud clock, where are test bench uses directly
+       * baud clock, Due to 16x Baud clock requirement at RTL, there will be
+       * some resolution loss, we expect at lower baud rate this resolution
+       * loss will be less. For Quick simulation perpose higher baud rate used
+       * *************************************************************************/
+       task tb_set_uart_baud;
+       input [31:0] ref_clk;
+       input [31:0] baud_rate;
+       output [31:0] baud_div;
+       reg   [31:0] baud_div;
+       begin
+	  // for 230400 Baud = (50Mhz/230400) = 216.7
+	  baud_div = ref_clk/baud_rate; // Get the Bit Baud rate
+	  // Baud 16x = 216/16 = 13
+          baud_div = baud_div/16; // To find the RTL baud 16x div value to find similar resolution loss in test bench
+	  // Test bench baud clock , 16x of above value
+	  // 13 * 16 = 208,  
+	  // (Note if you see original value was 216, now it's 208 )
+          baud_div = baud_div * 16;
+	  // Test bench half cycle counter to toggle it 
+	  // 208/2 = 104
+           baud_div = baud_div/2;
+	  //As counter run's from 0 , substract from 1
+	   baud_div = baud_div-1;
+       end
+       endtask
+       
+
 	initial begin
+        uart_data_bit           = 2'b11;
+        uart_stop_bits          = 0; // 0: 1 stop bit; 1: 2 stop bit;
+        uart_stick_parity       = 0; // 1: force even parity
+        uart_parity_en          = 0; // parity enable
+        uart_even_odd_parity    = 1; // 0: odd parity; 1: even parity
+	    tb_set_uart_baud(50000000,1152000,uart_divisor);// 50Mhz Ref clock, Baud Rate: 230400
+        uart_timeout            = 20000;// wait time limit
+        uart_fifo_enable        = 0;	// fifo mode disable
 
 		$value$plusargs("risc_core_id=%d", d_risc_id);
 
 		#200; // Wait for reset removal
-	        repeat (10) @(posedge clock);
+	    repeat (10) @(posedge clock);
 		$display("Monitor: Standalone User Risc Boot Test Started");
 
 		// Remove Wb Reset
 		wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
 
-	        repeat (2) @(posedge clock);
+	    repeat (2) @(posedge clock);
 		#1;
-		// Remove all the reset
-		$display("STATUS: Working with Both core Risc core 0 & 1 ");
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h31F);
+        // Remove all the reset
+        if(d_risc_id == 0) begin
+             $display("STATUS: Working with Risc core 0");
+             wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
+        end else if(d_risc_id == 1) begin
+             $display("STATUS: Working with Risc core 1");
+             wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
+        end else if(d_risc_id == 2) begin
+             $display("STATUS: Working with Risc core 2");
+             wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F);
+        end else if(d_risc_id == 3) begin
+             $display("STATUS: Working with Risc core 3");
+             wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
+        end
 
+        repeat (100) @(posedge clock);  // wait for Processor Get Ready
 
-		// Repeat cycles of 1000 clock edges as needed to complete testbench
-		repeat (22) begin
-			repeat (1000) @(posedge clock);
-			// $display("+1000 cycles");
-		end
+	    tb_uart.debug_mode = 0; // disable debug display
+        tb_uart.uart_init;
+        tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, 
+                                       uart_stick_parity, uart_timeout, uart_divisor);
 
+        repeat (60000) @(posedge clock);  // wait for Processor Get Ready
+	    flag  = 0;
+		check_sum = 0;
+        compare_start = 1;
+        
+        fork
+           begin
+              while(flag == 0)
+              begin
+                 tb_uart.read_char(read_data,flag);
+		         if(flag == 0)  begin
+		            $write ("%c",read_data);
+		            check_sum = check_sum+read_data;
+		         end
+              end
+           end
+           begin
+              repeat (200000) @(posedge clock);  // wait for Processor Get Ready
+           end
+           join_any
+        
+           #100
+           tb_uart.report_status(uart_rx_nu, uart_tx_nu);
+        
+           test_fail = 0;
 
-		$display("Monitor: Reading Back the expected value");
-		// User RISC core expect to write these value in global
-		// register, read back and decide on pass fail
-		// 0x30000018  = 0x11223344; 
-                // 0x3000001C  = 0x22334455; 
-                // 0x30000020  = 0x33445566; 
-                // 0x30000024  = 0x44556677; 
-                // 0x30000028 = 0x55667788; 
-                // 0x3000002C = 0x66778899; 
-
-                test_fail = 0;
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h11223344);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h22334455);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h33445566);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32'h44556677);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32'h55667788);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32'h66778899);
-
+		   $display("Total Rx Char: %d Check Sum : %x ",uart_rx_nu, check_sum);
+           // Check 
+           // if all the 102 byte received
+           // if no error 
+           if(uart_rx_nu != 102) test_fail = 1;
+           if(check_sum != 32'h1fab) test_fail = 1;
+           if(tb_uart.err_cnt != 0) test_fail = 1;
 
 	   
 	    	$display("###################################################");
           	if(test_fail == 0) begin
 		   `ifdef GL
-	    	       $display("Monitor: Standalone User Risc Boot (GL) Passed");
+	    	       $display("Monitor: Standalone String (GL) Passed");
 		   `else
-		       $display("Monitor: Standalone User Risc Boot (RTL) Passed");
+		       $display("Monitor: Standalone String (RTL) Passed");
 		   `endif
 	        end else begin
 		    `ifdef GL
-	    	        $display("Monitor: Standalone User Risc Boot (GL) Failed");
+	    	        $display("Monitor: Standalone String (GL) Failed");
 		    `else
-		        $display("Monitor: Standalone User Risc Boot (RTL) Failed");
+		        $display("Monitor: Standalone String (RTL) Failed");
 		    `endif
 		 end
 	    	$display("###################################################");
@@ -257,8 +351,8 @@
    assign io_in[32] = flash_io3;
 
    // Quard flash
-     s25fl256s #(.mem_file_name("user_mcore.hex"),
-	         .otp_file_name("none"),
+     s25fl256s #(.mem_file_name("arduino_string.ino.hex"),
+	             .otp_file_name("none"),
                  .TimingModel("S25FL512SAGMFI010_F_30pF")) 
 		 u_spi_flash_256mb (
            // Data Inputs/Outputs
@@ -274,6 +368,19 @@
        );
 
 
+//---------------------------
+//  UART Agent integration
+// --------------------------
+wire uart_txd,uart_rxd;
+
+assign uart_txd   = io_out[2];
+assign io_in[1]  = uart_rxd ;
+ 
+uart_agent tb_uart(
+	.mclk                (clock              ),
+	.txd                 (uart_rxd           ),
+	.rxd                 (uart_txd           )
+	);
 
 
 task wb_user_core_write;
diff --git a/verilog/dv/arduino_switchCase2/Makefile b/verilog/dv/arduino_switchCase2/Makefile
new file mode 100644
index 0000000..2533931
--- /dev/null
+++ b/verilog/dv/arduino_switchCase2/Makefile
@@ -0,0 +1,140 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+ 
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+DESIGNS?=../../..
+TOOLS?=/opt/riscv32i/
+
+export USER_PROJECT_VERILOG ?=  $(DESIGNS)/verilog
+export RISCDUINO_BOARD ?=  $(USER_PROJECT_VERILOG)/dv/common/riscduino_board/custom_board/riscduino
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+GCC_PREFIX?=riscv32-unknown-elf
+
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+RISC_CORE?=0
+
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
+.SUFFIXES:
+
+PATTERN = arduino_switchCase2
+
+all:  ${PATTERN:=.vcd}
+
+
+vvp:  ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${PATTERN}.ino.cpp -o ${PATTERN}.ino.cpp.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/Print.cpp -o Print.cpp.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WMath.cpp -o WMath.cpp.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WString.cpp -o WString.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WInterrupts.c -o WInterrupts.c.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/fe300prci/fe300prci_driver.c -o fe300prci_driver.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/abi.cpp -o abi.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/plic/plic_driver.c -o plic_driver.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/UARTClass.cpp -o UARTClass.cpp.o
+	${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/entry.S -o entry.S.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/hooks.c -o hooks.c.o
+	${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/init.S -o init.S.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/itoa.c -o itoa.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/main.cpp -o main.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/malloc.c -o malloc.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/new.cpp -o new.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/sbrk.c -o sbrk.c.o
+	${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/start.S -o start.S.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring.c -o wiring.c.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_analog.c -o wiring_analog.c.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_digital.c -o wiring_digital.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_pulse.cpp -o wiring_pulse.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_shift.c -o wiring_shift.c.o
+	${GCC_PREFIX}-ar rcs core.a Print.cpp.o
+	${GCC_PREFIX}-ar rcs core.a UARTClass.cpp.o
+	${GCC_PREFIX}-ar rcs core.a WInterrupts.c.o
+	${GCC_PREFIX}-ar rcs core.a WMath.cpp.o
+	${GCC_PREFIX}-ar rcs core.a WString.cpp.o
+	${GCC_PREFIX}-ar rcs core.a abi.cpp.o
+	${GCC_PREFIX}-ar rcs core.a fe300prci_driver.c.o
+	${GCC_PREFIX}-ar rcs core.a plic_driver.c.o
+	${GCC_PREFIX}-ar rcs core.a entry.S.o
+	${GCC_PREFIX}-ar rcs core.a hooks.c.o
+	${GCC_PREFIX}-ar rcs core.a init.S.o
+	${GCC_PREFIX}-ar rcs core.a itoa.c.o
+	${GCC_PREFIX}-ar rcs core.a main.cpp.o
+	${GCC_PREFIX}-ar rcs core.a malloc.c.o
+	${GCC_PREFIX}-ar rcs core.a new.cpp.o
+	${GCC_PREFIX}-ar rcs core.a sbrk.c.o
+	${GCC_PREFIX}-ar rcs core.a start.S.o
+	${GCC_PREFIX}-ar rcs core.a wiring.c.o
+	${GCC_PREFIX}-ar rcs core.a wiring_analog.c.o
+	${GCC_PREFIX}-ar rcs core.a wiring_digital.c.o
+	${GCC_PREFIX}-ar rcs core.a wiring_pulse.cpp.o
+	${GCC_PREFIX}-ar rcs core.a wiring_shift.c.o
+	${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf
+	${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.ino.elf ${PATTERN}.ino.bin
+	${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.ino.elf ${PATTERN}.ino.hex
+	${GCC_PREFIX}-objdump -D  ${PATTERN}.ino.elf >   ${PATTERN}.ino.dump
+	rm *.o *.a
+ifeq ($(SIM),RTL)
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
+	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
+	$< -o $@ 
+   endif
+else  
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+   endif
+endif
+
+%.vcd: %.vvp
+	vvp $< +risc_core_id=$(RISC_CORE)
+
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump *.a *.o
+
+.PHONY: clean hex all
diff --git a/verilog/dv/arduino_switchCase2/arduino_switchCase2.ino b/verilog/dv/arduino_switchCase2/arduino_switchCase2.ino
new file mode 100644
index 0000000..48cbaa4
--- /dev/null
+++ b/verilog/dv/arduino_switchCase2/arduino_switchCase2.ino
@@ -0,0 +1,65 @@
+/*
+  Switch statement with serial input
+
+  Demonstrates the use of a switch statement. The switch statement allows you
+  to choose from among a set of discrete values of a variable. It's like a
+  series of if statements.
+
+  To see this sketch in action, open the Serial monitor and send any character.
+  The characters a, b, c, d, and e, will turn on LEDs. Any other character will
+  turn the LEDs off.
+
+  The circuit:
+  - five LEDs attached to digital pins 2 through 6 through 220 ohm resistors
+
+  created 1 Jul 2009
+  by Tom Igoe
+
+  This example code is in the public domain.
+
+  https://www.arduino.cc/en/Tutorial/BuiltInExamples/SwitchCase2
+*/
+
+void setup() {
+  // initialize serial communication:
+  Serial.begin(9600);
+  // initialize the LED pins:
+  for (int thisPin = 2; thisPin < 7; thisPin++) {
+    pinMode(thisPin, OUTPUT);
+  }
+}
+
+void loop() {
+  // read the sensor:
+  if (Serial.available() > 0) {
+    int inByte = Serial.read();
+    // do something different depending on the character received.
+    // The switch statement expects single number values for each case; in this
+    // example, though, you're using single quotes to tell the controller to get
+    // the ASCII value for the character. For example 'a' = 97, 'b' = 98,
+    // and so forth:
+
+    switch (inByte) {
+      case 'a':
+        digitalWrite(2, HIGH);
+        break;
+      case 'b':
+        digitalWrite(3, HIGH);
+        break;
+      case 'c':
+        digitalWrite(4, HIGH);
+        break;
+      case 'd':
+        digitalWrite(5, HIGH);
+        break;
+      case 'e':
+        digitalWrite(6, HIGH);
+        break;
+      default:
+        // turn all the LEDs off:
+        for (int thisPin = 2; thisPin < 7; thisPin++) {
+          digitalWrite(thisPin, LOW);
+        }
+    }
+  }
+}
diff --git a/verilog/dv/arduino_switchCase2/arduino_switchCase2.ino.cpp b/verilog/dv/arduino_switchCase2/arduino_switchCase2.ino.cpp
new file mode 100644
index 0000000..e6c0924
--- /dev/null
+++ b/verilog/dv/arduino_switchCase2/arduino_switchCase2.ino.cpp
@@ -0,0 +1,69 @@
+#include <Arduino.h>
+/*
+  Switch statement with serial input
+
+  Demonstrates the use of a switch statement. The switch statement allows you
+  to choose from among a set of discrete values of a variable. It's like a
+  series of if statements.
+
+  To see this sketch in action, open the Serial monitor and send any character.
+  The characters a, b, c, d, and e, will turn on LEDs. Any other character will
+  turn the LEDs off.
+
+  The circuit:
+  - five LEDs attached to digital pins 2 through 6 through 220 ohm resistors
+
+  created 1 Jul 2009
+  by Tom Igoe
+
+  This example code is in the public domain.
+
+  https://www.arduino.cc/en/Tutorial/BuiltInExamples/SwitchCase2
+*/
+
+void setup();
+void loop();
+void setup() {
+  // initialize serial communication:
+  Serial.begin(1152000);
+  // initialize the LED pins:
+  for (int thisPin = 2; thisPin < 7; thisPin++) {
+    pinMode(thisPin, OUTPUT);
+  }
+}
+
+void loop() {
+  // read the sensor:
+  if (Serial.available() > 0) {
+    int inByte = Serial.read();
+    // do something different depending on the character received.
+    // The switch statement expects single number values for each case; in this
+    // example, though, you're using single quotes to tell the controller to get
+    // the ASCII value for the character. For example 'a' = 97, 'b' = 98,
+    // and so forth:
+
+    switch (inByte) {
+      case 'a':
+        digitalWrite(2, HIGH);
+        break;
+      case 'b':
+        digitalWrite(3, HIGH);
+        break;
+      case 'c':
+        digitalWrite(4, HIGH);
+        break;
+      case 'd':
+        digitalWrite(5, HIGH);
+        break;
+      case 'e':
+        digitalWrite(6, HIGH);
+        break;
+      default:
+        // turn all the LEDs off:
+        for (int thisPin = 2; thisPin < 7; thisPin++) {
+          digitalWrite(thisPin, LOW);
+        }
+    }
+  }
+}
+
diff --git a/verilog/dv/arduino_switchCase2/arduino_switchCase2_tb.v b/verilog/dv/arduino_switchCase2/arduino_switchCase2_tb.v
new file mode 100644
index 0000000..c3e9ffb
--- /dev/null
+++ b/verilog/dv/arduino_switchCase2/arduino_switchCase2_tb.v
@@ -0,0 +1,587 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  Standalone User validation Test bench                       ////
+////                                                              ////
+////  This file is part of the YIFive cores project               ////
+////  https://github.com/dineshannayya/yifive_r0.git              ////
+////  http://www.opencores.org/cores/yifive/                      ////
+////                                                              ////
+////  Description                                                 ////
+////   This is a standalone test bench to validate the            ////
+////   Digital core.                                              ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision :                                                  ////
+////    0.1 - 16th Feb 2021, Dinesh A                             ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+`default_nettype wire
+
+`timescale 1 ns / 1 ns
+
+`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+`include "uart_agent.v"
+`include "is62wvs1288.v"
+
+module arduino_switchCase2_tb;
+	reg clock;
+	reg wb_rst_i;
+	reg power1, power2;
+	reg power3, power4;
+
+        reg        wbd_ext_cyc_i;  // strobe/request
+        reg        wbd_ext_stb_i;  // strobe/request
+        reg [31:0] wbd_ext_adr_i;  // address
+        reg        wbd_ext_we_i;  // write
+        reg [31:0] wbd_ext_dat_i;  // data output
+        reg [3:0]  wbd_ext_sel_i;  // byte enable
+
+        wire [31:0] wbd_ext_dat_o;  // data input
+        wire        wbd_ext_ack_o;  // acknowlegement
+        wire        wbd_ext_err_o;  // error
+
+	// User I/O
+	wire [37:0] io_oeb;
+	wire [37:0] io_out;
+	wire [37:0] io_in;
+
+	wire gpio;
+	wire [37:0] mprj_io;
+	wire [7:0] mprj_io_0;
+	reg         test_fail;
+	reg [31:0] read_data;
+        //----------------------------------
+        // Uart Configuration
+        // ---------------------------------
+        reg [1:0]      uart_data_bit        ;
+        reg	       uart_stop_bits       ; // 0: 1 stop bit; 1: 2 stop bit;
+        reg	       uart_stick_parity    ; // 1: force even parity
+        reg	       uart_parity_en       ; // parity enable
+        reg	       uart_even_odd_parity ; // 0: odd parity; 1: even parity
+        
+        reg [7:0]      uart_data            ;
+        reg [15:0]     uart_divisor         ;	// divided by n * 16
+        reg [15:0]     uart_timeout         ;// wait time limit
+        
+        reg [15:0]     uart_rx_nu           ;
+        reg [15:0]     uart_tx_nu           ;
+        reg [7:0]      uart_write_data [0:39];
+        reg 	       uart_fifo_enable     ;	// fifo mode disable
+	reg            flag                 ;
+
+	reg [31:0]     check_sum            ;
+        
+	integer    d_risc_id;
+
+         integer i,j;
+
+parameter P_FSM_C      = 4'b0000; // Command Phase Only
+parameter P_FSM_CW     = 4'b0001; // Command + Write DATA Phase Only
+parameter P_FSM_CA     = 4'b0010; // Command -> Address Phase Only
+
+parameter P_FSM_CAR    = 4'b0011; // Command -> Address -> Read Data
+parameter P_FSM_CADR   = 4'b0100; // Command -> Address -> Dummy -> Read Data
+parameter P_FSM_CAMR   = 4'b0101; // Command -> Address -> Mode -> Read Data
+parameter P_FSM_CAMDR  = 4'b0110; // Command -> Address -> Mode -> Dummy -> Read Data
+
+parameter P_FSM_CAW    = 4'b0111; // Command -> Address ->Write Data
+parameter P_FSM_CADW   = 4'b1000; // Command -> Address -> DUMMY + Write Data
+parameter P_FSM_CAMW   = 4'b1001; // Command -> Address -> MODE + Write Data
+
+parameter P_FSM_CDR    = 4'b1010; // COMMAND -> DUMMY -> READ
+parameter P_FSM_CDW    = 4'b1011; // COMMAND -> DUMMY -> WRITE
+parameter P_FSM_CR     = 4'b1100;  // COMMAND -> READ
+
+parameter P_MODE_SWITCH_IDLE     = 2'b00;
+parameter P_MODE_SWITCH_AT_ADDR  = 2'b01;
+parameter P_MODE_SWITCH_AT_DATA  = 2'b10;
+
+parameter P_SINGLE = 2'b00;
+parameter P_DOUBLE = 2'b01;
+parameter P_QUAD   = 2'b10;
+parameter P_QDDR   = 2'b11;
+
+
+
+	// 50Mhz CLock
+	always #10 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	        flag  = 0;
+                wbd_ext_cyc_i ='h0;  // strobe/request
+                wbd_ext_stb_i ='h0;  // strobe/request
+                wbd_ext_adr_i ='h0;  // address
+                wbd_ext_we_i  ='h0;  // write
+                wbd_ext_dat_i ='h0;  // data output
+                wbd_ext_sel_i ='h0;  // byte enable
+	end
+
+	`ifdef WFDUMP
+	   initial begin
+	   	$dumpfile("simx.vcd");
+	   	$dumpvars(3, arduino_switchCase2_tb);
+	   	$dumpvars(0, arduino_switchCase2_tb.u_top.u_riscv_top.i_core_top_0);
+	   	$dumpvars(0, arduino_switchCase2_tb.u_top.u_riscv_top.u_connect);
+	   	$dumpvars(0, arduino_switchCase2_tb.u_top.u_riscv_top.u_intf);
+	   	$dumpvars(0, arduino_switchCase2_tb.u_top.u_uart_i2c_usb_spi.u_uart0_core);
+	   end
+       `endif
+
+       /*************************************************************************
+       * This is Baud Rate to clock divider conversion for Test Bench
+       * Note: DUT uses 16x baud clock, where are test bench uses directly
+       * baud clock, Due to 16x Baud clock requirement at RTL, there will be
+       * some resolution loss, we expect at lower baud rate this resolution
+       * loss will be less. For Quick simulation perpose higher baud rate used
+       * *************************************************************************/
+       task tb_set_uart_baud;
+       input [31:0] ref_clk;
+       input [31:0] baud_rate;
+       output [31:0] baud_div;
+       reg   [31:0] baud_div;
+       begin
+	  // for 230400 Baud = (50Mhz/230400) = 216.7
+	  baud_div = ref_clk/baud_rate; // Get the Bit Baud rate
+	  // Baud 16x = 216/16 = 13
+          baud_div = baud_div/16; // To find the RTL baud 16x div value to find similar resolution loss in test bench
+	  // Test bench baud clock , 16x of above value
+	  // 13 * 16 = 208,  
+	  // (Note if you see original value was 216, now it's 208 )
+          baud_div = baud_div * 16;
+	  // Test bench half cycle counter to toggle it 
+	  // 208/2 = 104
+           baud_div = baud_div/2;
+	  //As counter run's from 0 , substract from 1
+	   baud_div = baud_div-1;
+       end
+       endtask
+       
+
+     /************* Port-D Mapping **********************************
+      *             Arduino-No
+      *   Pin-2        0         PD0/RXD[0]                digital_io[1]
+      *   Pin-3        1         PD1/TXD[0]                digital_io[2]
+      *   Pin-4        2         PD2/RXD[1]/INT0           digital_io[3]
+      *   Pin-5        3         PD3/INT1/OC2B(PWM0)       digital_io[4]
+      *   Pin-6        4         PD4/TXD[1]                digital_io[5]
+      *   Pin-11       5         PD5/SS[3]/OC0B(PWM1)/T1   digital_io[8]
+      *   Pin-12       6         PD6/SS[2]/OC0A(PWM2)/AIN0 digital_io[9]/analog_io[2]
+      *   Pin-13       7         PD7/A1N1                  digital_io[10]/analog_io[3]
+      *   ********************************************************/
+
+     wire [7:0]  port_d_in = {  io_out[10],
+		                        io_out[9],
+		                        io_out[8],
+		                        io_out[5],
+			                    io_out[4],
+			                    io_out[3],
+		                        io_out[2],
+		                        io_out[1]
+			                };
+	initial begin
+               uart_data_bit           = 2'b11;
+               uart_stop_bits          = 0; // 0: 1 stop bit; 1: 2 stop bit;
+               uart_stick_parity       = 0; // 1: force even parity
+               uart_parity_en          = 0; // parity enable
+               uart_even_odd_parity    = 1; // 0: odd parity; 1: even parity
+	       tb_set_uart_baud(50000000,1152000,uart_divisor);// 50Mhz Ref clock, Baud Rate: 230400
+               uart_timeout            = 2000;// wait time limit
+               uart_fifo_enable        = 0;	// fifo mode disable
+
+		$value$plusargs("risc_core_id=%d", d_risc_id);
+
+		#200; // Wait for reset removal
+	        repeat (10) @(posedge clock);
+		$display("Monitor: Standalone User Risc Boot Test Started");
+
+		// Remove Wb Reset
+		wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+
+	    repeat (2) @(posedge clock);
+		#1;
+        // Remove WB and SPI Reset, Keep SDARM and CORE under Reset
+        wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F);
+
+		// QSPI SRAM:CS#2 Switch to QSPI Mode
+        wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h38});
+		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0);
+
+        // Remove all the reset
+        if(d_risc_id == 0) begin
+           $display("STATUS: Working with Risc core 0");
+           wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
+        end else if(d_risc_id == 1) begin
+           $display("STATUS: Working with Risc core 1");
+           wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
+        end else if(d_risc_id == 2) begin
+           $display("STATUS: Working with Risc core 2");
+           wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F);
+        end else if(d_risc_id == 3) begin
+           $display("STATUS: Working with Risc core 3");
+           wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
+        end
+
+        repeat (100) @(posedge clock);  // wait for Processor Get Ready
+
+	    tb_uart.debug_mode = 0; // disable debug display
+        tb_uart.uart_init;
+        tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, 
+                               uart_stick_parity, uart_timeout, uart_divisor);
+
+        repeat (45000) @(posedge clock);  // wait for Processor Get Ready
+	    flag  = 1;
+		check_sum = 0;
+        fork
+        begin 
+            fork
+            begin
+               tb_uart.write_char ("a");
+               tb_uart.write_char ("b");
+               tb_uart.write_char ("c");
+               tb_uart.write_char ("d");
+               tb_uart.write_char ("e");
+            end
+            begin
+               wait(port_d_in[2] == 1'b1);
+               $display("PORT-D Pin-2 High Detected");
+               wait(port_d_in[3] == 1'b1);
+               $display("PORT-D Pin-3 High Detected");
+               wait(port_d_in[4] == 1'b1);
+               $display("PORT-D Pin-4 High Detected");
+               wait(port_d_in[5] == 1'b1);
+               $display("PORT-D Pin-5 High Detected");
+               wait(port_d_in[6] == 1'b1);
+               $display("PORT-D Pin-6 High Detected");
+               test_fail =0;
+            end
+            join
+        end
+        begin
+           repeat (3000000) @(posedge clock);  // wait for Processor Get Ready
+           test_fail =1;
+        end
+        join_any
+        
+           #100
+           tb_uart.report_status(uart_rx_nu, uart_tx_nu);
+        
+
+	   
+	    	$display("###################################################");
+          	if(test_fail == 0) begin
+		   `ifdef GL
+	    	       $display("Monitor: arduino_switchCase2 (GL) Passed");
+		   `else
+		       $display("Monitor: arduino_switchCase2 (RTL) Passed");
+		   `endif
+	        end else begin
+		    `ifdef GL
+	    	        $display("Monitor: arduino_switchCase2 (GL) Failed");
+		    `else
+		        $display("Monitor: arduino_switchCase2 (RTL) Failed");
+		    `endif
+		 end
+	    	$display("###################################################");
+	    $finish;
+	end
+
+	initial begin
+		wb_rst_i <= 1'b1;
+		#100;
+		wb_rst_i <= 1'b0;	    	// Release reset
+	end
+wire USER_VDD1V8 = 1'b1;
+wire VSS = 1'b0;
+
+user_project_wrapper u_top(
+`ifdef USE_POWER_PINS
+    .vccd1(USER_VDD1V8),	// User area 1 1.8V supply
+    .vssd1(VSS),	// User area 1 digital ground
+`endif
+    .wb_clk_i        (clock),  // System clock
+    .user_clock2     (1'b1),  // Real-time clock
+    .wb_rst_i        (wb_rst_i),  // Regular Reset signal
+
+    .wbs_cyc_i   (wbd_ext_cyc_i),  // strobe/request
+    .wbs_stb_i   (wbd_ext_stb_i),  // strobe/request
+    .wbs_adr_i   (wbd_ext_adr_i),  // address
+    .wbs_we_i    (wbd_ext_we_i),  // write
+    .wbs_dat_i   (wbd_ext_dat_i),  // data output
+    .wbs_sel_i   (wbd_ext_sel_i),  // byte enable
+
+    .wbs_dat_o   (wbd_ext_dat_o),  // data input
+    .wbs_ack_o   (wbd_ext_ack_o),  // acknowlegement
+
+ 
+    // Logic Analyzer Signals
+    .la_data_in      ('1) ,
+    .la_data_out     (),
+    .la_oenb         ('0),
+ 
+
+    // IOs
+    .io_in          (io_in)  ,
+    .io_out         (io_out) ,
+    .io_oeb         (io_oeb) ,
+
+    .user_irq       () 
+
+);
+
+`ifndef GL // Drive Power for Hold Fix Buf
+    // All standard cell need power hook-up for functionality work
+    initial begin
+
+    end
+`endif    
+
+//------------------------------------------------------
+//  Integrate the Serial flash with qurd support to
+//  user core using the gpio pads
+//  ----------------------------------------------------
+
+   wire flash_clk = io_out[24];
+   wire flash_csb = io_out[25];
+   // Creating Pad Delay
+   wire #1 io_oeb_29 = io_oeb[29];
+   wire #1 io_oeb_30 = io_oeb[30];
+   wire #1 io_oeb_31 = io_oeb[31];
+   wire #1 io_oeb_32 = io_oeb[32];
+   tri  #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz;
+   tri  #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz;
+   tri  #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz;
+   tri  #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz;
+
+   assign io_in[29] = flash_io0;
+   assign io_in[30] = flash_io1;
+   assign io_in[31] = flash_io2;
+   assign io_in[32] = flash_io3;
+
+   // Quard flash
+     s25fl256s #(.mem_file_name("arduino_switchCase2.ino.hex"),
+	         .otp_file_name("none"),
+                 .TimingModel("S25FL512SAGMFI010_F_30pF")) 
+		 u_spi_flash_256mb (
+           // Data Inputs/Outputs
+       .SI      (flash_io0),
+       .SO      (flash_io1),
+       // Controls
+       .SCK     (flash_clk),
+       .CSNeg   (flash_csb),
+       .WPNeg   (flash_io2),
+       .HOLDNeg (flash_io3),
+       .RSTNeg  (!wb_rst_i)
+
+       );
+
+
+   wire spiram_csb = io_out[27];
+
+   is62wvs1288 #(.mem_file_name("none"))
+	u_sram (
+         // Data Inputs/Outputs
+           .io0     (flash_io0),
+           .io1     (flash_io1),
+           // Controls
+           .clk    (flash_clk),
+           .csb    (spiram_csb),
+           .io2    (flash_io2),
+           .io3    (flash_io3)
+    );
+//---------------------------
+//  UART Agent integration
+// --------------------------
+wire uart_txd,uart_rxd;
+
+assign uart_txd   = io_out[2];
+assign io_in[1]  = uart_rxd ;
+ 
+uart_agent tb_uart(
+	.mclk                (clock              ),
+	.txd                 (uart_rxd           ),
+	.rxd                 (uart_txd           )
+	);
+
+
+task wb_user_core_write;
+input [31:0] address;
+input [31:0] data;
+begin
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_adr_i =address;  // address
+  wbd_ext_we_i  ='h1;  // write
+  wbd_ext_dat_i =data;  // data output
+  wbd_ext_sel_i ='hF;  // byte enable
+  wbd_ext_cyc_i ='h1;  // strobe/request
+  wbd_ext_stb_i ='h1;  // strobe/request
+  wait(wbd_ext_ack_o == 1);
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_cyc_i ='h0;  // strobe/request
+  wbd_ext_stb_i ='h0;  // strobe/request
+  wbd_ext_adr_i ='h0;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='h0;  // data output
+  wbd_ext_sel_i ='h0;  // byte enable
+  $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
+  repeat (2) @(posedge clock);
+end
+endtask
+
+task  wb_user_core_read;
+input [31:0] address;
+output [31:0] data;
+reg    [31:0] data;
+begin
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_adr_i =address;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='0;  // data output
+  wbd_ext_sel_i ='hF;  // byte enable
+  wbd_ext_cyc_i ='h1;  // strobe/request
+  wbd_ext_stb_i ='h1;  // strobe/request
+  wait(wbd_ext_ack_o == 1);
+  repeat (1) @(negedge clock);
+  data  = wbd_ext_dat_o;  
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_cyc_i ='h0;  // strobe/request
+  wbd_ext_stb_i ='h0;  // strobe/request
+  wbd_ext_adr_i ='h0;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='h0;  // data output
+  wbd_ext_sel_i ='h0;  // byte enable
+  $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
+  repeat (2) @(posedge clock);
+end
+endtask
+
+task  wb_user_core_read_check;
+input [31:0] address;
+output [31:0] data;
+input [31:0] cmp_data;
+reg    [31:0] data;
+begin
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_adr_i =address;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='0;  // data output
+  wbd_ext_sel_i ='hF;  // byte enable
+  wbd_ext_cyc_i ='h1;  // strobe/request
+  wbd_ext_stb_i ='h1;  // strobe/request
+  wait(wbd_ext_ack_o == 1);
+  repeat (1) @(negedge clock);
+  data  = wbd_ext_dat_o;  
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_cyc_i ='h0;  // strobe/request
+  wbd_ext_stb_i ='h0;  // strobe/request
+  wbd_ext_adr_i ='h0;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='h0;  // data output
+  wbd_ext_sel_i ='h0;  // byte enable
+  if(data !== cmp_data) begin
+     $display("ERROR : WB USER ACCESS READ  Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
+     test_fail = 1;
+  end else begin
+     $display("STATUS: WB USER ACCESS READ  Address : 0x%x, Data : 0x%x",address,data);
+  end
+  repeat (2) @(posedge clock);
+end
+endtask
+
+`ifdef GL
+
+wire        wbd_spi_stb_i   = u_top.u_qspi_master.wbd_stb_i;
+wire        wbd_spi_ack_o   = u_top.u_qspi_master.wbd_ack_o;
+wire        wbd_spi_we_i    = u_top.u_qspi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i   = u_top.u_qspi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i   = u_top.u_qspi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o   = u_top.u_qspi_master.wbd_dat_o;
+wire [3:0]  wbd_spi_sel_i   = u_top.u_qspi_master.wbd_sel_i;
+
+wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb_spi.reg_cs;
+wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb_spi.reg_ack;
+wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb_spi.reg_wr;
+wire [8:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb_spi.reg_addr;
+wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb_spi.reg_wdata;
+wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb_spi.reg_rdata;
+wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb_spi.reg_be;
+
+`endif
+
+/**
+`ifdef GL
+//-----------------------------------------------------------------------------
+// RISC IMEM amd DMEM Monitoring TASK
+//-----------------------------------------------------------------------------
+
+`define RISC_CORE  user_uart_tb.u_top.u_core.u_riscv_top
+
+always@(posedge `RISC_CORE.wb_clk) begin
+    if(`RISC_CORE.wbd_imem_ack_i)
+          $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
+    if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
+          $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
+    if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
+          $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
+end
+
+`endif
+**/
+endmodule
+`include "s25fl256s.sv"
+`default_nettype wire
diff --git a/verilog/dv/bfm/bfm_ad5205.sv b/verilog/dv/bfm/bfm_ad5205.sv
new file mode 100644
index 0000000..d2ea131
--- /dev/null
+++ b/verilog/dv/bfm/bfm_ad5205.sv
@@ -0,0 +1,28 @@
+module bfm_ad5205 (
+              input  logic       sck      ,
+              input  logic       sdi      ,
+              input  logic       ssn      ,
+
+              output logic [2:0] channel  ,
+              output logic [7:0] position 
+           );
+
+
+logic [10:0] shift_reg;
+logic [10:0] load_reg;
+
+
+always @(posedge ssn)
+   load_reg = shift_reg;
+
+
+always @(posedge sck)
+    shift_reg = {shift_reg[9:0],sdi};
+
+
+assign channel  = load_reg[10:8];
+assign position = load_reg[7:0];
+
+
+endmodule
+
diff --git a/verilog/dv/c_func/inc/ext_reg_map.h b/verilog/dv/c_func/inc/ext_reg_map.h
new file mode 100644
index 0000000..cdb04f3
--- /dev/null
+++ b/verilog/dv/c_func/inc/ext_reg_map.h
@@ -0,0 +1,83 @@
+//--------------------------------------------------------------------
+// Register Address Map As Seen By the External/Caravel RISCV Core
+//--------------------------------------------------------------------
+
+//-------------------------------------
+// PinMux Register
+// ------------------------------------
+#define reg_glbl_chip_id       (*(volatile uint32_t*)0x30020000)  // reg_0  - Chip ID
+#define reg_glbl_cfg0          (*(volatile uint32_t*)0x30020004)  // reg_1  - Global Config-0
+#define reg_glbl_cfg1          (*(volatile uint32_t*)0x30020008)  // reg_2  - Global Config-1
+#define reg_glbl_intr_msk      (*(volatile uint32_t*)0x3002000C)  // reg_3  - Global Interrupt Mask
+#define reg_glbl_intr          (*(volatile uint32_t*)0x30020010)  // reg_4  - Global Interrupt
+#define reg_glbl_multi_func    (*(volatile uint32_t*)0x30020014)  // reg_5 - GPIO Multi Function
+#define reg_glbl_soft_reg_0    (*(volatile uint32_t*)0x30020018)  // reg_6 - Soft Register-0
+#define reg_glbl_soft_reg_1    (*(volatile uint32_t*)0x3002001C)  // reg_7 - Sof Register-1
+#define reg_glbl_soft_reg_2    (*(volatile uint32_t*)0x30020020)  // reg_8 - Sof Register-2
+#define reg_glbl_soft_reg_3    (*(volatile uint32_t*)0x30020024)  // reg_9 - Sof Register-3
+#define reg_glbl_soft_reg_4    (*(volatile uint32_t*)0x30020028)  // reg_10 - Sof Register-4
+#define reg_glbl_soft_reg_5    (*(volatile uint32_t*)0x3002002C)  // reg_11 - Sof Register-5
+
+#define reg_gpio_dsel         (*(volatile uint32_t*)0x30020040)  // reg_0  - GPIO Direction Select
+#define reg_gpio_type         (*(volatile uint32_t*)0x30020044)  // reg_1  - GPIO TYPE - Static/Waveform
+#define reg_gpio_idata        (*(volatile uint32_t*)0x30020048)  // reg_2  - GPIO Data In
+#define reg_gpio_odata        (*(volatile uint32_t*)0x3002004C)  // reg_3  - GPIO Data Out
+#define reg_gpio_intr_stat    (*(volatile uint32_t*)0x30020050)  // reg_4  - GPIO Interrupt status
+#define reg_gpio_intr_clr     (*(volatile uint32_t*)0x30020050)  // reg_5  - GPIO Interrupt Clear
+#define reg_gpio_intr_set     (*(volatile uint32_t*)0x30020054)  // reg_6 - GPIO Interrupt Set
+#define reg_gpio_intr_mask    (*(volatile uint32_t*)0x30020058)  // reg_7 - GPIO Interrupt Mask
+#define reg_gpio_pos_intr     (*(volatile uint32_t*)0x3002005C)  // reg_8 - GPIO Posedge Interrupt
+#define reg_gpio_neg_intr     (*(volatile uint32_t*)0x30020060)  // reg_9 - GPIO Neg Interrupt
+
+#define reg_pinmux_glbl_cfg   (*(volatile uint32_t*)0x30020080)  // reg_0 - PWM Reg-0
+#define reg_pinmux_cfg_pwm0   (*(volatile uint32_t*)0x30020084)  // reg_1 - PWM Reg-0
+#define reg_pinmux_cfg_pwm1   (*(volatile uint32_t*)0x30020088)  // reg_2 - PWM Reg-1
+#define reg_pinmux_cfg_pwm2   (*(volatile uint32_t*)0x3002008C)  // reg_3 - PWM Reg-2
+#define reg_pinmux_cfg_pwm3   (*(volatile uint32_t*)0x30020090)  // reg_4 - PWM Reg-3
+#define reg_pinmux_cfg_pwm4   (*(volatile uint32_t*)0x30020094)  // reg_5 - PWM Reg-4
+#define reg_pinmux_cfg_pwm5   (*(volatile uint32_t*)0x30020098)  // reg_6 - PWM Reg-5
+
+#define reg_timer_glbl_cfg    (*(volatile uint32_t*)0x300200C0)  // reg_0 - Global config
+#define reg_timer_cfg_timer0  (*(volatile uint32_t*)0x300200C4)  // reg_1 - Timer-0
+#define reg_timer_cfg_timer1  (*(volatile uint32_t*)0x300200C8)  // reg_2 - Timer-1
+#define reg_timer_cfg_timer2  (*(volatile uint32_t*)0x300200CC)  // reg_3 - Timer-2
+
+#define reg_sema_lock0        (*(volatile uint32_t*)0x30020100)  // reg_0  - Hardware Lock-0
+#define reg_sema_lock1        (*(volatile uint32_t*)0x30020104)  // reg_1  - Hardware Lock-1
+#define reg_sema_lock2        (*(volatile uint32_t*)0x30020108)  // reg_2  - Hardware Lock-2
+#define reg_sema_lock3        (*(volatile uint32_t*)0x3002010C)  // reg_3  - Hardware Lock-3
+#define reg_sema_lock4        (*(volatile uint32_t*)0x30020110)  // reg_4  - Hardware Lock-4
+#define reg_sema_lock5        (*(volatile uint32_t*)0x30020114)  // reg_5  - Hardware Lock-5
+#define reg_sema_lock6        (*(volatile uint32_t*)0x30020118)  // reg_6  - Hardware Lock-6
+#define reg_sema_lock7        (*(volatile uint32_t*)0x3002011C)  // reg_7  - Hardware Lock-7
+#define reg_sema_lock8        (*(volatile uint32_t*)0x30020120)  // reg_8  - Hardware Lock-8
+#define reg_sema_lock9        (*(volatile uint32_t*)0x30020124)  // reg_9  - Hardware Lock-9
+#define reg_sema_lock10       (*(volatile uint32_t*)0x30020128)  // reg_10 - Hardware Lock-10
+#define reg_sema_lock11       (*(volatile uint32_t*)0x3002012C)  // reg_11 - Hardware Lock-11
+#define reg_sema_lock12       (*(volatile uint32_t*)0x30020130)  // reg_12 - Hardware Lock-12
+#define reg_sema_lock13       (*(volatile uint32_t*)0x30020134)  // reg_13 - Hardware Lock-13
+#define reg_sema_lock14       (*(volatile uint32_t*)0x30020138)  // reg_14 - Hardware Lock-14
+#define reg_sema_lock_cfg     (*(volatile uint32_t*)0x3002013C)  // reg_15 - Hardware Lock config
+#define reg_sema_lock_stat    (*(volatile uint32_t*)0x3002013C)  // reg_15 - Hardware Lock Status
+
+
+#define reg_uart0_ctrl         (*(volatile uint32_t*)0x30010000)  // Reg-0
+#define reg_uart0_intr_stat    (*(volatile uint32_t*)0x30010004)  // Reg-1
+#define reg_uart0_baud_ctrl1   (*(volatile uint32_t*)0x30010008)  // Reg-2
+#define reg_uart0_baud_ctrl2   (*(volatile uint32_t*)0x3001000C)  // Reg-3
+#define reg_uart0_status       (*(volatile uint32_t*)0x30010010)  // Reg-4
+#define reg_uart0_txdata       (*(volatile uint32_t*)0x30010014)  // Reg-5
+#define reg_uart0_rxdata       (*(volatile uint32_t*)0x30010018)  // Reg-6
+#define reg_uart0_txfifo_stat  (*(volatile uint32_t*)0x3001001C)  // Reg-7
+#define reg_uart0_rxfifo_stat  (*(volatile uint32_t*)0x30010020)  // Reg-8
+
+#define reg_uart1_ctrl         (*(volatile uint32_t*)0x30010100)  // Reg-0
+#define reg_uart1_intr_stat    (*(volatile uint32_t*)0x30010104)  // Reg-1
+#define reg_uart1_baud_ctrl1   (*(volatile uint32_t*)0x30010108)  // Reg-2
+#define reg_uart1_baud_ctrl2   (*(volatile uint32_t*)0x3001010C)  // Reg-3
+#define reg_uart1_status       (*(volatile uint32_t*)0x30010110)  // Reg-4
+#define reg_uart1_txdata       (*(volatile uint32_t*)0x30010114)  // Reg-5
+#define reg_uart1_rxdata       (*(volatile uint32_t*)0x30010118)  // Reg-6
+#define reg_uart1_txfifo_stat  (*(volatile uint32_t*)0x3001011C)  // Reg-7
+#define reg_uart1_rxfifo_stat  (*(volatile uint32_t*)0x30010120)  // Reg-8
+
diff --git a/verilog/dv/c_func/inc/int_reg_map.h b/verilog/dv/c_func/inc/int_reg_map.h
new file mode 100644
index 0000000..669499d
--- /dev/null
+++ b/verilog/dv/c_func/inc/int_reg_map.h
@@ -0,0 +1,83 @@
+//--------------------------------------------------------------------
+// Register Address Map As Seen By the Internal RISCV Core
+//--------------------------------------------------------------------
+
+//-------------------------------------
+// PinMux Register
+// ------------------------------------
+#define reg_glbl_chip_id       (*(volatile uint32_t*)0x10020000)  // reg_0  - Chip ID
+#define reg_glbl_cfg0          (*(volatile uint32_t*)0x10020004)  // reg_1  - Global Config-0
+#define reg_glbl_cfg1          (*(volatile uint32_t*)0x10020008)  // reg_2  - Global Config-1
+#define reg_glbl_intr_msk      (*(volatile uint32_t*)0x1002000C)  // reg_3  - Global Interrupt Mask
+#define reg_glbl_intr          (*(volatile uint32_t*)0x10020010)  // reg_4  - Global Interrupt
+#define reg_glbl_multi_func    (*(volatile uint32_t*)0x10020014)  // reg_5 - GPIO Multi Function
+#define reg_glbl_soft_reg_0    (*(volatile uint32_t*)0x10020018)  // reg_6 - Soft Register-0
+#define reg_glbl_soft_reg_1    (*(volatile uint32_t*)0x1002001C)  // reg_7 - Sof Register-1
+#define reg_glbl_soft_reg_2    (*(volatile uint32_t*)0x10020020)  // reg_8 - Sof Register-2
+#define reg_glbl_soft_reg_3    (*(volatile uint32_t*)0x10020024)  // reg_9 - Sof Register-3
+#define reg_glbl_soft_reg_4    (*(volatile uint32_t*)0x10020028)  // reg_10 - Sof Register-4
+#define reg_glbl_soft_reg_5    (*(volatile uint32_t*)0x1002002C)  // reg_11 - Sof Register-5
+
+#define reg_gpio_dsel         (*(volatile uint32_t*)0x10020040)  // reg_0  - GPIO Direction Select
+#define reg_gpio_type         (*(volatile uint32_t*)0x10020044)  // reg_1  - GPIO TYPE - Static/Waveform
+#define reg_gpio_idata        (*(volatile uint32_t*)0x10020048)  // reg_2  - GPIO Data In
+#define reg_gpio_odata        (*(volatile uint32_t*)0x1002004C)  // reg_3  - GPIO Data Out
+#define reg_gpio_intr_stat    (*(volatile uint32_t*)0x10020050)  // reg_4  - GPIO Interrupt status
+#define reg_gpio_intr_clr     (*(volatile uint32_t*)0x10020050)  // reg_5  - GPIO Interrupt Clear
+#define reg_gpio_intr_set     (*(volatile uint32_t*)0x10020054)  // reg_6 - GPIO Interrupt Set
+#define reg_gpio_intr_mask    (*(volatile uint32_t*)0x10020058)  // reg_7 - GPIO Interrupt Mask
+#define reg_gpio_pos_intr     (*(volatile uint32_t*)0x1002005C)  // reg_8 - GPIO Posedge Interrupt
+#define reg_gpio_neg_intr     (*(volatile uint32_t*)0x10020060)  // reg_9 - GPIO Neg Interrupt
+
+#define reg_pinmux_glbl_cfg   (*(volatile uint32_t*)0x10020080)  // reg_0 - PWM Reg-0
+#define reg_pinmux_cfg_pwm0   (*(volatile uint32_t*)0x10020084)  // reg_1 - PWM Reg-0
+#define reg_pinmux_cfg_pwm1   (*(volatile uint32_t*)0x10020088)  // reg_2 - PWM Reg-1
+#define reg_pinmux_cfg_pwm2   (*(volatile uint32_t*)0x1002008C)  // reg_3 - PWM Reg-2
+#define reg_pinmux_cfg_pwm3   (*(volatile uint32_t*)0x10020090)  // reg_4 - PWM Reg-3
+#define reg_pinmux_cfg_pwm4   (*(volatile uint32_t*)0x10020094)  // reg_5 - PWM Reg-4
+#define reg_pinmux_cfg_pwm5   (*(volatile uint32_t*)0x10020098)  // reg_6 - PWM Reg-5
+
+#define reg_timer_glbl_cfg    (*(volatile uint32_t*)0x100200C0)  // reg_0 - Global config
+#define reg_timer_cfg_timer0  (*(volatile uint32_t*)0x100200C4)  // reg_1 - Timer-0
+#define reg_timer_cfg_timer1  (*(volatile uint32_t*)0x100200C8)  // reg_2 - Timer-1
+#define reg_timer_cfg_timer2  (*(volatile uint32_t*)0x100200CC)  // reg_3 - Timer-2
+
+#define reg_sema_lock0        (*(volatile uint32_t*)0x10020100)  // reg_0  - Hardware Lock-0
+#define reg_sema_lock1        (*(volatile uint32_t*)0x10020104)  // reg_1  - Hardware Lock-1
+#define reg_sema_lock2        (*(volatile uint32_t*)0x10020108)  // reg_2  - Hardware Lock-2
+#define reg_sema_lock3        (*(volatile uint32_t*)0x1002010C)  // reg_3  - Hardware Lock-3
+#define reg_sema_lock4        (*(volatile uint32_t*)0x10020110)  // reg_4  - Hardware Lock-4
+#define reg_sema_lock5        (*(volatile uint32_t*)0x10020114)  // reg_5  - Hardware Lock-5
+#define reg_sema_lock6        (*(volatile uint32_t*)0x10020118)  // reg_6  - Hardware Lock-6
+#define reg_sema_lock7        (*(volatile uint32_t*)0x1002011C)  // reg_7  - Hardware Lock-7
+#define reg_sema_lock8        (*(volatile uint32_t*)0x10020120)  // reg_8  - Hardware Lock-8
+#define reg_sema_lock9        (*(volatile uint32_t*)0x10020124)  // reg_9  - Hardware Lock-9
+#define reg_sema_lock10       (*(volatile uint32_t*)0x10020128)  // reg_10 - Hardware Lock-10
+#define reg_sema_lock11       (*(volatile uint32_t*)0x1002012C)  // reg_11 - Hardware Lock-11
+#define reg_sema_lock12       (*(volatile uint32_t*)0x10020130)  // reg_12 - Hardware Lock-12
+#define reg_sema_lock13       (*(volatile uint32_t*)0x10020134)  // reg_13 - Hardware Lock-13
+#define reg_sema_lock14       (*(volatile uint32_t*)0x10020138)  // reg_14 - Hardware Lock-14
+#define reg_sema_lock_cfg     (*(volatile uint32_t*)0x1002013C)  // reg_15 - Hardware Lock config
+#define reg_sema_lock_stat    (*(volatile uint32_t*)0x1002013C)  // reg_15 - Hardware Lock Status
+
+
+#define reg_uart0_ctrl         (*(volatile uint32_t*)0x10010000)  // Reg-0
+#define reg_uart0_intr_stat    (*(volatile uint32_t*)0x10010004)  // Reg-1
+#define reg_uart0_baud_ctrl1   (*(volatile uint32_t*)0x10010008)  // Reg-2
+#define reg_uart0_baud_ctrl2   (*(volatile uint32_t*)0x1001000C)  // Reg-3
+#define reg_uart0_status       (*(volatile uint32_t*)0x10010010)  // Reg-4
+#define reg_uart0_txdata       (*(volatile uint32_t*)0x10010014)  // Reg-5
+#define reg_uart0_rxdata       (*(volatile uint32_t*)0x10010018)  // Reg-6
+#define reg_uart0_txfifo_stat  (*(volatile uint32_t*)0x1001001C)  // Reg-7
+#define reg_uart0_rxfifo_stat  (*(volatile uint32_t*)0x10010020)  // Reg-8
+
+#define reg_uart1_ctrl         (*(volatile uint32_t*)0x10010100)  // Reg-0
+#define reg_uart1_intr_stat    (*(volatile uint32_t*)0x10010104)  // Reg-1
+#define reg_uart1_baud_ctrl1   (*(volatile uint32_t*)0x10010108)  // Reg-2
+#define reg_uart1_baud_ctrl2   (*(volatile uint32_t*)0x1001010C)  // Reg-3
+#define reg_uart1_status       (*(volatile uint32_t*)0x10010110)  // Reg-4
+#define reg_uart1_txdata       (*(volatile uint32_t*)0x10010114)  // Reg-5
+#define reg_uart1_rxdata       (*(volatile uint32_t*)0x10010118)  // Reg-6
+#define reg_uart1_txfifo_stat  (*(volatile uint32_t*)0x1001011C)  // Reg-7
+#define reg_uart1_rxfifo_stat  (*(volatile uint32_t*)0x10010120)  // Reg-8
+
diff --git a/verilog/dv/c_func/inc/user_reg_map.h b/verilog/dv/c_func/inc/user_reg_map.h
deleted file mode 100644
index 4508fb2..0000000
--- a/verilog/dv/c_func/inc/user_reg_map.h
+++ /dev/null
@@ -1,38 +0,0 @@
-
-
-//-------------------------------------
-// PinMux Register
-// ------------------------------------
-#define reg_pinmux_chip_id           (*(volatile uint32_t*)0x30020000)  // reg_0  - Chip ID
-#define reg_pinmux_gbl_cfg0          (*(volatile uint32_t*)0x30020004)  // reg_1  - Global Config-2
-#define reg_pinmux_gbl_cfg1          (*(volatile uint32_t*)0x30020008)  // reg_2  - Global Config-1
-#define reg_pinmux_gbl_intr_msk      (*(volatile uint32_t*)0x3002000C)  // reg_3  - Global Interrupt Mask
-#define reg_pinmux_gbl_intr          (*(volatile uint32_t*)0x30020010)  // reg_4  - Global Interrupt
-#define reg_pinmux_gpio_idata        (*(volatile uint32_t*)0x30020014)  // reg_5  - GPIO Data In
-#define reg_pinmux_gpio_odata        (*(volatile uint32_t*)0x30020018)  // reg_6  - GPIO Data Out
-#define reg_pinmux_gpio_dsel         (*(volatile uint32_t*)0x3002001C)  // reg_7  - GPIO Direction Select
-#define reg_pinmux_gpio_type         (*(volatile uint32_t*)0x30020020)  // reg_8  - GPIO TYPE - Static/Waveform
-#define reg_pinmux_gpio_intr_stat    (*(volatile uint32_t*)0x30020024)  // reg_9  - GPIO Interrupt status
-#define reg_pinmux_gpio_intr_clr     (*(volatile uint32_t*)0x30020024)  // reg_9  - GPIO Interrupt Clear
-#define reg_pinmux_gpio_intr_set     (*(volatile uint32_t*)0x30020028)  // reg_10 - GPIO Interrupt Set
-#define reg_pinmux_gpio_intr_mask    (*(volatile uint32_t*)0x3002002C)  // reg_11 - GPIO Interrupt Mask
-#define reg_pinmux_gpio_pos_intr     (*(volatile uint32_t*)0x30020030)  // reg_12 - GPIO Posedge Interrupt
-#define reg_pinmux_gpio_neg_intr     (*(volatile uint32_t*)0x30020034)  // reg_13 - GPIO Neg Interrupt
-#define reg_pinmux_gpio_multi_func   (*(volatile uint32_t*)0x30020038)  // reg_14 - GPIO Multi Function
-#define reg_pinmux_soft_reg_0        (*(volatile uint32_t*)0x3002003C)  // reg_15 - Soft Register
-#define reg_pinmux_cfg_pwm0          (*(volatile uint32_t*)0x30020040)  // reg_16 - PWM Reg-0
-#define reg_pinmux_cfg_pwm1          (*(volatile uint32_t*)0x30020044)  // reg_17 - PWM Reg-1
-#define reg_pinmux_cfg_pwm2          (*(volatile uint32_t*)0x30020048)  // reg_18 - PWM Reg-2
-#define reg_pinmux_cfg_pwm3          (*(volatile uint32_t*)0x3002004C)  // reg_19 - PWM Reg-3
-#define reg_pinmux_cfg_pwm4          (*(volatile uint32_t*)0x30020050)  // reg_20 - PWM Reg-4
-#define reg_pinmux_cfg_pwm5          (*(volatile uint32_t*)0x30020054)  // reg_21 - PWM Reg-5
-#define reg_pinmux_soft_reg_1        (*(volatile uint32_t*)0x30020058)  // reg_22 - Sof Register
-#define reg_pinmux_soft_reg_2        (*(volatile uint32_t*)0x3002005C)  // reg_23 - Sof Register
-#define reg_pinmux_soft_reg_3        (*(volatile uint32_t*)0x30020060)  // reg_24 - Sof Register
-#define reg_pinmux_soft_reg_4        (*(volatile uint32_t*)0x30020064)  // reg_25 - Sof Register
-#define reg_pinmux_soft_reg_5        (*(volatile uint32_t*)0x30020068)  // reg_26 - Sof Register
-#define reg_pinmux_soft_reg_6        (*(volatile uint32_t*)0x3002006C)  // reg_27 - Sof Register
-#define reg_pinmux_cfg_timer0        (*(volatile uint32_t*)0x30020070)  // reg_28 - Timer-0
-#define reg_pinmux_cfg_timer1        (*(volatile uint32_t*)0x30020074)  // reg_28 - Timer-1
-#define reg_pinmux_cfg_timer2        (*(volatile uint32_t*)0x30020078)  // reg_28 - Timer-2
-
diff --git a/verilog/dv/common/riscduino_board b/verilog/dv/common/riscduino_board
index 5888540..09f42e8 160000
--- a/verilog/dv/common/riscduino_board
+++ b/verilog/dv/common/riscduino_board
@@ -1 +1 @@
-Subproject commit 5888540bf2ae57d8c0326778a6d0c25b6ef95d35
+Subproject commit 09f42e80c78b05785fb7088fb3bff16b2044c6c8
diff --git a/verilog/dv/firmware/sc_print.c b/verilog/dv/firmware/sc_print.c
index b736d42..f2a1192 100644
--- a/verilog/dv/firmware/sc_print.c
+++ b/verilog/dv/firmware/sc_print.c
@@ -20,16 +20,37 @@
 #include <stdarg.h>
 #include "sc_print.h"
 
-#define SC_SIM_OUTPORT (0xf0000000)
-#define CHAR_BIT (8)
+#define SC_SIM_OUTPORT            (0xf0000000)
+#define REG_MPRJ_UART_CTRL        (0x10010000)
+#define REG_MPRJ_UART_INTR_STAT   (0x10010004)
+#define REG_MPRJ_UART_BAUD_CTRL1  (0x10010008)
+#define REG_MPRJ_UART_BAUD_CTRL2  (0x1001000C)
+#define REG_MPRJ_UART_STAT        (0x10010010)
+#define REG_MPRJ_UART_TXDATA      (0x10010014)
+#define REG_MPRJ_UART_RXDATA      (0x10010018)
+#define REG_MPRJ_UART_TFIFO_STAT  (0x1001001C)
+#define REG_MPRJ_UART_RFIFO_STAT  (0x10010020)
 
-static void
-sc_puts(long str, long strlen) {
+#define CHAR_BIT (8)
+/**
+static void sc_puts(long str, long strlen) {
 	volatile char *out_ptr = (volatile char*)SC_SIM_OUTPORT;
 	const char *in_ptr = (const char*)str;
 	for (long len = strlen; len > 0; --len)
 	  *out_ptr = *in_ptr++;
 }
+**/
+static void sc_puts(long str, long strlen) {
+	volatile char *out_ptr = (volatile char*)REG_MPRJ_UART_TXDATA;
+	volatile char *status  = (volatile char*)REG_MPRJ_UART_STAT;
+	const char *in_ptr = (const char*)str;
+	for (long len = strlen; len > 0; --len) {
+	  //if((*status & 0x1) != 0x1) {  // check UART TX fifo is not full
+	   *out_ptr = *in_ptr++;
+          //}
+	}
+
+}
 
 #undef putchar
 int
diff --git a/verilog/dv/risc_boot/Makefile b/verilog/dv/risc_boot/Makefile
index a4e04d4..2601fc5 100644
--- a/verilog/dv/risc_boot/Makefile
+++ b/verilog/dv/risc_boot/Makefile
@@ -53,7 +53,7 @@
 
 export TOOLS     ?=  /opt/riscv32i 
 export GCC_PATH  ?=  $(TOOLS)/bin
-export GCC_PREFIX?=    riscv32-unknown-linux-gnu
+GCC_PREFIX?=riscv32-unknown-elf
 
 
 ############## USER SPECIFIC DEFINE ##################
diff --git a/verilog/dv/risc_boot/risc_boot.c b/verilog/dv/risc_boot/risc_boot.c
index 00d308d..8ff48ff 100644
--- a/verilog/dv/risc_boot/risc_boot.c
+++ b/verilog/dv/risc_boot/risc_boot.c
@@ -160,11 +160,11 @@
 
 
     // Remove All Reset
-    reg_pinmux_gbl_cfg0 = 0x11F;
+    reg_glbl_cfg0 = 0x11F;
 
     // Enable UART Multi Functional Ports
 
-    reg_pinmux_gpio_multi_func = 0x100;
+    reg_glbl_multi_func = 0x100;
 
     // configure the user uart
     reg_mprj_uart_reg0  = 0x7;
diff --git a/verilog/dv/risc_boot/user_uart.dump b/verilog/dv/risc_boot/user_uart.dump
new file mode 100644
index 0000000..4d5b8b2
--- /dev/null
+++ b/verilog/dv/risc_boot/user_uart.dump
@@ -0,0 +1,212 @@
+
+user_uart.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <SIM_EXIT-0xf4>:
+	...
+
+000000f4 <SIM_EXIT>:
+  f4:	00000013          	nop
+
+000000f8 <SIM_STOP>:
+  f8:	0000006f          	j	f8 <SIM_STOP>
+  fc:	ffff                	0xffff
+  fe:	ffff                	0xffff
+
+Disassembly of section .text:
+
+00000100 <machine_trap_entry-0xc0>:
+	...
+
+000001c0 <machine_trap_entry>:
+ 1c0:	1200006f          	j	2e0 <trap_entry>
+ 1c4:	00000013          	nop
+ 1c8:	00000013          	nop
+ 1cc:	00000013          	nop
+ 1d0:	00000013          	nop
+ 1d4:	00000013          	nop
+ 1d8:	00000013          	nop
+ 1dc:	00000013          	nop
+ 1e0:	00000013          	nop
+ 1e4:	00000013          	nop
+ 1e8:	00000013          	nop
+ 1ec:	00000013          	nop
+ 1f0:	00000013          	nop
+ 1f4:	00000013          	nop
+ 1f8:	00000013          	nop
+ 1fc:	00000013          	nop
+
+00000200 <_start>:
+ 200:	00000093          	li	ra,0
+ 204:	00000113          	li	sp,0
+ 208:	00000193          	li	gp,0
+ 20c:	00000213          	li	tp,0
+ 210:	00000293          	li	t0,0
+ 214:	00000313          	li	t1,0
+ 218:	00000393          	li	t2,0
+ 21c:	00000413          	li	s0,0
+ 220:	00000493          	li	s1,0
+ 224:	00000513          	li	a0,0
+ 228:	00000593          	li	a1,0
+ 22c:	00000613          	li	a2,0
+ 230:	00000693          	li	a3,0
+ 234:	00000713          	li	a4,0
+ 238:	00000793          	li	a5,0
+ 23c:	00000813          	li	a6,0
+ 240:	00000893          	li	a7,0
+ 244:	00000913          	li	s2,0
+ 248:	00000993          	li	s3,0
+ 24c:	00000a13          	li	s4,0
+ 250:	00000a93          	li	s5,0
+ 254:	00000b13          	li	s6,0
+ 258:	00000b93          	li	s7,0
+ 25c:	00000c13          	li	s8,0
+ 260:	00000c93          	li	s9,0
+ 264:	00000d13          	li	s10,0
+ 268:	00000d93          	li	s11,0
+ 26c:	00000e13          	li	t3,0
+ 270:	00000e93          	li	t4,0
+ 274:	00000f13          	li	t5,0
+ 278:	00000f93          	li	t6,0
+ 27c:	08000197          	auipc	gp,0x8000
+ 280:	58418193          	addi	gp,gp,1412 # 8000800 <__global_pointer$>
+ 284:	08000597          	auipc	a1,0x8000
+ 288:	d7c58593          	addi	a1,a1,-644 # 8000000 <__BSS_START__>
+ 28c:	08000617          	auipc	a2,0x8000
+ 290:	d7460613          	addi	a2,a2,-652 # 8000000 <__BSS_START__>
+ 294:	a021                	j	29c <_start+0x9c>
+ 296:	0005a023          	sw	zero,0(a1)
+ 29a:	0591                	addi	a1,a1,4
+ 29c:	fec59de3          	bne	a1,a2,296 <_start+0x96>
+ 2a0:	0c480117          	auipc	sp,0xc480
+ 2a4:	56010113          	addi	sp,sp,1376 # c480800 <__C_STACK_TOP__>
+ 2a8:	0c4902b7          	lui	t0,0xc490
+ 2ac:	4305                	li	t1,1
+ 2ae:	0062a023          	sw	t1,0(t0) # c490000 <__C_STACK_TOP__+0xf800>
+ 2b2:	0c4902b7          	lui	t0,0xc490
+ 2b6:	00428293          	addi	t0,t0,4 # c490004 <__C_STACK_TOP__+0xf804>
+ 2ba:	06300313          	li	t1,99
+ 2be:	0062a023          	sw	t1,0(t0)
+ 2c2:	0c4902b7          	lui	t0,0xc490
+ 2c6:	01028293          	addi	t0,t0,16 # c490010 <__C_STACK_TOP__+0xf810>
+ 2ca:	537d                	li	t1,-1
+ 2cc:	0062a023          	sw	t1,0(t0)
+ 2d0:	0062a223          	sw	t1,4(t0)
+ 2d4:	4501                	li	a0,0
+ 2d6:	4581                	li	a1,0
+ 2d8:	0a8000ef          	jal	ra,380 <main>
+ 2dc:	0c40006f          	j	3a0 <sc_exit>
+
+000002e0 <trap_entry>:
+ 2e0:	716d                	addi	sp,sp,-272
+ 2e2:	c206                	sw	ra,4(sp)
+ 2e4:	c40a                	sw	sp,8(sp)
+ 2e6:	c60e                	sw	gp,12(sp)
+ 2e8:	c812                	sw	tp,16(sp)
+ 2ea:	ca16                	sw	t0,20(sp)
+ 2ec:	cc1a                	sw	t1,24(sp)
+ 2ee:	ce1e                	sw	t2,28(sp)
+ 2f0:	d022                	sw	s0,32(sp)
+ 2f2:	d226                	sw	s1,36(sp)
+ 2f4:	d42a                	sw	a0,40(sp)
+ 2f6:	d62e                	sw	a1,44(sp)
+ 2f8:	d832                	sw	a2,48(sp)
+ 2fa:	da36                	sw	a3,52(sp)
+ 2fc:	dc3a                	sw	a4,56(sp)
+ 2fe:	de3e                	sw	a5,60(sp)
+ 300:	c0c2                	sw	a6,64(sp)
+ 302:	c2c6                	sw	a7,68(sp)
+ 304:	c4ca                	sw	s2,72(sp)
+ 306:	c6ce                	sw	s3,76(sp)
+ 308:	c8d2                	sw	s4,80(sp)
+ 30a:	cad6                	sw	s5,84(sp)
+ 30c:	ccda                	sw	s6,88(sp)
+ 30e:	cede                	sw	s7,92(sp)
+ 310:	d0e2                	sw	s8,96(sp)
+ 312:	d2e6                	sw	s9,100(sp)
+ 314:	d4ea                	sw	s10,104(sp)
+ 316:	d6ee                	sw	s11,108(sp)
+ 318:	d8f2                	sw	t3,112(sp)
+ 31a:	daf6                	sw	t4,116(sp)
+ 31c:	dcfa                	sw	t5,120(sp)
+ 31e:	defe                	sw	t6,124(sp)
+ 320:	34202573          	csrr	a0,mcause
+ 324:	341025f3          	csrr	a1,mepc
+ 328:	860a                	mv	a2,sp
+ 32a:	048000ef          	jal	ra,372 <handle_trap>
+ 32e:	4092                	lw	ra,4(sp)
+ 330:	4122                	lw	sp,8(sp)
+ 332:	41b2                	lw	gp,12(sp)
+ 334:	4242                	lw	tp,16(sp)
+ 336:	42d2                	lw	t0,20(sp)
+ 338:	4362                	lw	t1,24(sp)
+ 33a:	43f2                	lw	t2,28(sp)
+ 33c:	5402                	lw	s0,32(sp)
+ 33e:	5492                	lw	s1,36(sp)
+ 340:	5522                	lw	a0,40(sp)
+ 342:	55b2                	lw	a1,44(sp)
+ 344:	5642                	lw	a2,48(sp)
+ 346:	56d2                	lw	a3,52(sp)
+ 348:	5762                	lw	a4,56(sp)
+ 34a:	57f2                	lw	a5,60(sp)
+ 34c:	4806                	lw	a6,64(sp)
+ 34e:	4896                	lw	a7,68(sp)
+ 350:	4926                	lw	s2,72(sp)
+ 352:	49b6                	lw	s3,76(sp)
+ 354:	4a46                	lw	s4,80(sp)
+ 356:	4ad6                	lw	s5,84(sp)
+ 358:	4b66                	lw	s6,88(sp)
+ 35a:	4bf6                	lw	s7,92(sp)
+ 35c:	5c06                	lw	s8,96(sp)
+ 35e:	5c96                	lw	s9,100(sp)
+ 360:	5d26                	lw	s10,104(sp)
+ 362:	5db6                	lw	s11,108(sp)
+ 364:	5e46                	lw	t3,112(sp)
+ 366:	5ed6                	lw	t4,116(sp)
+ 368:	5f66                	lw	t5,120(sp)
+ 36a:	5ff6                	lw	t6,124(sp)
+ 36c:	6151                	addi	sp,sp,272
+ 36e:	30200073          	mret
+
+00000372 <handle_trap>:
+ 372:	d83ff06f          	j	f4 <SIM_EXIT>
+	...
+
+00000380 <main>:
+ 380:	10010737          	lui	a4,0x10010
+ 384:	531c                	lw	a5,32(a4)
+ 386:	dffd                	beqz	a5,384 <main+0x4>
+ 388:	01872283          	lw	t0,24(a4) # 10010018 <__C_STACK_TOP__+0x3b8f818>
+ 38c:	00572a23          	sw	t0,20(a4)
+ 390:	bfd5                	j	384 <main+0x4>
+	...
+
+000003a0 <sc_exit>:
+ 3a0:	00000297          	auipc	t0,0x0
+ 3a4:	d5428293          	addi	t0,t0,-684 # f4 <SIM_EXIT>
+ 3a8:	8282                	jr	t0
+ 3aa:	00000013          	nop
+ 3ae:	00000013          	nop
+ 3b2:	00000013          	nop
+ 3b6:	00000013          	nop
+ 3ba:	00000013          	nop
+ 3be:	0001                	nop
+	...
+
+Disassembly of section .stack:
+
+0c480400 <__C_STACK_TOP__-0x400>:
+	...
+
+Disassembly of section .comment:
+
+00000000 <.comment>:
+   0:	3a434347          	fmsub.d	ft6,ft6,ft4,ft7,rmm
+   4:	2820                	fld	fs0,80(s0)
+   6:	29554e47          	fmsub.s	ft8,fa0,fs5,ft5,rmm
+   a:	3620                	fld	fs0,104(a2)
+   c:	312e                	fld	ft2,232(sp)
+   e:	302e                	fld	ft0,232(sp)
+	...
diff --git a/verilog/dv/riscv_regress/Makefile b/verilog/dv/riscv_regress/Makefile
index 609b7fe..d52ebf4 100644
--- a/verilog/dv/riscv_regress/Makefile
+++ b/verilog/dv/riscv_regress/Makefile
@@ -16,7 +16,7 @@
 export USER_PROJECT_VERILOG ?=  $(DESIGNS)/verilog
 ## YIFIVE FIRMWARE
 YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
-GCC_PREFIX?=riscv32-unknown-elf
+GCC_PREFIX?=riscv64-unknown-elf
 
 
 ## Simulation mode: RTL/GL
@@ -158,7 +158,7 @@
 todo_list    := $(bld_dir)/todo.txt
 
 # Environment
-export CROSS_PREFIX  ?= riscv32-unknown-elf-
+export CROSS_PREFIX  ?= riscv64-unknown-elf-
 export RISCV_GCC     ?= $(CROSS_PREFIX)gcc
 export RISCV_OBJDUMP ?= $(CROSS_PREFIX)objdump -D
 export RISCV_OBJCOPY ?= $(CROSS_PREFIX)objcopy -O verilog
diff --git a/verilog/dv/riscv_regress/tests/isr_sample/timer.h b/verilog/dv/riscv_regress/tests/isr_sample/timer.h
index 827b849..c306b2f 100644
--- a/verilog/dv/riscv_regress/tests/isr_sample/timer.h
+++ b/verilog/dv/riscv_regress/tests/isr_sample/timer.h
@@ -78,7 +78,7 @@
 .macro _run_timer
     li          TMP, MEM_MTIME_CTRL
     lw          TMP2, 0(TMP)
-    li          TMP3, (1 << YCR1_MTIME_CTRL_EN)
+    li          TMP3, (1 << YCR_MTIME_CTRL_EN)
     or          TMP2, TMP2, TMP3
     sw          TMP2, 0(TMP)
 .endm
@@ -86,7 +86,7 @@
 .macro _stop_timer
     li          TMP, MEM_MTIME_CTRL
     lw          TMP2, 0(TMP)
-    li          TMP3, (1 << YCR1_MTIME_CTRL_EN)
+    li          TMP3, (1 << YCR_MTIME_CTRL_EN)
     not         TMP3, TMP3
     and         TMP2, TMP2, TMP3
     sw          TMP2, 0(TMP)
diff --git a/verilog/dv/riscv_regress/user_risc_regress_tb.v b/verilog/dv/riscv_regress/user_risc_regress_tb.v
index ceaec71..e444404 100644
--- a/verilog/dv/riscv_regress/user_risc_regress_tb.v
+++ b/verilog/dv/riscv_regress/user_risc_regress_tb.v
@@ -291,7 +291,7 @@
 	        repeat (2) @(posedge clock);
 		#1;
 		// Remove WB and SPI Reset, Keep SDARM and CORE under Reset
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h01F);
+                wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F);
 
 		// CS#2 Switch to QSPI Mode
                 wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
@@ -305,10 +305,10 @@
 		// Remove all the reset
                if(d_risc_id == 0) begin
                     $display("STATUS: Working with Risc core 0");
-                    wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
+                    wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
                end else begin
                     $display("STATUS: Working with Risc core 1");
-                    wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
+                    wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
                end
 
 	end
diff --git a/verilog/dv/uart_master/Makefile b/verilog/dv/uart_master/Makefile
index 7bcd2b7..3ec839e 100644
--- a/verilog/dv/uart_master/Makefile
+++ b/verilog/dv/uart_master/Makefile
@@ -51,15 +51,12 @@
 ## Compiler Information 
 #######################################################################
 
-export GCC_PATH?=      $(TOOLS)/bin
-export GCC_PREFIX?=    riscv32-unknown-linux-gnu
+export TOOLS     ?=  /opt/riscv32i 
+export GCC_PATH  ?=  $(TOOLS)/bin
+GCC_PREFIX?=riscv32-unknown-elf
 
 
-############## USER SPECIFIC DEFINE ##################
 
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
-
-######################################################
 
 
 
@@ -153,28 +150,30 @@
 ##############################################################################
 
 %.vvp: %_tb.v %.hex
+
+## RTL
 ifeq ($(SIM),RTL)
    ifeq ($(DUMP),OFF)
-	iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+	iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
         -f$(VERILOG_PATH)/includes/includes.rtl.caravel \
         -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $<
     else  
-	iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+	iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
         -f$(VERILOG_PATH)/includes/includes.rtl.caravel \
         -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $<
    endif
-endif 
+endif
 
-## GL
+##GL
 ifeq ($(SIM),GL)
-    ifeq ($(CONFIG),caravel_user_project)
-		iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+   ifeq ($(DUMP),OFF)
+	iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
         -f$(VERILOG_PATH)/includes/includes.gl.caravel \
         -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $<
     else
-		iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
-        -f$(VERILOG_PATH)/includes/includes.gl.$(CONFIG) \
-		-f$(CARAVEL_PATH)/gl/__user_project_wrapper.v -o $@ $<
+	iverilog -Ttyp -DWFDUMP -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
+        -f$(VERILOG_PATH)/includes/includes.gl.caravel \
+        -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $<
     endif
 endif 
 
@@ -223,3 +222,9 @@
 	\rm  -f *.elf *.hex *.bin *.vvp *.log *.vcd *.lst *.hexe
 
 .PHONY: clean hex all
+
+
+
+
+
+
diff --git a/verilog/dv/uart_master/uart_master_tb.v b/verilog/dv/uart_master/uart_master_tb.v
index 2b021ee..f49daab 100644
--- a/verilog/dv/uart_master/uart_master_tb.v
+++ b/verilog/dv/uart_master/uart_master_tb.v
@@ -138,19 +138,19 @@
            $display("Monitor: Writing  expected value");
            
            test_fail = 0;
-           uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,32'h11223344);
-           uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,32'h22334455);
-           uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,32'h33445566);
-           uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,32'h44556677);
-           uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,32'h55667788);
-           uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,32'h66778899);
+           uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,32'h11223344);
+           uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,32'h22334455);
+           uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,32'h33445566);
+           uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,32'h44556677);
+           uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,32'h55667788);
+           uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,32'h66778899);
 
-           uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,32'h11223344);
-           uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,32'h22334455);
-           uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,32'h33445566);
-           uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,32'h44556677);
-           uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,32'h55667788);
-           uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,32'h66778899);
+           uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,32'h11223344);
+           uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,32'h22334455);
+           uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,32'h33445566);
+           uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,32'h44556677);
+           uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,32'h55667788);
+           uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,32'h66778899);
 
            $display("###################################################");
            if(test_fail == 0) begin
diff --git a/verilog/dv/user_aes/user_aes.c b/verilog/dv/user_aes/user_aes.c
index f78b8fe..cd1bfec 100644
--- a/verilog/dv/user_aes/user_aes.c
+++ b/verilog/dv/user_aes/user_aes.c
@@ -40,36 +40,20 @@
 static int test_decrypt_ecb(void);
 static void test_encrypt_ecb_verbose(void);
 
-#define reg_mprj_globl_reg0  (*(volatile uint32_t*)0x10020000)
-#define reg_mprj_globl_reg1  (*(volatile uint32_t*)0x10020004)
-#define reg_mprj_globl_reg2  (*(volatile uint32_t*)0x10020008)
-#define reg_mprj_globl_reg3  (*(volatile uint32_t*)0x1002000C)
-#define reg_mprj_globl_reg4  (*(volatile uint32_t*)0x10020010)
-#define reg_mprj_globl_reg5  (*(volatile uint32_t*)0x10020014)
-#define reg_mprj_globl_reg6  (*(volatile uint32_t*)0x10020018)
-#define reg_mprj_globl_reg7  (*(volatile uint32_t*)0x1002001C)
-#define reg_mprj_globl_reg8  (*(volatile uint32_t*)0x10020020)
-#define reg_mprj_globl_reg9  (*(volatile uint32_t*)0x10020024)
-#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x10020028)
-#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x1002002C)
-#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x10020030)
-#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x10020034)
-#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x10020038)
-#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x1002003C)
-#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x10020040)
-#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x10020044)
-#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x10020048)
-#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x1002004C)
-#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x10020050)
-#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x10020054)
-#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x10020058)
-#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x1002005C)
-#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x10020060)
-#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x10020064)
-#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x10020068)
-#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x1002006C)
+#define reg_mprj_globl_reg0  (*(volatile uint32_t*)0x10020000) // Chip ID
+#define reg_mprj_globl_reg1  (*(volatile uint32_t*)0x10020004) // Global Config-0
+#define reg_mprj_globl_reg2  (*(volatile uint32_t*)0x10020008) // Global Config-1
+#define reg_mprj_globl_reg3  (*(volatile uint32_t*)0x1002000C) // Global Interrupt Mask
+#define reg_mprj_globl_reg4  (*(volatile uint32_t*)0x10020010) // Global Interrupt
+#define reg_mprj_globl_reg5  (*(volatile uint32_t*)0x10020014) // Multi functional sel
+#define reg_mprj_globl_soft0  (*(volatile uint32_t*)0x10020018) // Sof Register-0
+#define reg_mprj_globl_soft1  (*(volatile uint32_t*)0x1002001C) // Sof Register-1
+#define reg_mprj_globl_soft2  (*(volatile uint32_t*)0x10020020) // Sof Register-2
+#define reg_mprj_globl_soft3  (*(volatile uint32_t*)0x10020024) // Sof Register-3
+#define reg_mprj_globl_soft4 (*(volatile uint32_t*)0x10020028) // Sof Register-4
+#define reg_mprj_globl_soft5 (*(volatile uint32_t*)0x1002002C) // Sof Register-5
 
-#define reg_mprg_pinmux_gpio_odata (*(volatile uint32_t*)0x10020018)
+#define reg_mprg_gpio_odata (*(volatile uint32_t*)0x1002004C)
 
 int main(void)
 {
@@ -86,34 +70,34 @@
     return 0;
 #endif
 
-    reg_mprg_pinmux_gpio_odata  = 0x00000100; 
-    reg_mprj_globl_reg23  = 0x00000000; 
+    reg_mprg_gpio_odata  = 0x00000100; 
+    reg_mprj_globl_soft0  = 0x00000000; 
     exit = test_encrypt_cbc();
-    reg_mprg_pinmux_gpio_odata  = 0x00000200; 
-    reg_mprj_globl_reg23  = exit;
+    reg_mprg_gpio_odata  = 0x00000200; 
+    reg_mprj_globl_soft0  = exit;
     exit += test_decrypt_cbc();
-    reg_mprg_pinmux_gpio_odata  = 0x00000300; 
-    reg_mprj_globl_reg23  = exit;
+    reg_mprg_gpio_odata  = 0x00000300; 
+    reg_mprj_globl_soft0  = exit;
     exit += test_encrypt_ctr();
-    reg_mprg_pinmux_gpio_odata  = 0x00000400; 
-    reg_mprj_globl_reg23  = exit;
+    reg_mprg_gpio_odata  = 0x00000400; 
+    reg_mprj_globl_soft0  = exit;
     exit += test_decrypt_ctr();
-    reg_mprg_pinmux_gpio_odata  = 0x00000500; 
-    reg_mprj_globl_reg23  = exit;
+    reg_mprg_gpio_odata  = 0x00000500; 
+    reg_mprj_globl_soft0  = exit;
     exit += test_decrypt_ecb();
-    reg_mprg_pinmux_gpio_odata  = 0x00000600; 
-    reg_mprj_globl_reg23  = exit;
+    reg_mprg_gpio_odata  = 0x00000600; 
+    reg_mprj_globl_soft0  = exit;
     exit += test_encrypt_ecb();
-    reg_mprg_pinmux_gpio_odata  = 0x00000700; 
-    reg_mprj_globl_reg23  = exit;
+    reg_mprg_gpio_odata  = 0x00000700; 
+    reg_mprj_globl_soft0  = exit;
     test_encrypt_ecb_verbose();
-    reg_mprg_pinmux_gpio_odata  = 0x00000800; 
-    reg_mprj_globl_reg23  = exit;
+    reg_mprg_gpio_odata  = 0x00000800; 
+    reg_mprj_globl_soft0  = exit;
 
     if(exit == 0) {
-        reg_mprg_pinmux_gpio_odata  = 0x00001800; 
+        reg_mprg_gpio_odata  = 0x00001800; 
     } else {
-        reg_mprg_pinmux_gpio_odata  = 0x0000A800; 
+        reg_mprg_gpio_odata  = 0x0000A800; 
     }
 
     return exit;
diff --git a/verilog/dv/user_aes/user_aes_tb.v b/verilog/dv/user_aes/user_aes_tb.v
index 3c46014..8d236d4 100644
--- a/verilog/dv/user_aes/user_aes_tb.v
+++ b/verilog/dv/user_aes/user_aes_tb.v
@@ -183,17 +183,17 @@
                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
 
                // Enable UART Multi Functional Ports
-               wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h100);
+               wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h100);
                
                repeat (2) @(posedge clock);
                #1;
 		// Remove all the reset
 		if(d_risc_id == 0) begin
 		     $display("STATUS: Working with Risc core 0");
-                     wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
+                     wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
 		end else if(d_risc_id == 1) begin
 		     $display("STATUS: Working with Risc core 1");
-                     wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
+                     wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
 		end 
 
                repeat (100) @(posedge clock);  // wait for Processor Get Ready
@@ -204,9 +204,9 @@
                                               uart_stick_parity, uart_timeout, uart_divisor);
 
 		// Set the PORT-B Direction as Output
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_DSEL,'h0000FF00);
+                wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_DSEL,'h0000FF00);
 		// Set the GPIO Output data: 0x00000000
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_ODATA,'h0000000);
+                wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_ODATA,'h0000000);
    
                fork
 	          begin
@@ -217,7 +217,7 @@
 	          end
                join_any
 	
-	       wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h00000000);
+	       wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h00000000);
 
                $display("###################################################");
                if(test_fail == 0) begin
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
index bcd24cd..5f1c60b 100644
--- a/verilog/dv/user_basic/user_basic_tb.v
+++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -150,10 +150,10 @@
 	`ifdef WFDUMP
 	   initial begin
 	   	$dumpfile("simx.vcd");
-	   	$dumpvars(0, user_basic_tb);
+	   	$dumpvars(1, user_basic_tb);
 	   	//$dumpvars(1, user_basic_tb.u_top);
 	   	//$dumpvars(0, user_basic_tb.u_top.u_pll);
-	   	//$dumpvars(1, user_basic_tb.u_top.u_wb_host);
+	   	$dumpvars(0, user_basic_tb.u_top.u_wb_host);
 	   	//$dumpvars(1, user_basic_tb.u_top.u_intercon);
 	   	//$dumpvars(1, user_basic_tb.u_top.u_intercon);
 	   	//$dumpvars(1, user_basic_tb.u_top.u_pinmux);
@@ -167,10 +167,6 @@
 	end
 
 
-// Hook to pll clock
-wire pll_clock = u_top.u_wb_host.u_clkbuf_pll.X;
-
-
 initial
 begin
 
@@ -244,35 +240,37 @@
 	  test_step = 10;
           wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h63,8'h69,8'hFF,8'h64});
 	  clock_monitor(5*CLK2_PERIOD,11*CLK2_PERIOD,257*CLK2_PERIOD,6*CLK2_PERIOD);
-  
-         $display("###################################################");
-         $display("Monitor: Checking the PLL:");
-         $display("###################################################");
+ 
+     `ifndef GL  
+     $display("###################################################");
+     $display("Monitor: Checking the PLL:");
+     $display("###################################################");
 	 test_step = 11;
 	 // Set PLL enable, no DCO mode ; Set PLL output divider to 0x03
-         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0000,8'h2});
-         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b0,5'h3,26'h00000});
-         repeat (100) @(posedge clock);
+     wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0000,8'h2});
+     wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b0,5'h3,26'h00000});
+     repeat (100) @(posedge clock);
 	 pll_clock_monitor(5);
 
 	 test_step = 12;
 	 // Set PLL enable, DCO mode ; Set PLL output divider to 0x01
-         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b000,4'b0000,8'h2});
-         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b1,5'h0,26'h0000});
-         repeat (100) @(posedge clock);
+     wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b000,4'b0000,8'h2});
+     wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b1,5'h0,26'h0000});
+     repeat (100) @(posedge clock);
 	 pll_clock_monitor(4);
 
-         $display("###################################################");
-         $display("Monitor: Monitor Clock output:");
-         $display("###################################################");
+     $display("###################################################");
+     $display("Monitor: Monitor Clock output:");
+     $display("###################################################");
 	 $display("Monitor: CPU: CLOCK2/(2+3), USB: CLOCK2/(2+9), RTC: CLOCK2/(2+255), WBS:CLOCK2/(2+4)");
 	 test_step = 13;
-         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h63,8'h69,8'hFF,8'h64});
+     wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h63,8'h69,8'hFF,8'h64});
 
 	 // Set PLL enable, DCO mode ; Set PLL output divider to 0x01
-         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b000,4'b0000,8'h2});
-         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b1,5'h0,26'h0000});
+     wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b000,4'b0000,8'h2});
+     wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b1,5'h0,26'h0000});
 	 dbg_clk_monitor(79,60,5*CLK2_PERIOD,11*CLK2_PERIOD,257*CLK2_PERIOD,6*CLK2_PERIOD);
+     `endif
          
 	 $display("###################################################");
          $display("Monitor: Checking the chip signature :");
@@ -281,9 +279,9 @@
          // Remove Wb/PinMux Reset
          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
 
-	 wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h8273_8343);
-	 wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h2007_2022);
-	 wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h0004_8000);
+	 wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h8273_8343);
+	 wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,32'h1508_2022);
+	 wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,32'h0005_0000);
 
       end
    
@@ -347,7 +345,7 @@
  
 
     // IOs
-    .io_in          (io_in)  ,
+    .io_in          ('h0)  ,
     .io_out         (io_out) ,
     .io_oeb         (io_oeb) ,
 
@@ -391,7 +389,12 @@
 task pll_clock_monitor;
 input [15:0] exp_period;
 begin
-   force clock_mon = u_top.u_wb_host.u_clkbuf_pll.X;
+   //force clock_mon = u_top.u_wb_host.pll_clk_out[0];
+   `ifdef GL
+      force clock_mon = u_top.u_wb_host.pll_clk_out[0];
+    `else
+      force clock_mon = u_top.u_wb_host.u_clkbuf_pll.X;
+    `endif
    check_clock_period("PLL CLock",exp_period);
    release clock_mon;
 end
diff --git a/verilog/dv/user_cache_bypass/user_cache_bypass.c b/verilog/dv/user_cache_bypass/user_cache_bypass.c
index 9c99cd9..a3e9b0d 100644
--- a/verilog/dv/user_cache_bypass/user_cache_bypass.c
+++ b/verilog/dv/user_cache_bypass/user_cache_bypass.c
@@ -19,42 +19,28 @@
 #define uint32_t  long
 #define uint16_t  int
 
-#define reg_mprj_globl_reg0  (*(volatile uint32_t*)0x10020000)
-#define reg_mprj_globl_reg1  (*(volatile uint32_t*)0x10020004)
-#define reg_mprj_globl_reg2  (*(volatile uint32_t*)0x10020008)
-#define reg_mprj_globl_reg3  (*(volatile uint32_t*)0x1002000C)
-#define reg_mprj_globl_reg4  (*(volatile uint32_t*)0x10020010)
-#define reg_mprj_globl_reg5  (*(volatile uint32_t*)0x10020014)
-#define reg_mprj_globl_reg6  (*(volatile uint32_t*)0x10020018)
-#define reg_mprj_globl_reg7  (*(volatile uint32_t*)0x1002001C)
-#define reg_mprj_globl_reg8  (*(volatile uint32_t*)0x10020020)
-#define reg_mprj_globl_reg9  (*(volatile uint32_t*)0x10020024)
-#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x10020028)
-#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x1002002C)
-#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x10020030)
-#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x10020034)
-#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x10020038)
-#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x1002003C)
-#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x10020040)
-#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x10020044)
-#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x10020048)
-#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x1002004C)
-#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x10020050)
-#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x10020054)
-#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x10020058)
-#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x1002005C)
-#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x10020060)
-#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x10020064)
-#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x10020068)
-#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x1002006C)
+#define reg_mprj_globl_reg0  (*(volatile uint32_t*)0x10020000) // Chip ID
+#define reg_mprj_globl_reg1  (*(volatile uint32_t*)0x10020004) // Global Config-0
+#define reg_mprj_globl_reg2  (*(volatile uint32_t*)0x10020008) // Global Config-1
+#define reg_mprj_globl_reg3  (*(volatile uint32_t*)0x1002000C) // Global Interrupt Mask
+#define reg_mprj_globl_reg4  (*(volatile uint32_t*)0x10020010) // Global Interrupt
+#define reg_mprj_globl_reg5  (*(volatile uint32_t*)0x10020014) // Multi functional sel
+#define reg_mprj_globl_soft0  (*(volatile uint32_t*)0x10020018) // Sof Register-0
+#define reg_mprj_globl_soft1  (*(volatile uint32_t*)0x1002001C) // Sof Register-1
+#define reg_mprj_globl_soft2  (*(volatile uint32_t*)0x10020020) // Sof Register-2
+#define reg_mprj_globl_soft3  (*(volatile uint32_t*)0x10020024) // Sof Register-3
+#define reg_mprj_globl_soft4 (*(volatile uint32_t*)0x10020028) // Sof Register-4
+#define reg_mprj_globl_soft5 (*(volatile uint32_t*)0x1002002C) // Sof Register-5
+
+
 // -------------------------------------------------------------------------
 // Test copying code into SRAM and running it from there.
 // -------------------------------------------------------------------------
 
 void test_function()
 {
-    reg_mprj_globl_reg24  = 0x33445566;  // Sig-3
-    reg_mprj_globl_reg25  = 0x44556677;  // Sig-4
+    reg_mprj_globl_soft2  = 0x33445566;  // Sig-2
+    reg_mprj_globl_soft3  = 0x44556677;  // Sig-3
 
     return;
 }
@@ -69,18 +55,18 @@
     src_ptr = &test_function;
     dst_ptr = func;
 
-    reg_mprj_globl_reg22  = 0x11223344;  // Sig-1
+    reg_mprj_globl_soft0  = 0x11223344;  // Sig-0
     while (src_ptr < &main) {
 	*(dst_ptr++) = *(src_ptr++);
     }
 
     // Call the routine in SRAM
-    reg_mprj_globl_reg23  = 0x22334455;  // Sig-2
+    reg_mprj_globl_soft1  = 0x22334455;  // Sig-1
     
     ((void(*)())func)();
 
-    reg_mprj_globl_reg26 = 0x55667788; 
-    reg_mprj_globl_reg27 = 0x66778899; 
+    reg_mprj_globl_soft4 = 0x55667788; 
+    reg_mprj_globl_soft5 = 0x66778899; 
 
     // Signal end of test
 }
diff --git a/verilog/dv/user_cache_bypass/user_cache_bypass_tb.v b/verilog/dv/user_cache_bypass/user_cache_bypass_tb.v
index c5d1478..45a24d3 100644
--- a/verilog/dv/user_cache_bypass/user_cache_bypass_tb.v
+++ b/verilog/dv/user_cache_bypass/user_cache_bypass_tb.v
@@ -135,15 +135,15 @@
 	        repeat (2) @(posedge clock);
 		#1;
 		// Set the icahce and dcache bypass
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG1,{4'b0,2'b11,2'b00,8'b0,16'b0});
+                wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG1,{4'b0,2'b11,2'b00,8'b0,16'b0});
 
 		// Remove all the reset
 		if(d_risc_id == 0) begin
 		     $display("STATUS: Working with Risc core 0");
-                     wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
+                     wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
 		end else begin
 		     $display("STATUS: Working with Risc core 1");
-                     wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
+                     wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
 		end
 
 
@@ -165,12 +165,12 @@
                 // 0x3000002C = 0x66778899; 
 
                 test_fail = 0;
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h11223344);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h22334455);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h33445566);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32'h44556677);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32'h55667788);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32'h66778899);
+		wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h11223344);
+		wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,32'h22334455);
+		wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,32'h33445566);
+		wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,read_data,32'h44556677);
+		wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,read_data,32'h55667788);
+		wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,read_data,32'h66778899);
 
 
 	   
diff --git a/verilog/dv/user_gpio/user_gpio_tb.v b/verilog/dv/user_gpio/user_gpio_tb.v
index 5a30dd9..0451459 100644
--- a/verilog/dv/user_gpio/user_gpio_tb.v
+++ b/verilog/dv/user_gpio/user_gpio_tb.v
@@ -217,7 +217,7 @@
 
 	/*****************************/
 
-	wire [15:0] irq_lines = u_top.u_pinmux.u_pinmux_reg.irq_lines;
+	wire [15:0] irq_lines = u_top.u_pinmux.u_glbl_reg.irq_lines;
 
 	initial begin
 		clock = 0;
@@ -252,34 +252,34 @@
                 wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
 
                 // Disable Multi func
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h000);
+                wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h000);
 
 		/************* GPIO As Output ******************/
 		$display("#####################################");
 		$display("Step-1: Testing GPIO As Output ");
 		// Set the Direction as Output
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_DSEL,'hFFFFFFFF);
+                wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_DSEL,'hFFFFFFFF);
 		// Set the GPIO Output data: 0x55555555
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_ODATA,'h55555555);
+                wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_ODATA,'h55555555);
 		cmp_gpio_output(8'h55,8'h55,8'h55,8'h55);
 
 		// Set the GPIO Output data: 0xAAAAAAAA
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_ODATA,'hAAAAAAAA);
+                wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_ODATA,'hAAAAAAAA);
 		cmp_gpio_output(8'hAA,8'hAA,8'hAA,8'hAA);
 
 		// Set the GPIO Output data: 0x5A5A5A5A5A5A
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_ODATA,'h5A5A5A5A);
+                wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_ODATA,'h5A5A5A5A);
 		cmp_gpio_output(8'h5A,8'h5A,8'h5A,8'h5A);
 		
 		// Set the GPIO Output data: 0xA5A5A5A5A5A5
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_ODATA,'hA5A5A5A5);
+                wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_ODATA,'hA5A5A5A5);
 		cmp_gpio_output(8'hA5,8'hA5,8'hA5,8'hA5);
 
 		/************* GPIO As Input ******************/
 		$display("#####################################");
 		$display("Step-2: Testing GPIO As Input ");
 		// Set the Direction as Input
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_DSEL,'h00000000);
+                wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_DSEL,'h00000000);
 
 		cmp_gpio_input(8'h55,8'h55,8'h55,8'h55);
 		cmp_gpio_input(8'hAA,8'hAA,8'hAA,8'hAA);
@@ -290,12 +290,12 @@
 		$display("#####################################");
 		$display("Step-3: Testing GPIO As Posedge Interrupt ");
 		// Set the Direction as Input
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_DSEL,'h00000000);
+                wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_DSEL,'h00000000);
 		// Set GPIO for posedge Interrupt
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_MASK,'hFFFFFFFF);
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_POS_INTR,'hFFFFFFFF);
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_NEG_INTR,'h00000000);
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR_MSK,'hFFFF);
+                wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_MASK,'hFFFFFFFF);
+                wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_POS_INTR_SEL,'hFFFFFFFF);
+                wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_NEG_INTR_SEL,'h00000000);
+                wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_MSK,'hFFFF);
 		
 		// Drive GPIO with 0x55
 		cmp_gpio_pos_intr(8'h55,8'h55,8'h55,8'h55);
@@ -314,12 +314,12 @@
 		$display("#####################################");
 		$display("Step-3: Testing GPIO As Negedge Interrupt ");
 		// Set the Direction as Input
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_DSEL,'h00000000);
+                wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_DSEL,'h00000000);
 		// Set GPIO for negedge Interrupt
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_MASK,'hFFFFFFFF);
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_POS_INTR,'h00000000);
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_NEG_INTR,'hFFFFFFFF);
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR_MSK,'hFFFF);
+                wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_MASK,'hFFFFFFFF);
+                wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_POS_INTR_SEL,'h00000000);
+                wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_NEG_INTR_SEL,'hFFFFFFFF);
+                wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_MSK,'hFFFF);
 		
 		// Drive GPIO with 0x55
 		cmp_gpio_neg_intr(8'h55,8'h55,8'h55,8'h55);
@@ -506,7 +506,7 @@
     port_c_out  = port_c;
     port_d_out  = port_d;
 
-    wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_IDATA,read_data,{port_d,port_c & 8'h7F,port_b,8'h0});
+    wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_IDATA,read_data,{port_d,port_c & 8'h7F,port_b,8'h0});
 end
 endtask
 
@@ -523,12 +523,12 @@
     cmp_gpio_input(8'h00,8'h00,8'h00,8'h00);
 
     // Clear Global Interrupt
-    wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,'h00008000);
+    wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,'h00008000);
 
    // Clear all the Interrupt
-    wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_CLR,'hFFFFFFFF);
+    wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_CLR,'hFFFFFFFF);
 
-    wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_STAT,read_data,32'h0);
+    wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_STAT,read_data,32'h0);
 
     // Drive Ports
     cmp_gpio_input(port_d,port_c,port_b,port_a);
@@ -544,10 +544,10 @@
     repeat (20) @(posedge clock); 
 
     // Check the GPIO Interrupt
-    wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_STAT,read_data,{port_d,port_c & 8'h7F,port_b,8'h0});
+    wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_STAT,read_data,{port_d,port_c & 8'h7F,port_b,8'h0});
     
     // Check The Global Interrupt
-    wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data,32'h8000);
+    wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,32'h8000);
     
     if(irq_lines[15] != 1'b1) begin
 	$display("ERROR: Global GPIO Interrupt not detected");
@@ -555,15 +555,15 @@
     end
 
     // Clear The GPIO Interrupt
-    wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_CLR,32'hFFFFFFFF);
+    wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_CLR,32'hFFFFFFFF);
 
     // Clear GPIO Interrupt
-    wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,'h8000);
+    wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,'h8000);
 
 
     // Check Interrupt are cleared
-    wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data,32'h0);
-    wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_STAT,read_data,32'h0);
+    wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,32'h0);
+    wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_STAT,read_data,32'h0);
     if(irq_lines[15] != 1'b0) begin
 	$display("ERROR: Global GPIO Interrupt is not cleared");
        `TB_GLBL.test_fail = 1;
@@ -584,11 +584,11 @@
     cmp_gpio_input(8'hFF,8'hFF,8'hFF,8'hFF);
 
     // Clear Global Interrupt
-    wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,'h00008000);
+    wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,'h00008000);
 
    // Clear all the Interrupt
-    wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_CLR,'hFFFFFFFF);
-    wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_STAT,read_data,32'h0);
+    wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_CLR,'hFFFFFFFF);
+    wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_STAT,read_data,32'h0);
 
     // Drive Ports
     cmp_gpio_input(port_d,port_c,port_b,port_a);
@@ -603,10 +603,10 @@
     repeat (20) @(posedge clock); 
 
     // Neg edge interrupt is will compliment  of input value
-    wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_STAT,read_data,{port_d ^ 8'hFF,(port_c ^ 8'hFF) & 8'h7F,port_b ^ 8'hFF,8'h0});
+    wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_STAT,read_data,{port_d ^ 8'hFF,(port_c ^ 8'hFF) & 8'h7F,port_b ^ 8'hFF,8'h0});
     
     // Check The Global Interrupt
-    wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data,32'h8000);
+    wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,32'h8000);
 
     if(irq_lines[15] != 1'b1) begin
 	$display("ERROR: Global GPIO Interrupt not detected");
@@ -614,14 +614,14 @@
     end
 
     // Clear The GPIO Interrupt
-    wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_CLR,32'hFFFFFFFF);
+    wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_CLR,32'hFFFFFFFF);
 
     // Clear GPIO Interrupt
-    wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,'h8000);
+    wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,'h8000);
 
     // Check Interrupt are cleared
-    wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data,32'h0);
-    wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_STAT,read_data,32'h0);
+    wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,32'h0);
+    wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_STAT,read_data,32'h0);
 
     if(irq_lines[15] != 1'b0) begin
 	$display("ERROR: Global GPIO Interrupt is not cleared");
diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v
index e41e0d2..87b94a3 100644
--- a/verilog/dv/user_i2cm/user_i2cm_tb.v
+++ b/verilog/dv/user_i2cm/user_i2cm_tb.v
@@ -146,10 +146,10 @@
    wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h01);
 
    // Enable I2C Multi Functional Ports
-   wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h8000);
+   wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h8000);
 
    // Remove i2m reset
-   wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h010);
+   wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h010);
 
    repeat (100) @(posedge clock);  
 
diff --git a/verilog/dv/user_mcore/Makefile b/verilog/dv/user_mcore_test1/Makefile
similarity index 89%
copy from verilog/dv/user_mcore/Makefile
copy to verilog/dv/user_mcore_test1/Makefile
index f635413..9aa71f1 100644
--- a/verilog/dv/user_mcore/Makefile
+++ b/verilog/dv/user_mcore_test1/Makefile
@@ -43,7 +43,7 @@
 
 .SUFFIXES:
 
-PATTERN = user_mcore
+PATTERN = user_mcore_test1
 
 all:  ${PATTERN:=.vcd}
 
@@ -51,13 +51,13 @@
 vvp:  ${PATTERN:=.vvp}
 
 %.vvp: %_tb.v
-	${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -c -I./ -I$(YIFIVE_FIRMWARE_PATH)  user_mcore.c -o user_mcore.o
+	${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -c -I./ -I$(YIFIVE_FIRMWARE_PATH)  ${PATTERN}.c -o ${PATTERN}.o
 	${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -c -I./ -I$(YIFIVE_FIRMWARE_PATH)  $(YIFIVE_FIRMWARE_PATH)/common_bthread.c -o common_bthread.o
 	${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH)  $(YIFIVE_FIRMWARE_PATH)/crt.S -o crt.o
-	${GCC_PREFIX}-gcc -o user_mcore.elf -T $(YIFIVE_FIRMWARE_PATH)/link.ld user_mcore.o crt.o common_bthread.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N
-	${GCC_PREFIX}-objcopy -O verilog user_mcore.elf user_mcore.hex
-	${GCC_PREFIX}-objdump -D user_mcore.elf > user_mcore.dump
-	rm crt.o user_mcore.o
+	${GCC_PREFIX}-gcc -o ${PATTERN}.elf -T $(YIFIVE_FIRMWARE_PATH)/link.ld ${PATTERN}.o crt.o common_bthread.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N
+	${GCC_PREFIX}-objcopy -O verilog ${PATTERN}.elf ${PATTERN}.hex
+	${GCC_PREFIX}-objdump -D ${PATTERN}.elf > ${PATTERN}.dump
+	rm crt.o ${PATTERN}.o
 ifeq ($(SIM),RTL)
    ifeq ($(DUMP),OFF)
 	iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
diff --git a/verilog/dv/user_mcore/user_mcore.c b/verilog/dv/user_mcore_test1/user_mcore_test1.c
similarity index 66%
rename from verilog/dv/user_mcore/user_mcore.c
rename to verilog/dv/user_mcore_test1/user_mcore_test1.c
index 4a5e14d..a77f439 100644
--- a/verilog/dv/user_mcore/user_mcore.c
+++ b/verilog/dv/user_mcore_test1/user_mcore_test1.c
@@ -24,34 +24,18 @@
 #define uint16_t  int
 #define size      10
 
-#define reg_mprj_globl_reg0  (*(volatile uint32_t*)0x10020000)
-#define reg_mprj_globl_reg1  (*(volatile uint32_t*)0x10020004)
-#define reg_mprj_globl_reg2  (*(volatile uint32_t*)0x10020008)
-#define reg_mprj_globl_reg3  (*(volatile uint32_t*)0x1002000C)
-#define reg_mprj_globl_reg4  (*(volatile uint32_t*)0x10020010)
-#define reg_mprj_globl_reg5  (*(volatile uint32_t*)0x10020014)
-#define reg_mprj_globl_reg6  (*(volatile uint32_t*)0x10020018)
-#define reg_mprj_globl_reg7  (*(volatile uint32_t*)0x1002001C)
-#define reg_mprj_globl_reg8  (*(volatile uint32_t*)0x10020020)
-#define reg_mprj_globl_reg9  (*(volatile uint32_t*)0x10020024)
-#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x10020028)
-#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x1002002C)
-#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x10020030)
-#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x10020034)
-#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x10020038)
-#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x1002003C)
-#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x10020040)
-#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x10020044)
-#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x10020048)
-#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x1002004C)
-#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x10020050)
-#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x10020054)
-#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x10020058)
-#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x1002005C)
-#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x10020060)
-#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x10020064)
-#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x10020068)
-#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x1002006C)
+#define reg_mprj_globl_reg0  (*(volatile uint32_t*)0x10020000) // Chip ID
+#define reg_mprj_globl_reg1  (*(volatile uint32_t*)0x10020004) // Global Config-0
+#define reg_mprj_globl_reg2  (*(volatile uint32_t*)0x10020008) // Global Config-1
+#define reg_mprj_globl_reg3  (*(volatile uint32_t*)0x1002000C) // Global Interrupt Mask
+#define reg_mprj_globl_reg4  (*(volatile uint32_t*)0x10020010) // Global Interrupt
+#define reg_mprj_globl_reg5  (*(volatile uint32_t*)0x10020014) // Multi functional sel
+#define reg_mprj_globl_soft0  (*(volatile uint32_t*)0x10020018) // Sof Register-0
+#define reg_mprj_globl_soft1  (*(volatile uint32_t*)0x1002001C) // Sof Register-1
+#define reg_mprj_globl_soft2  (*(volatile uint32_t*)0x10020020) // Sof Register-2
+#define reg_mprj_globl_soft3  (*(volatile uint32_t*)0x10020024) // Sof Register-3
+#define reg_mprj_globl_soft4 (*(volatile uint32_t*)0x10020028) // Sof Register-4
+#define reg_mprj_globl_soft5 (*(volatile uint32_t*)0x1002002C) // Sof Register-5
 // -------------------------------------------------------------------------
 // Multi-core test, Two Array is filled with below data, destination hold sum
 //      source           result            remark
@@ -124,12 +108,12 @@
        arg_t arg0 = { dest, src0, src1, 0, buf_size/2 };
        arg_t arg1 = { dest, src0, src1, buf_size/2, buf_size };
 
-       reg_mprj_globl_reg22  = 0x11223344;  // Sig-1
+       reg_mprj_globl_soft0  = 0x11223344;  // Sig-0
        // Initialize bare threads (bthread).
        bthread_init();
       
       
-       reg_mprj_globl_reg23  = 0x22334455;  // Sig-2
+       reg_mprj_globl_soft1  = 0x22334455;  // Sig-1
        // Start counting stats.
        //test_stats_on();
       
@@ -137,18 +121,18 @@
        // Spawn work onto core 1
        bthread_spawn( 1, &vvadd_mt, &arg1 );
       
-       reg_mprj_globl_reg24  = 0x33445566;  // Sig-3
+       reg_mprj_globl_soft2  = 0x33445566;  // Sig-2
        // Have core 0 also do some work.
        vvadd_mt(&arg0);
       
-       reg_mprj_globl_reg25  = 0x44556677;  // Sig-4
+       reg_mprj_globl_soft3  = 0x44556677;  // Sig-3
        // Wait for core 1 to finish.
        bthread_join(1);
 
 
        // Stop counting stats
        //test_stats_off();
-       reg_mprj_globl_reg26 = 0x55667788;  // sig-5
+       reg_mprj_globl_soft4 = 0x55667788;  // sig-4
       
        // Core 0 will verify the results.
        if ( bthread_get_core_id() == 0 ) {
@@ -159,7 +143,7 @@
             	test_pass &= 0;
            }
 	   if(test_pass == 0x1) {
-               reg_mprj_globl_reg27 = 0x66778899;  // sig-6
+               reg_mprj_globl_soft5 = 0x66778899;  // sig-5
 	   }
 
        }
diff --git a/verilog/dv/user_mcore/user_mcore_tb.v b/verilog/dv/user_mcore_test1/user_mcore_test1_tb.v
similarity index 94%
rename from verilog/dv/user_mcore/user_mcore_tb.v
rename to verilog/dv/user_mcore_test1/user_mcore_test1_tb.v
index b43dcba..a4bda85 100644
--- a/verilog/dv/user_mcore/user_mcore_tb.v
+++ b/verilog/dv/user_mcore_test1/user_mcore_test1_tb.v
@@ -65,7 +65,11 @@
 `timescale 1 ns / 1 ns
 
 `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
-module user_mcore_tb;
+
+`define TB_HEX_FILE "user_mcore_test1.hex"
+`define TB_TOP    user_mcore_test1_tb
+
+module `TB_TOP;
 	reg clock;
 	reg wb_rst_i;
 	reg power1, power2;
@@ -115,9 +119,9 @@
 	`ifdef WFDUMP
 	   initial begin
 	   	$dumpfile("simx.vcd");
-	   	$dumpvars(1, user_mcore_tb);
-	   	$dumpvars(1, user_mcore_tb.u_top);
-	   	$dumpvars(0, user_mcore_tb.u_top.u_riscv_top);
+	   	$dumpvars(1, `TB_TOP);
+	   	$dumpvars(1, `TB_TOP.u_top);
+	   	$dumpvars(0, `TB_TOP.u_top.u_riscv_top);
 	   end
        `endif
 
@@ -136,11 +140,11 @@
 		#1;
 		// Remove all the reset
 		$display("STATUS: Working with Both core Risc core 0 & 1 ");
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h31F);
+                wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h31F);
 
 
 		// Repeat cycles of 1000 clock edges as needed to complete testbench
-		repeat (22) begin
+		repeat (23) begin
 			repeat (1000) @(posedge clock);
 			// $display("+1000 cycles");
 		end
@@ -157,12 +161,12 @@
                 // 0x3000002C = 0x66778899; 
 
                 test_fail = 0;
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h11223344);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h22334455);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h33445566);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32'h44556677);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32'h55667788);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32'h66778899);
+		wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h11223344);
+		wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,32'h22334455);
+		wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,32'h33445566);
+		wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,read_data,32'h44556677);
+		wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,read_data,32'h55667788);
+		wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,read_data,32'h66778899);
 
 
 	   
@@ -257,7 +261,7 @@
    assign io_in[32] = flash_io3;
 
    // Quard flash
-     s25fl256s #(.mem_file_name("user_mcore.hex"),
+     s25fl256s #(.mem_file_name(`TB_HEX_FILE),
 	         .otp_file_name("none"),
                  .TimingModel("S25FL512SAGMFI010_F_30pF")) 
 		 u_spi_flash_256mb (
diff --git a/verilog/dv/user_mcore/Makefile b/verilog/dv/user_mcore_test2/Makefile
similarity index 89%
rename from verilog/dv/user_mcore/Makefile
rename to verilog/dv/user_mcore_test2/Makefile
index f635413..1c301e2 100644
--- a/verilog/dv/user_mcore/Makefile
+++ b/verilog/dv/user_mcore_test2/Makefile
@@ -43,7 +43,7 @@
 
 .SUFFIXES:
 
-PATTERN = user_mcore
+PATTERN = user_mcore_test2
 
 all:  ${PATTERN:=.vcd}
 
@@ -51,13 +51,13 @@
 vvp:  ${PATTERN:=.vvp}
 
 %.vvp: %_tb.v
-	${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -c -I./ -I$(YIFIVE_FIRMWARE_PATH)  user_mcore.c -o user_mcore.o
+	${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -c -I./ -I$(YIFIVE_FIRMWARE_PATH)  ${PATTERN}.c -o ${PATTERN}.o
 	${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -c -I./ -I$(YIFIVE_FIRMWARE_PATH)  $(YIFIVE_FIRMWARE_PATH)/common_bthread.c -o common_bthread.o
 	${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH)  $(YIFIVE_FIRMWARE_PATH)/crt.S -o crt.o
-	${GCC_PREFIX}-gcc -o user_mcore.elf -T $(YIFIVE_FIRMWARE_PATH)/link.ld user_mcore.o crt.o common_bthread.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N
-	${GCC_PREFIX}-objcopy -O verilog user_mcore.elf user_mcore.hex
-	${GCC_PREFIX}-objdump -D user_mcore.elf > user_mcore.dump
-	rm crt.o user_mcore.o
+	${GCC_PREFIX}-gcc -o ${PATTERN}.elf -T $(YIFIVE_FIRMWARE_PATH)/link.ld ${PATTERN}.o crt.o common_bthread.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N
+	${GCC_PREFIX}-objcopy -O verilog ${PATTERN}.elf ${PATTERN}.hex
+	${GCC_PREFIX}-objdump -D ${PATTERN}.elf > ${PATTERN}.dump
+	rm crt.o ${PATTERN}.o
 ifeq ($(SIM),RTL)
    ifeq ($(DUMP),OFF)
 	iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
diff --git a/verilog/dv/user_mcore_test2/user_mcore_test2.c b/verilog/dv/user_mcore_test2/user_mcore_test2.c
new file mode 100644
index 0000000..4ba53eb
--- /dev/null
+++ b/verilog/dv/user_mcore_test2/user_mcore_test2.c
@@ -0,0 +1,110 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#include "common_misc.h"
+#include "common_bthread.h"
+#include "../c_func/inc/int_reg_map.h"
+
+#define SC_SIM_OUTPORT (0xf0000000)
+#define uint32_t  long
+#define uint16_t  int
+#define size      10
+
+  print_message(const char *fmt) {
+      char ch;
+     // Wait for Semaphore-lock=0
+     while((reg_sema_lock0 & 0x1) == 0x0);
+     while(ch = *(unsigned char *)fmt) {
+
+        while((reg_uart0_status & 0x1) == 0x1);
+
+	    reg_uart0_txdata = ch;
+        ++fmt;
+     }
+     // Release Semaphore Lock
+     reg_sema_lock0 = 0x1;
+
+    // Added nop to Semaphore to acquire by other core
+    asm ("nop");
+    asm ("nop");
+    asm ("nop");
+    asm ("nop");
+
+
+  }
+
+
+ int main( int argc, char* argv[] )
+ {
+      char ch;
+
+       // Common Sub-Routine 
+       if ( bthread_get_core_id() == 0 ) {
+
+         // Enable the GPIO UART I/F
+         reg_glbl_multi_func = 0x100;
+
+         // Enable the UART TX/RX & STOP=2
+         reg_uart0_ctrl = 0x7;
+         // 1152000 Baud at 50Mhz System clock
+         reg_uart0_baud_ctrl1 = 0x0;
+         reg_uart0_baud_ctrl2 = 0x0;
+
+         reg_glbl_soft_reg_5 = 0x1; // Test Start Indication
+       }
+       // Core 0 thread
+       if ( bthread_get_core_id() == 0 ) {
+         print_message("UART command-0 from core-0\n");
+         print_message("UART command-1 from core-0\n");
+         print_message("UART command-2 from core-0\n");
+         print_message("UART command-3 from core-0\n");
+
+       }
+       // Core 1 thread
+       if ( bthread_get_core_id() == 1 ) {
+
+         while((reg_glbl_soft_reg_5 & 0x1) == 0x0); // wait for test start
+         print_message("UART command-0 from core-1\n");
+         print_message("UART command-1 from core-1\n");
+         print_message("UART command-2 from core-1\n");
+         print_message("UART command-3 from core-1\n");
+
+       }
+       // Core 2 thread
+       if ( bthread_get_core_id() == 2 ) {
+         while((reg_glbl_soft_reg_5 & 0x1) == 0x0); // wait for test start
+         print_message("UART command-0 from core-2\n");
+         print_message("UART command-1 from core-2\n");
+         print_message("UART command-2 from core-2\n");
+         print_message("UART command-3 from core-2\n");
+
+       }
+       // Core 3 thread
+       if ( bthread_get_core_id() == 3 ) {
+         while((reg_glbl_soft_reg_5 & 0x1) == 0x0); // wait for test start
+         print_message("UART command-0 from core-3\n");
+         print_message("UART command-1 from core-3\n");
+         print_message("UART command-2 from core-3\n");
+         print_message("UART command-3 from core-3\n");
+
+       }
+      
+       return 0;
+ }
+
+
diff --git a/verilog/dv/user_mcore/user_mcore_tb.v b/verilog/dv/user_mcore_test2/user_mcore_test2_tb.v
similarity index 68%
copy from verilog/dv/user_mcore/user_mcore_tb.v
copy to verilog/dv/user_mcore_test2/user_mcore_test2_tb.v
index b43dcba..7ee2ba2 100644
--- a/verilog/dv/user_mcore/user_mcore_tb.v
+++ b/verilog/dv/user_mcore_test2/user_mcore_test2_tb.v
@@ -65,7 +65,12 @@
 `timescale 1 ns / 1 ns
 
 `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
-module user_mcore_tb;
+`include "uart_agent.v"
+
+`define TB_HEX_FILE "user_mcore_test2.hex"
+`define TB_TOP    user_mcore_test2_tb
+
+module `TB_TOP;
 	reg clock;
 	reg wb_rst_i;
 	reg power1, power2;
@@ -90,38 +95,105 @@
 	wire gpio;
 	wire [37:0] mprj_io;
 	wire [7:0] mprj_io_0;
-	reg         test_fail;
+	reg        test_fail;
+	reg        test_start;
 	reg [31:0] read_data;
+        //----------------------------------
+        // Uart Configuration
+        // ---------------------------------
+        reg [1:0]      uart_data_bit        ;
+        reg	       uart_stop_bits       ; // 0: 1 stop bit; 1: 2 stop bit;
+        reg	       uart_stick_parity    ; // 1: force even parity
+        reg	       uart_parity_en       ; // parity enable
+        reg	       uart_even_odd_parity ; // 0: odd parity; 1: even parity
+        
+        reg [7:0]      uart_data            ;
+        reg [15:0]     uart_divisor         ;	// divided by n * 16
+        reg [15:0]     uart_timeout         ;// wait time limit
+        
+        reg [15:0]     uart_rx_nu           ;
+        reg [15:0]     uart_tx_nu           ;
+        reg [7:0]      uart_write_data [0:39];
+        reg 	       uart_fifo_enable     ;	// fifo mode disable
+	reg            flag                 ;
+
+	reg [31:0]     check_sum            ;
+        
 	integer    d_risc_id;
 
+         integer i,j;
 
 
 	// External clock is used by default.  Make this artificially fast for the
 	// simulation.  Normally this would be a slow clock and the digital PLL
 	// would be the fast clock.
 
-	always #12.5 clock <= (clock === 1'b0);
+
+	// 50Mhz CLock
+	always #10 clock <= (clock === 1'b0);
 
 	initial begin
-		clock = 0;
-                wbd_ext_cyc_i ='h0;  // strobe/request
-                wbd_ext_stb_i ='h0;  // strobe/request
-                wbd_ext_adr_i ='h0;  // address
-                wbd_ext_we_i  ='h0;  // write
-                wbd_ext_dat_i ='h0;  // data output
-                wbd_ext_sel_i ='h0;  // byte enable
+		clock         = 0;
+        test_start    = 0;
+	    flag          = 0;
+        wbd_ext_cyc_i ='h0;  // strobe/request
+        wbd_ext_stb_i ='h0;  // strobe/request
+        wbd_ext_adr_i ='h0;  // address
+        wbd_ext_we_i  ='h0;  // write
+        wbd_ext_dat_i ='h0;  // data output
+        wbd_ext_sel_i ='h0;  // byte enable
 	end
 
 	`ifdef WFDUMP
 	   initial begin
 	   	$dumpfile("simx.vcd");
-	   	$dumpvars(1, user_mcore_tb);
-	   	$dumpvars(1, user_mcore_tb.u_top);
-	   	$dumpvars(0, user_mcore_tb.u_top.u_riscv_top);
+	   	$dumpvars(1, `TB_TOP);
+	   	$dumpvars(0, `TB_TOP.tb_uart);
+	   	$dumpvars(1, `TB_TOP.u_top);
+	   	$dumpvars(0, `TB_TOP.u_top.u_riscv_top);
+	   	$dumpvars(0, `TB_TOP.u_top.u_uart_i2c_usb_spi);
 	   end
        `endif
 
+       /*************************************************************************
+       * This is Baud Rate to clock divider conversion for Test Bench
+       * Note: DUT uses 16x baud clock, where are test bench uses directly
+       * baud clock, Due to 16x Baud clock requirement at RTL, there will be
+       * some resolution loss, we expect at lower baud rate this resolution
+       * loss will be less. For Quick simulation perpose higher baud rate used
+       * *************************************************************************/
+       task tb_set_uart_baud;
+       input [31:0] ref_clk;
+       input [31:0] baud_rate;
+       output [31:0] baud_div;
+       reg   [31:0] baud_div;
+       begin
+	  // for 230400 Baud = (50Mhz/230400) = 216.7
+	  baud_div = ref_clk/baud_rate; // Get the Bit Baud rate
+	  // Baud 16x = 216/16 = 13
+          baud_div = baud_div/16; // To find the RTL baud 16x div value to find similar resolution loss in test bench
+	  // Test bench baud clock , 16x of above value
+	  // 13 * 16 = 208,  
+	  // (Note if you see original value was 216, now it's 208 )
+          baud_div = baud_div * 16;
+	  // Test bench half cycle counter to toggle it 
+	  // 208/2 = 104
+           baud_div = baud_div/2;
+	  //As counter run's from 0 , substract from 1
+	   baud_div = baud_div-1;
+       end
+       endtask
+       
+
 	initial begin
+               uart_data_bit           = 2'b11;
+               uart_stop_bits          = 0; // 0: 1 stop bit; 1: 2 stop bit;
+               uart_stick_parity       = 0; // 1: force even parity
+               uart_parity_en          = 0; // parity enable
+               uart_even_odd_parity    = 1; // 0: odd parity; 1: even parity
+	           tb_set_uart_baud(50000000,1152000,uart_divisor);// 50Mhz Ref clock, Baud Rate: 230400
+               uart_timeout            = 200;// wait time limit
+               uart_fifo_enable        = 0;	// fifo mode disable
 
 		$value$plusargs("risc_core_id=%d", d_risc_id);
 
@@ -136,48 +208,64 @@
 		#1;
 		// Remove all the reset
 		$display("STATUS: Working with Both core Risc core 0 & 1 ");
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h31F);
+        wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h31F);
 
+        read_data = 0;
+        // Wait for Software Reg-5 = 1 Set by the RiscV core
+        while (read_data !== 32'h1) begin
+           wb_user_core_read(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,read_data);
+        end
 
-		// Repeat cycles of 1000 clock edges as needed to complete testbench
-		repeat (22) begin
-			repeat (1000) @(posedge clock);
-			// $display("+1000 cycles");
-		end
+	    tb_uart.debug_mode = 0; // disable debug display
+        tb_uart.uart_init;
+        tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, uart_stick_parity, uart_timeout, uart_divisor);
 
+	    flag  = 0;
+		check_sum = 0;
+        test_start    = 1;
+            
+        fork
+           begin
+              while(flag == 0)
+              begin
+                 tb_uart.read_char(read_data,flag);
+		         if(flag == 0)  begin
+		            $write ("%c",read_data);
+		            check_sum = check_sum+read_data;
+		         end
+              end
+           end
+           begin
+              repeat (300000) @(posedge clock);  // wait for Processor Get Ready
+           end
+           join_any
+            
+           #100
+           tb_uart.report_status(uart_rx_nu, uart_tx_nu);
+            
 
-		$display("Monitor: Reading Back the expected value");
-		// User RISC core expect to write these value in global
-		// register, read back and decide on pass fail
-		// 0x30000018  = 0x11223344; 
-                // 0x3000001C  = 0x22334455; 
-                // 0x30000020  = 0x33445566; 
-                // 0x30000024  = 0x44556677; 
-                // 0x30000028 = 0x55667788; 
-                // 0x3000002C = 0x66778899; 
-
-                test_fail = 0;
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h11223344);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h22334455);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h33445566);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32'h44556677);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32'h55667788);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32'h66778899);
-
+           test_fail = 0;
+		   $display("Total Rx Char: %d Check Sum : %x ",uart_rx_nu, check_sum);
+             // Check 
+             // if all the 4224 byte received
+             // if no error 
+             if(uart_rx_nu != 216) test_fail = 1;
+             if(check_sum != 32'h44f0) test_fail = 1;
+             if(tb_uart.err_cnt != 0) test_fail = 1;
 
 	   
 	    	$display("###################################################");
           	if(test_fail == 0) begin
 		   `ifdef GL
-	    	       $display("Monitor: Standalone User Risc Boot (GL) Passed");
+	    	       $display("Monitor: multi core test (GL) Passed");
 		   `else
-		       $display("Monitor: Standalone User Risc Boot (RTL) Passed");
+		       $display("Monitor: multi core test (RTL) Passed");
 		   `endif
 	        end else begin
 		    `ifdef GL
-	    	        $display("Monitor: Standalone User Risc Boot (GL) Failed");
+	    	        $display("Monitor: multi core test (GL) Failed");
 		    `else
-		        $display("Monitor: Standalone User Risc Boot (RTL) Failed");
+		        $display("Monitor: multi core test (RTL) Failed");
 		    `endif
 		 end
 	    	$display("###################################################");
@@ -257,7 +345,7 @@
    assign io_in[32] = flash_io3;
 
    // Quard flash
-     s25fl256s #(.mem_file_name("user_mcore.hex"),
+     s25fl256s #(.mem_file_name(`TB_HEX_FILE),
 	         .otp_file_name("none"),
                  .TimingModel("S25FL512SAGMFI010_F_30pF")) 
 		 u_spi_flash_256mb (
@@ -274,6 +362,19 @@
        );
 
 
+//---------------------------
+//  UART Agent integration
+// --------------------------
+wire uart_txd,uart_rxd;
+
+assign uart_txd   = io_out[2];
+assign io_in[1]  = uart_rxd ;
+ 
+uart_agent tb_uart(
+	.mclk                (clock              ),
+	.txd                 (uart_rxd           ),
+	.rxd                 (uart_txd           )
+	);
 
 
 task wb_user_core_write;
@@ -326,7 +427,7 @@
   wbd_ext_we_i  ='h0;  // write
   wbd_ext_dat_i ='h0;  // data output
   wbd_ext_sel_i ='h0;  // byte enable
-  $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
+  //$display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
   repeat (2) @(posedge clock);
 end
 endtask
diff --git a/verilog/dv/user_pwm/user_pwm_tb.v b/verilog/dv/user_pwm/user_pwm_tb.v
index e5222cc..c6f24b7 100644
--- a/verilog/dv/user_pwm/user_pwm_tb.v
+++ b/verilog/dv/user_pwm/user_pwm_tb.v
@@ -144,17 +144,17 @@
 		wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
 
                 // Enable PWM Multi Functional Ports
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h03F);
+                wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h03F);
 
 	        repeat (2) @(posedge clock);
 		#1;
 
                 // Remove the reset
 		// Remove WB and SPI/UART Reset, Keep CORE under Reset
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h01F);
+                wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F);
 
 		// config 1us based on system clock - 1000/25ns = 40 
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG1,39);
+                wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_GLBL,39);
 
 		test_fail = 0;
 	        repeat (200) @(posedge clock);
@@ -162,12 +162,12 @@
 
 	        $display("Step-1, PWM-0: 1ms/2 = 500Hz; PWM-1: 1ms/3; PWM-2: 1ms/4, PWM-3: 1ms/5, PWM-4: 1ms/6, PWM-5: 1ms/7");
 	        test_step = 1;
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM0,'h0000_0000);
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM1,'h0000_0001);
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM2,'h0001_0001);
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM3,'h0001_0002);
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM4,'h0002_0002);
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM5,'h0002_0003);
+                wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_0,'h0000_0000);
+                wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_1,'h0000_0001);
+                wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_2,'h0001_0001);
+                wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_3,'h0001_0002);
+                wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_4,'h0002_0002);
+                wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_5,'h0002_0003);
 	        pwm_monitor(OneMsPeriod*2,OneMsPeriod*3,OneMsPeriod*4,OneMsPeriod*5,OneMsPeriod*6,OneMsPeriod*7);
 
 		repeat (100) @(posedge clock);
diff --git a/verilog/dv/user_qspi/user_qspi_tb.v b/verilog/dv/user_qspi/user_qspi_tb.v
index 4fd07e5..8f984e1 100644
--- a/verilog/dv/user_qspi/user_qspi_tb.v
+++ b/verilog/dv/user_qspi/user_qspi_tb.v
@@ -203,7 +203,7 @@
 	        repeat (2) @(posedge clock);
 		#1;
 		// Remove only WB and SPI Reset
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h2);
+                wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h2);
 
                 wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h0000); // Change the Bank Sel 0000
 
diff --git a/verilog/dv/user_qspi/user_risc_boot.c b/verilog/dv/user_qspi/user_risc_boot.c
index 0711b7b..83fb41b 100644
--- a/verilog/dv/user_qspi/user_risc_boot.c
+++ b/verilog/dv/user_qspi/user_risc_boot.c
@@ -18,34 +18,18 @@
 #define SC_SIM_OUTPORT (0xf0000000)
 #define uint32_t  long
 
-#define reg_mprj_globl_reg0  (*(volatile uint32_t*)0x30030000)
-#define reg_mprj_globl_reg1  (*(volatile uint32_t*)0x30030004)
-#define reg_mprj_globl_reg2  (*(volatile uint32_t*)0x30030008)
-#define reg_mprj_globl_reg3  (*(volatile uint32_t*)0x3003000C)
-#define reg_mprj_globl_reg4  (*(volatile uint32_t*)0x30030010)
-#define reg_mprj_globl_reg5  (*(volatile uint32_t*)0x30030014)
-#define reg_mprj_globl_reg6  (*(volatile uint32_t*)0x30030018)
-#define reg_mprj_globl_reg7  (*(volatile uint32_t*)0x3003001C)
-#define reg_mprj_globl_reg8  (*(volatile uint32_t*)0x30030020)
-#define reg_mprj_globl_reg9  (*(volatile uint32_t*)0x30030024)
-#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x30030028)
-#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x3003002C)
-#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x30030030)
-#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x30030034)
-#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x30030038)
-#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x3003003C)
-#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x30030040)
-#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x30030044)
-#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x30030048)
-#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x3003004C)
-#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x30030050)
-#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x30030054)
-#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x30030058)
-#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x3003005C)
-#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x30030060)
-#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x30030064)
-#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x30030068)
-#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x3003006C)
+#define reg_mprj_globl_reg0  (*(volatile uint32_t*)0x10020000) // Chip ID
+#define reg_mprj_globl_reg1  (*(volatile uint32_t*)0x10020004) // Global Config-0
+#define reg_mprj_globl_reg2  (*(volatile uint32_t*)0x10020008) // Global Config-1
+#define reg_mprj_globl_reg3  (*(volatile uint32_t*)0x1002000C) // Global Interrupt Mask
+#define reg_mprj_globl_reg4  (*(volatile uint32_t*)0x10020010) // Global Interrupt
+#define reg_mprj_globl_reg5  (*(volatile uint32_t*)0x10020014) // Multi functional sel
+#define reg_mprj_globl_soft0  (*(volatile uint32_t*)0x10020018) // Sof Register-0
+#define reg_mprj_globl_soft1  (*(volatile uint32_t*)0x1002001C) // Sof Register-1
+#define reg_mprj_globl_soft2  (*(volatile uint32_t*)0x10020020) // Sof Register-2
+#define reg_mprj_globl_soft3  (*(volatile uint32_t*)0x10020024) // Sof Register-3
+#define reg_mprj_globl_soft4 (*(volatile uint32_t*)0x10020028) // Sof Register-4
+#define reg_mprj_globl_soft5 (*(volatile uint32_t*)0x1002002C) // Sof Register-5
 
 int main()
 {
@@ -57,12 +41,12 @@
     //*out_ptr = 0xDDEEFF00;
 
     // Write software Write & Read Register
-    reg_mprj_globl_reg22  = 0x11223344; 
-    reg_mprj_globl_reg23  = 0x22334455; 
-    reg_mprj_globl_reg24  = 0x33445566; 
-    reg_mprj_globl_reg25  = 0x44556677; 
-    reg_mprj_globl_reg26 = 0x55667788; 
-    reg_mprj_globl_reg27 = 0x66778899; 
+    reg_mprj_globl_soft0  = 0x11223344; 
+    reg_mprj_globl_soft1  = 0x22334455; 
+    reg_mprj_globl_soft2  = 0x33445566; 
+    reg_mprj_globl_soft3  = 0x44556677; 
+    reg_mprj_globl_soft4 = 0x55667788; 
+    reg_mprj_globl_soft5 = 0x66778899; 
 
     while(1) {}
     return 0;
diff --git a/verilog/dv/user_risc_boot/user_risc_boot.c b/verilog/dv/user_risc_boot/user_risc_boot.c
index 37e424b..c14c9a7 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot.c
+++ b/verilog/dv/user_risc_boot/user_risc_boot.c
@@ -18,34 +18,18 @@
 #define SC_SIM_OUTPORT (0xf0000000)
 #define uint32_t  long
 
-#define reg_mprj_globl_reg0  (*(volatile uint32_t*)0x10020000)
-#define reg_mprj_globl_reg1  (*(volatile uint32_t*)0x10020004)
-#define reg_mprj_globl_reg2  (*(volatile uint32_t*)0x10020008)
-#define reg_mprj_globl_reg3  (*(volatile uint32_t*)0x1002000C)
-#define reg_mprj_globl_reg4  (*(volatile uint32_t*)0x10020010)
-#define reg_mprj_globl_reg5  (*(volatile uint32_t*)0x10020014)
-#define reg_mprj_globl_reg6  (*(volatile uint32_t*)0x10020018)
-#define reg_mprj_globl_reg7  (*(volatile uint32_t*)0x1002001C)
-#define reg_mprj_globl_reg8  (*(volatile uint32_t*)0x10020020)
-#define reg_mprj_globl_reg9  (*(volatile uint32_t*)0x10020024)
-#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x10020028)
-#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x1002002C)
-#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x10020030)
-#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x10020034)
-#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x10020038)
-#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x1002003C)
-#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x10020040)
-#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x10020044)
-#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x10020048)
-#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x1002004C)
-#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x10020050)
-#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x10020054)
-#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x10020058)
-#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x1002005C)
-#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x10020060)
-#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x10020064)
-#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x10020068)
-#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x1002006C)
+#define reg_mprj_globl_reg0  (*(volatile uint32_t*)0x10020000) // Chip ID
+#define reg_mprj_globl_reg1  (*(volatile uint32_t*)0x10020004) // Global Config-0
+#define reg_mprj_globl_reg2  (*(volatile uint32_t*)0x10020008) // Global Config-1
+#define reg_mprj_globl_reg3  (*(volatile uint32_t*)0x1002000C) // Global Interrupt Mask
+#define reg_mprj_globl_reg4  (*(volatile uint32_t*)0x10020010) // Global Interrupt
+#define reg_mprj_globl_reg5  (*(volatile uint32_t*)0x10020014) // Multi functional sel
+#define reg_mprj_globl_soft0  (*(volatile uint32_t*)0x10020018) // Sof Register-0
+#define reg_mprj_globl_soft1  (*(volatile uint32_t*)0x1002001C) // Sof Register-1
+#define reg_mprj_globl_soft2  (*(volatile uint32_t*)0x10020020) // Sof Register-2
+#define reg_mprj_globl_soft3  (*(volatile uint32_t*)0x10020024) // Sof Register-3
+#define reg_mprj_globl_soft4 (*(volatile uint32_t*)0x10020028) // Sof Register-4
+#define reg_mprj_globl_soft5 (*(volatile uint32_t*)0x1002002C) // Sof Register-5
 
 int main()
 {
@@ -57,12 +41,12 @@
     //*out_ptr = 0xDDEEFF00;
 
     // Write software Write & Read Register
-    reg_mprj_globl_reg22  = 0x11223344; 
-    reg_mprj_globl_reg23  = 0x22334455; 
-    reg_mprj_globl_reg24  = 0x33445566; 
-    reg_mprj_globl_reg25  = 0x44556677; 
-    reg_mprj_globl_reg26 = 0x55667788; 
-    reg_mprj_globl_reg27 = 0x66778899; 
+    reg_mprj_globl_soft0  = 0x11223344; 
+    reg_mprj_globl_soft1  = 0x22334455; 
+    reg_mprj_globl_soft2  = 0x33445566; 
+    reg_mprj_globl_soft3  = 0x44556677; 
+    reg_mprj_globl_soft4 = 0x55667788; 
+    reg_mprj_globl_soft5 = 0x66778899; 
     //reg_mprj_globl_reg12 = 0x778899AA; 
     //reg_mprj_globl_reg13 = 0x8899AABB; 
     //reg_mprj_globl_reg14 = 0x99AABBCC; 
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
index f8af2e8..79c705b 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v
+++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -145,10 +145,10 @@
 		// Remove all the reset
 		if(d_risc_id == 0) begin
 		     $display("STATUS: Working with Risc core 0");
-                     wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
+                     wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
 		end else begin
 		     $display("STATUS: Working with Risc core 1");
-                     wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
+                     wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
 		end
 
 
@@ -170,12 +170,12 @@
                 // 0x3000002C = 0x66778899; 
 
                 test_fail = 0;
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h11223344);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h22334455);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h33445566);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32'h44556677);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32'h55667788);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32'h66778899);
+		wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h11223344);
+		wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,32'h22334455);
+		wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,32'h33445566);
+		wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,read_data,32'h44556677);
+		wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,read_data,32'h55667788);
+		wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,read_data,32'h66778899);
 
 
 	   
@@ -240,6 +240,11 @@
 
 );
 
+// SSPI Slave I/F
+assign io_in[0]  = 1'b1; // RESET
+assign io_in[16] = 1'b0 ; // SPIS SCK 
+
+
 `ifndef GL // Drive Power for Hold Fix Buf
     // All standard cell need power hook-up for functionality work
     initial begin
diff --git a/verilog/dv/user_sema/Makefile b/verilog/dv/user_sema/Makefile
new file mode 100644
index 0000000..c74412f
--- /dev/null
+++ b/verilog/dv/user_sema/Makefile
@@ -0,0 +1,84 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+ 
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+DESIGNS?=../../..
+
+export USER_PROJECT_VERILOG ?=  $(DESIGNS)/verilog
+
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
+.SUFFIXES:
+
+PATTERN = user_sema
+
+all:  ${PATTERN:=.vcd}
+
+
+vvp:  ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+ifeq ($(SIM),RTL)
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
+	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
+	$< -o $@ 
+   endif
+else  
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+   endif
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump
+
+.PHONY: clean hex all
diff --git a/verilog/dv/user_mcore/user_mcore_tb.v b/verilog/dv/user_sema/user_sema_tb.v
similarity index 66%
copy from verilog/dv/user_mcore/user_mcore_tb.v
copy to verilog/dv/user_sema/user_sema_tb.v
index b43dcba..9b61ce6 100644
--- a/verilog/dv/user_mcore/user_mcore_tb.v
+++ b/verilog/dv/user_sema/user_sema_tb.v
@@ -16,13 +16,14 @@
 // SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
-////  Standalone User validation Test bench                       ////
+////  Hardware Semaphore validation Test bench                    ////
 ////                                                              ////
-////  This file is part of the riscduino cores project            ////
+////  This file is part of the YIFive cores project               ////
+////  https://github.com/dineshannayya/yifive_r0.git              ////
 ////                                                              ////
 ////  Description                                                 ////
 ////   This is a standalone test bench to validate the            ////
-////   Digital core multi-core behaviour.                         ////
+////   Digital core.                                              ////
 ////                                                              ////
 ////  To Do:                                                      ////
 ////    nothing                                                   ////
@@ -31,7 +32,7 @@
 ////      - Dinesh Annayya, dinesha@opencores.org                 ////
 ////                                                              ////
 ////  Revision :                                                  ////
-////    0.1 - 16th Feb 2021, Dinesh A                             ////
+////    0.1 - 17th Aug 2022, Dinesh A                             ////
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
@@ -62,48 +63,61 @@
 
 `default_nettype wire
 
-`timescale 1 ns / 1 ns
+`timescale 1 ns/10 ps
 
 `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
-module user_mcore_tb;
-	reg clock;
-	reg wb_rst_i;
-	reg power1, power2;
-	reg power3, power4;
 
-        reg        wbd_ext_cyc_i;  // strobe/request
-        reg        wbd_ext_stb_i;  // strobe/request
-        reg [31:0] wbd_ext_adr_i;  // address
-        reg        wbd_ext_we_i;  // write
-        reg [31:0] wbd_ext_dat_i;  // data output
-        reg [3:0]  wbd_ext_sel_i;  // byte enable
+`define TOP  user_sema_tb
 
-        wire [31:0] wbd_ext_dat_o;  // data input
-        wire        wbd_ext_ack_o;  // acknowlegement
-        wire        wbd_ext_err_o;  // error
+module `TOP;
+parameter CLK1_PERIOD = 10;
+parameter CLK2_PERIOD = 2;
 
-	// User I/O
-	wire [37:0] io_oeb;
-	wire [37:0] io_out;
-	wire [37:0] io_in;
+reg            clock         ;
+reg            clock2        ;
+reg            wb_rst_i      ;
+reg            power1, power2;
+reg            power3, power4;
 
-	wire gpio;
-	wire [37:0] mprj_io;
-	wire [7:0] mprj_io_0;
-	reg         test_fail;
-	reg [31:0] read_data;
-	integer    d_risc_id;
+reg            wbd_ext_cyc_i;  // strobe/request
+reg            wbd_ext_stb_i;  // strobe/request
+reg [31:0]     wbd_ext_adr_i;  // address
+reg            wbd_ext_we_i;  // write
+reg [31:0]     wbd_ext_dat_i;  // data output
+reg [3:0]      wbd_ext_sel_i;  // byte enable
 
+wire [31:0]    wbd_ext_dat_o;  // data input
+wire           wbd_ext_ack_o;  // acknowlegement
+wire           wbd_ext_err_o;  // error
 
+// User I/O
+wire [37:0]    io_oeb        ;
+wire [37:0]    io_out        ;
+wire [37:0]    io_in         ;
+
+wire [37:0]    mprj_io       ;
+wire [7:0]     mprj_io_0     ;
+reg            test_fail     ;
+reg [31:0]     read_data     ;
+reg [31:0]     exp_data     ;
+//----------------------------------
+// Uart Configuration
+// ---------------------------------
+integer        test_step;
+
+integer i,j;
 
 	// External clock is used by default.  Make this artificially fast for the
 	// simulation.  Normally this would be a slow clock and the digital PLL
 	// would be the fast clock.
 
-	always #12.5 clock <= (clock === 1'b0);
+	always #(CLK1_PERIOD/2) clock  <= (clock === 1'b0);
+	always #(CLK2_PERIOD/2) clock2 <= (clock2 === 1'b0);
 
 	initial begin
+		test_step = 0;
 		clock = 0;
+		clock2 = 0;
                 wbd_ext_cyc_i ='h0;  // strobe/request
                 wbd_ext_stb_i ='h0;  // strobe/request
                 wbd_ext_adr_i ='h0;  // address
@@ -115,90 +129,119 @@
 	`ifdef WFDUMP
 	   initial begin
 	   	$dumpfile("simx.vcd");
-	   	$dumpvars(1, user_mcore_tb);
-	   	$dumpvars(1, user_mcore_tb.u_top);
-	   	$dumpvars(0, user_mcore_tb.u_top.u_riscv_top);
+	   	$dumpvars(1, `TOP);
+	   	//$dumpvars(1, `TOP.u_top);
+	   	//$dumpvars(0, `TOP.u_top.u_pll);
+	   	$dumpvars(0, `TOP.u_top.u_wb_host);
+	   	//$dumpvars(1, `TOP.u_top.u_intercon);
+	   	//$dumpvars(1, `TOP.u_top.u_intercon);
+	   	$dumpvars(0, `TOP.u_top.u_pinmux);
 	   end
        `endif
 
 	initial begin
-
-		$value$plusargs("risc_core_id=%d", d_risc_id);
-
-		#200; // Wait for reset removal
-	        repeat (10) @(posedge clock);
-		$display("Monitor: Standalone User Risc Boot Test Started");
-
-		// Remove Wb Reset
-		wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
-
-	        repeat (2) @(posedge clock);
-		#1;
-		// Remove all the reset
-		$display("STATUS: Working with Both core Risc core 0 & 1 ");
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h31F);
-
-
-		// Repeat cycles of 1000 clock edges as needed to complete testbench
-		repeat (22) begin
-			repeat (1000) @(posedge clock);
-			// $display("+1000 cycles");
-		end
-
-
-		$display("Monitor: Reading Back the expected value");
-		// User RISC core expect to write these value in global
-		// register, read back and decide on pass fail
-		// 0x30000018  = 0x11223344; 
-                // 0x3000001C  = 0x22334455; 
-                // 0x30000020  = 0x33445566; 
-                // 0x30000024  = 0x44556677; 
-                // 0x30000028 = 0x55667788; 
-                // 0x3000002C = 0x66778899; 
-
-                test_fail = 0;
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h11223344);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h22334455);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h33445566);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32'h44556677);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32'h55667788);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32'h66778899);
-
-
-	   
-	    	$display("###################################################");
-          	if(test_fail == 0) begin
-		   `ifdef GL
-	    	       $display("Monitor: Standalone User Risc Boot (GL) Passed");
-		   `else
-		       $display("Monitor: Standalone User Risc Boot (RTL) Passed");
-		   `endif
-	        end else begin
-		    `ifdef GL
-	    	        $display("Monitor: Standalone User Risc Boot (GL) Failed");
-		    `else
-		        $display("Monitor: Standalone User Risc Boot (RTL) Failed");
-		    `endif
-		 end
-	    	$display("###################################################");
-	    $finish;
-	end
-
-	initial begin
 		wb_rst_i <= 1'b1;
 		#100;
 		wb_rst_i <= 1'b0;	    	// Release reset
 	end
+
+
+initial
+begin
+
+   #200; // Wait for reset removal
+   repeat (10) @(posedge clock);
+   $display("Monitor: Standalone User Basic Test Started");
+   
+   repeat (2) @(posedge clock);
+
+   test_fail=0;
+   fork
+      begin
+         // Remove Wb/PinMux Reset
+         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+
+         // Setting Lock Bit Individually and clearing it imediatly
+         for(i=0; i < 15; i = i+1) begin
+            read_data = 'h0;
+            // Step-1: Wait for Semaphore lock bit to '1'
+            while(read_data[0] == 0) begin
+               @(posedge clock) ;
+                  wb_user_core_read(`ADDR_SPACE_SEMA+ (i*4),read_data);
+             end 
+            // Step-2: Check is Really Lock Bit it Set the corresponding lock status
+             wb_user_core_read_check(`ADDR_SPACE_SEMA+`SEMA_CFG_STATUS,read_data, 1<< i);
+            // Step-3: Clear the Lock Bit
+             wb_user_core_write(`ADDR_SPACE_SEMA+(i*4),1);
+            // Step-4: Check is Really Lock Bit it Cleared the corresponding lock status
+             wb_user_core_read_check(`ADDR_SPACE_SEMA+`SEMA_CFG_STATUS,read_data, 0);
+            
+         end
+         // Setting all Lock Bit  and clearing it end
+         exp_data  = 'h0;
+         for(i=0; i < 15; i = i+1) begin
+            read_data = 'h0;
+            // Step-1: Wait for Semaphore lock bit to '1'
+            while(read_data[0] == 0) begin
+               @(posedge clock) ;
+                  wb_user_core_read(`ADDR_SPACE_SEMA+(i*4),read_data);
+             end 
+            exp_data  = exp_data | (1<< i);
+            wb_user_core_read_check(`ADDR_SPACE_SEMA+`SEMA_CFG_STATUS,read_data, exp_data);
+         end
+         // Step-2: Check all 15 Sema bit set
+         wb_user_core_read_check(`ADDR_SPACE_SEMA+`SEMA_CFG_STATUS,read_data, 32'h7FFF);
+         exp_data  = 32'h7FFF;
+         for(i=0; i < 15; i = i+1) begin
+            // Step-3: clear the Sema Bit
+            wb_user_core_write(`ADDR_SPACE_SEMA+(i*4),32'h1);
+            exp_data  = exp_data ^ (1<< i);
+            wb_user_core_read_check(`ADDR_SPACE_SEMA+`SEMA_CFG_STATUS,read_data, exp_data);
+         end
+         // Step-3: All hardware lock bit is cleared
+         wb_user_core_read_check(`ADDR_SPACE_SEMA+`SEMA_CFG_STATUS,read_data, 32'h0);
+      end
+   
+      begin
+      repeat (30000) @(posedge clock);
+   		// $display("+1000 cycles");
+      test_fail = 1;
+      end
+      join_any
+      disable fork; //disable pending fork activity
+
+   
+      $display("###################################################");
+      if(test_fail == 0) begin
+         `ifdef GL
+             $display("Monitor: Semaphore Test (GL) Passed");
+         `else
+             $display("Monitor: Semaphore Test (RTL) Passed");
+         `endif
+      end else begin
+          `ifdef GL
+              $display("Monitor: Semaphore Test (GL) Failed");
+          `else
+              $display("Monitor: Semaphore Test (RTL) Failed");
+          `endif
+       end
+      $display("###################################################");
+      #100
+      $finish;
+end
+
+
 wire USER_VDD1V8 = 1'b1;
 wire VSS = 1'b0;
 
+
 user_project_wrapper u_top(
 `ifdef USE_POWER_PINS
     .vccd1(USER_VDD1V8),	// User area 1 1.8V supply
     .vssd1(VSS),	// User area 1 digital ground
 `endif
     .wb_clk_i        (clock),  // System clock
-    .user_clock2     (1'b1),  // Real-time clock
+    .user_clock2     (clock2),  // Real-time clock
     .wb_rst_i        (wb_rst_i),  // Regular Reset signal
 
     .wbs_cyc_i   (wbd_ext_cyc_i),  // strobe/request
@@ -231,47 +274,11 @@
     // All standard cell need power hook-up for functionality work
     initial begin
 
+
     end
 `endif    
 
-//------------------------------------------------------
-//  Integrate the Serial flash with qurd support to
-//  user core using the gpio pads
-//  ----------------------------------------------------
 
-   wire flash_clk = io_out[24];
-   wire flash_csb = io_out[25];
-   // Creating Pad Delay
-   wire #1 io_oeb_29 = io_oeb[29];
-   wire #1 io_oeb_30 = io_oeb[30];
-   wire #1 io_oeb_31 = io_oeb[31];
-   wire #1 io_oeb_32 = io_oeb[32];
-   tri  #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz;
-   tri  #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz;
-   tri  #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz;
-   tri  #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz;
-
-   assign io_in[29] = flash_io0;
-   assign io_in[30] = flash_io1;
-   assign io_in[31] = flash_io2;
-   assign io_in[32] = flash_io3;
-
-   // Quard flash
-     s25fl256s #(.mem_file_name("user_mcore.hex"),
-	         .otp_file_name("none"),
-                 .TimingModel("S25FL512SAGMFI010_F_30pF")) 
-		 u_spi_flash_256mb (
-           // Data Inputs/Outputs
-       .SI      (flash_io0),
-       .SO      (flash_io1),
-       // Controls
-       .SCK     (flash_clk),
-       .CSNeg   (flash_csb),
-       .WPNeg   (flash_io2),
-       .HOLDNeg (flash_io3),
-       .RSTNeg  (!wb_rst_i)
-
-       );
 
 
 
@@ -406,5 +413,4 @@
 `endif
 **/
 endmodule
-`include "s25fl256s.sv"
 `default_nettype wire
diff --git a/verilog/dv/user_spi_isp/user_spi_isp_tb.v b/verilog/dv/user_spi_isp/user_spi_isp_tb.v
index a0e0fb5..95e4e51 100644
--- a/verilog/dv/user_spi_isp/user_spi_isp_tb.v
+++ b/verilog/dv/user_spi_isp/user_spi_isp_tb.v
@@ -154,19 +154,19 @@
    $display("Monitor: Writing  expected value");
    
    test_fail = 0;
-   u_spim.reg_wr_dword(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,32'h11223344);
-   u_spim.reg_wr_dword(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,32'h22334455);
-   u_spim.reg_wr_dword(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,32'h33445566);
-   u_spim.reg_wr_dword(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,32'h44556677);
-   u_spim.reg_wr_dword(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,32'h55667788);
-   u_spim.reg_wr_dword(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,32'h66778899);
+   u_spim.reg_wr_dword(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,32'h11223344);
+   u_spim.reg_wr_dword(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,32'h22334455);
+   u_spim.reg_wr_dword(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,32'h33445566);
+   u_spim.reg_wr_dword(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,32'h44556677);
+   u_spim.reg_wr_dword(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,32'h55667788);
+   u_spim.reg_wr_dword(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,32'h66778899);
 
-   u_spim.reg_rd_dword_cmp(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,32'h11223344);
-   u_spim.reg_rd_dword_cmp(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,32'h22334455);
-   u_spim.reg_rd_dword_cmp(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,32'h33445566);
-   u_spim.reg_rd_dword_cmp(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,32'h44556677);
-   u_spim.reg_rd_dword_cmp(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,32'h55667788);
-   u_spim.reg_rd_dword_cmp(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,32'h66778899);
+   u_spim.reg_rd_dword_cmp(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,32'h11223344);
+   u_spim.reg_rd_dword_cmp(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,32'h22334455);
+   u_spim.reg_rd_dword_cmp(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,32'h33445566);
+   u_spim.reg_rd_dword_cmp(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,32'h44556677);
+   u_spim.reg_rd_dword_cmp(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,32'h55667788);
+   u_spim.reg_rd_dword_cmp(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,32'h66778899);
    
    
    
diff --git a/verilog/dv/user_sram_exec/user_sram_exec.c b/verilog/dv/user_sram_exec/user_sram_exec.c
index 62546a8..3f36137 100644
--- a/verilog/dv/user_sram_exec/user_sram_exec.c
+++ b/verilog/dv/user_sram_exec/user_sram_exec.c
@@ -20,42 +20,26 @@
 #define uint32_t  long
 #define uint16_t  int
 
-#define reg_mprj_globl_reg0  (*(volatile uint32_t*)0x10020000)
-#define reg_mprj_globl_reg1  (*(volatile uint32_t*)0x10020004)
-#define reg_mprj_globl_reg2  (*(volatile uint32_t*)0x10020008)
-#define reg_mprj_globl_reg3  (*(volatile uint32_t*)0x1002000C)
-#define reg_mprj_globl_reg4  (*(volatile uint32_t*)0x10020010)
-#define reg_mprj_globl_reg5  (*(volatile uint32_t*)0x10020014)
-#define reg_mprj_globl_reg6  (*(volatile uint32_t*)0x10020018)
-#define reg_mprj_globl_reg7  (*(volatile uint32_t*)0x1002001C)
-#define reg_mprj_globl_reg8  (*(volatile uint32_t*)0x10020020)
-#define reg_mprj_globl_reg9  (*(volatile uint32_t*)0x10020024)
-#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x10020028)
-#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x1002002C)
-#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x10020030)
-#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x10020034)
-#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x10020038)
-#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x1002003C)
-#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x10020040)
-#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x10020044)
-#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x10020048)
-#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x1002004C)
-#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x10020050)
-#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x10020054)
-#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x10020058)
-#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x1002005C)
-#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x10020060)
-#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x10020064)
-#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x10020068)
-#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x1002006C)
+#define reg_mprj_globl_reg0  (*(volatile uint32_t*)0x10020000) // Chip ID
+#define reg_mprj_globl_reg1  (*(volatile uint32_t*)0x10020004) // Global Config-0
+#define reg_mprj_globl_reg2  (*(volatile uint32_t*)0x10020008) // Global Config-1
+#define reg_mprj_globl_reg3  (*(volatile uint32_t*)0x1002000C) // Global Interrupt Mask
+#define reg_mprj_globl_reg4  (*(volatile uint32_t*)0x10020010) // Global Interrupt
+#define reg_mprj_globl_reg5  (*(volatile uint32_t*)0x10020014) // Multi functional sel
+#define reg_mprj_globl_soft0  (*(volatile uint32_t*)0x10020018) // Sof Register-0
+#define reg_mprj_globl_soft1  (*(volatile uint32_t*)0x1002001C) // Sof Register-1
+#define reg_mprj_globl_soft2  (*(volatile uint32_t*)0x10020020) // Sof Register-2
+#define reg_mprj_globl_soft3  (*(volatile uint32_t*)0x10020024) // Sof Register-3
+#define reg_mprj_globl_soft4 (*(volatile uint32_t*)0x10020028) // Sof Register-4
+#define reg_mprj_globl_soft5 (*(volatile uint32_t*)0x1002002C) // Sof Register-5
 // -------------------------------------------------------------------------
 // Test copying code into SRAM and running it from there.
 // -------------------------------------------------------------------------
 
 void test_function()
 {
-    reg_mprj_globl_reg24  = 0x33445566;  // Sig-3
-    reg_mprj_globl_reg25  = 0x44556677;  // Sig-4
+    reg_mprj_globl_soft2  = 0x33445566;  // Sig-2
+    reg_mprj_globl_soft3  = 0x44556677;  // Sig-3
 
     return;
 }
@@ -70,18 +54,18 @@
     src_ptr = &test_function;
     dst_ptr = func;
 
-    reg_mprj_globl_reg22  = 0x11223344;  // Sig-1
+    reg_mprj_globl_soft0  = 0x11223344;  // Sig-0
     while (src_ptr < &main) {
 	*(dst_ptr++) = *(src_ptr++);
     }
 
     // Call the routine in SRAM
-    reg_mprj_globl_reg23  = 0x22334455;  // Sig-2
+    reg_mprj_globl_soft1  = 0x22334455;  // Sig-1
     
     ((void(*)())func)();
 
-    reg_mprj_globl_reg26 = 0x55667788; 
-    reg_mprj_globl_reg27 = 0x66778899; 
+    reg_mprj_globl_soft4 = 0x55667788; // Sig-4
+    reg_mprj_globl_soft5 = 0x66778899; // Sig-5
 
     // Signal end of test
 }
diff --git a/verilog/dv/user_sram_exec/user_sram_exec_tb.v b/verilog/dv/user_sram_exec/user_sram_exec_tb.v
index 2aaad02..a8f6568 100644
--- a/verilog/dv/user_sram_exec/user_sram_exec_tb.v
+++ b/verilog/dv/user_sram_exec/user_sram_exec_tb.v
@@ -137,10 +137,10 @@
 		// Remove all the reset
 		if(d_risc_id == 0) begin
 		     $display("STATUS: Working with Risc core 0");
-                     wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
+                     wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
 		end else begin
 		     $display("STATUS: Working with Risc core 1");
-                     wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
+                     wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
 		end
 
 
@@ -162,12 +162,12 @@
                 // 0x3000002C = 0x66778899; 
 
                 test_fail = 0;
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h11223344);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h22334455);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h33445566);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32'h44556677);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32'h55667788);
-		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32'h66778899);
+		wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h11223344);
+		wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,32'h22334455);
+		wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,32'h33445566);
+		wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,read_data,32'h44556677);
+		wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,read_data,32'h55667788);
+		wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,read_data,32'h66778899);
 
 
 	   
diff --git a/verilog/dv/user_sspi/.sspi_task.v.swp b/verilog/dv/user_sspi/.sspi_task.v.swp
deleted file mode 100644
index ecd1440..0000000
--- a/verilog/dv/user_sspi/.sspi_task.v.swp
+++ /dev/null
Binary files differ
diff --git a/verilog/dv/user_sspi/user_sspi_tb.v b/verilog/dv/user_sspi/user_sspi_tb.v
index c8e3f5c..eee28ca 100644
--- a/verilog/dv/user_sspi/user_sspi_tb.v
+++ b/verilog/dv/user_sspi/user_sspi_tb.v
@@ -142,14 +142,14 @@
                 // Enable SPI Multi Functional Ports
                 // wire        cfg_spim_enb         = cfg_multi_func_sel[10];
                 // wire [3:0]  cfg_spim_cs_enb      = cfg_multi_func_sel[14:11];
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h7C00);
+                wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h7C00);
 
 	        repeat (2) @(posedge clock);
 		#1;
 
                 // Remove the reset
 		// Remove WB and SPI/UART Reset, Keep CORE under Reset
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h01F);
+                wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F);
 
 
 		test_fail = 0;
@@ -448,6 +448,11 @@
 
 );
 
+// SSPI Slave I/F
+assign io_in[0]  = 1'b1; // RESET
+assign io_in[16] = 1'b0 ; // SPIS SCK 
+
+
 `ifndef GL // Drive Power for Hold Fix Buf
     // All standard cell need power hook-up for functionality work
     initial begin
@@ -456,7 +461,7 @@
 `endif    
 
 //------------------------------------------------------
-//  Integrate the Serial flash with qurd support to
+//  Integrate the Serial flash with quad support to
 //  user core using the gpio pads
 //  ----------------------------------------------------
    wire flash_io1;
diff --git a/verilog/dv/user_timer/user_timer_tb.v b/verilog/dv/user_timer/user_timer_tb.v
index b27d655..5a4f0ab 100644
--- a/verilog/dv/user_timer/user_timer_tb.v
+++ b/verilog/dv/user_timer/user_timer_tb.v
@@ -146,13 +146,13 @@
 
                 // Remove the reset
 		// Remove WB and SPI/UART Reset, Keep CORE under Reset
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h01F);
+                wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F);
 
 		// config 1us based on system clock - 1000/25ns = 40 
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG1,39);
+                wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_GLBL,39);
 
 		// Enable Timer Interrupt
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR_MSK,'h700);
+                wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_MSK,'h700);
 
 		test_fail = 0;
 	        repeat (200) @(posedge clock);
@@ -160,25 +160,25 @@
 
 	        $display("Step-1, Timer-0: 1us * 100 = 100us; Timer-1: 200us; Timer-2: 300us");
 	        test_step = 1;
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER0,'h0001_0063);
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER1,'h0001_00C7);
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER2,'h0001_012B);
+                wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_0,'h0001_0063);
+                wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_1,'h0001_00C7);
+                wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_2,'h0001_012B);
 	        timer_monitor(OneUsPeriod*100,OneUsPeriod*200,OneUsPeriod*300);
 
 		$display("Checking the Timer Interrupt generation and clearing");
 
 		// Disable the Timer - To avoid multiple interrupt generation
 		// during status check and interrupt clearing
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER0,'h0000_0063);
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER1,'h0000_00C7);
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER2,'h0000_012B);
+                wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_0,'h0000_0063);
+                wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_1,'h0000_00C7);
+                wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_2,'h0000_012B);
 
-                wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data);
+                wb_user_core_read(`ADDR_SPACE_GLBL+`GPIO_CFG_INTR_STAT,read_data);
 		if((u_top.u_pinmux.irq_lines[10:8] == 3'b111) && (read_data[10:8] == 3'b111)) begin
 		    $display("STATUS: Timer Interrupt detected ");
 		    // Clearing the Timer Interrupt
-                    wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,'h700);
-                    wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data);
+                    wb_user_core_write(`ADDR_SPACE_GLBL+`GPIO_CFG_INTR_CLR,'h700);
+                    wb_user_core_read(`ADDR_SPACE_GLBL+`GPIO_CFG_INTR_STAT,read_data);
 		    if((u_top.u_pinmux.irq_lines[10:8] == 3'b111) && (read_data[10:8] == 3'b000)) begin
 		       $display("ERROR: Timer Interrupt not cleared ");
 		       test_fail = 1;
@@ -192,25 +192,25 @@
 
 	        $display("Step-2, Timer-0: 1us * 200 = 200us; Timer-1: 300us; Timer-2: 400us");
 	        test_step = 2;
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER0,'h0001_00C7);
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER1,'h0001_012B);
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER2,'h0001_018F);
+                wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_0,'h0001_00C7);
+                wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_1,'h0001_012B);
+                wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_2,'h0001_018F);
 	        timer_monitor(OneUsPeriod*200,OneUsPeriod*300,OneUsPeriod*400);
 
 		$display("Checking the Timer Interrupt generation and clearing");
 
 		// Disable the Timer - To avoid multiple interrupt generation
 		// during status check and interrupt clearing
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER0,'h0000_0063);
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER1,'h0000_00C7);
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER2,'h0000_012B);
+                wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_0,'h0000_0063);
+                wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_1,'h0000_00C7);
+                wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_2,'h0000_012B);
 
-                wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data);
+                wb_user_core_read(`ADDR_SPACE_GLBL+`GPIO_CFG_INTR_STAT,read_data);
 		if((u_top.u_pinmux.irq_lines[10:8] == 3'b111) && (read_data[10:8] == 3'b111)) begin
 		    $display("STATUS: Timer Interrupt detected ");
 		    // Clearing the Timer Interrupt
-                    wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,'h700);
-                    wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data);
+                    wb_user_core_write(`ADDR_SPACE_GLBL+`GPIO_CFG_INTR_CLR,'h700);
+                    wb_user_core_read(`ADDR_SPACE_GLBL+`GPIO_CFG_INTR_STAT,read_data);
 		    if((u_top.u_pinmux.irq_lines[10:8] == 3'b111) && (read_data[10:8] == 3'b000)) begin
 		       $display("ERROR: Timer Interrupt not cleared ");
 		       test_fail = 1;
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index e0656e9..0096617 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -146,7 +146,8 @@
 	`ifdef WFDUMP
 	   initial begin
 	   	$dumpfile("simx.vcd");
-	   	$dumpvars(0, user_uart_tb);
+	   	$dumpvars(1, user_uart_tb);
+	   	$dumpvars(1, user_uart_tb.u_top);
 	   end
        `endif
 
@@ -176,23 +177,23 @@
    wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
 
    // Enable UART Multi Functional Ports
-   wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h100);
+   wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h100);
    
    repeat (2) @(posedge clock);
    #1;
    // Remove all the reset
    if(d_risc_id == 0) begin
 	$display("STATUS: Working with Risc core 0");
-	wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
+	wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
    end else if(d_risc_id == 1) begin
 	$display("STATUS: Working with Risc core 1");
-	wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
+	wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
    end else if(d_risc_id == 2) begin
 	$display("STATUS: Working with Risc core 2");
-	wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h41F);
+	wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F);
    end else if(d_risc_id == 3) begin
 	$display("STATUS: Working with Risc core 3");
-	wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h81F);
+	wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
    end
 
    repeat (100) @(posedge clock);  // wait for Processor Get Ready
@@ -299,6 +300,11 @@
 
 );
 
+// SSPI Slave I/F
+assign io_in[0]  = 1'b1; // RESET
+assign io_in[16] = 1'b0 ; // SPIS SCK 
+
+
 `ifndef GL // Drive Power for Hold Fix Buf
     // All standard cell need power hook-up for functionality work
     initial begin
diff --git a/verilog/dv/user_uart1/user_uart1_tb.v b/verilog/dv/user_uart1/user_uart1_tb.v
index 44587e4..6a2d3c5 100644
--- a/verilog/dv/user_uart1/user_uart1_tb.v
+++ b/verilog/dv/user_uart1/user_uart1_tb.v
@@ -176,23 +176,23 @@
    wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
 
    // Enable UART Multi Functional Ports
-   wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h200);
+   wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h200);
    
    repeat (2) @(posedge clock);
    #1;
    // Remove all the reset
    if(d_risc_id == 0) begin
 	$display("STATUS: Working with Risc core 0");
-	wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h143);
+	wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h143);
    end else if(d_risc_id == 1) begin
 	$display("STATUS: Working with Risc core 1");
-	wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h243);
+	wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h243);
    end else if(d_risc_id == 2) begin
 	$display("STATUS: Working with Risc core 2");
-	wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h443);
+	wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h443);
    end else if(d_risc_id == 3) begin
 	$display("STATUS: Working with Risc core 2");
-	wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h84F);
+	wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h84F);
    end
 
    repeat (100) @(posedge clock);  // wait for Processor Get Ready
@@ -299,6 +299,11 @@
 
 );
 
+// SSPI Slave I/F
+assign io_in[0]  = 1'b1; // RESET
+assign io_in[16] = 1'b0 ; // SPIS SCK 
+
+
 `ifndef GL // Drive Power for Hold Fix Buf
     // All standard cell need power hook-up for functionality work
     initial begin
diff --git a/verilog/dv/user_uart_master/user_uart_master_tb.v b/verilog/dv/user_uart_master/user_uart_master_tb.v
index 40d7b07..4ed2f00 100644
--- a/verilog/dv/user_uart_master/user_uart_master_tb.v
+++ b/verilog/dv/user_uart_master/user_uart_master_tb.v
@@ -195,19 +195,19 @@
    $display("Monitor: Writing  expected value");
    
    test_fail = 0;
-   uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,32'h11223344);
-   uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,32'h22334455);
-   uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,32'h33445566);
-   uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,32'h44556677);
-   uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,32'h55667788);
-   uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,32'h66778899);
+   uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,32'h11223344);
+   uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,32'h22334455);
+   uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,32'h33445566);
+   uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,32'h44556677);
+   uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,32'h55667788);
+   uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,32'h66778899);
 
-   uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,32'h11223344);
-   uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,32'h22334455);
-   uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,32'h33445566);
-   uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,32'h44556677);
-   uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,32'h55667788);
-   uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,32'h66778899);
+   uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,32'h11223344);
+   uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,32'h22334455);
+   uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,32'h33445566);
+   uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,32'h44556677);
+   uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,32'h55667788);
+   uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,32'h66778899);
    
    
    
diff --git a/verilog/dv/user_usb/user_usb_tb.v b/verilog/dv/user_usb/user_usb_tb.v
index 5974990..98115f7 100644
--- a/verilog/dv/user_usb/user_usb_tb.v
+++ b/verilog/dv/user_usb/user_usb_tb.v
@@ -176,7 +176,7 @@
                 wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
 
                 // Enable SPI Multi Functional Ports
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h400);
+                wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h400);
 
 	        repeat (2) @(posedge clock);
 		#1;
@@ -188,7 +188,7 @@
 
                 // Remove the reset
 		// Remove WB and SPI/UART Reset, Keep CORE under Reset
-                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h03F);
+                wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h03F);
 
 
 		test_fail = 0;
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile
index 5ae8623..3ec839e 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/wb_port/Makefile
@@ -53,7 +53,7 @@
 
 export TOOLS     ?=  /opt/riscv32i 
 export GCC_PATH  ?=  $(TOOLS)/bin
-export GCC_PREFIX?=    riscv32-unknown-linux-gnu
+GCC_PREFIX?=riscv32-unknown-elf
 
 
 
diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c
index 03a5799..642303c 100644
--- a/verilog/dv/wb_port/wb_port.c
+++ b/verilog/dv/wb_port/wb_port.c
@@ -98,31 +98,32 @@
     reg_mprj_wbhost_reg0 = 0x1;
 
     // Remove Reset
-    reg_pinmux_gbl_cfg0 = 0x01f;
+    reg_glbl_cfg0 = 0x01f;
 
-    if (reg_pinmux_chip_id != 0x82682301) bFail = 1;
+    if (reg_glbl_chip_id != 0x82682501) bFail = 1;
+    if (bFail == 1) reg_mprj_datal = 0xAB610000;
 
     // write software write & read Register
-    reg_pinmux_soft_reg_1  = 0x11223344; 
-    reg_pinmux_soft_reg_2  = 0x22334455; 
-    reg_pinmux_soft_reg_3  = 0x33445566; 
-    reg_pinmux_soft_reg_4  = 0x44556677; 
-    reg_pinmux_soft_reg_5  = 0x55667788; 
-    reg_pinmux_soft_reg_6  = 0x66778899; 
+    reg_glbl_soft_reg_0  = 0x11223344; 
+    reg_glbl_soft_reg_1  = 0x22334455; 
+    reg_glbl_soft_reg_2  = 0x33445566; 
+    reg_glbl_soft_reg_3  = 0x44556677; 
+    reg_glbl_soft_reg_4  = 0x55667788; 
+    reg_glbl_soft_reg_5  = 0x66778899; 
 
 
-    if (reg_pinmux_soft_reg_1  != 0x11223344) bFail = 1;
-    if (bFail == 1) reg_mprj_datal = 0xAB610000;
-    if (reg_pinmux_soft_reg_2  != 0x22334455) bFail = 1;
+    if (reg_glbl_soft_reg_0  != 0x11223344) bFail = 1;
     if (bFail == 1) reg_mprj_datal = 0xAB620000;
-    if (reg_pinmux_soft_reg_3  != 0x33445566) bFail = 1;
+    if (reg_glbl_soft_reg_1  != 0x22334455) bFail = 1;
     if (bFail == 1) reg_mprj_datal = 0xAB630000;
-    if (reg_pinmux_soft_reg_4  != 0x44556677) bFail = 1;
+    if (reg_glbl_soft_reg_2  != 0x33445566) bFail = 1;
     if (bFail == 1) reg_mprj_datal = 0xAB640000;
-    if (reg_pinmux_soft_reg_5 != 0x55667788) bFail = 1;
+    if (reg_glbl_soft_reg_3  != 0x44556677) bFail = 1;
     if (bFail == 1) reg_mprj_datal = 0xAB650000;
-    if (reg_pinmux_soft_reg_6 != 0x66778899) bFail = 1;
+    if (reg_glbl_soft_reg_4 != 0x55667788) bFail = 1;
     if (bFail == 1) reg_mprj_datal = 0xAB660000;
+    if (reg_glbl_soft_reg_5 != 0x66778899) bFail = 1;
+    if (bFail == 1) reg_mprj_datal = 0xAB670000;
 
     if(bFail == 0) {
         reg_mprj_datal = 0xAB6A0000;
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project
index 2876d64..d355b07 100644
--- a/verilog/includes/includes.gl.caravel_user_project
+++ b/verilog/includes/includes.gl.caravel_user_project
@@ -117,7 +117,7 @@
 #-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pwm.sv
 #-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/timer.sv
 #else
-$(USER_PROJECT_VERILOG)/gl/pinmux.v
+$(USER_PROJECT_VERILOG)/gl/pinmux_top.v
 #endif
 
 ##################################################
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index 5e4aeb0..01f8d3c 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -7,11 +7,19 @@
 +incdir+$(USER_PROJECT_VERILOG)/dv/model
 +incdir+$(USER_PROJECT_VERILOG)/dv/agents
 $(USER_PROJECT_VERILOG)/rtl/user_reg_map.v
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux_top.sv
 -v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux.sv
--v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux_reg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/glbl_reg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/gpio_top.sv
 -v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/gpio_intr.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/gpio_reg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pwm_top.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pwm_reg.sv
 -v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pwm.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/timer_top.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/timer_reg.sv
 -v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/timer.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/semaphore_reg.sv
 -v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type1.sv
 -v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type2.sv
 -v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_top.sv
@@ -45,6 +53,7 @@
 -v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_ctl.sv  
 -v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_if.sv
 -v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_cfg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_clkgen.sv
 -v $(USER_PROJECT_VERILOG)/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv
 -v $(USER_PROJECT_VERILOG)/rtl/lib/async_fifo.sv  
 -v $(USER_PROJECT_VERILOG)/rtl/lib/registers.v
diff --git a/verilog/rtl/lib/registers.v b/verilog/rtl/lib/registers.v
index e4a87a1..b9a093e 100755
--- a/verilog/rtl/lib/registers.v
+++ b/verilog/rtl/lib/registers.v
@@ -288,6 +288,45 @@
 endmodule
 
 /*********************************************************************
+ module: generic 16b register
+***********************************************************************/
+module  gen_16b_reg	(
+	      //List of Inputs
+	      cs,
+	      we,		 
+	      data_in,
+	      reset_n,
+	      clk,
+	      
+	      //List of Outs
+	      data_out
+	      );
+
+  parameter   RESET_DEFAULT    = 16'h0;  
+  input [1:0]      we;	
+  input            cs;
+  input [15:0]     data_in;	
+  input            reset_n;
+  input		       clk;
+  output [15:0]    data_out;
+
+
+  reg [15:0]    data_out;
+
+always @ (posedge clk or negedge reset_n) begin 
+  if (reset_n == 1'b0) begin
+    data_out  <= RESET_DEFAULT ;
+  end
+  else begin
+    if(cs && we[0]) data_out[7:0]   <= data_in[7:0];
+    if(cs && we[1]) data_out[15:8]  <= data_in[15:8];
+  end
+end
+
+
+endmodule
+
+/*********************************************************************
  module: generic 32b register
 ***********************************************************************/
 module  gen_32b_reg	(
diff --git a/verilog/rtl/pinmux/src/glbl_reg.sv b/verilog/rtl/pinmux/src/glbl_reg.sv
new file mode 100644
index 0000000..d91ff4e
--- /dev/null
+++ b/verilog/rtl/pinmux/src/glbl_reg.sv
@@ -0,0 +1,437 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  Global Register                                             ////
+////                                                              ////
+////  This file is part of the riscduino cores project            ////
+////  https://github.com/dineshannayya/riscduino.git              ////
+////                                                              ////
+////  Description                                                 ////
+////      Hold all the Global and PinMux Register                 ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision :                                                  ////
+////    0.1 - 16th Feb 2021, Dinesh A                             ////
+////          initial version                                     ////
+//////////////////////////////////////////////////////////////////////
+//
+module glbl_reg (
+                       // System Signals
+                       // Inputs
+		               input logic             mclk                   ,
+                       input logic             h_reset_n              ,
+
+                       // Global Reset control
+                       output logic  [1:0]     cpu_core_rst_n         ,
+                       output logic            cpu_intf_rst_n         ,
+                       output logic            qspim_rst_n            ,
+                       output logic            sspim_rst_n            ,
+                       output logic  [1:0]     uart_rst_n             ,
+                       output logic            i2cm_rst_n             ,
+                       output logic            usb_rst_n              ,
+
+		       // Reg Bus Interface Signal
+                       input logic             reg_cs                 ,
+                       input logic             reg_wr                 ,
+                       input logic [3:0]       reg_addr               ,
+                       input logic [31:0]      reg_wdata              ,
+                       input logic [3:0]       reg_be                 ,
+
+                       // Outputs
+                       output logic [31:0]     reg_rdata              ,
+                       output logic            reg_ack                ,
+
+		               input  logic [1:0]      ext_intr_in            ,
+
+		      // Risc configuration
+                       output logic [15:0]     irq_lines              ,
+                       output logic            soft_irq               ,
+                       output logic [2:0]      user_irq               ,
+		               input  logic            usb_intr               ,
+		               input  logic            i2cm_intr              ,
+
+		               output logic [15:0]     cfg_riscv_ctrl         ,
+                       output  logic [31:0]    cfg_multi_func_sel     ,// multifunction pins
+                        
+
+		               input   logic [2:0]      timer_intr            ,
+		               input   logic            gpio_intr             
+   ); 
+
+
+                       
+//-----------------------------------------------------------------------
+// Internal Wire Declarations
+//-----------------------------------------------------------------------
+
+logic          sw_rd_en               ;
+logic          sw_wr_en;
+logic [4:0]    sw_addr; // addressing 16 registers
+logic [31:0]   sw_reg_wdata;
+logic [3:0]    wr_be  ;
+
+logic [31:0]   reg_out;
+logic  [31:0]   reg_0;  // Chip ID
+logic  [31:0]   reg_1;  // Global Reg-0
+logic  [31:0]   reg_2;  // Global Reg-1
+logic  [31:0]   reg_3;  // Global Interrupt Mask
+logic [31:0]    reg_4;  // Global Interrupt Status
+logic [31:0]    reg_5;  // Multi Function Sel
+logic [31:0]    reg_6;  // Software Reg-0
+logic [31:0]    reg_7;  // Software Reg-1
+logic [31:0]    reg_8;  // Software Reg-2
+logic [31:0]    reg_9;  // Software Reg-3
+logic  [31:0]   reg_10; // Software Reg-4
+logic [31:0]    reg_11; // Software Reg-5
+
+
+logic           cs_int;
+
+
+assign       sw_addr       = reg_addr ;
+assign       sw_rd_en      = reg_cs & !reg_wr;
+assign       sw_wr_en      = reg_cs & reg_wr;
+assign       wr_be         = reg_be;
+assign       sw_reg_wdata  = reg_wdata;
+
+
+always @ (posedge mclk or negedge h_reset_n)
+begin : preg_out_Seq
+   if (h_reset_n == 1'b0) begin
+      reg_rdata  <= 'h0;
+      reg_ack    <= 1'b0;
+   end else if (reg_cs && !reg_ack) begin
+      reg_rdata <= reg_out ;
+      reg_ack   <= 1'b1;
+   end else begin
+      reg_ack        <= 1'b0;
+   end
+end
+
+
+
+//-----------------------------------------------------------------------
+// register read enable and write enable decoding logic
+//-----------------------------------------------------------------------
+wire   sw_wr_en_0 = sw_wr_en  & (sw_addr == 4'h0);
+wire   sw_wr_en_1 = sw_wr_en  & (sw_addr == 4'h1);
+wire   sw_wr_en_2 = sw_wr_en  & (sw_addr == 4'h2);
+wire   sw_wr_en_3 = sw_wr_en  & (sw_addr == 4'h3);
+wire   sw_wr_en_4 = sw_wr_en  & (sw_addr == 4'h4);
+wire   sw_wr_en_5 = sw_wr_en  & (sw_addr == 4'h5);
+wire   sw_wr_en_6 = sw_wr_en  & (sw_addr == 4'h6);
+wire   sw_wr_en_7 = sw_wr_en  & (sw_addr == 4'h7);
+wire   sw_wr_en_8 = sw_wr_en  & (sw_addr == 4'h8);
+wire   sw_wr_en_9 = sw_wr_en  & (sw_addr == 4'h9);
+wire   sw_wr_en_10 = sw_wr_en & (sw_addr == 4'hA);
+wire   sw_wr_en_11 = sw_wr_en & (sw_addr == 4'hB);
+
+
+wire   sw_rd_en_0  = sw_rd_en  & (sw_addr == 4'h0);
+wire   sw_rd_en_1  = sw_rd_en  & (sw_addr == 4'h1);
+wire   sw_rd_en_2  = sw_rd_en  & (sw_addr == 4'h2);
+wire   sw_rd_en_3  = sw_rd_en  & (sw_addr == 4'h3);
+wire   sw_rd_en_4  = sw_rd_en  & (sw_addr == 4'h4);
+wire   sw_rd_en_5  = sw_rd_en  & (sw_addr == 4'h5);
+wire   sw_rd_en_6  = sw_rd_en  & (sw_addr == 4'h6);
+wire   sw_rd_en_7  = sw_rd_en  & (sw_addr == 4'h7);
+wire   sw_rd_en_8  = sw_rd_en  & (sw_addr == 4'h8);
+wire   sw_rd_en_9  = sw_rd_en  & (sw_addr == 4'h9);
+wire   sw_rd_en_10 = sw_rd_en  & (sw_addr == 4'hA);
+wire   sw_rd_en_11 = sw_rd_en  & (sw_addr == 4'hB);
+
+//-----------------------------------------------------------------------
+// Individual register assignments
+//-----------------------------------------------------------------------
+
+// Chip ID
+// chip-id[3:0] mapping
+//    0 -  YIFIVE (MPW-2)
+//    1 -  Riscdunio (MPW-3)
+//    2 -  Riscdunio (MPW-4)
+//    3 -  Riscdunio (MPW-5)
+//    4 -  Riscdunio (MPW-6)
+//    5 -  Riscdunio (MPW-7)
+//    6 -  Riscdunio (MPW-8)
+//    7 -  Riscdunio (MPW-9)
+
+wire [15:0] manu_id      =  16'h8268; // Asci value of RD
+wire [3:0]  total_core   =  4'h2;
+wire [3:0]  chip_id      =  4'h5;
+wire [7:0]  chip_rev     =  8'h01;
+
+assign reg_0 = {manu_id,total_core,chip_id,chip_rev};
+
+
+//------------------------------------------
+// reg-1: GLBL_CFG_0
+//------------------------------------------
+wire [31:0] cfg_glb_ctrl = reg_1;
+
+ctech_buf u_buf_cpu_intf_rst  (.A(cfg_glb_ctrl[0]),.X(cpu_intf_rst_n));
+ctech_buf u_buf_qspim_rst     (.A(cfg_glb_ctrl[1]),.X(qspim_rst_n));
+ctech_buf u_buf_sspim_rst     (.A(cfg_glb_ctrl[2]),.X(sspim_rst_n));
+ctech_buf u_buf_uart0_rst     (.A(cfg_glb_ctrl[3]),.X(uart_rst_n[0]));
+ctech_buf u_buf_i2cm_rst      (.A(cfg_glb_ctrl[4]),.X(i2cm_rst_n));
+ctech_buf u_buf_usb_rst       (.A(cfg_glb_ctrl[5]),.X(usb_rst_n));
+ctech_buf u_buf_uart1_rst     (.A(cfg_glb_ctrl[6]),.X(uart_rst_n[1]));
+
+ctech_buf u_buf_cpu0_rst      (.A(cfg_glb_ctrl[8]),.X(cpu_core_rst_n[0]));
+ctech_buf u_buf_cpu1_rst      (.A(cfg_glb_ctrl[9]),.X(cpu_core_rst_n[1]));
+
+gen_32b_reg  #(32'h0) u_reg_1	(
+	      //List of Inputs
+	      .reset_n    (h_reset_n     ),
+	      .clk        (mclk          ),
+	      .cs         (sw_wr_en_1    ),
+	      .we         (wr_be         ),		 
+	      .data_in    (sw_reg_wdata  ),
+	      
+	      //List of Outs
+	      .data_out   (reg_1         )
+	      );
+
+//----------------------------------------------
+// reg-2: GLBL_CFG_1
+//------------------------------------------
+
+gen_32b_reg  #(32'h0) u_reg_2	(
+	      //List of Inputs
+	      .reset_n    (h_reset_n     ),
+	      .clk        (mclk          ),
+	      .cs         (sw_wr_en_2    ),
+	      .we         (wr_be         ),		 
+	      .data_in    (sw_reg_wdata  ),
+	      
+	      //List of Outs
+	      .data_out   (reg_2         )
+	      );
+
+assign cfg_riscv_ctrl      = reg_2[31:16];
+
+//-----------------------------------------------------------------------
+//   reg-3 : Global Interrupt Mask
+//-----------------------------------------------------------------------
+
+gen_32b_reg  #(32'h0) u_reg_3	(
+	      //List of Inputs
+	      .reset_n    (h_reset_n     ),
+	      .clk        (mclk          ),
+	      .cs         (sw_wr_en_3    ),
+	      .we         (wr_be         ),		 
+	      .data_in    (sw_reg_wdata  ),
+	      
+	      //List of Outs
+	      .data_out   (reg_3         )
+	      );
+
+//-----------------------------------------------------------------------
+//   reg-4 : Global Interrupt Status
+//-----------------------------------------------------------------
+assign  irq_lines     = reg_3[15:0] & reg_4[15:0]; 
+assign  soft_irq      = reg_3[16]   & reg_4[16]; 
+assign  user_irq      = reg_3[19:17]& reg_4[19:17]; 
+
+
+generic_register #(8,0  ) u_reg4_be0 (
+	      .we            ({8{sw_wr_en_4 & 
+                                 wr_be[0]   }}   ),		 
+	      .data_in       (sw_reg_wdata[7:0]  ),
+	      .reset_n       (h_reset_n          ),
+	      .clk           (mclk               ),
+	      
+	      //List of Outs
+	      .data_out      (reg_4[7:0]         )
+          );
+
+
+wire [7:0] hware_intr_req = {gpio_intr, ext_intr_in[1:0], usb_intr, i2cm_intr,timer_intr[2:0]};
+
+generic_intr_stat_reg #(.WD(8),
+	                .RESET_DEFAULT(0)) u_reg4_be1 (
+		 //inputs
+		 .clk         (mclk              ),
+		 .reset_n     (h_reset_n         ),
+	         .reg_we      ({8{sw_wr_en_4 & reg_ack & 
+                                 wr_be[1]   }}  ),		 
+		 .reg_din    (sw_reg_wdata[15:8] ),
+		 .hware_req  (hware_intr_req     ),
+		 
+		 //outputs
+		 .data_out    (reg_4[15:8]       )
+	      );
+
+
+
+generic_register #(4,0  ) u_reg4_be2 (
+	      .we            ({4{sw_wr_en_4 & 
+                                 wr_be[2]   }}  ),		 
+	      .data_in       (sw_reg_wdata[19:16]),
+	      .reset_n       (h_reset_n           ),
+	      .clk           (mclk              ),
+	      
+	      //List of Outs
+	      .data_out      (reg_4[19:16]        )
+          );
+
+assign reg_4[31:20] = '0;
+
+
+//-----------------------------------------------------------------------
+// Logic for cfg_multi_func_sel :Enable GPIO to act as multi function pins 
+//-----------------------------------------------------------------------
+assign  cfg_multi_func_sel = reg_5[31:0]; // to be used for read
+
+
+gen_32b_reg  #(32'h0) u_reg_5	(
+	      //List of Inputs
+	      .reset_n    (h_reset_n     ),
+	      .clk        (mclk          ),
+	      .cs         (sw_wr_en_5    ),
+	      .we         (wr_be         ),		 
+	      .data_in    (sw_reg_wdata  ),
+	      
+	      //List of Outs
+	      .data_out   (reg_5        )
+	      );
+
+//-----------------------------------------
+// Software Reg-0 : ASCI Representation of RISC = 32'h8273_8343
+// ----------------------------------------
+gen_32b_reg  #(32'h8273_8343) u_reg_6	(
+	      //List of Inputs
+	      .reset_n    (h_reset_n     ),
+	      .clk        (mclk          ),
+	      .cs         (sw_wr_en_6    ),
+	      .we         (wr_be         ),		 
+	      .data_in    (sw_reg_wdata  ),
+	      
+	      //List of Outs
+	      .data_out   (reg_6       )
+	      );
+
+//-----------------------------------------
+// Software Reg-1, Release date: <DAY><MONTH><YEAR>
+// ----------------------------------------
+gen_32b_reg  #(32'h1508_2022) u_reg_7	(
+	      //List of Inputs
+	      .reset_n    (h_reset_n     ),
+	      .clk        (mclk          ),
+	      .cs         (sw_wr_en_7    ),
+	      .we         (wr_be         ),		 
+	      .data_in    (sw_reg_wdata  ),
+	      
+	      //List of Outs
+	      .data_out   (reg_7       )
+	      );
+
+//-----------------------------------------
+// Software Reg-2: Poject Revison 5.0 = 0005000
+// ----------------------------------------
+gen_32b_reg  #(32'h0005_0000) u_reg_8	(
+	      //List of Inputs
+	      .reset_n    (h_reset_n     ),
+	      .clk        (mclk          ),
+	      .cs         (sw_wr_en_8    ),
+	      .we         (wr_be         ),		 
+	      .data_in    (sw_reg_wdata  ),
+	      
+	      //List of Outs
+	      .data_out   (reg_8       )
+	      );
+
+//-----------------------------------------
+// Software Reg-3
+// ----------------------------------------
+gen_32b_reg  #(32'h0) u_reg_9	(
+	      //List of Inputs
+	      .reset_n    (h_reset_n     ),
+	      .clk        (mclk          ),
+	      .cs         (sw_wr_en_9   ),
+	      .we         (wr_be         ),		 
+	      .data_in    (sw_reg_wdata  ),
+	      
+	      //List of Outs
+	      .data_out   (reg_9       )
+	      );
+
+//-----------------------------------------
+// Software Reg-4
+// ----------------------------------------
+gen_32b_reg  #(32'h0) u_reg_10	(
+	      //List of Inputs
+	      .reset_n    (h_reset_n     ),
+	      .clk        (mclk          ),
+	      .cs         (sw_wr_en_10   ),
+	      .we         (wr_be         ),		 
+	      .data_in    (sw_reg_wdata  ),
+	      
+	      //List of Outs
+	      .data_out   (reg_10       )
+	      );
+
+//-----------------------------------------
+// Software Reg-5
+// ----------------------------------------
+gen_32b_reg  #(32'h0) u_reg_11	(
+	      //List of Inputs
+	      .reset_n    (h_reset_n     ),
+	      .clk        (mclk          ),
+	      .cs         (sw_wr_en_11   ),
+	      .we         (wr_be         ),		 
+	      .data_in    (sw_reg_wdata  ),
+	      
+	      //List of Outs
+	      .data_out   (reg_11       )
+	      );
+
+
+
+//-----------------------------------------------------------------------
+// Register Read Path Multiplexer instantiation
+//-----------------------------------------------------------------------
+
+always_comb
+begin 
+  reg_out [31:0] = 32'h0;
+
+  case (sw_addr [3:0])
+    4'b0000 : reg_out [31:0] = reg_0  [31:0];     
+    4'b0001 : reg_out [31:0] = reg_1  [31:0];    
+    4'b0010 : reg_out [31:0] = reg_2  [31:0];     
+    4'b0011 : reg_out [31:0] = reg_3  [31:0];    
+    4'b0100 : reg_out [31:0] = reg_4  [31:0];    
+    4'b0101 : reg_out [31:0] = reg_5  [31:0];    
+    4'b0110 : reg_out [31:0] = reg_6  [31:0];    
+    4'b0111 : reg_out [31:0] = reg_7  [31:0];    
+    4'b1000 : reg_out [31:0] = reg_8  [31:0];    
+    4'b1001 : reg_out [31:0] = reg_9  [31:0];    
+    4'b1010 : reg_out [31:0] = reg_10 [31:0];   
+    4'b1011 : reg_out [31:0] = reg_11 [31:0];   
+    default  : reg_out [31:0] = 32'h0;
+  endcase
+end
+
+
+endmodule                       
diff --git a/verilog/rtl/pinmux/src/gpio_control.sv b/verilog/rtl/pinmux/src/gpio_control.sv
deleted file mode 100644
index 4c917dc..0000000
--- a/verilog/rtl/pinmux/src/gpio_control.sv
+++ /dev/null
@@ -1,44 +0,0 @@
-
-// GPIO Interrupt Generation
-module gpio_intr (
-   input  logic         mclk                     ,// System clk
-   input  logic         h_reset_n                ,// system reset
-   input  logic [31:0]  gpio_prev_indata         ,// previously captured GPIO I/P pins data
-   input  logic [31:0]  cfg_gpio_data_in         ,// GPIO I/P pins data captured into this
-   input  logic [31:0]  cfg_gpio_out_data        ,// GPIO statuc O/P data from config reg
-   input  logic [31:0]  cfg_gpio_dir_sel         ,// decides on GPIO pin is I/P or O/P at pad level
-   input  logic [31:0]  cfg_gpio_posedge_int_sel ,// select posedge interrupt
-   input  logic [31:0]  cfg_gpio_negedge_int_sel ,// select negedge interrupt
-   
-   
-   output logic [31:0]  pad_gpio_out             ,// GPIO O/P to the gpio cfg reg
-   output logic [31:0]  gpio_int_event            // to the cfg interrupt status reg 
- 
-);
-
-
-integer i;
-//-----------------------------------------------------------------------
-// Logic for interrupt detection 
-//-----------------------------------------------------------------------
-
-reg [31:0]  local_gpio_int_event;             // to the cfg interrupt status reg 
-always @(cfg_gpio_data_in or cfg_gpio_negedge_int_sel or cfg_gpio_posedge_int_sel
-            or gpio_prev_indata)
-begin
-   for (i=0; i<32; i=i+1)
-   begin 
-   // looking for rising edge int 
-      local_gpio_int_event[i] = ((cfg_gpio_posedge_int_sel[i] & ~gpio_prev_indata[i] 
-                                   &  cfg_gpio_data_in[i]) | 
-                                 (cfg_gpio_negedge_int_sel[i] & gpio_prev_indata[i] & 
-                                     ~cfg_gpio_data_in[i]));
-                                // looking for falling edge int 
-   end
-end
-
-assign gpio_int_event   = local_gpio_int_event[31:0]; // goes as O/P to the cfg reg 
-
-assign pad_gpio_out     = cfg_gpio_out_data[31:0]     ;// O/P on the GPIO bus
-
-endmodule
diff --git a/verilog/rtl/pinmux/src/gpio_reg.sv b/verilog/rtl/pinmux/src/gpio_reg.sv
new file mode 100644
index 0000000..be61923
--- /dev/null
+++ b/verilog/rtl/pinmux/src/gpio_reg.sv
@@ -0,0 +1,325 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  GPIO Register                                               ////
+////                                                              ////
+////  This file is part of the riscduino cores project            ////
+////  https://github.com/dineshannayya/riscduino.git              ////
+////                                                              ////
+////  Description                                                 ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision :                                                  ////
+////    0.1 - 15th Aug 2022, Dinesh A                             ////
+////          initial version                                     ////
+//////////////////////////////////////////////////////////////////////
+//
+module gpio_reg  (
+                       // System Signals
+                       // Inputs
+		               input logic           mclk               ,
+                       input logic           h_reset_n          ,
+
+		               // Reg Bus Interface Signal
+                       input logic           reg_cs             ,
+                       input logic           reg_wr             ,
+                       input logic [3:0]     reg_addr           ,
+                       input logic [31:0]    reg_wdata          ,
+                       input logic [3:0]     reg_be             ,
+
+                       // Outputs
+                       output logic [31:0]   reg_rdata          ,
+                       output logic          reg_ack            ,
+
+
+                       input  logic  [31:0]  gpio_in_data             ,
+                       output logic  [31:0]  gpio_prev_indata         ,// previously captured GPIO I/P pins data
+                       input  logic  [31:0]  gpio_int_event           ,
+                       output logic  [31:0]  cfg_gpio_out_data        ,// GPIO statuc O/P data from config reg
+                       output logic  [31:0]  cfg_gpio_dir_sel         ,// decides on GPIO pin is I/P or O/P at pad level, 0 -> Input, 1 -> Output
+                       output logic  [31:0]  cfg_gpio_out_type        ,// GPIO Type, Unused
+                       output logic  [31:0]  cfg_multi_func_sel       ,// GPIO Multi function type
+                       output logic  [31:0]  cfg_gpio_posedge_int_sel ,// select posedge interrupt
+                       output logic  [31:0]  cfg_gpio_negedge_int_sel ,// select negedge interrupt
+                       output logic  [31:00] cfg_gpio_data_in         ,
+
+                       output logic          gpio_intr          
+
+
+                ); 
+
+//-----------------------------------------------------------------------
+// Internal Wire Declarations
+//-----------------------------------------------------------------------
+
+logic          sw_rd_en        ;
+logic          sw_wr_en        ;
+logic [3:0]    sw_addr         ; // addressing 16 registers
+logic [31:0]   sw_reg_wdata    ;
+logic [3:0]    sw_be           ;
+
+logic [31:0]   reg_out         ;
+logic [31:0]   reg_0           ; // GPIO Direction Select
+logic [31:0]   reg_1           ; // GPIO TYPE - Unused
+logic [31:0]   reg_2           ; // GPIO IN DATA
+logic [31:0]   reg_3           ; // GPIO OUT DATA
+logic [31:0]   reg_4           ; // GPIO INTERRUPT STATUS/CLEAR
+logic [31:0]   reg_5           ; // GPIO INTERRUPT SET
+logic [31:0]   reg_6           ; // GPIO INTERRUPT MASK
+logic [31:0]   reg_7           ; // GPIO POSEDGE INTERRUPT SEL
+logic [31:0]   reg_8           ; // GPIO NEGEDGE INTERRUPT SEL
+
+assign       sw_addr       = reg_addr;
+assign       sw_rd_en      = reg_cs & !reg_wr;
+assign       sw_wr_en      = reg_cs & reg_wr;
+assign       sw_be         = reg_be;
+assign       sw_reg_wdata  = reg_wdata;
+
+//-----------------------------------------------------------------------
+// register read enable and write enable decoding logic
+//-----------------------------------------------------------------------
+wire   sw_wr_en_0 = sw_wr_en  & (sw_addr == 4'h0);
+wire   sw_wr_en_1 = sw_wr_en  & (sw_addr == 4'h1);
+wire   sw_wr_en_2 = sw_wr_en  & (sw_addr == 4'h2);
+wire   sw_wr_en_3 = sw_wr_en  & (sw_addr == 4'h3);
+wire   sw_wr_en_4 = sw_wr_en  & (sw_addr == 4'h4);
+wire   sw_wr_en_5 = sw_wr_en  & (sw_addr == 4'h5);
+wire   sw_wr_en_6 = sw_wr_en  & (sw_addr == 4'h6);
+wire   sw_wr_en_7 = sw_wr_en  & (sw_addr == 4'h7);
+wire   sw_wr_en_8 = sw_wr_en  & (sw_addr == 4'h8);
+
+wire   sw_rd_en_0 = sw_rd_en  & (sw_addr == 4'h0);
+wire   sw_rd_en_1 = sw_rd_en  & (sw_addr == 4'h1);
+wire   sw_rd_en_2 = sw_rd_en  & (sw_addr == 4'h2);
+wire   sw_rd_en_3 = sw_rd_en  & (sw_addr == 4'h3);
+wire   sw_rd_en_4 = sw_rd_en  & (sw_addr == 4'h4);
+wire   sw_rd_en_5 = sw_rd_en  & (sw_addr == 4'h5);
+wire   sw_rd_en_6 = sw_rd_en  & (sw_addr == 4'h6);
+wire   sw_rd_en_7 = sw_rd_en  & (sw_addr == 4'h7);
+wire   sw_rd_en_8 = sw_rd_en  & (sw_addr == 4'h8);
+
+
+always @ (posedge mclk or negedge h_reset_n)
+begin : preg_out_Seq
+   if (h_reset_n == 1'b0) begin
+      reg_rdata  <= 'h0;
+      reg_ack    <= 1'b0;
+   end else if (reg_cs && !reg_ack) begin
+      reg_rdata  <= reg_out;
+      reg_ack    <= 1'b1;
+   end else begin
+      reg_ack    <= 1'b0;
+   end
+end
+
+//-----------------------------------------------------------------------
+// Logic for cfg_gpio_dir_sel 
+//-----------------------------------------------------------------------
+assign cfg_gpio_dir_sel = reg_0[31:0]; // data to the GPIO O/P pins 
+
+gen_32b_reg  #(32'h0) u_reg_0	(
+	      //List of Inputs
+	      .reset_n    (h_reset_n     ),
+	      .clk        (mclk          ),
+	      .cs         (sw_wr_en_0    ),
+	      .we         (sw_be         ),		 
+	      .data_in    (sw_reg_wdata  ),
+	      
+	      //List of Outs
+	      .data_out   (reg_0         )
+	      );
+//-----------------------------------------------------------------------
+// Logic for cfg_gpio_out_type 
+//-----------------------------------------------------------------------
+assign cfg_gpio_out_type = reg_1[31:0]; // Un-used
+
+gen_32b_reg  #(32'h0) u_reg_1	(
+	      //List of Inputs
+	      .reset_n    (h_reset_n     ),
+	      .clk        (mclk          ),
+	      .cs         (sw_wr_en_1    ),
+	      .we         (sw_be         ),		 
+	      .data_in    (sw_reg_wdata  ),
+	      
+	      //List of Outs
+	      .data_out   (reg_1         )
+	      );
+//-----------------------------------------------------------------------
+// Logic for gpio_data_in 
+//-----------------------------------------------------------------------
+logic [31:0] gpio_in_data_s;
+logic [31:0] gpio_in_data_ss;
+// Double Sync the gpio pin data for edge detection
+always @ (posedge mclk or negedge h_reset_n)
+begin 
+  if (h_reset_n == 1'b0) begin
+    reg_2  <= 'h0 ;
+    gpio_in_data_s  <= 32'd0;
+    gpio_in_data_ss <= 32'd0;
+  end
+  else begin
+    gpio_in_data_s   <= gpio_in_data;
+    gpio_in_data_ss <= gpio_in_data_s;
+    reg_2           <= gpio_in_data_ss;
+  end
+end
+
+
+assign cfg_gpio_data_in = reg_2[31:0]; // to be used for edge interrupt detect
+assign gpio_prev_indata = gpio_in_data_ss;
+
+//-----------------------------------------------------------------------
+// Logic for cfg_gpio_out_data 
+//-----------------------------------------------------------------------
+assign cfg_gpio_out_data = reg_3[31:0]; // data to the GPIO control blk 
+
+gen_32b_reg  #(32'h0) u_reg_3	(
+	      //List of Inputs
+	      .reset_n    (h_reset_n     ),
+	      .clk        (mclk          ),
+	      .cs         (sw_wr_en_3    ),
+	      .we         (sw_be         ),		 
+	      .data_in    (sw_reg_wdata  ),
+	      
+	      //List of Outs
+	      .data_out   (reg_3         )
+	      );
+
+
+
+//--------------------------------------------------------
+// Interrupt Status Generation
+// Note: Reg_4 --> Interrupt Status Register, Writting '1' will clear the
+//                 corresponding interrupt status bit. Writting '0' has no
+//                 effect 
+//       Reg_5 --> Writting one to this register will set the interrupt in
+//                  interrupt status register (reg_4), Writting '0' does not has any
+//                  effect.
+/// Always update int_status, even if no register write is occuring.
+//	    Interrupt posting is higher priority than int clear by host 
+//--------------------------------------------------------
+wire [31:0] gpio_int_status = reg_4;				      
+
+generic_intr_stat_reg #(.WD(32),
+	                .RESET_DEFAULT(0))  u_reg_4 (
+		 //inputs
+		 .clk         (mclk              ),
+		 .reset_n     (h_reset_n         ),
+	     .reg_we      ({
+		               {8{sw_wr_en_4 & reg_ack & sw_be[2]}},
+		               {8{sw_wr_en_4 & reg_ack & sw_be[2]}},
+		               {8{sw_wr_en_4 & reg_ack & sw_be[1]}},
+		               {8{sw_wr_en_4 & reg_ack & sw_be[0]}}
+		               }  ),		 
+		 .reg_din    (sw_reg_wdata[31:0] ),
+		 .hware_req  (gpio_int_event | {
+		               {8{sw_wr_en_5 & reg_ack}} & sw_reg_wdata[31:24],
+		               {8{sw_wr_en_5 & reg_ack}} & sw_reg_wdata[23:16],
+		               {8{sw_wr_en_5 & reg_ack}} & sw_reg_wdata[15:8] ,
+		               {8{sw_wr_en_5 & reg_ack}} & sw_reg_wdata[7:0]   
+		               }     ),
+		 
+		 //outputs
+		 .data_out    (reg_4[31:0]       )
+	      );
+//-------------------------------------------------
+// Returns same value as interrupt status register
+//------------------------------------------------
+
+assign reg_5 = reg_4;
+//-----------------------------------------------------------------------
+// Logic for cfg_gpio_int_mask :  GPIO interrupt mask  
+//-----------------------------------------------------------------------
+wire [31:0]  cfg_gpio_int_mask = reg_6[31:0]; // to be used for read
+
+assign gpio_intr  = ( | (reg_4 & reg_6) ); // interrupt pin to the RISC
+
+
+//  Register-11
+gen_32b_reg  #(32'h0) u_reg_6	(
+	      //List of Inputs
+	      .reset_n    (h_reset_n     ),
+	      .clk        (mclk          ),
+	      .cs         (sw_wr_en_6    ),
+	      .we         (sw_be         ),		 
+	      .data_in    (sw_reg_wdata  ),
+	      
+	      //List of Outs
+	      .data_out   (reg_6         )
+	      );
+//-----------------------------------------------------------------------
+// Logic for cfg_gpio_posedge_int_sel :  Enable posedge GPIO interrupt 
+//-----------------------------------------------------------------------
+assign  cfg_gpio_posedge_int_sel = reg_7[31:0]; // to be used for read
+gen_32b_reg  #(32'h0) u_reg_7	(
+	      //List of Inputs
+	      .reset_n    (h_reset_n     ),
+	      .clk        (mclk          ),
+	      .cs         (sw_wr_en_7    ),
+	      .we         (sw_be         ),		 
+	      .data_in    (sw_reg_wdata  ),
+	      
+	      //List of Outs
+	      .data_out   (reg_7        )
+	      );
+//-----------------------------------------------------------------------
+// Logic for cfg_gpio_negedge_int_sel :  Enable negedge GPIO interrupt 
+//-----------------------------------------------------------------------
+assign cfg_gpio_negedge_int_sel = reg_8[31:0]; // to be used for read
+gen_32b_reg  #(32'h0) u_reg_8	(
+	      //List of Inputs
+	      .reset_n    (h_reset_n     ),
+	      .clk        (mclk          ),
+	      .cs         (sw_wr_en_8    ),
+	      .we         (sw_be         ),		 
+	      .data_in    (sw_reg_wdata  ),
+	      
+	      //List of Outs
+	      .data_out   (reg_8        )
+	      );
+
+
+//-----------------------------------------------------------------------
+// Register Read Path Multiplexer instantiation
+//-----------------------------------------------------------------------
+
+always_comb
+begin 
+  reg_out [31:0] = 32'h0;
+
+  case (sw_addr [3:0])
+    4'b0000    : reg_out [31:0] = reg_0 [31:0];     
+    4'b0001    : reg_out [31:0] = reg_1 [31:0];    
+    4'b0010    : reg_out [31:0] = reg_2 [31:0];     
+    4'b0011    : reg_out [31:0] = reg_3 [31:0];    
+    4'b0100    : reg_out [31:0] = reg_4 [31:0];    
+    4'b0101    : reg_out [31:0] = reg_5 [31:0];    
+    4'b0110    : reg_out [31:0] = reg_6 [31:0];    
+    4'b0111    : reg_out [31:0] = reg_7 [31:0];    
+    4'b1000    : reg_out [31:0] = reg_8 [31:0];    
+    default    : reg_out [31:0] = 32'h0;
+  endcase
+end
+
+endmodule
diff --git a/verilog/rtl/pinmux/src/gpio_top.sv b/verilog/rtl/pinmux/src/gpio_top.sv
new file mode 100644
index 0000000..0a7fd02
--- /dev/null
+++ b/verilog/rtl/pinmux/src/gpio_top.sv
@@ -0,0 +1,130 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  GPIO Top                                                     ////
+////                                                              ////
+////  This file is part of the riscduino cores project            ////
+////  https://github.com/dineshannayya/riscduino.git              ////
+////                                                              ////
+////  Description                                                 ////
+///                                                               ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision :                                                  ////
+////    0.1 - 15th Aug 2022, Dinesh A                             ////
+////          initial version                                     ////
+//////////////////////////////////////////////////////////////////////
+
+module gpio_top  (
+                       // System Signals
+                       // Inputs
+		               input logic           mclk,
+                       input logic           h_reset_n,
+
+		               // Reg Bus Interface Signal
+                       input logic           reg_cs,
+                       input logic           reg_wr,
+                       input logic [3:0]     reg_addr,
+                       input logic [31:0]    reg_wdata,
+                       input logic [3:0]     reg_be,
+
+                       // Outputs
+                       output logic [31:0]   reg_rdata,
+                       output logic          reg_ack,
+                   
+                       output  logic [31:0]  cfg_gpio_dir_sel, 
+                       input   logic [31:0]  pad_gpio_in,
+                       output  logic [31:0]  pad_gpio_out,
+
+                       output  logic         gpio_intr
+
+                ); 
+
+
+logic  [31:0]  gpio_prev_indata         ;// previously captured GPIO I/P pins data
+logic  [31:0]  cfg_gpio_out_data        ;// GPIO statuc O/P data from config reg
+logic  [31:0]  cfg_gpio_out_type        ;// GPIO Type, Unused
+logic  [31:0]  cfg_multi_func_sel       ;// GPIO Multi function type
+logic  [31:0]  cfg_gpio_posedge_int_sel ;// select posedge interrupt
+logic  [31:0]  cfg_gpio_negedge_int_sel ;// select negedge interrupt
+logic  [31:00] cfg_gpio_data_in         ;
+logic [31:0]   gpio_int_event           ;
+
+
+gpio_reg  u_reg (
+		       .mclk                         (mclk                    ),
+               .h_reset_n                    (h_reset_n               ),
+
+		       // Reg Bus Interface Signal
+               .reg_cs                       (reg_cs                  ),
+               .reg_wr                       (reg_wr                  ),
+               .reg_addr                     (reg_addr                ),
+               .reg_wdata                    (reg_wdata               ),
+               .reg_be                       (reg_be                  ),
+
+               // Outputs
+               .reg_rdata                    (reg_rdata               ),
+               .reg_ack                      (reg_ack                 ),
+
+            // GPIO input pins
+               .gpio_in_data                 (pad_gpio_in             ),
+               .gpio_prev_indata             (gpio_prev_indata        ),
+               .gpio_int_event               (gpio_int_event          ),
+
+            // GPIO config pins
+               .cfg_gpio_out_data            (cfg_gpio_out_data       ),
+               .cfg_gpio_dir_sel             (cfg_gpio_dir_sel        ),
+               .cfg_gpio_out_type            (cfg_gpio_out_type       ),
+               .cfg_gpio_posedge_int_sel     (cfg_gpio_posedge_int_sel),
+               .cfg_gpio_negedge_int_sel     (cfg_gpio_negedge_int_sel),
+               .cfg_multi_func_sel           (cfg_multi_func_sel      ),
+	           .cfg_gpio_data_in             (cfg_gpio_data_in        ),
+
+               .gpio_intr                    (gpio_intr               )
+
+
+                ); 
+
+
+gpio_intr_gen u_gpio_intr (
+   // System Signals
+   // Inputs
+          .mclk                    (mclk                    ),
+          .h_reset_n               (h_reset_n                ),
+
+   // GPIO cfg input pins
+          .gpio_prev_indata        (gpio_prev_indata        ),
+          .cfg_gpio_data_in        (cfg_gpio_data_in        ),
+          .cfg_gpio_dir_sel        (cfg_gpio_dir_sel        ),
+          .cfg_gpio_out_data       (cfg_gpio_out_data       ),
+          .cfg_gpio_posedge_int_sel(cfg_gpio_posedge_int_sel),
+          .cfg_gpio_negedge_int_sel(cfg_gpio_negedge_int_sel),
+
+
+   // GPIO output pins
+          .pad_gpio_out            (pad_gpio_out            ),
+          .gpio_int_event          (gpio_int_event          )  
+  );
+
+endmodule
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv
index e36556c..54c0ef9 100755
--- a/verilog/rtl/pinmux/src/pinmux.sv
+++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -17,13 +17,13 @@
 //
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
-////  Pinmux                                                     ////
+////  Pinmux                                                      ////
 ////                                                              ////
 ////  This file is part of the riscduino cores project            ////
 ////  https://github.com/dineshannayya/riscduino.git              ////
 ////                                                              ////
 ////  Description                                                 ////
-////      PinMux Manages all the pin multiplexing                 ////
+////      Manages all the pin multiplexing                        ////
 ////                                                              ////
 ////  To Do:                                                      ////
 ////    nothing                                                   ////
@@ -32,482 +32,9 @@
 ////      - Dinesh Annayya, dinesha@opencores.org                 ////
 ////                                                              ////
 ////  Revision :                                                  ////
-////    0.1 - 16th Feb 2021, Dinesh A                             ////
-////          initial version                                     ////
-////    0.2 - 6 April 2021, Dinesh A                              ////
-////          1. SSPI CS# increased from 1 to 4                   ////
-//            2. UART I/F increase from 1 to 2                    ////
-////    0.3 - 8 July 2022, Dinesh A                               ////
-////          In ardunio, SPI chip select are control through     ////
-////          GPIO, So we have moved the Auto generated SPI CS    ////
-////          different config bit. I2C config position moved from////
-////          bit[14] to bit [15]                                 ////
-////    0.4 - 20 July 2022, Dinesh A                              ////
-////         On Power On, If RESET* = 0, then system will enter   ////
-////         in to SPIS slave mode to support boot                ////
+////    0.1 - 16th Aug 2022, Dinesh A                             ////
+////          Seperated the pinmux from pinmux_top module         ////
 //////////////////////////////////////////////////////////////////////
-
-module pinmux (
-                    `ifdef USE_POWER_PINS
-                       input logic         vccd1,// User area 1 1.8V supply
-                       input logic         vssd1,// User area 1 digital ground
-                    `endif
-                        // clock skew adjust
-                       input logic [3:0]        cfg_cska_pinmux,
-                       input logic	        wbd_clk_int,
-                       output logic	        wbd_clk_pinmux,
-                       // System Signals
-                       // Inputs
-		       input logic             mclk,
-                       input logic             h_reset_n,
-
-                       // Global Reset control
-                       output logic  [1:0]     cpu_core_rst_n   ,
-                       output logic            cpu_intf_rst_n   ,
-                       output logic            qspim_rst_n      ,
-                       output logic            sspim_rst_n      ,
-                       output logic [1:0]      uart_rst_n       ,
-                       output logic            i2cm_rst_n       ,
-                       output logic            usb_rst_n        ,
-
-		       output logic [15:0]     cfg_riscv_ctrl,
-
-		       // Reg Bus Interface Signal
-                       input logic             reg_cs,
-                       input logic             reg_wr,
-                       input logic [7:0]       reg_addr,
-                       input logic [31:0]      reg_wdata,
-                       input logic [3:0]       reg_be,
-
-                       // Outputs
-                       output logic [31:0]     reg_rdata,
-                       output logic            reg_ack,
-
-		      // Risc configuration
-                       output logic [15:0]     irq_lines,
-                       output logic            soft_irq,
-                       output logic [2:0]      user_irq,
-		       input  logic            usb_intr,
-		       input  logic            i2cm_intr,
-
-                       // Digital IO
-                       output logic [37:0]     digital_io_out,
-                       output logic [37:0]     digital_io_oen,
-                       input  logic [37:0]     digital_io_in,
-
-		       // SFLASH I/F
-		       input  logic            sflash_sck,
-		       input  logic [3:0]      sflash_ss,
-		       input  logic [3:0]      sflash_oen,
-		       input  logic [3:0]      sflash_do,
-		       output logic [3:0]      sflash_di,
-
-		       // SSRAM I/F - Temp Masked
-		       //input  logic            ssram_sck,
-		       //input  logic            ssram_ss,
-		       //input  logic [3:0]      ssram_oen,
-		       //input  logic [3:0]      ssram_do,
-		       //output logic [3:0]      ssram_di,
-
-		       // USB I/F
-		       input   logic           usb_dp_o,
-		       input   logic           usb_dn_o,
-		       input   logic           usb_oen,
-		       output   logic          usb_dp_i,
-		       output   logic          usb_dn_i,
-
-		       // UART I/F
-		       input   logic  [1:0]    uart_txd,
-		       output  logic  [1:0]    uart_rxd,
-
-		       // I2CM I/F
-		       input   logic           i2cm_clk_o,
-		       output  logic           i2cm_clk_i,
-		       input   logic           i2cm_clk_oen,
-		       input   logic           i2cm_data_oen,
-		       input   logic           i2cm_data_o,
-		       output  logic           i2cm_data_i,
-
-		       // SPI MASTER
-		       input   logic           spim_sck,
-		       input   logic [3:0]     spim_ssn,
-		       input   logic           spim_miso,
-		       output  logic           spim_mosi,
-		       
-		       // SPI SLAVE
-		       output   logic           spis_sck,
-		       output   logic           spis_ssn,
-		       input    logic           spis_miso,
-		       output   logic           spis_mosi,
-
-                       // UART MASTER I/F
-                       output  logic            uartm_rxd ,
-                       input logic              uartm_txd  ,       
-
-		       output  logic           pulse1m_mclk,
-	               output  logic [31:0]    pinmux_debug,
-
-		       input   logic           dbg_clk_mon
-
-   ); 
-
-
-
-logic sreset_n;  // Sync Reset
-   
-/* clock pulse */
-//********************************************************
-logic           pulse_1us               ; // 1 UsSecond Pulse for waveform Generator
-logic           pulse_1ms               ; // 1 UsSecond Pulse for waveform Generator
-logic           pulse_1s                ; // 1Second Pulse for waveform Generator
-logic [9:0]     cfg_pulse_1us           ; // 1us pulse generation config
-
-
-//---------------------------------------------------------
-// Timer Register                          
-// -------------------------------------------------------
-logic [2:0]    cfg_timer_update        ; // CPU write to timer register
-logic [31:0]   cfg_timer0              ; // Timer-0 register
-logic [31:0]   cfg_timer1              ; // Timer-1 register
-logic [31:0]   cfg_timer2              ; // Timer-2 register
-logic [2:0]    timer_intr              ;
-
-//---------------------------------------------------
-// 6 PWM variabled
-//---------------------------------------------------
-
-logic [5:0]     pwm_wfm                 ;
-logic [5:0]     cfg_pwm_enb             ;
-logic [15:0]    cfg_pwm0_high           ;
-logic [15:0]    cfg_pwm0_low            ;
-logic [15:0]    cfg_pwm1_high           ;
-logic [15:0]    cfg_pwm1_low            ;
-logic [15:0]    cfg_pwm2_high           ;
-logic [15:0]    cfg_pwm2_low            ;
-logic [15:0]    cfg_pwm3_high           ;
-logic [15:0]    cfg_pwm3_low            ;
-logic [15:0]    cfg_pwm4_high           ;
-logic [15:0]    cfg_pwm4_low            ;
-logic [15:0]    cfg_pwm5_high           ;
-logic [15:0]    cfg_pwm5_low            ;
-
-
-wire  [31:0]  gpio_prev_indata         ;// previously captured GPIO I/P pins data
-wire  [31:0]  cfg_gpio_out_data        ;// GPIO statuc O/P data from config reg
-wire  [31:0]  cfg_gpio_dir_sel         ;// decides on GPIO pin is I/P or O/P at pad level, 0 -> Input, 1 -> Output
-wire  [31:0]  cfg_gpio_out_type        ;// GPIO Type, Unused
-wire  [31:0]  cfg_multi_func_sel       ;// GPIO Multi function type
-wire  [31:0]  cfg_gpio_posedge_int_sel ;// select posedge interrupt
-wire  [31:0]  cfg_gpio_negedge_int_sel ;// select negedge interrupt
-wire  [31:00] cfg_gpio_data_in         ;
-
-
-reg [7:0]     port_a_in;      // PORT A Data In
-reg [7:0]     port_b_in;      // PORT B Data In
-reg [7:0]     port_c_in;      // PORT C Data In
-reg [7:0]     port_d_in;      // PORT D Data In
-
-wire [7:0]    port_a_out;     // PORT A Data Out
-wire [7:0]    port_b_out;     // PORT B Data Out
-wire [7:0]    port_c_out;     // PORT C Data Out
-wire [7:0]    port_d_out;     // PORT D Data Out
-wire [31:0]   pad_gpio_in;    // GPIO data input from PAD
-wire [31:0]   pad_gpio_out;   // GPIO Data out towards PAD
-wire [31:0]   gpio_int_event; // GPIO Interrupt indication
-reg [1:0]     ext_intr_in;    // External PAD level interrupt
-
-// GPIO to PORT Mapping
-assign      pad_gpio_in[7:0]     = port_a_in;
-assign      pad_gpio_in[15:8]    = port_b_in;
-assign      pad_gpio_in[23:16]   = port_c_in;
-assign      pad_gpio_in[31:24]   = port_d_in;
-
-assign      port_a_out           = pad_gpio_out[7:0];
-assign      port_b_out           = pad_gpio_out[15:8];
-assign      port_c_out           = pad_gpio_out[23:16];
-assign      port_d_out           = pad_gpio_out[31:24];
-
-assign      pinmux_debug = '0; // Todo: Need to fix
-
-// SSRAM I/F - Temp masked
-//input  logic            ssram_sck,
-//input  logic            ssram_ss,
-//input  logic [3:0]      ssram_oen,
-//input  logic [3:0]      ssram_do,
-//output logic [3:0]      ssram_di,
-
-// pinmux clock skew control
-clk_skew_adjust u_skew_pinmux
-       (
-`ifdef USE_POWER_PINS
-               .vccd1      (vccd1                      ),// User area 1 1.8V supply
-               .vssd1      (vssd1                      ),// User area 1 digital ground
-`endif
-	       .clk_in     (wbd_clk_int                 ), 
-	       .sel        (cfg_cska_pinmux             ), 
-	       .clk_out    (wbd_clk_pinmux              ) 
-       );
-
-reset_sync  u_rst_sync (
-	      .scan_mode  (1'b0        ),
-              .dclk       (mclk        ), // Destination clock domain
-	      .arst_n     (h_reset_n   ), // active low async reset
-              .srst_n     (sreset_n    )
-          );
-
-gpio_intr_gen u_gpio_intr (
-   // System Signals
-   // Inputs
-          .mclk                    (mclk                    ),
-          .h_reset_n               (sreset_n                ),
-
-   // GPIO cfg input pins
-          .gpio_prev_indata        (gpio_prev_indata        ),
-          .cfg_gpio_data_in        (cfg_gpio_data_in        ),
-          .cfg_gpio_dir_sel        (cfg_gpio_dir_sel        ),
-          .cfg_gpio_out_data       (cfg_gpio_out_data       ),
-          .cfg_gpio_posedge_int_sel(cfg_gpio_posedge_int_sel),
-          .cfg_gpio_negedge_int_sel(cfg_gpio_negedge_int_sel),
-
-
-   // GPIO output pins
-          .pad_gpio_out            (pad_gpio_out            ),
-          .gpio_int_event          (gpio_int_event          )  
-  );
-
-
-// 1us pulse
-pulse_gen_type2  #(.WD(10)) u_pulse_1us (
-
-	.clk_pulse_o               (pulse_1us        ),
-	.clk                       (mclk             ),
-        .reset_n                   (sreset_n         ),
-	.cfg_max_cnt               (cfg_pulse_1us    )
-
-     );
-
-// 1millisecond pulse
-pulse_gen_type1 u_pulse_1ms (
-
-	.clk_pulse_o               (pulse_1ms       ),
-	.clk                       (mclk            ),
-        .reset_n                   (sreset_n        ),
-	.trigger                   (pulse_1us       )
-
-      );
-
-// 1 second pulse
-pulse_gen_type1 u_pulse_1s (
-
-	.clk_pulse_o               (pulse_1s    ),
-	.clk                       (mclk        ),
-        .reset_n                   (sreset_n    ),
-	.trigger                   (pulse_1ms   )
-
-       );
-
-
-// Timer
-
-wire       cfg_timer0_enb    = cfg_timer0[16];
-wire [1:0] cfg_timer0_clksel = cfg_timer0[18:17];
-wire [15:0] cfg_timer0_compare = cfg_timer0[15:0];
-
-timer  u_timer_0
-  (
-     .reset_n                      (sreset_n             ),// system syn reset
-     .mclk                         (mclk                 ),// master clock
-     .pulse_1us                    (pulse_1us            ),
-     .pulse_1ms                    (pulse_1ms            ),
-     .pulse_1s                     (pulse_1s             ),
-
-     .cfg_timer_update             (cfg_timer_update[0]  ), 
-     .cfg_timer_enb                (cfg_timer0_enb       ),     
-     .cfg_timer_compare            (cfg_timer0_compare   ),
-     .cfg_timer_clksel             (cfg_timer0_clksel    ),// to select the timer 1us/1ms reference clock
-
-     .timer_intr                   (timer_intr[0]         )
-   );
-
-// Timer
-wire       cfg_timer1_enb      = cfg_timer1[16];
-wire [1:0] cfg_timer1_clksel   = cfg_timer1[18:17];
-wire [15:0] cfg_timer1_compare = cfg_timer1[15:0];
-timer  u_timer_1
-  (
-     .reset_n                      (sreset_n             ),// system syn reset
-     .mclk                         (mclk                 ),// master clock
-     .pulse_1us                    (pulse_1us            ),
-     .pulse_1ms                    (pulse_1ms            ),
-     .pulse_1s                     (pulse_1s             ),
-
-     .cfg_timer_update             (cfg_timer_update[1]  ), 
-     .cfg_timer_enb                (cfg_timer1_enb       ),     
-     .cfg_timer_compare            (cfg_timer1_compare   ),
-     .cfg_timer_clksel             (cfg_timer1_clksel    ),// to select the timer 1us/1ms reference clock
-
-     .timer_intr                   (timer_intr[1]         )
-   );
-
-// Timer
-wire       cfg_timer2_enb    = cfg_timer2[16];
-wire [1:0] cfg_timer2_clksel = cfg_timer2[18:17];
-wire [15:0] cfg_timer2_compare = cfg_timer2[15:0];
-timer  u_timer_2
-  (
-     .reset_n                      (sreset_n             ),// system syn reset
-     .mclk                         (mclk                 ),// master clock
-     .pulse_1us                    (pulse_1us            ),
-     .pulse_1ms                    (pulse_1ms            ),
-     .pulse_1s                     (pulse_1s             ),
-
-     .cfg_timer_update             (cfg_timer_update[2]  ), 
-     .cfg_timer_enb                (cfg_timer2_enb       ),     
-     .cfg_timer_compare            (cfg_timer2_compare   ),
-     .cfg_timer_clksel             (cfg_timer2_clksel    ),// to select the timer 1us/1ms reference clock
-
-     .timer_intr                   (timer_intr[2]        )
-   );
-
-
-pinmux_reg u_pinmux_reg(
-      // System Signals
-      // Inputs
-          .mclk                         (mclk                    ),
-          .h_reset_n                    (sreset_n                ),
-
-          .cpu_core_rst_n               (cpu_core_rst_n          ),
-          .cpu_intf_rst_n               (cpu_intf_rst_n          ),
-          .qspim_rst_n                  (qspim_rst_n             ),
-          .sspim_rst_n                  (sspim_rst_n             ),
-          .uart_rst_n                   (uart_rst_n              ),
-          .i2cm_rst_n                   (i2cm_rst_n              ),
-          .usb_rst_n                    (usb_rst_n               ),
-
-	  .cfg_riscv_ctrl               (cfg_riscv_ctrl          ),
-
-
-      // Reg read/write Interface Inputs
-          .reg_cs                       (reg_cs                  ),
-          .reg_wr                       (reg_wr                  ),
-          .reg_addr                     (reg_addr                ),
-          .reg_wdata                    (reg_wdata               ),
-          .reg_be                       (reg_be                  ),
-
-          .reg_rdata                    (reg_rdata               ),
-          .reg_ack                      (reg_ack                 ),
-
-	  .ext_intr_in                  (ext_intr_in             ),
-
-	  .irq_lines                    (irq_lines               ),
-	  .soft_irq                     (soft_irq                ),
-	  .user_irq                     (user_irq                ),
-          .usb_intr                     (usb_intr                ),
-          .i2cm_intr                    (i2cm_intr               ),
-
-	  .cfg_pulse_1us                (cfg_pulse_1us           ),
-
-
-          .cfg_pwm0_high                (cfg_pwm0_high           ),
-          .cfg_pwm0_low                 (cfg_pwm0_low            ),
-          .cfg_pwm1_high                (cfg_pwm1_high           ),
-          .cfg_pwm1_low                 (cfg_pwm1_low            ),
-          .cfg_pwm2_high                (cfg_pwm2_high           ),
-          .cfg_pwm2_low                 (cfg_pwm2_low            ),
-          .cfg_pwm3_high                (cfg_pwm3_high           ),
-          .cfg_pwm3_low                 (cfg_pwm3_low            ),
-          .cfg_pwm4_high                (cfg_pwm4_high           ),
-          .cfg_pwm4_low                 (cfg_pwm4_low            ),
-          .cfg_pwm5_high                (cfg_pwm5_high           ),
-          .cfg_pwm5_low                 (cfg_pwm5_low            ),
-
-      // GPIO input pins
-          .gpio_in_data                 (pad_gpio_in             ),
-          .gpio_int_event               (gpio_int_event          ),
-
-      // GPIO config pins
-          .cfg_gpio_out_data            (cfg_gpio_out_data       ),
-          .cfg_gpio_dir_sel             (cfg_gpio_dir_sel        ),
-          .cfg_gpio_out_type            (cfg_gpio_out_type       ),
-          .cfg_gpio_posedge_int_sel     (cfg_gpio_posedge_int_sel),
-          .cfg_gpio_negedge_int_sel     (cfg_gpio_negedge_int_sel),
-          .cfg_multi_func_sel           (cfg_multi_func_sel      ),
-	  .cfg_gpio_data_in             (cfg_gpio_data_in        ),
-
-
-       // Outputs
-          .gpio_prev_indata             (gpio_prev_indata        ) ,
-
-
-          .timer_intr                   (timer_intr             ),
-          .cfg_timer_update             (cfg_timer_update       ),
-          .cfg_timer0                   (cfg_timer0             ),
-          .cfg_timer1                   (cfg_timer1             ),
-          .cfg_timer2                   (cfg_timer2             )
-
-
-   ); 
-
-
-// 6 PWM Waveform Generator
-pwm  u_pwm_0 (
-	  .waveform                    (pwm_wfm[0]         ), 
-	  .h_reset_n                   (sreset_n           ),
-	  .mclk                        (mclk               ),
-	  .pulse1m_mclk                (pulse_1ms          ),
-	  .cfg_pwm_enb                 (cfg_pwm_enb[0]     ),
-	  .cfg_pwm_high                (cfg_pwm0_high      ),
-	  .cfg_pwm_low                 (cfg_pwm0_low       )
-     );
-
-pwm  u_pwm_1 (
-	  .waveform                    (pwm_wfm[1]         ), 
-	  .h_reset_n                   (sreset_n           ),
-	  .mclk                        (mclk               ),
-	  .pulse1m_mclk                (pulse_1ms          ),
-	  .cfg_pwm_enb                 (cfg_pwm_enb[1]     ),
-	  .cfg_pwm_high                (cfg_pwm1_high      ),
-	  .cfg_pwm_low                 (cfg_pwm1_low       )
-     );
-   
-pwm  u_pwm_2 (
-	  .waveform                    (pwm_wfm[2]         ), 
-	  .h_reset_n                   (sreset_n           ),
-	  .mclk                        (mclk               ),
-	  .pulse1m_mclk                (pulse_1ms          ),
-	  .cfg_pwm_enb                 (cfg_pwm_enb[2]     ),
-	  .cfg_pwm_high                (cfg_pwm2_high      ),
-	  .cfg_pwm_low                 (cfg_pwm2_low       )
-     );
-
-pwm  u_pwm_3 (
-	  .waveform                    (pwm_wfm[3]         ), 
-	  .h_reset_n                   (sreset_n           ),
-	  .mclk                        (mclk               ),
-	  .pulse1m_mclk                (pulse_1ms          ),
-	  .cfg_pwm_enb                 (cfg_pwm_enb[3]     ),
-	  .cfg_pwm_high                (cfg_pwm3_high      ),
-	  .cfg_pwm_low                 (cfg_pwm3_low       )
-     );
-pwm  u_pwm_4 (
-	  .waveform                    (pwm_wfm[4]         ), 
-	  .h_reset_n                   (sreset_n           ),
-	  .mclk                        (mclk               ),
-	  .pulse1m_mclk                (pulse_1ms          ),
-	  .cfg_pwm_enb                 (cfg_pwm_enb[4]     ),
-	  .cfg_pwm_high                (cfg_pwm4_high      ),
-	  .cfg_pwm_low                 (cfg_pwm4_low       )
-     );
-pwm  u_pwm_5 (
-	  .waveform                    (pwm_wfm[5]         ), 
-	  .h_reset_n                   (sreset_n           ),
-	  .mclk                        (mclk               ),
-	  .pulse1m_mclk                (pulse_1ms          ),
-	  .cfg_pwm_enb                 (cfg_pwm_enb[5]     ),
-	  .cfg_pwm_high                (cfg_pwm5_high      ),
-	  .cfg_pwm_low                 (cfg_pwm5_low       )
-     );
-
 /************************************************
 * Pin Mapping    ATMGE CONFIG
 *   ATMEGA328                        caravel Pin Mapping
@@ -559,6 +86,99 @@
 * Pin-1 RESET is not supported as there is no suppport for fuse config
 **************/
 
+module pinmux (
+               // Digital IO
+               output logic [37:0]     digital_io_out          ,
+               output logic [37:0]     digital_io_oen          ,
+               input  logic [37:0]     digital_io_in           ,
+
+               // Config
+               input logic  [31:0]    cfg_gpio_dir_sel         ,
+               input logic  [31:0]    cfg_multi_func_sel       ,
+
+               output logic[5:0]       cfg_pwm_enb             ,
+               input logic [5:0]       pwm_wfm                 ,
+               output logic [1:0]      ext_intr_in             ,  // External PAD level interrupt
+               output  logic [31:0]    pad_gpio_in             ,  // GPIO data input from PAD
+               input  logic [31:0]     pad_gpio_out            ,  // GPIO Data out towards PAD
+
+		       // SFLASH I/F
+		       input  logic            sflash_sck              ,
+		       input  logic [3:0]      sflash_ss               ,
+		       input  logic [3:0]      sflash_oen              ,
+		       input  logic [3:0]      sflash_do               ,
+		       output logic [3:0]      sflash_di               ,
+
+		       // SSRAM I/F - Temp Masked
+		       //input  logic            ssram_sck,
+		       //input  logic            ssram_ss,
+		       //input  logic [3:0]      ssram_oen,
+		       //input  logic [3:0]      ssram_do,
+		       //output logic [3:0]      ssram_di,
+
+		       // USB I/F
+		       input   logic           usb_dp_o,
+		       input   logic           usb_dn_o,
+		       input   logic           usb_oen,
+		       output   logic          usb_dp_i,
+		       output   logic          usb_dn_i,
+
+		       // UART I/F
+		       input   logic  [1:0]    uart_txd,
+		       output  logic  [1:0]    uart_rxd,
+
+		       // I2CM I/F
+		       input   logic           i2cm_clk_o,
+		       output  logic           i2cm_clk_i,
+		       input   logic           i2cm_clk_oen,
+		       input   logic           i2cm_data_oen,
+		       input   logic           i2cm_data_o,
+		       output  logic           i2cm_data_i,
+
+		       // SPI MASTER
+		       input   logic           spim_sck,
+		       input   logic [3:0]     spim_ssn,
+		       input   logic           spim_miso,
+		       output  logic           spim_mosi,
+		       
+		       // SPI SLAVE
+		       output   logic           spis_sck,
+		       output   logic           spis_ssn,
+		       input    logic           spis_miso,
+		       output   logic           spis_mosi,
+
+               // UART MASTER I/F
+               output  logic            uartm_rxd ,
+               input logic              uartm_txd ,       
+
+		       input   logic           dbg_clk_mon
+
+   ); 
+
+
+
+reg [7:0]     port_a_in;      // PORT A Data In
+reg [7:0]     port_b_in;      // PORT B Data In
+reg [7:0]     port_c_in;      // PORT C Data In
+reg [7:0]     port_d_in;      // PORT D Data In
+
+wire [7:0]    port_a_out;     // PORT A Data Out
+wire [7:0]    port_b_out;     // PORT B Data Out
+wire [7:0]    port_c_out;     // PORT C Data Out
+wire [7:0]    port_d_out;     // PORT D Data Out
+
+// GPIO to PORT Mapping
+assign      pad_gpio_in[7:0]     = port_a_in;
+assign      pad_gpio_in[15:8]    = port_b_in;
+assign      pad_gpio_in[23:16]   = port_c_in;
+assign      pad_gpio_in[31:24]   = port_d_in;
+
+assign      port_a_out           = pad_gpio_out[7:0];
+assign      port_b_out           = pad_gpio_out[15:8];
+assign      port_c_out           = pad_gpio_out[23:16];
+assign      port_d_out           = pad_gpio_out[31:24];
+
+
 assign      cfg_pwm_enb          = cfg_multi_func_sel[5:0];
 wire [1:0]  cfg_int_enb          = cfg_multi_func_sel[7:6];
 wire [1:0]  cfg_uart_enb         = cfg_multi_func_sel[9:8];
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv
deleted file mode 100644
index 744c07b..0000000
--- a/verilog/rtl/pinmux/src/pinmux_reg.sv
+++ /dev/null
@@ -1,902 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//      http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
-//
-//////////////////////////////////////////////////////////////////////
-////                                                              ////
-////  Pinmux Register                                             ////
-////                                                              ////
-////  This file is part of the riscduino cores project            ////
-////  https://github.com/dineshannayya/riscduino.git              ////
-////                                                              ////
-////  Description                                                 ////
-////      Hold all the Global and PinMux Register                 ////
-////                                                              ////
-////  To Do:                                                      ////
-////    nothing                                                   ////
-////                                                              ////
-////  Author(s):                                                  ////
-////      - Dinesh Annayya, dinesha@opencores.org                 ////
-////                                                              ////
-////  Revision :                                                  ////
-////    0.1 - 16th Feb 2021, Dinesh A                             ////
-////          initial version                                     ////
-//////////////////////////////////////////////////////////////////////
-//
-module pinmux_reg (
-                       // System Signals
-                       // Inputs
-		       input logic             mclk,
-                       input logic             h_reset_n,
-
-                       // Global Reset control
-                       output logic  [1:0]     cpu_core_rst_n   ,
-                       output logic            cpu_intf_rst_n   ,
-                       output logic            qspim_rst_n      ,
-                       output logic            sspim_rst_n      ,
-                       output logic  [1:0]     uart_rst_n       ,
-                       output logic            i2cm_rst_n       ,
-                       output logic            usb_rst_n        ,
-
-		       // Reg Bus Interface Signal
-                       input logic             reg_cs,
-                       input logic             reg_wr,
-                       input logic [7:0]       reg_addr,
-                       input logic [31:0]      reg_wdata,
-                       input logic [3:0]       reg_be,
-
-                       // Outputs
-                       output logic [31:0]     reg_rdata,
-                       output logic            reg_ack,
-
-		       input  logic [1:0]      ext_intr_in,
-
-		      // Risc configuration
-                       output logic [15:0]     irq_lines,
-                       output logic            soft_irq,
-                       output logic [2:0]      user_irq,
-		       input  logic            usb_intr,
-		       input  logic            i2cm_intr,
-
-                       output logic [9:0]      cfg_pulse_1us,
-		       output logic [15:0]     cfg_riscv_ctrl,
-		       
-                       //---------------------------------------------------
-                       // 6 PWM Configuration
-                       //---------------------------------------------------
-                       
-                       output logic [15:0]    cfg_pwm0_high           ,
-                       output logic [15:0]    cfg_pwm0_low            ,
-                       output logic [15:0]    cfg_pwm1_high           ,
-                       output logic [15:0]    cfg_pwm1_low            ,
-                       output logic [15:0]    cfg_pwm2_high           ,
-                       output logic [15:0]    cfg_pwm2_low            ,
-                       output logic [15:0]    cfg_pwm3_high           ,
-                       output logic [15:0]    cfg_pwm3_low            ,
-                       output logic [15:0]    cfg_pwm4_high           ,
-                       output logic [15:0]    cfg_pwm4_low            ,
-                       output logic [15:0]    cfg_pwm5_high           ,
-                       output logic [15:0]    cfg_pwm5_low            ,
-
-                // GPIO input pins
-                       input  logic [31:0]     gpio_in_data   ,// GPIO I/P pins
-                       input  logic [31:0]     gpio_int_event ,// from gpio control blk
-
-
-
-                // GPIO config pins
-                       output  logic [31:0]     cfg_gpio_out_data        ,// to the GPIO control block 
-                       output  logic [31:0]     cfg_gpio_data_in         ,// GPIO I/P pins data captured into this
-                       output  logic [31:0]     cfg_gpio_dir_sel         ,// decides on GPIO pin is I/P or O/P at pad level
-                       output  logic [31:0]     cfg_gpio_out_type        ,// O/P is static , '1' : waveform
-                       output  logic [31:0]     cfg_gpio_posedge_int_sel ,// select posedge interrupt
-                       output  logic [31:0]     cfg_gpio_negedge_int_sel ,// select negedge interrupt
-                       output  logic [31:0]     cfg_multi_func_sel       ,// multifunction pins
-                        
-                       // Outputs
-                       output logic [31:0]      gpio_prev_indata         ,// prv data from GPIO I/P pins
-
-		       input   logic [2:0]      timer_intr               ,
-                       output  logic [2:0]      cfg_timer_update         ,
-                       output  logic [31:0]     cfg_timer0               ,      
-                       output  logic [31:0]     cfg_timer1               ,      
-                       output  logic [31:0]     cfg_timer2               
-   ); 
-
-
-                       
-//-----------------------------------------------------------------------
-// Internal Wire Declarations
-//-----------------------------------------------------------------------
-
-logic          sw_rd_en               ;
-logic          sw_wr_en;
-logic [4:0]    sw_addr; // addressing 16 registers
-logic [31:0]   sw_reg_wdata;
-logic [3:0]    wr_be  ;
-
-logic [31:0]   reg_out;
-logic  [31:0]   reg_0; // Chip ID
-logic  [31:0]   reg_1; // Risc Fuse Id
-logic  [31:0]   reg_2; // Global config-1
-logic  [31:0]   reg_3; // Global config-2
-logic [31:0]    reg_4; // GPIO Read Data
-logic [31:0]    reg_5; // GPIO Output Data
-logic [31:0]    reg_6; // GPIO Dir Sel
-logic [31:0]    reg_7; // GPIO Type
-logic [31:0]    reg_8; // Interrupt
-logic [31:0]    reg_9; // GPIO Interrupt Status
-logic  [31:0]   reg_10; // GPIO Interrupt Status
-logic [31:0]    reg_11; // GPIO Interrupt Mask
-logic [31:0]    reg_12; // GPIO Posedge Interrupt Select
-logic [31:0]    reg_13; // GPIO Negedge Interrupt Select
-logic [31:0]    reg_14; // Software-Reg_14
-logic [31:0]    reg_15; // Software-Reg_15
-logic [31:0]    reg_16; // PWN-0 Config
-logic [31:0]    reg_17; // PWN-1 Config
-logic [31:0]    reg_18; // PWN-2 Config
-logic [31:0]    reg_19; // PWN-3 Config
-logic [31:0]    reg_20; // PWN-4 Config
-logic [31:0]    reg_21; // PWN-5 Config
-logic [31:0]    reg_22; // Software-Reg1
-logic [31:0]    reg_23; // Software-Reg2
-logic [31:0]    reg_24; // Software-Reg3
-logic [31:0]    reg_25; // Software-Reg4
-logic [31:0]    reg_26; // Software-Reg5
-logic [31:0]    reg_27; // Software-Reg6
-logic [31:0]    reg_28; // Software-Reg6
-logic [31:0]    reg_29; // Software-Reg6
-logic [31:0]    reg_30; // Software-Reg6
-
-
-logic           cs_int;
-logic           gpio_intr;
-
-
-assign       sw_addr       = reg_addr [6:2];
-assign       sw_rd_en      = reg_cs & !reg_wr;
-assign       sw_wr_en      = reg_cs & reg_wr;
-assign       wr_be         = reg_be;
-assign       sw_reg_wdata  = reg_wdata;
-
-
-//-----------------------------------
-// Edge detection for Logic Bist
-// ----------------------------------
-
-logic wb_req;
-logic wb_req_d;
-logic wb_req_pedge;
-
-always_ff @(negedge h_reset_n or posedge mclk) begin
-    if ( h_reset_n == 1'b0 ) begin
-        wb_req    <= '0;
-	wb_req_d  <= '0;
-   end else begin
-       wb_req   <= reg_cs && (reg_ack == 0) ;
-       wb_req_d <= wb_req;
-   end
-end
-
-// Detect pos edge of request
-assign wb_req_pedge = (wb_req_d ==0) && (wb_req==1'b1);
-
-
-always @ (posedge mclk or negedge h_reset_n)
-begin : preg_out_Seq
-   if (h_reset_n == 1'b0) begin
-      reg_rdata  <= 'h0;
-      reg_ack    <= 1'b0;
-   end else if (reg_cs && !reg_ack) begin
-      reg_rdata <= reg_out ;
-      reg_ack   <= 1'b1;
-   end else begin
-      reg_ack        <= 1'b0;
-   end
-end
-
-
-
-//-----------------------------------------------------------------------
-// register read enable and write enable decoding logic
-//-----------------------------------------------------------------------
-wire   sw_wr_en_0 = sw_wr_en  & (sw_addr == 5'h0);
-wire   sw_wr_en_1 = sw_wr_en  & (sw_addr == 5'h1);
-wire   sw_wr_en_2 = sw_wr_en  & (sw_addr == 5'h2);
-wire   sw_wr_en_3 = sw_wr_en  & (sw_addr == 5'h3);
-wire   sw_wr_en_4 = sw_wr_en  & (sw_addr == 5'h4);
-wire   sw_wr_en_5 = sw_wr_en  & (sw_addr == 5'h5);
-wire   sw_wr_en_6 = sw_wr_en  & (sw_addr == 5'h6);
-wire   sw_wr_en_7 = sw_wr_en  & (sw_addr == 5'h7);
-wire   sw_wr_en_8 = sw_wr_en  & (sw_addr == 5'h8);
-wire   sw_wr_en_9 = sw_wr_en  & (sw_addr == 5'h9);
-wire   sw_wr_en_10 = sw_wr_en & (sw_addr == 5'hA);
-wire   sw_wr_en_11 = sw_wr_en & (sw_addr == 5'hB);
-wire   sw_wr_en_12 = sw_wr_en & (sw_addr == 5'hC);
-wire   sw_wr_en_13 = sw_wr_en & (sw_addr == 5'hD);
-wire   sw_wr_en_14 = sw_wr_en & (sw_addr == 5'hE);
-wire   sw_wr_en_15 = sw_wr_en & (sw_addr == 5'hF);
-wire   sw_wr_en_16 = sw_wr_en & (sw_addr == 5'h10);
-wire   sw_wr_en_17 = sw_wr_en & (sw_addr == 5'h11);
-wire   sw_wr_en_18 = sw_wr_en & (sw_addr == 5'h12);
-wire   sw_wr_en_19 = sw_wr_en & (sw_addr == 5'h13);
-wire   sw_wr_en_20 = sw_wr_en & (sw_addr == 5'h14);
-wire   sw_wr_en_21 = sw_wr_en & (sw_addr == 5'h15);
-
-wire   sw_wr_en_22 = sw_wr_en & (sw_addr == 5'h16);
-wire   sw_wr_en_23 = sw_wr_en & (sw_addr == 5'h17);
-wire   sw_wr_en_24 = sw_wr_en & (sw_addr == 5'h18);
-wire   sw_wr_en_25 = sw_wr_en & (sw_addr == 5'h19);
-wire   sw_wr_en_26 = sw_wr_en & (sw_addr == 5'h1A);
-wire   sw_wr_en_27 = sw_wr_en & (sw_addr == 5'h1B);
-wire   sw_wr_en_28 = sw_wr_en & (sw_addr == 5'h1C);
-wire   sw_wr_en_29 = sw_wr_en & (sw_addr == 5'h1D);
-wire   sw_wr_en_30 = sw_wr_en & (sw_addr == 5'h1E);
-wire   sw_wr_en_31 = sw_wr_en & (sw_addr == 5'h1F);
-
-wire   sw_rd_en_28 = sw_rd_en & (sw_addr == 5'h1C);
-wire   sw_rd_en_29 = sw_rd_en & (sw_addr == 5'h1D);
-wire   sw_rd_en_30 = sw_rd_en & (sw_addr == 5'h1E);
-wire   sw_rd_en_31 = sw_rd_en & (sw_addr == 5'h1F);
-
-
-//-----------------------------------------------------------------------
-// Individual register assignments
-//-----------------------------------------------------------------------
-
-
-// Chip ID
-// chip-id[3:0] mapping
-//    0 -  YIFIVE (MPW-2)
-//    1 -  Riscdunio (MPW-3)
-//    2 -  Riscdunio (MPW-4)
-//    3 -  Riscdunio (MPW-5)
-
-wire [15:0] manu_id      =  16'h8268; // Asci value of RD
-wire [3:0]  total_core   =  4'h2;
-wire [3:0]  chip_id      =  4'h3;
-wire [7:0]  chip_rev     =  8'h01;
-
-assign reg_0 = {manu_id,total_core,chip_id,chip_rev};
-
-
-//------------------------------------------
-// reg-2: GLBL_CFG_0
-//------------------------------------------
-wire [31:0] cfg_glb_ctrl = reg_1;
-
-ctech_buf u_buf_cpu_intf_rst  (.A(cfg_glb_ctrl[0]),.X(cpu_intf_rst_n));
-ctech_buf u_buf_qspim_rst     (.A(cfg_glb_ctrl[1]),.X(qspim_rst_n));
-ctech_buf u_buf_sspim_rst     (.A(cfg_glb_ctrl[2]),.X(sspim_rst_n));
-ctech_buf u_buf_uart0_rst     (.A(cfg_glb_ctrl[3]),.X(uart_rst_n[0]));
-ctech_buf u_buf_i2cm_rst      (.A(cfg_glb_ctrl[4]),.X(i2cm_rst_n));
-ctech_buf u_buf_usb_rst       (.A(cfg_glb_ctrl[5]),.X(usb_rst_n));
-ctech_buf u_buf_uart1_rst     (.A(cfg_glb_ctrl[6]),.X(uart_rst_n[1]));
-
-ctech_buf u_buf_cpu0_rst      (.A(cfg_glb_ctrl[8]),.X(cpu_core_rst_n[0]));
-ctech_buf u_buf_cpu1_rst      (.A(cfg_glb_ctrl[9]),.X(cpu_core_rst_n[1]));
-
-gen_32b_reg  #(32'h0) u_reg_1	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_1    ),
-	      .we         (wr_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_1         )
-	      );
-
-//----------------------------------------------
-// reg-2: GLBL_CFG_1
-//------------------------------------------
-
-gen_32b_reg  #(32'h0) u_reg_2	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_2    ),
-	      .we         (wr_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_2         )
-	      );
-
-assign cfg_pulse_1us       = reg_2[9:0];
-assign cfg_riscv_ctrl      = reg_2[31:16];
-
-//-----------------------------------------------------------------------
-//   reg-3 : Global Interrupt Mask
-//-----------------------------------------------------------------------
-
-gen_32b_reg  #(32'h0) u_reg_3	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_3    ),
-	      .we         (wr_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_3         )
-	      );
-
-//-----------------------------------------------------------------------
-//   reg-4 : Global Interrupt Status
-//-----------------------------------------------------------------
-assign  irq_lines     = reg_3[15:0] & reg_4[15:0]; 
-assign  soft_irq      = reg_3[16]   & reg_4[16]; 
-assign  user_irq      = reg_3[19:17]& reg_4[19:17]; 
-
-
-generic_register #(8,0  ) u_reg4_be0 (
-	      .we            ({8{sw_wr_en_4 & 
-                                 wr_be[0]   }}   ),		 
-	      .data_in       (sw_reg_wdata[7:0]  ),
-	      .reset_n       (h_reset_n          ),
-	      .clk           (mclk               ),
-	      
-	      //List of Outs
-	      .data_out      (reg_4[7:0]         )
-          );
-
-
-wire [7:0] hware_intr_req = {gpio_intr, ext_intr_in[1:0], usb_intr, i2cm_intr,timer_intr[2:0]};
-
-generic_intr_stat_reg #(.WD(8),
-	                .RESET_DEFAULT(0)) u_reg4_be1 (
-		 //inputs
-		 .clk         (mclk              ),
-		 .reset_n     (h_reset_n         ),
-	         .reg_we      ({8{sw_wr_en_4 & reg_ack & 
-                                 wr_be[1]   }}  ),		 
-		 .reg_din    (sw_reg_wdata[15:8] ),
-		 .hware_req  (hware_intr_req     ),
-		 
-		 //outputs
-		 .data_out    (reg_4[15:8]       )
-	      );
-
-
-
-generic_register #(4,0  ) u_reg4_be2 (
-	      .we            ({4{sw_wr_en_4 & 
-                                 wr_be[2]   }}  ),		 
-	      .data_in       (sw_reg_wdata[19:16]),
-	      .reset_n       (h_reset_n           ),
-	      .clk           (mclk              ),
-	      
-	      //List of Outs
-	      .data_out      (reg_4[19:16]        )
-          );
-
-assign reg_4[31:20] = '0;
-
-
-//-----------------------------------------------------------------------
-// Logic for gpio_data_in 
-//-----------------------------------------------------------------------
-logic [31:0] gpio_in_data_s;
-logic [31:0] gpio_in_data_ss;
-// Double Sync the gpio pin data for edge detection
-always @ (posedge mclk or negedge h_reset_n)
-begin 
-  if (h_reset_n == 1'b0) begin
-    reg_5  <= 'h0 ;
-    gpio_in_data_s  <= 32'd0;
-    gpio_in_data_ss <= 32'd0;
-  end
-  else begin
-    gpio_in_data_s   <= gpio_in_data;
-    gpio_in_data_ss <= gpio_in_data_s;
-    reg_5           <= gpio_in_data_ss;
-  end
-end
-
-
-assign cfg_gpio_data_in = reg_5[31:0]; // to be used for edge interrupt detect
-assign gpio_prev_indata = gpio_in_data_ss;
-
-//-----------------------------------------------------------------------
-// Logic for cfg_gpio_out_data 
-//-----------------------------------------------------------------------
-assign cfg_gpio_out_data = reg_6[31:0]; // data to the GPIO control blk 
-
-gen_32b_reg  #(32'h0) u_reg_6	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_6    ),
-	      .we         (wr_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_6         )
-	      );
-//-----------------------------------------------------------------------
-// Logic for cfg_gpio_dir_sel 
-//-----------------------------------------------------------------------
-assign cfg_gpio_dir_sel = reg_7[31:0]; // data to the GPIO O/P pins 
-
-gen_32b_reg  #(32'h0) u_reg_7	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_7    ),
-	      .we         (wr_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_7         )
-	      );
-//-----------------------------------------------------------------------
-// Logic for cfg_gpio_out_type 
-//-----------------------------------------------------------------------
-assign cfg_gpio_out_type = reg_8[31:0]; // to be used for read
-
-gen_32b_reg  #(32'h0) u_reg_8	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_8    ),
-	      .we         (wr_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_8         )
-	      );
-
-
-
-//-----------------------------------------------------------------------
-// Logic for cfg_int_status 
-// Always update int_status, even if no register write is occuring.
-// Interrupt posting is higher priority than int clear by host 
-//-----------------------------------------------------------------------
-wire [31:0]  cfg_gpio_int_status = reg_9[31:0]; // to be used for read
-
-//--------------------------------------------------------
-// Interrupt Status Generation
-// Note: Reg_9 --> Interrupt Status Register, Writting '1' will clear the
-//                 corresponding interrupt status bit. Writting '0' has no
-//                 effect 
-//       Reg_10 --> Writting one to this register will set the interrupt in
-//                  interrupt status register (reg_9), Writting '0' does not has any
-//                  effect.
-/// Always update int_status, even if no register write is occuring.
-//	    Interrupt posting is higher priority than int clear by host 
-//--------------------------------------------------------
-wire [31:0] gpio_int_status = reg_9;				      
-
-generic_intr_stat_reg #(.WD(32),
-	                .RESET_DEFAULT(0))  u_reg_9 (
-		 //inputs
-		 .clk         (mclk              ),
-		 .reset_n     (h_reset_n         ),
-	         .reg_we      ({
-		               {8{sw_wr_en_9 & reg_ack & wr_be[2]}},
-		               {8{sw_wr_en_9 & reg_ack & wr_be[2]}},
-		               {8{sw_wr_en_9 & reg_ack & wr_be[1]}},
-		               {8{sw_wr_en_9 & reg_ack & wr_be[0]}}
-		               }  ),		 
-		 .reg_din    (sw_reg_wdata[31:0] ),
-		 .hware_req  (gpio_int_event | {
-		               {8{sw_wr_en_10 & reg_ack}} & sw_reg_wdata[31:24],
-		               {8{sw_wr_en_10 & reg_ack}} & sw_reg_wdata[23:16],
-		               {8{sw_wr_en_10 & reg_ack}} & sw_reg_wdata[15:8] ,
-		               {8{sw_wr_en_10 & reg_ack}} & sw_reg_wdata[7:0]   
-		               }     ),
-		 
-		 //outputs
-		 .data_out    (reg_9[31:0]       )
-	      );
-//-------------------------------------------------
-// Returns same value as interrupt status register
-//------------------------------------------------
-
-assign reg_10 = reg_9;
-//-----------------------------------------------------------------------
-// Logic for cfg_gpio_int_mask :  GPIO interrupt mask  
-//-----------------------------------------------------------------------
-wire [31:0]  cfg_gpio_int_mask = reg_11[31:0]; // to be used for read
-
-assign gpio_intr  = ( | (reg_9 & reg_11) ); // interrupt pin to the RISC
-
-
-//  Register-11
-gen_32b_reg  #(32'h0) u_reg_11	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_11   ),
-	      .we         (wr_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_11        )
-	      );
-//-----------------------------------------------------------------------
-// Logic for cfg_gpio_posedge_int_sel :  Enable posedge GPIO interrupt 
-//-----------------------------------------------------------------------
-assign  cfg_gpio_posedge_int_sel = reg_12[31:0]; // to be used for read
-gen_32b_reg  #(32'h0) u_reg_12	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_12   ),
-	      .we         (wr_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_12        )
-	      );
-//-----------------------------------------------------------------------
-// Logic for cfg_gpio_negedge_int_sel :  Enable negedge GPIO interrupt 
-//-----------------------------------------------------------------------
-assign cfg_gpio_negedge_int_sel = reg_13[31:0]; // to be used for read
-gen_32b_reg  #(32'h0) u_reg_13	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_13   ),
-	      .we         (wr_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_13        )
-	      );
-
-//-----------------------------------------------------------------------
-// Logic for cfg_multi_func_sel :Enable GPIO to act as multi function pins 
-//-----------------------------------------------------------------------
-assign  cfg_multi_func_sel = reg_14[31:0]; // to be used for read
-
-
-gen_32b_reg  #(32'h0) u_reg_14	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_14   ),
-	      .we         (wr_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_14        )
-	      );
-
-// Reg-15
-gen_32b_reg  #(32'h0) u_reg_15	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_15   ),
-	      .we         (wr_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_15        )
-	      );
-//-----------------------------------------------------------------------
-// Logic for PWM-0 Config
-//-----------------------------------------------------------------------
-assign  cfg_pwm0_low  = reg_16[15:0];  // low period of w/f 
-assign  cfg_pwm0_high = reg_16[31:16]; // high period of w/f 
-
-gen_32b_reg  #(32'h0) u_reg_16	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_16   ),
-	      .we         (wr_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_16        )
-	      );
-
-
-//-----------------------------------------------------------------------
-// Logic for PWM-1 Config
-//-----------------------------------------------------------------------
-assign  cfg_pwm1_low  = reg_17[15:0];  // low period of w/f 
-assign  cfg_pwm1_high = reg_17[31:16]; // high period of w/f 
-gen_32b_reg  #(32'h0) u_reg_17	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_17   ),
-	      .we         (wr_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_17         )
-	      );
-
-//-----------------------------------------------------------------------
-// Logic for PWM-2 Config
-//-----------------------------------------------------------------------
-assign  cfg_pwm2_low  = reg_18[15:0];  // low period of w/f 
-assign  cfg_pwm2_high = reg_18[31:16]; // high period of w/f 
-gen_32b_reg  #(32'h0) u_reg_18	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_18   ),
-	      .we         (wr_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_18        )
-	      );
-
-//-----------------------------------------------------------------------
-// Logic for PWM-3 Config
-//-----------------------------------------------------------------------
-assign  cfg_pwm3_low  = reg_19[15:0];  // low period of w/f 
-assign  cfg_pwm3_high = reg_19[31:16]; // high period of w/f 
-gen_32b_reg  #(32'h0) u_reg_19	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_19   ),
-	      .we         (wr_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_19        )
-	      );
-
-//-----------------------------------------------------------------------
-// Logic for PWM-4 Config
-//-----------------------------------------------------------------------
-assign  cfg_pwm4_low  = reg_20[15:0];  // low period of w/f 
-assign  cfg_pwm4_high = reg_20[31:16]; // high period of w/f 
-
-gen_32b_reg  #(32'h0) u_reg_20	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_20   ),
-	      .we         (wr_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_20        )
-	      );
-
-//-----------------------------------------------------------------------
-// Logic for PWM-5 Config
-//-----------------------------------------------------------------------
-assign  cfg_pwm5_low  = reg_21[15:0];  // low period of w/f 
-assign  cfg_pwm5_high = reg_21[31:16]; // high period of w/f 
-
-gen_32b_reg  #(32'h0) u_reg_21	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_21   ),
-	      .we         (wr_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_21       )
-	      );
-
-
-//-----------------------------------------
-// Software Reg-1 : ASCI Representation of RISC = 32'h8273_8343
-// ----------------------------------------
-gen_32b_reg  #(32'h8273_8343) u_reg_22	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_22   ),
-	      .we         (wr_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_22       )
-	      );
-
-//-----------------------------------------
-// Software Reg-2, Release date: <DAY><MONTH><YEAR>
-// ----------------------------------------
-gen_32b_reg  #(32'h2007_2022) u_reg_23	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_23   ),
-	      .we         (wr_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_23       )
-	      );
-
-//-----------------------------------------
-// Software Reg-3: Poject Revison 4.7 = 0004800
-// ----------------------------------------
-gen_32b_reg  #(32'h0004_8000) u_reg_24	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_24   ),
-	      .we         (wr_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_24       )
-	      );
-
-//-----------------------------------------
-// Software Reg-4
-// ----------------------------------------
-gen_32b_reg  #(32'h0) u_reg_25	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_25   ),
-	      .we         (wr_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_25       )
-	      );
-
-//-----------------------------------------
-// Software Reg-5
-// ----------------------------------------
-gen_32b_reg  #(32'h0) u_reg_26	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_26   ),
-	      .we         (wr_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_26       )
-	      );
-
-//-----------------------------------------
-// Software Reg-6
-// ----------------------------------------
-gen_32b_reg  #(32'h0) u_reg_27	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_27   ),
-	      .we         (wr_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_27       )
-	      );
-
-
-//-----------------------------------------------------------------------
-//   reg-28
-// Assumption: wr_en is two cycle and reg_ack is asserted in second cycle
-//     In first cycle, local register will be updated
-//     In second cycle, update indication sent to timer block
-//   -----------------------------------------------------------------
-assign cfg_timer0          = reg_28[18:0];
-assign cfg_timer_update[0] = sw_wr_en_28 & reg_ack; 
-
-gen_32b_reg  #(32'h0) u_reg_28	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_28   ),
-	      .we         (wr_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_28[31:0]  )
-	      );
-
-//-----------------------------------------------------------------------
-//   reg-29
-// Assumption: wr_en is two cycle and reg_ack is asserted in second cycle
-//     In first cycle, local register will be updated
-//     In second cycle, update indication sent to timer block
-//   -----------------------------------------------------------------
-assign cfg_timer1          = reg_29[18:0];
-assign cfg_timer_update[1] = sw_wr_en_29 & reg_ack;
-
-gen_32b_reg  #(32'h0) u_reg_29	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_29   ),
-	      .we         (wr_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_29[31:0]  )
-	      );
-
-
-//-----------------------------------------------------------------------
-//   reg-30
-// Assumption: wr_en is two cycle and reg_ack is asserted in second cycle
-//     In first cycle, local register will be updated
-//     In second cycle, update indication sent to timer block
-//   -----------------------------------------------------------------
-assign cfg_timer2          = reg_30[18:0];
-assign cfg_timer_update[2] = sw_wr_en_30 & reg_ack;
-
-gen_32b_reg  #(32'h0) u_reg_30	(
-	      //List of Inputs
-	      .reset_n    (h_reset_n     ),
-	      .clk        (mclk          ),
-	      .cs         (sw_wr_en_30   ),
-	      .we         (wr_be         ),		 
-	      .data_in    (sw_reg_wdata  ),
-	      
-	      //List of Outs
-	      .data_out   (reg_30[31:0]  )
-	      );
-
-//-----------------------------------------------------------------------
-// Register Read Path Multiplexer instantiation
-//-----------------------------------------------------------------------
-
-always_comb
-begin 
-  reg_out [31:0] = 32'h0;
-
-  case (sw_addr [4:0])
-    5'b00000 : reg_out [31:0] = reg_0 [31:0];     
-    5'b00001 : reg_out [31:0] = reg_1 [31:0];    
-    5'b00010 : reg_out [31:0] = reg_2 [31:0];     
-    5'b00011 : reg_out [31:0] = reg_3 [31:0];    
-    5'b00100 : reg_out [31:0] = reg_4 [31:0];    
-    5'b00101 : reg_out [31:0] = reg_5 [31:0];    
-    5'b00110 : reg_out [31:0] = reg_6 [31:0];    
-    5'b00111 : reg_out [31:0] = reg_7 [31:0];    
-    5'b01000 : reg_out [31:0] = reg_8 [31:0];    
-    5'b01001 : reg_out [31:0] = reg_9 [31:0];    
-    5'b01010 : reg_out [31:0] = reg_10 [31:0];   
-    5'b01011 : reg_out [31:0] = reg_11 [31:0];   
-    5'b01100 : reg_out [31:0] = reg_12 [31:0];   
-    5'b01101 : reg_out [31:0] = reg_13 [31:0];
-    5'b01110 : reg_out [31:0] = reg_14 [31:0];
-    5'b01111 : reg_out [31:0] = reg_15 [31:0]; 
-    5'b10000 : reg_out [31:0] = reg_16 [31:0];
-    5'b10001 : reg_out [31:0] = reg_17 [31:0];
-    5'b10010 : reg_out [31:0] = reg_18 [31:0];
-    5'b10011 : reg_out [31:0] = reg_19 [31:0];
-    5'b10100 : reg_out [31:0] = reg_20 [31:0];
-    5'b10101 : reg_out [31:0] = reg_21 [31:0];
-    5'b10110 : reg_out [31:0] = reg_22 [31:0];
-    5'b10111 : reg_out [31:0] = reg_23 [31:0];
-    5'b11000 : reg_out [31:0] = reg_24 [31:0];
-    5'b11001 : reg_out [31:0] = reg_25 [31:0];
-    5'b11010 : reg_out [31:0] = reg_26 [31:0];
-    5'b11011 : reg_out [31:0] = reg_27 [31:0];
-    5'b11100 : reg_out [31:0] = reg_28 [31:0];
-    5'b11101 : reg_out [31:0] = reg_29 [31:0];
-    5'b11110 : reg_out [31:0] = reg_30 [31:0]; 
-    5'b11111 : reg_out [31:0] = 32'h0;
-    default  : reg_out [31:0] = 32'h0;
-  endcase
-end
-
-
-endmodule                       
diff --git a/verilog/rtl/pinmux/src/pinmux_top.sv b/verilog/rtl/pinmux/src/pinmux_top.sv
new file mode 100755
index 0000000..c84c1a7
--- /dev/null
+++ b/verilog/rtl/pinmux/src/pinmux_top.sv
@@ -0,0 +1,485 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  Pinmux                                                     ////
+////                                                              ////
+////  This file is part of the riscduino cores project            ////
+////  https://github.com/dineshannayya/riscduino.git              ////
+////                                                              ////
+////  Description                                                 ////
+////      PinMux Manages all the pin multiplexing                 ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision :                                                  ////
+////    0.1 - 16th Feb 2021, Dinesh A                             ////
+////          initial version                                     ////
+////    0.2 - 6 April 2021, Dinesh A                              ////
+////          1. SSPI CS# increased from 1 to 4                   ////
+//            2. UART I/F increase from 1 to 2                    ////
+////    0.3 - 8 July 2022, Dinesh A                               ////
+////          In ardunio, SPI chip select are control through     ////
+////          GPIO, So we have moved the Auto generated SPI CS    ////
+////          different config bit. I2C config position moved from////
+////          bit[14] to bit [15]                                 ////
+////    0.4 - 20 July 2022, Dinesh A                              ////
+////         On Power On, If RESET* = 0, then system will enter   ////
+////         in to SPIS slave mode to support boot                ////
+//////////////////////////////////////////////////////////////////////
+
+module pinmux_top (
+                    `ifdef USE_POWER_PINS
+                       input logic         vccd1,// User area 1 1.8V supply
+                       input logic         vssd1,// User area 1 digital ground
+                    `endif
+                        // clock skew adjust
+                       input logic [3:0]        cfg_cska_pinmux,
+                       input logic	        wbd_clk_int,
+                       output logic	        wbd_clk_pinmux,
+                       // System Signals
+                       // Inputs
+		       input logic             mclk,
+                       input logic             h_reset_n,
+
+                       // Global Reset control
+                       output logic  [1:0]     cpu_core_rst_n   ,
+                       output logic            cpu_intf_rst_n   ,
+                       output logic            qspim_rst_n      ,
+                       output logic            sspim_rst_n      ,
+                       output logic [1:0]      uart_rst_n       ,
+                       output logic            i2cm_rst_n       ,
+                       output logic            usb_rst_n        ,
+
+		       output logic [15:0]     cfg_riscv_ctrl,
+
+		       // Reg Bus Interface Signal
+                       input logic             reg_cs,
+                       input logic             reg_wr,
+                       input logic [8:0]       reg_addr,
+                       input logic [31:0]      reg_wdata,
+                       input logic [3:0]       reg_be,
+
+                       // Outputs
+                       output logic [31:0]     reg_rdata,
+                       output logic            reg_ack,
+
+		      // Risc configuration
+                       output logic [15:0]     irq_lines,
+                       output logic            soft_irq,
+                       output logic [2:0]      user_irq,
+		       input  logic            usb_intr,
+		       input  logic            i2cm_intr,
+
+                       // Digital IO
+                       output logic [37:0]     digital_io_out,
+                       output logic [37:0]     digital_io_oen,
+                       input  logic [37:0]     digital_io_in,
+
+		       // SFLASH I/F
+		       input  logic            sflash_sck,
+		       input  logic [3:0]      sflash_ss,
+		       input  logic [3:0]      sflash_oen,
+		       input  logic [3:0]      sflash_do,
+		       output logic [3:0]      sflash_di,
+
+		       // SSRAM I/F - Temp Masked
+		       //input  logic            ssram_sck,
+		       //input  logic            ssram_ss,
+		       //input  logic [3:0]      ssram_oen,
+		       //input  logic [3:0]      ssram_do,
+		       //output logic [3:0]      ssram_di,
+
+		       // USB I/F
+		       input   logic           usb_dp_o,
+		       input   logic           usb_dn_o,
+		       input   logic           usb_oen,
+		       output   logic          usb_dp_i,
+		       output   logic          usb_dn_i,
+
+		       // UART I/F
+		       input   logic  [1:0]    uart_txd,
+		       output  logic  [1:0]    uart_rxd,
+
+		       // I2CM I/F
+		       input   logic           i2cm_clk_o,
+		       output  logic           i2cm_clk_i,
+		       input   logic           i2cm_clk_oen,
+		       input   logic           i2cm_data_oen,
+		       input   logic           i2cm_data_o,
+		       output  logic           i2cm_data_i,
+
+		       // SPI MASTER
+		       input   logic           spim_sck,
+		       input   logic [3:0]     spim_ssn,
+		       input   logic           spim_miso,
+		       output  logic           spim_mosi,
+		       
+		       // SPI SLAVE
+		       output   logic           spis_sck,
+		       output   logic           spis_ssn,
+		       input    logic           spis_miso,
+		       output   logic           spis_mosi,
+
+                       // UART MASTER I/F
+                       output  logic            uartm_rxd ,
+                       input logic              uartm_txd  ,       
+
+		       output  logic           pulse1m_mclk,
+	               output  logic [31:0]    pinmux_debug,
+
+		       input   logic           dbg_clk_mon
+
+   ); 
+
+
+
+logic sreset_n;  // Sync Reset
+   
+/* clock pulse */
+//********************************************************
+logic           pulse_1ms               ; // 1 Milli Second Pulse for waveform Generator
+logic [5:0]     cfg_pwm_enb             ;
+
+
+//---------------------------------------------------------
+// Timer Register                          
+// -------------------------------------------------------
+logic [2:0]    timer_intr              ;
+
+//---------------------------------------------------
+// 6 PWM variabled
+//---------------------------------------------------
+
+logic [5:0]     pwm_wfm                 ;
+
+
+wire  [31:0]  cfg_gpio_dir_sel         ;// decides on GPIO pin is I/P or O/P at pad level, 0 -> Input, 1 -> Output
+wire  [31:0]  cfg_gpio_out_type        ;// GPIO Type, Unused
+wire  [31:0]  cfg_multi_func_sel       ;// GPIO Multi function type
+
+
+reg [7:0]     port_a_in;      // PORT A Data In
+reg [7:0]     port_b_in;      // PORT B Data In
+reg [7:0]     port_c_in;      // PORT C Data In
+reg [7:0]     port_d_in;      // PORT D Data In
+
+wire [7:0]    port_a_out;     // PORT A Data Out
+wire [7:0]    port_b_out;     // PORT B Data Out
+wire [7:0]    port_c_out;     // PORT C Data Out
+wire [7:0]    port_d_out;     // PORT D Data Out
+wire [31:0]   pad_gpio_in;    // GPIO data input from PAD
+wire [31:0]   pad_gpio_out;   // GPIO Data out towards PAD
+wire [31:0]   gpio_int_event; // GPIO Interrupt indication
+reg [1:0]     ext_intr_in;    // External PAD level interrupt
+
+
+assign      pinmux_debug = '0; // Todo: Need to fix
+
+//------------------------------------------------------
+// Register Map Decoding
+
+`define SEL_GLBL  3'b000   // GLOBAL REGISTER
+`define SEL_GPIO  3'b001   // GPIO REGISTER
+`define SEL_PWM   3'b010   // PWM REGISTER
+`define SEL_TIMER 3'b011   // TIMER REGISTER
+`define SEL_SEMA  3'b100   // SEMAPHORE REGISTER
+
+
+//----------------------------------------
+//  Register Response Path Mux
+//  --------------------------------------
+logic [31:0]  reg_glbl_rdata;
+logic         reg_glbl_ack;
+
+logic [31:0]  reg_gpio_rdata;
+logic         reg_gpio_ack;
+
+logic [31:0]  reg_pwm_rdata;
+logic         reg_pwm_ack;
+
+logic [31:0]  reg_timer_rdata;
+logic         reg_timer_ack;
+
+logic [15:0]  reg_sema_rdata;
+logic         reg_sema_ack;
+
+
+assign reg_rdata = (reg_addr[8:6] == `SEL_GLBL)  ? {reg_glbl_rdata} : 
+	               (reg_addr[8:6] == `SEL_GPIO)  ? {reg_gpio_rdata} :
+	               (reg_addr[8:6] == `SEL_PWM)   ? {reg_pwm_rdata}  :
+	               (reg_addr[8:6] == `SEL_TIMER) ? reg_timer_rdata  : 
+	               (reg_addr[8:6] == `SEL_SEMA)  ? {16'h0,reg_sema_rdata} : 'h0;
+
+assign reg_ack   = (reg_addr[8:6] == `SEL_GLBL)  ? reg_glbl_ack   : 
+	               (reg_addr[8:6] == `SEL_GPIO)  ? reg_gpio_ack   : 
+	               (reg_addr[8:6] == `SEL_PWM)   ? reg_pwm_ack    : 
+	               (reg_addr[8:6] == `SEL_TIMER) ? reg_timer_ack  : 
+	               (reg_addr[8:6] == `SEL_SEMA)  ? reg_sema_ack   : 1'b0;
+
+wire reg_glbl_cs  = (reg_addr[8:6] == `SEL_GLBL) ? reg_cs : 1'b0;
+wire reg_gpio_cs  = (reg_addr[8:6] == `SEL_GPIO) ? reg_cs : 1'b0;
+wire reg_pwm_cs   = (reg_addr[8:6] == `SEL_PWM)  ? reg_cs : 1'b0;
+wire reg_timer_cs = (reg_addr[8:6] == `SEL_TIMER)? reg_cs : 1'b0;
+wire reg_sema_cs  = (reg_addr[8:6] == `SEL_SEMA) ? reg_cs : 1'b0;
+
+//---------------------------------------------------------------------
+
+// SSRAM I/F - Temp masked
+//input  logic            ssram_sck,
+//input  logic            ssram_ss,
+//input  logic [3:0]      ssram_oen,
+//input  logic [3:0]      ssram_do,
+//output logic [3:0]      ssram_di,
+
+// pinmux clock skew control
+clk_skew_adjust u_skew_pinmux
+       (
+`ifdef USE_POWER_PINS
+               .vccd1      (vccd1                      ),// User area 1 1.8V supply
+               .vssd1      (vssd1                      ),// User area 1 digital ground
+`endif
+	       .clk_in     (wbd_clk_int                 ), 
+	       .sel        (cfg_cska_pinmux             ), 
+	       .clk_out    (wbd_clk_pinmux              ) 
+       );
+
+reset_sync  u_rst_sync (
+	      .scan_mode  (1'b0        ),
+              .dclk       (mclk        ), // Destination clock domain
+	      .arst_n     (h_reset_n   ), // active low async reset
+              .srst_n     (sreset_n    )
+          );
+
+//------------------------------------------------------------------
+// Global Register
+//------------------------------------------------------------------
+glbl_reg u_glbl_reg(
+      // System Signals
+      // Inputs
+          .mclk                         (mclk                    ),
+          .h_reset_n                    (sreset_n                ),
+
+          .cpu_core_rst_n               (cpu_core_rst_n          ),
+          .cpu_intf_rst_n               (cpu_intf_rst_n          ),
+          .qspim_rst_n                  (qspim_rst_n             ),
+          .sspim_rst_n                  (sspim_rst_n             ),
+          .uart_rst_n                   (uart_rst_n              ),
+          .i2cm_rst_n                   (i2cm_rst_n              ),
+          .usb_rst_n                    (usb_rst_n               ),
+
+	      .cfg_riscv_ctrl               (cfg_riscv_ctrl          ),
+          .cfg_multi_func_sel           (cfg_multi_func_sel      ),
+
+
+      // Reg read/write Interface Inputs
+          .reg_cs                       (reg_glbl_cs             ),
+          .reg_wr                       (reg_wr                  ),
+          .reg_addr                     (reg_addr[5:2]           ),
+          .reg_wdata                    (reg_wdata               ),
+          .reg_be                       (reg_be                  ),
+
+          .reg_rdata                    (reg_glbl_rdata          ),
+          .reg_ack                      (reg_glbl_ack            ),
+
+	      .ext_intr_in                  (ext_intr_in             ),
+
+	      .irq_lines                    (irq_lines               ),
+	      .soft_irq                     (soft_irq                ),
+	      .user_irq                     (user_irq                ),
+          .usb_intr                     (usb_intr                ),
+          .i2cm_intr                    (i2cm_intr               ),
+
+
+
+          .timer_intr                   (timer_intr             ),
+          .gpio_intr                    (gpio_intr              )
+
+
+   ); 
+
+//-----------------------------------------------------------------------
+// GPIO Top
+//-----------------------------------------------------------------------
+gpio_top  u_gpio(
+              // System Signals
+              // Inputs
+		      .mclk                     ( mclk                      ),
+              .h_reset_n                (h_reset_n                  ),
+
+		      // Reg Bus Interface Signal
+              .reg_cs                   (reg_gpio_cs                ),
+              .reg_wr                   (reg_wr                     ),
+              .reg_addr                 (reg_addr[5:2]             ),
+              .reg_wdata                (reg_wdata                  ),
+              .reg_be                   (reg_be                     ),
+
+              // Outputs
+              .reg_rdata                (reg_gpio_rdata             ),
+              .reg_ack                  (reg_gpio_ack               ),
+
+
+              .cfg_gpio_dir_sel         (cfg_gpio_dir_sel           ),
+              .pad_gpio_in              (pad_gpio_in                ),
+              .pad_gpio_out             (pad_gpio_out               ),
+
+              .gpio_intr                (gpio_intr                  )          
+
+
+                ); 
+
+//-----------------------------------------------------------------------
+// PWM Top
+//-----------------------------------------------------------------------
+pwm_top  u_pwm(
+              // System Signals
+              // Inputs
+		      .mclk                     ( mclk                      ),
+              .h_reset_n                (h_reset_n                  ),
+
+		      // Reg Bus Interface Signal
+              .reg_cs                   (reg_pwm_cs                 ),
+              .reg_wr                   (reg_wr                     ),
+              .reg_addr                 (reg_addr[4:2]              ),
+              .reg_wdata                (reg_wdata                  ),
+              .reg_be                   (reg_be                     ),
+
+              // Outputs
+              .reg_rdata                (reg_pwm_rdata              ),
+              .reg_ack                  (reg_pwm_ack                ),
+
+              .pulse_1ms                (pulse_1ms                  ), 
+              .cfg_pwm_enb              (cfg_pwm_enb                ),
+              .pwm_wfm                  (pwm_wfm                    ) 
+           );
+
+//-----------------------------------------------------------------------
+// Timer Top
+//-----------------------------------------------------------------------
+timer_top  u_timer(
+              // System Signals
+              // Inputs
+		      .mclk                     ( mclk                      ),
+              .h_reset_n                (h_reset_n                  ),
+
+		      // Reg Bus Interface Signal
+              .reg_cs                   (reg_timer_cs               ),
+              .reg_wr                   (reg_wr                     ),
+              .reg_addr                 (reg_addr[3:2]              ),
+              .reg_wdata                (reg_wdata                  ),
+              .reg_be                   (reg_be                     ),
+
+              // Outputs
+              .reg_rdata                (reg_timer_rdata            ),
+              .reg_ack                  (reg_timer_ack              ),
+
+              .pulse_1ms                (pulse_1ms                  ), 
+              .timer_intr               (timer_intr                 ) 
+           );
+
+//-----------------------------------------------------------------------
+// Semaphore Register
+//-----------------------------------------------------------------------
+semaphore_reg  u_semaphore(
+              // System Signals
+              // Inputs
+		      .mclk                     ( mclk                      ),
+              .h_reset_n                (h_reset_n                  ),
+
+		      // Reg Bus Interface Signal
+              .reg_cs                   (reg_sema_cs                ),
+              .reg_wr                   (reg_wr                     ),
+              .reg_addr                 (reg_addr[5:2]              ),
+              .reg_wdata                (reg_wdata[15:0]            ),
+              .reg_be                   (reg_be[1:0]                ),
+
+              // Outputs
+              .reg_rdata                (reg_sema_rdata             ),
+              .reg_ack                  (reg_sema_ack               )
+         );
+
+
+pinmux u_pinmux (
+               // Digital IO
+               .digital_io_out          (digital_io_out      ),
+               .digital_io_oen          (digital_io_oen      ),
+               .digital_io_in           (digital_io_in       ),
+
+               // Config
+               .cfg_gpio_dir_sel        (cfg_gpio_dir_sel    ),
+               .cfg_multi_func_sel      (cfg_multi_func_sel  ),
+
+               .cfg_pwm_enb             (cfg_pwm_enb         ),                                                          
+               .pwm_wfm                 (pwm_wfm             ),
+               .ext_intr_in             (ext_intr_in         ),  // External PAD level interrupt
+               .pad_gpio_in             (pad_gpio_in         ),  // GPIO data input from PAD
+               .pad_gpio_out            (pad_gpio_out        ),  // GPIO Data out towards PAD
+
+		       // SFLASH I/F
+		       .sflash_sck              (sflash_sck          ),
+		       .sflash_ss               (sflash_ss           ),
+		       .sflash_oen              (sflash_oen          ),
+		       .sflash_do               (sflash_do           ),
+		       .sflash_di               (sflash_di           ),
+
+		       // USB I/F
+		       .usb_dp_o                (usb_dp_o            ),
+		       .usb_dn_o                (usb_dn_o            ),
+		       .usb_oen                 (usb_oen             ),
+		       .usb_dp_i                (usb_dp_i            ),
+		       .usb_dn_i                (usb_dn_i            ),
+
+		       // UART I/F
+		       .uart_txd                (uart_txd            ),
+		       .uart_rxd                (uart_rxd            ),
+
+		       // I2CM I/F
+		       .i2cm_clk_o              (i2cm_clk_o          ),
+		       .i2cm_clk_i              (i2cm_clk_i          ),
+		       .i2cm_clk_oen            (i2cm_clk_oen        ),
+		       .i2cm_data_oen           (i2cm_data_oen       ),
+		       .i2cm_data_o             (i2cm_data_o         ),
+		       .i2cm_data_i             (i2cm_data_i         ),
+
+		       // SPI MASTER
+		       .spim_sck                (spim_sck            ),
+		       .spim_ssn                (spim_ssn            ),
+		       .spim_miso               (spim_miso           ),
+		       .spim_mosi               (spim_mosi           ),
+		       
+		       // SPI SLAVE
+		       .spis_sck                (spis_sck            ),
+		       .spis_ssn                (spis_ssn            ),
+		       .spis_miso               (spis_miso           ),
+		       .spis_mosi               (spis_mosi           ),
+
+               // UART MASTER I/F
+               .uartm_rxd               (uartm_rxd           ),
+               .uartm_txd               (uartm_txd           ),       
+                                                   
+		       .dbg_clk_mon             (dbg_clk_mon         )
+
+   ); 
+
+endmodule 
+
+
diff --git a/verilog/rtl/pinmux/src/pwm_reg.sv b/verilog/rtl/pinmux/src/pwm_reg.sv
new file mode 100644
index 0000000..702c138
--- /dev/null
+++ b/verilog/rtl/pinmux/src/pwm_reg.sv
@@ -0,0 +1,255 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  PWM Register                                                ////
+////                                                              ////
+////  This file is part of the riscduino cores project            ////
+////  https://github.com/dineshannayya/riscduino.git              ////
+////                                                              ////
+////  Description                                                 ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision :                                                  ////
+////    0.1 - 15th Aug 2022, Dinesh A                             ////
+////          initial version                                     ////
+//////////////////////////////////////////////////////////////////////
+//
+module pwm_reg  (
+                       // System Signals
+                       // Inputs
+		               input logic           mclk               ,
+                       input logic           h_reset_n          ,
+
+		               // Reg Bus Interface Signal
+                       input logic           reg_cs             ,
+                       input logic           reg_wr             ,
+                       input logic [2:0]     reg_addr           ,
+                       input logic [31:0]    reg_wdata          ,
+                       input logic [3:0]     reg_be             ,
+
+                       // Outputs
+                       output logic [31:0]   reg_rdata          ,
+                       output logic          reg_ack            ,
+
+                       output logic [15:0]    cfg_pwm0_high     ,
+                       output logic [15:0]    cfg_pwm0_low      ,
+                       output logic [15:0]    cfg_pwm1_high     ,
+                       output logic [15:0]    cfg_pwm1_low      ,
+                       output logic [15:0]    cfg_pwm2_high     ,
+                       output logic [15:0]    cfg_pwm2_low      ,
+                       output logic [15:0]    cfg_pwm3_high     ,
+                       output logic [15:0]    cfg_pwm3_low      ,
+                       output logic [15:0]    cfg_pwm4_high     ,
+                       output logic [15:0]    cfg_pwm4_low      ,
+                       output logic [15:0]    cfg_pwm5_high     ,
+                       output logic [15:0]    cfg_pwm5_low      
+
+                ); 
+
+//-----------------------------------------------------------------------
+// Internal Wire Declarations
+//-----------------------------------------------------------------------
+
+logic          sw_rd_en        ;
+logic          sw_wr_en        ;
+logic [2:0]    sw_addr         ; // addressing 16 registers
+logic [31:0]   sw_reg_wdata    ;
+logic [3:0]    sw_be           ;
+
+logic [31:0]   reg_out         ;
+logic [31:0]   reg_0           ; // CONFIG - Unused
+logic [31:0]   reg_1           ; // PWM-REG-0
+logic [31:0]   reg_2           ; // PWM-REG-1
+logic [31:0]   reg_3           ; // PWM-REG-2
+logic [31:0]   reg_4           ; // PWM-REG-3
+logic [31:0]   reg_5           ; // PWM-REG-4
+logic [31:0]   reg_6           ; // PWM-REG-5
+
+assign       sw_addr       = reg_addr;
+assign       sw_rd_en      = reg_cs & !reg_wr;
+assign       sw_wr_en      = reg_cs & reg_wr;
+assign       sw_be         = reg_be;
+assign       sw_reg_wdata  = reg_wdata;
+
+//-----------------------------------------------------------------------
+// register read enable and write enable decoding logic
+//-----------------------------------------------------------------------
+wire   sw_wr_en_0 = sw_wr_en  & (sw_addr == 3'h0);
+wire   sw_wr_en_1 = sw_wr_en  & (sw_addr == 3'h1);
+wire   sw_wr_en_2 = sw_wr_en  & (sw_addr == 3'h2);
+wire   sw_wr_en_3 = sw_wr_en  & (sw_addr == 3'h3);
+wire   sw_wr_en_4 = sw_wr_en  & (sw_addr == 3'h4);
+wire   sw_wr_en_5 = sw_wr_en  & (sw_addr == 3'h5);
+wire   sw_wr_en_6 = sw_wr_en  & (sw_addr == 3'h6);
+
+wire   sw_rd_en_0 = sw_rd_en  & (sw_addr == 3'h0);
+wire   sw_rd_en_1 = sw_rd_en  & (sw_addr == 3'h1);
+wire   sw_rd_en_2 = sw_rd_en  & (sw_addr == 3'h2);
+wire   sw_rd_en_3 = sw_rd_en  & (sw_addr == 3'h3);
+wire   sw_rd_en_4 = sw_rd_en  & (sw_addr == 3'h4);
+wire   sw_rd_en_5 = sw_rd_en  & (sw_addr == 3'h5);
+wire   sw_rd_en_6 = sw_rd_en  & (sw_addr == 3'h6);
+
+
+always @ (posedge mclk or negedge h_reset_n)
+begin : preg_out_Seq
+   if (h_reset_n == 1'b0) begin
+      reg_rdata  <= 'h0;
+      reg_ack    <= 1'b0;
+   end else if (reg_cs && !reg_ack) begin
+      reg_rdata  <= reg_out;
+      reg_ack    <= 1'b1;
+   end else begin
+      reg_ack    <= 1'b0;
+   end
+end
+
+//--------------------------------------------
+// reg-0: Reserve for pwm global config
+//---------------------------------------------
+assign reg_0 = 'h0;
+//-----------------------------------------------------------------------
+// Logic for PWM-0 Config
+//-----------------------------------------------------------------------
+assign  cfg_pwm0_low  = reg_1[15:0];  // low period of w/f 
+assign  cfg_pwm0_high = reg_1[31:16]; // high period of w/f 
+
+gen_32b_reg  #(32'h0) u_reg_1	(
+	      //List of Inputs
+	      .reset_n    (h_reset_n     ),
+	      .clk        (mclk          ),
+	      .cs         (sw_wr_en_1    ),
+	      .we         (sw_be         ),		 
+	      .data_in    (sw_reg_wdata  ),
+	      
+	      //List of Outs
+	      .data_out   (reg_1         )
+	      );
+
+
+//-----------------------------------------------------------------------
+// Logic for PWM-1 Config
+//-----------------------------------------------------------------------
+assign  cfg_pwm1_low  = reg_2[15:0];  // low period of w/f 
+assign  cfg_pwm1_high = reg_2[31:16]; // high period of w/f 
+gen_32b_reg  #(32'h0) u_reg_2	(
+	      //List of Inputs
+	      .reset_n    (h_reset_n     ),
+	      .clk        (mclk          ),
+	      .cs         (sw_wr_en_2    ),
+	      .we         (sw_be         ),		 
+	      .data_in    (sw_reg_wdata  ),
+	      
+	      //List of Outs
+	      .data_out   (reg_2         )
+	      );
+
+//-----------------------------------------------------------------------
+// Logic for PWM-2 Config
+//-----------------------------------------------------------------------
+assign  cfg_pwm2_low  = reg_3[15:0];  // low period of w/f 
+assign  cfg_pwm2_high = reg_3[31:16]; // high period of w/f 
+gen_32b_reg  #(32'h0) u_reg_3	(
+	      //List of Inputs
+	      .reset_n    (h_reset_n     ),
+	      .clk        (mclk          ),
+	      .cs         (sw_wr_en_3   ),
+	      .we         (sw_be         ),		 
+	      .data_in    (sw_reg_wdata  ),
+	      
+	      //List of Outs
+	      .data_out   (reg_3        )
+	      );
+
+//-----------------------------------------------------------------------
+// Logic for PWM-3 Config
+//-----------------------------------------------------------------------
+assign  cfg_pwm3_low  = reg_4[15:0];  // low period of w/f 
+assign  cfg_pwm3_high = reg_4[31:16]; // high period of w/f 
+gen_32b_reg  #(32'h0) u_reg_4	(
+	      //List of Inputs
+	      .reset_n    (h_reset_n     ),
+	      .clk        (mclk          ),
+	      .cs         (sw_wr_en_4   ),
+	      .we         (sw_be         ),		 
+	      .data_in    (sw_reg_wdata  ),
+	      
+	      //List of Outs
+	      .data_out   (reg_4        )
+	      );
+
+//-----------------------------------------------------------------------
+// Logic for PWM-4 Config
+//-----------------------------------------------------------------------
+assign  cfg_pwm4_low  = reg_5[15:0];  // low period of w/f 
+assign  cfg_pwm4_high = reg_5[31:16]; // high period of w/f 
+
+gen_32b_reg  #(32'h0) u_reg_5	(
+	      //List of Inputs
+	      .reset_n    (h_reset_n     ),
+	      .clk        (mclk          ),
+	      .cs         (sw_wr_en_5   ),
+	      .we         (sw_be         ),		 
+	      .data_in    (sw_reg_wdata  ),
+	      
+	      //List of Outs
+	      .data_out   (reg_5        )
+	      );
+
+//-----------------------------------------------------------------------
+// Logic for PWM-5 Config
+//-----------------------------------------------------------------------
+assign  cfg_pwm5_low  = reg_6[15:0];  // low period of w/f 
+assign  cfg_pwm5_high = reg_6[31:16]; // high period of w/f 
+
+gen_32b_reg  #(32'h0) u_reg_6	(
+	      //List of Inputs
+	      .reset_n    (h_reset_n     ),
+	      .clk        (mclk          ),
+	      .cs         (sw_wr_en_6    ),
+	      .we         (sw_be         ),		 
+	      .data_in    (sw_reg_wdata  ),
+	      
+	      //List of Outs
+	      .data_out   (reg_6        )
+	      );
+
+
+always_comb
+begin 
+  reg_out [31:0] = 32'h0;
+
+  case (sw_addr [2:0])
+    3'b000    : reg_out [31:0] = reg_0 [31:0];     
+    3'b001    : reg_out [31:0] = reg_1 [31:0];    
+    3'b010    : reg_out [31:0] = reg_2 [31:0];     
+    3'b011    : reg_out [31:0] = reg_3 [31:0];    
+    3'b100    : reg_out [31:0] = reg_4 [31:0];    
+    3'b101    : reg_out [31:0] = reg_5 [31:0];    
+    3'b110    : reg_out [31:0] = reg_6 [31:0];    
+    default   : reg_out [31:0] = 32'h0;
+  endcase
+end
+
+endmodule
diff --git a/verilog/rtl/pinmux/src/pwm_top.sv b/verilog/rtl/pinmux/src/pwm_top.sv
new file mode 100644
index 0000000..2b8d3a5
--- /dev/null
+++ b/verilog/rtl/pinmux/src/pwm_top.sv
@@ -0,0 +1,172 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  PWM Top                                                     ////
+////                                                              ////
+////  This file is part of the riscduino cores project            ////
+////  https://github.com/dineshannayya/riscduino.git              ////
+////                                                              ////
+////  Description                                                 ////
+///     Includes 6 PWM                                            ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision :                                                  ////
+////    0.1 - 15th Aug 2022, Dinesh A                             ////
+////          initial version                                     ////
+//////////////////////////////////////////////////////////////////////
+
+module pwm_top  (
+                       // System Signals
+                       // Inputs
+		               input logic           mclk,
+                       input logic           h_reset_n,
+
+		               // Reg Bus Interface Signal
+                       input logic           reg_cs,
+                       input logic           reg_wr,
+                       input logic [2:0]     reg_addr,
+                       input logic [31:0]    reg_wdata,
+                       input logic [3:0]     reg_be,
+
+                       // Outputs
+                       output logic [31:0]   reg_rdata,
+                       output logic          reg_ack,
+
+                   
+                       input  logic          pulse_1ms, 
+                       input  logic [5:0]    cfg_pwm_enb,
+                       output logic [5:0]    pwm_wfm 
+
+                ); 
+
+//---------------------------------------------------
+// 6 PWM variabled
+//---------------------------------------------------
+
+logic [15:0]    cfg_pwm0_high           ;
+logic [15:0]    cfg_pwm0_low            ;
+logic [15:0]    cfg_pwm1_high           ;
+logic [15:0]    cfg_pwm1_low            ;
+logic [15:0]    cfg_pwm2_high           ;
+logic [15:0]    cfg_pwm2_low            ;
+logic [15:0]    cfg_pwm3_high           ;
+logic [15:0]    cfg_pwm3_low            ;
+logic [15:0]    cfg_pwm4_high           ;
+logic [15:0]    cfg_pwm4_low            ;
+logic [15:0]    cfg_pwm5_high           ;
+logic [15:0]    cfg_pwm5_low            ;
+
+
+
+pwm_reg  u_reg (
+		       .mclk             (mclk                ),
+               .h_reset_n        (h_reset_n           ),
+
+		       // Reg Bus Interface Signal
+               .reg_cs           (reg_cs              ),
+               .reg_wr           (reg_wr              ),
+               .reg_addr         (reg_addr            ),
+               .reg_wdata        (reg_wdata           ),
+               .reg_be           (reg_be              ),
+
+               // Outputs
+               .reg_rdata        (reg_rdata           ),
+               .reg_ack          (reg_ack             ),
+
+               .cfg_pwm0_high    (cfg_pwm0_high       ),
+               .cfg_pwm0_low     (cfg_pwm0_low        ),
+               .cfg_pwm1_high    (cfg_pwm1_high       ),
+               .cfg_pwm1_low     (cfg_pwm1_low        ),
+               .cfg_pwm2_high    (cfg_pwm2_high       ),
+               .cfg_pwm2_low     (cfg_pwm2_low        ),
+               .cfg_pwm3_high    (cfg_pwm3_high       ),
+               .cfg_pwm3_low     (cfg_pwm3_low        ),
+               .cfg_pwm4_high    (cfg_pwm4_high       ),
+               .cfg_pwm4_low     (cfg_pwm4_low        ),
+               .cfg_pwm5_high    (cfg_pwm5_high       ),
+               .cfg_pwm5_low     (cfg_pwm5_low        )
+
+                ); 
+
+
+// 6 PWM Waveform Generator
+pwm  u_pwm_0 (
+	  .waveform                    (pwm_wfm[0]         ), 
+	  .h_reset_n                   (h_reset_n          ),
+	  .mclk                        (mclk               ),
+	  .pulse1m_mclk                (pulse_1ms          ),
+	  .cfg_pwm_enb                 (cfg_pwm_enb[0]     ),
+	  .cfg_pwm_high                (cfg_pwm0_high      ),
+	  .cfg_pwm_low                 (cfg_pwm0_low       )
+     );
+
+pwm  u_pwm_1 (
+	  .waveform                    (pwm_wfm[1]         ), 
+	  .h_reset_n                   (h_reset_n          ),
+	  .mclk                        (mclk               ),
+	  .pulse1m_mclk                (pulse_1ms          ),
+	  .cfg_pwm_enb                 (cfg_pwm_enb[1]     ),
+	  .cfg_pwm_high                (cfg_pwm1_high      ),
+	  .cfg_pwm_low                 (cfg_pwm1_low       )
+     );
+   
+pwm  u_pwm_2 (
+	  .waveform                    (pwm_wfm[2]         ), 
+	  .h_reset_n                   (h_reset_n          ),
+	  .mclk                        (mclk               ),
+	  .pulse1m_mclk                (pulse_1ms          ),
+	  .cfg_pwm_enb                 (cfg_pwm_enb[2]     ),
+	  .cfg_pwm_high                (cfg_pwm2_high      ),
+	  .cfg_pwm_low                 (cfg_pwm2_low       )
+     );
+
+pwm  u_pwm_3 (
+	  .waveform                    (pwm_wfm[3]         ), 
+	  .h_reset_n                   (h_reset_n          ),
+	  .mclk                        (mclk               ),
+	  .pulse1m_mclk                (pulse_1ms          ),
+	  .cfg_pwm_enb                 (cfg_pwm_enb[3]     ),
+	  .cfg_pwm_high                (cfg_pwm3_high      ),
+	  .cfg_pwm_low                 (cfg_pwm3_low       )
+     );
+pwm  u_pwm_4 (
+	  .waveform                    (pwm_wfm[4]         ), 
+	  .h_reset_n                   (h_reset_n          ),
+	  .mclk                        (mclk               ),
+	  .pulse1m_mclk                (pulse_1ms          ),
+	  .cfg_pwm_enb                 (cfg_pwm_enb[4]     ),
+	  .cfg_pwm_high                (cfg_pwm4_high      ),
+	  .cfg_pwm_low                 (cfg_pwm4_low       )
+     );
+pwm  u_pwm_5 (
+	  .waveform                    (pwm_wfm[5]         ), 
+	  .h_reset_n                   (h_reset_n          ),
+	  .mclk                        (mclk               ),
+	  .pulse1m_mclk                (pulse_1ms          ),
+	  .cfg_pwm_enb                 (cfg_pwm_enb[5]     ),
+	  .cfg_pwm_high                (cfg_pwm5_high      ),
+	  .cfg_pwm_low                 (cfg_pwm5_low       )
+     );
+
+endmodule
diff --git a/verilog/rtl/pinmux/src/semaphore_reg.sv b/verilog/rtl/pinmux/src/semaphore_reg.sv
new file mode 100644
index 0000000..c347178
--- /dev/null
+++ b/verilog/rtl/pinmux/src/semaphore_reg.sv
@@ -0,0 +1,165 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  Semaphore Register                                          ////
+////                                                              ////
+////  This file is part of the riscduino cores project            ////
+////  https://github.com/dineshannayya/riscduino.git              ////
+////                                                              ////
+////  Description                                                 ////
+//// A semaphore is a variable or abstract data type that         ////
+//// provides a simple but useful abstraction for controlling     ////
+//// access by multiple processes to a common resource in a       ////
+//// parallel programming or multi-user environment.              ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision :                                                  ////
+////    0.1 - 15th Aug 2022, Dinesh A                             ////
+////          initial version                                     ////
+//////////////////////////////////////////////////////////////////////
+//
+/***************************************************************
+  Special Semaphore Register Implementation
+  Read access from 0 to 14 will return corresponsonding bit lock status. 
+     If lock is free, then it return '1' and also lock the corresponding bit
+     If lock is busy, then it return '0' 
+  Write & Read access with address 15 does normal write and read access, 
+   this location should used for only debug purpose
+
+*****************************************************************/
+module semaphore_reg  #(parameter DW = 16,         // DATA WIDTH
+                        parameter AW = $clog2(DW), // ADDRESS WIDTH
+                        parameter BW = $clog2(AW)  // BYTE WIDTH
+                ) (
+                       // System Signals
+                       // Inputs
+		               input logic           mclk,
+                       input logic           h_reset_n,
+
+		               // Reg Bus Interface Signal
+                       input logic           reg_cs,
+                       input logic           reg_wr,
+                       input logic [AW-1:0]  reg_addr,
+                       input logic [DW-1:0]  reg_wdata,
+                       input logic [BW-1:0]  reg_be,
+
+                       // Outputs
+                       output logic [DW-1:0] reg_rdata,
+                       output logic          reg_ack
+
+                ); 
+
+//-----------------------------------------------------------------------
+// Internal Wire Declarations
+//-----------------------------------------------------------------------
+
+logic          sw_rd_en        ;
+logic          sw_wr_en        ;
+logic [AW-1:0] sw_addr         ; // addressing 16 registers
+logic [DW-1:0] sw_reg_wdata    ;
+logic [BW-1:0] sw_be           ;
+
+logic [DW-1:0] reg_out         ;
+logic [DW-1:0] reg_0           ; 
+logic          sw_wr_en_0      ;
+
+assign       sw_addr       = reg_addr;
+assign       sw_rd_en      = reg_cs & !reg_wr;
+assign       sw_wr_en      = reg_cs & reg_wr;
+
+
+always @ (posedge mclk or negedge h_reset_n)
+begin : preg_out_Seq
+   if (h_reset_n == 1'b0) begin
+      reg_rdata  <= 'h0;
+      reg_ack    <= 1'b0;
+   end else if (reg_cs && !reg_ack) begin
+      reg_rdata  <= reg_out[DW-1:0] ;
+      reg_ack    <= 1'b1;
+   end else begin
+      reg_ack    <= 1'b0;
+   end
+end
+
+/***************************************************************
+  Special Semaphore Register Implementation
+  Read access from 0 to 30 will return corresponsonding bit lock status. 
+     If lock is free, then it return '1' and lock the corresponding bit
+     If lock is busy, then it return '0' and lock the corresponding bit
+*****************************************************************/
+
+gen_16b_reg  #('h0) u_reg_0	(
+	      //List of Inputs
+	      .reset_n    (h_reset_n             ),
+	      .clk        (mclk                  ),
+	      .cs         (sw_wr_en_0            ),
+	      .we         (sw_be[BW-1:0]         ),		 
+	      .data_in    (sw_reg_wdata[DW-1:0]  ),
+	      
+	      //List of Outs
+	      .data_out   (reg_0                 )
+	      );
+
+
+//-----------------------------------------------------------------------
+// Register Write Data
+//-----------------------------------------------------------------------
+
+always_comb
+begin 
+  sw_reg_wdata  = 'h0;
+  sw_wr_en_0    = 'b0;
+  sw_be         = 'h0;
+
+   // Address 0xF, is Simple Write Register
+   if(sw_addr == {AW {1'b1}}) begin 
+      sw_reg_wdata = reg_0;
+      sw_wr_en_0   = sw_wr_en & reg_ack;
+      sw_be        = reg_be[BW-1:0];
+   end else begin // 0 to 0xE is Semaphore Register
+       if(sw_rd_en) begin  // Read will always lock the bit '1'
+          sw_reg_wdata = (reg_0   | ( 1 << sw_addr)) ; 
+       end else begin // To release the Lock Write with '1'
+          sw_reg_wdata  = (reg_0  ^ ((reg_wdata [DW-1:0] & 'h1)  << sw_addr)) ; 
+       end
+       sw_wr_en_0 = reg_ack;
+       sw_be      = {BW{1'b1}};
+    end
+end
+
+//-----------------------------------------------------------------------
+// Register Read Path Multiplexer instantiation
+//-----------------------------------------------------------------------
+
+always_comb
+begin 
+  if(sw_addr == {AW {1'b1}}) begin 
+     reg_out = reg_0;
+  end else begin
+     reg_out = (reg_0 >> sw_addr ) ^ 'h1; 
+  end
+end
+
+
+endmodule
diff --git a/verilog/rtl/pinmux/src/timer_reg.sv b/verilog/rtl/pinmux/src/timer_reg.sv
new file mode 100644
index 0000000..cd48587
--- /dev/null
+++ b/verilog/rtl/pinmux/src/timer_reg.sv
@@ -0,0 +1,213 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  Timer Register                                              ////
+////                                                              ////
+////  This file is part of the riscduino cores project            ////
+////  https://github.com/dineshannayya/riscduino.git              ////
+////                                                              ////
+////  Description                                                 ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision :                                                  ////
+////    0.1 - 15th Aug 2022, Dinesh A                             ////
+////          initial version                                     ////
+//////////////////////////////////////////////////////////////////////
+//
+module timer_reg  (
+                       // System Signals
+                       // Inputs
+		               input logic           mclk               ,
+                       input logic           h_reset_n          ,
+
+		               // Reg Bus Interface Signal
+                       input logic           reg_cs             ,
+                       input logic           reg_wr             ,
+                       input logic [1:0]     reg_addr           ,
+                       input logic [31:0]    reg_wdata          ,
+                       input logic [3:0]     reg_be             ,
+
+                       // Outputs
+                       output logic [31:0]   reg_rdata          ,
+                       output logic          reg_ack            ,
+
+                       output logic [9:0]    cfg_pulse_1us      ,
+                       output logic [2:0]    cfg_timer_update   , // CPU write to timer register
+                       output logic [18:0]   cfg_timer0         , // Timer-0 register
+                       output logic [18:0]   cfg_timer1         , // Timer-1 register
+                       output logic [18:0]   cfg_timer2         , // Timer-2 register
+                       output logic [2:0]    timer_intr         
+
+                ); 
+
+//-----------------------------------------------------------------------
+// Internal Wire Declarations
+//-----------------------------------------------------------------------
+
+logic          sw_rd_en        ;
+logic          sw_wr_en        ;
+logic [1:0]    sw_addr         ; // addressing 16 registers
+logic [31:0]   sw_reg_wdata    ;
+logic [3:0]    sw_be           ;
+
+logic [31:0]   reg_out         ;
+logic [31:0]   reg_0           ;  // TIMER GLOBAL CONFIG
+logic [31:0]   reg_1           ;  // TIMER-0
+logic [31:0]   reg_2           ;  // TIMER-1
+logic [31:0]   reg_3           ;  // TIMER-2
+
+assign       sw_addr       = reg_addr;
+assign       sw_rd_en      = reg_cs & !reg_wr;
+assign       sw_wr_en      = reg_cs & reg_wr;
+assign       sw_be         = reg_be;
+assign       sw_reg_wdata  = reg_wdata;
+
+//-----------------------------------------------------------------------
+// register read enable and write enable decoding logic
+//-----------------------------------------------------------------------
+wire   sw_wr_en_0 = sw_wr_en  & (sw_addr == 2'h0);
+wire   sw_wr_en_1 = sw_wr_en  & (sw_addr == 2'h1);
+wire   sw_wr_en_2 = sw_wr_en  & (sw_addr == 2'h2);
+wire   sw_wr_en_3 = sw_wr_en  & (sw_addr == 2'h3);
+
+wire   sw_rd_en_0 = sw_rd_en  & (sw_addr == 2'h0);
+wire   sw_rd_en_1 = sw_rd_en  & (sw_addr == 2'h1);
+wire   sw_rd_en_2 = sw_rd_en  & (sw_addr == 2'h2);
+wire   sw_rd_en_3 = sw_rd_en  & (sw_addr == 2'h3);
+
+
+always @ (posedge mclk or negedge h_reset_n)
+begin : preg_out_Seq
+   if (h_reset_n == 1'b0) begin
+      reg_rdata  <= 'h0;
+      reg_ack    <= 1'b0;
+   end else if (reg_cs && !reg_ack) begin
+      reg_rdata  <= reg_out;
+      reg_ack    <= 1'b1;
+   end else begin
+      reg_ack    <= 1'b0;
+   end
+end
+
+
+//----------------------------------------------
+// reg-0: GLBL_CFG
+//------------------------------------------
+
+gen_32b_reg  #('h0) u_reg_0	(
+	      //List of Inputs
+	      .reset_n    (h_reset_n     ),
+	      .clk        (mclk          ),
+	      .cs         (sw_wr_en_0    ),
+	      .we         (sw_be         ),		 
+	      .data_in    (sw_reg_wdata  ),
+	      
+	      //List of Outs
+	      .data_out   (reg_0         )
+	      );
+
+assign cfg_pulse_1us       = reg_0[9:0];
+
+//-----------------------------------------------------------------------
+//   reg-1
+// Assumption: wr_en is two cycle and reg_ack is asserted in second cycle
+//     In first cycle, local register will be updated
+//     In second cycle, update indication sent to timer block
+//   -----------------------------------------------------------------
+assign cfg_timer0          = reg_1[18:0];
+assign cfg_timer_update[0] = sw_wr_en_1 & reg_ack; 
+
+gen_32b_reg  #(32'h0) u_reg_1	(
+	      //List of Inputs
+	      .reset_n    (h_reset_n     ),
+	      .clk        (mclk          ),
+	      .cs         (sw_wr_en_1    ),
+	      .we         (sw_be         ),		 
+	      .data_in    (sw_reg_wdata  ),
+	      
+	      //List of Outs
+	      .data_out   (reg_1[31:0]  )
+	      );
+
+//-----------------------------------------------------------------------
+//   reg-2
+// Assumption: wr_en is two cycle and reg_ack is asserted in second cycle
+//     In first cycle, local register will be updated
+//     In second cycle, update indication sent to timer block
+//   -----------------------------------------------------------------
+assign cfg_timer1          = reg_2[18:0];
+assign cfg_timer_update[1] = sw_wr_en_2 & reg_ack;
+
+gen_32b_reg  #(32'h0) u_reg_2	(
+	      //List of Inputs
+	      .reset_n    (h_reset_n     ),
+	      .clk        (mclk          ),
+	      .cs         (sw_wr_en_2    ),
+	      .we         (sw_be         ),		 
+	      .data_in    (sw_reg_wdata  ),
+	      
+	      //List of Outs
+	      .data_out   (reg_2[31:0]   )
+	      );
+
+
+//-----------------------------------------------------------------------
+//   reg-3
+// Assumption: wr_en is two cycle and reg_ack is asserted in second cycle
+//     In first cycle, local register will be updated
+//     In second cycle, update indication sent to timer block
+//   -----------------------------------------------------------------
+assign cfg_timer2          = reg_3[18:0];
+assign cfg_timer_update[2] = sw_wr_en_3 & reg_ack;
+
+gen_32b_reg  #(32'h0) u_reg_3	(
+	      //List of Inputs
+	      .reset_n    (h_reset_n     ),
+	      .clk        (mclk          ),
+	      .cs         (sw_wr_en_3    ),
+	      .we         (sw_be         ),		 
+	      .data_in    (sw_reg_wdata  ),
+	      
+	      //List of Outs
+	      .data_out   (reg_3[31:0]   )
+	      );
+
+//-----------------------------------------------------------------------
+// Register Read Path Multiplexer instantiation
+//-----------------------------------------------------------------------
+
+always_comb
+begin 
+  reg_out [31:0] = 32'h0;
+
+  case (sw_addr [1:0])
+    2'b00    : reg_out [31:0] = reg_0 [31:0];     
+    2'b01    : reg_out [31:0] = reg_1 [31:0];    
+    2'b10    : reg_out [31:0] = reg_2 [31:0];     
+    2'b11    : reg_out [31:0] = reg_3 [31:0];    
+    default  : reg_out [31:0] = 32'h0;
+  endcase
+end
+
+endmodule
diff --git a/verilog/rtl/pinmux/src/timer_top.sv b/verilog/rtl/pinmux/src/timer_top.sv
new file mode 100644
index 0000000..ae981dc
--- /dev/null
+++ b/verilog/rtl/pinmux/src/timer_top.sv
@@ -0,0 +1,191 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  Timer Top                                                   ////
+////                                                              ////
+////  This file is part of the riscduino cores project            ////
+////  https://github.com/dineshannayya/riscduino.git              ////
+////                                                              ////
+////  Description                                                 ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision :                                                  ////
+////    0.1 - 15th Aug 2022, Dinesh A                             ////
+////          initial version                                     ////
+//////////////////////////////////////////////////////////////////////
+
+module timer_top  (
+                       // System Signals
+                       // Inputs
+		               input logic           mclk,
+                       input logic           h_reset_n,
+
+		               // Reg Bus Interface Signal
+                       input logic           reg_cs,
+                       input logic           reg_wr,
+                       input logic [1:0]     reg_addr,
+                       input logic [31:0]    reg_wdata,
+                       input logic [3:0]     reg_be,
+
+                       // Outputs
+                       output logic [31:0]   reg_rdata,
+                       output logic          reg_ack,
+
+                       output logic          pulse_1ms,
+                       output logic [2:0]    timer_intr 
+
+                ); 
+
+//---------------------------------------------------------
+// Timer Register                          
+// -------------------------------------------------------
+logic [2:0]    cfg_timer_update        ; // CPU write to timer register
+logic [18:0]   cfg_timer0              ; // Timer-0 register
+logic [18:0]   cfg_timer1              ; // Timer-1 register
+logic [18:0]   cfg_timer2              ; // Timer-2 register
+
+/* clock pulse */
+//********************************************************
+logic           pulse_1us               ; // 1 UsSecond Pulse for waveform Generator
+logic           pulse_1s                ; // 1Second Pulse for waveform Generator
+logic [9:0]     cfg_pulse_1us           ; // 1us pulse generation config
+
+timer_reg  u_reg (
+		       .mclk             (mclk                ),
+               .h_reset_n        (h_reset_n           ),
+
+		       // Reg Bus Interface Signal
+               .reg_cs           (reg_cs              ),
+               .reg_wr           (reg_wr              ),
+               .reg_addr         (reg_addr            ),
+               .reg_wdata        (reg_wdata           ),
+               .reg_be           (reg_be              ),
+
+               // Outputs
+               .reg_rdata        (reg_rdata           ),
+               .reg_ack          (reg_ack             ),
+
+               .cfg_pulse_1us    (cfg_pulse_1us       ),
+               .cfg_timer_update (cfg_timer_update    ),
+               .cfg_timer0       (cfg_timer0          ),
+               .cfg_timer1       (cfg_timer1          ),
+               .cfg_timer2       (cfg_timer2          )
+
+                ); 
+
+// 1us pulse
+pulse_gen_type2  #(.WD(10)) u_pulse_1us (
+
+	.clk_pulse_o               (pulse_1us        ),
+	.clk                       (mclk             ),
+    .reset_n                   (h_reset_n        ),
+	.cfg_max_cnt               (cfg_pulse_1us    )
+
+     );
+
+// 1us/1000 to 1millisecond pulse
+pulse_gen_type1 u_pulse_1ms (
+
+	.clk_pulse_o               (pulse_1ms       ),
+	.clk                       (mclk            ),
+    .reset_n                   (h_reset_n       ),
+	.trigger                   (pulse_1us       )
+
+      );
+
+// 1ms/1000 => 1 second pulse
+pulse_gen_type1 u_pulse_1s (
+
+	.clk_pulse_o               (pulse_1s    ),
+	.clk                       (mclk        ),
+    .reset_n                   (h_reset_n   ),
+	.trigger                   (pulse_1ms   )
+
+       );
+
+// Timer
+
+wire [1:0]  cfg_timer0_clksel = cfg_timer0[18:17];
+wire        cfg_timer0_enb    = cfg_timer0[16];
+wire [15:0] cfg_timer0_compare = cfg_timer0[15:0];
+
+timer  u_timer_0
+  (
+     .reset_n                      (sreset_n             ),// system syn reset
+     .mclk                         (mclk                 ),// master clock
+     .pulse_1us                    (pulse_1us            ),
+     .pulse_1ms                    (pulse_1ms            ),
+     .pulse_1s                     (pulse_1s             ),
+
+     .cfg_timer_update             (cfg_timer_update[0]  ), 
+     .cfg_timer_enb                (cfg_timer0_enb       ),     
+     .cfg_timer_compare            (cfg_timer0_compare   ),
+     .cfg_timer_clksel             (cfg_timer0_clksel    ),// to select the timer 1us/1ms reference clock
+
+     .timer_intr                   (timer_intr[0]         )
+   );
+
+// Timer
+wire [1:0] cfg_timer1_clksel   = cfg_timer1[18:17];
+wire       cfg_timer1_enb      = cfg_timer1[16];
+wire [15:0] cfg_timer1_compare = cfg_timer1[15:0];
+timer  u_timer_1
+  (
+     .reset_n                      (sreset_n             ),// system syn reset
+     .mclk                         (mclk                 ),// master clock
+     .pulse_1us                    (pulse_1us            ),
+     .pulse_1ms                    (pulse_1ms            ),
+     .pulse_1s                     (pulse_1s             ),
+
+     .cfg_timer_update             (cfg_timer_update[1]  ), 
+     .cfg_timer_enb                (cfg_timer1_enb       ),     
+     .cfg_timer_compare            (cfg_timer1_compare   ),
+     .cfg_timer_clksel             (cfg_timer1_clksel    ),// to select the timer 1us/1ms reference clock
+
+     .timer_intr                   (timer_intr[1]         )
+   );
+
+// Timer
+wire [1:0] cfg_timer2_clksel = cfg_timer2[18:17];
+wire       cfg_timer2_enb    = cfg_timer2[16];
+wire [15:0] cfg_timer2_compare = cfg_timer2[15:0];
+
+timer  u_timer_2
+  (
+     .reset_n                      (sreset_n             ),// system syn reset
+     .mclk                         (mclk                 ),// master clock
+     .pulse_1us                    (pulse_1us            ),
+     .pulse_1ms                    (pulse_1ms            ),
+     .pulse_1s                     (pulse_1s             ),
+
+     .cfg_timer_update             (cfg_timer_update[2]  ), 
+     .cfg_timer_enb                (cfg_timer2_enb       ),     
+     .cfg_timer_compare            (cfg_timer2_compare   ),
+     .cfg_timer_clksel             (cfg_timer2_clksel    ),// to select the timer 1us/1ms reference clock
+
+     .timer_intr                   (timer_intr[2]        )
+   );
+
+
+endmodule
diff --git a/verilog/rtl/sspim/src/sspim_cfg.sv b/verilog/rtl/sspim/src/sspim_cfg.sv
index e849f81..cc81df0 100755
--- a/verilog/rtl/sspim/src/sspim_cfg.sv
+++ b/verilog/rtl/sspim/src/sspim_cfg.sv
@@ -46,17 +46,28 @@
 //// from http://www.opencores.org/lgpl.shtml                     ////
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
+/*******************************************************************
+SPI Mode:
+     Mode 0 (the default)− Clock is normally low (CPOL = 0), and Data sampled on rising edge and shifted out on the falling edge.  (CPHA = 0). - Supported
+     Mode 1              − Clock is normally low (CPOL = 0), and Data sampled on the falling edge and shifted out on the rising edge. (CPHA = 1). - Not Supported
+     Mode 2              − Clock is normally high (CPOL = 1), and Data sampled on the rising edge and shifted out on the falling edge. (CPHA = 0). - Supported
+     Mode 3              − Clock is normally high (CPOL = 1), and Data sampled on the falling edge and shifted out on the rising edge (CPHA = 1). - Not Supported
 
 
+********************************************************************/
+
 
 module sspim_cfg (
               input  logic          mclk               ,
               input  logic          reset_n            ,
               
               output logic [1:0]    cfg_tgt_sel        ,
-              
+
+              output logic          cfg_cpol           , // spi clock idle phase
+              output logic          cfg_cpha           , // spi data sample and lanch phase
+              output logic          cfg_bit_order      , // SPI TX/RX Bit Order,  1 -> LSBFIRST or  0 -> MSBFIRST
               output logic          cfg_op_req         , // SPI operation request
-	      output logic          cfg_endian         , // Endian selection
+	          output logic          cfg_endian         , // Endian selection
               output logic [1:0]    cfg_op_type        , // SPI operation type
               output logic [1:0]    cfg_transfer_size  , // SPI transfer size
               output logic [5:0]    cfg_sck_period     , // sck clock period
@@ -98,6 +109,7 @@
 logic  [31:0]    reg_1;  // Software-Reg_1
 logic  [31:0]    reg_2;  // Software-Reg_2
 logic  [31:0]    reg_out;
+logic  [1:0]     cfg_spi_mode;
 
 //-----------------------------------------------------------------------
 // Main code starts here
@@ -168,7 +180,13 @@
 //-----------------------------------------------------------------------
 // Logic for Register 0 : SPI Control Register
 //-----------------------------------------------------------------------
+
+assign cfg_cpha = cfg_spi_mode[0];
+assign cfg_cpol = cfg_spi_mode[1];
+
 assign    cfg_op_req         = reg_0[31];    // cpu request
+assign    cfg_bit_order      = reg_0[28];    //  1 -> LSBFIRST or  0 -> MSBFIRST
+assign    cfg_spi_mode       = reg_0[27:26]; // spi mode
 assign    cfg_endian         = reg_0[25];    // Endian, 0 - little, 1 - Big
 assign    cfg_tgt_sel        = reg_0[24:23]; // target chip select
 assign    cfg_op_type        = reg_0[22:21]; // SPI operation type
@@ -210,18 +228,17 @@
 	      .data_out      (reg_0[23:16]       )
           );
 
-generic_register #(2,0  ) u_spi_ctrl_be3 (
-	      .we            ({2{sw_wr_en_0 & 
+generic_register #(7,0  ) u_spi_ctrl_be3 (
+	      .we            ({7{sw_wr_en_0 & 
                                 wr_be[3]   }}  ),		 
-	      .data_in       (reg_wdata[25:24] ),
+	      .data_in       (reg_wdata[30:24] ),
 	      .reset_n       (reset_n           ),
 	      .clk           (mclk              ),
 	      
 	      //List of Outs
-	      .data_out      (reg_0[25:24]       )
+	      .data_out      (reg_0[30:24]       )
           );
 
-assign reg_0[30:26] = 5'h0;
 
 req_register #(0  ) u_spi_ctrl_req (
 	      .cpu_we       ({sw_wr_en_0 & 
diff --git a/verilog/rtl/sspim/src/sspim_clkgen.sv b/verilog/rtl/sspim/src/sspim_clkgen.sv
new file mode 100755
index 0000000..bb1a8b4
--- /dev/null
+++ b/verilog/rtl/sspim/src/sspim_clkgen.sv
@@ -0,0 +1,146 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  Single SPI Master Interface Module                          ////
+////                                                              ////
+////  This file is part of the riscduino cores project            ////
+////  https://github.com/dineshannayya/riscduino.git              ////
+////                                                              ////
+////  Description                                                 ////
+////      SPI Clock Gen module                                    ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision :                                                  ////
+////      V.0  - 06 Oct 2021                                      ////
+////          Initial SpI Module picked from                      ////
+////             http://www.opencores.org/cores/turbo8051/        ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+/*********************************************************************
+   Design Implementation Reference
+   Reference: https://www.allaboutcircuits.com/technical-articles/spi-serial-peripheral-interface/
+*********************************************************************/  
+
+
+module sspim_clkgen
+       ( 
+  input  logic          clk,
+  input  logic          reset_n,
+  input  logic          cfg_op_req,
+  input  logic          cfg_cpol,    // CPOL : clock polarity CPOL :0- Clock Idle state low, 1 - Clock idle state high
+  input  logic          cfg_cpha,    // CPHA : Clock Phase
+    
+  input  logic [5:0]    cfg_sck_period,
+
+  input  logic          sck_active,
+
+  output logic          sck_int,  // SCLK
+  output logic          shift,    // Data Shift Phase
+  output logic          sample,   // Data Sample Phase
+  output logic          sck_ne,   // sclk negative phase
+  output logic          sck_pe    // sclk positive phase
+         
+         );
+
+ //*************************************************************************
+
+
+  logic [5:0]       clk_cnt;
+  logic  [5:0]      sck_half_period;
+
+
+  
+  assign sck_ne = (cfg_cpha == 0) ? shift  : sample;
+  assign sck_pe = (cfg_cpha == 0) ? sample : shift;
+
+  assign sck_half_period = {1'b0, cfg_sck_period[5:1]};
+  // The first transition on the sck_toggle happens one SCK period
+  // after op_en or boot_en is asserted
+  always @(posedge clk or negedge reset_n) begin
+     if(!reset_n) begin
+        shift    <= 1'b0;
+        sample   <= 1'b0;
+        clk_cnt  <= 6'h0;
+        sck_int  <= 1'b1;
+     end // if (!reset_n)
+     else 
+     begin
+        if(cfg_op_req) 
+        begin
+           // clock counter
+           if(clk_cnt == cfg_sck_period) begin
+              clk_cnt <= 'h0;
+           end else begin
+              clk_cnt <= clk_cnt + 1'b1;
+            end
+
+           if(clk_cnt == sck_half_period) 
+           begin
+              shift  <= 1'b1;
+              sample <= 1'b0;
+           end // if (clk_cnt == sck_half_period)
+           else 
+           begin
+              if(clk_cnt == cfg_sck_period) 
+              begin
+                 shift <= 1'b0;
+                 sample <= 1'b1;
+              end // if (clk_cnt == cfg_sck_period)
+              else 
+              begin
+                 shift  <= 1'b0;
+                 sample <= 1'b0;
+              end // else: !if(clk_cnt == cfg_sck_period)
+           end // else: !if(clk_cnt == sck_half_period)
+        end // if (op_en)
+        else 
+        begin
+           clk_cnt   <= 6'h0;
+           shift     <= 1'b0;
+           sample    <= 1'b0;
+        end // else: !if(op_en)
+           
+
+        if(sck_active) begin
+           if(sck_ne)       sck_int <= 0;
+           else if(sck_pe)  sck_int <= 1;
+        end else if (cfg_cpol == 0) begin // CPOL :0- Clock Idle state low
+           sck_int <= 0;
+        end else begin // CPOL :1- Clock Idle state High
+           sck_int <= 1;
+        end
+     end // else: !if(!reset_n)
+  end // always @ (posedge clk or negedge reset_n)
+  
+
+
+endmodule
diff --git a/verilog/rtl/sspim/src/sspim_ctl.sv b/verilog/rtl/sspim/src/sspim_ctl.sv
index ea6aa1f..25971e0 100755
--- a/verilog/rtl/sspim/src/sspim_ctl.sv
+++ b/verilog/rtl/sspim/src/sspim_ctl.sv
@@ -52,25 +52,24 @@
        ( 
   input  logic          clk,
   input  logic          reset_n,
+  input  logic          cfg_cpol,
   input  logic          cfg_op_req,
   input  logic          cfg_endian,
   input  logic [1:0]    cfg_op_type,
   input  logic [1:0]    cfg_transfer_size,
+  input  logic [4:0]    cfg_sck_cs_period, 
     
-  input  logic [5:0]    cfg_sck_period,
-  input  logic [4:0]    cfg_sck_cs_period, // cs setup & hold period
   input  logic [7:0]    cfg_cs_byte,
   input  logic [31:0]   cfg_datain,
   output logic [31:0]   cfg_dataout,
 
   output logic [7:0]    byte_out, // Byte out for Serial Shifting out
   input  logic [7:0]    byte_in,  // Serial Received Byte
-  output logic          sck_int,
   output logic          cs_int_n,
-  output logic          sck_pe,
-  output logic          sck_ne,
-  output logic          shift_out,
-  output logic          shift_in,
+  input logic           shift,
+  input logic           sample,
+
+  output logic          sck_active,
   output logic          load_byte,
   output logic          op_done
          
@@ -80,74 +79,25 @@
 
  parameter LITTLE_ENDIAN  = 1'b0;
  parameter BIG_ENDIAN     = 1'b1;
+ 
+ parameter SPI_WR         = 2'b00;
+ parameter SPI_RD         = 2'b01;
+ parameter SPI_WR_RD      = 2'b10;
 
-  logic [5:0]       clk_cnt;
   logic [5:0]       sck_cnt;
 
   logic [3:0]       spiif_cs;
-  logic             shift_enb;
-  logic             clr_sck_cnt ;
-  logic             sck_out_en;
 
-  logic  [5:0]      sck_half_period;
   logic [2:0]       byte_cnt;
 
 
   `define SPI_IDLE   4'b0000
   `define SPI_CS_SU  4'b0001
-  `define SPI_WRITE  4'b0010
-  `define SPI_READ   4'b0011
-  `define SPI_CS_HLD 4'b0100
-  `define SPI_WAIT   4'b0101
+  `define SPI_DATA   4'b0010
+  `define SPI_CS_HLD 4'b0011
+  `define SPI_WAIT   4'b0100
 
 
-  assign sck_half_period = {1'b0, cfg_sck_period[5:1]};
-  // The first transition on the sck_toggle happens one SCK period
-  // after op_en or boot_en is asserted
-  always @(posedge clk or negedge reset_n) begin
-     if(!reset_n) begin
-        sck_ne   <= 1'b0;
-        clk_cnt  <= 6'h1;
-        sck_pe   <= 1'b0;
-        sck_int  <= 1'b0;
-     end // if (!reset_n)
-     else 
-     begin
-        if(cfg_op_req) 
-        begin
-           if(clk_cnt == sck_half_period) 
-           begin
-              sck_ne <= 1'b1;
-              sck_pe <= 1'b0;
-              if(sck_out_en) sck_int <= 0;
-              clk_cnt <= clk_cnt + 1'b1;
-           end // if (clk_cnt == sck_half_period)
-           else 
-           begin
-              if(clk_cnt == cfg_sck_period) 
-              begin
-                 sck_ne <= 1'b0;
-                 sck_pe <= 1'b1;
-                 if(sck_out_en) sck_int <= 1;
-                 clk_cnt <= 6'h1;
-              end // if (clk_cnt == cfg_sck_period)
-              else 
-              begin
-                 clk_cnt <= clk_cnt + 1'b1;
-                 sck_pe <= 1'b0;
-                 sck_ne <= 1'b0;
-              end // else: !if(clk_cnt == cfg_sck_period)
-           end // else: !if(clk_cnt == sck_half_period)
-        end // if (op_en)
-        else 
-        begin
-           clk_cnt    <= 6'h1;
-           sck_pe     <= 1'b0;
-           sck_ne     <= 1'b0;
-        end // else: !if(op_en)
-     end // else: !if(!reset_n)
-  end // always @ (posedge clk or negedge reset_n)
-  
 
 wire [1:0] cs_data =  (byte_cnt == 2'b00) ? cfg_cs_byte[7:6]  :
                       (byte_cnt == 2'b01) ? cfg_cs_byte[5:4]  :
@@ -162,104 +112,72 @@
                             (byte_cnt == 2'b10) ? cfg_datain[15:8]  : cfg_datain[7:0]) ;
          
          
-assign shift_out =  shift_enb && sck_ne;
 
 always @(posedge clk or negedge reset_n) begin
    if(!reset_n) begin
       spiif_cs    <= `SPI_IDLE;
       sck_cnt     <= 6'h0;
-      shift_in    <= 1'b0;
-      clr_sck_cnt <= 1'b1;
       byte_cnt    <= 2'b00;
       cs_int_n    <= 1'b1;
-      sck_out_en  <= 1'b0;
-      shift_enb   <= 1'b0;
       cfg_dataout <= 32'h0;
       load_byte   <= 1'b0;
+      sck_active  <= 1'b0;
    end
    else begin
-      if(sck_ne)
-         sck_cnt <=  clr_sck_cnt  ? 6'h0 : sck_cnt + 1 ;
-
       case(spiif_cs)
       `SPI_IDLE   : 
       begin
+          sck_active  <= 1'b0;
+          load_byte   <= 1'b0;
           op_done     <= 0;
-          clr_sck_cnt <= 1'b1;
-          sck_out_en  <= 1'b0;
-          shift_enb   <= 1'b0;
           if(cfg_op_req) 
           begin
               cfg_dataout <= 32'h0;
               spiif_cs    <= `SPI_CS_SU;
-           end 
-           else begin
+           end else begin
               spiif_cs <= `SPI_IDLE;
            end 
       end 
 
       `SPI_CS_SU  : 
        begin
-          if(sck_ne) begin
+          if(shift) begin
             cs_int_n <= cs_data[1];
             if(sck_cnt == cfg_sck_cs_period) begin
-               clr_sck_cnt <= 1'b1;
-               if(cfg_op_type == 0) begin // Write Mode
+               sck_cnt <=  'h0;
+               if((cfg_op_type == SPI_WR) || (cfg_op_type == SPI_WR_RD )) begin // Write Mode
                   load_byte   <= 1'b1;
-                  spiif_cs    <= `SPI_WRITE;
-                  shift_enb   <= 1'b0;
-               end else begin
-                  shift_in    <= 1;
-                  spiif_cs    <= `SPI_READ;
-                end
-             end
-             else begin 
-                clr_sck_cnt <= 1'b0;
-             end
+               end 
+               spiif_cs    <= `SPI_DATA;
+            end else begin 
+               sck_cnt <=  sck_cnt + 1 ;
+            end
          end
       end 
 
-      `SPI_WRITE : 
+      `SPI_DATA : 
        begin 
          load_byte   <= 1'b0;
-         if(sck_ne) begin
-           if(sck_cnt == 3'h7 )begin
-              clr_sck_cnt <= 1'b1;
-              spiif_cs    <= `SPI_CS_HLD;
-              shift_enb   <= 1'b0;
-              sck_out_en  <= 1'b0; // Disable clock output
-           end
-           else begin
-              shift_enb   <= 1'b1;
-              sck_out_en  <= 1'b1;
-              clr_sck_cnt <= 1'b0;
-           end
-         end else begin
-            shift_enb   <= 1'b1;
-         end
-      end 
-
-      `SPI_READ : 
-       begin 
-         if(sck_ne) begin
-             if( sck_cnt == 3'h7 ) begin
-                clr_sck_cnt <= 1'b1;
-                shift_in    <= 0;
-                spiif_cs    <= `SPI_CS_HLD;
-                sck_out_en  <= 1'b0; // Disable clock output
-             end
-             else begin
-                sck_out_en  <= 1'b1; // Disable clock output
-                clr_sck_cnt <= 1'b0;
-             end
+         if((shift && (cfg_cpol == 1)) || (sample && (cfg_cpol == 0)) ) begin
+               sck_active  <= 1'b1;
+         end else if((sample && (cfg_cpol == 1)) || (shift && (cfg_cpol == 0)) ) begin
+            if(sck_cnt == 4'h8 )begin
+               sck_active  <= 1'b0;
+               sck_cnt     <=  'h0;
+               spiif_cs    <= `SPI_CS_HLD;
+            end
+            else begin
+               sck_active  <= 1'b1;
+               sck_cnt     <=  sck_cnt + 1 ;
+            end
          end
       end 
 
       `SPI_CS_HLD : begin
-         if(sck_ne) begin
+         if(shift) begin
              cs_int_n <= cs_data[0];
             if(sck_cnt == cfg_sck_cs_period) begin
-               if(cfg_op_type == 1) begin // Read Mode
+               if((cfg_op_type == SPI_RD) || (cfg_op_type == SPI_WR_RD)) begin // Read Mode
                   cfg_dataout <= (cfg_endian == LITTLE_ENDIAN) ?
 			         ((byte_cnt[1:0] == 2'b00) ? { cfg_dataout[31:8],byte_in } :
                                   (byte_cnt[1:0] == 2'b01) ? { cfg_dataout[31:16], byte_in, cfg_dataout[7:0] } :
@@ -270,7 +188,7 @@
                                   (byte_cnt[1:0] == 2'b10) ? { cfg_dataout[31:16], byte_in, cfg_dataout[7:0]  } :
                                                              { cfg_dataout[31:8],byte_in}) ;
                end
-               clr_sck_cnt <= 1'b1;
+               sck_cnt     <=  'h0;
                if(byte_cnt == cfg_transfer_size) begin
                   spiif_cs <= `SPI_WAIT;
                   byte_cnt <= 0;
@@ -281,7 +199,7 @@
                end
             end
             else begin
-                clr_sck_cnt <= 1'b0;
+                sck_cnt     <=  sck_cnt + 1 ;
             end
          end 
       end // case: `SPI_CS_HLD    
diff --git a/verilog/rtl/sspim/src/sspim_if.sv b/verilog/rtl/sspim/src/sspim_if.sv
index 42b18f2..ece9ffd 100755
--- a/verilog/rtl/sspim/src/sspim_if.sv
+++ b/verilog/rtl/sspim/src/sspim_if.sv
@@ -47,24 +47,25 @@
 
 module sspim_if
           (
-          input  logic clk,
-          input  logic reset_n,
-          input  logic sck_pe,
-          input  logic sck_int,
-          input  logic cs_int_n,
+          input  logic       clk,
+          input  logic       reset_n,
+          input  logic       sck_int,
+          input  logic       cs_int_n,
+          input  logic       cfg_bit_order, // 1 -> LSBFIRST or  0 -> MSBFIRST
           
           input  logic       load_byte,
           input  logic [1:0] cfg_tgt_sel,
 
           input  logic [7:0] byte_out,
-          input  logic       shift_out,
-          input  logic       shift_in,
+          input  logic       sck_active,
+          input  logic       shift,
+          input  logic       sample,
 
-          output logic  [7:0] byte_in,
-          output logic        sck,
-          output logic        so,
-          output logic  [3:0] cs_n,
-          input  logic        si
+          output logic  [7:0]byte_in,
+          output logic       sck,
+          output logic       so,
+          output logic  [3:0]cs_n,
+          input  logic       si
            );
 
 
@@ -73,6 +74,9 @@
   logic [7:0]    si_reg;
 
 
+   wire shift_out = shift & sck_active;
+   wire sample_in  = sample & sck_active;
+
   //Output Shift Register
 
   always @(posedge clk or negedge reset_n) begin
@@ -86,13 +90,19 @@
            if(shift_out) begin 
               // Handling backto back case : 
               // Last Transfer bit + New Trasfer Load
-              so <= so_reg[7];
+              if(cfg_bit_order) so <= so_reg[0]; // LSB FIRST
+              else              so <= so_reg[7]; // MSB FIRST
            end
         end // if (load_byte)
         else begin
            if(shift_out) begin
-              so <= so_reg[7];
-              so_reg <= {so_reg[6:0],1'b0};
+              if(cfg_bit_order) begin // LSB FIRST
+                 so     <= so_reg[0];
+                 so_reg <= {1'b0,so_reg[7:1]};
+              end else begin
+                 so     <= so_reg[7];
+                 so_reg <= {so_reg[6:0],1'b0};
+              end
            end // if (shift_out)
         end // else: !if(load_byte)
      end // else: !if(!reset_n)
@@ -103,11 +113,14 @@
   always @(posedge clk or negedge reset_n) begin
      if(!reset_n) begin
         si_reg <= 8'h0;
-     end
-     else begin
-        if(sck_pe & shift_in) begin
-           si_reg[7:0] <= {si_reg[6:0],si};
-        end // if (sck_pe & shift_in)
+     end else begin
+        if(sample_in) begin
+           if(cfg_bit_order) begin // LSB FIRST
+               si_reg[7:0] <= {si,si_reg[7:1]};
+           end else begin // MSB FIRST
+               si_reg[7:0] <= {si_reg[6:0],si};
+           end
+        end // if (sample_in)
      end // else: !if(!reset_n)
   end // always @ (posedge clk or negedge reset_n)
 
diff --git a/verilog/rtl/sspim/src/sspim_top.sv b/verilog/rtl/sspim/src/sspim_top.sv
index 2a28d2e..6f0f17f 100755
--- a/verilog/rtl/sspim/src/sspim_top.sv
+++ b/verilog/rtl/sspim/src/sspim_top.sv
@@ -46,6 +46,9 @@
 ////            out is big endian, i.e bit[7],[6] ..[0]           ////
 ////    0.3 - April 6, 2022, Dinesh A                             ////
 ////            Four chip select are driven out                   ////
+////    0.4 - Aug 5, 2022, Dinesh A                               ////
+////          A. SPI Mode 0 to 3 support added,                   ////
+////          B. SPI Duplex mode TX-RX Mode added                 ////
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
@@ -125,54 +128,81 @@
 logic  [31:0]        cfg_datain                    ; // data for transfer
 logic  [31:0]        cfg_dataout                   ; // data for received
 logic                hware_op_done                 ; // operation done
-
+logic                cfg_bit_order                 ; // Bit order 1 -> LSBFIRST or  0 -> MSBFIRST
+logic                cfg_cpol                      ; // spi clock idle phase
+logic                cfg_cpha                      ; // spi data sample and lanch phase
 
 sspim_if  u_spi_if
           (
           . clk                         (clk                          ), 
           . reset_n                     (reset_n                      ),
 
-           // towards ctrl i/f
-          . sck_pe                      (sck_pe                       ),
+          // cfg
+          . cfg_bit_order               (cfg_bit_order                ),
+          . cfg_tgt_sel                 (cfg_tgt_sel                  ),
+
+          // clkgen
+          . shift                       (shift                        ),
+          . sample                      (sample                       ),   
           . sck_int                     (sck_int                      ),
+
+           // towards ctrl i/f
+          . sck_active                  (sck_active                   ),
           . cs_int_n                    (cs_int_n                     ),
           . byte_in                     (byte_in                      ),
           . load_byte                   (load_byte                    ),
           . byte_out                    (byte_out                     ),
-          . shift_out                   (shift_out                    ),
-          . shift_in                    (shift_in                     ),
 
-          . cfg_tgt_sel                 (cfg_tgt_sel                  ),
-
+          // External I/F
           . sck                         (sck                          ),
           . so                          (so                           ),
           . si                          (si                           ),
           . cs_n                        (ssn                          )
            );
 
+sspim_clkgen u_clkgen
+       ( 
+          . clk                         (clk                          ), 
+          . reset_n                     (reset_n                      ),
+
+          // cfg
+          . cfg_cpol                    (cfg_cpol                     ),    
+          . cfg_cpha                    (cfg_cpha                     ),    
+          . cfg_sck_period              (cfg_sck_period               ),
+          . cfg_op_req                  (cfg_op_req                   ),
+
+          // ctrl
+          . sck_active                  (sck_active                   ),
+
+          . sck_int                     (sck_int                      ),  
+          . shift                       (shift                        ),    
+          . sample                      (sample                       ),   
+          . sck_ne                      (),   
+          . sck_pe                      ()
+         
+         );
 
 sspim_ctl  u_spi_ctrl
        ( 
           . clk                         (clk                          ),
           . reset_n                     (reset_n                      ),
 
+          // cfg
+          . cfg_cpol                    (cfg_cpol                     ),    
           . cfg_op_req                  (cfg_op_req                   ),
           . cfg_endian                  (cfg_endian                   ),
           . cfg_op_type                 (cfg_op_type                  ),
           . cfg_transfer_size           (cfg_transfer_size            ),
-          . cfg_sck_period              (cfg_sck_period               ),
           . cfg_sck_cs_period           (cfg_sck_cs_period            ),
           . cfg_cs_byte                 (cfg_cs_byte                  ),
           . cfg_datain                  (cfg_datain                   ),
           . cfg_dataout                 (cfg_dataout                  ),
           . op_done                     (hware_op_done                ),
 
-          . sck_int                     (sck_int                      ),
+          . sck_active                  (sck_active                   ),
           . cs_int_n                    (cs_int_n                     ),
-          . sck_pe                      (sck_pe                       ),
-          . sck_ne                      (sck_ne                       ),
-          . shift_out                   (shift_out                    ),
-          . shift_in                    (shift_in                     ),
+          . shift                       (shift                        ),
+          . sample                      (sample                       ),
           . load_byte                   (load_byte                    ),
           . byte_out                    (byte_out                     ),
           . byte_in                     (byte_in                      )
@@ -200,6 +230,9 @@
 
 
            // configuration signal
+          . cfg_cpol                    (cfg_cpol                     ),
+          . cfg_cpha                    (cfg_cpha                     ),
+          . cfg_bit_order               (cfg_bit_order                ),
           . cfg_tgt_sel                 (cfg_tgt_sel                  ),
           . cfg_op_req                  (cfg_op_req                   ), // SPI operation request
           . cfg_endian                  (cfg_endian                   ),
diff --git a/verilog/rtl/uart/src/uart_core.sv b/verilog/rtl/uart/src/uart_core.sv
index 948cd35..653e285 100644
--- a/verilog/rtl/uart/src/uart_core.sv
+++ b/verilog/rtl/uart/src/uart_core.sv
@@ -185,8 +185,9 @@
 
 //##############################################################
 // 16x Baud clock generation
+//  Baud Rate config = (F_CPU / (BAUD * 16)) - 2 
 // Example: to generate 19200 Baud clock from 50Mhz Link clock
-//    50 * 1000 * 1000 / (2 + cfg_baud_16x) = 19200 * 16
+//    cfg_baud_16x = ((50 * 1000 * 1000) / (19200 * 16)) - 2
 //    cfg_baud_16x = 0xA0 (160)
 //###############################################################
 
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 34c8794..3429628 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -35,6 +35,7 @@
 ////      8. 2KB icache and 2KB dcache                            ////
 ////      8. 6 Channel ADC                                        ////
 ////      9. Pinmux with GPIO and 6 PWM                           ////
+////
 ////                                                              ////
 ////  To Do:                                                      ////
 ////    nothing                                                   ////
@@ -216,6 +217,20 @@
 ////         SPI ISP boot option added in wb_host, spi slave uses ////
 ////         same spi master interface, but will be active only   ////
 ////         when internal SPI config disabled + RESET PIN = 0    ////
+////    4.9  Aug 5 2022, Dinesh A                                 ////
+////         changes in sspim                                     ////
+////           A. SPI Mode 0 to 3 support added,                  ////
+////           B. SPI Duplex mode TX-RX Mode added                ////
+////    5.0  Aug 15 2022, Dinesh A                                ////
+////          A. 15 Hardware Semahore added                       ////
+////          B. Pinmux Address Space are Split as                ////
+////             `define ADDR_SPACE_PINMUX  32'h1002_0000         ////
+////             `define ADDR_SPACE_GLBL    32'h1002_0000         ////
+////             `define ADDR_SPACE_GPIO    32'h1002_0040         ////
+////             `define ADDR_SPACE_PWM     32'h1002_0080         ////
+////             `define ADDR_SPACE_TIMER   32'h1002_00C0         ////
+////             `define ADDR_SPACE_SEMA    32'h1002_0100         ////
+////                                                              ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
 //// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
@@ -243,6 +258,32 @@
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 
+/*********************************************************************
+    Memory Map:                                               ////
+                                                              ////
+       SOC Memory Map                                         ////
+       0x0000_0000 to 0x0FFF_FFFF  - QSPIM MEMORY             ////
+       0x1000_0000 to 0x1000_00FF  - QSPIM REG
+       0x1001_0000 to 0x1001_003F  - UART0
+       0x1001_0040 to 0x1001_007F  - I2
+       0x1001_0080 to 0x1001_00BF  - USB
+       0x1001_00C0 to 0x1001_00FF  - SSPIM
+       0x1001_0100 to 0x1001_013F  - UART1
+       0x1002_0000 to 0x1002_00FF  - PINMUX
+
+       Caravel Memory Map:
+-----------------------------------------------------------------------
+      caravel user space is 0x3000_0000 to 0x300F_FFFF
+      So we have allocated 
+      0x3008_0000 - 0x3008_00FF - Assigned to WB Host Address Space
+      Since We need more than 16MB Address space to access SDRAM/SPI we have
+      added indirect MSB 13 bit address select option
+      So Address will be {Bank_Sel[15:3], wbm_adr_i[18:0]}
+ ---------------------------------------------------------------------
+       0x3080_0000 to 0x3080_00FF  - WB HOST 
+       0x3000_0000 to 0x307F_FFFF  - Indirect Address
+                                     {Bank_Sel[15:3],WB ADDR[18:0]}
+***********************************************************************/
 
 module user_project_wrapper (
 `ifdef USE_POWER_PINS
@@ -418,7 +459,7 @@
 //    Global Register Wishbone Interface
 //---------------------------------------------------------------------
 wire                           wbd_glbl_stb_o                         ; // strobe/request
-wire   [7:0]                   wbd_glbl_adr_o                         ; // address
+wire   [8:0]                   wbd_glbl_adr_o                         ; // address
 wire                           wbd_glbl_we_o                          ; // write
 wire   [WB_WIDTH-1:0]          wbd_glbl_dat_o                         ; // data output
 wire   [3:0]                   wbd_glbl_sel_o                         ; // byte enable
@@ -1214,7 +1255,7 @@
 
      );
 
-pinmux u_pinmux(
+pinmux_top u_pinmux(
 `ifdef USE_POWER_PINS
           .vccd1                   (vccd1                   ),// User area 1 1.8V supply
           .vssd1                   (vssd1                   ),// User area 1 digital ground
diff --git a/verilog/rtl/user_reg_map.v b/verilog/rtl/user_reg_map.v
index 42f9e73..53d8331 100644
--- a/verilog/rtl/user_reg_map.v
+++ b/verilog/rtl/user_reg_map.v
@@ -9,6 +9,11 @@
 `define ADDR_SPACE_SSPI    32'h3001_00C0
 `define ADDR_SPACE_UART1   32'h3001_0100
 `define ADDR_SPACE_PINMUX  32'h3002_0000
+`define ADDR_SPACE_GLBL    32'h3002_0000
+`define ADDR_SPACE_GPIO    32'h3002_0040
+`define ADDR_SPACE_PWM     32'h3002_0080
+`define ADDR_SPACE_TIMER   32'h3002_00C0
+`define ADDR_SPACE_SEMA    32'h3002_0100
 `define ADDR_SPACE_WBHOST  32'h3008_0000
 
 //--------------------------------------------------
@@ -21,41 +26,74 @@
 `define WBHOST_PLL_CTRL           8'h10  // reg_4  - PLL Control
 
 //--------------------------------------------------
-// Pinmux Register
+// GLOBAL Register
 // -------------------------------------------------
+`define GLBL_CFG_CHIP_ID       8'h00  // reg_0  - Chip ID
+`define GLBL_CFG_CFG0          8'h04  // reg_1  - Global Config-0
+`define GLBL_CFG_CFG1          8'h08  // reg_2  - Global Config-1
+`define GLBL_CFG_INTR_MSK      8'h0C  // reg_3  - Global Interrupt Mask
+`define GLBL_CFG_INTR_STAT     8'h10  // reg_4  - Global Interrupt
+`define GLBL_CFG_MUTI_FUNC     8'h14  // reg_5  - Multi functional sel
+`define GLBL_CFG_SOFT_REG_0    8'h18  // reg_6 - Sof Register
+`define GLBL_CFG_SOFT_REG_1    8'h1C  // reg_7 - Sof Register
+`define GLBL_CFG_SOFT_REG_2    8'h20  // reg_8 - Sof Register
+`define GLBL_CFG_SOFT_REG_3    8'h24  // reg_9 - Sof Register
+`define GLBL_CFG_SOFT_REG_4    8'h28  // reg_10 - Sof Register
+`define GLBL_CFG_SOFT_REG_5    8'h2C  // reg_11 - Sof Register
 
-`define PINMUX_CHIP_ID           8'h00  // reg_0  - Chip ID
-`define PINMUX_GBL_CFG0          8'h04  // reg_1  - Global Config-2
-`define PINMUX_GBL_CFG1          8'h08  // reg_2  - Global Config-1
-`define PINMUX_GBL_INTR_MSK      8'h0C  // reg_3  - Global Interrupt Mask
-`define PINMUX_GBL_INTR          8'h10  // reg_4  - Global Interrupt
-`define PINMUX_GPIO_IDATA        8'h14  // reg_5  - GPIO Data In
-`define PINMUX_GPIO_ODATA        8'h18  // reg_6  - GPIO Data Out
-`define PINMUX_GPIO_DSEL         8'h1C  // reg_7  - GPIO Direction Select
-`define PINMUX_GPIO_TYPE         8'h20  // reg_8  - GPIO TYPE - Static/Waveform
-`define PINMUX_GPIO_INTR_STAT    8'h24  // reg_9  - GPIO Interrupt status
-`define PINMUX_GPIO_INTR_CLR     8'h24  // reg_9  - GPIO Interrupt Clear
-`define PINMUX_GPIO_INTR_SET     8'h28  // reg_10 - GPIO Interrupt Set
-`define PINMUX_GPIO_INTR_MASK    8'h2C  // reg_11 - GPIO Interrupt Mask
-`define PINMUX_GPIO_POS_INTR     8'h30  // reg_12 - GPIO Posedge Interrupt
-`define PINMUX_GPIO_NEG_INTR     8'h34  // reg_13 - GPIO Neg Interrupt
-`define PINMUX_GPIO_MULTI_FUNC   8'h38  // reg_14 - GPIO Multi Function
-`define PINMUX_SOFT_REG_0        8'h3C  // reg_15 - Soft Register
-`define PINMUX_CFG_PWM0          8'h40  // reg_16 - PWM Reg-0
-`define PINMUX_CFG_PWM1          8'h44  // reg_17 - PWM Reg-1
-`define PINMUX_CFG_PWM2          8'h48  // reg_18 - PWM Reg-2
-`define PINMUX_CFG_PWM3          8'h4C  // reg_19 - PWM Reg-3
-`define PINMUX_CFG_PWM4          8'h50  // reg_20 - PWM Reg-4
-`define PINMUX_CFG_PWM5          8'h54  // reg_21 - PWM Reg-5
-`define PINMUX_SOFT_REG_1        8'h58  // reg_22 - Sof Register
-`define PINMUX_SOFT_REG_2        8'h5C  // reg_23 - Sof Register
-`define PINMUX_SOFT_REG_3        8'h60  // reg_24 - Sof Register
-`define PINMUX_SOFT_REG_4        8'h64  // reg_25 - Sof Register
-`define PINMUX_SOFT_REG_5        8'h68  // reg_26 - Sof Register
-`define PINMUX_SOFT_REG_6        8'h6C  // reg_27 - Sof Register
-`define PINMUX_CFG_TIMER0        8'h70  // reg_28 - Timer-0
-`define PINMUX_CFG_TIMER1        8'h74  // reg_28 - Timer-1
-`define PINMUX_CFG_TIMER2        8'h78  // reg_28 - Timer-2
+//--------------------------------------------------
+// GPIO Register
+// -------------------------------------------------
+`define GPIO_CFG_DSEL         8'h00  // reg_0  - GPIO Direction Select
+`define GPIO_CFG_TYPE         8'h04  // reg_1  - GPIO TYPE - Static/Waveform
+`define GPIO_CFG_IDATA        8'h08  // reg_2  - GPIO Data In
+`define GPIO_CFG_ODATA        8'h0C  // reg_3  - GPIO Data Out
+`define GPIO_CFG_INTR_STAT    8'h10  // reg_4  - GPIO Interrupt status
+`define GPIO_CFG_INTR_CLR     8'h10  // reg_4  - GPIO Interrupt Clear
+`define GPIO_CFG_INTR_SET     8'h14  // reg_5  - GPIO Interrupt Set
+`define GPIO_CFG_INTR_MASK    8'h18  // reg_6  - GPIO Interrupt Mask
+`define GPIO_CFG_POS_INTR_SEL 8'h1C  // reg_7  - GPIO Posedge Interrupt
+`define GPIO_CFG_NEG_INTR_SEL 8'h20  // reg_8  - GPIO Neg Interrupt
+
+
+//--------------------------------------------------
+// PWM Register
+// -------------------------------------------------
+`define PWM_GLBL_CFG          8'h00  // reg_0 - PWM Global Config
+`define PWM_CFG_PWM_0         8'h04  // reg_1 - PWM Reg-0
+`define PWM_CFG_PWM_1         8'h08  // reg_2 - PWM Reg-1
+`define PWM_CFG_PWM_2         8'h0C  // reg_3 - PWM Reg-2
+`define PWM_CFG_PWM_3         8'h10  // reg_4 - PWM Reg-3
+`define PWM_CFG_PWM_4         8'h14  // reg_5 - PWM Reg-4
+`define PWM_CFG_PWM_5         8'h18  // reg_6 - PWM Reg-5
+
+//--------------------------------------------------
+// TIMER Register
+// -------------------------------------------------
+`define TIMER_CFG_GLBL        8'h00  // reg_0 - Global Config
+`define TIMER_CFG_TIMER_0     8'h04  // reg_1 - Timer-0
+`define TIMER_CFG_TIMER_1     8'h08  // reg_2 - Timer-1
+`define TIMER_CFG_TIMER_2     8'h0C  // reg_3 - Timer-2
+
+//--------------------------------------------------
+// SEMAPHORE Register
+// -------------------------------------------------
+`define SEMA_CFG_LOCK_0       8'h00  // reg_0  - Semaphore Lock Bit-0
+`define SEMA_CFG_LOCK_1       8'h04  // reg_1  - Semaphore Lock Bit-1
+`define SEMA_CFG_LOCK_2       8'h08  // reg_2  - Semaphore Lock Bit-2
+`define SEMA_CFG_LOCK_3       8'h0C  // reg_3  - Semaphore Lock Bit-3
+`define SEMA_CFG_LOCK_4       8'h10  // reg_4  - Semaphore Lock Bit-4
+`define SEMA_CFG_LOCK_5       8'h14  // reg_5  - Semaphore Lock Bit-5
+`define SEMA_CFG_LOCK_6       8'h18  // reg_6  - Semaphore Lock Bit-6
+`define SEMA_CFG_LOCK_7       8'h1C  // reg_7  - Semaphore Lock Bit-7
+`define SEMA_CFG_LOCK_8       8'h20  // reg_8  - Semaphore Lock Bit-8
+`define SEMA_CFG_LOCK_9       8'h24  // reg_9  - Semaphore Lock Bit-9
+`define SEMA_CFG_LOCK_10      8'h28  // reg_10 - Semaphore Lock Bit-10
+`define SEMA_CFG_LOCK_11      8'h2C  // reg_11 - Semaphore Lock Bit-11
+`define SEMA_CFG_LOCK_12      8'h30  // reg_12 - Semaphore Lock Bit-12
+`define SEMA_CFG_LOCK_13      8'h34  // reg_13 - Semaphore Lock Bit-13
+`define SEMA_CFG_LOCK_14      8'h38  // reg_14 - Semaphore Lock Bit-14
+`define SEMA_CFG_STATUS       8'h3C  // reg_15 - Semaphore Lock Status
 
 //----------------------------------------------------------
 // QSPI Register Map
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv
index 26029c2..d3d85cc 100644
--- a/verilog/rtl/wb_host/src/wb_host.sv
+++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -411,11 +411,11 @@
 // Locally there register are define to control the reset and clock for user
 // area
 //-----------------------------------------------------------------------
-// caravel user space is 0x3000_0000 to 0x3007_FFFF
+// caravel user space is 0x3000_0000 to 0x300F_FFFF
 // So we have allocated 
 // 0x3008_0000 - 0x3008_00FF - Assigned to WB Host Address Space
 // Since We need more than 16MB Address space to access SDRAM/SPI we have
-// added indirect MSB 8 bit address select option
+// added indirect MSB 13 bit address select option
 // So Address will be {Bank_Sel[15:3], wbm_adr_i[18:0]}
 // ---------------------------------------------------------------------
 assign reg_sel       = wb_req & (wb_adr_i[19] == 1'b1);
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
index 9fb6344..7e348fc 100644
--- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
+++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -203,8 +203,8 @@
          input	logic 	        s2_wbd_ack_i,
          // input	logic 	s2_wbd_err_i, - unused
          output	logic [31:0]	s2_wbd_dat_o,
-         output	logic [7:0]	s2_wbd_adr_o, // glbl reg need only 8 bits
-         output	logic [3:0]	s2_wbd_sel_o,
+         output	logic [8:0]	    s2_wbd_adr_o, // glbl reg need only 9 bits
+         output	logic [3:0]	    s2_wbd_sel_o,
          output	logic 	        s2_wbd_we_o,
          output	logic 	        s2_wbd_cyc_o,
          output	logic 	        s2_wbd_stb_o
@@ -677,7 +677,7 @@
  assign  s1_wbd_stb_o =  s1_wb_wr.wbd_stb ;
                       
  assign  s2_wbd_dat_o =  s2_wb_wr.wbd_dat ;
- assign  s2_wbd_adr_o =  s2_wb_wr.wbd_adr[7:0] ; // Global Reg Need 8 bit
+ assign  s2_wbd_adr_o =  s2_wb_wr.wbd_adr[8:0] ; // Global Reg Need 8 bit
  assign  s2_wbd_sel_o =  s2_wb_wr.wbd_sel ;
  assign  s2_wbd_we_o  =  s2_wb_wr.wbd_we  ;
  assign  s2_wbd_cyc_o =  s2_wb_wr.wbd_cyc ;