diff --git a/Makefile b/Makefile
index a54eedb..dc5ba38 100644
--- a/Makefile
+++ b/Makefile
@@ -247,18 +247,18 @@
 	fi
 
 zip:
-	gzip -f lef/*
-	gzip -f gds/*
-	gzip -f spef/*
-	gzip -f spi/lvs/*
-	gzip -f verilog/gl/*
+	gzip -f -r lef/*
+	gzip -f -r gds/*
+	gzip -f -r spef/*
+	gzip -f -r spi/lvs/*
+	gzip -f -r verilog/gl/*
 
 unzip:
-	gzip -d lef/*
-	gzip -d gds/*
-	gzip -d spef/*
-	gzip -d spi/lvs/*
-	gzip -d verilog/gl/*
+	gzip -d -r lef/*
+	gzip -d -r gds/*
+	gzip -d -r spef/*
+	gzip -d -r spi/lvs/*
+	gzip -d -r verilog/gl/*
 
 .PHONY: help
 help:
diff --git a/openlane/bus_rep_east/config.tcl b/openlane/bus_rep_east/config.tcl
new file mode 100755
index 0000000..0362cfc
--- /dev/null
+++ b/openlane/bus_rep_east/config.tcl
@@ -0,0 +1,134 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+# Global
+# ------
+
+set script_dir [file dirname [file normalize [info script]]]
+# Name
+set ::env(DESIGN_NAME) bus_rep_east
+
+
+set ::env(DESIGN_IS_CORE) "1"
+set ::env(FP_PDN_CORE_RING) {1}
+
+# Timing configuration
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) ""
+set ::env(CLOCK_NET) ""
+
+set ::env(SYNTH_MAX_FANOUT) 4
+set ::env(SYNTH_BUFFERING) {0}
+
+
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+
+# Sources
+# -------
+
+# Local sources + no2usb sources
+set ::env(VERILOG_FILES) "\
+        $::env(DESIGN_DIR)/../../verilog/rtl/bus_rep/bus_rep_east.sv \
+	"
+
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
+
+set ::env(SYNTH_PARAMETERS) "BUS_REP_WD=45 "
+
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+#set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+#set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+
+set ::env(LEC_ENABLE) 0
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+
+# Floorplanning
+# -------------
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 3420 50"
+
+#set ::env(GRT_OBS) "met4  0 0 300 1725"
+
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
+
+#set ::env(PDN_CFG) $::env(DESIGN_DIR)/pdn.tcl
+
+
+
+set ::env(PL_TIME_DRIVEN) 1
+set ::env(PL_TARGET_DENSITY) "0.20"
+set ::env(CELL_PAD) "8"
+set ::env(GRT_ADJUSTMENT) 0.2
+
+# helps in anteena fix
+set ::env(USE_ARC_ANTENNA_CHECK) "0"
+
+
+#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+## CTS
+set ::env(CLOCK_TREE_SYNTH) {0}
+
+## Placement
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) "0"
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) "0"
+
+## Routing
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0"
+
+#LVS Issue - DEF Base looks to having issue
+set ::env(MAGIC_EXT_USE_GDS) {1}
+
+#set ::env(GLB_RT_MAXLAYER) 3
+set ::env(RT_MAX_LAYER) {met3}
+set ::env(FP_PDN_LOWER_LAYER) {met2}
+set ::env(FP_PDN_UPPER_LAYER) {met3}
+
+set ::env(FP_IO_HLAYER) {met2}
+set ::env(FP_IO_VLAYER) {met1}
+
+#Lef 
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+
+## Placement
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) 2
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) "500"
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) "2.0"
+
+set ::env(ECO_ENABLE) {0}
+#set ::env(CURRENT_STEP) "synthesis"
+#set ::env(LAST_STEP) "parasitics_sta"
+
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "1"
+set ::env(QUIT_ON_LVS_ERROR) "1"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/bus_rep_east/interactive.tcl b/openlane/bus_rep_east/interactive.tcl
new file mode 100755
index 0000000..5b5c6c8
--- /dev/null
+++ b/openlane/bus_rep_east/interactive.tcl
@@ -0,0 +1,337 @@
+#!/usr/bin/env tclsh
+# Copyright 2020-2022 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+package require openlane; # provides the utils as well
+proc run_placement_step {args} {
+    if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
+        set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
+    }
+
+    run_placement
+}
+
+proc run_cts_step {args} {
+    if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
+        set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
+    }
+
+    run_cts
+    run_resizer_timing
+    if { $::env(RSZ_USE_OLD_REMOVER) == 1} {
+        remove_buffers_from_nets
+    }
+}
+
+proc run_routing_step {args} {
+    if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
+        set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
+    }
+    if { $::env(ECO_ENABLE) == 0 } {
+        run_routing
+    }
+}
+
+proc run_parasitics_sta_step {args} {
+    if { ! [ info exists ::env(PARSITICS_CURRENT_DEF) ] } {
+        set ::env(PARSITICS_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(PARSITICS_CURRENT_DEF)
+    }
+
+    if { $::env(RUN_SPEF_EXTRACTION) && ($::env(ECO_ENABLE) == 0)} {
+        run_parasitics_sta
+    }
+}
+
+proc run_diode_insertion_2_5_step {args} {
+    if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
+        set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
+    }
+    if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
+        run_antenna_check
+        heal_antenna_violators; # modifies the routed DEF
+    }
+
+}
+
+proc run_irdrop_report_step {args} {
+    if { $::env(RUN_IRDROP_REPORT) } {
+        run_irdrop_report
+    }
+}
+
+proc run_lvs_step {{ lvs_enabled 1 }} {
+    if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
+        set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
+    }
+
+    if { $lvs_enabled && $::env(RUN_LVS) } {
+        run_magic_spice_export;
+        run_lvs; # requires run_magic_spice_export
+    }
+
+}
+
+proc run_drc_step {{ drc_enabled 1 }} {
+    if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
+        set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
+    }
+    if { $drc_enabled } {
+        if { $::env(RUN_MAGIC_DRC) } {
+            run_magic_drc
+        }
+        if {$::env(RUN_KLAYOUT_DRC)} {
+            run_klayout_drc
+        }
+    }
+}
+
+proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
+    if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
+        set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
+    }
+    if { $antenna_check_enabled } {
+        run_antenna_check
+    }
+}
+
+proc run_erc_step {args} {
+    if { $::env(RUN_CVC) } {
+        run_erc
+    }
+}
+
+proc run_eco_step {args} {
+    if { $::env(ECO_ENABLE) == 1 } {
+        run_eco_flow
+    }
+}
+
+proc run_magic_step {args} {
+    if {$::env(RUN_MAGIC)} {
+        run_magic
+    }
+}
+
+proc run_klayout_step {args} {
+    if {$::env(RUN_KLAYOUT)} {
+        run_klayout
+    }
+    if {$::env(RUN_KLAYOUT_XOR)} {
+        run_klayout_gds_xor
+    }
+}
+
+proc run_post_run_hooks {} {
+    if { [file exists $::env(DESIGN_DIR)/hooks/post_run.py]} {
+        puts_info "Running post run hook"
+        set result [exec $::env(OPENROAD_BIN) -exit -no_init -python $::env(DESIGN_DIR)/hooks/post_run.py]
+        puts_info "$result"
+    } else {
+        puts_info "hooks/post_run.py not found, skipping"
+    }
+}
+
+proc run_floorplan {args} {
+    # |----------------------------------------------------|
+    # |----------------   2. FLOORPLAN   ------------------|
+    # |----------------------------------------------------|
+    #
+    # intial fp
+    init_floorplan
+
+    # check for deprecated io variables
+    if { [info exists ::env(FP_IO_HMETAL)]} {
+        set ::env(FP_IO_HLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_HMETAL) - 1}]]
+        puts_warn "You're using FP_IO_HMETAL in your configuration, which is a deprecated variable that will be removed in the future."
+        puts_warn "We recommend you update your configuration as follows:"
+        puts_warn "\tset ::env(FP_IO_HLAYER) {$::env(FP_IO_HLAYER)}"
+    }
+
+    if { [info exists ::env(FP_IO_VMETAL)]} {
+        set ::env(FP_IO_VLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_VMETAL) - 1}]]
+        puts_warn "You're using FP_IO_VMETAL in your configuration, which is a deprecated variable that will be removed in the future."
+        puts_warn "We recommend you update your configuration as follows:"
+        puts_warn "\tset ::env(FP_IO_VLAYER) {$::env(FP_IO_VLAYER)}"
+    }
+
+
+    # place io
+    if { [info exists ::env(FP_PIN_ORDER_CFG)] } {
+        place_io_ol
+    } else {
+        if { [info exists ::env(FP_CONTEXT_DEF)] && [info exists ::env(FP_CONTEXT_LEF)] } {
+            place_io
+            global_placement_or
+            place_contextualized_io \
+                -lef $::env(FP_CONTEXT_LEF) \
+                -def $::env(FP_CONTEXT_DEF)
+        } else {
+            place_io
+        }
+    }
+
+    apply_def_template
+
+    #if { [info exist ::env(EXTRA_LEFS)] } {
+        if { [info exist ::env(MACRO_PLACEMENT_CFG)] } {
+            file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(placement_tmpfiles)/macro_placement.cfg
+            manual_macro_placement -f
+        } else {
+        #    global_placement_or
+        #    basic_macro_placement
+        }
+    #}
+
+    if { $::env(RUN_TAP_DECAP_INSERTION) } {
+        tap_decap_or
+    }
+
+    scrot_klayout -layout $::env(CURRENT_DEF) -log $::env(floorplan_logs)/screenshot.log
+
+    run_power_grid_generation
+}
+
+
+
+proc run_flow {args} {
+    set options {
+        {-design optional}
+        {-from optional}
+        {-to optional}
+        {-save_path optional}
+        {-override_env optional}
+    }
+    set flags {-save -run_hooks -no_lvs -no_drc -no_antennacheck -gui}
+    parse_key_args "run_non_interactive_mode" args arg_values $options flags_map $flags -no_consume
+
+    prep {*}$args
+    # signal trap SIGINT save_state;
+
+    if { [info exists flags_map(-gui)] } {
+        or_gui
+        return
+    }
+    if { [info exists arg_values(-override_env)] } {
+        load_overrides $arg_values(-override_env)
+    }
+
+    set LVS_ENABLED 1
+    set DRC_ENABLED 1
+
+    set ANTENNACHECK_ENABLED [expr ![info exists flags_map(-no_antennacheck)] ]
+
+    set steps [dict create \
+        "synthesis" "run_synthesis" \
+        "floorplan" "run_floorplan" \
+        "placement" "run_placement_step" \
+        "cts" "run_cts_step" \
+        "routing" "run_routing_step" \
+        "parasitics_sta" "run_parasitics_sta_step" \
+        "eco" "run_eco_step" \
+        "diode_insertion" "run_diode_insertion_2_5_step" \
+        "irdrop" "run_irdrop_report_step" \
+        "gds_magic" "run_magic_step" \
+        "gds_klayout" "run_klayout_step" \
+        "lvs" "run_lvs_step $LVS_ENABLED " \
+        "drc" "run_drc_step $DRC_ENABLED " \
+        "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED " \
+        "cvc" "run_lef_cvc"
+    ]
+
+    if { [info exists arg_values(-from) ]} {
+        puts_info "Starting flow at $arg_values(-from)..."
+        set ::env(CURRENT_STEP) $arg_values(-from)
+    } elseif {  [info exists ::env(CURRENT_STEP) ] } {
+        puts_info "Resuming flow from $::env(CURRENT_STEP)..."
+    } else {
+        set ::env(CURRENT_STEP) "synthesis"
+    }
+
+    set_if_unset arg_values(-from) $::env(CURRENT_STEP)
+    set_if_unset arg_values(-to) "cvc"
+
+    set exe 0;
+    dict for {step_name step_exe} $steps {
+        if { [ string equal $arg_values(-from) $step_name ] } {
+            set exe 1;
+        }
+
+        if { $exe } {
+            # For when it fails
+            set ::env(CURRENT_STEP) $step_name
+            [lindex $step_exe 0] [lindex $step_exe 1] ;
+        }
+
+        if { [ string equal $arg_values(-to) $step_name ] } {
+            set exe 0:
+            break;
+        }
+
+    }
+
+    # for when it resumes
+    set steps_as_list [dict keys $steps]
+    set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
+    set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
+
+    # Saves to <RUN_DIR>/results/final
+    save_final_views
+
+    # Saves to design directory or custom
+    if {  [info exists flags_map(-save) ] } {
+        if { ! [info exists arg_values(-save_path)] } {
+            set arg_values(-save_path) $::env(DESIGN_DIR)
+        }
+        save_final_views\
+            -save_path $arg_values(-save_path)\
+            -tag $::env(RUN_TAG)
+    }
+    calc_total_runtime
+    save_state
+    generate_final_summary_report
+
+    check_timing_violations
+
+    if { [info exists arg_values(-save_path)]\
+        && $arg_values(-save_path) != "" } {
+        set ::env(HOOK_OUTPUT_PATH) "[file normalize $arg_values(-save_path)]"
+    } else {
+        set ::env(HOOK_OUTPUT_PATH) $::env(RESULTS_DIR)/final
+    }
+
+    if {[info exists flags_map(-run_hooks)]} {
+        run_post_run_hooks
+    }
+
+    puts_success "Flow complete."
+
+    show_warnings "Note that the following warnings have been generated:"
+}
+
+run_flow {*}$argv
diff --git a/openlane/bus_rep_east/macro.cfg b/openlane/bus_rep_east/macro.cfg
new file mode 100644
index 0000000..e84abca
--- /dev/null
+++ b/openlane/bus_rep_east/macro.cfg
@@ -0,0 +1,46 @@
+u_rp\[0\].u_buf			7.82	10.88	FN
+u_rp\[1\].u_buf			85.1	10.88	FN
+u_rp\[2\].u_buf			162.38	10.88	FN
+u_rp\[3\].u_buf			239.66	10.88	FN
+u_rp\[4\].u_buf			316.94	10.88	FN
+u_rp\[5\].u_buf			394.22	10.88	FN
+u_rp\[6\].u_buf			471.5	10.88	FN
+u_rp\[7\].u_buf			548.78	10.88	FN
+u_rp\[8\].u_buf			626.06	10.88	FN
+u_rp\[9\].u_buf			703.34	10.88	FN
+u_rp\[10\].u_buf			780.62	10.88	FN
+u_rp\[11\].u_buf			857.9	10.88	FN
+u_rp\[12\].u_buf			935.18	10.88	FN
+u_rp\[13\].u_buf			1012.46	10.88	FN
+u_rp\[14\].u_buf			1089.74	10.88	FN
+u_rp\[15\].u_buf			1167.02	10.88	FN
+u_rp\[16\].u_buf			1244.3	10.88	FN
+u_rp\[17\].u_buf			1321.58	10.88	FN
+u_rp\[18\].u_buf			1398.86	10.88	FN
+u_rp\[19\].u_buf			1476.14	10.88	FN
+u_rp\[20\].u_buf			1553.42	10.88	FN
+u_rp\[21\].u_buf			1630.7	10.88	FN
+u_rp\[22\].u_buf			1707.98	10.88	FN
+u_rp\[23\].u_buf			1785.26	10.88	FN
+u_rp\[24\].u_buf			1862.54	10.88	FN
+u_rp\[25\].u_buf			1939.82	10.88	FN
+u_rp\[26\].u_buf			2017.1	10.88	FN
+u_rp\[27\].u_buf			2094.38	10.88	FN
+u_rp\[28\].u_buf			2171.66	10.88	FN
+u_rp\[29\].u_buf			2248.94	10.88	FN
+u_rp\[30\].u_buf			2326.22	10.88	FN
+u_rp\[31\].u_buf			2403.5	10.88	FN
+u_rp\[32\].u_buf			2480.78	10.88	FN
+u_rp\[33\].u_buf			2558.06	10.88	FN
+u_rp\[34\].u_buf			2635.34	10.88	FN
+u_rp\[35\].u_buf			2712.62	10.88	FN
+u_rp\[36\].u_buf			2789.9	10.88	FN
+u_rp\[37\].u_buf			2867.18	10.88	FN
+u_rp\[38\].u_buf			2944.46	10.88	FN
+u_rp\[39\].u_buf			3021.74	10.88	FN
+u_rp\[40\].u_buf			3099.02	10.88	FN
+u_rp\[41\].u_buf			3176.3	10.88	FN
+u_rp\[42\].u_buf			3253.58	10.88	FN
+u_rp\[43\].u_buf			3330.86	10.88	FN
+u_rp\[44\].u_buf			3408.14	10.88	FN
+
diff --git a/openlane/bus_rep_east/pdn.tcl b/openlane/bus_rep_east/pdn.tcl
new file mode 100644
index 0000000..1fe689b
--- /dev/null
+++ b/openlane/bus_rep_east/pdn.tcl
@@ -0,0 +1,49 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# Power nets
+set ::power_nets $::env(VDD_PIN)
+set ::ground_nets $::env(GND_PIN)
+
+set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
+
+pdngen::specify_grid stdcell {
+    name grid
+    rails {
+	    met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
+    }
+    straps {
+	    met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
+	    met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
+    }
+    connect {{met1 met4} {met4 met5}}
+}
+
+pdngen::specify_grid macro {
+    power_pins "VPWR"
+    ground_pins "VGND"
+    blockages "li1 met1 met2 met3 met4"
+    straps { 
+    } 
+    connect {{met4_PIN_ver met5}}
+}
+
+set ::halo 5
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;
diff --git a/openlane/bus_rep_east/pin_order.cfg b/openlane/bus_rep_east/pin_order.cfg
new file mode 100644
index 0000000..bfe94f9
--- /dev/null
+++ b/openlane/bus_rep_east/pin_order.cfg
@@ -0,0 +1,99 @@
+#BUS_SORT
+
+#MANUAL_PLACE
+
+#N
+ch_out\[0\]    0 0 225
+ch_out\[1\]    
+ch_in\[2\]
+ch_out\[3\]    
+ch_out\[4\]    
+ch_in\[5\]
+ch_out\[6\]    
+ch_out\[7\]    
+ch_in\[8\]
+ch_out\[9\]    
+ch_out\[10\]    
+ch_in\[11\]
+ch_out\[12\]    
+ch_out\[13\]    
+ch_in\[14\]
+ch_out\[15\]    
+ch_out\[16\]    
+ch_in\[17\]
+ch_out\[18\]    
+ch_out\[19\]    
+ch_in\[20\]
+ch_out\[21\]    
+ch_out\[22\]    
+ch_in\[23\]
+ch_out\[24\]    
+ch_out\[25\]    
+ch_in\[26\]
+ch_out\[27\]    
+ch_out\[28\]    
+ch_in\[29\]
+ch_out\[30\]    
+ch_out\[31\]    
+ch_in\[32\]
+ch_out\[33\]    
+ch_out\[34\]    
+ch_in\[35\]
+ch_out\[36\]    
+ch_out\[37\]    
+ch_in\[38\]
+ch_out\[39\]    
+ch_out\[40\]    
+ch_in\[41\]
+ch_out\[42\]    
+ch_out\[43\]    
+ch_in\[44\]
+
+#S
+ch_in\[0\]    1140 0 6
+ch_in\[1\]
+ch_out\[2\]
+ch_in\[3\]    
+ch_in\[4\]
+ch_out\[5\]
+ch_in\[6\]    
+ch_in\[7\]
+ch_out\[8\]
+ch_in\[9\]    
+ch_in\[10\]
+ch_out\[11\]
+ch_in\[12\]    
+ch_in\[13\]
+ch_out\[14\]
+ch_in\[15\]    
+ch_in\[16\]
+ch_out\[17\]
+ch_in\[18\]    
+ch_in\[19\]
+ch_out\[20\]
+ch_in\[21\]    
+ch_in\[22\]
+ch_out\[23\]
+ch_in\[24\]    
+ch_in\[25\]
+ch_out\[26\]
+ch_in\[27\]    
+ch_in\[28\]
+ch_out\[29\]
+ch_in\[30\]    
+ch_in\[31\]
+ch_out\[32\]
+ch_in\[33\]    
+ch_in\[34\]
+ch_out\[35\]
+ch_in\[36\]    
+ch_in\[37\]
+ch_out\[38\]
+ch_in\[39\]    
+ch_in\[40\]
+ch_out\[41\]
+ch_in\[42\]    
+ch_in\[43\]
+ch_out\[44\]
+
+
diff --git a/openlane/bus_rep_north/config.tcl b/openlane/bus_rep_north/config.tcl
new file mode 100755
index 0000000..4168921
--- /dev/null
+++ b/openlane/bus_rep_north/config.tcl
@@ -0,0 +1,134 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+# Global
+# ------
+
+set script_dir [file dirname [file normalize [info script]]]
+# Name
+set ::env(DESIGN_NAME) bus_rep_north
+
+
+set ::env(DESIGN_IS_CORE) "1"
+set ::env(FP_PDN_CORE_RING) {1}
+
+# Timing configuration
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) ""
+set ::env(CLOCK_NET) ""
+
+set ::env(SYNTH_MAX_FANOUT) 4
+set ::env(SYNTH_BUFFERING) {0}
+
+
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+
+# Sources
+# -------
+
+# Local sources + no2usb sources
+set ::env(VERILOG_FILES) "\
+        $::env(DESIGN_DIR)/../../verilog/rtl/bus_rep/bus_rep_north.sv \
+	"
+
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
+
+set ::env(SYNTH_PARAMETERS) "BUS_REP_WD=27 "
+
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+#set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+#set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+
+set ::env(LEC_ENABLE) 0
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+
+# Floorplanning
+# -------------
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 2650 50"
+
+#set ::env(GRT_OBS) "met4  0 0 300 1725"
+
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
+
+#set ::env(PDN_CFG) $::env(DESIGN_DIR)/pdn.tcl
+
+
+
+set ::env(PL_TIME_DRIVEN) 1
+set ::env(PL_TARGET_DENSITY) "0.20"
+set ::env(CELL_PAD) "8"
+set ::env(GRT_ADJUSTMENT) 0.2
+
+# helps in anteena fix
+set ::env(USE_ARC_ANTENNA_CHECK) "0"
+
+
+#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+## CTS
+set ::env(CLOCK_TREE_SYNTH) {0}
+
+## Placement
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) "0"
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) "0"
+
+## Routing
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0"
+
+#LVS Issue - DEF Base looks to having issue
+set ::env(MAGIC_EXT_USE_GDS) {1}
+
+#set ::env(GLB_RT_MAXLAYER) 3
+set ::env(RT_MAX_LAYER) {met3}
+set ::env(FP_PDN_LOWER_LAYER) {met2}
+set ::env(FP_PDN_UPPER_LAYER) {met3}
+
+set ::env(FP_IO_HLAYER) {met2}
+set ::env(FP_IO_VLAYER) {met1}
+
+#Lef 
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+
+## Placement
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) 2
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) "500"
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) "2.0"
+
+set ::env(ECO_ENABLE) {0}
+#set ::env(CURRENT_STEP) "synthesis"
+#set ::env(LAST_STEP) "parasitics_sta"
+
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "1"
+set ::env(QUIT_ON_LVS_ERROR) "1"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/bus_rep_north/interactive.tcl b/openlane/bus_rep_north/interactive.tcl
new file mode 100755
index 0000000..5b5c6c8
--- /dev/null
+++ b/openlane/bus_rep_north/interactive.tcl
@@ -0,0 +1,337 @@
+#!/usr/bin/env tclsh
+# Copyright 2020-2022 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+package require openlane; # provides the utils as well
+proc run_placement_step {args} {
+    if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
+        set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
+    }
+
+    run_placement
+}
+
+proc run_cts_step {args} {
+    if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
+        set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
+    }
+
+    run_cts
+    run_resizer_timing
+    if { $::env(RSZ_USE_OLD_REMOVER) == 1} {
+        remove_buffers_from_nets
+    }
+}
+
+proc run_routing_step {args} {
+    if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
+        set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
+    }
+    if { $::env(ECO_ENABLE) == 0 } {
+        run_routing
+    }
+}
+
+proc run_parasitics_sta_step {args} {
+    if { ! [ info exists ::env(PARSITICS_CURRENT_DEF) ] } {
+        set ::env(PARSITICS_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(PARSITICS_CURRENT_DEF)
+    }
+
+    if { $::env(RUN_SPEF_EXTRACTION) && ($::env(ECO_ENABLE) == 0)} {
+        run_parasitics_sta
+    }
+}
+
+proc run_diode_insertion_2_5_step {args} {
+    if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
+        set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
+    }
+    if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
+        run_antenna_check
+        heal_antenna_violators; # modifies the routed DEF
+    }
+
+}
+
+proc run_irdrop_report_step {args} {
+    if { $::env(RUN_IRDROP_REPORT) } {
+        run_irdrop_report
+    }
+}
+
+proc run_lvs_step {{ lvs_enabled 1 }} {
+    if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
+        set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
+    }
+
+    if { $lvs_enabled && $::env(RUN_LVS) } {
+        run_magic_spice_export;
+        run_lvs; # requires run_magic_spice_export
+    }
+
+}
+
+proc run_drc_step {{ drc_enabled 1 }} {
+    if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
+        set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
+    }
+    if { $drc_enabled } {
+        if { $::env(RUN_MAGIC_DRC) } {
+            run_magic_drc
+        }
+        if {$::env(RUN_KLAYOUT_DRC)} {
+            run_klayout_drc
+        }
+    }
+}
+
+proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
+    if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
+        set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
+    }
+    if { $antenna_check_enabled } {
+        run_antenna_check
+    }
+}
+
+proc run_erc_step {args} {
+    if { $::env(RUN_CVC) } {
+        run_erc
+    }
+}
+
+proc run_eco_step {args} {
+    if { $::env(ECO_ENABLE) == 1 } {
+        run_eco_flow
+    }
+}
+
+proc run_magic_step {args} {
+    if {$::env(RUN_MAGIC)} {
+        run_magic
+    }
+}
+
+proc run_klayout_step {args} {
+    if {$::env(RUN_KLAYOUT)} {
+        run_klayout
+    }
+    if {$::env(RUN_KLAYOUT_XOR)} {
+        run_klayout_gds_xor
+    }
+}
+
+proc run_post_run_hooks {} {
+    if { [file exists $::env(DESIGN_DIR)/hooks/post_run.py]} {
+        puts_info "Running post run hook"
+        set result [exec $::env(OPENROAD_BIN) -exit -no_init -python $::env(DESIGN_DIR)/hooks/post_run.py]
+        puts_info "$result"
+    } else {
+        puts_info "hooks/post_run.py not found, skipping"
+    }
+}
+
+proc run_floorplan {args} {
+    # |----------------------------------------------------|
+    # |----------------   2. FLOORPLAN   ------------------|
+    # |----------------------------------------------------|
+    #
+    # intial fp
+    init_floorplan
+
+    # check for deprecated io variables
+    if { [info exists ::env(FP_IO_HMETAL)]} {
+        set ::env(FP_IO_HLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_HMETAL) - 1}]]
+        puts_warn "You're using FP_IO_HMETAL in your configuration, which is a deprecated variable that will be removed in the future."
+        puts_warn "We recommend you update your configuration as follows:"
+        puts_warn "\tset ::env(FP_IO_HLAYER) {$::env(FP_IO_HLAYER)}"
+    }
+
+    if { [info exists ::env(FP_IO_VMETAL)]} {
+        set ::env(FP_IO_VLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_VMETAL) - 1}]]
+        puts_warn "You're using FP_IO_VMETAL in your configuration, which is a deprecated variable that will be removed in the future."
+        puts_warn "We recommend you update your configuration as follows:"
+        puts_warn "\tset ::env(FP_IO_VLAYER) {$::env(FP_IO_VLAYER)}"
+    }
+
+
+    # place io
+    if { [info exists ::env(FP_PIN_ORDER_CFG)] } {
+        place_io_ol
+    } else {
+        if { [info exists ::env(FP_CONTEXT_DEF)] && [info exists ::env(FP_CONTEXT_LEF)] } {
+            place_io
+            global_placement_or
+            place_contextualized_io \
+                -lef $::env(FP_CONTEXT_LEF) \
+                -def $::env(FP_CONTEXT_DEF)
+        } else {
+            place_io
+        }
+    }
+
+    apply_def_template
+
+    #if { [info exist ::env(EXTRA_LEFS)] } {
+        if { [info exist ::env(MACRO_PLACEMENT_CFG)] } {
+            file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(placement_tmpfiles)/macro_placement.cfg
+            manual_macro_placement -f
+        } else {
+        #    global_placement_or
+        #    basic_macro_placement
+        }
+    #}
+
+    if { $::env(RUN_TAP_DECAP_INSERTION) } {
+        tap_decap_or
+    }
+
+    scrot_klayout -layout $::env(CURRENT_DEF) -log $::env(floorplan_logs)/screenshot.log
+
+    run_power_grid_generation
+}
+
+
+
+proc run_flow {args} {
+    set options {
+        {-design optional}
+        {-from optional}
+        {-to optional}
+        {-save_path optional}
+        {-override_env optional}
+    }
+    set flags {-save -run_hooks -no_lvs -no_drc -no_antennacheck -gui}
+    parse_key_args "run_non_interactive_mode" args arg_values $options flags_map $flags -no_consume
+
+    prep {*}$args
+    # signal trap SIGINT save_state;
+
+    if { [info exists flags_map(-gui)] } {
+        or_gui
+        return
+    }
+    if { [info exists arg_values(-override_env)] } {
+        load_overrides $arg_values(-override_env)
+    }
+
+    set LVS_ENABLED 1
+    set DRC_ENABLED 1
+
+    set ANTENNACHECK_ENABLED [expr ![info exists flags_map(-no_antennacheck)] ]
+
+    set steps [dict create \
+        "synthesis" "run_synthesis" \
+        "floorplan" "run_floorplan" \
+        "placement" "run_placement_step" \
+        "cts" "run_cts_step" \
+        "routing" "run_routing_step" \
+        "parasitics_sta" "run_parasitics_sta_step" \
+        "eco" "run_eco_step" \
+        "diode_insertion" "run_diode_insertion_2_5_step" \
+        "irdrop" "run_irdrop_report_step" \
+        "gds_magic" "run_magic_step" \
+        "gds_klayout" "run_klayout_step" \
+        "lvs" "run_lvs_step $LVS_ENABLED " \
+        "drc" "run_drc_step $DRC_ENABLED " \
+        "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED " \
+        "cvc" "run_lef_cvc"
+    ]
+
+    if { [info exists arg_values(-from) ]} {
+        puts_info "Starting flow at $arg_values(-from)..."
+        set ::env(CURRENT_STEP) $arg_values(-from)
+    } elseif {  [info exists ::env(CURRENT_STEP) ] } {
+        puts_info "Resuming flow from $::env(CURRENT_STEP)..."
+    } else {
+        set ::env(CURRENT_STEP) "synthesis"
+    }
+
+    set_if_unset arg_values(-from) $::env(CURRENT_STEP)
+    set_if_unset arg_values(-to) "cvc"
+
+    set exe 0;
+    dict for {step_name step_exe} $steps {
+        if { [ string equal $arg_values(-from) $step_name ] } {
+            set exe 1;
+        }
+
+        if { $exe } {
+            # For when it fails
+            set ::env(CURRENT_STEP) $step_name
+            [lindex $step_exe 0] [lindex $step_exe 1] ;
+        }
+
+        if { [ string equal $arg_values(-to) $step_name ] } {
+            set exe 0:
+            break;
+        }
+
+    }
+
+    # for when it resumes
+    set steps_as_list [dict keys $steps]
+    set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
+    set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
+
+    # Saves to <RUN_DIR>/results/final
+    save_final_views
+
+    # Saves to design directory or custom
+    if {  [info exists flags_map(-save) ] } {
+        if { ! [info exists arg_values(-save_path)] } {
+            set arg_values(-save_path) $::env(DESIGN_DIR)
+        }
+        save_final_views\
+            -save_path $arg_values(-save_path)\
+            -tag $::env(RUN_TAG)
+    }
+    calc_total_runtime
+    save_state
+    generate_final_summary_report
+
+    check_timing_violations
+
+    if { [info exists arg_values(-save_path)]\
+        && $arg_values(-save_path) != "" } {
+        set ::env(HOOK_OUTPUT_PATH) "[file normalize $arg_values(-save_path)]"
+    } else {
+        set ::env(HOOK_OUTPUT_PATH) $::env(RESULTS_DIR)/final
+    }
+
+    if {[info exists flags_map(-run_hooks)]} {
+        run_post_run_hooks
+    }
+
+    puts_success "Flow complete."
+
+    show_warnings "Note that the following warnings have been generated:"
+}
+
+run_flow {*}$argv
diff --git a/openlane/bus_rep_north/macro.cfg b/openlane/bus_rep_north/macro.cfg
new file mode 100644
index 0000000..f743181
--- /dev/null
+++ b/openlane/bus_rep_north/macro.cfg
@@ -0,0 +1,27 @@
+u_rp\[0\].u_buf			7.82	10.88	FN
+u_rp\[1\].u_buf			97.98	10.88	FN
+u_rp\[2\].u_buf			188.14	10.88	FN
+u_rp\[3\].u_buf			278.3	10.88	FN
+u_rp\[4\].u_buf			368.46	10.88	FN
+u_rp\[5\].u_buf			458.62	10.88	FN
+u_rp\[6\].u_buf			548.78	10.88	FN
+u_rp\[7\].u_buf			638.94	10.88	FN
+u_rp\[8\].u_buf			729.1	10.88	FN
+u_rp\[9\].u_buf			819.26	10.88	FN
+u_rp\[10\].u_buf		909.42	10.88	FN
+u_rp\[11\].u_buf		999.58	10.88	FN
+u_rp\[12\].u_buf		1089.74	10.88	FN
+u_rp\[13\].u_buf		1179.9	10.88	FN
+u_rp\[14\].u_buf		1270.06	10.88	FN
+u_rp\[15\].u_buf		1360.22	10.88	FN
+u_rp\[16\].u_buf		1450.38	10.88	FN
+u_rp\[17\].u_buf		1540.54	10.88	FN
+u_rp\[18\].u_buf		1630.7	10.88	FN
+u_rp\[19\].u_buf		1720.86	10.88	FN
+u_rp\[20\].u_buf		1811.02	10.88	FN
+u_rp\[21\].u_buf		1901.18	10.88	FN
+u_rp\[22\].u_buf		1991.34	10.88	FN
+u_rp\[23\].u_buf		2081.5	10.88	FN
+u_rp\[24\].u_buf		2171.66	10.88	FN
+u_rp\[25\].u_buf		2261.82	10.88	FN
+u_rp\[26\].u_buf		2351.98	10.88	FN
diff --git a/openlane/bus_rep_north/pdn.tcl b/openlane/bus_rep_north/pdn.tcl
new file mode 100644
index 0000000..1fe689b
--- /dev/null
+++ b/openlane/bus_rep_north/pdn.tcl
@@ -0,0 +1,49 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# Power nets
+set ::power_nets $::env(VDD_PIN)
+set ::ground_nets $::env(GND_PIN)
+
+set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
+
+pdngen::specify_grid stdcell {
+    name grid
+    rails {
+	    met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
+    }
+    straps {
+	    met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
+	    met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
+    }
+    connect {{met1 met4} {met4 met5}}
+}
+
+pdngen::specify_grid macro {
+    power_pins "VPWR"
+    ground_pins "VGND"
+    blockages "li1 met1 met2 met3 met4"
+    straps { 
+    } 
+    connect {{met4_PIN_ver met5}}
+}
+
+set ::halo 5
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;
diff --git a/openlane/bus_rep_north/pin_order.cfg b/openlane/bus_rep_north/pin_order.cfg
new file mode 100644
index 0000000..d6472e3
--- /dev/null
+++ b/openlane/bus_rep_north/pin_order.cfg
@@ -0,0 +1,61 @@
+#BUS_SORT
+
+#MANUAL_PLACE
+
+#N
+ch_out\[0\]    0 0 250
+ch_out\[1\]    
+ch_in\[2\]
+ch_out\[3\]    
+ch_out\[4\]    
+ch_in\[5\]
+ch_out\[6\]    
+ch_out\[7\]    
+ch_in\[8\]
+ch_out\[9\]    
+ch_out\[10\]    
+ch_in\[11\]
+ch_out\[12\]    
+ch_out\[13\]    
+ch_in\[14\]
+ch_out\[15\]    
+ch_out\[16\]    
+ch_in\[17\]
+ch_out\[18\]    
+ch_out\[19\]    
+ch_in\[20\]
+ch_out\[21\]    
+ch_out\[22\]    
+ch_in\[23\]
+ch_out\[24\]    
+ch_out\[25\]    
+ch_in\[26\]
+
+#S
+ch_in\[0\]    2000 0 64
+ch_in\[1\]
+ch_out\[2\]
+ch_in\[3\]    
+ch_in\[4\]
+ch_out\[5\]
+ch_in\[6\]    
+ch_in\[7\]
+ch_out\[8\]
+ch_in\[9\]    
+ch_in\[10\]
+ch_out\[11\]
+ch_in\[12\]    
+ch_in\[13\]
+ch_out\[14\]
+ch_in\[15\]    
+ch_in\[16\]
+ch_out\[17\]
+ch_in\[18\]    
+ch_in\[19\]
+ch_out\[20\]
+ch_in\[21\]    
+ch_in\[22\]
+ch_out\[23\]
+ch_in\[24\]    
+ch_in\[25\]
+ch_out\[26\]
diff --git a/openlane/bus_rep_south/config.tcl b/openlane/bus_rep_south/config.tcl
new file mode 100755
index 0000000..eec763c
--- /dev/null
+++ b/openlane/bus_rep_south/config.tcl
@@ -0,0 +1,134 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+# Global
+# ------
+
+set script_dir [file dirname [file normalize [info script]]]
+# Name
+set ::env(DESIGN_NAME) bus_rep_south
+
+
+set ::env(DESIGN_IS_CORE) "1"
+set ::env(FP_PDN_CORE_RING) {1}
+
+# Timing configuration
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) ""
+set ::env(CLOCK_NET) ""
+
+set ::env(SYNTH_MAX_FANOUT) 4
+set ::env(SYNTH_BUFFERING) {0}
+
+
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+
+# Sources
+# -------
+
+# Local sources + no2usb sources
+set ::env(VERILOG_FILES) "\
+        $::env(DESIGN_DIR)/../../verilog/rtl/bus_rep/bus_rep_south.sv \
+	"
+
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
+
+set ::env(SYNTH_PARAMETERS) "BUS_REP_WD=253 "
+
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+#set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+#set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+
+set ::env(LEC_ENABLE) 0
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+
+# Floorplanning
+# -------------
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 2650 50"
+
+#set ::env(GRT_OBS) "met4  0 0 300 1725"
+
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
+
+#set ::env(PDN_CFG) $::env(DESIGN_DIR)/pdn.tcl
+
+
+
+set ::env(PL_TIME_DRIVEN) 1
+set ::env(PL_TARGET_DENSITY) "0.20"
+set ::env(CELL_PAD) "8"
+set ::env(GRT_ADJUSTMENT) 0.2
+
+# helps in anteena fix
+set ::env(USE_ARC_ANTENNA_CHECK) "0"
+
+
+#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+## CTS
+set ::env(CLOCK_TREE_SYNTH) {0}
+
+## Placement
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) "0"
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) "0"
+
+## Routing
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0"
+
+#LVS Issue - DEF Base looks to having issue
+set ::env(MAGIC_EXT_USE_GDS) {1}
+
+#set ::env(GLB_RT_MAXLAYER) 3
+set ::env(RT_MAX_LAYER) {met3}
+set ::env(FP_PDN_LOWER_LAYER) {met2}
+set ::env(FP_PDN_UPPER_LAYER) {met3}
+
+set ::env(FP_IO_HLAYER) {met2}
+set ::env(FP_IO_VLAYER) {met1}
+
+#Lef 
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+
+## Placement
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) 2
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) "600"
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) "2.0"
+
+set ::env(ECO_ENABLE) {0}
+#set ::env(CURRENT_STEP) "synthesis"
+#set ::env(LAST_STEP) "parasitics_sta"
+
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "1"
+set ::env(QUIT_ON_LVS_ERROR) "1"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/bus_rep_south/interactive.tcl b/openlane/bus_rep_south/interactive.tcl
new file mode 100755
index 0000000..5b5c6c8
--- /dev/null
+++ b/openlane/bus_rep_south/interactive.tcl
@@ -0,0 +1,337 @@
+#!/usr/bin/env tclsh
+# Copyright 2020-2022 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+package require openlane; # provides the utils as well
+proc run_placement_step {args} {
+    if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
+        set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
+    }
+
+    run_placement
+}
+
+proc run_cts_step {args} {
+    if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
+        set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
+    }
+
+    run_cts
+    run_resizer_timing
+    if { $::env(RSZ_USE_OLD_REMOVER) == 1} {
+        remove_buffers_from_nets
+    }
+}
+
+proc run_routing_step {args} {
+    if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
+        set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
+    }
+    if { $::env(ECO_ENABLE) == 0 } {
+        run_routing
+    }
+}
+
+proc run_parasitics_sta_step {args} {
+    if { ! [ info exists ::env(PARSITICS_CURRENT_DEF) ] } {
+        set ::env(PARSITICS_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(PARSITICS_CURRENT_DEF)
+    }
+
+    if { $::env(RUN_SPEF_EXTRACTION) && ($::env(ECO_ENABLE) == 0)} {
+        run_parasitics_sta
+    }
+}
+
+proc run_diode_insertion_2_5_step {args} {
+    if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
+        set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
+    }
+    if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
+        run_antenna_check
+        heal_antenna_violators; # modifies the routed DEF
+    }
+
+}
+
+proc run_irdrop_report_step {args} {
+    if { $::env(RUN_IRDROP_REPORT) } {
+        run_irdrop_report
+    }
+}
+
+proc run_lvs_step {{ lvs_enabled 1 }} {
+    if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
+        set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
+    }
+
+    if { $lvs_enabled && $::env(RUN_LVS) } {
+        run_magic_spice_export;
+        run_lvs; # requires run_magic_spice_export
+    }
+
+}
+
+proc run_drc_step {{ drc_enabled 1 }} {
+    if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
+        set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
+    }
+    if { $drc_enabled } {
+        if { $::env(RUN_MAGIC_DRC) } {
+            run_magic_drc
+        }
+        if {$::env(RUN_KLAYOUT_DRC)} {
+            run_klayout_drc
+        }
+    }
+}
+
+proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
+    if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
+        set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
+    }
+    if { $antenna_check_enabled } {
+        run_antenna_check
+    }
+}
+
+proc run_erc_step {args} {
+    if { $::env(RUN_CVC) } {
+        run_erc
+    }
+}
+
+proc run_eco_step {args} {
+    if { $::env(ECO_ENABLE) == 1 } {
+        run_eco_flow
+    }
+}
+
+proc run_magic_step {args} {
+    if {$::env(RUN_MAGIC)} {
+        run_magic
+    }
+}
+
+proc run_klayout_step {args} {
+    if {$::env(RUN_KLAYOUT)} {
+        run_klayout
+    }
+    if {$::env(RUN_KLAYOUT_XOR)} {
+        run_klayout_gds_xor
+    }
+}
+
+proc run_post_run_hooks {} {
+    if { [file exists $::env(DESIGN_DIR)/hooks/post_run.py]} {
+        puts_info "Running post run hook"
+        set result [exec $::env(OPENROAD_BIN) -exit -no_init -python $::env(DESIGN_DIR)/hooks/post_run.py]
+        puts_info "$result"
+    } else {
+        puts_info "hooks/post_run.py not found, skipping"
+    }
+}
+
+proc run_floorplan {args} {
+    # |----------------------------------------------------|
+    # |----------------   2. FLOORPLAN   ------------------|
+    # |----------------------------------------------------|
+    #
+    # intial fp
+    init_floorplan
+
+    # check for deprecated io variables
+    if { [info exists ::env(FP_IO_HMETAL)]} {
+        set ::env(FP_IO_HLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_HMETAL) - 1}]]
+        puts_warn "You're using FP_IO_HMETAL in your configuration, which is a deprecated variable that will be removed in the future."
+        puts_warn "We recommend you update your configuration as follows:"
+        puts_warn "\tset ::env(FP_IO_HLAYER) {$::env(FP_IO_HLAYER)}"
+    }
+
+    if { [info exists ::env(FP_IO_VMETAL)]} {
+        set ::env(FP_IO_VLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_VMETAL) - 1}]]
+        puts_warn "You're using FP_IO_VMETAL in your configuration, which is a deprecated variable that will be removed in the future."
+        puts_warn "We recommend you update your configuration as follows:"
+        puts_warn "\tset ::env(FP_IO_VLAYER) {$::env(FP_IO_VLAYER)}"
+    }
+
+
+    # place io
+    if { [info exists ::env(FP_PIN_ORDER_CFG)] } {
+        place_io_ol
+    } else {
+        if { [info exists ::env(FP_CONTEXT_DEF)] && [info exists ::env(FP_CONTEXT_LEF)] } {
+            place_io
+            global_placement_or
+            place_contextualized_io \
+                -lef $::env(FP_CONTEXT_LEF) \
+                -def $::env(FP_CONTEXT_DEF)
+        } else {
+            place_io
+        }
+    }
+
+    apply_def_template
+
+    #if { [info exist ::env(EXTRA_LEFS)] } {
+        if { [info exist ::env(MACRO_PLACEMENT_CFG)] } {
+            file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(placement_tmpfiles)/macro_placement.cfg
+            manual_macro_placement -f
+        } else {
+        #    global_placement_or
+        #    basic_macro_placement
+        }
+    #}
+
+    if { $::env(RUN_TAP_DECAP_INSERTION) } {
+        tap_decap_or
+    }
+
+    scrot_klayout -layout $::env(CURRENT_DEF) -log $::env(floorplan_logs)/screenshot.log
+
+    run_power_grid_generation
+}
+
+
+
+proc run_flow {args} {
+    set options {
+        {-design optional}
+        {-from optional}
+        {-to optional}
+        {-save_path optional}
+        {-override_env optional}
+    }
+    set flags {-save -run_hooks -no_lvs -no_drc -no_antennacheck -gui}
+    parse_key_args "run_non_interactive_mode" args arg_values $options flags_map $flags -no_consume
+
+    prep {*}$args
+    # signal trap SIGINT save_state;
+
+    if { [info exists flags_map(-gui)] } {
+        or_gui
+        return
+    }
+    if { [info exists arg_values(-override_env)] } {
+        load_overrides $arg_values(-override_env)
+    }
+
+    set LVS_ENABLED 1
+    set DRC_ENABLED 1
+
+    set ANTENNACHECK_ENABLED [expr ![info exists flags_map(-no_antennacheck)] ]
+
+    set steps [dict create \
+        "synthesis" "run_synthesis" \
+        "floorplan" "run_floorplan" \
+        "placement" "run_placement_step" \
+        "cts" "run_cts_step" \
+        "routing" "run_routing_step" \
+        "parasitics_sta" "run_parasitics_sta_step" \
+        "eco" "run_eco_step" \
+        "diode_insertion" "run_diode_insertion_2_5_step" \
+        "irdrop" "run_irdrop_report_step" \
+        "gds_magic" "run_magic_step" \
+        "gds_klayout" "run_klayout_step" \
+        "lvs" "run_lvs_step $LVS_ENABLED " \
+        "drc" "run_drc_step $DRC_ENABLED " \
+        "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED " \
+        "cvc" "run_lef_cvc"
+    ]
+
+    if { [info exists arg_values(-from) ]} {
+        puts_info "Starting flow at $arg_values(-from)..."
+        set ::env(CURRENT_STEP) $arg_values(-from)
+    } elseif {  [info exists ::env(CURRENT_STEP) ] } {
+        puts_info "Resuming flow from $::env(CURRENT_STEP)..."
+    } else {
+        set ::env(CURRENT_STEP) "synthesis"
+    }
+
+    set_if_unset arg_values(-from) $::env(CURRENT_STEP)
+    set_if_unset arg_values(-to) "cvc"
+
+    set exe 0;
+    dict for {step_name step_exe} $steps {
+        if { [ string equal $arg_values(-from) $step_name ] } {
+            set exe 1;
+        }
+
+        if { $exe } {
+            # For when it fails
+            set ::env(CURRENT_STEP) $step_name
+            [lindex $step_exe 0] [lindex $step_exe 1] ;
+        }
+
+        if { [ string equal $arg_values(-to) $step_name ] } {
+            set exe 0:
+            break;
+        }
+
+    }
+
+    # for when it resumes
+    set steps_as_list [dict keys $steps]
+    set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
+    set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
+
+    # Saves to <RUN_DIR>/results/final
+    save_final_views
+
+    # Saves to design directory or custom
+    if {  [info exists flags_map(-save) ] } {
+        if { ! [info exists arg_values(-save_path)] } {
+            set arg_values(-save_path) $::env(DESIGN_DIR)
+        }
+        save_final_views\
+            -save_path $arg_values(-save_path)\
+            -tag $::env(RUN_TAG)
+    }
+    calc_total_runtime
+    save_state
+    generate_final_summary_report
+
+    check_timing_violations
+
+    if { [info exists arg_values(-save_path)]\
+        && $arg_values(-save_path) != "" } {
+        set ::env(HOOK_OUTPUT_PATH) "[file normalize $arg_values(-save_path)]"
+    } else {
+        set ::env(HOOK_OUTPUT_PATH) $::env(RESULTS_DIR)/final
+    }
+
+    if {[info exists flags_map(-run_hooks)]} {
+        run_post_run_hooks
+    }
+
+    puts_success "Flow complete."
+
+    show_warnings "Note that the following warnings have been generated:"
+}
+
+run_flow {*}$argv
diff --git a/openlane/bus_rep_south/macro.cfg b/openlane/bus_rep_south/macro.cfg
new file mode 100644
index 0000000..535d4ee
--- /dev/null
+++ b/openlane/bus_rep_south/macro.cfg
@@ -0,0 +1,254 @@
+u_rp\[0\].u_buf			7.82	10.88	FN
+u_rp\[1\].u_buf			7.82	16.32	FN
+u_rp\[2\].u_buf			20.7	10.88	FN
+u_rp\[3\].u_buf			20.7	16.32	FN
+u_rp\[4\].u_buf			33.58	10.88	FN
+u_rp\[5\].u_buf			33.58	16.32	FN
+u_rp\[6\].u_buf			46.46	10.88	FN
+u_rp\[7\].u_buf			46.46	16.32	FN
+u_rp\[8\].u_buf			59.34	10.88	FN
+u_rp\[9\].u_buf			59.34	16.32	FN
+u_rp\[10\].u_buf			72.22	10.88	FN
+u_rp\[11\].u_buf			72.22	16.32	FN
+u_rp\[12\].u_buf			85.1	10.88	FN
+u_rp\[13\].u_buf			85.1	16.32	FN
+u_rp\[14\].u_buf			97.98	10.88	FN
+u_rp\[15\].u_buf			97.98	16.32	FN
+u_rp\[16\].u_buf			110.86	10.88	FN
+u_rp\[17\].u_buf			110.86	16.32	FN
+u_rp\[18\].u_buf			123.74	10.88	FN
+u_rp\[19\].u_buf			123.74	16.32	FN
+u_rp\[20\].u_buf			136.62	10.88	FN
+u_rp\[21\].u_buf			136.62	16.32	FN
+u_rp\[22\].u_buf			149.5	10.88	FN
+u_rp\[23\].u_buf			149.5	16.32	FN
+u_rp\[24\].u_buf			162.38	10.88	FN
+u_rp\[25\].u_buf			162.38	16.32	FN
+u_rp\[26\].u_buf			175.26	10.88	FN
+u_rp\[27\].u_buf			175.26	16.32	FN
+u_rp\[28\].u_buf			188.14	10.88	FN
+u_rp\[29\].u_buf			188.14	16.32	FN
+u_rp\[30\].u_buf			201.02	10.88	FN
+u_rp\[31\].u_buf			201.02	16.32	FN
+u_rp\[32\].u_buf			213.9	10.88	FN
+u_rp\[33\].u_buf			213.9	16.32	FN
+u_rp\[34\].u_buf			226.78	10.88	FN
+u_rp\[35\].u_buf			226.78	16.32	FN
+u_rp\[36\].u_buf			239.66	10.88	FN
+u_rp\[37\].u_buf			239.66	16.32	FN
+u_rp\[38\].u_buf			252.54	10.88	FN
+u_rp\[39\].u_buf			252.54	16.32	FN
+u_rp\[40\].u_buf			265.42	10.88	FN
+u_rp\[41\].u_buf			265.42	16.32	FN
+u_rp\[42\].u_buf			278.3	10.88	FN
+u_rp\[43\].u_buf			278.3	16.32	FN
+u_rp\[44\].u_buf			291.18	10.88	FN
+u_rp\[45\].u_buf			291.18	16.32	FN
+u_rp\[46\].u_buf			304.06	10.88	FN
+u_rp\[47\].u_buf			304.06	16.32	FN
+u_rp\[48\].u_buf			316.94	10.88	FN
+u_rp\[49\].u_buf			316.94	16.32	FN
+u_rp\[50\].u_buf			329.82	10.88	FN
+u_rp\[51\].u_buf			329.82	16.32	FN
+u_rp\[52\].u_buf			342.7	10.88	FN
+u_rp\[53\].u_buf			342.7	16.32	FN
+u_rp\[54\].u_buf			355.58	10.88	FN
+u_rp\[55\].u_buf			355.58	16.32	FN
+u_rp\[56\].u_buf			368.46	10.88	FN
+u_rp\[57\].u_buf			368.46	16.32	FN
+u_rp\[58\].u_buf			381.34	10.88	FN
+u_rp\[59\].u_buf			381.34	16.32	FN
+u_rp\[60\].u_buf			394.22	10.88	FN
+u_rp\[61\].u_buf			394.22	16.32	FN
+u_rp\[62\].u_buf			407.1	10.88	FN
+u_rp\[63\].u_buf			407.1	16.32	FN
+u_rp\[64\].u_buf			419.98	10.88	FN
+u_rp\[65\].u_buf			419.98	16.32	FN
+u_rp\[66\].u_buf			432.86	10.88	FN
+u_rp\[67\].u_buf			432.86	16.32	FN
+u_rp\[68\].u_buf			445.74	10.88	FN
+u_rp\[69\].u_buf			445.74	16.32	FN
+u_rp\[70\].u_buf			458.62	10.88	FN
+u_rp\[71\].u_buf			458.62	16.32	FN
+u_rp\[72\].u_buf			471.5	10.88	FN
+u_rp\[73\].u_buf			471.5	16.32	FN
+u_rp\[74\].u_buf			484.38	10.88	FN
+u_rp\[75\].u_buf			484.38	16.32	FN
+u_rp\[76\].u_buf			497.26	10.88	FN
+u_rp\[77\].u_buf			497.26	16.32	FN
+u_rp\[78\].u_buf			510.14	10.88	FN
+u_rp\[79\].u_buf			510.14	16.32	FN
+u_rp\[80\].u_buf			523.02	10.88	FN
+u_rp\[81\].u_buf			523.02	16.32	FN
+u_rp\[82\].u_buf			535.9	10.88	FN
+u_rp\[83\].u_buf			535.9	16.32	FN
+u_rp\[84\].u_buf			548.78	10.88	FN
+u_rp\[85\].u_buf			548.78	16.32	FN
+u_rp\[86\].u_buf			561.66	10.88	FN
+u_rp\[87\].u_buf			561.66	16.32	FN
+u_rp\[88\].u_buf			574.54	10.88	FN
+u_rp\[89\].u_buf			574.54	16.32	FN
+u_rp\[90\].u_buf			587.42	10.88	FN
+u_rp\[91\].u_buf			587.42	16.32	FN
+u_rp\[92\].u_buf			600.3	10.88	FN
+u_rp\[93\].u_buf			600.3	16.32	FN
+u_rp\[94\].u_buf			613.18	10.88	FN
+u_rp\[95\].u_buf			613.18	16.32	FN
+u_rp\[96\].u_buf			626.06	10.88	FN
+u_rp\[97\].u_buf			626.06	16.32	FN
+u_rp\[98\].u_buf			638.94	10.88	FN
+u_rp\[99\].u_buf			638.94	16.32	FN
+u_rp\[100\].u_buf			651.82	10.88	FN
+u_rp\[101\].u_buf			651.82	16.32	FN
+u_rp\[102\].u_buf			664.7	10.88	FN
+u_rp\[103\].u_buf			664.7	16.32	FN
+u_rp\[104\].u_buf			677.58	10.88	FN
+u_rp\[105\].u_buf			677.58	16.32	FN
+u_rp\[106\].u_buf			690.46	10.88	FN
+u_rp\[107\].u_buf			703.34	10.88	FN
+u_rp\[108\].u_buf			716.22	10.88	FN
+u_rp\[109\].u_buf			729.1	10.88	FN
+u_rp\[110\].u_buf			741.98	10.88	FN
+u_rp\[111\].u_buf			754.86	10.88	FN
+u_rp\[112\].u_buf			767.74	10.88	FN
+u_rp\[113\].u_buf			780.62	10.88	FN
+u_rp\[114\].u_buf			793.5	10.88	FN
+u_rp\[115\].u_buf			806.38	10.88	FN
+u_rp\[116\].u_buf			819.26	10.88	FN
+u_rp\[117\].u_buf			832.14	10.88	FN
+u_rp\[118\].u_buf			845.02	10.88	FN
+u_rp\[119\].u_buf			857.9	10.88	FN
+u_rp\[120\].u_buf			870.78	10.88	FN
+u_rp\[121\].u_buf			883.66	10.88	FN
+u_rp\[122\].u_buf			896.54	10.88	FN
+u_rp\[123\].u_buf			909.42	10.88	FN
+u_rp\[124\].u_buf			922.3	10.88	FN
+u_rp\[125\].u_buf			935.18	10.88	FN
+u_rp\[126\].u_buf			948.06	10.88	FN
+u_rp\[127\].u_buf			960.94	10.88	FN
+u_rp\[128\].u_buf			973.82	10.88	FN
+u_rp\[129\].u_buf			986.7	10.88	FN
+u_rp\[130\].u_buf			999.58	10.88	FN
+u_rp\[131\].u_buf			1012.46	10.88	FN
+u_rp\[132\].u_buf			1025.34	10.88	FN
+u_rp\[133\].u_buf			1038.22	10.88	FN
+u_rp\[134\].u_buf			1051.1	10.88	FN
+u_rp\[135\].u_buf			1063.98	10.88	FN
+u_rp\[136\].u_buf			1076.86	10.88	FN
+u_rp\[137\].u_buf			1089.74	10.88	FN
+u_rp\[138\].u_buf			1102.62	10.88	FN
+u_rp\[139\].u_buf			1115.5	10.88	FN
+u_rp\[140\].u_buf			1128.38	10.88	FN
+u_rp\[141\].u_buf			1141.26	10.88	FN
+u_rp\[142\].u_buf			1154.14	10.88	FN
+u_rp\[143\].u_buf			1167.02	10.88	FN
+u_rp\[144\].u_buf			1179.9	10.88	FN
+u_rp\[145\].u_buf			1192.78	10.88	FN
+u_rp\[146\].u_buf			1205.66	10.88	FN
+u_rp\[147\].u_buf			1218.54	10.88	FN
+u_rp\[148\].u_buf			1231.42	10.88	FN
+u_rp\[149\].u_buf			1244.3	10.88	FN
+u_rp\[150\].u_buf			1257.18	10.88	FN
+u_rp\[151\].u_buf			1270.06	10.88	FN
+u_rp\[152\].u_buf			1282.94	10.88	FN
+u_rp\[153\].u_buf			1295.82	10.88	FN
+u_rp\[154\].u_buf			1308.7	10.88	FN
+u_rp\[155\].u_buf			1321.58	10.88	FN
+u_rp\[156\].u_buf			1334.46	10.88	FN
+u_rp\[157\].u_buf			1347.34	10.88	FN
+u_rp\[158\].u_buf			1360.22	10.88	FN
+u_rp\[159\].u_buf			1373.1	10.88	FN
+u_rp\[160\].u_buf			1385.98	10.88	FN
+u_rp\[161\].u_buf			1398.86	10.88	FN
+u_rp\[162\].u_buf			1411.74	10.88	FN
+u_rp\[163\].u_buf			1424.62	10.88	FN
+u_rp\[164\].u_buf			1437.5	10.88	FN
+u_rp\[165\].u_buf			1450.38	10.88	FN
+u_rp\[166\].u_buf			1463.26	10.88	FN
+u_rp\[167\].u_buf			1476.14	10.88	FN
+u_rp\[168\].u_buf			1489.02	10.88	FN
+u_rp\[169\].u_buf			1501.9	10.88	FN
+u_rp\[170\].u_buf			1514.78	10.88	FN
+u_rp\[171\].u_buf			1527.66	10.88	FN
+u_rp\[172\].u_buf			1540.54	10.88	FN
+u_rp\[173\].u_buf			1553.42	10.88	FN
+u_rp\[174\].u_buf			1566.3	10.88	FN
+u_rp\[175\].u_buf			1579.18	10.88	FN
+u_rp\[176\].u_buf			1592.06	10.88	FN
+u_rp\[177\].u_buf			1604.94	10.88	FN
+u_rp\[178\].u_buf			1617.82	10.88	FN
+u_rp\[179\].u_buf			1630.70	10.88	FN
+u_rp\[180\].u_buf			1643.58	10.88	FN
+u_rp\[181\].u_buf			1656.46	10.88	FN
+u_rp\[182\].u_buf			1669.34	10.88	FN
+u_rp\[183\].u_buf			1682.22	10.88	FN
+u_rp\[184\].u_buf			1695.10	10.88	FN
+u_rp\[185\].u_buf			1707.98	10.88	FN
+u_rp\[186\].u_buf			1720.86	10.88	FN
+u_rp\[187\].u_buf			1733.74	10.88	FN
+u_rp\[188\].u_buf			1746.62	10.88	FN
+u_rp\[189\].u_buf			1759.50	10.88	FN
+u_rp\[190\].u_buf			1772.38	10.88	FN
+u_rp\[191\].u_buf			1785.26	10.88	FN
+u_rp\[192\].u_buf			1798.14	10.88	FN
+u_rp\[193\].u_buf			1811.02	10.88	FN
+u_rp\[194\].u_buf			1823.90	10.88	FN
+u_rp\[195\].u_buf			1836.78	10.88	FN
+u_rp\[196\].u_buf			1849.66	10.88	FN
+u_rp\[197\].u_buf			1862.54	10.88	FN
+u_rp\[198\].u_buf			1875.42	10.88	FN
+u_rp\[199\].u_buf			1888.30	10.88	FN
+u_rp\[200\].u_buf			1901.18	10.88	FN
+u_rp\[201\].u_buf			1914.06	10.88	FN
+u_rp\[202\].u_buf			1926.94	10.88	FN
+u_rp\[203\].u_buf			1939.82	10.88	FN
+u_rp\[204\].u_buf			1952.70	10.88	FN
+u_rp\[205\].u_buf			1965.58	10.88	FN
+u_rp\[206\].u_buf			1978.46	10.88	FN
+u_rp\[207\].u_buf			1991.34	10.88	FN
+u_rp\[208\].u_buf			2004.22	10.88	FN
+u_rp\[209\].u_buf			2017.10	10.88	FN
+u_rp\[210\].u_buf			2029.98	10.88	FN
+u_rp\[211\].u_buf			2042.86	10.88	FN
+u_rp\[212\].u_buf			2055.74	10.88	FN
+u_rp\[213\].u_buf			2068.62	10.88	FN
+u_rp\[214\].u_buf			2081.50	10.88	FN
+u_rp\[215\].u_buf			2094.38	10.88	FN
+u_rp\[216\].u_buf			2107.26	10.88	FN
+u_rp\[217\].u_buf			2120.14	10.88	FN
+u_rp\[218\].u_buf			2133.02	10.88	FN
+u_rp\[219\].u_buf			2145.90	10.88	FN
+u_rp\[220\].u_buf			2158.78	10.88	FN
+u_rp\[221\].u_buf			2171.66	10.88	FN
+u_rp\[222\].u_buf			2184.54	10.88	FN
+u_rp\[223\].u_buf			2197.42	10.88	FN
+u_rp\[224\].u_buf			2210.30	10.88	FN
+u_rp\[225\].u_buf			2223.18	10.88	FN
+u_rp\[226\].u_buf			2236.06	10.88	FN
+u_rp\[227\].u_buf			2248.94	10.88	FN
+u_rp\[228\].u_buf			2261.82	10.88	FN
+u_rp\[229\].u_buf			2274.70	10.88	FN
+u_rp\[230\].u_buf			2287.58	10.88	FN
+u_rp\[231\].u_buf			2300.46	10.88	FN
+u_rp\[232\].u_buf			2313.34	10.88	FN
+u_rp\[233\].u_buf			2326.22	10.88	FN
+u_rp\[234\].u_buf			2339.10	10.88	FN
+u_rp\[235\].u_buf			2351.98	10.88	FN
+u_rp\[236\].u_buf			2364.86	10.88	FN
+u_rp\[237\].u_buf			2377.74	10.88	FN
+u_rp\[238\].u_buf			2390.62	10.88	FN
+u_rp\[239\].u_buf			2403.50	10.88	FN
+u_rp\[240\].u_buf			2416.38	10.88	FN
+u_rp\[241\].u_buf			2429.26	10.88	FN
+u_rp\[242\].u_buf			2442.14	10.88	FN
+u_rp\[243\].u_buf			2455.02	10.88	FN
+u_rp\[244\].u_buf			2467.90	10.88	FN
+u_rp\[245\].u_buf			2480.78	10.88	FN
+u_rp\[246\].u_buf			2493.66	10.88	FN
+u_rp\[247\].u_buf			2506.54	10.88	FN
+u_rp\[248\].u_buf			2519.42	10.88	FN
+u_rp\[249\].u_buf			2532.30	10.88	FN
+u_rp\[250\].u_buf			2545.18	10.88	FN
+u_rp\[251\].u_buf			2558.06	10.88	FN
+u_rp\[252\].u_buf			2570.94	10.88	FN
+
diff --git a/openlane/bus_rep_south/pdn.tcl b/openlane/bus_rep_south/pdn.tcl
new file mode 100644
index 0000000..1fe689b
--- /dev/null
+++ b/openlane/bus_rep_south/pdn.tcl
@@ -0,0 +1,49 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# Power nets
+set ::power_nets $::env(VDD_PIN)
+set ::ground_nets $::env(GND_PIN)
+
+set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
+
+pdngen::specify_grid stdcell {
+    name grid
+    rails {
+	    met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
+    }
+    straps {
+	    met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
+	    met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
+    }
+    connect {{met1 met4} {met4 met5}}
+}
+
+pdngen::specify_grid macro {
+    power_pins "VPWR"
+    ground_pins "VGND"
+    blockages "li1 met1 met2 met3 met4"
+    straps { 
+    } 
+    connect {{met4_PIN_ver met5}}
+}
+
+set ::halo 5
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;
diff --git a/openlane/bus_rep_south/pin_order.cfg b/openlane/bus_rep_south/pin_order.cfg
new file mode 100644
index 0000000..4546535
--- /dev/null
+++ b/openlane/bus_rep_south/pin_order.cfg
@@ -0,0 +1,528 @@
+#BUS_SORT
+
+#MANUAL_PLACE
+
+#N
+ch_out\[0\]    1000 0 8
+ch_out\[1\]
+ch_in\[2\]
+ch_out\[3\]
+ch_out\[4\]
+ch_out\[5\]
+ch_out\[6\]
+ch_out\[7\]
+ch_in\[8\]
+ch_out\[9\]
+ch_out\[10\]
+ch_out\[11\]
+ch_in\[12\]
+ch_out\[13\]
+ch_out\[14\]
+ch_out\[15\]
+ch_in\[16\]
+ch_out\[17\]
+ch_out\[18\]
+ch_out\[19\]
+ch_in\[20\]
+ch_out\[21\]
+ch_out\[22\]
+ch_out\[23\]
+ch_in\[24\]
+
+ch_out\[25\]
+ch_out\[26\]
+ch_in\[27\]
+ch_out\[28\]
+ch_out\[29\]
+ch_in\[30\]
+ch_out\[31\]
+ch_out\[32\]
+ch_in\[33\]
+ch_out\[34\]
+ch_out\[35\]
+ch_in\[36\]
+ch_out\[37\]
+ch_out\[38\]
+ch_in\[39\]
+ch_out\[40\]
+ch_out\[41\]
+ch_in\[42\]
+ch_out\[43\]
+ch_out\[44\]
+ch_in\[45\]
+ch_out\[46\]
+ch_out\[47\]
+ch_in\[48\]
+ch_out\[49\]
+ch_out\[50\]
+ch_in\[51\]
+ch_out\[52\]
+ch_out\[53\]
+ch_in\[54\]
+ch_out\[55\]
+ch_out\[56\]
+ch_in\[57\]
+ch_out\[58\]
+ch_out\[59\]
+ch_in\[60\]
+ch_out\[61\]
+ch_out\[62\]
+ch_in\[63\]
+ch_out\[64\]
+ch_out\[65\]
+ch_in\[66\]
+ch_out\[67\]
+ch_out\[68\]
+ch_in\[69\]
+ch_out\[70\]
+ch_out\[71\]
+ch_in\[72\]
+ch_out\[73\]
+ch_out\[74\]
+ch_in\[75\]
+ch_out\[76\]
+ch_out\[77\]
+ch_in\[78\]
+ch_out\[79\]
+ch_out\[80\]
+ch_in\[81\]
+ch_out\[82\]
+ch_out\[83\]
+ch_in\[84\]
+ch_out\[85\]
+ch_out\[86\]
+ch_in\[87\]
+ch_out\[88\]
+ch_out\[89\]
+ch_in\[90\]
+ch_out\[91\]
+ch_out\[92\]
+ch_in\[93\]
+ch_out\[94\]
+ch_out\[95\]
+ch_in\[96\]
+ch_out\[97\]
+ch_out\[98\]
+ch_in\[99\]
+ch_out\[100\]
+ch_out\[101\]
+ch_in\[102\]
+ch_out\[103\]
+ch_out\[104\]
+ch_in\[105\]
+
+
+
+
+ch_out\[106\]    1800 0 8
+ch_in\[107\]
+ch_out\[108\]
+ch_in\[109\]
+ch_out\[110\]
+ch_in\[111\]
+ch_out\[112\]
+ch_in\[113\]
+ch_out\[114\]
+ch_in\[115\]
+ch_out\[116\]
+ch_in\[117\]
+ch_out\[118\]
+ch_in\[119\]
+ch_out\[120\]
+ch_in\[121\]
+ch_out\[122\]
+ch_in\[123\]
+ch_out\[124\]
+ch_in\[125\]
+ch_out\[126\]
+ch_in\[127\]
+ch_out\[128\]
+ch_in\[129\]
+ch_out\[130\]
+ch_in\[131\]
+ch_out\[132\]
+ch_in\[133\]
+ch_out\[134\]
+ch_in\[135\]
+ch_out\[136\]
+ch_in\[137\]
+ch_out\[138\]
+ch_in\[139\]
+ch_out\[140\]
+ch_in\[141\]
+ch_in\[142\]   
+ch_in\[143\]
+ch_in\[144\]
+ch_in\[145\]
+ch_in\[146\]
+ch_in\[147\]
+ch_in\[148\]
+ch_in\[149\]
+ch_in\[150\]
+ch_in\[151\]
+ch_in\[152\]
+ch_in\[153\]
+ch_in\[154\]
+ch_in\[155\]
+ch_in\[156\]
+ch_in\[157\]
+ch_in\[158\]
+ch_in\[159\]
+ch_in\[160\]
+ch_in\[161\]
+ch_in\[162\]
+ch_in\[163\]
+ch_in\[164\]
+ch_in\[165\]
+ch_in\[166\]
+ch_in\[167\]
+ch_in\[168\]
+ch_in\[169\]
+ch_in\[170\]
+ch_in\[171\]
+ch_in\[172\]
+ch_in\[173\]
+ch_in\[174\]
+ch_in\[175\]
+ch_in\[176\]
+ch_in\[177\]
+ch_in\[178\]
+ch_in\[179\]
+ch_in\[180\]
+ch_in\[181\]
+ch_in\[182\]
+ch_in\[183\]
+ch_in\[184\]
+ch_in\[185\]
+ch_in\[186\]
+ch_in\[187\]
+
+ch_in\[188\]   2200 0 4
+ch_in\[189\]
+ch_in\[190\]
+ch_in\[191\]
+ch_in\[192\]
+ch_in\[193\]
+ch_in\[194\]
+ch_in\[195\]
+ch_in\[196\]
+ch_in\[197\]
+ch_in\[198\]
+ch_in\[199\]
+ch_in\[200\]
+ch_in\[201\]
+ch_in\[202\]
+ch_in\[203\]
+ch_in\[204\]
+ch_in\[205\]
+ch_in\[206\]
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+ch_in\[215\]
+ch_in\[216\]
+ch_in\[217\]
+ch_in\[218\]
+ch_in\[219\]
+
+ch_in\[220\]    2400 0 4
+ch_in\[221\]
+ch_in\[222\]
+ch_in\[223\]
+ch_in\[224\]
+ch_in\[225\]
+ch_in\[226\]
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+ch_in\[240\]
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+ch_in\[246\]
+ch_in\[247\]
+ch_in\[248\]
+ch_in\[249\]
+ch_in\[250\]
+ch_in\[251\]
+ch_out\[252\]
+
+
+#S
+ch_in\[0\]    0 0 16
+ch_in\[1\]   
+ch_out\[2\]   
+ch_in\[3\]   
+ch_in\[4\]   
+ch_in\[5\]   
+ch_in\[6\]   
+ch_in\[7\]   
+ch_out\[8\]   
+ch_in\[9\]   
+ch_in\[10\]   
+ch_in\[11\]   
+ch_out\[12\]   
+ch_in\[13\]   
+ch_in\[14\]   
+ch_in\[15\]   
+ch_out\[16\]   
+ch_in\[17\]   
+ch_in\[18\]   
+ch_in\[19\]   
+ch_out\[20\]   
+ch_in\[21\]   
+ch_in\[22\]   
+ch_in\[23\]   
+ch_out\[24\]   
+ch_in\[25\]   
+ch_in\[26\]   
+ch_out\[27\]   
+ch_in\[28\]   
+ch_in\[29\]   
+ch_out\[30\]   
+ch_in\[31\]   
+ch_in\[32\]   
+ch_out\[33\]   
+ch_in\[34\]   
+ch_in\[35\]   
+ch_out\[36\]   
+ch_in\[37\]   
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+ch_in\[44\]   
+ch_out\[45\]   
+ch_in\[46\]   
+ch_in\[47\]   
+ch_out\[48\]   
+ch_in\[49\]   
+ch_in\[50\]   
+ch_out\[51\]   
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+ch_out\[60\]   
+ch_in\[61\]   
+ch_in\[62\]   
+ch_out\[63\]   
+ch_in\[64\]   
+ch_in\[65\]   
+ch_out\[66\]   
+ch_in\[67\]   
+ch_in\[68\]   
+ch_out\[69\]   
+ch_in\[70\]   
+ch_in\[71\]   
+ch_out\[72\]   
+ch_in\[73\]   
+ch_in\[74\]   
+ch_out\[75\]   
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+ch_in\[77\]   
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+ch_in\[80\]   
+ch_out\[81\]   
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+ch_in\[83\]   
+ch_out\[84\]   
+ch_in\[85\]   
+ch_in\[86\]   
+ch_out\[87\]   
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+ch_in\[89\]   
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+ch_in\[94\]   
+ch_in\[95\]   
+ch_out\[96\]   
+ch_in\[97\]   
+ch_in\[98\]   
+ch_out\[99\]   
+ch_in\[100\]   
+ch_in\[101\]   
+ch_out\[102\]   
+ch_in\[103\]   
+ch_in\[104\]   
+ch_out\[105\]   
+
+
+ch_in\[106\]   600 0 32
+ch_out\[107\] 
+ch_in\[108\] 
+ch_out\[109\] 
+ch_in\[110\] 
+ch_out\[111\] 
+ch_in\[112\] 
+ch_out\[113\] 
+ch_in\[114\] 
+ch_out\[115\] 
+ch_in\[116\] 
+ch_out\[117\] 
+ch_in\[118\] 
+ch_out\[119\] 
+ch_in\[120\] 
+ch_out\[121\] 
+ch_in\[122\] 
+ch_out\[123\] 
+ch_in\[124\] 
+ch_out\[125\] 
+
+ch_in\[126\]    810 0 32
+ch_out\[127\] 
+ch_in\[128\] 
+ch_out\[129\] 
+ch_in\[130\] 
+ch_out\[131\] 
+ch_in\[132\] 
+ch_out\[133\] 
+ch_in\[134\] 
+ch_out\[135\] 
+ch_in\[136\] 
+ch_out\[137\] 
+ch_in\[138\] 
+ch_out\[139\] 
+ch_in\[140\] 
+ch_out\[141\] 
+
+
+ch_out\[142\] 1100 0 32
+ch_out\[143\] 
+ch_out\[144\] 
+ch_out\[145\] 
+ch_out\[146\] 
+ch_out\[147\] 
+ch_out\[148\] 
+ch_out\[149\] 
+ch_out\[150\] 
+ch_out\[151\] 
+ch_out\[152\] 
+ch_out\[153\] 
+ch_out\[154\] 
+ch_out\[155\] 
+ch_out\[156\] 
+ch_out\[157\] 
+ch_out\[158\] 
+ch_out\[159\] 
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+ch_out\[161\] 
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+ch_out\[180\] 
+ch_out\[181\] 
+ch_out\[182\] 
+ch_out\[183\] 
+ch_out\[184\] 
+ch_out\[185\] 
+ch_out\[186\] 
+ch_out\[187\] 
+
+ch_out\[188\] 1800 0 32
+ch_out\[189\] 
+ch_out\[190\] 
+ch_out\[191\] 
+ch_out\[192\] 
+ch_out\[193\] 
+ch_out\[194\] 
+ch_out\[195\] 
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+ch_out\[198\] 
+ch_out\[199\] 
+ch_out\[200\] 
+ch_out\[201\] 
+ch_out\[202\] 
+ch_out\[203\] 
+ch_out\[204\] 
+ch_out\[205\] 
+ch_out\[206\] 
+ch_out\[207\] 
+ch_out\[208\] 
+ch_out\[209\] 
+ch_out\[210\] 
+ch_out\[211\] 
+ch_out\[212\] 
+ch_out\[213\] 
+ch_out\[214\] 
+ch_out\[215\] 
+ch_out\[216\] 
+ch_out\[217\] 
+ch_out\[218\] 
+ch_out\[219\] 
+ch_out\[220\] 
+ch_out\[221\] 
+ch_out\[222\] 
+ch_out\[223\] 
+ch_out\[224\] 
+ch_out\[225\] 
+ch_out\[226\] 
+ch_out\[227\] 
+ch_out\[228\] 
+ch_out\[229\] 
+ch_out\[230\] 
+ch_out\[231\] 
+ch_out\[232\] 
+ch_out\[233\] 
+ch_out\[234\] 
+ch_out\[235\] 
+ch_out\[236\] 
+ch_out\[237\] 
+ch_out\[238\] 
+ch_out\[239\] 
+ch_out\[240\] 
+ch_out\[241\] 
+ch_out\[242\] 
+ch_out\[243\] 
+ch_out\[244\] 
+ch_out\[245\] 
+ch_out\[246\] 
+ch_out\[247\] 
+ch_out\[248\] 
+ch_out\[249\] 
+ch_out\[250\] 
+ch_out\[251\] 
+ch_in\[252\] 
+
diff --git a/openlane/bus_rep_west/config.tcl b/openlane/bus_rep_west/config.tcl
new file mode 100755
index 0000000..7cae84a
--- /dev/null
+++ b/openlane/bus_rep_west/config.tcl
@@ -0,0 +1,134 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+# Global
+# ------
+
+set script_dir [file dirname [file normalize [info script]]]
+# Name
+set ::env(DESIGN_NAME) bus_rep_west
+
+
+set ::env(DESIGN_IS_CORE) "1"
+set ::env(FP_PDN_CORE_RING) {1}
+
+# Timing configuration
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) ""
+set ::env(CLOCK_NET) ""
+
+set ::env(SYNTH_MAX_FANOUT) 4
+set ::env(SYNTH_BUFFERING) {0}
+
+
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+
+# Sources
+# -------
+
+# Local sources + no2usb sources
+set ::env(VERILOG_FILES) "\
+        $::env(DESIGN_DIR)/../../verilog/rtl/bus_rep/bus_rep_west.sv \
+	"
+
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
+
+set ::env(SYNTH_PARAMETERS) "BUS_REP_WD=42 "
+
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+#set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+#set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+
+set ::env(LEC_ENABLE) 0
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+
+# Floorplanning
+# -------------
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 3250 50"
+
+#set ::env(GRT_OBS) "met4  0 0 300 1725"
+
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
+
+#set ::env(PDN_CFG) $::env(DESIGN_DIR)/pdn.tcl
+
+
+
+set ::env(PL_TIME_DRIVEN) 1
+set ::env(PL_TARGET_DENSITY) "0.20"
+set ::env(CELL_PAD) "8"
+set ::env(GRT_ADJUSTMENT) 0.2
+
+# helps in anteena fix
+set ::env(USE_ARC_ANTENNA_CHECK) "0"
+
+
+#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+## CTS
+set ::env(CLOCK_TREE_SYNTH) {0}
+
+## Placement
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) "0"
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) "0"
+
+## Routing
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0"
+
+#LVS Issue - DEF Base looks to having issue
+set ::env(MAGIC_EXT_USE_GDS) {1}
+
+#set ::env(GLB_RT_MAXLAYER) 3
+set ::env(RT_MAX_LAYER) {met3}
+set ::env(FP_PDN_LOWER_LAYER) {met2}
+set ::env(FP_PDN_UPPER_LAYER) {met3}
+
+set ::env(FP_IO_HLAYER) {met2}
+set ::env(FP_IO_VLAYER) {met1}
+
+#Lef 
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+
+## Placement
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) 2
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) "500"
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) "2.0"
+
+set ::env(ECO_ENABLE) {0}
+#set ::env(CURRENT_STEP) "synthesis"
+#set ::env(LAST_STEP) "parasitics_sta"
+
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "1"
+set ::env(QUIT_ON_LVS_ERROR) "1"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/bus_rep_west/interactive.tcl b/openlane/bus_rep_west/interactive.tcl
new file mode 100755
index 0000000..5b5c6c8
--- /dev/null
+++ b/openlane/bus_rep_west/interactive.tcl
@@ -0,0 +1,337 @@
+#!/usr/bin/env tclsh
+# Copyright 2020-2022 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+package require openlane; # provides the utils as well
+proc run_placement_step {args} {
+    if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
+        set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
+    }
+
+    run_placement
+}
+
+proc run_cts_step {args} {
+    if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
+        set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
+    }
+
+    run_cts
+    run_resizer_timing
+    if { $::env(RSZ_USE_OLD_REMOVER) == 1} {
+        remove_buffers_from_nets
+    }
+}
+
+proc run_routing_step {args} {
+    if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
+        set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
+    }
+    if { $::env(ECO_ENABLE) == 0 } {
+        run_routing
+    }
+}
+
+proc run_parasitics_sta_step {args} {
+    if { ! [ info exists ::env(PARSITICS_CURRENT_DEF) ] } {
+        set ::env(PARSITICS_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(PARSITICS_CURRENT_DEF)
+    }
+
+    if { $::env(RUN_SPEF_EXTRACTION) && ($::env(ECO_ENABLE) == 0)} {
+        run_parasitics_sta
+    }
+}
+
+proc run_diode_insertion_2_5_step {args} {
+    if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
+        set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
+    }
+    if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
+        run_antenna_check
+        heal_antenna_violators; # modifies the routed DEF
+    }
+
+}
+
+proc run_irdrop_report_step {args} {
+    if { $::env(RUN_IRDROP_REPORT) } {
+        run_irdrop_report
+    }
+}
+
+proc run_lvs_step {{ lvs_enabled 1 }} {
+    if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
+        set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
+    }
+
+    if { $lvs_enabled && $::env(RUN_LVS) } {
+        run_magic_spice_export;
+        run_lvs; # requires run_magic_spice_export
+    }
+
+}
+
+proc run_drc_step {{ drc_enabled 1 }} {
+    if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
+        set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
+    }
+    if { $drc_enabled } {
+        if { $::env(RUN_MAGIC_DRC) } {
+            run_magic_drc
+        }
+        if {$::env(RUN_KLAYOUT_DRC)} {
+            run_klayout_drc
+        }
+    }
+}
+
+proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
+    if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
+        set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
+    }
+    if { $antenna_check_enabled } {
+        run_antenna_check
+    }
+}
+
+proc run_erc_step {args} {
+    if { $::env(RUN_CVC) } {
+        run_erc
+    }
+}
+
+proc run_eco_step {args} {
+    if { $::env(ECO_ENABLE) == 1 } {
+        run_eco_flow
+    }
+}
+
+proc run_magic_step {args} {
+    if {$::env(RUN_MAGIC)} {
+        run_magic
+    }
+}
+
+proc run_klayout_step {args} {
+    if {$::env(RUN_KLAYOUT)} {
+        run_klayout
+    }
+    if {$::env(RUN_KLAYOUT_XOR)} {
+        run_klayout_gds_xor
+    }
+}
+
+proc run_post_run_hooks {} {
+    if { [file exists $::env(DESIGN_DIR)/hooks/post_run.py]} {
+        puts_info "Running post run hook"
+        set result [exec $::env(OPENROAD_BIN) -exit -no_init -python $::env(DESIGN_DIR)/hooks/post_run.py]
+        puts_info "$result"
+    } else {
+        puts_info "hooks/post_run.py not found, skipping"
+    }
+}
+
+proc run_floorplan {args} {
+    # |----------------------------------------------------|
+    # |----------------   2. FLOORPLAN   ------------------|
+    # |----------------------------------------------------|
+    #
+    # intial fp
+    init_floorplan
+
+    # check for deprecated io variables
+    if { [info exists ::env(FP_IO_HMETAL)]} {
+        set ::env(FP_IO_HLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_HMETAL) - 1}]]
+        puts_warn "You're using FP_IO_HMETAL in your configuration, which is a deprecated variable that will be removed in the future."
+        puts_warn "We recommend you update your configuration as follows:"
+        puts_warn "\tset ::env(FP_IO_HLAYER) {$::env(FP_IO_HLAYER)}"
+    }
+
+    if { [info exists ::env(FP_IO_VMETAL)]} {
+        set ::env(FP_IO_VLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_VMETAL) - 1}]]
+        puts_warn "You're using FP_IO_VMETAL in your configuration, which is a deprecated variable that will be removed in the future."
+        puts_warn "We recommend you update your configuration as follows:"
+        puts_warn "\tset ::env(FP_IO_VLAYER) {$::env(FP_IO_VLAYER)}"
+    }
+
+
+    # place io
+    if { [info exists ::env(FP_PIN_ORDER_CFG)] } {
+        place_io_ol
+    } else {
+        if { [info exists ::env(FP_CONTEXT_DEF)] && [info exists ::env(FP_CONTEXT_LEF)] } {
+            place_io
+            global_placement_or
+            place_contextualized_io \
+                -lef $::env(FP_CONTEXT_LEF) \
+                -def $::env(FP_CONTEXT_DEF)
+        } else {
+            place_io
+        }
+    }
+
+    apply_def_template
+
+    #if { [info exist ::env(EXTRA_LEFS)] } {
+        if { [info exist ::env(MACRO_PLACEMENT_CFG)] } {
+            file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(placement_tmpfiles)/macro_placement.cfg
+            manual_macro_placement -f
+        } else {
+        #    global_placement_or
+        #    basic_macro_placement
+        }
+    #}
+
+    if { $::env(RUN_TAP_DECAP_INSERTION) } {
+        tap_decap_or
+    }
+
+    scrot_klayout -layout $::env(CURRENT_DEF) -log $::env(floorplan_logs)/screenshot.log
+
+    run_power_grid_generation
+}
+
+
+
+proc run_flow {args} {
+    set options {
+        {-design optional}
+        {-from optional}
+        {-to optional}
+        {-save_path optional}
+        {-override_env optional}
+    }
+    set flags {-save -run_hooks -no_lvs -no_drc -no_antennacheck -gui}
+    parse_key_args "run_non_interactive_mode" args arg_values $options flags_map $flags -no_consume
+
+    prep {*}$args
+    # signal trap SIGINT save_state;
+
+    if { [info exists flags_map(-gui)] } {
+        or_gui
+        return
+    }
+    if { [info exists arg_values(-override_env)] } {
+        load_overrides $arg_values(-override_env)
+    }
+
+    set LVS_ENABLED 1
+    set DRC_ENABLED 1
+
+    set ANTENNACHECK_ENABLED [expr ![info exists flags_map(-no_antennacheck)] ]
+
+    set steps [dict create \
+        "synthesis" "run_synthesis" \
+        "floorplan" "run_floorplan" \
+        "placement" "run_placement_step" \
+        "cts" "run_cts_step" \
+        "routing" "run_routing_step" \
+        "parasitics_sta" "run_parasitics_sta_step" \
+        "eco" "run_eco_step" \
+        "diode_insertion" "run_diode_insertion_2_5_step" \
+        "irdrop" "run_irdrop_report_step" \
+        "gds_magic" "run_magic_step" \
+        "gds_klayout" "run_klayout_step" \
+        "lvs" "run_lvs_step $LVS_ENABLED " \
+        "drc" "run_drc_step $DRC_ENABLED " \
+        "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED " \
+        "cvc" "run_lef_cvc"
+    ]
+
+    if { [info exists arg_values(-from) ]} {
+        puts_info "Starting flow at $arg_values(-from)..."
+        set ::env(CURRENT_STEP) $arg_values(-from)
+    } elseif {  [info exists ::env(CURRENT_STEP) ] } {
+        puts_info "Resuming flow from $::env(CURRENT_STEP)..."
+    } else {
+        set ::env(CURRENT_STEP) "synthesis"
+    }
+
+    set_if_unset arg_values(-from) $::env(CURRENT_STEP)
+    set_if_unset arg_values(-to) "cvc"
+
+    set exe 0;
+    dict for {step_name step_exe} $steps {
+        if { [ string equal $arg_values(-from) $step_name ] } {
+            set exe 1;
+        }
+
+        if { $exe } {
+            # For when it fails
+            set ::env(CURRENT_STEP) $step_name
+            [lindex $step_exe 0] [lindex $step_exe 1] ;
+        }
+
+        if { [ string equal $arg_values(-to) $step_name ] } {
+            set exe 0:
+            break;
+        }
+
+    }
+
+    # for when it resumes
+    set steps_as_list [dict keys $steps]
+    set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
+    set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
+
+    # Saves to <RUN_DIR>/results/final
+    save_final_views
+
+    # Saves to design directory or custom
+    if {  [info exists flags_map(-save) ] } {
+        if { ! [info exists arg_values(-save_path)] } {
+            set arg_values(-save_path) $::env(DESIGN_DIR)
+        }
+        save_final_views\
+            -save_path $arg_values(-save_path)\
+            -tag $::env(RUN_TAG)
+    }
+    calc_total_runtime
+    save_state
+    generate_final_summary_report
+
+    check_timing_violations
+
+    if { [info exists arg_values(-save_path)]\
+        && $arg_values(-save_path) != "" } {
+        set ::env(HOOK_OUTPUT_PATH) "[file normalize $arg_values(-save_path)]"
+    } else {
+        set ::env(HOOK_OUTPUT_PATH) $::env(RESULTS_DIR)/final
+    }
+
+    if {[info exists flags_map(-run_hooks)]} {
+        run_post_run_hooks
+    }
+
+    puts_success "Flow complete."
+
+    show_warnings "Note that the following warnings have been generated:"
+}
+
+run_flow {*}$argv
diff --git a/openlane/bus_rep_west/macro.cfg b/openlane/bus_rep_west/macro.cfg
new file mode 100644
index 0000000..5bd9eb4
--- /dev/null
+++ b/openlane/bus_rep_west/macro.cfg
@@ -0,0 +1,42 @@
+u_rp\[0\].u_buf			7.82	10.88	FN
+u_rp\[1\].u_buf			85.1	10.88	FN
+u_rp\[2\].u_buf			162.38	10.88	FN
+u_rp\[3\].u_buf			239.66	10.88	FN
+u_rp\[4\].u_buf			316.94	10.88	FN
+u_rp\[5\].u_buf			394.22	10.88	FN
+u_rp\[6\].u_buf			471.5	10.88	FN
+u_rp\[7\].u_buf			548.78	10.88	FN
+u_rp\[8\].u_buf			626.06	10.88	FN
+u_rp\[9\].u_buf			703.34	10.88	FN
+u_rp\[10\].u_buf			780.62	10.88	FN
+u_rp\[11\].u_buf			857.9	10.88	FN
+u_rp\[12\].u_buf			935.18	10.88	FN
+u_rp\[13\].u_buf			1012.46	10.88	FN
+u_rp\[14\].u_buf			1089.74	10.88	FN
+u_rp\[15\].u_buf			1167.02	10.88	FN
+u_rp\[16\].u_buf			1244.3	10.88	FN
+u_rp\[17\].u_buf			1321.58	10.88	FN
+u_rp\[18\].u_buf			1398.86	10.88	FN
+u_rp\[19\].u_buf			1476.14	10.88	FN
+u_rp\[20\].u_buf			1553.42	10.88	FN
+u_rp\[21\].u_buf			1630.7	10.88	FN
+u_rp\[22\].u_buf			1707.98	10.88	FN
+u_rp\[23\].u_buf			1785.26	10.88	FN
+u_rp\[24\].u_buf			1862.54	10.88	FN
+u_rp\[25\].u_buf			1939.82	10.88	FN
+u_rp\[26\].u_buf			2017.1	10.88	FN
+u_rp\[27\].u_buf			2094.38	10.88	FN
+u_rp\[28\].u_buf			2171.66	10.88	FN
+u_rp\[29\].u_buf			2248.94	10.88	FN
+u_rp\[30\].u_buf			2326.22	10.88	FN
+u_rp\[31\].u_buf			2403.5	10.88	FN
+u_rp\[32\].u_buf			2480.78	10.88	FN
+u_rp\[33\].u_buf			2558.06	10.88	FN
+u_rp\[34\].u_buf			2635.34	10.88	FN
+u_rp\[35\].u_buf			2712.62	10.88	FN
+u_rp\[36\].u_buf			2789.9	10.88	FN
+u_rp\[37\].u_buf			2867.18	10.88	FN
+u_rp\[38\].u_buf			2944.46	10.88	FN
+u_rp\[39\].u_buf			3021.74	10.88	FN
+u_rp\[40\].u_buf			3099.02	10.88	FN
+u_rp\[41\].u_buf			3176.3	10.88	FN
diff --git a/openlane/bus_rep_west/pdn.tcl b/openlane/bus_rep_west/pdn.tcl
new file mode 100644
index 0000000..1fe689b
--- /dev/null
+++ b/openlane/bus_rep_west/pdn.tcl
@@ -0,0 +1,49 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# Power nets
+set ::power_nets $::env(VDD_PIN)
+set ::ground_nets $::env(GND_PIN)
+
+set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
+
+pdngen::specify_grid stdcell {
+    name grid
+    rails {
+	    met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
+    }
+    straps {
+	    met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
+	    met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
+    }
+    connect {{met1 met4} {met4 met5}}
+}
+
+pdngen::specify_grid macro {
+    power_pins "VPWR"
+    ground_pins "VGND"
+    blockages "li1 met1 met2 met3 met4"
+    straps { 
+    } 
+    connect {{met4_PIN_ver met5}}
+}
+
+set ::halo 5
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;
diff --git a/openlane/bus_rep_west/pin_order.cfg b/openlane/bus_rep_west/pin_order.cfg
new file mode 100644
index 0000000..74e6240
--- /dev/null
+++ b/openlane/bus_rep_west/pin_order.cfg
@@ -0,0 +1,91 @@
+#BUS_SORT
+
+#MANUAL_PLACE
+
+#S
+ch_in\[0\]    0 0 225
+ch_out\[1\]    
+ch_out\[2\]
+ch_in\[3\]    
+ch_out\[4\]    
+ch_out\[5\]
+ch_in\[6\]    
+ch_out\[7\]    
+ch_out\[8\]
+ch_in\[9\]    
+ch_out\[10\]    
+ch_out\[11\]
+ch_in\[12\]    
+ch_out\[13\]    
+ch_out\[14\]
+ch_in\[15\]    
+ch_out\[16\]    
+ch_out\[17\]
+ch_in\[18\]    
+ch_out\[19\]    
+ch_out\[20\]
+ch_in\[21\]    
+ch_out\[22\]    
+ch_out\[23\]
+ch_in\[24\]    
+ch_out\[25\]    
+ch_out\[26\]
+ch_in\[27\]    
+ch_out\[28\]    
+ch_out\[29\]
+ch_in\[30\]    
+ch_out\[31\]    
+ch_out\[32\]
+ch_in\[33\]    
+ch_out\[34\]    
+ch_out\[35\]
+ch_in\[36\]    
+ch_out\[37\]    
+ch_out\[38\]
+ch_in\[39\]    
+ch_out\[40\]    
+ch_out\[41\]
+
+#N
+ch_out\[0\]    100 0 4
+ch_in\[1\]
+ch_in\[2\]
+ch_out\[3\]    
+ch_in\[4\]
+ch_in\[5\]
+ch_out\[6\]    
+ch_in\[7\]
+ch_in\[8\]
+ch_out\[9\]    
+ch_in\[10\]
+ch_in\[11\]
+ch_out\[12\]    
+ch_in\[13\]
+ch_in\[14\]
+ch_out\[15\]    
+ch_in\[16\]
+ch_in\[17\]
+ch_out\[18\]    
+ch_in\[19\]
+ch_in\[20\]
+ch_out\[21\]    
+ch_in\[22\]
+ch_in\[23\]
+ch_out\[24\]    
+ch_in\[25\]
+ch_in\[26\]
+ch_out\[27\]    
+ch_in\[28\]
+ch_in\[29\]
+ch_out\[30\]    
+ch_in\[31\]
+ch_in\[32\]
+ch_out\[33\]    
+ch_in\[34\]
+ch_in\[35\]
+ch_out\[36\]    
+ch_in\[37\]
+ch_in\[38\]
+ch_out\[39\]    
+ch_in\[40\]
+ch_in\[41\]
diff --git a/openlane/pinmux_top/config.tcl b/openlane/pinmux_top/config.tcl
index 3900d26..b52bc4e 100755
--- a/openlane/pinmux_top/config.tcl
+++ b/openlane/pinmux_top/config.tcl
@@ -30,6 +30,7 @@
 set ::env(CLOCK_PORT) "mclk"
 
 set ::env(SYNTH_MAX_FANOUT) 4
+set ::env(SYNTH_BUFFERING) {0}
 
 ## CTS BUFFER
 set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
diff --git a/openlane/pinmux_top/pin_order.cfg b/openlane/pinmux_top/pin_order.cfg
index a8e15ef..fff23e7 100644
--- a/openlane/pinmux_top/pin_order.cfg
+++ b/openlane/pinmux_top/pin_order.cfg
@@ -425,23 +425,6 @@
 digital_io_out\[24\]
 digital_io_in\[24\]
 
-sflash_oen\[0\]    350 0 2
-sflash_oen\[1\]
-sflash_oen\[2\]
-sflash_oen\[3\]
-sflash_ss\[0\]
-sflash_ss\[1\]
-sflash_ss\[2\]
-sflash_ss\[3\]
-sflash_sck   
-sflash_do\[0\]
-sflash_do\[1\]
-sflash_do\[2\]
-sflash_do\[3\]
-sflash_di\[0\]      
-sflash_di\[1\]      
-sflash_di\[2\]      
-sflash_di\[3\]      
 
 digital_io_in\[23\]     400  0
 digital_io_out\[23\]
@@ -473,6 +456,23 @@
 
 
 #E
+sflash_oen\[0\]    
+sflash_oen\[1\]
+sflash_oen\[2\]
+sflash_oen\[3\]
+sflash_ss\[0\]
+sflash_ss\[1\]
+sflash_ss\[2\]
+sflash_ss\[3\]
+sflash_sck   
+sflash_do\[0\]
+sflash_do\[1\]
+sflash_do\[2\]
+sflash_do\[3\]
+sflash_di\[0\]      
+sflash_di\[1\]      
+sflash_di\[2\]      
+sflash_di\[3\]      
 
 digital_io_in\[0\]   0200 0 4
 digital_io_out\[0\]
diff --git a/openlane/qspim_top/pin_order.cfg b/openlane/qspim_top/pin_order.cfg
index c078759..8c81d46 100644
--- a/openlane/qspim_top/pin_order.cfg
+++ b/openlane/qspim_top/pin_order.cfg
@@ -2,40 +2,8 @@
 #MANUAL_PLACE
 
 #E
-spi_debug\[0\]        0000 0  2
-spi_debug\[1\]        
-spi_debug\[2\]        
-spi_debug\[3\]        
-spi_debug\[4\]        
-spi_debug\[5\]        
-spi_debug\[6\]        
-spi_debug\[7\]        
-spi_debug\[8\]        
-spi_debug\[9\]        
-spi_debug\[10\]        
-spi_debug\[11\]        
-spi_debug\[12\]        
-spi_debug\[13\]        
-spi_debug\[14\]        
-spi_debug\[15\]        
-spi_debug\[16\]        
-spi_debug\[17\]        
-spi_debug\[18\]        
-spi_debug\[19\]        
-spi_debug\[20\]        
-spi_debug\[21\]        
-spi_debug\[22\]        
-spi_debug\[23\]        
-spi_debug\[24\]        
-spi_debug\[25\]        
-spi_debug\[26\]        
-spi_debug\[27\]        
-spi_debug\[28\]        
-spi_debug\[29\]        
-spi_debug\[30\]        
-spi_debug\[31\]        
 
-spi_sdi\[3\]             0200 0 2
+spi_sdi\[3\]             0500 0 2
 spi_sdi\[2\]        
 spi_sdi\[1\]        
 spi_sdi\[0\]        
@@ -192,3 +160,36 @@
 strap_pre_sram
 strap_flash\[1\]
 strap_flash\[0\]
+
+spi_debug\[0\]        0200 0  2
+spi_debug\[1\]        
+spi_debug\[2\]        
+spi_debug\[3\]        
+spi_debug\[4\]        
+spi_debug\[5\]        
+spi_debug\[6\]        
+spi_debug\[7\]        
+spi_debug\[8\]        
+spi_debug\[9\]        
+spi_debug\[10\]        
+spi_debug\[11\]        
+spi_debug\[12\]        
+spi_debug\[13\]        
+spi_debug\[14\]        
+spi_debug\[15\]        
+spi_debug\[16\]        
+spi_debug\[17\]        
+spi_debug\[18\]        
+spi_debug\[19\]        
+spi_debug\[20\]        
+spi_debug\[21\]        
+spi_debug\[22\]        
+spi_debug\[23\]        
+spi_debug\[24\]        
+spi_debug\[25\]        
+spi_debug\[26\]        
+spi_debug\[27\]        
+spi_debug\[28\]        
+spi_debug\[29\]        
+spi_debug\[30\]        
+spi_debug\[31\]        
diff --git a/openlane/uart_i2c_usb_spi_top/config.tcl b/openlane/uart_i2c_usb_spi_top/config.tcl
index 358a009..fcf98c4 100644
--- a/openlane/uart_i2c_usb_spi_top/config.tcl
+++ b/openlane/uart_i2c_usb_spi_top/config.tcl
@@ -30,6 +30,7 @@
 set ::env(CLOCK_PORT) "app_clk usb_clk u_uart0_core.u_lineclk_buf.genblk1.u_mux/X u_uart1_core.u_lineclk_buf.genblk1.u_mux/X"
 
 set ::env(SYNTH_MAX_FANOUT) 4
+set ::env(SYNTH_BUFFERING) {0}
 
 ## CTS BUFFER
 set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
diff --git a/openlane/uart_i2c_usb_spi_top/pin_order.cfg b/openlane/uart_i2c_usb_spi_top/pin_order.cfg
index 2801070..b518404 100644
--- a/openlane/uart_i2c_usb_spi_top/pin_order.cfg
+++ b/openlane/uart_i2c_usb_spi_top/pin_order.cfg
@@ -101,7 +101,7 @@
 usb_rstn 
 
 
-#E
+#N
 scl_pad_i 
 scl_pad_o
 scl_pad_oen_o
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index b9e53fb..f26769b 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -78,6 +78,10 @@
 	    $::env(DESIGN_DIR)/../../verilog/gl/dac_top.v \
 	    $::env(DESIGN_DIR)/../../verilog/gl/aes_top.v \
 	    $::env(DESIGN_DIR)/../../verilog/gl/fpu_wrapper.v \
+	    $::env(DESIGN_DIR)/../../verilog/gl/bus_rep_south.v \
+	    $::env(DESIGN_DIR)/../../verilog/gl/bus_rep_north.v \
+	    $::env(DESIGN_DIR)/../../verilog/gl/bus_rep_east.v \
+	    $::env(DESIGN_DIR)/../../verilog/gl/bus_rep_west.v \
 	    "
 
 set ::env(EXTRA_LEFS) "\
@@ -94,6 +98,10 @@
 	$lef_root/dac_top.lef \
 	$lef_root/aes_top.lef \
 	$lef_root/fpu_wrapper.lef \
+	$lef_root/bus_rep_south.lef \
+	$lef_root/bus_rep_north.lef \
+	$lef_root/bus_rep_east.lef \
+	$lef_root/bus_rep_west.lef \
 	"
 
 set ::env(EXTRA_GDS_FILES) "\
@@ -110,6 +118,10 @@
 	$::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds \
 	$gds_root/aes_top.gds \
 	$gds_root/fpu_wrapper.gds \
+	$gds_root/bus_rep_south.gds \
+	$gds_root/bus_rep_north.gds \
+	$gds_root/bus_rep_east.gds \
+	$gds_root/bus_rep_west.gds \
 	"
 
 set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
@@ -121,6 +133,10 @@
 
 ## Internal Macros
 ### Macro PDN Connections
+set ::env(FP_PDN_CHECK_NODES) 1
+set ::env(FP_PDN_IRDROP) "1"
+set ::env(RUN_IRDROP_REPORT) "1"
+####################
 
 set ::env(FP_PDN_ENABLE_MACROS_GRID) {1}
 set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) "0"
@@ -133,8 +149,8 @@
 set ::env(FP_PDN_VPITCH) "80"
 set ::env(FP_PDN_HOFFSET) "5"
 set ::env(FP_PDN_HPITCH) "80"
-set ::env(FP_PDN_HWIDTH) {6.2}
-set ::env(FP_PDN_VWIDTH) {6.2}
+set ::env(FP_PDN_HWIDTH) {5.2}
+set ::env(FP_PDN_VWIDTH) {5.2}
 set ::env(FP_PDN_HSPACING) {13.8}
 set ::env(FP_PDN_VSPACING) {13.8}
 
@@ -161,6 +177,7 @@
                     met1  150  750 833.1  1166.54,\
                     met2  150  750 833.1  1166.54,\
                     met3  150  750 833.1  1166.54,\
+                    met3  50   100 100    3350,\
 	                met5  0 0 2920 3520"
 
 #set ::env(FP_PDN_POWER_STRAPS) "vccd1 vssd1 1, vccd2 vssd2 0, vdda1 vssa1 1, vdda2 vssa2 1"
@@ -181,7 +198,11 @@
 	u_riscv_top.u_intf          vccd1 vssd1 vccd1 vssd1,\
 	u_4x8bit_dac                vdda1 vssa1 vccd1 vssd1,\
 	u_aes                       vccd1 vssd1 vccd1 vssd1,\
-	u_fpu                       vccd1 vssd1 vccd1 vssd1
+	u_fpu                       vccd1 vssd1 vccd1 vssd1,\
+	u_rp_south                  vccd1 vssd1 vccd1 vssd1,\
+	u_rp_north                  vccd1 vssd1 vccd1 vssd1,\
+	u_rp_east                   vccd1 vssd1 vccd1 vssd1,\
+	u_rp_west                   vccd1 vssd1 vccd1 vssd1
       	"
 
 
@@ -203,4 +224,6 @@
 set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
 set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
 
+## Temp Masked due to long Run Time
+set ::env(RUN_KLAYOUT_XOR) {0}
 
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index f120935..3a3500f 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -4,9 +4,9 @@
 u_pinmux                     2250            2000           N
 u_pll                        2500            3028           N
 
-u_fpu                       1000            2600           N
-u_aes                       50              2600           N
-u_riscv_top.i_core_top_0    75	     1400 	     N
+u_fpu                       1100            2600           N
+u_aes                       150             2600           N
+u_riscv_top.i_core_top_0    150	     1400 	     N
 u_riscv_top.i_core_top_1    1200	     1400	     FN
 u_riscv_top.u_connect       733	     1400	     N
 u_riscv_top.u_intf          950 	     650	     N
@@ -15,5 +15,9 @@
 u_tsram0_2kb                150             750            N
 
 
-u_intercon                  1850            650             N
-u_wb_host                   1750            100             N
+u_intercon                  1850            650          N
+u_wb_host                   1750            150          N
+u_rp_south                   100            20           N
+u_rp_north                   100            3400         N
+u_rp_east                   2820            50           E
+u_rp_west                     50            100          E
diff --git a/openlane/user_project_wrapper/pdn_cfg.tcl b/openlane/user_project_wrapper/pdn_cfg.tcl
index b2a2b42..b317190 100644
--- a/openlane/user_project_wrapper/pdn_cfg.tcl
+++ b/openlane/user_project_wrapper/pdn_cfg.tcl
@@ -150,14 +150,46 @@
         -spacings "$::env(FP_PDN_CORE_RING_VSPACING) $::env(FP_PDN_CORE_RING_HSPACING)" \
         -core_offset "$::env(FP_PDN_CORE_RING_VOFFSET) $::env(FP_PDN_CORE_RING_HOFFSET)"
 }
+##################################
+# Common Macro Power Hook Up
+#   Power Connect met-4 to met-5
+##################################
 
 define_pdn_grid \
     -macro \
-    -default \
-    -name macro \
+    -name macro_1 \
+    -instances "u_pll u_intercon u_pinmux u_qspi_master u_tsram0_2kb u_icache_2kb u_dcache_2kb u_uart_i2c_usb_spi u_wb_host u_riscv_top.i_core_top_0 u_riscv_top.i_core_top_1 u_riscv_top.u_connect u_riscv_top.u_intf u_4x8bit_dac u_aes u_fpu" \
     -starts_with POWER \
     -halo "$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)"
 
 add_pdn_connect \
-    -grid macro \
+    -grid macro_1 \
     -layers "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"
+
+##################################
+# u_rp_North & u_rp_south Power Hook Up
+#  Power connect met-3 to met-4
+##################################
+
+define_pdn_grid \
+    -macro \
+    -name macro_2 \
+    -instances "u_rp_south u_rp_north" \
+    -starts_with POWER \
+    -halo "$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)"
+
+add_pdn_connect -grid macro_2 -layers "met3 met4"
+
+##################################
+# u_rp_east Power Hook Up
+#  Power connect met-3 to met-5
+##################################
+
+define_pdn_grid \
+    -macro \
+    -name macro_3 \
+    -instances "u_rp_east u_rp_west" \
+    -starts_with POWER \
+    -halo "$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)"
+
+add_pdn_connect -grid macro_3 -layers "met3 met5"
diff --git a/openlane/ycr2_iconnect/pin_order.cfg b/openlane/ycr2_iconnect/pin_order.cfg
index e23aca7..48f9639 100644
--- a/openlane/ycr2_iconnect/pin_order.cfg
+++ b/openlane/ycr2_iconnect/pin_order.cfg
@@ -753,7 +753,7 @@
 core_debug_sel\[1\]  300 0 2
 core_debug_sel\[0\]
 
-riscv_debug\[63\]   
+riscv_debug\[63\]
 riscv_debug\[62\]
 riscv_debug\[61\]
 riscv_debug\[60\]
diff --git a/openlane/ycr_intf/base.sdc b/openlane/ycr_intf/base.sdc
index cc73165..2542338 100644
--- a/openlane/ycr_intf/base.sdc
+++ b/openlane/ycr_intf/base.sdc
@@ -2,6 +2,7 @@
 # Timing Constraints
 ###############################################################################
 create_clock -name core_clk -period 10.0000 [get_ports {core_clk}]
+create_clock -name rtc_clk -period 40.0000 [get_ports {rtc_clk}]
 create_clock -name wb_clk -period 10.0000 [get_ports {wb_clk}]
 
 create_generated_clock -name dcache_mem_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {dcache mem clock0} [get_ports dcache_mem_clk0]
@@ -20,6 +21,7 @@
 
 set_clock_groups -name async_clock -asynchronous \
  -group [get_clocks {core_clk dcache_mem_clk0 dcache_mem_clk1 icache_mem_clk0 icache_mem_clk1}]\
+ -group [get_clocks {rtc_clk}]\
  -group [get_clocks {wb_clk}] -comment {Async Clock group}
 
 # Set case analysis
diff --git a/signoff/qspim_top/OPENLANE_VERSION b/signoff/qspim_top/OPENLANE_VERSION
index fabca1a..1234be5 100644
--- a/signoff/qspim_top/OPENLANE_VERSION
+++ b/signoff/qspim_top/OPENLANE_VERSION
@@ -1 +1 @@
-OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
+OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483
diff --git a/signoff/qspim_top/PDK_SOURCES b/signoff/qspim_top/PDK_SOURCES
index ef91c87..f8d3b3a 100644
--- a/signoff/qspim_top/PDK_SOURCES
+++ b/signoff/qspim_top/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c
+open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93
diff --git a/signoff/ycr_core_top/OPENLANE_VERSION b/signoff/ycr_core_top/OPENLANE_VERSION
index fabca1a..1234be5 100644
--- a/signoff/ycr_core_top/OPENLANE_VERSION
+++ b/signoff/ycr_core_top/OPENLANE_VERSION
@@ -1 +1 @@
-OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
+OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483
diff --git a/signoff/ycr_core_top/PDK_SOURCES b/signoff/ycr_core_top/PDK_SOURCES
index ef91c87..f8d3b3a 100644
--- a/signoff/ycr_core_top/PDK_SOURCES
+++ b/signoff/ycr_core_top/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c
+open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93
diff --git a/verilog/dv/risc_boot/risc_boot_tb.v b/verilog/dv/risc_boot/risc_boot_tb.v
index ef56ee4..2ea05db 100644
--- a/verilog/dv/risc_boot/risc_boot_tb.v
+++ b/verilog/dv/risc_boot/risc_boot_tb.v
@@ -143,6 +143,14 @@
 
 	initial begin
 
+		$display("################# NOTE:#####################################");
+        $display("This test assumes Caravel GPIO are pre-programmed with user_define.v value");
+        $display("If you see RTL simulation fails, cross check mgmt_core_wrapper/verilog/includes/includes.rtl.caravel ");
+        $display("    From: -v $(CARAVEL_PATH)/rtl/user_defines.v       ");
+        $display("    To:   -v $(USER_PROJECT_VERILOG)/rtl/user_defines.v ");
+        $display("    Gate Sim expect to fail as caravel gate netlist have not generated based on user_define.v in user project");
+		$display("#####################################################################################");
+        
 		// Repeat cycles of 1000 clock edges as needed to complete testbench
 		repeat (80) begin
 			repeat (2000) @(posedge clock);
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project
index d7c52cc..35d26f5 100644
--- a/verilog/includes/includes.gl.caravel_user_project
+++ b/verilog/includes/includes.gl.caravel_user_project
@@ -224,6 +224,10 @@
 
 $(USER_PROJECT_VERILOG)/gl/aes_top.v
 $(USER_PROJECT_VERILOG)/gl/fpu_wrapper.v
+$(USER_PROJECT_VERILOG)/gl/bus_rep_south.v
+$(USER_PROJECT_VERILOG)/gl/bus_rep_north.v
+$(USER_PROJECT_VERILOG)/gl/bus_rep_east.v
+$(USER_PROJECT_VERILOG)/gl/bus_rep_west.v
 
 -v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/dg_pll.v
 
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index 30634b6..e770eff 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -167,3 +167,7 @@
 
 
 -v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/dg_pll.v
+-v $(USER_PROJECT_VERILOG)/rtl/bus_rep/bus_rep_south.sv
+-v $(USER_PROJECT_VERILOG)/rtl/bus_rep/bus_rep_north.sv
+-v $(USER_PROJECT_VERILOG)/rtl/bus_rep/bus_rep_east.sv
+-v $(USER_PROJECT_VERILOG)/rtl/bus_rep/bus_rep_west.sv
diff --git a/verilog/rtl/bus_rep/bus_rep_east.sv b/verilog/rtl/bus_rep/bus_rep_east.sv
new file mode 100644
index 0000000..6e7626d
--- /dev/null
+++ b/verilog/rtl/bus_rep/bus_rep_east.sv
@@ -0,0 +1,52 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//               Bus Repater                                        //
+//////////////////////////////////////////////////////////////////////
+module bus_rep_east #(
+	parameter BUS_REP_WD = 7
+        ) (
+`ifdef USE_POWER_PINS
+         input logic            vccd1,    // User area 1 1.8V supply
+         input logic            vssd1,    // User area 1 digital ground
+`endif
+	 // Bus repeaters
+	 input  [BUS_REP_WD-1:0]  ch_in,
+	 output [BUS_REP_WD-1:0] ch_out
+      );
+
+// channel repeater
+
+`ifndef SYNTHESIS
+
+assign ch_out = ch_in;
+
+`else
+
+ genvar i;
+ generate
+	for (i = 0; i < BUS_REP_WD; i = i + 1) begin : u_rp
+       sky130_fd_sc_hd__clkbuf_4 u_buf ( .A(ch_in[i]), .X(ch_out[i]));
+    end
+ endgenerate
+
+`endif
+
+
+endmodule
+
diff --git a/verilog/rtl/bus_rep/bus_rep_north.sv b/verilog/rtl/bus_rep/bus_rep_north.sv
new file mode 100644
index 0000000..bb13510
--- /dev/null
+++ b/verilog/rtl/bus_rep/bus_rep_north.sv
@@ -0,0 +1,52 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//               Bus Repater                                        //
+//////////////////////////////////////////////////////////////////////
+module bus_rep_north #(
+	parameter BUS_REP_WD = 7
+        ) (
+`ifdef USE_POWER_PINS
+         input logic            vccd1,    // User area 1 1.8V supply
+         input logic            vssd1,    // User area 1 digital ground
+`endif
+	 // Bus repeaters
+	 input  [BUS_REP_WD-1:0]  ch_in,
+	 output [BUS_REP_WD-1:0] ch_out
+      );
+
+// channel repeater
+
+`ifndef SYNTHESIS
+
+assign ch_out = ch_in;
+
+`else
+
+ genvar i;
+ generate
+	for (i = 0; i < BUS_REP_WD; i = i + 1) begin : u_rp
+       sky130_fd_sc_hd__clkbuf_4 u_buf ( .A(ch_in[i]), .X(ch_out[i]));
+    end
+ endgenerate
+
+`endif
+
+
+endmodule
+
diff --git a/verilog/rtl/bus_rep/bus_rep_south.sv b/verilog/rtl/bus_rep/bus_rep_south.sv
new file mode 100644
index 0000000..ea877be
--- /dev/null
+++ b/verilog/rtl/bus_rep/bus_rep_south.sv
@@ -0,0 +1,52 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//               Bus Repater                                        //
+//////////////////////////////////////////////////////////////////////
+module bus_rep_south #(
+	parameter BUS_REP_WD = 7
+        ) (
+`ifdef USE_POWER_PINS
+         input logic            vccd1,    // User area 1 1.8V supply
+         input logic            vssd1,    // User area 1 digital ground
+`endif
+	 // Bus repeaters
+	 input  [BUS_REP_WD-1:0]  ch_in,
+	 output [BUS_REP_WD-1:0] ch_out
+      );
+
+// channel repeater
+
+`ifndef SYNTHESIS
+
+assign ch_out = ch_in;
+
+`else
+
+ genvar i;
+ generate
+	for (i = 0; i < BUS_REP_WD; i = i + 1) begin : u_rp
+       sky130_fd_sc_hd__clkbuf_4 u_buf ( .A(ch_in[i]), .X(ch_out[i]));
+    end
+ endgenerate
+
+`endif
+
+
+endmodule
+
diff --git a/verilog/rtl/bus_rep/bus_rep_west.sv b/verilog/rtl/bus_rep/bus_rep_west.sv
new file mode 100644
index 0000000..f02c930
--- /dev/null
+++ b/verilog/rtl/bus_rep/bus_rep_west.sv
@@ -0,0 +1,52 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//               Bus Repater                                        //
+//////////////////////////////////////////////////////////////////////
+module bus_rep_west #(
+	parameter BUS_REP_WD = 7
+        ) (
+`ifdef USE_POWER_PINS
+         input logic            vccd1,    // User area 1 1.8V supply
+         input logic            vssd1,    // User area 1 digital ground
+`endif
+	 // Bus repeaters
+	 input  [BUS_REP_WD-1:0]  ch_in,
+	 output [BUS_REP_WD-1:0] ch_out
+      );
+
+// channel repeater
+
+`ifndef SYNTHESIS
+
+assign ch_out = ch_in;
+
+`else
+
+ genvar i;
+ generate
+	for (i = 0; i < BUS_REP_WD; i = i + 1) begin : u_rp
+       sky130_fd_sc_hd__clkbuf_4 u_buf ( .A(ch_in[i]), .X(ch_out[i]));
+    end
+ endgenerate
+
+`endif
+
+
+endmodule
+
diff --git a/verilog/rtl/bus_repeater.sv b/verilog/rtl/bus_repeater.sv
new file mode 100644
index 0000000..8312ed8
--- /dev/null
+++ b/verilog/rtl/bus_repeater.sv
@@ -0,0 +1,859 @@
+/*********************************************
+  Bus Repeater SOUTH
+**********************************************/
+wire          wb_clk_i_rp;
+wire          wb_rst_i_rp ;      
+wire          wbs_cyc_i_rp ;     
+wire          wbs_stb_i_rp ;     
+wire          wbs_we_i_rp  ;    
+wire   [3:0]  wbs_sel_i_rp;      
+wire   [31:0] wbs_adr_i_rp; 
+wire   [31:0] wbs_dat_i_rp; 
+
+wire          wbs_ack_int_o ;     
+wire   [31:0] wbs_dat_int_o;
+
+wire   [17:0] la_data_in_rp;
+
+wire [252:0] ch_in_south = {
+                    user_clock2,
+                    la_data_out_int[127],
+                    la_data_out_int[126],
+                    la_data_out_int[125],
+                    la_data_out_int[124],
+                    la_data_out_int[123],
+                    la_data_out_int[122],
+                    la_data_out_int[121],
+                    la_data_out_int[120],
+                    la_data_out_int[119],
+                    la_data_out_int[118],
+                    la_data_out_int[117],
+                    la_data_out_int[116],
+                    la_data_out_int[115],
+                    la_data_out_int[114],
+                    la_data_out_int[113],
+                    la_data_out_int[112],
+                    la_data_out_int[111],
+                    la_data_out_int[110],
+                    la_data_out_int[109],
+                    la_data_out_int[108],
+                    la_data_out_int[107],
+                    la_data_out_int[106],
+                    la_data_out_int[105],
+                    la_data_out_int[104],
+                    la_data_out_int[103],
+                    la_data_out_int[102],
+                    la_data_out_int[101],
+                    la_data_out_int[100],
+                    la_data_out_int[99],
+                    la_data_out_int[98],
+                    la_data_out_int[97],
+                    la_data_out_int[96],
+                    la_data_out_int[95],
+                    la_data_out_int[94],
+                    la_data_out_int[93],
+                    la_data_out_int[92],
+                    la_data_out_int[91],
+                    la_data_out_int[90],
+                    la_data_out_int[89],
+                    la_data_out_int[88],
+                    la_data_out_int[87],
+                    la_data_out_int[86],
+                    la_data_out_int[85],
+                    la_data_out_int[84],
+                    la_data_out_int[83],
+                    la_data_out_int[82],
+                    la_data_out_int[81],
+                    la_data_out_int[80],
+                    la_data_out_int[79],
+                    la_data_out_int[78],
+                    la_data_out_int[77],
+                    la_data_out_int[76],
+                    la_data_out_int[75],
+                    la_data_out_int[74],
+                    la_data_out_int[73],
+                    la_data_out_int[72],
+                    la_data_out_int[71],
+                    la_data_out_int[70],
+                    la_data_out_int[69],
+                    la_data_out_int[68],
+                    la_data_out_int[67],
+                    la_data_out_int[66],
+                    la_data_out_int[65],
+                    la_data_out_int[64],
+                    la_data_out_int[63],
+                    la_data_out_int[62],
+                    la_data_out_int[61],
+                    la_data_out_int[60],
+                    la_data_out_int[59],
+                    la_data_out_int[58],
+                    la_data_out_int[57],
+                    la_data_out_int[56],
+                    la_data_out_int[55],
+                    la_data_out_int[54],
+                    la_data_out_int[53],
+                    la_data_out_int[52],
+                    la_data_out_int[51],
+                    la_data_out_int[50],
+                    la_data_out_int[49],
+                    la_data_out_int[48],
+                    la_data_out_int[47],
+                    la_data_out_int[46],
+                    la_data_out_int[45],
+                    la_data_out_int[44],
+                    la_data_out_int[43],
+                    la_data_out_int[42],
+                    la_data_out_int[41],
+                    la_data_out_int[40],
+                    la_data_out_int[39],
+                    la_data_out_int[38],
+                    la_data_out_int[37],
+                    la_data_out_int[36],
+                    la_data_out_int[35],
+                    la_data_out_int[34],
+                    la_data_out_int[33],
+                    la_data_out_int[32],
+                    la_data_out_int[31],
+                    la_data_out_int[30],
+                    la_data_out_int[29],
+                    la_data_out_int[28],
+                    la_data_out_int[27],
+                    la_data_out_int[26],
+                    la_data_out_int[25],
+                    la_data_out_int[24],
+                    la_data_out_int[23],
+                    la_data_out_int[22],
+                    la_data_out_int[21],
+                    la_data_out_int[20],
+                    la_data_out_int[19],
+                    la_data_out_int[18],
+                    la_data_out_int[17],
+                    la_data_in[17],
+                    la_data_out_int[16],
+                    la_data_in[16],
+                    la_data_out_int[15],
+                    la_data_in[15],
+                    la_data_out_int[14],
+                    la_data_in[14],
+                    la_data_out_int[13],
+                    la_data_in[13],
+                    la_data_out_int[12],
+                    la_data_in[12],
+                    la_data_out_int[11],
+                    la_data_in[11],
+                    la_data_out_int[10],
+                    la_data_in[10],
+                    la_data_out_int[9],
+                    la_data_in[9],
+                    la_data_out_int[8],
+                    la_data_in[8],
+                    la_data_out_int[7],
+                    la_data_in[7],
+                    la_data_out_int[6],
+                    la_data_in[6],
+                    la_data_out_int[5],
+                    la_data_in[5],
+                    la_data_out_int[4],
+                    la_data_in[4],
+                    la_data_out_int[3],
+                    la_data_in[3],
+                    la_data_out_int[2],
+                    la_data_in[2],
+                    la_data_out_int[1],
+                    la_data_in[1],
+                    la_data_out_int[0],
+                    la_data_in[0],
+
+                    wbs_dat_int_o[31]  , // 105
+                    wbs_dat_i[31]      ,
+                    wbs_adr_i[31]      ,
+                    wbs_dat_int_o[30]  , 
+                    wbs_dat_i[30]      ,
+                    wbs_adr_i[30]      ,
+                    wbs_dat_int_o[29]  , 
+                    wbs_dat_i[29]      ,
+                    wbs_adr_i[29]      ,
+                    wbs_dat_int_o[28]  , 
+                    wbs_dat_i[28]      ,
+                    wbs_adr_i[28]      ,
+                    wbs_dat_int_o[27]  , 
+                    wbs_dat_i[27]      ,
+                    wbs_adr_i[27]      ,
+                    wbs_dat_int_o[26]  , 
+                    wbs_dat_i[26]      ,
+                    wbs_adr_i[26]      ,
+                    wbs_dat_int_o[25]  , 
+                    wbs_dat_i[25]      ,
+                    wbs_adr_i[25]      ,
+                    wbs_dat_int_o[24]  , 
+                    wbs_dat_i[24]      ,
+                    wbs_adr_i[24]      ,
+                    wbs_dat_int_o[23]  , 
+                    wbs_dat_i[23]      ,
+                    wbs_adr_i[23]      ,
+                    wbs_dat_int_o[22]  , 
+                    wbs_dat_i[22]      ,
+                    wbs_adr_i[22]      ,
+                    wbs_dat_int_o[21]  , 
+                    wbs_dat_i[21]      ,
+                    wbs_adr_i[21]      ,
+                    wbs_dat_int_o[20]  , 
+                    wbs_dat_i[20]      ,
+                    wbs_adr_i[20]      ,
+                    wbs_dat_int_o[19]  , 
+                    wbs_dat_i[19]      ,
+                    wbs_adr_i[19]      ,
+                    wbs_dat_int_o[18]  , 
+                    wbs_dat_i[18]      ,
+                    wbs_adr_i[18]      ,
+                    wbs_dat_int_o[17]  , 
+                    wbs_dat_i[17]      ,
+                    wbs_adr_i[17]      ,
+                    wbs_dat_int_o[16]  , 
+                    wbs_dat_i[16]      ,
+                    wbs_adr_i[16]      ,
+                    wbs_dat_int_o[15]  , 
+                    wbs_dat_i[15]      ,
+                    wbs_adr_i[15]      ,
+                    wbs_dat_int_o[14]  , 
+                    wbs_dat_i[14]      ,
+                    wbs_adr_i[14]      ,
+                    wbs_dat_int_o[13]  , 
+                    wbs_dat_i[13]      ,
+                    wbs_adr_i[13]      ,
+                    wbs_dat_int_o[12]  , 
+                    wbs_dat_i[12]      ,
+                    wbs_adr_i[12]      ,
+                    wbs_dat_int_o[11]  , 
+                    wbs_dat_i[11]      ,
+                    wbs_adr_i[11]      ,
+                    wbs_dat_int_o[10]  , 
+                    wbs_dat_i[10]      ,
+                    wbs_adr_i[10]      ,
+                    wbs_dat_int_o[9]   , 
+                    wbs_dat_i[9]       ,
+                    wbs_adr_i[9]       ,
+                    wbs_dat_int_o[8]   , // 36
+                    wbs_dat_i[8]       ,
+                    wbs_adr_i[8]       ,
+                    wbs_dat_int_o[7]   , // 33
+                    wbs_dat_i[7]       ,
+                    wbs_adr_i[7]       ,
+                    wbs_dat_int_o[6]   , // 30
+                    wbs_dat_i[6]       ,
+                    wbs_adr_i[6]       ,
+                    wbs_dat_int_o[5]   , // 27
+                    wbs_dat_i[5]       ,
+                    wbs_adr_i[5]       ,
+                    wbs_dat_int_o[4]   , // 24
+                    wbs_dat_i[4]       ,
+                    wbs_adr_i[4]       ,
+                    wbs_sel_i[3]       ,
+                    wbs_dat_int_o[3]   , // 20
+                    wbs_dat_i[3]       ,
+                    wbs_adr_i[3]       , 
+                    wbs_sel_i[2]       , 
+                    wbs_dat_int_o[2]   , // 16
+                    wbs_dat_i[2]       ,
+                    wbs_adr_i[2]       ,
+                    wbs_sel_i[1]       ,
+                    wbs_dat_int_o[1]   , // 12
+                    wbs_dat_i[1]       ,
+                    wbs_adr_i[1]       ,
+                    wbs_sel_i[0]       , 
+                    wbs_dat_int_o[0]   , // 8
+                    wbs_dat_i[0]       ,
+                    wbs_adr_i[0]       ,
+                    wbs_we_i           ,
+                    wbs_stb_i          ,
+                    wbs_cyc_i          ,
+                    wbs_ack_int_o      ,  
+                    wb_rst_i           ,  
+                    wb_clk_i           
+            };
+wire [252:0] ch_out_south ;
+assign {
+                    user_clock2_rp  ,
+                    la_data_out[127],
+                    la_data_out[126],
+                    la_data_out[125],
+                    la_data_out[124],
+                    la_data_out[123],
+                    la_data_out[122],
+                    la_data_out[121],
+                    la_data_out[120],
+                    la_data_out[119],
+                    la_data_out[118],
+                    la_data_out[117],
+                    la_data_out[116],
+                    la_data_out[115],
+                    la_data_out[114],
+                    la_data_out[113],
+                    la_data_out[112],
+                    la_data_out[111],
+                    la_data_out[110],
+                    la_data_out[109],
+                    la_data_out[108],
+                    la_data_out[107],
+                    la_data_out[106],
+                    la_data_out[105],
+                    la_data_out[104],
+                    la_data_out[103],
+                    la_data_out[102],
+                    la_data_out[101],
+                    la_data_out[100],
+                    la_data_out[99],
+                    la_data_out[98],
+                    la_data_out[97],
+                    la_data_out[96],
+                    la_data_out[95],
+                    la_data_out[94],
+                    la_data_out[93],
+                    la_data_out[92],
+                    la_data_out[91],
+                    la_data_out[90],
+                    la_data_out[89],
+                    la_data_out[88],
+                    la_data_out[87],
+                    la_data_out[86],
+                    la_data_out[85],
+                    la_data_out[84],
+                    la_data_out[83],
+                    la_data_out[82],
+                    la_data_out[81],
+                    la_data_out[80],
+                    la_data_out[79],
+                    la_data_out[78],
+                    la_data_out[77],
+                    la_data_out[76],
+                    la_data_out[75],
+                    la_data_out[74],
+                    la_data_out[73],
+                    la_data_out[72],
+                    la_data_out[71],
+                    la_data_out[70],
+                    la_data_out[69],
+                    la_data_out[68],
+                    la_data_out[67],
+                    la_data_out[66],
+                    la_data_out[65],
+                    la_data_out[64],
+                    la_data_out[63],
+                    la_data_out[62],
+                    la_data_out[61],
+                    la_data_out[60],
+                    la_data_out[59],
+                    la_data_out[58],
+                    la_data_out[57],
+                    la_data_out[56],
+                    la_data_out[55],
+                    la_data_out[54],
+                    la_data_out[53],
+                    la_data_out[52],
+                    la_data_out[51],
+                    la_data_out[50],
+                    la_data_out[49],
+                    la_data_out[48],
+                    la_data_out[47],
+                    la_data_out[46],
+                    la_data_out[45],
+                    la_data_out[44],
+                    la_data_out[43],
+                    la_data_out[42],
+                    la_data_out[41],
+                    la_data_out[40],
+                    la_data_out[39],
+                    la_data_out[38],
+                    la_data_out[37],
+                    la_data_out[36],
+                    la_data_out[35],
+                    la_data_out[34],
+                    la_data_out[33],
+                    la_data_out[32],
+                    la_data_out[31],
+                    la_data_out[30],
+                    la_data_out[29],
+                    la_data_out[28],
+                    la_data_out[27],
+                    la_data_out[26],
+                    la_data_out[25],
+                    la_data_out[24],
+                    la_data_out[23],
+                    la_data_out[22],
+                    la_data_out[21],
+                    la_data_out[20],
+                    la_data_out[19],
+                    la_data_out[18],
+                    la_data_out[17],
+                    la_data_in_rp[17],
+                    la_data_out[16],
+                    la_data_in_rp[16],
+                    la_data_out[15],
+                    la_data_in_rp[15],
+                    la_data_out[14],
+                    la_data_in_rp[14],
+                    la_data_out[13],
+                    la_data_in_rp[13],
+                    la_data_out[12],
+                    la_data_in_rp[12],
+                    la_data_out[11],
+                    la_data_in_rp[11],
+                    la_data_out[10],
+                    la_data_in_rp[10],
+                    la_data_out[9],
+                    la_data_in_rp[9],
+                    la_data_out[8],
+                    la_data_in_rp[8],
+                    la_data_out[7],
+                    la_data_in_rp[7],
+                    la_data_out[6],
+                    la_data_in_rp[6],
+                    la_data_out[5],
+                    la_data_in_rp[5],
+                    la_data_out[4],
+                    la_data_in_rp[4],
+                    la_data_out[3],
+                    la_data_in_rp[3],
+                    la_data_out[2],
+                    la_data_in_rp[2],
+                    la_data_out[1],
+                    la_data_in_rp[1],
+                    la_data_out[0],
+                    la_data_in_rp[0],
+
+                    wbs_dat_o[31]   , 
+                    wbs_dat_i_rp[31],
+                    wbs_adr_i_rp[31],
+                    wbs_dat_o[30]   , 
+                    wbs_dat_i_rp[30],
+                    wbs_adr_i_rp[30],
+                    wbs_dat_o[29]   , 
+                    wbs_dat_i_rp[29],
+                    wbs_adr_i_rp[29],
+                    wbs_dat_o[28]   , 
+                    wbs_dat_i_rp[28],
+                    wbs_adr_i_rp[28],
+                    wbs_dat_o[27]   , 
+                    wbs_dat_i_rp[27],
+                    wbs_adr_i_rp[27],
+                    wbs_dat_o[26]   , 
+                    wbs_dat_i_rp[26],
+                    wbs_adr_i_rp[26],
+                    wbs_dat_o[25]   , 
+                    wbs_dat_i_rp[25],
+                    wbs_adr_i_rp[25],
+                    wbs_dat_o[24]   , 
+                    wbs_dat_i_rp[24],
+                    wbs_adr_i_rp[24],
+                    wbs_dat_o[23]   , 
+                    wbs_dat_i_rp[23],
+                    wbs_adr_i_rp[23],
+                    wbs_dat_o[22]   , 
+                    wbs_dat_i_rp[22],
+                    wbs_adr_i_rp[22],
+                    wbs_dat_o[21]   , 
+                    wbs_dat_i_rp[21],
+                    wbs_adr_i_rp[21],
+                    wbs_dat_o[20]   , 
+                    wbs_dat_i_rp[20],
+                    wbs_adr_i_rp[20],
+                    wbs_dat_o[19]   , 
+                    wbs_dat_i_rp[19],
+                    wbs_adr_i_rp[19],
+                    wbs_dat_o[18]   , 
+                    wbs_dat_i_rp[18],
+                    wbs_adr_i_rp[18],
+                    wbs_dat_o[17]   , 
+                    wbs_dat_i_rp[17],
+                    wbs_adr_i_rp[17],
+                    wbs_dat_o[16]   , 
+                    wbs_dat_i_rp[16],
+                    wbs_adr_i_rp[16],
+                    wbs_dat_o[15]   , 
+                    wbs_dat_i_rp[15],
+                    wbs_adr_i_rp[15],
+                    wbs_dat_o[14]   , 
+                    wbs_dat_i_rp[14],
+                    wbs_adr_i_rp[14],
+                    wbs_dat_o[13]   , 
+                    wbs_dat_i_rp[13],
+                    wbs_adr_i_rp[13],
+                    wbs_dat_o[12]   , 
+                    wbs_dat_i_rp[12],
+                    wbs_adr_i_rp[12],
+                    wbs_dat_o[11]   , 
+                    wbs_dat_i_rp[11],
+                    wbs_adr_i_rp[11],
+                    wbs_dat_o[10]   , 
+                    wbs_dat_i_rp[10],
+                    wbs_adr_i_rp[10],
+                    wbs_dat_o[9]   , 
+                    wbs_dat_i_rp[9],
+                    wbs_adr_i_rp[9],
+                    wbs_dat_o[8]   , 
+                    wbs_dat_i_rp[8],
+                    wbs_adr_i_rp[8],
+                    wbs_dat_o[7]   , 
+                    wbs_dat_i_rp[7],
+                    wbs_adr_i_rp[7],
+                    wbs_dat_o[6]   , 
+                    wbs_dat_i_rp[6],
+                    wbs_adr_i_rp[6],
+                    wbs_dat_o[5]   , 
+                    wbs_dat_i_rp[5],
+                    wbs_adr_i_rp[5],
+                    wbs_dat_o[4]   , 
+                    wbs_dat_i_rp[4],
+                    wbs_adr_i_rp[4],
+
+                    wbs_sel_i_rp[3]       ,
+                    wbs_dat_o[3]   , 
+                    wbs_dat_i_rp[3]       ,
+                    wbs_adr_i_rp[3]       , 
+                    wbs_sel_i_rp[2]       , 
+                    wbs_dat_o[2]   , 
+                    wbs_dat_i_rp[2]       ,
+                    wbs_adr_i_rp[2]       ,
+                    wbs_sel_i_rp[1]       ,
+                    wbs_dat_o[1]   , 
+                    wbs_dat_i_rp[1]       ,
+                    wbs_adr_i_rp[1]       ,
+                    wbs_sel_i_rp[0]       , 
+                    wbs_dat_o[0]   , 
+                    wbs_dat_i_rp[0]       ,
+                    wbs_adr_i_rp[0]       ,
+                    wbs_we_i_rp           ,
+                    wbs_stb_i_rp          ,
+                    wbs_cyc_i_rp          ,
+                    wbs_ack_o             ,  
+                    wb_rst_i_rp           ,  
+                    wb_clk_i_rp           
+            } = ch_out_south;
+
+bus_rep_south  #(
+`ifndef SYNTHESIS
+.BUS_REP_WD(253)
+`endif
+      ) u_rp_south(
+`ifdef USE_POWER_PINS
+    .vccd1                 (vccd1                  ),
+    .vssd1                 (vssd1                  ),
+`endif
+    .ch_in (ch_in_south),
+    .ch_out (ch_out_south)
+   );
+
+
+/*********************************************
+  Bus Repeater WEST
+**********************************************/
+
+wire [41:0] ch_in_west = {
+                          io_oeb_int[37],
+                          io_out_int[37],
+                          io_in[37],
+                          io_oeb_int[36],
+                          io_out_int[36],
+                          io_in[36],
+                          io_oeb_int[35],
+                          io_out_int[35],
+                          io_in[35],
+                          io_oeb_int[34],
+                          io_out_int[34],
+                          io_in[34],
+                          io_oeb_int[33],
+                          io_out_int[33],
+                          io_in[33],
+                          io_oeb_int[32],
+                          io_out_int[32],
+                          io_in[32],
+                          io_oeb_int[31],
+                          io_out_int[31],
+                          io_in[31],
+                          io_oeb_int[30],
+                          io_out_int[30],
+                          io_in[30],
+                          io_oeb_int[29],
+                          io_out_int[29],
+                          io_in[29],
+                          io_oeb_int[28],
+                          io_out_int[28],
+                          io_in[28],
+                          io_oeb_int[27],
+                          io_out_int[27],
+                          io_in[27],
+                          io_oeb_int[26],
+                          io_out_int[26],
+                          io_in[26],
+                          io_oeb_int[25],
+                          io_out_int[25],
+                          io_in[25],
+                          io_oeb_int[24],
+                          io_out_int[24],
+                          io_in[24]
+                         };
+
+wire [41:0] ch_out_west ;
+assign  {
+                          io_oeb[37],
+                          io_out[37],
+                          io_in_rp[37],
+                          io_oeb[36],
+                          io_out[36],
+                          io_in_rp[36],
+                          io_oeb[35],
+                          io_out[35],
+                          io_in_rp[35],
+                          io_oeb[34],
+                          io_out[34],
+                          io_in_rp[34],
+                          io_oeb[33],
+                          io_out[33],
+                          io_in_rp[33],
+                          io_oeb[32],
+                          io_out[32],
+                          io_in_rp[32],
+                          io_oeb[31],
+                          io_out[31],
+                          io_in_rp[31],
+                          io_oeb[30],
+                          io_out[30],
+                          io_in_rp[30],
+                          io_oeb[29],
+                          io_out[29],
+                          io_in_rp[29],
+                          io_oeb[28],
+                          io_out[28],
+                          io_in_rp[28],
+                          io_oeb[27],
+                          io_out[27],
+                          io_in_rp[27],
+                          io_oeb[26],
+                          io_out[26],
+                          io_in_rp[26],
+                          io_oeb[25],
+                          io_out[25],
+                          io_in_rp[25],
+                          io_oeb[24],
+                          io_out[24],
+                          io_in_rp[24]
+
+         } = ch_out_west;
+
+bus_rep_west  #(
+`ifndef SYNTHESIS
+.BUS_REP_WD(42)
+`endif
+      ) u_rp_west(
+`ifdef USE_POWER_PINS
+    .vccd1                 (vccd1                  ),
+    .vssd1                 (vssd1                  ),
+`endif
+    .ch_in  (ch_in_west),
+    .ch_out (ch_out_west)
+   );
+
+/*********************************************
+  Bus Repeater NORTH
+**********************************************/
+
+wire [26:0] ch_in_north = {
+                            io_in[15],
+                            io_out_int[15],
+                            io_oeb_int[15],
+                            io_in[16],
+                            io_out_int[16],
+                            io_oeb_int[16],
+                            io_in[17],
+                            io_out_int[17],
+                            io_oeb_int[17],
+                            io_in[18],
+                            io_out_int[18],
+                            io_oeb_int[18],
+                            io_in[19],
+                            io_out_int[19],
+                            io_oeb_int[19],
+                            io_in[20],
+                            io_out_int[20],
+                            io_oeb_int[20],
+                            io_in[21],
+                            io_out_int[21],
+                            io_oeb_int[21],
+                            io_in[22],
+                            io_out_int[22],
+                            io_oeb_int[22],
+                            io_in[23],
+                            io_out_int[23],
+                            io_oeb_int[23]
+                          };
+
+
+wire [26:0] ch_out_north ;
+assign  {
+           io_in_rp[15],
+           io_out[15],
+           io_oeb[15],
+           io_in_rp[16],
+           io_out[16],
+           io_oeb[16],
+           io_in_rp[17],
+           io_out[17],
+           io_oeb[17],
+           io_in_rp[18],
+           io_out[18],
+           io_oeb[18],
+           io_in_rp[19],
+           io_out[19],
+           io_oeb[19],
+           io_in_rp[20],
+           io_out[20],
+           io_oeb[20],
+           io_in_rp[21],
+           io_out[21],
+           io_oeb[21],
+           io_in_rp[22],
+           io_out[22],
+           io_oeb[22],
+           io_in_rp[23],
+           io_out[23],
+           io_oeb[23]
+          } = ch_out_north;
+
+bus_rep_north  #(
+`ifndef SYNTHESIS
+.BUS_REP_WD(27)
+`endif
+      ) u_rp_north(
+`ifdef USE_POWER_PINS
+    .vccd1                 (vccd1                  ),
+    .vssd1                 (vssd1                  ),
+`endif
+    .ch_in (ch_in_north),
+    .ch_out (ch_out_north)
+   );
+
+/*********************************************
+  Bus Repeater EAST
+**********************************************/
+
+wire [44:0] ch_in_east = {
+                            io_in[0],
+                            io_out_int[0],
+                            io_oeb_int[0],
+                            io_in[1],
+                            io_out_int[1],
+                            io_oeb_int[1],
+                            io_in[2],
+                            io_out_int[2],
+                            io_oeb_int[2],
+                            io_in[3],
+                            io_out_int[3],
+                            io_oeb_int[3],
+                            io_in[4],
+                            io_out_int[4],
+                            io_oeb_int[4],
+                            io_in[5],
+                            io_out_int[5],
+                            io_oeb_int[5],
+                            io_in[6],
+                            io_out_int[6],
+                            io_oeb_int[6],
+                            io_in[7],
+                            io_out_int[7],
+                            io_oeb_int[7],
+                            io_in[8],
+                            io_out_int[8],
+                            io_oeb_int[8],
+                            io_in[9],
+                            io_out_int[9],
+                            io_oeb_int[9],
+                            io_in[10],
+                            io_out_int[10],
+                            io_oeb_int[10],
+                            io_in[11],
+                            io_out_int[11],
+                            io_oeb_int[11],
+                            io_in[12],
+                            io_out_int[12],
+                            io_oeb_int[12],
+                            io_in[13],
+                            io_out_int[13],
+                            io_oeb_int[13],
+                            io_in[14],
+                            io_out_int[14],
+                            io_oeb_int[14]
+                          };
+
+
+wire [44:0] ch_out_east ;
+assign  {
+                            io_in_rp[0],
+                            io_out[0],
+                            io_oeb[0],
+                            io_in_rp[1],
+                            io_out[1],
+                            io_oeb[1],
+                            io_in_rp[2],
+                            io_out[2],
+                            io_oeb[2],
+                            io_in_rp[3],
+                            io_out[3],
+                            io_oeb[3],
+                            io_in_rp[4],
+                            io_out[4],
+                            io_oeb[4],
+                            io_in_rp[5],
+                            io_out[5],
+                            io_oeb[5],
+                            io_in_rp[6],
+                            io_out[6],
+                            io_oeb[6],
+                            io_in_rp[7],
+                            io_out[7],
+                            io_oeb[7],
+                            io_in_rp[8],
+                            io_out[8],
+                            io_oeb[8],
+                            io_in_rp[9],
+                            io_out[9],
+                            io_oeb[9],
+                            io_in_rp[10],
+                            io_out[10],
+                            io_oeb[10],
+                            io_in_rp[11],
+                            io_out[11],
+                            io_oeb[11],
+                            io_in_rp[12],
+                            io_out[12],
+                            io_oeb[12],
+                            io_in_rp[13],
+                            io_out[13],
+                            io_oeb[13],
+                            io_in_rp[14],
+                            io_out[14],
+                            io_oeb[14]
+        } = ch_out_east;
+
+bus_rep_east  #(
+`ifndef SYNTHESIS
+.BUS_REP_WD(45)
+`endif
+      ) u_rp_east(
+`ifdef USE_POWER_PINS
+    .vccd1                 (vccd1                  ),
+    .vssd1                 (vssd1                  ),
+`endif
+    .ch_in (ch_in_east),
+    .ch_out (ch_out_east)
+   );
+
+//---------------------------------------------------------
+// No Repeated added for these ports yet
+//---------------------------------------------------------
+//assign io_oeb[14:0]    = io_oeb_int[14:0];
+//assign io_out[14:0]    = io_out_int[14:0];
+//assign io_in_rp[14:0]  = io_in[14:0];
+
+//assign io_oeb[37:24]    = io_oeb_int[37:24];
+//assign io_out[37:24]    = io_out_int[37:24];
+//assign io_in_rp[37:24]  = io_in[37:24];
diff --git a/verilog/rtl/i2cm/src/core/i2cm_top.v b/verilog/rtl/i2cm/src/core/i2cm_top.v
index 2fea533..d929ec5 100755
--- a/verilog/rtl/i2cm/src/core/i2cm_top.v
+++ b/verilog/rtl/i2cm/src/core/i2cm_top.v
@@ -129,6 +129,17 @@
 	wire i2c_al;      // i2c bus arbitration lost
 	reg  al;          // status register arbitration lost bit
 
+//###################################
+// Application Reset Synchronization
+//###################################
+wire aresetn_ss;
+reset_sync  u_app_rst (
+	      .scan_mode  (1'b0           ),
+          .dclk       (wb_clk_i       ), // Destination clock domain
+	      .arst_n     (aresetn        ), // active low async reset
+          .srst_n     (aresetn_ss     )
+          );
+
 	//
 	// module body
 	//
@@ -157,8 +168,8 @@
 	end
 
 	// generate registers
-	always @(posedge wb_clk_i or negedge aresetn)
-	  if (!aresetn)
+	always @(posedge wb_clk_i or negedge aresetn_ss)
+	  if (!aresetn_ss)
 	    begin
 	        prer <= #1 16'hffff;
 	        ctr  <= #1  8'h0;
@@ -181,8 +192,8 @@
 	      endcase
 
 	// generate command register (special case)
-	always @(posedge wb_clk_i or negedge aresetn)
-	  if (!aresetn)
+	always @(posedge wb_clk_i or negedge aresetn_ss)
+	  if (!aresetn_ss)
 	    cr <= #1 8'h0;
 	  else if (!sresetn)
 	    cr <= #1 8'h0;
@@ -217,7 +228,7 @@
 	i2cm_byte_ctrl u_byte_ctrl (
 		.clk          ( wb_clk_i     ),
 		.sresetn      ( sresetn      ),
-		.aresetn      ( aresetn      ),
+		.aresetn      ( aresetn_ss   ),
 		.ena          ( core_en      ),
 		.clk_cnt      ( prer         ),
 		.start        ( sta          ),
@@ -241,8 +252,8 @@
 	);
 
 	// status register block + interrupt request signal
-	always @(posedge wb_clk_i or negedge aresetn)
-	  if (!aresetn)
+	always @(posedge wb_clk_i or negedge aresetn_ss)
+	  if (!aresetn_ss)
 	    begin
 	        al       <= #1 1'b0;
 	        rxack    <= #1 1'b0;
@@ -265,8 +276,8 @@
 	    end
 
 	// generate interrupt request signals
-	always @(posedge wb_clk_i or negedge aresetn)
-	  if (!aresetn)
+	always @(posedge wb_clk_i or negedge aresetn_ss)
+	  if (!aresetn_ss)
 	    wb_inta_o <= #1 1'b0;
 	  else if (!sresetn)
 	    wb_inta_o <= #1 1'b0;
diff --git a/verilog/rtl/sspim/src/sspim_top.sv b/verilog/rtl/sspim/src/sspim_top.sv
index 97a3cae..fbd5144 100755
--- a/verilog/rtl/sspim/src/sspim_top.sv
+++ b/verilog/rtl/sspim/src/sspim_top.sv
@@ -139,10 +139,23 @@
 logic                cs_int_n                      ;
 logic                load_byte                     ;
 
+
+//###################################
+// Application Reset Synchronization
+//###################################
+wire reset_ssn;
+reset_sync  u_app_rst (
+	      .scan_mode  (1'b0           ),
+          .dclk       (clk            ), // Destination clock domain
+	      .arst_n     (reset_n        ), // active low async reset
+          .srst_n     (reset_ssn      )
+          );
+
+
 sspim_if  u_spi_if
           (
           . clk                         (clk                          ), 
-          . reset_n                     (reset_n                      ),
+          . reset_n                     (reset_ssn                    ),
 
           // cfg
           . cfg_bit_order               (cfg_bit_order                ),
@@ -170,7 +183,7 @@
 sspim_clkgen u_clkgen
        ( 
           . clk                         (clk                          ), 
-          . reset_n                     (reset_n                      ),
+          . reset_n                     (reset_ssn                    ),
 
           // cfg
           . cfg_cpol                    (cfg_cpol                     ),    
@@ -192,7 +205,7 @@
 sspim_ctl  u_spi_ctrl
        ( 
           . clk                         (clk                          ),
-          . reset_n                     (reset_n                      ),
+          . reset_n                     (reset_ssn                    ),
 
           // cfg
           . cfg_cpol                    (cfg_cpol                     ),    
@@ -222,7 +235,7 @@
 sspim_cfg u_cfg (
 
           . mclk                        (clk                          ),
-          . reset_n                     (reset_n                      ),
+          . reset_n                     (reset_ssn                    ),
 
         // Reg Bus Interface Signal
           . reg_cs                      (reg_cs                       ),
diff --git a/verilog/rtl/user_params.svh b/verilog/rtl/user_params.svh
index 3b11f4f..9aebae3 100644
--- a/verilog/rtl/user_params.svh
+++ b/verilog/rtl/user_params.svh
@@ -4,11 +4,11 @@
 // ASCI Representation of RISC = 32'h8273_8343
 parameter CHIP_SIGNATURE = 32'h8273_8343;
 // Software Reg-1, Release date: <DAY><MONTH><YEAR>
-parameter CHIP_RELEASE_DATE = 32'h2811_2022;
+parameter CHIP_RELEASE_DATE = 32'h0412_2022;
 // Software Reg-2: Poject Revison 5.1 = 0005200
-parameter CHIP_REVISION   = 32'h0006_1000;
+parameter CHIP_REVISION   = 32'h0006_2000;
 
-parameter CLK_SKEW1_RESET_VAL = 32'b0000_0000_0100_1000_1000_1110_1000_0100;
+parameter CLK_SKEW1_RESET_VAL = 32'b0000_0000_0100_0111_1000_1110_1000_0100;
 parameter CLK_SKEW2_RESET_VAL = 32'b1000_1000_1000_1000_1000_1000_0111_1110;
 
 parameter PSTRAP_DEFAULT_VALUE = 15'b000_0011_1010_0000;
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index fc2e8b8..926f6f4 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -293,6 +293,9 @@
 ////    6.1  Nov 28, 2022, Dinesh A                               ////
 ////        Power Hook up connectivity issue for                  ////
 ////        aes,fpu,bus repeater is fixed                         ////
+////    6.2  Dec 4, 2022, Dinesh A                                ////
+////         Bus repeater north/south/east/west added for better  ////
+////         global buffering                                     ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
 //// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
@@ -875,7 +878,7 @@
 assign       cfg_ccska_aes          = cfg_clk_skew_ctrl2[27:24];
 assign       cfg_ccska_fpu          = cfg_clk_skew_ctrl2[31:28];
 
-assign la_data_out[127:0]    = {pinmux_debug,spi_debug,riscv_debug};
+wire [127:0] la_data_out_int    = {pinmux_debug,spi_debug,riscv_debug};
 
 wire   int_pll_clock       = pll_clk_out[0];
 
@@ -889,8 +892,15 @@
 wire       cpu_clk_rp_fpu    = cpu_clk_rp[7];
 wire       cpu_clk_rp_pinmux = cpu_clk_rp[8];
 
+//----------------------------------------------------------
+// Bus Repeater Initiatiation
+//----------------------------------------------------------
+wire  [37:0]                io_in_rp           ;
+wire  [37:0]                io_out_int         ;
+wire  [37:0]                io_oeb_int         ;
+wire                        user_clock2_rp     ;
 
-
+`include "bus_repeater.sv"
 
 /***********************************************
  Wishbone HOST
@@ -901,8 +911,8 @@
           .vccd1                   (vccd1                   ),// User area 1 1.8V supply
           .vssd1                   (vssd1                   ),// User area 1 digital ground
 `endif
-          .user_clock1             (wb_clk_i                ),
-          .user_clock2             (user_clock2             ),
+          .user_clock1             (wb_clk_i_rp             ),
+          .user_clock2             (user_clock2_rp          ),
           .int_pll_clock           (int_pll_clock           ),
 
           .cpu_clk                 (cpu_clk                 ),
@@ -921,16 +931,16 @@
           .wbd_pll_rst_n           (wbd_pll_rst_n           ),
 
     // Master Port
-          .wbm_rst_i               (wb_rst_i                ),  
-          .wbm_clk_i               (wb_clk_i                ),  
-          .wbm_cyc_i               (wbs_cyc_i               ),  
-          .wbm_stb_i               (wbs_stb_i               ),  
-          .wbm_adr_i               (wbs_adr_i               ),  
-          .wbm_we_i                (wbs_we_i                ),  
-          .wbm_dat_i               (wbs_dat_i               ),  
-          .wbm_sel_i               (wbs_sel_i               ),  
-          .wbm_dat_o               (wbs_dat_o               ),  
-          .wbm_ack_o               (wbs_ack_o               ),  
+          .wbm_rst_i               (wb_rst_i_rp             ),  
+          .wbm_clk_i               (wb_clk_i_rp             ),  
+          .wbm_cyc_i               (wbs_cyc_i_rp            ),  
+          .wbm_stb_i               (wbs_stb_i_rp            ),  
+          .wbm_adr_i               (wbs_adr_i_rp            ),  
+          .wbm_we_i                (wbs_we_i_rp             ),  
+          .wbm_dat_i               (wbs_dat_i_rp            ),  
+          .wbm_sel_i               (wbs_sel_i_rp            ),  
+          .wbm_dat_o               (wbs_dat_int_o           ),  
+          .wbm_ack_o               (wbs_ack_int_o           ),  
           .wbm_err_o               (                        ),  
 
     // Clock Skeq Adjust
@@ -954,7 +964,7 @@
           .cfg_clk_skew_ctrl1      (cfg_clk_skew_ctrl1      ),
           .cfg_clk_skew_ctrl2      (cfg_clk_skew_ctrl2      ),
 
-          .la_data_in              (la_data_in[17:0]        ),
+          .la_data_in              (la_data_in_rp[17:0]     ),
 
           .uartm_rxd               (uartm_rxd               ),
           .uartm_txd               (uartm_txd               ),
@@ -1611,8 +1621,8 @@
           .strap_sticky            (strap_sticky            ),
 	      .strap_uartm             (strap_uartm             ),
 
-          .user_clock1             (wb_clk_i                ),
-          .user_clock2             (user_clock2             ),
+          .user_clock1             (wb_clk_i_rp             ),
+          .user_clock2             (user_clock2_rp          ),
           .int_pll_clock           (int_pll_clock           ),
           .xtal_clk                (xtal_clk                ),
           .cpu_clk                 (cpu_clk_rp_pinmux       ),
@@ -1651,9 +1661,9 @@
           .i2cm_intr               (i2cm_intr_o             ),
 
        // Digital IO
-          .digital_io_out          (io_out                  ),
-          .digital_io_oen          (io_oeb                  ),
-          .digital_io_in           (io_in                   ),
+          .digital_io_out          (io_out_int              ),
+          .digital_io_oen          (io_oeb_int              ),
+          .digital_io_in           (io_in_rp                ),
 
        // SFLASH I/F
           .sflash_sck              (sflash_sck              ),
diff --git a/verilog/rtl/wb_interconnect/src/wb_arb.sv b/verilog/rtl/wb_interconnect/src/wb_arb.sv
index a67047b..5c4d50c 100644
--- a/verilog/rtl/wb_interconnect/src/wb_arb.sv
+++ b/verilog/rtl/wb_interconnect/src/wb_arb.sv
@@ -114,15 +114,15 @@
          grant0:
       	// if this req is dropped or next is asserted, check for other req's
       	if(!req[0] ) begin
-      		if(req[1])	next_state = grant1;
+      		if(req[1])	    next_state = grant1;
       		else if(req[2])	next_state = grant2;
       		else if(req[3])	next_state = grant3;
       	end
          grant1:
       	// if this req is dropped or next is asserted, check for other req's
       	if(!req[1] ) begin
-      		if(req[2])	next_state = grant2;
-      		if(req[3])	next_state = grant3;
+      		if(req[2])	    next_state = grant2;
+      		if(req[3])	    next_state = grant3;
       		else if(req[0])	next_state = grant0;
       	end
          grant2:
diff --git a/verilog/rtl/wb_interconnect/src/wb_slave_port.sv b/verilog/rtl/wb_interconnect/src/wb_slave_port.sv
index bc70ea2..4c5196b 100644
--- a/verilog/rtl/wb_interconnect/src/wb_slave_port.sv
+++ b/verilog/rtl/wb_interconnect/src/wb_slave_port.sv
@@ -238,10 +238,10 @@
 // Generate Multiplexed Master Interface based on grant
 always_comb begin
      case(gnt)
-        3'h0:	   m_bus_wr = m0_wb_wr;
-        3'h1:	   m_bus_wr = m1_wb_wr;
-        3'h2:	   m_bus_wr = m2_wb_wr;
-        3'h3:	   m_bus_wr = m3_wb_wr;
+        2'h0:	   m_bus_wr = m0_wb_wr;
+        2'h1:	   m_bus_wr = m1_wb_wr;
+        2'h2:	   m_bus_wr = m2_wb_wr;
+        2'h3:	   m_bus_wr = m3_wb_wr;
         default:   m_bus_wr = m0_wb_wr;
      endcase			
 end