2022-12-03 15:29:55 - [INFO] - {{Project Git Info}} Repository: https://github.com/dineshannayya/riscduino_dcore.git | Branch: main | Commit: ddec3fbfabd8cef36812a3f9e833e94adfc47f23
2022-12-03 15:29:55 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: riscduino-dcore_d4_
2022-12-03 15:29:58 - [INFO] - {{Project Type Info}} digital
2022-12-03 15:29:59 - [INFO] - {{Project GDS Info}} user_project_wrapper: 6827dd3ff4694632747e41f2c2ffe4f5e28f5dbf
2022-12-03 15:29:59 - [INFO] - {{Tools Info}} KLayout: v0.27.12 | Magic: v8.3.340
2022-12-03 15:29:59 - [INFO] - {{PDKs Info}} SKY130A: f70d8ca46961ff92719d8870a18a076370b85f6c | Open PDKs: 0059588eebfc704681dc2368bd1d33d96281d10f
2022-12-03 15:29:59 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/logs'
2022-12-03 15:29:59 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, GPIO-Defines, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
2022-12-03 15:29:59 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 14: License
2022-12-03 15:30:00 - [INFO] - An approved LICENSE (Apache-2.0) was found in riscduino-dcore_d4_.
2022-12-03 15:30:00 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
2022-12-03 15:30:01 - [INFO] - An approved LICENSE (Apache-2.0) was found in riscduino-dcore_d4_.
2022-12-03 15:30:01 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
2022-12-03 15:30:01 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino-dcore_d4_/verilog/dv/common/bfm/usb_device/core/usb1d_ctrl.v): 'utf-8' codec can't decode byte 0x96 in position 5130: invalid start byte
2022-12-03 15:30:01 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino-dcore_d4_/verilog/dv/common/model/mt48lc8m8a2.v): 'utf-8' codec can't decode byte 0xa9 in position 1830: invalid start byte
2022-12-03 15:30:01 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 422 non-compliant file(s) with the SPDX Standard.
2022-12-03 15:30:01 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['riscduino-dcore_d4_/run_regress', 'riscduino-dcore_d4_/deps/timing-scripts/timing.mk', 'riscduino-dcore_d4_/deps/timing-scripts/env/caravel_spef_mapping-mpw2-calibre.tcl', 'riscduino-dcore_d4_/deps/timing-scripts/env/caravel_spef_mapping-mpw2.tcl', 'riscduino-dcore_d4_/deps/timing-scripts/env/caravel_spef_mapping-mpw5-calibre.tcl', 'riscduino-dcore_d4_/deps/timing-scripts/env/caravel_spef_mapping-mpw7.tcl', 'riscduino-dcore_d4_/deps/timing-scripts/env/caravel_spef_mapping.tcl', 'riscduino-dcore_d4_/deps/timing-scripts/env/common.tcl', 'riscduino-dcore_d4_/deps/timing-scripts/env/f.tcl', 'riscduino-dcore_d4_/deps/timing-scripts/env/s.tcl', 'riscduino-dcore_d4_/deps/timing-scripts/env/t.tcl', 'riscduino-dcore_d4_/deps/timing-scripts/scripts/compare_reports.py', 'riscduino-dcore_d4_/deps/timing-scripts/scripts/generate_spef_mapping.py', 'riscduino-dcore_d4_/deps/timing-scripts/scripts/get_macros.py', 'riscduino-dcore_d4_/deps/timing-scripts/scripts/pdk_helpers.py']
2022-12-03 15:30:01 - [INFO] - For the full SPDX compliance report check: riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/logs/spdx_compliance_report.log
2022-12-03 15:30:01 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 14: Makefile
2022-12-03 15:30:01 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
2022-12-03 15:30:01 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 14: Default
2022-12-03 15:30:01 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
2022-12-03 15:30:02 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
2022-12-03 15:30:02 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 14: Documentation
2022-12-03 15:30:02 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
2022-12-03 15:30:02 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 14: Consistency
2022-12-03 15:30:11 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in caravel are connected to power
2022-12-03 15:30:11 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravel netlist passed all consistency checks.
2022-12-03 15:30:11 - [INFO] - PORTS CHECK PASSED: Netlist user_project_wrapper ports match the golden wrapper ports
2022-12-03 15:30:11 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_project_wrapper contains at least 1 instances (16 instances). 
2022-12-03 15:30:11 - [INFO] - MODELING CHECK PASSED: Netlist user_project_wrapper is structural.
2022-12-03 15:30:11 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_project_wrapper matches the provided structural netlist.
2022-12-03 15:30:11 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in user_project_wrapper are connected to power
2022-12-03 15:30:11 - [INFO] - PORT TYPES CHECK PASSED: Netlist user_project_wrapper port types match the golden wrapper port types.
2022-12-03 15:30:11 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_project_wrapper netlist passed all consistency checks.
2022-12-03 15:30:11 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
2022-12-03 15:30:11 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 14: GPIO-Defines
2022-12-03 15:30:11 - [INFO] - GPIO-DEFINES: Checking verilog/rtl/user_defines.v, parsing files: ['/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_base.v', 'riscduino-dcore_d4_/verilog/rtl/user_defines.v', '/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_observe.v']
2022-12-03 15:30:13 - [INFO] - GPIO-DEFINES report path: riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/outputs/reports/gpio_defines.report
2022-12-03 15:30:13 - [INFO] - {{GPIO-DEFINES CHECK PASSED}} The user verilog/rtl/user_defines.v is valid.
2022-12-03 15:30:13 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 14: XOR
2022-12-03 15:34:16 - [INFO] - {{XOR CHECK UPDATE}} Total XOR differences: 0, for more details view riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/outputs/user_project_wrapper.xor.gds
2022-12-03 15:34:16 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
2022-12-03 15:34:16 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 14: Magic DRC
2022-12-03 16:12:51 - [INFO] - 0 DRC violations
2022-12-03 16:12:51 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-12-03 16:12:51 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 14: Klayout FEOL
2022-12-03 16:12:51 - [INFO] - in CUSTOM klayout_gds_drc_check
2022-12-03 16:12:51 - [INFO] - run: klayout -b -r /opt/checks/tech-files/sky130A_mr.drc -rd input=riscduino-dcore_d4_/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/outputs/reports/klayout_feol_check.xml -rd feol=true >& riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/logs/klayout_feol_check.log
2022-12-03 16:16:24 - [INFO] - No DRC Violations found
2022-12-03 16:16:24 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-12-03 16:16:24 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 14: Klayout BEOL
2022-12-03 16:16:24 - [INFO] - in CUSTOM klayout_gds_drc_check
2022-12-03 16:16:24 - [INFO] - run: klayout -b -r /opt/checks/tech-files/sky130A_mr.drc -rd input=riscduino-dcore_d4_/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/outputs/reports/klayout_beol_check.xml -rd beol=true >& riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/logs/klayout_beol_check.log
2022-12-03 16:44:17 - [INFO] - No DRC Violations found
2022-12-03 16:44:17 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-12-03 16:44:17 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 14: Klayout Offgrid
2022-12-03 16:44:17 - [INFO] - in CUSTOM klayout_gds_drc_check
2022-12-03 16:44:17 - [INFO] - run: klayout -b -r /opt/checks/tech-files/sky130A_mr.drc -rd input=riscduino-dcore_d4_/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/outputs/reports/klayout_offgrid_check.xml -rd offgrid=true >& riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/logs/klayout_offgrid_check.log
2022-12-03 16:49:42 - [INFO] - No DRC Violations found
2022-12-03 16:49:42 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-12-03 16:49:42 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 14: Klayout Metal Minimum Clear Area Density
2022-12-03 16:49:42 - [INFO] - in CUSTOM klayout_gds_drc_check
2022-12-03 16:49:42 - [INFO] - run: klayout -b -r /opt/checks/drc_checks/klayout/met_min_ca_density.lydrc -rd input=riscduino-dcore_d4_/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/outputs/reports/klayout_met_min_ca_density_check.xml >& riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/logs/klayout_met_min_ca_density_check.log
2022-12-03 16:51:57 - [INFO] - No DRC Violations found
2022-12-03 16:51:57 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-12-03 16:51:57 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 14: Klayout Pin Label Purposes Overlapping Drawing
2022-12-03 16:51:57 - [INFO] - in CUSTOM klayout_gds_drc_check
2022-12-03 16:51:58 - [INFO] - run: klayout -b -r /opt/checks/drc_checks/klayout/pin_label_purposes_overlapping_drawing.rb.drc -rd input=riscduino-dcore_d4_/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml -rd top_cell_name=user_project_wrapper >& riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
2022-12-03 16:52:42 - [INFO] - No DRC Violations found
2022-12-03 16:52:42 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-12-03 16:52:42 - [INFO] - {{STEP UPDATE}} Executing Check 14 of 14: Klayout ZeroArea
2022-12-03 16:52:42 - [INFO] - in CUSTOM klayout_gds_drc_check
2022-12-03 16:52:42 - [INFO] - run: klayout -b -r /opt/checks/drc_checks/klayout/zeroarea.rb.drc -rd input=riscduino-dcore_d4_/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/outputs/reports/klayout_zeroarea_check.xml -rd cleaned_output=riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/outputs/user_project_wrapper_no_zero_areas.gds >& riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/logs/klayout_zeroarea_check.log
2022-12-03 16:53:08 - [INFO] - No DRC Violations found
2022-12-03 16:53:08 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-12-03 16:53:08 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/logs'
2022-12-03 16:53:08 - [INFO] - {{SUCCESS}} All Checks Passed !!!