#BUS_SORT
#MANUAL_PLACE

#W
sram0_clk0                  000  0   2
sram0_csb0
sram0_web0
sram0_addr0\[8\]
sram0_addr0\[7\]
sram0_addr0\[6\]
sram0_addr0\[5\]
sram0_addr0\[4\]
sram0_addr0\[3\]
sram0_addr0\[2\]
sram0_addr0\[1\]
sram0_addr0\[0\]
sram0_wmask0\[3\]
sram0_wmask0\[2\]
sram0_wmask0\[1\]
sram0_wmask0\[0\]
sram0_din0\[31\]
sram0_din0\[30\]
sram0_din0\[29\]
sram0_din0\[28\]
sram0_din0\[27\]
sram0_din0\[26\]
sram0_din0\[25\]
sram0_din0\[24\]
sram0_din0\[23\]
sram0_din0\[22\]
sram0_din0\[21\]
sram0_din0\[20\]
sram0_din0\[19\]
sram0_din0\[18\]
sram0_din0\[17\]
sram0_din0\[16\]
sram0_din0\[15\]
sram0_din0\[14\]
sram0_din0\[13\]
sram0_din0\[12\]
sram0_din0\[11\]
sram0_din0\[10\]
sram0_din0\[9\]
sram0_din0\[8\]
sram0_din0\[7\]
sram0_din0\[6\]
sram0_din0\[5\]
sram0_din0\[4\]
sram0_din0\[3\]
sram0_din0\[2\]
sram0_din0\[1\]
sram0_din0\[0\]
sram0_dout0\[31\]
sram0_dout0\[30\]
sram0_dout0\[29\]
sram0_dout0\[28\]
sram0_dout0\[27\]
sram0_dout0\[26\]
sram0_dout0\[25\]
sram0_dout0\[24\]
sram0_dout0\[23\]
sram0_dout0\[22\]
sram0_dout0\[21\]
sram0_dout0\[20\]
sram0_dout0\[19\]
sram0_dout0\[18\]
sram0_dout0\[17\]
sram0_dout0\[16\]
sram0_dout0\[15\]
sram0_dout0\[14\]
sram0_dout0\[13\]
sram0_dout0\[12\]
sram0_dout0\[11\]
sram0_dout0\[10\]
sram0_dout0\[9\]
sram0_dout0\[8\]
sram0_dout0\[7\]
sram0_dout0\[6\]
sram0_dout0\[5\]
sram0_dout0\[4\]
sram0_dout0\[3\]
sram0_dout0\[2\]
sram0_dout0\[1\]
sram0_dout0\[0\]


sram0_clk1               110  0 2
sram0_csb1
sram0_addr1\[8\]
sram0_addr1\[7\]
sram0_addr1\[6\]
sram0_addr1\[5\]
sram0_addr1\[4\]
sram0_addr1\[3\]
sram0_addr1\[2\]
sram0_addr1\[1\]
sram0_addr1\[0\]
sram0_dout1\[31\]
sram0_dout1\[30\]
sram0_dout1\[29\]
sram0_dout1\[28\]
sram0_dout1\[27\]
sram0_dout1\[26\]
sram0_dout1\[25\]
sram0_dout1\[24\]
sram0_dout1\[23\]
sram0_dout1\[22\]
sram0_dout1\[21\]
sram0_dout1\[20\]
sram0_dout1\[19\]
sram0_dout1\[18\]
sram0_dout1\[17\]
sram0_dout1\[16\]
sram0_dout1\[15\]
sram0_dout1\[14\]
sram0_dout1\[13\]
sram0_dout1\[12\]
sram0_dout1\[11\]
sram0_dout1\[10\]
sram0_dout1\[9\]
sram0_dout1\[8\]
sram0_dout1\[7\]
sram0_dout1\[6\]
sram0_dout1\[5\]
sram0_dout1\[4\]
sram0_dout1\[3\]
sram0_dout1\[2\]
sram0_dout1\[1\]
sram0_dout1\[0\]

core0_uid\[1\]   0200 00 2
core0_uid\[0\]   
core0_imem_req_ack
core0_imem_req
core0_imem_cmd
core0_imem_addr\[31\]
core0_imem_addr\[30\]
core0_imem_addr\[29\]
core0_imem_addr\[28\]
core0_imem_addr\[27\]
core0_imem_addr\[26\]
core0_imem_addr\[25\]
core0_imem_addr\[24\]
core0_imem_addr\[23\]
core0_imem_addr\[22\]
core0_imem_addr\[21\]
core0_imem_addr\[20\]
core0_imem_addr\[19\]
core0_imem_addr\[18\]
core0_imem_addr\[17\]
core0_imem_addr\[16\]
core0_imem_addr\[15\]
core0_imem_addr\[14\]
core0_imem_addr\[13\]
core0_imem_addr\[12\]
core0_imem_addr\[11\]
core0_imem_addr\[10\]
core0_imem_addr\[9\]
core0_imem_addr\[8\]
core0_imem_addr\[7\]
core0_imem_addr\[6\]
core0_imem_addr\[5\]
core0_imem_addr\[4\]
core0_imem_addr\[3\]
core0_imem_addr\[2\]
core0_imem_addr\[1\]
core0_imem_addr\[0\]
core0_imem_bl\[2\]
core0_imem_bl\[1\]
core0_imem_bl\[0\]
core0_imem_rdata\[31\]
core0_imem_rdata\[30\]
core0_imem_rdata\[29\]
core0_imem_rdata\[28\]
core0_imem_rdata\[27\]
core0_imem_rdata\[26\]
core0_imem_rdata\[25\]
core0_imem_rdata\[24\]
core0_imem_rdata\[23\]
core0_imem_rdata\[22\]
core0_imem_rdata\[21\]
core0_imem_rdata\[20\]
core0_imem_rdata\[19\]
core0_imem_rdata\[18\]
core0_imem_rdata\[17\]
core0_imem_rdata\[16\]
core0_imem_rdata\[15\]
core0_imem_rdata\[14\]
core0_imem_rdata\[13\]
core0_imem_rdata\[12\]
core0_imem_rdata\[11\]
core0_imem_rdata\[10\]
core0_imem_rdata\[9\]
core0_imem_rdata\[8\]
core0_imem_rdata\[7\]
core0_imem_rdata\[6\]
core0_imem_rdata\[5\]
core0_imem_rdata\[4\]
core0_imem_rdata\[3\]
core0_imem_rdata\[2\]
core0_imem_rdata\[1\]
core0_imem_rdata\[0\]
core0_imem_resp\[1\]
core0_imem_resp\[0\]

core0_dmem_req_ack   0350 0 2
core0_dmem_req
core0_dmem_cmd
core0_dmem_width\[1\]
core0_dmem_width\[0\]
core0_dmem_addr\[31\]
core0_dmem_addr\[30\]
core0_dmem_addr\[29\]
core0_dmem_addr\[28\]
core0_dmem_addr\[27\]
core0_dmem_addr\[26\]
core0_dmem_addr\[25\]
core0_dmem_addr\[24\]
core0_dmem_addr\[23\]
core0_dmem_addr\[22\]
core0_dmem_addr\[21\]
core0_dmem_addr\[20\]
core0_dmem_addr\[19\]
core0_dmem_addr\[18\]
core0_dmem_addr\[17\]
core0_dmem_addr\[16\]
core0_dmem_addr\[15\]
core0_dmem_addr\[14\]
core0_dmem_addr\[13\]
core0_dmem_addr\[12\]
core0_dmem_addr\[11\]
core0_dmem_addr\[10\]
core0_dmem_addr\[9\]
core0_dmem_addr\[8\]
core0_dmem_addr\[7\]
core0_dmem_addr\[6\]
core0_dmem_addr\[5\]
core0_dmem_addr\[4\]
core0_dmem_addr\[3\]
core0_dmem_addr\[2\]
core0_dmem_addr\[1\]
core0_dmem_addr\[0\]
core0_dmem_wdata\[31\]
core0_dmem_wdata\[30\]
core0_dmem_wdata\[29\]
core0_dmem_wdata\[28\]
core0_dmem_wdata\[27\]
core0_dmem_wdata\[26\]
core0_dmem_wdata\[25\]
core0_dmem_wdata\[24\]
core0_dmem_wdata\[23\]
core0_dmem_wdata\[22\]
core0_dmem_wdata\[21\]
core0_dmem_wdata\[20\]
core0_dmem_wdata\[19\]
core0_dmem_wdata\[18\]
core0_dmem_wdata\[17\]
core0_dmem_wdata\[16\]
core0_dmem_wdata\[15\]
core0_dmem_wdata\[14\]
core0_dmem_wdata\[13\]
core0_dmem_wdata\[12\]
core0_dmem_wdata\[11\]
core0_dmem_wdata\[10\]
core0_dmem_wdata\[9\]
core0_dmem_wdata\[8\]
core0_dmem_wdata\[7\]
core0_dmem_wdata\[6\]
core0_dmem_wdata\[5\]
core0_dmem_wdata\[4\]
core0_dmem_wdata\[3\]
core0_dmem_wdata\[2\]
core0_dmem_wdata\[1\]
core0_dmem_wdata\[0\]
core0_dmem_rdata\[31\]
core0_dmem_rdata\[30\]
core0_dmem_rdata\[29\]
core0_dmem_rdata\[28\]
core0_dmem_rdata\[27\]
core0_dmem_rdata\[26\]
core0_dmem_rdata\[25\]
core0_dmem_rdata\[24\]
core0_dmem_rdata\[23\]
core0_dmem_rdata\[22\]
core0_dmem_rdata\[21\]
core0_dmem_rdata\[20\]
core0_dmem_rdata\[19\]
core0_dmem_rdata\[18\]
core0_dmem_rdata\[17\]
core0_dmem_rdata\[16\]
core0_dmem_rdata\[15\]
core0_dmem_rdata\[14\]
core0_dmem_rdata\[13\]
core0_dmem_rdata\[12\]
core0_dmem_rdata\[11\]
core0_dmem_rdata\[10\]
core0_dmem_rdata\[9\]
core0_dmem_rdata\[8\]
core0_dmem_rdata\[7\]
core0_dmem_rdata\[6\]
core0_dmem_rdata\[5\]
core0_dmem_rdata\[4\]
core0_dmem_rdata\[3\]
core0_dmem_rdata\[2\]
core0_dmem_rdata\[1\]
core0_dmem_rdata\[0\]
core0_dmem_resp\[1\]
core0_dmem_resp\[0\]

core0_debug\[48\]    0500 0 2
core0_debug\[47\]
core0_debug\[46\]
core0_debug\[45\]
core0_debug\[44\]
core0_debug\[43\]
core0_debug\[42\]
core0_debug\[41\]
core0_debug\[40\]
core0_debug\[39\]
core0_debug\[38\]
core0_debug\[37\]
core0_debug\[36\]
core0_debug\[35\]
core0_debug\[34\]
core0_debug\[33\]
core0_debug\[32\]
core0_debug\[31\]
core0_debug\[30\]
core0_debug\[29\]
core0_debug\[28\]
core0_debug\[27\]
core0_debug\[26\]
core0_debug\[25\]
core0_debug\[24\]
core0_debug\[23\]
core0_debug\[22\]
core0_debug\[21\]
core0_debug\[20\]
core0_debug\[19\]
core0_debug\[18\]
core0_debug\[17\]
core0_debug\[16\]
core0_debug\[15\]
core0_debug\[14\]
core0_debug\[13\]
core0_debug\[12\]
core0_debug\[11\]
core0_debug\[10\]
core0_debug\[9\]
core0_debug\[8\]
core0_debug\[7\]
core0_debug\[6\]
core0_debug\[5\]
core0_debug\[4\]
core0_debug\[3\]
core0_debug\[2\]
core0_debug\[1\]
core0_debug\[0\]

core0_timer_irq        0600 0 2
core0_timer_val\[63\]
core0_timer_val\[62\]
core0_timer_val\[61\]
core0_timer_val\[60\]
core0_timer_val\[59\]
core0_timer_val\[58\]
core0_timer_val\[57\]
core0_timer_val\[56\]
core0_timer_val\[55\]
core0_timer_val\[54\]
core0_timer_val\[53\]
core0_timer_val\[52\]
core0_timer_val\[51\]
core0_timer_val\[50\]
core0_timer_val\[49\]
core0_timer_val\[48\]
core0_timer_val\[47\]
core0_timer_val\[46\]
core0_timer_val\[45\]
core0_timer_val\[44\]
core0_timer_val\[43\]
core0_timer_val\[42\]
core0_timer_val\[41\]
core0_timer_val\[40\]
core0_timer_val\[39\]
core0_timer_val\[38\]
core0_timer_val\[37\]
core0_timer_val\[36\]
core0_timer_val\[35\]
core0_timer_val\[34\]
core0_timer_val\[33\]
core0_timer_val\[32\]
core0_timer_val\[31\]
core0_timer_val\[30\]
core0_timer_val\[29\]
core0_timer_val\[28\]
core0_timer_val\[27\]
core0_timer_val\[26\]
core0_timer_val\[25\]
core0_timer_val\[24\]
core0_timer_val\[23\]
core0_timer_val\[22\]
core0_timer_val\[21\]
core0_timer_val\[20\]
core0_timer_val\[19\]
core0_timer_val\[18\]
core0_timer_val\[17\]
core0_timer_val\[16\]
core0_timer_val\[15\]
core0_timer_val\[14\]
core0_timer_val\[13\]
core0_timer_val\[12\]
core0_timer_val\[11\]
core0_timer_val\[10\]
core0_timer_val\[9\]
core0_timer_val\[8\]
core0_timer_val\[7\]
core0_timer_val\[6\]
core0_timer_val\[5\]
core0_timer_val\[4\]
core0_timer_val\[3\]
core0_timer_val\[2\]
core0_timer_val\[1\]
core0_timer_val\[0\]

core0_irq_lines\[31\]
core0_irq_lines\[30\]
core0_irq_lines\[29\]
core0_irq_lines\[28\]
core0_irq_lines\[27\]
core0_irq_lines\[26\]
core0_irq_lines\[25\]
core0_irq_lines\[24\]
core0_irq_lines\[23\]
core0_irq_lines\[22\]
core0_irq_lines\[21\]
core0_irq_lines\[20\]
core0_irq_lines\[19\]
core0_irq_lines\[18\]
core0_irq_lines\[17\]
core0_irq_lines\[16\]
core0_irq_lines\[15\]
core0_irq_lines\[14\]
core0_irq_lines\[13\]
core0_irq_lines\[12\]
core0_irq_lines\[11\]
core0_irq_lines\[10\]
core0_irq_lines\[9\]
core0_irq_lines\[8\]
core0_irq_lines\[7\]
core0_irq_lines\[6\]
core0_irq_lines\[5\]
core0_irq_lines\[4\]
core0_irq_lines\[3\]
core0_irq_lines\[2\]
core0_irq_lines\[1\]
core0_irq_lines\[0\]
core0_irq_soft


#S
core_icache_req_ack           000 0 2
core_icache_req
core_icache_cmd      
core_icache_addr\[31\]     
core_icache_addr\[30\]     
core_icache_addr\[29\]     
core_icache_addr\[28\]     
core_icache_addr\[27\]     
core_icache_addr\[26\]     
core_icache_addr\[25\]     
core_icache_addr\[24\]     
core_icache_addr\[23\]     
core_icache_addr\[22\]     
core_icache_addr\[21\]     
core_icache_addr\[20\]     
core_icache_addr\[19\]     
core_icache_addr\[18\]     
core_icache_addr\[17\]     
core_icache_addr\[16\]     
core_icache_addr\[15\]     
core_icache_addr\[14\]     
core_icache_addr\[13\]     
core_icache_addr\[12\]     
core_icache_addr\[11\]     
core_icache_addr\[10\]     
core_icache_addr\[9\]     
core_icache_addr\[8\]     
core_icache_addr\[7\]     
core_icache_addr\[6\]     
core_icache_addr\[5\]     
core_icache_addr\[4\]     
core_icache_addr\[3\]     
core_icache_addr\[2\]     
core_icache_addr\[1\]     
core_icache_addr\[0\]     
core_icache_bl\[2\]      
core_icache_bl\[1\]      
core_icache_bl\[0\]      
core_icache_width\[1\]    
core_icache_width\[0\]    
core_icache_rdata\[31\]    
core_icache_rdata\[30\]    
core_icache_rdata\[29\]    
core_icache_rdata\[28\]    
core_icache_rdata\[27\]    
core_icache_rdata\[26\]    
core_icache_rdata\[25\]    
core_icache_rdata\[24\]    
core_icache_rdata\[23\]    
core_icache_rdata\[22\]    
core_icache_rdata\[21\]    
core_icache_rdata\[20\]    
core_icache_rdata\[19\]    
core_icache_rdata\[18\]    
core_icache_rdata\[17\]    
core_icache_rdata\[16\]    
core_icache_rdata\[15\]    
core_icache_rdata\[14\]    
core_icache_rdata\[13\]    
core_icache_rdata\[12\]    
core_icache_rdata\[11\]    
core_icache_rdata\[10\]    
core_icache_rdata\[9\]    
core_icache_rdata\[8\]    
core_icache_rdata\[7\]    
core_icache_rdata\[6\]    
core_icache_rdata\[5\]    
core_icache_rdata\[4\]    
core_icache_rdata\[3\]    
core_icache_rdata\[2\]    
core_icache_rdata\[1\]    
core_icache_rdata\[0\]    
core_icache_resp\[1\]     
core_icache_resp\[0\]     


core_dcache_req_ack        100 0 2
core_dcache_req      
core_dcache_cmd      
core_dcache_width\[1\]    
core_dcache_width\[0\]    
core_dcache_addr\[31\]     
core_dcache_addr\[30\]     
core_dcache_addr\[29\]     
core_dcache_addr\[28\]     
core_dcache_addr\[27\]     
core_dcache_addr\[26\]     
core_dcache_addr\[25\]     
core_dcache_addr\[24\]     
core_dcache_addr\[23\]     
core_dcache_addr\[22\]     
core_dcache_addr\[21\]     
core_dcache_addr\[20\]     
core_dcache_addr\[19\]     
core_dcache_addr\[18\]     
core_dcache_addr\[17\]     
core_dcache_addr\[16\]     
core_dcache_addr\[15\]     
core_dcache_addr\[14\]     
core_dcache_addr\[13\]     
core_dcache_addr\[12\]     
core_dcache_addr\[11\]     
core_dcache_addr\[10\]     
core_dcache_addr\[9\]     
core_dcache_addr\[8\]     
core_dcache_addr\[7\]     
core_dcache_addr\[6\]     
core_dcache_addr\[5\]     
core_dcache_addr\[4\]     
core_dcache_addr\[3\]     
core_dcache_addr\[2\]     
core_dcache_addr\[1\]     
core_dcache_addr\[0\]     
core_dcache_wdata\[31\]    
core_dcache_wdata\[30\]    
core_dcache_wdata\[29\]    
core_dcache_wdata\[28\]    
core_dcache_wdata\[27\]    
core_dcache_wdata\[26\]    
core_dcache_wdata\[25\]    
core_dcache_wdata\[24\]    
core_dcache_wdata\[23\]    
core_dcache_wdata\[22\]    
core_dcache_wdata\[21\]    
core_dcache_wdata\[20\]    
core_dcache_wdata\[19\]    
core_dcache_wdata\[18\]    
core_dcache_wdata\[17\]    
core_dcache_wdata\[16\]    
core_dcache_wdata\[15\]    
core_dcache_wdata\[14\]    
core_dcache_wdata\[13\]    
core_dcache_wdata\[12\]    
core_dcache_wdata\[11\]    
core_dcache_wdata\[10\]    
core_dcache_wdata\[9\]    
core_dcache_wdata\[8\]    
core_dcache_wdata\[7\]    
core_dcache_wdata\[6\]    
core_dcache_wdata\[5\]    
core_dcache_wdata\[4\]    
core_dcache_wdata\[3\]    
core_dcache_wdata\[2\]    
core_dcache_wdata\[1\]    
core_dcache_wdata\[0\]    
core_dcache_rdata\[31\]    
core_dcache_rdata\[30\]    
core_dcache_rdata\[29\]    
core_dcache_rdata\[28\]    
core_dcache_rdata\[27\]    
core_dcache_rdata\[26\]    
core_dcache_rdata\[25\]    
core_dcache_rdata\[24\]    
core_dcache_rdata\[23\]    
core_dcache_rdata\[22\]    
core_dcache_rdata\[21\]    
core_dcache_rdata\[20\]    
core_dcache_rdata\[19\]    
core_dcache_rdata\[18\]    
core_dcache_rdata\[17\]    
core_dcache_rdata\[16\]    
core_dcache_rdata\[15\]    
core_dcache_rdata\[14\]    
core_dcache_rdata\[13\]    
core_dcache_rdata\[12\]    
core_dcache_rdata\[11\]    
core_dcache_rdata\[10\]    
core_dcache_rdata\[9\]    
core_dcache_rdata\[8\]    
core_dcache_rdata\[7\]    
core_dcache_rdata\[6\]    
core_dcache_rdata\[5\]    
core_dcache_rdata\[4\]    
core_dcache_rdata\[3\]    
core_dcache_rdata\[2\]    
core_dcache_rdata\[1\]    
core_dcache_rdata\[0\]    
core_dcache_resp\[1\]     
core_dcache_resp\[0\]     

core_dmem_req_ack          0200 0 2
core_dmem_req        
core_dmem_cmd
core_dmem_bl\[2\]        
core_dmem_bl\[1\]        
core_dmem_bl\[0\]        
core_dmem_width\[1\]      
core_dmem_width\[0\]      
core_dmem_addr\[31\]       
core_dmem_addr\[30\]       
core_dmem_addr\[29\]       
core_dmem_addr\[28\]       
core_dmem_addr\[27\]       
core_dmem_addr\[26\]       
core_dmem_addr\[25\]       
core_dmem_addr\[24\]       
core_dmem_addr\[23\]       
core_dmem_addr\[22\]       
core_dmem_addr\[21\]       
core_dmem_addr\[20\]       
core_dmem_addr\[19\]       
core_dmem_addr\[18\]       
core_dmem_addr\[17\]       
core_dmem_addr\[16\]       
core_dmem_addr\[15\]       
core_dmem_addr\[14\]       
core_dmem_addr\[13\]       
core_dmem_addr\[12\]       
core_dmem_addr\[11\]       
core_dmem_addr\[10\]       
core_dmem_addr\[9\]       
core_dmem_addr\[8\]       
core_dmem_addr\[7\]       
core_dmem_addr\[6\]       
core_dmem_addr\[5\]       
core_dmem_addr\[4\]       
core_dmem_addr\[3\]       
core_dmem_addr\[2\]       
core_dmem_addr\[1\]       
core_dmem_addr\[0\]       
core_dmem_wdata\[31\]      
core_dmem_wdata\[30\]      
core_dmem_wdata\[29\]      
core_dmem_wdata\[28\]      
core_dmem_wdata\[27\]      
core_dmem_wdata\[26\]      
core_dmem_wdata\[25\]      
core_dmem_wdata\[24\]      
core_dmem_wdata\[23\]      
core_dmem_wdata\[22\]      
core_dmem_wdata\[21\]      
core_dmem_wdata\[20\]      
core_dmem_wdata\[19\]      
core_dmem_wdata\[18\]      
core_dmem_wdata\[17\]      
core_dmem_wdata\[16\]      
core_dmem_wdata\[15\]      
core_dmem_wdata\[14\]      
core_dmem_wdata\[13\]      
core_dmem_wdata\[12\]      
core_dmem_wdata\[11\]      
core_dmem_wdata\[10\]      
core_dmem_wdata\[9\]      
core_dmem_wdata\[8\]      
core_dmem_wdata\[7\]      
core_dmem_wdata\[6\]      
core_dmem_wdata\[5\]      
core_dmem_wdata\[4\]      
core_dmem_wdata\[3\]      
core_dmem_wdata\[2\]      
core_dmem_wdata\[1\]      
core_dmem_wdata\[0\]      
core_dmem_rdata\[31\]      
core_dmem_rdata\[30\]      
core_dmem_rdata\[29\]      
core_dmem_rdata\[28\]      
core_dmem_rdata\[27\]      
core_dmem_rdata\[26\]      
core_dmem_rdata\[25\]      
core_dmem_rdata\[24\]      
core_dmem_rdata\[23\]      
core_dmem_rdata\[22\]      
core_dmem_rdata\[21\]      
core_dmem_rdata\[20\]      
core_dmem_rdata\[19\]      
core_dmem_rdata\[18\]      
core_dmem_rdata\[17\]      
core_dmem_rdata\[16\]      
core_dmem_rdata\[15\]      
core_dmem_rdata\[14\]      
core_dmem_rdata\[13\]      
core_dmem_rdata\[12\]      
core_dmem_rdata\[11\]      
core_dmem_rdata\[10\]      
core_dmem_rdata\[9\]      
core_dmem_rdata\[8\]      
core_dmem_rdata\[7\]      
core_dmem_rdata\[6\]      
core_dmem_rdata\[5\]      
core_dmem_rdata\[4\]      
core_dmem_rdata\[3\]      
core_dmem_rdata\[2\]      
core_dmem_rdata\[1\]      
core_dmem_rdata\[0\]      
core_dmem_resp\[1\]       
core_dmem_resp\[0\]       

cfg_dcache_force_flush
cfg_sram_lphase\[1\]
cfg_sram_lphase\[0\]

core_debug_sel\[1\]  300 0 2
core_debug_sel\[0\]

riscv_debug\[63\]   
riscv_debug\[62\]
riscv_debug\[61\]
riscv_debug\[60\]
riscv_debug\[59\]
riscv_debug\[58\]
riscv_debug\[57\]
riscv_debug\[56\]
riscv_debug\[55\]
riscv_debug\[54\]
riscv_debug\[53\]
riscv_debug\[52\]
riscv_debug\[51\]
riscv_debug\[50\]
riscv_debug\[49\]
riscv_debug\[48\]
riscv_debug\[47\]
riscv_debug\[46\]
riscv_debug\[45\]
riscv_debug\[44\]
riscv_debug\[43\]
riscv_debug\[42\]
riscv_debug\[41\]
riscv_debug\[40\]
riscv_debug\[39\]
riscv_debug\[38\]
riscv_debug\[37\]
riscv_debug\[36\]
riscv_debug\[35\]
riscv_debug\[34\]
riscv_debug\[33\]
riscv_debug\[32\]
riscv_debug\[31\]
riscv_debug\[30\]
riscv_debug\[29\]
riscv_debug\[28\]
riscv_debug\[27\]
riscv_debug\[26\]
riscv_debug\[25\]
riscv_debug\[24\]
riscv_debug\[23\]
riscv_debug\[22\]
riscv_debug\[21\]
riscv_debug\[20\]
riscv_debug\[19\]
riscv_debug\[18\]
riscv_debug\[17\]
riscv_debug\[16\]
riscv_debug\[15\]
riscv_debug\[14\]
riscv_debug\[13\]
riscv_debug\[12\]
riscv_debug\[11\]
riscv_debug\[10\]
riscv_debug\[9\]
riscv_debug\[8\]
riscv_debug\[7\]
riscv_debug\[6\]
riscv_debug\[5\]
riscv_debug\[4\]
riscv_debug\[3\]
riscv_debug\[2\]
riscv_debug\[1\]
riscv_debug\[0\]

#E
core1_uid\[1\]      0200 00 2
core1_uid\[0\]   
core1_imem_req_ack
core1_imem_req
core1_imem_cmd
core1_imem_addr\[31\]
core1_imem_addr\[30\]
core1_imem_addr\[29\]
core1_imem_addr\[28\]
core1_imem_addr\[27\]
core1_imem_addr\[26\]
core1_imem_addr\[25\]
core1_imem_addr\[24\]
core1_imem_addr\[23\]
core1_imem_addr\[22\]
core1_imem_addr\[21\]
core1_imem_addr\[20\]
core1_imem_addr\[19\]
core1_imem_addr\[18\]
core1_imem_addr\[17\]
core1_imem_addr\[16\]
core1_imem_addr\[15\]
core1_imem_addr\[14\]
core1_imem_addr\[13\]
core1_imem_addr\[12\]
core1_imem_addr\[11\]
core1_imem_addr\[10\]
core1_imem_addr\[9\]
core1_imem_addr\[8\]
core1_imem_addr\[7\]
core1_imem_addr\[6\]
core1_imem_addr\[5\]
core1_imem_addr\[4\]
core1_imem_addr\[3\]
core1_imem_addr\[2\]
core1_imem_addr\[1\]
core1_imem_addr\[0\]
core1_imem_bl\[2\]
core1_imem_bl\[1\]
core1_imem_bl\[0\]
core1_imem_rdata\[31\]
core1_imem_rdata\[30\]
core1_imem_rdata\[29\]
core1_imem_rdata\[28\]
core1_imem_rdata\[27\]
core1_imem_rdata\[26\]
core1_imem_rdata\[25\]
core1_imem_rdata\[24\]
core1_imem_rdata\[23\]
core1_imem_rdata\[22\]
core1_imem_rdata\[21\]
core1_imem_rdata\[20\]
core1_imem_rdata\[19\]
core1_imem_rdata\[18\]
core1_imem_rdata\[17\]
core1_imem_rdata\[16\]
core1_imem_rdata\[15\]
core1_imem_rdata\[14\]
core1_imem_rdata\[13\]
core1_imem_rdata\[12\]
core1_imem_rdata\[11\]
core1_imem_rdata\[10\]
core1_imem_rdata\[9\]
core1_imem_rdata\[8\]
core1_imem_rdata\[7\]
core1_imem_rdata\[6\]
core1_imem_rdata\[5\]
core1_imem_rdata\[4\]
core1_imem_rdata\[3\]
core1_imem_rdata\[2\]
core1_imem_rdata\[1\]
core1_imem_rdata\[0\]
core1_imem_resp\[1\]
core1_imem_resp\[0\]

core1_dmem_req_ack   0350 0 2
core1_dmem_req
core1_dmem_cmd
core1_dmem_width\[1\]
core1_dmem_width\[0\]
core1_dmem_addr\[31\]
core1_dmem_addr\[30\]
core1_dmem_addr\[29\]
core1_dmem_addr\[28\]
core1_dmem_addr\[27\]
core1_dmem_addr\[26\]
core1_dmem_addr\[25\]
core1_dmem_addr\[24\]
core1_dmem_addr\[23\]
core1_dmem_addr\[22\]
core1_dmem_addr\[21\]
core1_dmem_addr\[20\]
core1_dmem_addr\[19\]
core1_dmem_addr\[18\]
core1_dmem_addr\[17\]
core1_dmem_addr\[16\]
core1_dmem_addr\[15\]
core1_dmem_addr\[14\]
core1_dmem_addr\[13\]
core1_dmem_addr\[12\]
core1_dmem_addr\[11\]
core1_dmem_addr\[10\]
core1_dmem_addr\[9\]
core1_dmem_addr\[8\]
core1_dmem_addr\[7\]
core1_dmem_addr\[6\]
core1_dmem_addr\[5\]
core1_dmem_addr\[4\]
core1_dmem_addr\[3\]
core1_dmem_addr\[2\]
core1_dmem_addr\[1\]
core1_dmem_addr\[0\]
core1_dmem_wdata\[31\]
core1_dmem_wdata\[30\]
core1_dmem_wdata\[29\]
core1_dmem_wdata\[28\]
core1_dmem_wdata\[27\]
core1_dmem_wdata\[26\]
core1_dmem_wdata\[25\]
core1_dmem_wdata\[24\]
core1_dmem_wdata\[23\]
core1_dmem_wdata\[22\]
core1_dmem_wdata\[21\]
core1_dmem_wdata\[20\]
core1_dmem_wdata\[19\]
core1_dmem_wdata\[18\]
core1_dmem_wdata\[17\]
core1_dmem_wdata\[16\]
core1_dmem_wdata\[15\]
core1_dmem_wdata\[14\]
core1_dmem_wdata\[13\]
core1_dmem_wdata\[12\]
core1_dmem_wdata\[11\]
core1_dmem_wdata\[10\]
core1_dmem_wdata\[9\]
core1_dmem_wdata\[8\]
core1_dmem_wdata\[7\]
core1_dmem_wdata\[6\]
core1_dmem_wdata\[5\]
core1_dmem_wdata\[4\]
core1_dmem_wdata\[3\]
core1_dmem_wdata\[2\]
core1_dmem_wdata\[1\]
core1_dmem_wdata\[0\]
core1_dmem_rdata\[31\]
core1_dmem_rdata\[30\]
core1_dmem_rdata\[29\]
core1_dmem_rdata\[28\]
core1_dmem_rdata\[27\]
core1_dmem_rdata\[26\]
core1_dmem_rdata\[25\]
core1_dmem_rdata\[24\]
core1_dmem_rdata\[23\]
core1_dmem_rdata\[22\]
core1_dmem_rdata\[21\]
core1_dmem_rdata\[20\]
core1_dmem_rdata\[19\]
core1_dmem_rdata\[18\]
core1_dmem_rdata\[17\]
core1_dmem_rdata\[16\]
core1_dmem_rdata\[15\]
core1_dmem_rdata\[14\]
core1_dmem_rdata\[13\]
core1_dmem_rdata\[12\]
core1_dmem_rdata\[11\]
core1_dmem_rdata\[10\]
core1_dmem_rdata\[9\]
core1_dmem_rdata\[8\]
core1_dmem_rdata\[7\]
core1_dmem_rdata\[6\]
core1_dmem_rdata\[5\]
core1_dmem_rdata\[4\]
core1_dmem_rdata\[3\]
core1_dmem_rdata\[2\]
core1_dmem_rdata\[1\]
core1_dmem_rdata\[0\]
core1_dmem_resp\[1\]
core1_dmem_resp\[0\]

core1_debug\[48\]    0500 0 2
core1_debug\[47\]
core1_debug\[46\]
core1_debug\[45\]
core1_debug\[44\]
core1_debug\[43\]
core1_debug\[42\]
core1_debug\[41\]
core1_debug\[40\]
core1_debug\[39\]
core1_debug\[38\]
core1_debug\[37\]
core1_debug\[36\]
core1_debug\[35\]
core1_debug\[34\]
core1_debug\[33\]
core1_debug\[32\]
core1_debug\[31\]
core1_debug\[30\]
core1_debug\[29\]
core1_debug\[28\]
core1_debug\[27\]
core1_debug\[26\]
core1_debug\[25\]
core1_debug\[24\]
core1_debug\[23\]
core1_debug\[22\]
core1_debug\[21\]
core1_debug\[20\]
core1_debug\[19\]
core1_debug\[18\]
core1_debug\[17\]
core1_debug\[16\]
core1_debug\[15\]
core1_debug\[14\]
core1_debug\[13\]
core1_debug\[12\]
core1_debug\[11\]
core1_debug\[10\]
core1_debug\[9\]
core1_debug\[8\]
core1_debug\[7\]
core1_debug\[6\]
core1_debug\[5\]
core1_debug\[4\]
core1_debug\[3\]
core1_debug\[2\]
core1_debug\[1\]
core1_debug\[0\]

core1_timer_irq        600 0 2
core1_timer_val\[63\]
core1_timer_val\[62\]
core1_timer_val\[61\]
core1_timer_val\[60\]
core1_timer_val\[59\]
core1_timer_val\[58\]
core1_timer_val\[57\]
core1_timer_val\[56\]
core1_timer_val\[55\]
core1_timer_val\[54\]
core1_timer_val\[53\]
core1_timer_val\[52\]
core1_timer_val\[51\]
core1_timer_val\[50\]
core1_timer_val\[49\]
core1_timer_val\[48\]
core1_timer_val\[47\]
core1_timer_val\[46\]
core1_timer_val\[45\]
core1_timer_val\[44\]
core1_timer_val\[43\]
core1_timer_val\[42\]
core1_timer_val\[41\]
core1_timer_val\[40\]
core1_timer_val\[39\]
core1_timer_val\[38\]
core1_timer_val\[37\]
core1_timer_val\[36\]
core1_timer_val\[35\]
core1_timer_val\[34\]
core1_timer_val\[33\]
core1_timer_val\[32\]
core1_timer_val\[31\]
core1_timer_val\[30\]
core1_timer_val\[29\]
core1_timer_val\[28\]
core1_timer_val\[27\]
core1_timer_val\[26\]
core1_timer_val\[25\]
core1_timer_val\[24\]
core1_timer_val\[23\]
core1_timer_val\[22\]
core1_timer_val\[21\]
core1_timer_val\[20\]
core1_timer_val\[19\]
core1_timer_val\[18\]
core1_timer_val\[17\]
core1_timer_val\[16\]
core1_timer_val\[15\]
core1_timer_val\[14\]
core1_timer_val\[13\]
core1_timer_val\[12\]
core1_timer_val\[11\]
core1_timer_val\[10\]
core1_timer_val\[9\]
core1_timer_val\[8\]
core1_timer_val\[7\]
core1_timer_val\[6\]
core1_timer_val\[5\]
core1_timer_val\[4\]
core1_timer_val\[3\]
core1_timer_val\[2\]
core1_timer_val\[1\]
core1_timer_val\[0\]
core1_irq_lines\[31\]
core1_irq_lines\[30\]
core1_irq_lines\[29\]
core1_irq_lines\[28\]
core1_irq_lines\[27\]
core1_irq_lines\[26\]
core1_irq_lines\[25\]
core1_irq_lines\[24\]
core1_irq_lines\[23\]
core1_irq_lines\[22\]
core1_irq_lines\[21\]
core1_irq_lines\[20\]
core1_irq_lines\[19\]
core1_irq_lines\[18\]
core1_irq_lines\[17\]
core1_irq_lines\[16\]
core1_irq_lines\[15\]
core1_irq_lines\[14\]
core1_irq_lines\[13\]
core1_irq_lines\[12\]
core1_irq_lines\[11\]
core1_irq_lines\[10\]
core1_irq_lines\[9\]
core1_irq_lines\[8\]
core1_irq_lines\[7\]
core1_irq_lines\[6\]
core1_irq_lines\[5\]
core1_irq_lines\[4\]
core1_irq_lines\[3\]
core1_irq_lines\[2\]
core1_irq_lines\[1\]
core1_irq_lines\[0\]
core1_irq_soft


core_irq_lines_i\[31\]   850 0 2
core_irq_lines_i\[30\]
core_irq_lines_i\[29\]
core_irq_lines_i\[28\]
core_irq_lines_i\[27\]
core_irq_lines_i\[26\]
core_irq_lines_i\[25\]
core_irq_lines_i\[24\]
core_irq_lines_i\[23\]
core_irq_lines_i\[22\]
core_irq_lines_i\[21\]
core_irq_lines_i\[20\]
core_irq_lines_i\[19\]
core_irq_lines_i\[18\]
core_irq_lines_i\[17\]
core_irq_lines_i\[16\]
core_irq_lines_i\[15\]
core_irq_lines_i\[14\]
core_irq_lines_i\[13\]
core_irq_lines_i\[12\]
core_irq_lines_i\[11\]
core_irq_lines_i\[10\]
core_irq_lines_i\[9\]
core_irq_lines_i\[8\]
core_irq_lines_i\[7\]
core_irq_lines_i\[6\]
core_irq_lines_i\[5\]
core_irq_lines_i\[4\]
core_irq_lines_i\[3\]
core_irq_lines_i\[2\]
core_irq_lines_i\[1\]
core_irq_lines_i\[0\]
core_irq_soft_i

cfg_ccska\[3\]
cfg_ccska\[2\]
cfg_ccska\[1\]
cfg_ccska\[0\]
core_clk_int
core_clk_skew
core_clk          
rtc_clk
pwrup_rst_n
cpu_intf_rst_n
cfg_bypass_icache
cfg_bypass_dcache