diff --git a/openlane/uart_i2cm_usb_spi_top/base.sdc b/openlane/uart_i2cm_usb_spi_top/base.sdc
index 69c2345..4a33fc5 100644
--- a/openlane/uart_i2cm_usb_spi_top/base.sdc
+++ b/openlane/uart_i2cm_usb_spi_top/base.sdc
@@ -7,8 +7,8 @@
 # Timing Constraints
 ###############################################################################
 create_clock -name app_clk -period 10.0000 [get_ports {app_clk}]
-create_clock -name uart0_baud_clk -period 100.0000 [get_pins {u_uart0_core.u_lineclk_buf.u_mux/X}]
-create_clock -name uart1_baud_clk -period 100.0000 [get_pins {u_uart1_core.u_lineclk_buf.u_mux/X}]
+create_clock -name uart0_baud_clk -period 100.0000 [get_pins {u_uart0_core.u_lineclk_buf.genblk1.u_mux/X}]
+create_clock -name uart1_baud_clk -period 100.0000 [get_pins {u_uart1_core.u_lineclk_buf.genblk1.u_mux/X}]
 create_clock -name usb_clk -period 100.0000 [get_ports {usb_clk}]
 
 set_clock_transition 0.1500 [all_clocks]
diff --git a/openlane/uart_i2cm_usb_spi_top/config.tcl b/openlane/uart_i2cm_usb_spi_top/config.tcl
index 9b0cbc5..a97080d 100644
--- a/openlane/uart_i2cm_usb_spi_top/config.tcl
+++ b/openlane/uart_i2cm_usb_spi_top/config.tcl
@@ -27,7 +27,7 @@
 
 # Timing configuration
 set ::env(CLOCK_PERIOD) "10"
-set ::env(CLOCK_PORT) "app_clk usb_clk u_uart_core.u_lineclk_buf.u_mux/X"
+set ::env(CLOCK_PORT) "app_clk usb_clk u_uart0_core.u_lineclk_buf.genblk1.u_mux/X u_uart1_core.u_lineclk_buf.genblk1.u_mux/X"
 
 set ::env(SYNTH_MAX_FANOUT) 4
 
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 2346fea..3abc64f 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -110,7 +110,7 @@
 
 set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr2c/src/includes ]
 
-set ::env(GLB_RT_MAXLAYER) 6
+#set ::env(GLB_RT_MAXLAYER) 6
 set ::env(RT_MAX_LAYER) {met5}
 
 set ::env(FP_PDN_CHECK_NODES) 0
diff --git a/openlane/wb_host/base.sdc b/openlane/wb_host/base.sdc
index 9d9cc79..a5b2325 100644
--- a/openlane/wb_host/base.sdc
+++ b/openlane/wb_host/base.sdc
@@ -8,7 +8,12 @@
 ###############################################################################
 create_clock -name wbm_clk_i -period 10.0000 [get_ports {wbm_clk_i}]
 create_clock -name wbs_clk_i -period 10.0000 [get_ports {wbs_clk_i}]
-create_clock -name uart_clk -period 100.0000 [get_pins {u_uart2wb.u_core.u_uart_clk.u_mux/X}]
+create_clock -name uart_clk -period 100.0000 [get_pins {u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X}]
+
+create_clock -name int_pll_clock -period 10.0000  [get_pins {u_clkbuf_pll.u_buf/X}]
+create_clock -name wbs_ref_clk   -period 10.0000  [get_pins {u_wbs_ref_clkbuf.u_buf/X}]
+create_clock -name cpu_ref_clk   -period 10.0000  [get_pins {u_cpu_ref_clkbuf.u_buf/X}]
+create_clock -name usb_ref_clk   -period 10.0000  [get_pins {u_usb_ref_clkbuf.u_buf/X}]
 
 set_clock_transition 0.1500 [all_clocks]
 set_clock_uncertainty -setup 0.2500 [all_clocks]
@@ -20,9 +25,14 @@
 set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
 
 set_clock_groups -name async_clock -asynchronous \
- -group [get_clocks {uart_clk}]  \
- -group [get_clocks {wbs_clk_i}] \
- -group [get_clocks {wbm_clk_i}] -comment {Async Clock group}
+ -group [get_clocks {uart_clk}]      \
+ -group [get_clocks {wbs_clk_i}]     \
+ -group [get_clocks {wbm_clk_i}]     \
+ -group [get_clocks {int_pll_clock}] \
+ -group [get_clocks {wbs_ref_clk}]   \
+ -group [get_clocks {cpu_ref_clk}]   \
+ -group [get_clocks {usb_ref_clk}]   \
+ -comment {Async Clock group}
 
 ### ClkSkew Adjust
 set_case_analysis 0 [get_ports {cfg_cska_wh[0]}]
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl
index a69184e..0d8ff81 100755
--- a/openlane/wb_host/config.tcl
+++ b/openlane/wb_host/config.tcl
@@ -26,7 +26,7 @@
 
 # Timing configuration
 set ::env(CLOCK_PERIOD) "10"
-set ::env(CLOCK_PORT) "wbm_clk_i wbs_clk_i u_uart2wb.u_core.u_uart_clk.u_mux/X"
+set ::env(CLOCK_PORT) "wbm_clk_i wbs_clk_i u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X"
 
 set ::env(SYNTH_MAX_FANOUT) 4
 
diff --git a/sta/sdc/caravel.sdc b/sta/sdc/caravel.sdc
index c9efeb9..02e4326 100644
--- a/sta/sdc/caravel.sdc
+++ b/sta/sdc/caravel.sdc
@@ -14,14 +14,24 @@
 #create_clock [get_pins  clocking/pll_clk90 ] -name "pll_clk90"  -period 25
 
 create_generated_clock -name wb_clk -add -source [get_ports {clock}] -master_clock [get_clocks clock] -divide_by 1 -comment {Wishbone User Clock} [get_pins mprj/wb_clk_i]
+create_clock -name int_pll_clock -period 5.0000  [get_pins {mprj/u_wb_host/u_clkbuf_pll.u_buf/X}]
+
+create_clock -name wbs_ref_clk -period 5.0000   [get_pins {mprj/u_wb_host/u_wbs_ref_clkbuf.u_buf/X}]
 create_clock -name wbs_clk_i   -period 10.0000  [get_pins {mprj/u_wb_host/wbs_clk_out}]
-create_clock -name cpu_ref_clk -period 10.0000  [get_pins {mprj/u_wb_host/u_cpu_ref_sel.u_mux/X}]
+
+create_clock -name cpu_ref_clk -period 5.0000   [get_pins {mprj/u_wb_host/u_cpu_ref_clkbuf.u_buf/X}]
 create_clock -name cpu_clk     -period 10.0000  [get_pins {mprj/u_wb_host/cpu_clk}]
+
 create_clock -name rtc_clk     -period 50.0000  [get_pins {mprj/u_wb_host/rtc_clk}]
+
+create_clock -name pll_ref_clk -period 20.0000  [get_pins {mprj/u_wb_host/pll_ref_clk}]
+create_clock -name pll_clk_0   -period 5.0000   [get_pins {mprj/u_pll/ringosc.ibufp01/Y}]
+
+create_clock -name usb_ref_clk -period 5.0000   [get_pins {mprj/u_wb_host/u_usb_ref_clkbuf.u_buf/X}]
 create_clock -name usb_clk     -period 20.0000  [get_pins {mprj/u_wb_host/usb_clk}]
-create_clock -name uarts0_clk  -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart0_core.u_lineclk_buf.u_mux/X}]
-create_clock -name uarts1_clk  -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart1_core.u_lineclk_buf.u_mux/X}]
-create_clock -name uartm_clk   -period 100.0000 [get_pins {mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.u_mux/X}]
+create_clock -name uarts0_clk  -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart0_core.u_lineclk_buf.genblk1.u_mux/X}]
+create_clock -name uarts1_clk  -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart1_core.u_lineclk_buf.genblk1.u_mux/X}]
+create_clock -name uartm_clk   -period 100.0000 [get_pins {mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X}]
 
 
 ## Case analysis
@@ -70,17 +80,22 @@
 set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_sram_lphase[1]}]
 
 #disable clock gating check at static clock select pins
-set_false_path -through [get_pins mprj/u_wb_host/u_wbs_clk_sel.u_mux/S]
+set_false_path -through [get_pins mprj/u_wb_host/u_wbs_clk_sel.genblk1.u_mux/S]
 
 set_propagated_clock [all_clocks]
 
 set_clock_groups -name async_clock -asynchronous \
  -group [get_clocks {clock wb_clk }]\
  -group [get_clocks {user_clk2}]\
+ -group [get_clocks {int_pll_clock}]\
  -group [get_clocks {wbs_clk_i}]\
+ -group [get_clocks {wbs_ref_clk}]\
  -group [get_clocks {cpu_clk}]\
  -group [get_clocks {cpu_ref_clk}]\
  -group [get_clocks {rtc_clk}]\
+ -group [get_clocks {usb_ref_clk}]\
+ -group [get_clocks {pll_ref_clk}]\
+ -group [get_clocks {pll_clk_0}]\
  -group [get_clocks {usb_clk}]\
  -group [get_clocks {uarts0_clk}]\
  -group [get_clocks {uarts1_clk}]\
@@ -149,8 +164,6 @@
 set_false_path -from [get_ports mprj_io[*]]
 set_false_path -from [get_ports gpio]
 
-## User Project static signals
-set_false_path -through [get_pins mprj/u_pinmux/bist_en]
 
 # TODO set this as parameter
 set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index b5a6da1..e0656e9 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -186,13 +186,13 @@
 	wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
    end else if(d_risc_id == 1) begin
 	$display("STATUS: Working with Risc core 1");
-	wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h243);
+	wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
    end else if(d_risc_id == 2) begin
 	$display("STATUS: Working with Risc core 2");
-	wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h443);
+	wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h41F);
    end else if(d_risc_id == 3) begin
-	$display("STATUS: Working with Risc core 2");
-	wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h84F);
+	$display("STATUS: Working with Risc core 3");
+	wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h81F);
    end
 
    repeat (100) @(posedge clock);  // wait for Processor Get Ready
diff --git a/verilog/includes/includes.rtl.lib b/verilog/includes/includes.rtl.lib
new file mode 100644
index 0000000..5045805
--- /dev/null
+++ b/verilog/includes/includes.rtl.lib
@@ -0,0 +1,3 @@
+-v $(USER_PROJECT_VERILOG)/rtl/digital_pll/src/digital_pll_controller.v
+-v $(USER_PROJECT_VERILOG)/rtl/digital_pll/src/digital_pll.v
+-v $(USER_PROJECT_VERILOG)/rtl/digital_pll/src/ring_osc2x13.v
diff --git a/verilog/rtl/lib/ctech_cells.sv b/verilog/rtl/lib/ctech_cells.sv
index ebbd617..bd34f11 100644
--- a/verilog/rtl/lib/ctech_cells.sv
+++ b/verilog/rtl/lib/ctech_cells.sv
@@ -15,7 +15,7 @@
          for (tcnt = 0; $unsigned(tcnt) < WB; tcnt=tcnt+1) begin : bit_
              sky130_fd_sc_hd__mux2_8 u_mux (.A0 (A0[tcnt]), .A1 (A1[tcnt]), .S  (S), .X (X[tcnt]));
          end
-       end else begin : bit_
+       end else begin
           sky130_fd_sc_hd__mux2_8 u_mux (.A0 (A0), .A1 (A1), .S  (S), .X (X));
        end
     endgenerate
@@ -39,7 +39,7 @@
          for (tcnt = 0; $unsigned(tcnt) < WB; tcnt=tcnt+1) begin : bit_
              sky130_fd_sc_hd__mux2_2 u_mux (.A0 (A0[tcnt]), .A1 (A1[tcnt]), .S  (S), .X (X[tcnt]));
          end
-       end else begin : bit_
+       end else begin 
           sky130_fd_sc_hd__mux2_2 u_mux (.A0 (A0), .A1 (A1), .S  (S), .X (X));
        end
     endgenerate
@@ -63,7 +63,7 @@
          for (tcnt = 0; $unsigned(tcnt) < WB; tcnt=tcnt+1) begin : bit_
              sky130_fd_sc_hd__mux2_4 u_mux (.A0 (A0[tcnt]), .A1 (A1[tcnt]), .S  (S), .X (X[tcnt]));
          end
-       end else begin : bit_
+       end else begin
           sky130_fd_sc_hd__mux2_4 u_mux (.A0 (A0), .A1 (A1), .S  (S), .X (X));
        end
     endgenerate
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv
index 1ae477c..8256742 100644
--- a/verilog/rtl/wb_host/src/wb_host.sv
+++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -549,6 +549,7 @@
 // Generate Internal WishBone Clock
 //----------------------------------
 logic       wb_clk_div;
+logic       wbs_ref_clk_int;
 logic       wbs_ref_clk;
 
 wire  [1:0]   cfg_wb_clk_src_sel   =  cfg_wb_clk_ctrl[7:6];
@@ -556,9 +557,11 @@
 wire  [4:0]   cfg_wb_clk_ratio     =  cfg_wb_clk_ctrl[4:0];
 
 
-assign wbs_ref_clk = (cfg_wb_clk_src_sel ==2'b00) ? user_clock1 :
-                     (cfg_wb_clk_src_sel ==2'b01) ? user_clock2 :	
-	             int_pll_clock;
+assign wbs_ref_clk_int = (cfg_wb_clk_src_sel ==2'b00) ? user_clock1 :
+                         (cfg_wb_clk_src_sel ==2'b01) ? user_clock2 :	
+	                 int_pll_clock;
+
+ctech_clk_buf u_wbs_ref_clkbuf (.A (wbs_ref_clk_int), . X(wbs_ref_clk));
 
 //assign wbs_clk_out  = (cfg_wb_clk_div)  ? wb_clk_div : wbm_clk_i;
 ctech_mux2x1 u_wbs_clk_sel (.A0 (wbs_ref_clk), .A1 (wb_clk_div), .S  (cfg_wb_clk_div), .X  (wbs_clk_out));
@@ -578,6 +581,7 @@
 // Generate CORE Clock Generation
 //----------------------------------
 wire   cpu_clk_div;
+wire   cpu_ref_clk_int;
 wire   cpu_ref_clk;
 wire   cpu_clk_int;
 
@@ -585,9 +589,11 @@
 wire       cfg_cpu_clk_div       = cfg_cpu_clk_ctrl[5];
 wire [4:0] cfg_cpu_clk_ratio     = cfg_cpu_clk_ctrl[4:0];
 
-assign cpu_ref_clk = (cfg_cpu_clk_src_sel ==2'b00) ? user_clock1 :
-                     (cfg_cpu_clk_src_sel ==2'b01) ? user_clock2 :	
-	             int_pll_clock;
+assign cpu_ref_clk_int = (cfg_cpu_clk_src_sel ==2'b00) ? user_clock1 :
+                         (cfg_cpu_clk_src_sel ==2'b01) ? user_clock2 :	
+	                 int_pll_clock;
+
+ctech_clk_buf u_cpu_ref_clkbuf (.A (cpu_ref_clk_int), . X(cpu_ref_clk));
 
 //assign cpu_clk_int = (cfg_cpu_clk_div)     ? cpu_clk_div : cpu_ref_clk;
 ctech_mux2x1 u_cpu_clk_sel (.A0 (cpu_ref_clk), .A1 (cpu_clk_div), .S  (cfg_cpu_clk_div),     .X  (cpu_clk_int));
@@ -626,6 +632,7 @@
 // Generate USB Clock Generation
 //----------------------------------
 wire   usb_clk_div;
+wire   usb_ref_clk_int;
 wire   usb_ref_clk;
 wire   usb_clk_int;
 
@@ -633,9 +640,10 @@
 wire       cfg_usb_clk_div       = cfg_usb_clk_ctrl[5];
 wire [4:0] cfg_usb_clk_ratio     = cfg_usb_clk_ctrl[4:0];
 
-assign usb_ref_clk = (cfg_usb_clk_sel_sel ==2'b00) ? user_clock1 :
-                     (cfg_usb_clk_sel_sel ==2'b01) ? user_clock2 :	
-	             int_pll_clock;
+assign usb_ref_clk_int = (cfg_usb_clk_sel_sel ==2'b00) ? user_clock1 :
+                         (cfg_usb_clk_sel_sel ==2'b01) ? user_clock2 :	
+	                 int_pll_clock;
+ctech_clk_buf u_usb_ref_clkbuf (.A (usb_ref_clk_int), . X(usb_ref_clk));
 //assign usb_clk_int = (cfg_usb_clk_div)     ? usb_clk_div : usb_ref_clk;
 ctech_mux2x1 u_usb_clk_sel (.A0 (usb_ref_clk), .A1 (usb_clk_div), .S  (cfg_usb_clk_div), .X  (usb_clk_int));