blob: e75590d902a46f7f0b778837f433fbc7a0c1a03b [file] [log] [blame]
//////////////////////////////////////////////////////////////////////////////
// SPDX-FileCopyrightText: 2021, Dinesh Annayya
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// SPDX-License-Identifier: Apache-2.0
// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
// //////////////////////////////////////////////////////////////////////////
#define SC_SIM_OUTPORT (0xf0000000)
#include "../c_func/inc/int_reg_map.h"
#include "common_misc.h"
#include "common_bthread.h"
int main()
{
reg_glbl_cfg0 |= 0x1F; // Remove Reset for UART
reg_glbl_multi_func |=0x100; // Enable UART Multi func
reg_uart0_ctrl = 0x07; // Enable Uart Access {3'h0,2'b00,1'b1,1'b1,1'b1}
// GLBL_CFG_MAIL_BOX used as mail box, each core update boot up handshake at 8 bit
// bit[7:0] - core-0
// bit[15:8] - core-1
// bit[23:16] - core-2
// bit[31:24] - core-3
reg_glbl_mail_box = 0x1 << (bthread_get_core_id() * 8); // Start of Main
while(1) {
// Check UART RX fifo has data, if available loop back the data
// Also check txfifo is not full
if((reg_uart0_rxfifo_stat != 0) && ((reg_uart0_status & 0x1) != 0x1)) {
reg_uart0_txdata = reg_uart0_rxdata;
}
}
return 0;
}