diff --git a/README.md b/README.md
index e6e9b0b..acfd916 100644
--- a/README.md
+++ b/README.md
@@ -55,6 +55,7 @@
     * UART with 16Byte FIFO
     * USB 1.1 Host
     * I2C Master
+    * UART Master
     * Simple SPI Master
     * 6 Channel ADC (in Progress)
     * 6 PWM
@@ -133,6 +134,7 @@
 Following Design changes are done on the basic version of syntacore RISC core
 ```
    * Some of the sv syntex are changed to standard verilog format to make compatibile with opensource tool iverilog & yosys
+   * local Instruction Memory is increased from 4 to 8 location
    * Instruction Request are changed from Single word to 4 Word Burst
    * Multiplication and Divsion are changed to improve timing
    * Additional pipe line stages added to improve the RISC timing closure near to 50Mhz
@@ -146,7 +148,7 @@
 ### Block Diagram
 <table>
   <tr>
-    <td  align="center"><img src="./docs/source/_static/syntacore_blockdiagram.svg" ></td>
+    <td  align="center"><img src="./docs/source/_static/riscvcore_blockdiagram.png" ></td>
   </tr>
 </table>
 
diff --git a/docs/source/_static/riscvcore_blockdiagram.png b/docs/source/_static/riscvcore_blockdiagram.png
new file mode 100644
index 0000000..d1f4594
--- /dev/null
+++ b/docs/source/_static/riscvcore_blockdiagram.png
Binary files differ
diff --git a/docs/source/_static/sdram_controller.jpg b/docs/source/_static/sdram_controller.jpg
deleted file mode 100644
index 5c0cb82..0000000
--- a/docs/source/_static/sdram_controller.jpg
+++ /dev/null
Binary files differ
diff --git a/docs/source/_static/syntacore_blockdiagram.svg b/docs/source/_static/syntacore_blockdiagram.svg
deleted file mode 100644
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