2022-11-22 18:11:42 - [INFO] - {{Project Git Info}} Repository: https://github.com/deepsita/AXSOP.git | Branch: main | Commit: 7c186c526ae428170c70c7dcee4ca756ef92381b
2022-11-22 18:11:42 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: energy_efficient_sum-of-products_circuit
2022-11-22 18:11:42 - [INFO] - {{Project Type Info}} digital
2022-11-22 18:11:42 - [INFO] - {{Project GDS Info}} user_project_wrapper: bdff9875863d1f2753f9de5beb5b13ea96f3351d
2022-11-22 18:11:42 - [INFO] - {{Tools Info}} KLayout: v0.27.12 | Magic: v8.3.340
2022-11-22 18:11:42 - [INFO] - {{PDKs Info}} SKY130A: f70d8ca46961ff92719d8870a18a076370b85f6c | Open PDKs: 0059588eebfc704681dc2368bd1d33d96281d10f
2022-11-22 18:11:42 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'energy_efficient_sum-of-products_circuit/jobs/mpw_precheck/793b2636-5a3c-4e7c-b3b8-5432a87876c8/logs'
2022-11-22 18:11:42 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, GPIO-Defines, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
2022-11-22 18:11:42 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 14: License
2022-11-22 18:11:43 - [INFO] - An approved LICENSE (Apache-2.0) was found in energy_efficient_sum-of-products_circuit.
2022-11-22 18:11:43 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
2022-11-22 18:11:44 - [INFO] - An approved LICENSE (Apache-2.0) was found in energy_efficient_sum-of-products_circuit.
2022-11-22 18:11:44 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
2022-11-22 18:11:44 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 37 non-compliant file(s) with the SPDX Standard.
2022-11-22 18:11:44 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['energy_efficient_sum-of-products_circuit/Makefile', 'energy_efficient_sum-of-products_circuit/docs/Makefile', 'energy_efficient_sum-of-products_circuit/docs/environment.yml', 'energy_efficient_sum-of-products_circuit/docs/source/conf.py', 'energy_efficient_sum-of-products_circuit/docs/source/index.rst', 'energy_efficient_sum-of-products_circuit/docs/source/quickstart.rst', 'energy_efficient_sum-of-products_circuit/openlane/Makefile', 'energy_efficient_sum-of-products_circuit/openlane/user_proj_example/config.json', 'energy_efficient_sum-of-products_circuit/openlane/user_project_wrapper/config.json', 'energy_efficient_sum-of-products_circuit/openlane/user_project_wrapper/fixed_dont_change/default_wrapper_cfgs.tcl', 'energy_efficient_sum-of-products_circuit/openlane/user_project_wrapper/fixed_dont_change/fixed_wrapper_cfgs.tcl', 'energy_efficient_sum-of-products_circuit/sdc/user_proj_example.sdc', 'energy_efficient_sum-of-products_circuit/sdc/user_project_wrapper.sdc', 'energy_efficient_sum-of-products_circuit/verilog/dv/Makefile', 'energy_efficient_sum-of-products_circuit/verilog/dv/io_ports/Makefile']
2022-11-22 18:11:44 - [INFO] - For the full SPDX compliance report check: energy_efficient_sum-of-products_circuit/jobs/mpw_precheck/793b2636-5a3c-4e7c-b3b8-5432a87876c8/logs/spdx_compliance_report.log
2022-11-22 18:11:44 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 14: Makefile
2022-11-22 18:11:44 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
2022-11-22 18:11:44 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 14: Default
2022-11-22 18:11:44 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
2022-11-22 18:11:44 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
2022-11-22 18:11:44 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 14: Documentation
2022-11-22 18:11:44 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
2022-11-22 18:11:44 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 14: Consistency
2022-11-22 18:11:49 - [INFO] - HIERARCHY CHECK PASSED: Module user_project_wrapper is instantiated in caravel. 
2022-11-22 18:11:49 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravel contains at least 8 instances (92 instances). 
2022-11-22 18:11:49 - [INFO] - MODELING CHECK PASSED: Netlist caravel is structural.
2022-11-22 18:11:49 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_project_wrapper are correctly connected in the top level netlist caravel.
2022-11-22 18:11:49 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in caravel are connected to power
2022-11-22 18:11:49 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravel netlist passed all consistency checks.
2022-11-22 18:11:49 - [INFO] - PORTS CHECK PASSED: Netlist user_project_wrapper ports match the golden wrapper ports
2022-11-22 18:11:49 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_project_wrapper contains at least 1 instances (1 instances). 
2022-11-22 18:11:49 - [INFO] - MODELING CHECK PASSED: Netlist user_project_wrapper is structural.
2022-11-22 18:11:49 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_project_wrapper matches the provided structural netlist.
2022-11-22 18:11:49 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in user_project_wrapper are connected to power
2022-11-22 18:11:49 - [INFO] - PORT TYPES CHECK PASSED: Netlist user_project_wrapper port types match the golden wrapper port types.
2022-11-22 18:11:49 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_project_wrapper netlist passed all consistency checks.
2022-11-22 18:11:49 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
2022-11-22 18:11:49 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 14: GPIO-Defines
2022-11-22 18:11:49 - [INFO] - GPIO-DEFINES: Checking verilog/rtl/user_defines.v, parsing files: ['/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_base.v', 'energy_efficient_sum-of-products_circuit/verilog/rtl/user_defines.v', '/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_observe.v']
2022-11-22 18:11:50 - [INFO] - GPIO-DEFINES report path: energy_efficient_sum-of-products_circuit/jobs/mpw_precheck/793b2636-5a3c-4e7c-b3b8-5432a87876c8/outputs/reports/gpio_defines.report
2022-11-22 18:11:50 - [INFO] - {{GPIO-DEFINES CHECK PASSED}} The user verilog/rtl/user_defines.v is valid.
2022-11-22 18:11:50 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 14: XOR
2022-11-22 18:11:57 - [INFO] - {{XOR CHECK UPDATE}} Total XOR differences: 0, for more details view energy_efficient_sum-of-products_circuit/jobs/mpw_precheck/793b2636-5a3c-4e7c-b3b8-5432a87876c8/outputs/user_project_wrapper.xor.gds
2022-11-22 18:11:57 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
2022-11-22 18:11:57 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 14: Magic DRC
2022-11-22 18:11:57 - [INFO] - 0 DRC violations
2022-11-22 18:11:57 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-11-22 18:11:57 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 14: Klayout FEOL
2022-11-22 18:12:14 - [INFO] - No DRC Violations found
2022-11-22 18:12:14 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-11-22 18:12:14 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 14: Klayout BEOL
2022-11-22 18:13:48 - [INFO] - No DRC Violations found
2022-11-22 18:13:48 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-11-22 18:13:48 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 14: Klayout Offgrid
2022-11-22 18:14:13 - [INFO] - No DRC Violations found
2022-11-22 18:14:13 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-11-22 18:14:13 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 14: Klayout Metal Minimum Clear Area Density
2022-11-22 18:14:19 - [INFO] - No DRC Violations found
2022-11-22 18:14:19 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-11-22 18:14:19 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 14: Klayout Pin Label Purposes Overlapping Drawing
2022-11-22 18:14:23 - [INFO] - No DRC Violations found
2022-11-22 18:14:23 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-11-22 18:14:23 - [INFO] - {{STEP UPDATE}} Executing Check 14 of 14: Klayout ZeroArea
2022-11-22 18:14:25 - [INFO] - No DRC Violations found
2022-11-22 18:14:25 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-11-22 18:14:25 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'energy_efficient_sum-of-products_circuit/jobs/mpw_precheck/793b2636-5a3c-4e7c-b3b8-5432a87876c8/logs'
2022-11-22 18:14:25 - [INFO] - {{SUCCESS}} All Checks Passed !!!