)]}'
{
  "commit": "e85588c3a388b35767da03a916627318a2c02c77",
  "tree": "abd8f97d33a08e9470a5853586ff2f472d2d5293",
  "parents": [
    "ef1fb0390b2e4e4ac6210f3f8457f8635b65aa69"
  ],
  "author": {
    "name": "Sean Cross",
    "email": "sean@xobs.io",
    "time": "Wed Dec 28 14:03:55 2022 +0800"
  },
  "committer": {
    "name": "Sean Cross",
    "email": "sean@xobs.io",
    "time": "Wed Dec 28 14:03:55 2022 +0800"
  },
  "message": "verilog: use correct path for wb_pio rtl\n\nThese files still referred to `user_proj_example`.\n\nSigned-off-by: Sean Cross \u003csean@xobs.io\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "3537de803dd1d472e447f0791344cbf5c9391455",
      "old_mode": 33188,
      "old_path": "verilog/rtl/uprj_netlists.v",
      "new_id": "0fcdbdd2f29899a7d8901ff8f38d3220f83765be",
      "new_mode": 33188,
      "new_path": "verilog/rtl/uprj_netlists.v"
    },
    {
      "type": "modify",
      "old_id": "9faaea5e5e55c790fdccac8d03f856a100637179",
      "old_mode": 33188,
      "old_path": "verilog/rtl/wb_pio_top.v",
      "new_id": "9506cfe907aa93ecfd2f419b1e0a8b7c151e2ff6",
      "new_mode": 33188,
      "new_path": "verilog/rtl/wb_pio_top.v"
    }
  ]
}