diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 3537de8..0fcdbdd 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -21,8 +21,8 @@
     // Assume default net type to be wire because GL netlists don't have the wire definitions
     `default_nettype wire
     `include "gl/user_project_wrapper.v"
-    `include "gl/user_proj_example.v"
+    `include "gl/wb_pio.v"
 `else
     `include "user_project_wrapper.v"
-    `include "user_proj_example.v"
-`endif
\ No newline at end of file
+    `include "wb_pio.v"
+`endif
diff --git a/verilog/rtl/wb_pio_top.v b/verilog/rtl/wb_pio_top.v
index 9faaea5..9506cfe 100644
--- a/verilog/rtl/wb_pio_top.v
+++ b/verilog/rtl/wb_pio_top.v
@@ -17,20 +17,9 @@
 /*
  *-------------------------------------------------------------
  *
- * user_proj_example
+ * wb_pio
  *
- * This is an example of a (trivially simple) user project,
- * showing how the user project can connect to the logic
- * analyzer, the wishbone bus, and the I/O pads.
- *
- * This project generates an integer count, which is output
- * on the user area GPIO pads (digital output only).  The
- * wishbone connection allows the project to be controlled
- * (start and stop) from the management SoC program.
- *
- * See the testbenches in directory "mprj_counter" for the
- * example programs that drive this user project.  The three
- * testbenches are "io_ports", "la_test1", and "la_test2".
+ * Create a PIO block on the Wishbone bus at address 0x3000_0000.
  *
  *-------------------------------------------------------------
  */