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# Created by write_sdc
# Wed Aug 31 13:53:24 2022
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current_design openGFX430
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# Timing Constraints
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create_clock -name mclk -period 10.0000 [get_ports {mclk}]
set_clock_transition 0.1500 [get_clocks {mclk}]
set_clock_uncertainty 0.2500 mclk
set_propagated_clock [get_clocks {mclk}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dbg_freeze_i}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_d_i[0]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_d_i[10]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_d_i[11]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_d_i[12]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_d_i[13]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_d_i[14]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_d_i[15]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_d_i[1]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_d_i[2]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_d_i[3]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_d_i[4]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_d_i[5]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_d_i[6]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_d_i[7]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_d_i[8]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_d_i[9]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_dout_i[0]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_dout_i[10]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_dout_i[11]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_dout_i[12]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_dout_i[13]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_dout_i[14]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_dout_i[15]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_dout_i[1]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_dout_i[2]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_dout_i[3]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_dout_i[4]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_dout_i[5]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_dout_i[6]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_dout_i[7]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_dout_i[8]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_dout_i[9]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_addr_i[0]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_addr_i[10]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_addr_i[11]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_addr_i[12]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_addr_i[13]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_addr_i[1]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_addr_i[2]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_addr_i[3]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_addr_i[4]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_addr_i[5]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_addr_i[6]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_addr_i[7]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_addr_i[8]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_addr_i[9]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_din_i[0]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_din_i[10]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_din_i[11]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_din_i[12]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_din_i[13]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_din_i[14]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_din_i[15]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_din_i[1]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_din_i[2]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_din_i[3]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_din_i[4]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_din_i[5]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_din_i[6]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_din_i[7]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_din_i[8]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_din_i[9]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_en_i}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_we_i[0]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_we_i[1]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {puc_rst}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_dout_i[0]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_dout_i[10]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_dout_i[11]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_dout_i[12]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_dout_i[13]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_dout_i[14]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_dout_i[15]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_dout_i[1]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_dout_i[2]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_dout_i[3]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_dout_i[4]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_dout_i[5]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_dout_i[6]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_dout_i[7]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_dout_i[8]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_dout_i[9]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_gfx_o}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_cs_n_o}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_d_en_o}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_d_o[0]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_d_o[10]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_d_o[11]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_d_o[12]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_d_o[13]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_d_o[14]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_d_o[15]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_d_o[1]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_d_o[2]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_d_o[3]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_d_o[4]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_d_o[5]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_d_o[6]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_d_o[7]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_d_o[8]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_d_o[9]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_on_o}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_rd_n_o}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_reset_n_o}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_rs_o}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lt24_wr_n_o}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_addr_o[0]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_addr_o[1]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_addr_o[2]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_addr_o[3]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_addr_o[4]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_addr_o[5]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_addr_o[6]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_addr_o[7]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_addr_o[8]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_cen_o}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_din_o[0]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_din_o[10]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_din_o[11]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_din_o[12]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_din_o[13]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_din_o[14]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_din_o[15]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_din_o[1]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_din_o[2]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_din_o[3]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_din_o[4]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_din_o[5]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_din_o[6]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_din_o[7]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_din_o[8]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_din_o[9]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {lut_ram_wen_o}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_dout_o[0]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_dout_o[10]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_dout_o[11]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_dout_o[12]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_dout_o[13]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_dout_o[14]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_dout_o[15]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_dout_o[1]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_dout_o[2]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_dout_o[3]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_dout_o[4]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_dout_o[5]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_dout_o[6]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_dout_o[7]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_dout_o[8]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {per_dout_o[9]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_addr_o[0]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_addr_o[10]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_addr_o[11]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_addr_o[12]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_addr_o[13]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_addr_o[14]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_addr_o[15]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_addr_o[16]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_addr_o[1]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_addr_o[2]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_addr_o[3]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_addr_o[4]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_addr_o[5]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_addr_o[6]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_addr_o[7]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_addr_o[8]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_addr_o[9]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_cen_o}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_din_o[0]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_din_o[10]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_din_o[11]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_din_o[12]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_din_o[13]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_din_o[14]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_din_o[15]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_din_o[1]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_din_o[2]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_din_o[3]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_din_o[4]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_din_o[5]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_din_o[6]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_din_o[7]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_din_o[8]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_din_o[9]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {vid_ram_wen_o}]
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# Environment
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set_load -pin_load 0.0334 [get_ports {irq_gfx_o}]
set_load -pin_load 0.0334 [get_ports {lt24_cs_n_o}]
set_load -pin_load 0.0334 [get_ports {lt24_d_en_o}]
set_load -pin_load 0.0334 [get_ports {lt24_on_o}]
set_load -pin_load 0.0334 [get_ports {lt24_rd_n_o}]
set_load -pin_load 0.0334 [get_ports {lt24_reset_n_o}]
set_load -pin_load 0.0334 [get_ports {lt24_rs_o}]
set_load -pin_load 0.0334 [get_ports {lt24_wr_n_o}]
set_load -pin_load 0.0334 [get_ports {lut_ram_cen_o}]
set_load -pin_load 0.0334 [get_ports {lut_ram_wen_o}]
set_load -pin_load 0.0334 [get_ports {vid_ram_cen_o}]
set_load -pin_load 0.0334 [get_ports {vid_ram_wen_o}]
set_load -pin_load 0.0334 [get_ports {lt24_d_o[15]}]
set_load -pin_load 0.0334 [get_ports {lt24_d_o[14]}]
set_load -pin_load 0.0334 [get_ports {lt24_d_o[13]}]
set_load -pin_load 0.0334 [get_ports {lt24_d_o[12]}]
set_load -pin_load 0.0334 [get_ports {lt24_d_o[11]}]
set_load -pin_load 0.0334 [get_ports {lt24_d_o[10]}]
set_load -pin_load 0.0334 [get_ports {lt24_d_o[9]}]
set_load -pin_load 0.0334 [get_ports {lt24_d_o[8]}]
set_load -pin_load 0.0334 [get_ports {lt24_d_o[7]}]
set_load -pin_load 0.0334 [get_ports {lt24_d_o[6]}]
set_load -pin_load 0.0334 [get_ports {lt24_d_o[5]}]
set_load -pin_load 0.0334 [get_ports {lt24_d_o[4]}]
set_load -pin_load 0.0334 [get_ports {lt24_d_o[3]}]
set_load -pin_load 0.0334 [get_ports {lt24_d_o[2]}]
set_load -pin_load 0.0334 [get_ports {lt24_d_o[1]}]
set_load -pin_load 0.0334 [get_ports {lt24_d_o[0]}]
set_load -pin_load 0.0334 [get_ports {lut_ram_addr_o[8]}]
set_load -pin_load 0.0334 [get_ports {lut_ram_addr_o[7]}]
set_load -pin_load 0.0334 [get_ports {lut_ram_addr_o[6]}]
set_load -pin_load 0.0334 [get_ports {lut_ram_addr_o[5]}]
set_load -pin_load 0.0334 [get_ports {lut_ram_addr_o[4]}]
set_load -pin_load 0.0334 [get_ports {lut_ram_addr_o[3]}]
set_load -pin_load 0.0334 [get_ports {lut_ram_addr_o[2]}]
set_load -pin_load 0.0334 [get_ports {lut_ram_addr_o[1]}]
set_load -pin_load 0.0334 [get_ports {lut_ram_addr_o[0]}]
set_load -pin_load 0.0334 [get_ports {lut_ram_din_o[15]}]
set_load -pin_load 0.0334 [get_ports {lut_ram_din_o[14]}]
set_load -pin_load 0.0334 [get_ports {lut_ram_din_o[13]}]
set_load -pin_load 0.0334 [get_ports {lut_ram_din_o[12]}]
set_load -pin_load 0.0334 [get_ports {lut_ram_din_o[11]}]
set_load -pin_load 0.0334 [get_ports {lut_ram_din_o[10]}]
set_load -pin_load 0.0334 [get_ports {lut_ram_din_o[9]}]
set_load -pin_load 0.0334 [get_ports {lut_ram_din_o[8]}]
set_load -pin_load 0.0334 [get_ports {lut_ram_din_o[7]}]
set_load -pin_load 0.0334 [get_ports {lut_ram_din_o[6]}]
set_load -pin_load 0.0334 [get_ports {lut_ram_din_o[5]}]
set_load -pin_load 0.0334 [get_ports {lut_ram_din_o[4]}]
set_load -pin_load 0.0334 [get_ports {lut_ram_din_o[3]}]
set_load -pin_load 0.0334 [get_ports {lut_ram_din_o[2]}]
set_load -pin_load 0.0334 [get_ports {lut_ram_din_o[1]}]
set_load -pin_load 0.0334 [get_ports {lut_ram_din_o[0]}]
set_load -pin_load 0.0334 [get_ports {per_dout_o[15]}]
set_load -pin_load 0.0334 [get_ports {per_dout_o[14]}]
set_load -pin_load 0.0334 [get_ports {per_dout_o[13]}]
set_load -pin_load 0.0334 [get_ports {per_dout_o[12]}]
set_load -pin_load 0.0334 [get_ports {per_dout_o[11]}]
set_load -pin_load 0.0334 [get_ports {per_dout_o[10]}]
set_load -pin_load 0.0334 [get_ports {per_dout_o[9]}]
set_load -pin_load 0.0334 [get_ports {per_dout_o[8]}]
set_load -pin_load 0.0334 [get_ports {per_dout_o[7]}]
set_load -pin_load 0.0334 [get_ports {per_dout_o[6]}]
set_load -pin_load 0.0334 [get_ports {per_dout_o[5]}]
set_load -pin_load 0.0334 [get_ports {per_dout_o[4]}]
set_load -pin_load 0.0334 [get_ports {per_dout_o[3]}]
set_load -pin_load 0.0334 [get_ports {per_dout_o[2]}]
set_load -pin_load 0.0334 [get_ports {per_dout_o[1]}]
set_load -pin_load 0.0334 [get_ports {per_dout_o[0]}]
set_load -pin_load 0.0334 [get_ports {vid_ram_addr_o[16]}]
set_load -pin_load 0.0334 [get_ports {vid_ram_addr_o[15]}]
set_load -pin_load 0.0334 [get_ports {vid_ram_addr_o[14]}]
set_load -pin_load 0.0334 [get_ports {vid_ram_addr_o[13]}]
set_load -pin_load 0.0334 [get_ports {vid_ram_addr_o[12]}]
set_load -pin_load 0.0334 [get_ports {vid_ram_addr_o[11]}]
set_load -pin_load 0.0334 [get_ports {vid_ram_addr_o[10]}]
set_load -pin_load 0.0334 [get_ports {vid_ram_addr_o[9]}]
set_load -pin_load 0.0334 [get_ports {vid_ram_addr_o[8]}]
set_load -pin_load 0.0334 [get_ports {vid_ram_addr_o[7]}]
set_load -pin_load 0.0334 [get_ports {vid_ram_addr_o[6]}]
set_load -pin_load 0.0334 [get_ports {vid_ram_addr_o[5]}]
set_load -pin_load 0.0334 [get_ports {vid_ram_addr_o[4]}]
set_load -pin_load 0.0334 [get_ports {vid_ram_addr_o[3]}]
set_load -pin_load 0.0334 [get_ports {vid_ram_addr_o[2]}]
set_load -pin_load 0.0334 [get_ports {vid_ram_addr_o[1]}]
set_load -pin_load 0.0334 [get_ports {vid_ram_addr_o[0]}]
set_load -pin_load 0.0334 [get_ports {vid_ram_din_o[15]}]
set_load -pin_load 0.0334 [get_ports {vid_ram_din_o[14]}]
set_load -pin_load 0.0334 [get_ports {vid_ram_din_o[13]}]
set_load -pin_load 0.0334 [get_ports {vid_ram_din_o[12]}]
set_load -pin_load 0.0334 [get_ports {vid_ram_din_o[11]}]
set_load -pin_load 0.0334 [get_ports {vid_ram_din_o[10]}]
set_load -pin_load 0.0334 [get_ports {vid_ram_din_o[9]}]
set_load -pin_load 0.0334 [get_ports {vid_ram_din_o[8]}]
set_load -pin_load 0.0334 [get_ports {vid_ram_din_o[7]}]
set_load -pin_load 0.0334 [get_ports {vid_ram_din_o[6]}]
set_load -pin_load 0.0334 [get_ports {vid_ram_din_o[5]}]
set_load -pin_load 0.0334 [get_ports {vid_ram_din_o[4]}]
set_load -pin_load 0.0334 [get_ports {vid_ram_din_o[3]}]
set_load -pin_load 0.0334 [get_ports {vid_ram_din_o[2]}]
set_load -pin_load 0.0334 [get_ports {vid_ram_din_o[1]}]
set_load -pin_load 0.0334 [get_ports {vid_ram_din_o[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_freeze_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {per_en_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {puc_rst}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {lt24_d_i[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {lt24_d_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {lt24_d_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {lt24_d_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {lt24_d_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {lt24_d_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {lt24_d_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {lt24_d_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {lt24_d_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {lt24_d_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {lt24_d_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {lt24_d_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {lt24_d_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {lt24_d_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {lt24_d_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {lt24_d_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {lut_ram_dout_i[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {lut_ram_dout_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {lut_ram_dout_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {lut_ram_dout_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {lut_ram_dout_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {lut_ram_dout_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {lut_ram_dout_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {lut_ram_dout_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {lut_ram_dout_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {lut_ram_dout_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {lut_ram_dout_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {lut_ram_dout_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {lut_ram_dout_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {lut_ram_dout_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {lut_ram_dout_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {lut_ram_dout_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {per_addr_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {per_addr_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {per_addr_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {per_addr_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {per_addr_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {per_addr_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {per_addr_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {per_addr_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {per_addr_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {per_addr_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {per_addr_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {per_addr_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {per_addr_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {per_addr_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {per_din_i[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {per_din_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {per_din_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {per_din_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {per_din_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {per_din_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {per_din_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {per_din_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {per_din_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {per_din_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {per_din_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {per_din_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {per_din_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {per_din_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {per_din_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {per_din_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {per_we_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {per_we_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {vid_ram_dout_i[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {vid_ram_dout_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {vid_ram_dout_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {vid_ram_dout_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {vid_ram_dout_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {vid_ram_dout_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {vid_ram_dout_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {vid_ram_dout_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {vid_ram_dout_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {vid_ram_dout_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {vid_ram_dout_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {vid_ram_dout_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {vid_ram_dout_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {vid_ram_dout_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {vid_ram_dout_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {vid_ram_dout_i[0]}]
set_timing_derate -early 0.9500
set_timing_derate -late 1.0500
###############################################################################
# Design Rules
###############################################################################
set_max_fanout 5.0000 [current_design]