tree 95f67289299d839d7e54aefd5bd9fd07ec3d054f
parent b9b38f09fb86da62163158ba69f0ec01aa27032a
author Ian Zhang <ianzhang1986@gmail.com> 1661702713 -0700
committer GitHub <noreply@github.com> 1661702713 -0700
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External input ctrl (#6)

* Add end to end read out logic and testing

Fix verilog inference errors

Attempt to add state control

Signed-off-by: ianboyanzhang

Fix errors reported by yosys

* Fix openlane layout config (#5)