blob: af6f9b45381d0ba95aa9d7c60b8efab1c5548b04 [file]
Project Chip ID is: 483166
Setting Project Chip ID to: 00075f5e
Step 1: Modify Layout of the user_id_programming subcell
Done!
Step 2: Add user project ID parameter to source verilog.
Done!
Step 3: Add user project ID parameter to gate-level verilog.
Done!
Step 4: Add user project ID text to top level layout.
Done!