timestamp 1669950137
version 8.3
tech sky130A
style ngspice()
scale 1000 1 500000
resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
use VGA_routing VGA_routing_0 1 0 280 0 1 -18
use VCO VCO_1 0 1 115536 -1 0 464188
use VCO VCO_0 1 0 -7837 0 1 638742
use TX_line TX_line_0 1 0 200000 0 1 464000
use BGR_lvs BGR_lvs_0 1 0 254230 0 1 568403
port "io_analog[4]" 41 329294 702300 334294 704800 m5
port "io_analog[4]" 47 318994 702300 323994 704800 m5
port "io_analog[5]" 42 227594 702300 232594 704800 m5
port "io_analog[5]" 48 217294 702300 222294 704800 m5
port "io_analog[6]" 43 175894 702300 180894 704800 m5
port "io_analog[6]" 49 165594 702300 170594 704800 m5
port "io_analog[4]" 41 329294 702300 334294 704800 m4
port "io_analog[4]" 47 318994 702300 323994 704800 m4
port "io_analog[5]" 42 227594 702300 232594 704800 m4
port "io_analog[5]" 48 217294 702300 222294 704800 m4
port "io_in_3v3[0]" 83 583520 1544 584800 1656 m3
port "io_oeb[26]" 128 -800 1544 480 1656 m3
port "io_in[0]" 56 583520 2726 584800 2838 m3
port "io_out[26]" 155 -800 2726 480 2838 m3
port "io_out[0]" 137 583520 3908 584800 4020 m3
port "io_in[26]" 74 -800 3908 480 4020 m3
port "io_oeb[0]" 110 583520 5090 584800 5202 m3
port "io_in_3v3[26]" 101 -800 5090 480 5202 m3
port "io_in_3v3[1]" 94 583520 6272 584800 6384 m3
port "io_oeb[25]" 127 -800 6272 480 6384 m3
port "io_in[1]" 67 583520 7454 584800 7566 m3
port "io_out[25]" 154 -800 7454 480 7566 m3
port "io_out[1]" 148 583520 8636 584800 8748 m3
port "io_in[25]" 73 -800 8636 480 8748 m3
port "io_oeb[1]" 121 583520 9818 584800 9930 m3
port "io_in_3v3[25]" 100 -800 9818 480 9930 m3
port "io_in_3v3[2]" 102 583520 11000 584800 11112 m3
port "io_oeb[24]" 126 -800 11000 480 11112 m3
port "io_in[2]" 75 583520 12182 584800 12294 m3
port "io_out[24]" 153 -800 12182 480 12294 m3
port "io_out[2]" 156 583520 13364 584800 13476 m3
port "io_in[24]" 72 -800 13364 480 13476 m3
port "io_oeb[2]" 129 583520 14546 584800 14658 m3
port "io_in_3v3[24]" 99 -800 14546 480 14658 m3
port "io_in_3v3[3]" 103 583520 15728 584800 15840 m3
port "gpio_noesd[17]" 26 -800 15728 480 15840 m3
port "io_in[3]" 76 583520 16910 584800 17022 m3
port "gpio_analog[17]" 8 -800 16910 480 17022 m3
port "io_out[3]" 157 583520 18092 584800 18204 m3
port "io_oeb[3]" 130 583520 19274 584800 19386 m3
port "io_in_3v3[4]" 104 583520 20456 584800 20568 m3
port "io_in[4]" 77 583520 21638 584800 21750 m3
port "io_out[4]" 158 583520 22820 584800 22932 m3
port "io_oeb[4]" 131 583520 24002 584800 24114 m3
port "io_oeb[23]" 125 -800 32422 480 32534 m3
port "io_out[23]" 152 -800 33604 480 33716 m3
port "io_in[23]" 71 -800 34786 480 34898 m3
port "io_in_3v3[23]" 98 -800 35968 480 36080 m3
port "gpio_noesd[16]" 25 -800 37150 480 37262 m3
port "gpio_analog[16]" 7 -800 38332 480 38444 m3
port "io_in_3v3[5]" 105 583520 46914 584800 47026 m3
port "io_in[5]" 78 583520 48096 584800 48208 m3
port "io_out[5]" 159 583520 49278 584800 49390 m3
port "io_oeb[5]" 132 583520 50460 584800 50572 m3
port "io_oeb[22]" 124 -800 75644 480 75756 m3
port "io_out[22]" 151 -800 76826 480 76938 m3
port "io_in[22]" 70 -800 78008 480 78120 m3
port "io_in_3v3[22]" 97 -800 79190 480 79302 m3
port "gpio_noesd[15]" 24 -800 80372 480 80484 m3
port "gpio_analog[15]" 6 -800 81554 480 81666 m3
port "io_in_3v3[6]" 106 583520 91572 584800 91684 m3
port "io_in[6]" 79 583520 92754 584800 92866 m3
port "io_out[6]" 160 583520 93936 584800 94048 m3
port "io_oeb[6]" 133 583520 95118 584800 95230 m3
port "io_oeb[21]" 123 -800 118866 480 118978 m3
port "io_out[21]" 150 -800 120048 480 120160 m3
port "io_in[21]" 69 -800 121230 480 121342 m3
port "io_in_3v3[21]" 96 -800 122412 480 122524 m3
port "gpio_noesd[14]" 23 -800 123594 480 123706 m3
port "gpio_analog[14]" 5 -800 124776 480 124888 m3
port "vssa1" 565 582340 136830 584800 141630 m3
port "vssa1" 564 582340 146830 584800 151630 m3
port "vssd2" 571 0 162888 1660 167688 m3
port "vssd2" 570 0 172888 1660 177688 m3
port "vssd1" 569 582340 181430 584800 186230 m3
port "vssd1" 568 582340 191430 584800 196230 m3
port "vdda2" 561 0 214888 1660 219688 m3
port "vdda2" 560 0 204888 1660 209688 m3
port "vdda1" 559 582340 225230 584800 230030 m3
port "vdda1" 558 582340 235230 584800 240030 m3
port "io_oeb[20]" 122 -800 246488 480 246600 m3
port "io_out[20]" 149 -800 247670 480 247782 m3
port "io_in[20]" 68 -800 248852 480 248964 m3
port "io_in_3v3[20]" 95 -800 250034 480 250146 m3
port "gpio_noesd[13]" 22 -800 251216 480 251328 m3
port "gpio_analog[13]" 4 -800 252398 480 252510 m3
port "gpio_analog[0]" 0 583520 269230 584800 269342 m3
port "gpio_noesd[0]" 18 583520 270412 584800 270524 m3
port "io_in_3v3[7]" 107 583520 271594 584800 271706 m3
port "io_in[7]" 80 583520 272776 584800 272888 m3
port "io_out[7]" 161 583520 273958 584800 274070 m3
port "io_oeb[7]" 134 583520 275140 584800 275252 m3
port "io_oeb[19]" 120 -800 289510 480 289622 m3
port "io_out[19]" 147 -800 290692 480 290804 m3
port "io_in_3v3[19]" 93 -800 293056 480 293168 m3
port "gpio_noesd[12]" 21 -800 294238 480 294350 m3
port "gpio_analog[12]" 3 -800 295420 480 295532 m3
port "gpio_analog[1]" 9 583520 313652 584800 313764 m3
port "gpio_noesd[1]" 27 583520 314834 584800 314946 m3
port "io_in_3v3[8]" 108 583520 316016 584800 316128 m3
port "io_in[8]" 81 583520 317198 584800 317310 m3
port "io_out[8]" 162 583520 318380 584800 318492 m3
port "io_oeb[8]" 135 583520 319562 584800 319674 m3
port "io_oeb[18]" 119 -800 332732 480 332844 m3
port "io_out[18]" 146 -800 333914 480 334026 m3
port "io_in_3v3[18]" 92 -800 336278 480 336390 m3
port "gpio_noesd[11]" 20 -800 337460 480 337572 m3
port "gpio_analog[11]" 2 -800 338642 480 338754 m3
port "gpio_analog[2]" 10 583520 358874 584800 358986 m3
port "gpio_noesd[2]" 28 583520 360056 584800 360168 m3
port "io_in_3v3[9]" 109 583520 361238 584800 361350 m3
port "io_in[9]" 82 583520 362420 584800 362532 m3
port "io_out[9]" 163 583520 363602 584800 363714 m3
port "io_oeb[9]" 136 583520 364784 584800 364896 m3
port "gpio_analog[3]" 11 583520 405296 584800 405408 m3
port "gpio_noesd[3]" 29 583520 406478 584800 406590 m3
port "io_in_3v3[10]" 84 583520 407660 584800 407772 m3
port "io_in[10]" 57 583520 408842 584800 408954 m3
port "io_out[10]" 138 583520 410024 584800 410136 m3
port "io_oeb[10]" 111 583520 411206 584800 411318 m3
port "io_oeb[17]" 118 -800 375954 480 376066 m3
port "io_out[17]" 145 -800 377136 480 377248 m3
port "io_in_3v3[17]" 91 -800 379500 480 379612 m3
port "gpio_noesd[10]" 19 -800 380682 480 380794 m3
port "gpio_analog[10]" 1 -800 381864 480 381976 m3
port "gpio_analog[4]" 12 583520 449718 584800 449830 m3
port "gpio_noesd[4]" 30 583520 450900 584800 451012 m3
port "io_in_3v3[11]" 85 583520 452082 584800 452194 m3
port "io_in[11]" 58 583520 453264 584800 453376 m3
port "io_out[11]" 139 583520 454446 584800 454558 m3
port "io_oeb[11]" 112 583520 455628 584800 455740 m3
port "io_oeb[16]" 117 -800 419176 480 419288 m3
port "io_out[16]" 144 -800 420358 480 420470 m3
port "io_in_3v3[16]" 90 -800 422722 480 422834 m3
port "gpio_noesd[9]" 35 -800 423904 480 424016 m3
port "gpio_analog[9]" 17 -800 425086 480 425198 m3
port "io_oeb[15]" 116 -800 462398 480 462510 m3
port "io_out[15]" 143 -800 463580 480 463692 m3
port "io_in[15]" 62 -800 464762 480 464874 m3
port "gpio_noesd[8]" 34 -800 467126 480 467238 m3
port "gpio_analog[8]" 16 -800 468308 480 468420 m3
port "gpio_analog[5]" 13 583520 494140 584800 494252 m3
port "gpio_noesd[5]" 31 583520 495322 584800 495434 m3
port "io_in_3v3[12]" 86 583520 496504 584800 496616 m3
port "io_in[12]" 59 583520 497686 584800 497798 m3
port "io_out[12]" 140 583520 498868 584800 498980 m3
port "io_oeb[12]" 113 583520 500050 584800 500162 m3
port "io_oeb[14]" 115 -800 505620 480 505732 m3
port "io_out[14]" 142 -800 506802 480 506914 m3
port "io_in[14]" 61 -800 507984 480 508096 m3
port "io_in_3v3[14]" 88 -800 509166 480 509278 m3
port "gpio_noesd[7]" 33 -800 510348 480 510460 m3
port "vdda1" 556 582340 540562 584800 545362 m3
port "vdda1" 557 582340 550562 584800 555362 m3
port "vssa2" 567 0 549442 1660 554242 m3
port "vssa2" 566 0 559442 1660 564242 m3
port "gpio_analog[6]" 14 583520 583562 584800 583674 m3
port "gpio_noesd[6]" 32 583520 584744 584800 584856 m3
port "io_in_3v3[13]" 87 583520 585926 584800 586038 m3
port "io_in[13]" 60 583520 587108 584800 587220 m3
port "io_out[13]" 141 583520 588290 584800 588402 m3
port "io_oeb[13]" 114 583520 589472 584800 589584 m3
port "gpio_analog[7]" 15 -800 511530 480 511642 m3
port "vccd1" 553 582340 629784 584800 634584 m3
port "vccd1" 552 582340 639784 584800 644584 m3
port "io_analog[0]" 36 582300 677984 584800 682984 m3
port "io_analog[1]" 38 566594 702300 571594 704800 m3
port "vssa1" 562 520594 702340 525394 704800 m3
port "vssa1" 563 510594 702340 515394 704800 m3
port "io_analog[2]" 39 465394 702300 470394 704800 m3
port "io_analog[3]" 40 413394 702300 418394 704800 m3
port "io_analog[4]" 41 329294 702300 334294 704800 m3
port "io_clamp_high[0]" 50 326794 702300 328994 704800 m3
port "io_clamp_low[0]" 53 324294 702300 326494 704800 m3
port "io_analog[4]" 47 318994 702300 323994 704800 m3
port "io_analog[5]" 42 227594 702300 232594 704800 m3
port "io_clamp_high[1]" 51 225094 702300 227294 704800 m3
port "io_clamp_low[1]" 54 222594 702300 224794 704800 m3
port "io_analog[5]" 48 217294 702300 222294 704800 m3
port "io_analog[6]" 43 175894 702300 180894 704800 m3
port "io_clamp_high[2]" 52 173394 702300 175594 704800 m3
port "io_clamp_low[2]" 55 170894 702300 173094 704800 m3
port "io_analog[6]" 49 165594 702300 170594 704800 m3
port "vccd2" 555 0 633842 1660 638642 m3
port "vccd2" 554 0 643842 1660 648642 m3
port "io_analog[7]" 44 120194 702300 125194 704800 m3
port "io_analog[8]" 45 68194 702300 73194 704800 m3
port "io_analog[9]" 46 16194 702300 21194 704800 m3
port "user_irq[2]" 551 583250 -800 583362 480 m2
port "user_irq[1]" 550 582068 -800 582180 480 m2
port "user_irq[0]" 549 580886 -800 580998 480 m2
port "user_clock2" 548 579704 -800 579816 480 m2
port "la_oenb[127]" 450 578522 -800 578634 480 m2
port "la_data_out[127]" 322 577340 -800 577452 480 m2
port "la_data_in[127]" 194 576158 -800 576270 480 m2
port "la_oenb[126]" 449 574976 -800 575088 480 m2
port "la_data_out[126]" 321 573794 -800 573906 480 m2
port "la_data_in[126]" 193 572612 -800 572724 480 m2
port "la_oenb[125]" 448 571430 -800 571542 480 m2
port "la_data_out[125]" 320 570248 -800 570360 480 m2
port "la_data_in[125]" 192 569066 -800 569178 480 m2
port "la_oenb[124]" 447 567884 -800 567996 480 m2
port "la_data_out[124]" 319 566702 -800 566814 480 m2
port "la_data_in[124]" 191 565520 -800 565632 480 m2
port "la_oenb[123]" 446 564338 -800 564450 480 m2
port "la_data_out[123]" 318 563156 -800 563268 480 m2
port "la_data_in[123]" 190 561974 -800 562086 480 m2
port "la_oenb[122]" 445 560792 -800 560904 480 m2
port "la_data_out[122]" 317 559610 -800 559722 480 m2
port "la_data_in[122]" 189 558428 -800 558540 480 m2
port "la_oenb[121]" 444 557246 -800 557358 480 m2
port "la_data_out[121]" 316 556064 -800 556176 480 m2
port "la_data_in[121]" 188 554882 -800 554994 480 m2
port "la_oenb[120]" 443 553700 -800 553812 480 m2
port "la_data_out[120]" 315 552518 -800 552630 480 m2
port "la_data_in[120]" 187 551336 -800 551448 480 m2
port "la_oenb[119]" 441 550154 -800 550266 480 m2
port "la_data_out[119]" 313 548972 -800 549084 480 m2
port "la_data_in[119]" 185 547790 -800 547902 480 m2
port "la_oenb[118]" 440 546608 -800 546720 480 m2
port "la_data_out[118]" 312 545426 -800 545538 480 m2
port "la_data_in[118]" 184 544244 -800 544356 480 m2
port "la_oenb[117]" 439 543062 -800 543174 480 m2
port "la_data_out[117]" 311 541880 -800 541992 480 m2
port "la_data_in[117]" 183 540698 -800 540810 480 m2
port "la_oenb[116]" 438 539516 -800 539628 480 m2
port "la_data_out[116]" 310 538334 -800 538446 480 m2
port "la_data_in[116]" 182 537152 -800 537264 480 m2
port "la_oenb[115]" 437 535970 -800 536082 480 m2
port "la_data_out[115]" 309 534788 -800 534900 480 m2
port "la_data_in[115]" 181 533606 -800 533718 480 m2
port "la_oenb[114]" 436 532424 -800 532536 480 m2
port "la_data_out[114]" 308 531242 -800 531354 480 m2
port "la_data_in[114]" 180 530060 -800 530172 480 m2
port "la_oenb[113]" 435 528878 -800 528990 480 m2
port "la_data_out[113]" 307 527696 -800 527808 480 m2
port "la_data_in[113]" 179 526514 -800 526626 480 m2
port "la_oenb[112]" 434 525332 -800 525444 480 m2
port "la_data_out[112]" 306 524150 -800 524262 480 m2
port "la_data_in[112]" 178 522968 -800 523080 480 m2
port "la_oenb[111]" 433 521786 -800 521898 480 m2
port "la_data_out[111]" 305 520604 -800 520716 480 m2
port "la_data_in[111]" 177 519422 -800 519534 480 m2
port "la_oenb[110]" 432 518240 -800 518352 480 m2
port "la_data_out[110]" 304 517058 -800 517170 480 m2
port "la_data_in[110]" 176 515876 -800 515988 480 m2
port "la_oenb[109]" 430 514694 -800 514806 480 m2
port "la_data_out[109]" 302 513512 -800 513624 480 m2
port "la_data_in[109]" 174 512330 -800 512442 480 m2
port "la_oenb[108]" 429 511148 -800 511260 480 m2
port "la_data_out[108]" 301 509966 -800 510078 480 m2
port "la_data_in[108]" 173 508784 -800 508896 480 m2
port "la_oenb[107]" 428 507602 -800 507714 480 m2
port "la_data_out[107]" 300 506420 -800 506532 480 m2
port "la_data_in[107]" 172 505238 -800 505350 480 m2
port "la_oenb[106]" 427 504056 -800 504168 480 m2
port "la_data_out[106]" 299 502874 -800 502986 480 m2
port "la_data_in[106]" 171 501692 -800 501804 480 m2
port "la_oenb[105]" 426 500510 -800 500622 480 m2
port "la_data_out[105]" 298 499328 -800 499440 480 m2
port "la_data_in[105]" 170 498146 -800 498258 480 m2
port "la_oenb[104]" 425 496964 -800 497076 480 m2
port "la_data_out[104]" 297 495782 -800 495894 480 m2
port "la_data_in[104]" 169 494600 -800 494712 480 m2
port "la_oenb[103]" 424 493418 -800 493530 480 m2
port "la_data_out[103]" 296 492236 -800 492348 480 m2
port "la_data_in[103]" 168 491054 -800 491166 480 m2
port "la_oenb[102]" 423 489872 -800 489984 480 m2
port "la_data_out[102]" 295 488690 -800 488802 480 m2
port "la_data_in[102]" 167 487508 -800 487620 480 m2
port "la_oenb[101]" 422 486326 -800 486438 480 m2
port "la_data_out[101]" 294 485144 -800 485256 480 m2
port "la_data_in[101]" 166 483962 -800 484074 480 m2
port "la_oenb[100]" 421 482780 -800 482892 480 m2
port "la_data_out[100]" 293 481598 -800 481710 480 m2
port "la_data_in[100]" 165 480416 -800 480528 480 m2
port "la_oenb[99]" 546 479234 -800 479346 480 m2
port "la_data_out[99]" 418 478052 -800 478164 480 m2
port "la_data_in[99]" 290 476870 -800 476982 480 m2
port "la_oenb[98]" 545 475688 -800 475800 480 m2
port "la_data_out[98]" 417 474506 -800 474618 480 m2
port "la_data_in[98]" 289 473324 -800 473436 480 m2
port "la_oenb[97]" 544 472142 -800 472254 480 m2
port "la_data_out[97]" 416 470960 -800 471072 480 m2
port "la_data_in[97]" 288 469778 -800 469890 480 m2
port "la_oenb[96]" 543 468596 -800 468708 480 m2
port "la_data_out[96]" 415 467414 -800 467526 480 m2
port "la_data_in[96]" 287 466232 -800 466344 480 m2
port "la_oenb[95]" 542 465050 -800 465162 480 m2
port "la_data_out[95]" 414 463868 -800 463980 480 m2
port "la_data_in[95]" 286 462686 -800 462798 480 m2
port "la_oenb[94]" 541 461504 -800 461616 480 m2
port "la_data_out[94]" 413 460322 -800 460434 480 m2
port "la_data_in[94]" 285 459140 -800 459252 480 m2
port "la_oenb[93]" 540 457958 -800 458070 480 m2
port "la_data_out[93]" 412 456776 -800 456888 480 m2
port "la_data_in[93]" 284 455594 -800 455706 480 m2
port "la_oenb[92]" 539 454412 -800 454524 480 m2
port "la_data_out[92]" 411 453230 -800 453342 480 m2
port "la_data_in[92]" 283 452048 -800 452160 480 m2
port "la_oenb[91]" 538 450866 -800 450978 480 m2
port "la_data_out[91]" 410 449684 -800 449796 480 m2
port "la_data_in[91]" 282 448502 -800 448614 480 m2
port "la_oenb[90]" 537 447320 -800 447432 480 m2
port "la_data_out[90]" 409 446138 -800 446250 480 m2
port "la_data_in[90]" 281 444956 -800 445068 480 m2
port "la_oenb[89]" 535 443774 -800 443886 480 m2
port "la_data_out[89]" 407 442592 -800 442704 480 m2
port "la_data_in[89]" 279 441410 -800 441522 480 m2
port "la_oenb[88]" 534 440228 -800 440340 480 m2
port "la_data_out[88]" 406 439046 -800 439158 480 m2
port "la_data_in[88]" 278 437864 -800 437976 480 m2
port "la_oenb[87]" 533 436682 -800 436794 480 m2
port "la_data_out[87]" 405 435500 -800 435612 480 m2
port "la_data_in[87]" 277 434318 -800 434430 480 m2
port "la_oenb[86]" 532 433136 -800 433248 480 m2
port "la_data_out[86]" 404 431954 -800 432066 480 m2
port "la_data_in[86]" 276 430772 -800 430884 480 m2
port "la_oenb[85]" 531 429590 -800 429702 480 m2
port "la_data_out[85]" 403 428408 -800 428520 480 m2
port "la_data_in[85]" 275 427226 -800 427338 480 m2
port "la_oenb[84]" 530 426044 -800 426156 480 m2
port "la_data_out[84]" 402 424862 -800 424974 480 m2
port "la_data_in[84]" 274 423680 -800 423792 480 m2
port "la_oenb[83]" 529 422498 -800 422610 480 m2
port "la_data_out[83]" 401 421316 -800 421428 480 m2
port "la_data_in[83]" 273 420134 -800 420246 480 m2
port "la_oenb[82]" 528 418952 -800 419064 480 m2
port "la_data_out[82]" 400 417770 -800 417882 480 m2
port "la_data_in[82]" 272 416588 -800 416700 480 m2
port "la_oenb[81]" 527 415406 -800 415518 480 m2
port "la_data_out[81]" 399 414224 -800 414336 480 m2
port "la_data_in[81]" 271 413042 -800 413154 480 m2
port "la_oenb[80]" 526 411860 -800 411972 480 m2
port "la_data_out[80]" 398 410678 -800 410790 480 m2
port "la_data_in[80]" 270 409496 -800 409608 480 m2
port "la_oenb[79]" 524 408314 -800 408426 480 m2
port "la_data_out[79]" 396 407132 -800 407244 480 m2
port "la_data_in[79]" 268 405950 -800 406062 480 m2
port "la_oenb[78]" 523 404768 -800 404880 480 m2
port "la_data_out[78]" 395 403586 -800 403698 480 m2
port "la_data_in[78]" 267 402404 -800 402516 480 m2
port "la_oenb[77]" 522 401222 -800 401334 480 m2
port "la_data_out[77]" 394 400040 -800 400152 480 m2
port "la_data_in[77]" 266 398858 -800 398970 480 m2
port "la_oenb[76]" 521 397676 -800 397788 480 m2
port "la_data_out[76]" 393 396494 -800 396606 480 m2
port "la_data_in[76]" 265 395312 -800 395424 480 m2
port "la_oenb[75]" 520 394130 -800 394242 480 m2
port "la_data_out[75]" 392 392948 -800 393060 480 m2
port "la_data_in[75]" 264 391766 -800 391878 480 m2
port "la_oenb[74]" 519 390584 -800 390696 480 m2
port "la_data_out[74]" 391 389402 -800 389514 480 m2
port "la_data_in[74]" 263 388220 -800 388332 480 m2
port "la_oenb[73]" 518 387038 -800 387150 480 m2
port "la_data_out[73]" 390 385856 -800 385968 480 m2
port "la_data_in[73]" 262 384674 -800 384786 480 m2
port "la_oenb[72]" 517 383492 -800 383604 480 m2
port "la_data_out[72]" 389 382310 -800 382422 480 m2
port "la_data_in[72]" 261 381128 -800 381240 480 m2
port "la_oenb[71]" 516 379946 -800 380058 480 m2
port "la_data_out[71]" 388 378764 -800 378876 480 m2
port "la_data_in[71]" 260 377582 -800 377694 480 m2
port "la_oenb[70]" 515 376400 -800 376512 480 m2
port "la_data_out[70]" 387 375218 -800 375330 480 m2
port "la_data_in[70]" 259 374036 -800 374148 480 m2
port "la_oenb[69]" 513 372854 -800 372966 480 m2
port "la_data_out[69]" 385 371672 -800 371784 480 m2
port "la_data_in[69]" 257 370490 -800 370602 480 m2
port "la_oenb[68]" 512 369308 -800 369420 480 m2
port "la_data_out[68]" 384 368126 -800 368238 480 m2
port "la_data_in[68]" 256 366944 -800 367056 480 m2
port "la_oenb[67]" 511 365762 -800 365874 480 m2
port "la_data_out[67]" 383 364580 -800 364692 480 m2
port "la_data_in[67]" 255 363398 -800 363510 480 m2
port "la_oenb[66]" 510 362216 -800 362328 480 m2
port "la_data_out[66]" 382 361034 -800 361146 480 m2
port "la_data_in[66]" 254 359852 -800 359964 480 m2
port "la_oenb[65]" 509 358670 -800 358782 480 m2
port "la_data_out[65]" 381 357488 -800 357600 480 m2
port "la_data_in[65]" 253 356306 -800 356418 480 m2
port "la_oenb[64]" 508 355124 -800 355236 480 m2
port "la_data_out[64]" 380 353942 -800 354054 480 m2
port "la_data_in[64]" 252 352760 -800 352872 480 m2
port "la_oenb[63]" 507 351578 -800 351690 480 m2
port "la_data_out[63]" 379 350396 -800 350508 480 m2
port "la_data_in[63]" 251 349214 -800 349326 480 m2
port "la_oenb[62]" 506 348032 -800 348144 480 m2
port "la_data_out[62]" 378 346850 -800 346962 480 m2
port "la_data_in[62]" 250 345668 -800 345780 480 m2
port "la_oenb[61]" 505 344486 -800 344598 480 m2
port "la_data_out[61]" 377 343304 -800 343416 480 m2
port "la_data_in[61]" 249 342122 -800 342234 480 m2
port "la_oenb[60]" 504 340940 -800 341052 480 m2
port "la_data_out[60]" 376 339758 -800 339870 480 m2
port "la_data_in[60]" 248 338576 -800 338688 480 m2
port "la_oenb[59]" 502 337394 -800 337506 480 m2
port "la_data_out[59]" 374 336212 -800 336324 480 m2
port "la_data_in[59]" 246 335030 -800 335142 480 m2
port "la_oenb[58]" 501 333848 -800 333960 480 m2
port "la_data_out[58]" 373 332666 -800 332778 480 m2
port "la_data_in[58]" 245 331484 -800 331596 480 m2
port "la_oenb[57]" 500 330302 -800 330414 480 m2
port "la_data_out[57]" 372 329120 -800 329232 480 m2
port "la_data_in[57]" 244 327938 -800 328050 480 m2
port "la_oenb[56]" 499 326756 -800 326868 480 m2
port "la_data_out[56]" 371 325574 -800 325686 480 m2
port "la_data_in[56]" 243 324392 -800 324504 480 m2
port "la_oenb[55]" 498 323210 -800 323322 480 m2
port "la_data_out[55]" 370 322028 -800 322140 480 m2
port "la_data_in[55]" 242 320846 -800 320958 480 m2
port "la_oenb[54]" 497 319664 -800 319776 480 m2
port "la_data_out[54]" 369 318482 -800 318594 480 m2
port "la_data_in[54]" 241 317300 -800 317412 480 m2
port "la_oenb[53]" 496 316118 -800 316230 480 m2
port "la_data_out[53]" 368 314936 -800 315048 480 m2
port "la_data_in[53]" 240 313754 -800 313866 480 m2
port "la_oenb[52]" 495 312572 -800 312684 480 m2
port "la_data_out[52]" 367 311390 -800 311502 480 m2
port "la_data_in[52]" 239 310208 -800 310320 480 m2
port "la_oenb[51]" 494 309026 -800 309138 480 m2
port "la_data_out[51]" 366 307844 -800 307956 480 m2
port "la_data_in[51]" 238 306662 -800 306774 480 m2
port "la_oenb[50]" 493 305480 -800 305592 480 m2
port "la_data_out[50]" 365 304298 -800 304410 480 m2
port "la_data_in[50]" 237 303116 -800 303228 480 m2
port "la_oenb[49]" 491 301934 -800 302046 480 m2
port "la_data_out[49]" 363 300752 -800 300864 480 m2
port "la_data_in[49]" 235 299570 -800 299682 480 m2
port "la_oenb[48]" 490 298388 -800 298500 480 m2
port "la_data_out[48]" 362 297206 -800 297318 480 m2
port "la_data_in[48]" 234 296024 -800 296136 480 m2
port "la_oenb[47]" 489 294842 -800 294954 480 m2
port "la_data_out[47]" 361 293660 -800 293772 480 m2
port "la_data_in[47]" 233 292478 -800 292590 480 m2
port "la_oenb[46]" 488 291296 -800 291408 480 m2
port "la_data_out[46]" 360 290114 -800 290226 480 m2
port "la_data_in[46]" 232 288932 -800 289044 480 m2
port "la_oenb[45]" 487 287750 -800 287862 480 m2
port "la_data_out[45]" 359 286568 -800 286680 480 m2
port "la_data_in[45]" 231 285386 -800 285498 480 m2
port "la_oenb[44]" 486 284204 -800 284316 480 m2
port "la_data_out[44]" 358 283022 -800 283134 480 m2
port "la_data_in[44]" 230 281840 -800 281952 480 m2
port "la_oenb[43]" 485 280658 -800 280770 480 m2
port "la_data_out[43]" 357 279476 -800 279588 480 m2
port "la_data_in[43]" 229 278294 -800 278406 480 m2
port "la_oenb[42]" 484 277112 -800 277224 480 m2
port "la_data_out[42]" 356 275930 -800 276042 480 m2
port "la_data_in[42]" 228 274748 -800 274860 480 m2
port "la_oenb[41]" 483 273566 -800 273678 480 m2
port "la_data_out[41]" 355 272384 -800 272496 480 m2
port "la_data_in[41]" 227 271202 -800 271314 480 m2
port "la_oenb[40]" 482 270020 -800 270132 480 m2
port "la_data_out[40]" 354 268838 -800 268950 480 m2
port "la_data_in[40]" 226 267656 -800 267768 480 m2
port "la_oenb[39]" 480 266474 -800 266586 480 m2
port "la_data_out[39]" 352 265292 -800 265404 480 m2
port "la_data_in[39]" 224 264110 -800 264222 480 m2
port "la_oenb[38]" 479 262928 -800 263040 480 m2
port "la_data_out[38]" 351 261746 -800 261858 480 m2
port "la_data_in[38]" 223 260564 -800 260676 480 m2
port "la_oenb[37]" 478 259382 -800 259494 480 m2
port "la_data_out[37]" 350 258200 -800 258312 480 m2
port "la_data_in[37]" 222 257018 -800 257130 480 m2
port "la_oenb[36]" 477 255836 -800 255948 480 m2
port "la_data_out[36]" 349 254654 -800 254766 480 m2
port "la_data_in[36]" 221 253472 -800 253584 480 m2
port "la_oenb[35]" 476 252290 -800 252402 480 m2
port "la_data_out[35]" 348 251108 -800 251220 480 m2
port "la_data_in[35]" 220 249926 -800 250038 480 m2
port "la_oenb[34]" 475 248744 -800 248856 480 m2
port "la_data_out[34]" 347 247562 -800 247674 480 m2
port "la_data_in[34]" 219 246380 -800 246492 480 m2
port "la_oenb[33]" 474 245198 -800 245310 480 m2
port "la_data_out[33]" 346 244016 -800 244128 480 m2
port "la_data_in[33]" 218 242834 -800 242946 480 m2
port "la_oenb[32]" 473 241652 -800 241764 480 m2
port "la_data_out[32]" 345 240470 -800 240582 480 m2
port "la_data_in[32]" 217 239288 -800 239400 480 m2
port "la_oenb[31]" 472 238106 -800 238218 480 m2
port "la_data_out[31]" 344 236924 -800 237036 480 m2
port "la_data_in[31]" 216 235742 -800 235854 480 m2
port "la_oenb[30]" 471 234560 -800 234672 480 m2
port "la_data_out[30]" 343 233378 -800 233490 480 m2
port "la_data_in[30]" 215 232196 -800 232308 480 m2
port "la_oenb[29]" 469 231014 -800 231126 480 m2
port "la_data_out[29]" 341 229832 -800 229944 480 m2
port "la_data_in[29]" 213 228650 -800 228762 480 m2
port "la_oenb[28]" 468 227468 -800 227580 480 m2
port "la_data_out[28]" 340 226286 -800 226398 480 m2
port "la_data_in[28]" 212 225104 -800 225216 480 m2
port "la_oenb[27]" 467 223922 -800 224034 480 m2
port "la_data_out[27]" 339 222740 -800 222852 480 m2
port "la_data_in[27]" 211 221558 -800 221670 480 m2
port "la_oenb[26]" 466 220376 -800 220488 480 m2
port "la_data_out[26]" 338 219194 -800 219306 480 m2
port "la_data_in[26]" 210 218012 -800 218124 480 m2
port "la_oenb[25]" 465 216830 -800 216942 480 m2
port "la_data_out[25]" 337 215648 -800 215760 480 m2
port "la_data_in[25]" 209 214466 -800 214578 480 m2
port "la_oenb[24]" 464 213284 -800 213396 480 m2
port "la_data_out[24]" 336 212102 -800 212214 480 m2
port "la_data_in[24]" 208 210920 -800 211032 480 m2
port "la_oenb[23]" 463 209738 -800 209850 480 m2
port "la_data_out[23]" 335 208556 -800 208668 480 m2
port "la_data_in[23]" 207 207374 -800 207486 480 m2
port "la_oenb[22]" 462 206192 -800 206304 480 m2
port "la_data_out[22]" 334 205010 -800 205122 480 m2
port "la_data_in[22]" 206 203828 -800 203940 480 m2
port "la_oenb[21]" 461 202646 -800 202758 480 m2
port "la_data_out[21]" 333 201464 -800 201576 480 m2
port "la_data_in[21]" 205 200282 -800 200394 480 m2
port "la_oenb[20]" 460 199100 -800 199212 480 m2
port "la_data_out[20]" 332 197918 -800 198030 480 m2
port "la_data_in[20]" 204 196736 -800 196848 480 m2
port "la_oenb[19]" 458 195554 -800 195666 480 m2
port "la_data_out[19]" 330 194372 -800 194484 480 m2
port "la_data_in[19]" 202 193190 -800 193302 480 m2
port "la_oenb[18]" 457 192008 -800 192120 480 m2
port "la_data_out[18]" 329 190826 -800 190938 480 m2
port "la_data_in[18]" 201 189644 -800 189756 480 m2
port "la_oenb[17]" 456 188462 -800 188574 480 m2
port "la_data_out[17]" 328 187280 -800 187392 480 m2
port "la_data_in[17]" 200 186098 -800 186210 480 m2
port "la_oenb[16]" 455 184916 -800 185028 480 m2
port "la_data_out[16]" 327 183734 -800 183846 480 m2
port "la_data_in[16]" 199 182552 -800 182664 480 m2
port "la_oenb[15]" 454 181370 -800 181482 480 m2
port "la_data_out[15]" 326 180188 -800 180300 480 m2
port "la_data_in[15]" 198 179006 -800 179118 480 m2
port "la_oenb[14]" 453 177824 -800 177936 480 m2
port "la_data_out[14]" 325 176642 -800 176754 480 m2
port "la_data_in[14]" 197 175460 -800 175572 480 m2
port "la_oenb[13]" 452 174278 -800 174390 480 m2
port "la_data_out[13]" 324 173096 -800 173208 480 m2
port "la_data_in[13]" 196 171914 -800 172026 480 m2
port "la_oenb[12]" 451 170732 -800 170844 480 m2
port "la_data_out[12]" 323 169550 -800 169662 480 m2
port "la_data_in[12]" 195 168368 -800 168480 480 m2
port "la_oenb[11]" 442 167186 -800 167298 480 m2
port "la_data_out[11]" 314 166004 -800 166116 480 m2
port "la_data_in[11]" 186 164822 -800 164934 480 m2
port "la_oenb[10]" 431 163640 -800 163752 480 m2
port "la_data_out[10]" 303 162458 -800 162570 480 m2
port "la_data_in[10]" 175 161276 -800 161388 480 m2
port "la_oenb[9]" 547 160094 -800 160206 480 m2
port "la_data_out[9]" 419 158912 -800 159024 480 m2
port "la_data_in[9]" 291 157730 -800 157842 480 m2
port "la_oenb[8]" 536 156548 -800 156660 480 m2
port "la_data_out[8]" 408 155366 -800 155478 480 m2
port "la_data_in[8]" 280 154184 -800 154296 480 m2
port "la_oenb[7]" 525 153002 -800 153114 480 m2
port "la_data_out[7]" 397 151820 -800 151932 480 m2
port "la_data_in[7]" 269 150638 -800 150750 480 m2
port "la_oenb[6]" 514 149456 -800 149568 480 m2
port "la_data_out[6]" 386 148274 -800 148386 480 m2
port "la_data_in[6]" 258 147092 -800 147204 480 m2
port "la_oenb[5]" 503 145910 -800 146022 480 m2
port "la_data_out[5]" 375 144728 -800 144840 480 m2
port "la_data_in[5]" 247 143546 -800 143658 480 m2
port "la_oenb[4]" 492 142364 -800 142476 480 m2
port "la_data_out[4]" 364 141182 -800 141294 480 m2
port "la_data_in[4]" 236 140000 -800 140112 480 m2
port "la_oenb[3]" 481 138818 -800 138930 480 m2
port "la_data_out[3]" 353 137636 -800 137748 480 m2
port "la_data_in[3]" 225 136454 -800 136566 480 m2
port "la_oenb[2]" 470 135272 -800 135384 480 m2
port "la_data_out[2]" 342 134090 -800 134202 480 m2
port "la_data_in[2]" 214 132908 -800 133020 480 m2
port "la_oenb[1]" 459 131726 -800 131838 480 m2
port "la_data_out[1]" 331 130544 -800 130656 480 m2
port "la_data_in[1]" 203 129362 -800 129474 480 m2
port "la_oenb[0]" 420 128180 -800 128292 480 m2
port "la_data_out[0]" 292 126998 -800 127110 480 m2
port "la_data_in[0]" 164 125816 -800 125928 480 m2
port "wbs_dat_o[31]" 664 124634 -800 124746 480 m2
port "wbs_dat_i[31]" 632 123452 -800 123564 480 m2
port "wbs_adr_i[31]" 599 122270 -800 122382 480 m2
port "wbs_dat_o[30]" 663 121088 -800 121200 480 m2
port "wbs_dat_i[30]" 631 119906 -800 120018 480 m2
port "wbs_adr_i[30]" 598 118724 -800 118836 480 m2
port "wbs_dat_o[29]" 661 117542 -800 117654 480 m2
port "wbs_dat_i[29]" 629 116360 -800 116472 480 m2
port "wbs_adr_i[29]" 596 115178 -800 115290 480 m2
port "wbs_dat_o[28]" 660 113996 -800 114108 480 m2
port "wbs_dat_i[28]" 628 112814 -800 112926 480 m2
port "wbs_adr_i[28]" 595 111632 -800 111744 480 m2
port "wbs_dat_o[27]" 659 110450 -800 110562 480 m2
port "wbs_dat_i[27]" 627 109268 -800 109380 480 m2
port "wbs_adr_i[27]" 594 108086 -800 108198 480 m2
port "wbs_dat_o[26]" 658 106904 -800 107016 480 m2
port "wbs_dat_i[26]" 626 105722 -800 105834 480 m2
port "wbs_adr_i[26]" 593 104540 -800 104652 480 m2
port "wbs_dat_o[25]" 657 103358 -800 103470 480 m2
port "wbs_dat_i[25]" 625 102176 -800 102288 480 m2
port "wbs_adr_i[25]" 592 100994 -800 101106 480 m2
port "wbs_dat_o[24]" 656 99812 -800 99924 480 m2
port "wbs_dat_i[24]" 624 98630 -800 98742 480 m2
port "wbs_adr_i[24]" 591 97448 -800 97560 480 m2
port "wbs_dat_o[23]" 655 96266 -800 96378 480 m2
port "wbs_dat_i[23]" 623 95084 -800 95196 480 m2
port "wbs_adr_i[23]" 590 93902 -800 94014 480 m2
port "wbs_dat_o[22]" 654 92720 -800 92832 480 m2
port "wbs_dat_i[22]" 622 91538 -800 91650 480 m2
port "wbs_adr_i[22]" 589 90356 -800 90468 480 m2
port "wbs_dat_o[21]" 653 89174 -800 89286 480 m2
port "wbs_dat_i[21]" 621 87992 -800 88104 480 m2
port "wbs_adr_i[21]" 588 86810 -800 86922 480 m2
port "wbs_dat_o[20]" 652 85628 -800 85740 480 m2
port "wbs_dat_i[20]" 620 84446 -800 84558 480 m2
port "wbs_adr_i[20]" 587 83264 -800 83376 480 m2
port "wbs_dat_o[19]" 650 82082 -800 82194 480 m2
port "wbs_dat_i[19]" 618 80900 -800 81012 480 m2
port "wbs_adr_i[19]" 585 79718 -800 79830 480 m2
port "wbs_dat_o[18]" 649 78536 -800 78648 480 m2
port "wbs_dat_i[18]" 617 77354 -800 77466 480 m2
port "wbs_adr_i[18]" 584 76172 -800 76284 480 m2
port "wbs_dat_o[17]" 648 74990 -800 75102 480 m2
port "wbs_dat_i[17]" 616 73808 -800 73920 480 m2
port "wbs_adr_i[17]" 583 72626 -800 72738 480 m2
port "wbs_dat_o[16]" 647 71444 -800 71556 480 m2
port "wbs_dat_i[16]" 615 70262 -800 70374 480 m2
port "wbs_adr_i[16]" 582 69080 -800 69192 480 m2
port "wbs_dat_o[15]" 646 67898 -800 68010 480 m2
port "wbs_dat_i[15]" 614 66716 -800 66828 480 m2
port "wbs_adr_i[15]" 581 65534 -800 65646 480 m2
port "wbs_dat_o[14]" 645 64352 -800 64464 480 m2
port "wbs_dat_i[14]" 613 63170 -800 63282 480 m2
port "wbs_adr_i[14]" 580 61988 -800 62100 480 m2
port "wbs_dat_o[13]" 644 60806 -800 60918 480 m2
port "wbs_dat_i[13]" 612 59624 -800 59736 480 m2
port "wbs_adr_i[13]" 579 58442 -800 58554 480 m2
port "wbs_dat_o[12]" 643 57260 -800 57372 480 m2
port "wbs_dat_i[12]" 611 56078 -800 56190 480 m2
port "wbs_adr_i[12]" 578 54896 -800 55008 480 m2
port "wbs_dat_o[11]" 642 53714 -800 53826 480 m2
port "wbs_dat_i[11]" 610 52532 -800 52644 480 m2
port "wbs_adr_i[11]" 577 51350 -800 51462 480 m2
port "wbs_dat_o[10]" 641 50168 -800 50280 480 m2
port "wbs_dat_i[10]" 609 48986 -800 49098 480 m2
port "wbs_adr_i[10]" 576 47804 -800 47916 480 m2
port "wbs_dat_o[9]" 671 46622 -800 46734 480 m2
port "wbs_dat_i[9]" 639 45440 -800 45552 480 m2
port "wbs_adr_i[9]" 606 44258 -800 44370 480 m2
port "wbs_dat_o[8]" 670 43076 -800 43188 480 m2
port "wbs_dat_i[8]" 638 41894 -800 42006 480 m2
port "wbs_adr_i[8]" 605 40712 -800 40824 480 m2
port "wbs_dat_o[7]" 669 39530 -800 39642 480 m2
port "wbs_dat_i[7]" 637 38348 -800 38460 480 m2
port "wbs_adr_i[7]" 604 37166 -800 37278 480 m2
port "wbs_dat_o[6]" 668 35984 -800 36096 480 m2
port "wbs_dat_i[6]" 636 34802 -800 34914 480 m2
port "wbs_adr_i[6]" 603 33620 -800 33732 480 m2
port "wbs_dat_o[5]" 667 32438 -800 32550 480 m2
port "wbs_dat_i[5]" 635 31256 -800 31368 480 m2
port "wbs_adr_i[5]" 602 30074 -800 30186 480 m2
port "wbs_dat_o[4]" 666 28892 -800 29004 480 m2
port "wbs_dat_i[4]" 634 27710 -800 27822 480 m2
port "wbs_adr_i[4]" 601 26528 -800 26640 480 m2
port "wbs_sel_i[3]" 675 25346 -800 25458 480 m2
port "wbs_dat_o[3]" 665 24164 -800 24276 480 m2
port "wbs_dat_i[3]" 633 22982 -800 23094 480 m2
port "wbs_adr_i[3]" 600 21800 -800 21912 480 m2
port "wbs_sel_i[2]" 674 20618 -800 20730 480 m2
port "wbs_dat_o[2]" 662 19436 -800 19548 480 m2
port "wbs_dat_i[2]" 630 18254 -800 18366 480 m2
port "wbs_adr_i[2]" 597 17072 -800 17184 480 m2
port "wbs_sel_i[1]" 673 15890 -800 16002 480 m2
port "wbs_dat_o[1]" 651 14708 -800 14820 480 m2
port "wbs_dat_i[1]" 619 13526 -800 13638 480 m2
port "wbs_adr_i[1]" 586 12344 -800 12456 480 m2
port "wbs_sel_i[0]" 672 11162 -800 11274 480 m2
port "wbs_dat_o[0]" 640 9980 -800 10092 480 m2
port "wbs_dat_i[0]" 608 8798 -800 8910 480 m2
port "wbs_adr_i[0]" 575 7616 -800 7728 480 m2
port "wbs_we_i" 677 6434 -800 6546 480 m2
port "wbs_stb_i" 676 5252 -800 5364 480 m2
port "wbs_cyc_i" 607 4070 -800 4182 480 m2
port "wbs_ack_o" 574 2888 -800 3000 480 m2
port "wb_rst_i" 573 1706 -800 1818 480 m2
port "wb_clk_i" 572 524 -800 636 480 m2
port "io_in[19]" 66 -800 291874 480 291986 m3
port "io_analog[6]" 49 165594 702300 170594 704800 m4
port "io_analog[6]" 43 175894 702300 180894 704800 m4
port "io_in_3v3[15]" 89 -800 465944 480 466056 m3
port "io_in[16]" 63 -800 421540 480 421652 m3
port "io_in[17]" 64 -800 378318 480 378430 m3
port "io_in[18]" 65 -800 335096 480 335208 m3
port "io_analog[10]" 678 0 680242 1700 685242 m3
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node "wbs_dat_i[6]" 1 524.407 34802 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_adr_i[6]" 1 524.407 33620 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_dat_o[5]" 1 524.407 32438 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_dat_i[5]" 1 524.407 31256 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_adr_i[5]" 1 524.407 30074 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_dat_o[4]" 1 524.407 28892 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_dat_i[4]" 1 524.407 27710 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_adr_i[4]" 1 524.407 26528 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_sel_i[3]" 1 524.407 25346 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_dat_o[3]" 1 524.407 24164 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_dat_i[3]" 1 524.407 22982 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_adr_i[3]" 1 524.407 21800 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_sel_i[2]" 1 524.407 20618 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_dat_o[2]" 1 524.407 19436 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_dat_i[2]" 1 524.407 18254 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_adr_i[2]" 1 524.407 17072 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_sel_i[1]" 1 524.407 15890 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_dat_o[1]" 1 524.407 14708 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_dat_i[1]" 1 524.407 13526 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_adr_i[1]" 1 524.407 12344 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_sel_i[0]" 1 524.407 11162 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_dat_o[0]" 1 524.407 9980 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_dat_i[0]" 1 524.407 8798 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_adr_i[0]" 1 524.407 7616 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_we_i" 1 524.407 6434 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_stb_i" 1 524.407 5252 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_cyc_i" 1 524.407 4070 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_ack_o" 1 524.407 2888 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wb_rst_i" 1 524.407 1706 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wb_clk_i" 1 556.373 524 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "io_in[19]" 0 23139 -800 291874 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22400 600 10160400 114160 0 0 0 0 0 0
node "REF2" 2 250050 148000 434000 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2677600 12160 300240000 313600 162000000 326000 0 0 0 0
node "io_analog[6]" 0 706547 175894 702300 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 105920000 43200 738160200 182040 2058031004 281206 58292472 33436 0 0
node "REF" 1 323137 23190 671420 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 442000 4820 570876000 588400 27342000 131820 0 0 0 0
node "CTRL1" 1 115499 56980 660080 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36400 1080 46118000 681920 10352160 116200 0 0 0 0 0 0
equiv "CTRL1" "io_in_3v3[15]"
node "CTRL2" 2 58787.7 56720 399500 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 194800 3960 46081600 681520 10299920 115680 0 0 0 0 0 0
equiv "CTRL2" "io_in[16]"
node "CTRL3" 3 65499.3 56480 399760 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 223600 4440 49187200 726040 10254000 115200 0 0 0 0 0 0
equiv "CTRL3" "io_in[17]"
node "CTRL4" 3 73659.2 56200 400020 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 257200 5000 55396800 814920 10213120 114640 0 0 0 0 0 0
equiv "CTRL4" "io_in[18]"
node "CTRL5" 3 129627 55960 400280 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 283600 5440 61645200 904440 0 0 0 0 0 0 0 0
node "VCTRL" 1 269272 14920 433480 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 147296000 777300 460000 2840 25122400 42440 0 0 0 0 0 0
equiv "VCTRL" "io_analog[10]"
substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
cap "la_oenb[118]" "la_data_in[119]" 56.6372
cap "la_data_out[108]" "la_oenb[108]" 56.6372
cap "la_oenb[59]" "la_data_out[59]" 56.6372
cap "la_oenb[47]" "la_data_out[47]" 56.6372
cap "la_oenb[122]" "la_data_out[122]" 56.6372
cap "la_oenb[20]" "la_data_out[20]" 56.6372
cap "io_oeb[25]" "io_in_3v3[26]" 82.3652
cap "io_in[9]" "io_in_3v3[9]" 82.3652
cap "la_data_in[85]" "la_data_out[85]" 56.6372
cap "la_data_in[33]" "la_data_out[33]" 56.6372
cap "wbs_adr_i[5]" "wbs_dat_o[4]" 56.6372
cap "io_in[4]" "io_in_3v3[4]" 82.3652
cap "gpio_noesd[17]" "io_in_3v3[24]" 82.3652
cap "la_oenb[74]" "la_data_in[75]" 56.6372
cap "la_oenb[67]" "la_data_in[68]" 56.6372
cap "la_data_out[58]" "la_oenb[58]" 56.6372
cap "la_oenb[54]" "la_data_out[54]" 56.6372
cap "la_data_out[16]" "la_oenb[16]" 56.6372
cap "la_oenb[6]" "la_data_in[7]" 56.6372
cap "io_in[25]" "io_out[25]" 82.3652
cap "io_oeb[8]" "io_out[8]" 82.3652
cap "la_data_in[91]" "la_data_out[91]" 56.6372
cap "io_in[0]" "io_out[0]" 82.3652
cap "la_oenb[104]" "la_data_in[105]" 56.6372
cap "la_oenb[79]" "la_data_out[79]" 56.6372
cap "la_data_in[26]" "la_data_out[26]" 56.6372
cap "io_oeb[9]" "io_out[9]" 82.3652
cap "io_analog[5]" "io_clamp_high[1]" 493.833
cap "io_clamp_low[1]" "io_clamp_high[1]" 486.842
cap "la_oenb[64]" "la_data_in[65]" 56.6372
cap "io_in_3v3[17]" "CTRL3" 82.5992
cap "la_oenb[76]" "la_data_in[77]" 56.6372
cap "la_data_in[53]" "la_data_out[53]" 56.6372
cap "la_oenb[9]" "la_data_in[10]" 56.6372
cap "wbs_adr_i[25]" "wbs_dat_i[25]" 56.6372
cap "VCTRL" "vssa2" 4778.97
cap "io_out[2]" "io_oeb[2]" 82.3652
cap "la_data_out[121]" "la_oenb[121]" 56.6372
cap "wbs_dat_i[18]" "wbs_adr_i[18]" 56.6372
cap "wbs_dat_o[8]" "wbs_dat_i[8]" 56.6372
cap "io_in_3v3[12]" "gpio_noesd[5]" 82.3652
cap "la_data_in[100]" "la_data_out[100]" 56.6372
cap "la_data_in[59]" "la_data_out[59]" 56.6372
cap "la_data_in[25]" "la_data_out[25]" 56.6372
cap "wbs_dat_o[2]" "wbs_sel_i[2]" 56.6372
cap "vdda2" "io_in[19]" 7165.04
cap "la_data_in[72]" "la_data_out[72]" 56.6372
cap "wbs_adr_i[15]" "wbs_dat_o[14]" 56.6372
cap "m3_292774_580566#" "m3_290506_594136#" 1254.93
cap "la_data_in[52]" "la_data_out[52]" 56.6372
cap "la_oenb[19]" "la_data_in[20]" 56.6372
cap "la_oenb[14]" "la_data_in[15]" 56.6372
cap "la_data_in[9]" "la_data_out[9]" 56.6372
cap "wbs_adr_i[8]" "wbs_dat_o[7]" 56.6372
cap "io_out[19]" "io_in[19]" 82.5221
cap "gpio_noesd[3]" "gpio_analog[3]" 82.3652
cap "REF2" "gpio_analog[7]" 4259.99
cap "la_oenb[4]" "la_data_in[5]" 56.6372
cap "io_analog[5]" "io_clamp_low[1]" 735.436
cap "la_data_in[108]" "la_data_out[108]" 56.6372
cap "la_oenb[84]" "la_data_out[84]" 56.6372
cap "la_oenb[34]" "la_data_in[35]" 56.6372
cap "la_oenb[0]" "la_data_out[0]" 56.6372
cap "wbs_dat_o[14]" "wbs_dat_i[14]" 56.6372
cap "la_data_out[105]" "la_oenb[105]" 56.6372
cap "la_oenb[94]" "la_data_in[95]" 56.6372
cap "wbs_adr_i[8]" "wbs_dat_i[8]" 56.6372
cap "io_oeb[12]" "io_out[12]" 82.3652
cap "io_oeb[13]" "io_out[13]" 82.3652
cap "la_data_out[89]" "la_oenb[89]" 56.6372
cap "la_oenb[69]" "la_data_in[70]" 56.6372
cap "la_oenb[44]" "la_data_in[45]" 56.6372
cap "wbs_adr_i[16]" "wbs_dat_i[16]" 56.6372
cap "la_oenb[124]" "la_data_out[124]" 56.6372
cap "la_data_in[31]" "la_data_out[31]" 56.6372
cap "la_oenb[10]" "la_data_in[11]" 56.6372
cap "wbs_adr_i[10]" "wbs_dat_i[10]" 56.6372
cap "la_data_in[93]" "la_data_out[93]" 56.6372
cap "la_data_out[75]" "la_oenb[75]" 56.6372
cap "la_oenb[66]" "la_data_in[67]" 56.6372
cap "la_oenb[62]" "la_data_in[63]" 56.6372
cap "gpio_analog[7]" "CTRL5" 408.732
cap "CTRL5" "CTRL3" 297.982
cap "la_data_in[102]" "la_data_out[102]" 56.6372
cap "wbs_dat_i[17]" "wbs_dat_o[17]" 56.6372
cap "io_in_3v3[6]" "io_in[6]" 82.3652
cap "la_oenb[45]" "la_data_out[45]" 56.6372
cap "io_in[22]" "io_out[22]" 82.3652
cap "la_oenb[20]" "la_data_in[21]" 56.6372
cap "io_in_3v3[26]" "io_in[26]" 82.3652
cap "la_oenb[97]" "la_data_in[98]" 56.6372
cap "CTRL4" "vdda2" 7786.91
cap "CTRL4" "vccd2" 761.391
cap "gpio_analog[9]" "gpio_noesd[9]" 82.3652
cap "la_data_in[113]" "la_data_out[113]" 56.6372
cap "la_data_out[60]" "la_oenb[60]" 56.6372
cap "la_data_in[46]" "la_data_out[46]" 56.6372
cap "la_data_out[42]" "la_oenb[42]" 56.6372
cap "la_oenb[1]" "la_data_in[2]" 56.6372
cap "la_data_in[106]" "la_data_out[106]" 56.6372
cap "la_data_out[25]" "la_oenb[25]" 56.6372
cap "io_analog[5]" "io_clamp_low[1]" 486.842
cap "la_oenb[83]" "la_data_in[84]" 56.6372
cap "wbs_dat_o[16]" "wbs_adr_i[17]" 56.6372
cap "io_oeb[18]" "io_out[18]" 82.3652
cap "io_analog[5]" "io_clamp_low[1]" 493.833
cap "la_data_out[52]" "la_oenb[52]" 56.6372
cap "vccd2" "io_analog[6]" 542249
cap "gpio_analog[14]" "gpio_noesd[14]" 82.3652
cap "CTRL1" "gpio_noesd[8]" 82.8772
cap "la_oenb[43]" "la_data_in[44]" 56.6372
cap "wbs_adr_i[4]" "wbs_dat_i[4]" 56.6372
cap "REF" "REF2" 1567.06
cap "la_data_out[17]" "la_oenb[17]" 56.6372
cap "vdda2" "OUT180" 193.423
cap "la_data_in[123]" "la_data_out[123]" 56.6372
cap "la_oenb[39]" "la_data_in[40]" 56.6372
cap "la_oenb[21]" "la_data_in[22]" 56.6372
cap "vdda2" "vssa2" 304667
cap "vccd2" "vssa2" 171658
cap "gpio_noesd[13]" "io_in_3v3[20]" 82.3652
cap "la_data_out[62]" "la_oenb[62]" 56.6372
cap "wbs_dat_o[12]" "wbs_dat_i[12]" 56.6372
cap "gpio_noesd[4]" "gpio_analog[4]" 82.3652
cap "la_oenb[109]" "la_data_in[110]" 56.6372
cap "wbs_dat_o[26]" "wbs_adr_i[27]" 56.6372
cap "la_data_in[79]" "la_data_out[79]" 56.6372
cap "la_data_in[76]" "la_data_out[76]" 56.6372
cap "REF" "CTRL5" 1188.97
cap "io_in[1]" "io_in_3v3[1]" 82.3652
cap "io_out[9]" "io_in[9]" 82.3652
cap "la_oenb[15]" "la_data_out[15]" 56.6372
cap "la_oenb[84]" "la_data_in[85]" 56.6372
cap "la_oenb[32]" "la_data_in[33]" 56.6372
cap "CTRL2" "gpio_analog[7]" 291.111
cap "io_out[4]" "io_in[4]" 82.3652
cap "la_data_in[50]" "la_data_out[50]" 56.6372
cap "la_data_in[38]" "la_data_out[38]" 56.6372
cap "CTRL2" "CTRL3" 98582.2
cap "la_oenb[90]" "la_data_in[91]" 56.6372
cap "la_oenb[57]" "la_data_out[57]" 56.6372
cap "la_data_in[4]" "la_data_out[4]" 56.6372
cap "gpio_noesd[10]" "io_in_3v3[17]" 82.3652
cap "la_data_out[80]" "la_oenb[80]" 56.6372
cap "la_oenb[25]" "la_data_in[26]" 56.6372
cap "io_oeb[24]" "io_in_3v3[25]" 82.3652
cap "gpio_noesd[0]" "gpio_analog[0]" 82.3652
cap "la_oenb[52]" "la_data_in[53]" 56.6372
cap "io_in_3v3[21]" "io_in[21]" 82.3652
cap "io_out[16]" "io_oeb[16]" 82.3652
cap "la_oenb[43]" "la_data_out[43]" 56.6372
cap "wbs_dat_o[23]" "wbs_dat_i[23]" 56.6372
cap "wbs_dat_i[19]" "wbs_adr_i[19]" 56.6372
cap "wbs_dat_i[9]" "wbs_adr_i[9]" 56.6372
cap "la_oenb[58]" "la_data_in[59]" 56.6372
cap "io_clamp_high[2]" "io_analog[6]" 5610.15
cap "la_oenb[99]" "la_data_in[100]" 56.6372
cap "la_oenb[24]" "la_data_in[25]" 56.6372
cap "la_oenb[71]" "la_data_in[72]" 56.6372
cap "wbs_dat_o[27]" "wbs_dat_i[27]" 56.6372
cap "la_data_in[62]" "la_data_out[62]" 56.6372
cap "la_oenb[51]" "la_data_in[52]" 56.6372
cap "la_oenb[8]" "la_data_in[9]" 56.6372
cap "wbs_adr_i[14]" "wbs_dat_o[13]" 56.6372
cap "wbs_dat_o[1]" "wbs_sel_i[1]" 56.6372
cap "la_data_in[121]" "la_data_out[121]" 56.6372
cap "wbs_sel_i[3]" "wbs_dat_o[3]" 56.6372
cap "CTRL1" "gpio_analog[7]" 411.335
cap "gpio_noesd[11]" "io_in_3v3[18]" 82.3652
cap "user_irq[1]" "user_irq[2]" 56.6372
cap "la_oenb[107]" "la_data_in[108]" 56.6372
cap "wbs_dat_o[0]" "wbs_sel_i[0]" 56.6372
cap "io_in_3v3[4]" "io_oeb[3]" 82.3652
cap "wbs_dat_i[2]" "wbs_adr_i[2]" 56.6372
cap "CTRL1" "CTRL3" 286.887
cap "la_data_out[66]" "la_oenb[66]" 56.6372
cap "gpio_noesd[2]" "io_in_3v3[9]" 82.3652
cap "io_in_3v3[10]" "gpio_noesd[3]" 82.3652
cap "la_data_in[116]" "la_data_out[116]" 56.6372
cap "io_out[14]" "io_oeb[14]" 82.3652
cap "la_oenb[30]" "la_data_in[31]" 56.6372
cap "REF" "CTRL2" 796.903
cap "VCTRL" "CTRL5" 201.326
cap "la_oenb[92]" "la_data_in[93]" 56.6372
cap "la_oenb[77]" "la_data_out[77]" 56.6372
cap "io_analog[4]" "io_analog[4]" 26259.4
cap "la_oenb[101]" "la_data_in[102]" 56.6372
cap "io_oeb[1]" "io_out[1]" 82.3652
cap "la_data_in[28]" "la_data_out[28]" 56.6372
cap "la_data_in[0]" "la_data_out[0]" 56.6372
cap "io_in_3v3[22]" "io_in[22]" 82.3652
cap "la_data_in[97]" "la_data_out[97]" 56.6372
cap "la_oenb[90]" "la_data_out[90]" 56.6372
cap "la_oenb[8]" "la_data_out[8]" 56.6372
cap "io_out[21]" "io_oeb[21]" 82.3652
cap "gpio_analog[11]" "gpio_noesd[11]" 82.3652
cap "wbs_dat_o[6]" "wbs_adr_i[7]" 56.6372
cap "la_oenb[112]" "la_data_in[113]" 56.6372
cap "la_oenb[45]" "la_data_in[46]" 56.6372
cap "la_data_in[43]" "la_data_out[43]" 56.6372
cap "wbs_adr_i[28]" "wbs_dat_i[28]" 56.6372
cap "io_in[3]" "io_in_3v3[3]" 82.3652
cap "la_oenb[105]" "la_data_in[106]" 56.6372
cap "la_data_in[16]" "la_data_out[16]" 56.6372
cap "CTRL4" "vssa2" 1509.96
cap "la_data_in[61]" "la_data_out[61]" 56.6372
cap "la_data_out[72]" "la_oenb[72]" 56.6372
cap "wbs_dat_i[0]" "wbs_adr_i[0]" 56.6372
cap "io_out[15]" "io_oeb[15]" 82.3652
cap "la_data_out[53]" "la_oenb[53]" 56.6372
cap "REF" "CTRL1" 1197.65
cap "la_data_in[74]" "la_data_out[74]" 56.6372
cap "la_oenb[122]" "la_data_in[123]" 56.6372
cap "la_data_out[31]" "la_oenb[31]" 56.6372
cap "gpio_analog[13]" "gpio_noesd[13]" 82.3652
cap "la_data_in[127]" "la_data_out[127]" 56.6372
cap "wbs_adr_i[29]" "wbs_dat_i[29]" 56.6372
cap "la_oenb[75]" "la_data_in[76]" 56.6372
cap "la_data_in[8]" "la_data_out[8]" 56.6372
cap "la_data_in[3]" "la_data_out[3]" 56.6372
cap "la_data_out[94]" "la_oenb[94]" 56.6372
cap "la_oenb[78]" "la_data_in[79]" 56.6372
cap "wbs_adr_i[6]" "wbs_dat_o[5]" 56.6372
cap "io_out[2]" "io_in[2]" 82.3652
cap "CTRL2" "VCTRL" 153.991
cap "la_data_out[101]" "la_oenb[101]" 56.6372
cap "wbs_dat_i[5]" "wbs_dat_o[5]" 56.6372
cap "vccd2" "REF2" 47689.4
cap "la_data_in[48]" "la_data_out[48]" 56.6372
cap "la_oenb[37]" "la_data_in[38]" 56.6372
cap "la_data_out[33]" "la_oenb[33]" 56.6372
cap "la_oenb[49]" "la_data_in[50]" 56.6372
cap "io_analog[4]" "io_analog[4]" 21353.1
cap "wbs_stb_i" "wbs_we_i" 56.6372
cap "gpio_analog[10]" "gpio_noesd[10]" 82.3652
cap "la_oenb[3]" "la_data_in[4]" 56.6372
cap "wbs_dat_i[22]" "wbs_dat_o[22]" 56.6372
cap "la_data_in[90]" "la_data_out[90]" 56.6372
cap "la_oenb[68]" "la_data_out[68]" 56.6372
cap "wbs_dat_i[11]" "wbs_dat_o[11]" 56.6372
cap "wbs_dat_i[3]" "wbs_adr_i[3]" 56.6372
cap "io_in_3v3[7]" "gpio_noesd[0]" 82.3652
cap "io_in_3v3[13]" "gpio_noesd[6]" 82.3652
cap "vdda2" "CTRL5" 1271.8
cap "la_data_in[120]" "la_data_out[120]" 56.6372
cap "la_oenb[26]" "la_data_out[26]" 56.6372
cap "la_data_out[23]" "la_oenb[23]" 56.6372
cap "vccd2" "CTRL5" 1573.79
cap "la_data_in[73]" "la_data_out[73]" 56.6372
cap "la_data_in[32]" "la_data_out[32]" 56.6372
cap "io_analog[6]" "io_analog[6]" 27450.9
cap "la_oenb[120]" "la_data_out[120]" 56.6372
cap "wbs_adr_i[31]" "wbs_dat_i[31]" 56.6372
cap "wbs_dat_i[28]" "wbs_dat_o[28]" 56.6372
cap "la_oenb[61]" "la_data_in[62]" 56.6372
cap "io_in[0]" "io_in_3v3[0]" 82.3652
cap "gpio_noesd[7]" "gpio_analog[7]" 84.4369
cap "REF" "io_analog[7]" 2220
cap "la_data_in[13]" "la_data_out[13]" 56.6372
cap "CTRL1" "VCTRL" 561.222
cap "la_oenb[120]" "la_data_in[121]" 56.6372
cap "la_oenb[69]" "la_data_out[69]" 56.6372
cap "la_data_in[66]" "la_data_out[66]" 56.6372
cap "la_data_in[57]" "la_data_out[57]" 56.6372
cap "io_analog[6]" "io_analog[6]" 23873.1
cap "user_irq[0]" "user_irq[1]" 56.6372
cap "la_data_out[78]" "la_oenb[78]" 56.6372
cap "wbs_adr_i[30]" "wbs_dat_i[30]" 56.6372
cap "gpio_analog[15]" "gpio_noesd[15]" 82.3652
cap "la_data_in[126]" "la_data_out[126]" 56.6372
cap "la_data_in[86]" "la_data_out[86]" 56.6372
cap "wbs_dat_i[9]" "wbs_dat_o[9]" 56.6372
cap "la_data_in[54]" "la_data_out[54]" 56.6372
cap "wbs_dat_i[31]" "wbs_dat_o[31]" 56.6372
cap "wbs_adr_i[12]" "wbs_dat_i[12]" 56.6372
cap "gpio_analog[16]" "gpio_noesd[16]" 82.3652
cap "io_in[14]" "io_out[14]" 82.3652
cap "la_oenb[115]" "la_data_in[116]" 56.6372
cap "la_oenb[98]" "la_data_out[98]" 56.6372
cap "wbs_adr_i[15]" "wbs_dat_i[15]" 56.6372
cap "la_data_in[104]" "la_data_out[104]" 56.6372
cap "la_data_out[64]" "la_oenb[64]" 56.6372
cap "wbs_dat_i[18]" "wbs_dat_o[18]" 56.6372
cap "io_analog[5]" "io_analog[5]" 26259.4
cap "la_data_in[101]" "la_data_out[101]" 56.6372
cap "la_data_out[73]" "la_oenb[73]" 56.6372
cap "la_data_out[70]" "la_oenb[70]" 56.6372
cap "la_data_out[49]" "la_oenb[49]" 56.6372
cap "wbs_dat_i[25]" "wbs_dat_o[25]" 56.6372
cap "wbs_dat_o[12]" "wbs_adr_i[13]" 56.6372
cap "io_out[5]" "io_in[5]" 82.3652
cap "io_in[10]" "io_in_3v3[10]" 82.3652
cap "la_data_out[107]" "la_oenb[107]" 56.6372
cap "la_oenb[27]" "la_data_in[28]" 56.6372
cap "la_data_out[6]" "la_oenb[6]" 56.6372
cap "la_oenb[96]" "la_data_in[97]" 56.6372
cap "la_data_out[1]" "la_oenb[1]" 56.6372
cap "wbs_dat_o[31]" "la_data_in[0]" 56.6372
cap "io_oeb[4]" "io_out[4]" 82.3652
cap "la_data_out[126]" "la_oenb[126]" 56.6372
cap "la_data_out[123]" "la_oenb[123]" 56.6372
cap "la_data_in[83]" "la_data_out[83]" 56.6372
cap "io_in[19]" "CTRL5" 62.2374
cap "io_in[21]" "io_out[21]" 82.3652
cap "la_data_out[96]" "la_oenb[96]" 56.6372
cap "wbs_dat_o[2]" "wbs_dat_i[2]" 56.6372
cap "io_out[19]" "io_oeb[19]" 82.3652
cap "txinb" "txina" 1775.07
cap "la_oenb[42]" "la_data_in[43]" 56.6372
cap "wbs_dat_o[27]" "wbs_adr_i[28]" 56.6372
cap "wbs_adr_i[21]" "wbs_dat_i[21]" 56.6372
cap "la_data_in[96]" "la_data_out[96]" 56.6372
cap "la_oenb[15]" "la_data_in[16]" 56.6372
cap "vdda2" "CTRL2" 7772.19
cap "gpio_analog[8]" "gpio_noesd[8]" 82.3652
cap "la_oenb[60]" "la_data_in[61]" 56.6372
cap "vccd2" "CTRL2" 743.055
cap "io_oeb[3]" "io_out[3]" 82.3652
cap "CTRL4" "io_in_3v3[18]" 82.7704
cap "la_data_out[99]" "la_oenb[99]" 56.6372
cap "wbs_adr_i[14]" "wbs_dat_i[14]" 56.6372
cap "io_in[15]" "io_out[15]" 82.3652
cap "la_oenb[102]" "la_data_out[102]" 56.6372
cap "wbs_dat_i[24]" "wbs_dat_o[24]" 56.6372
cap "la_data_in[118]" "la_data_out[118]" 56.6372
cap "la_data_in[78]" "la_data_out[78]" 56.6372
cap "la_oenb[73]" "la_data_in[74]" 56.6372
cap "wbs_dat_i[30]" "wbs_dat_o[30]" 56.6372
cap "io_analog[4]" "io_clamp_high[0]" 735.436
cap "wbs_dat_o[28]" "wbs_adr_i[29]" 56.6372
cap "wbs_stb_i" "wbs_cyc_i" 56.6372
cap "io_out[20]" "io_oeb[20]" 82.3652
cap "la_oenb[126]" "la_data_in[127]" 56.6372
cap "la_oenb[39]" "la_data_out[39]" 56.6372
cap "la_data_in[30]" "la_data_out[30]" 56.6372
cap "wbs_adr_i[18]" "wbs_dat_o[17]" 56.6372
cap "gpio_noesd[2]" "gpio_analog[2]" 82.3652
cap "la_oenb[24]" "la_data_out[24]" 56.6372
cap "io_analog[6]" "REF2" 80084.7
cap "io_analog[4]" "io_clamp_high[0]" 493.833
cap "la_data_in[12]" "la_data_out[12]" 56.6372
cap "la_oenb[7]" "la_data_in[8]" 56.6372
cap "la_oenb[2]" "la_data_in[3]" 56.6372
cap "gpio_analog[7]" "CTRL3" 293.707
cap "la_oenb[71]" "la_data_out[71]" 56.6372
cap "la_data_in[125]" "la_data_out[125]" 56.6372
cap "la_data_in[81]" "la_data_out[81]" 56.6372
cap "wbs_dat_o[10]" "wbs_adr_i[11]" 56.6372
cap "CTRL4" "CTRL5" 82115.4
cap "la_oenb[67]" "la_data_out[67]" 56.6372
cap "wbs_dat_o[7]" "wbs_dat_i[7]" 56.6372
cap "io_in[11]" "io_in_3v3[11]" 82.3652
cap "vdda2" "CTRL1" 8451.37
cap "la_data_in[49]" "la_data_out[49]" 56.6372
cap "la_oenb[48]" "la_data_out[48]" 56.6372
cap "la_oenb[47]" "la_data_in[48]" 56.6372
cap "vccd2" "CTRL1" 1592.17
cap "io_analog[5]" "io_analog[5]" 21353.1
cap "REF2" "vssa2" 31320.9
cap "gpio_analog[17]" "gpio_noesd[17]" 82.3652
cap "la_data_in[34]" "la_data_out[34]" 56.6372
cap "la_oenb[37]" "la_data_out[37]" 56.6372
cap "la_oenb[127]" "la_data_out[127]" 56.6372
cap "la_oenb[112]" "la_data_out[112]" 56.6372
cap "la_oenb[89]" "la_data_in[90]" 56.6372
cap "la_data_in[55]" "la_data_out[55]" 56.6372
cap "la_data_in[18]" "la_data_out[18]" 56.6372
cap "la_data_out[12]" "la_oenb[12]" 56.6372
cap "io_out[17]" "io_oeb[17]" 82.3652
cap "io_in[15]" "CTRL1" 82.6395
cap "io_in[13]" "io_in_3v3[13]" 83.2612
cap "io_analog[6]" "io_clamp_high[2]" 489.029
cap "la_oenb[50]" "la_data_out[50]" 56.6372
cap "la_oenb[125]" "la_data_out[125]" 56.6372
cap "la_data_in[115]" "la_data_out[115]" 56.6372
cap "wbs_dat_o[19]" "wbs_adr_i[20]" 56.6372
cap "la_oenb[119]" "la_data_in[120]" 56.6372
cap "la_oenb[116]" "la_data_out[116]" 56.6372
cap "la_oenb[31]" "la_data_in[32]" 56.6372
cap "wbs_dat_i[20]" "wbs_dat_o[20]" 56.6372
cap "wbs_ack_o" "wb_rst_i" 56.6372
cap "la_oenb[72]" "la_data_in[73]" 56.6372
cap "wbs_dat_o[15]" "wbs_dat_i[15]" 56.6372
cap "wbs_dat_i[5]" "wbs_adr_i[5]" 56.6372
cap "vssa2" "CTRL5" 2888.32
cap "la_data_out[28]" "la_oenb[28]" 56.6372
cap "wbs_dat_o[30]" "wbs_adr_i[31]" 56.6372
cap "wbs_adr_i[22]" "wbs_dat_i[22]" 56.6372
cap "wbs_adr_i[3]" "wbs_sel_i[2]" 56.6372
cap "la_data_in[47]" "la_data_out[47]" 56.6372
cap "la_data_in[27]" "la_data_out[27]" 56.6372
cap "io_in_3v3[1]" "io_oeb[0]" 82.3652
cap "la_oenb[65]" "la_data_in[66]" 56.6372
cap "la_oenb[56]" "la_data_in[57]" 56.6372
cap "la_data_out[44]" "la_oenb[44]" 56.6372
cap "la_oenb[12]" "la_data_in[13]" 56.6372
cap "io_in[26]" "io_out[26]" 82.3652
cap "wbs_dat_o[29]" "wbs_adr_i[30]" 56.6372
cap "REF" "CTRL3" 805.557
cap "user_clock2" "user_irq[0]" 56.6372
cap "la_oenb[125]" "la_data_in[126]" 56.6372
cap "la_data_in[124]" "la_data_out[124]" 56.6372
cap "la_oenb[85]" "la_data_in[86]" 56.6372
cap "wbs_dat_i[24]" "wbs_adr_i[24]" 56.6372
cap "la_oenb[53]" "la_data_in[54]" 56.6372
cap "wbs_dat_o[13]" "wbs_dat_i[13]" 56.6372
cap "wbs_we_i" "wbs_adr_i[0]" 56.6372
cap "io_oeb[22]" "io_out[22]" 82.3652
cap "la_data_out[21]" "la_oenb[21]" 56.6372
cap "la_data_out[9]" "la_oenb[9]" 56.6372
cap "io_in_3v3[14]" "io_in[14]" 82.3652
cap "la_oenb[103]" "la_data_in[104]" 56.6372
cap "la_data_in[94]" "la_data_out[94]" 56.6372
cap "la_data_out[38]" "la_oenb[38]" 56.6372
cap "wb_clk_i" "wb_rst_i" 56.6372
cap "la_oenb[113]" "la_data_out[113]" 56.6372
cap "la_oenb[100]" "la_data_in[101]" 56.6372
cap "CTRL4" "CTRL2" 232.119
cap "io_analog[6]" "io_analog[6]" 27499.9
cap "io_out[10]" "io_in[10]" 82.3652
cap "io_analog[7]" "vccd2" 89613.2
cap "io_in_3v3[7]" "io_in[7]" 82.3652
cap "la_oenb[82]" "la_data_in[83]" 56.6372
cap "la_data_out[86]" "la_oenb[86]" 56.6372
cap "wbs_adr_i[1]" "wbs_sel_i[0]" 56.6372
cap "la_oenb[95]" "la_data_in[96]" 56.6372
cap "la_oenb[82]" "la_data_out[82]" 56.6372
cap "wbs_dat_o[25]" "wbs_adr_i[26]" 56.6372
cap "la_data_out[103]" "la_oenb[103]" 56.6372
cap "CTRL2" "vssa2" 1571.15
cap "la_data_in[82]" "la_data_out[82]" 56.6372
cap "la_oenb[76]" "la_data_out[76]" 56.6372
cap "la_data_in[107]" "la_data_out[107]" 56.6372
cap "la_oenb[117]" "la_data_in[118]" 56.6372
cap "la_oenb[77]" "la_data_in[78]" 56.6372
cap "wbs_sel_i[1]" "wbs_adr_i[2]" 56.6372
cap "CTRL4" "CTRL1" 255.895
cap "io_in[20]" "io_out[20]" 82.3652
cap "la_oenb[29]" "la_data_in[30]" 56.6372
cap "io_in_3v3[24]" "io_in[24]" 82.3652
cap "la_data_out[81]" "la_oenb[81]" 56.6372
cap "la_data_in[17]" "la_data_out[17]" 56.6372
cap "VCTRL" "gpio_analog[7]" 647.184
cap "gpio_analog[6]" "gpio_noesd[6]" 82.3652
cap "la_data_out[117]" "la_oenb[117]" 56.6372
cap "la_oenb[29]" "la_data_out[29]" 56.6372
cap "VCTRL" "CTRL3" 155.036
cap "la_data_in[87]" "la_data_out[87]" 56.6372
cap "la_data_in[29]" "la_data_out[29]" 56.6372
cap "la_oenb[11]" "la_data_in[12]" 56.6372
cap "la_data_out[4]" "la_oenb[4]" 56.6372
cap "la_oenb[124]" "la_data_in[125]" 56.6372
cap "la_data_in[117]" "la_data_out[117]" 56.6372
cap "la_oenb[80]" "la_data_in[81]" 56.6372
cap "io_in_3v3[16]" "CTRL2" 82.5579
cap "la_data_out[13]" "la_oenb[13]" 56.6372
cap "io_out[11]" "io_in[11]" 82.3652
cap "wbs_dat_o[8]" "wbs_adr_i[9]" 56.6372
cap "io_analog[5]" "io_analog[5]" 26259.4
cap "io_in_3v3[19]" "io_in[19]" 82.5221
cap "la_data_in[103]" "la_data_out[103]" 56.6372
cap "la_oenb[56]" "la_data_out[56]" 56.6372
cap "la_oenb[48]" "la_data_in[49]" 56.6372
cap "io_analog[5]" "io_analog[5]" 21353.1
cap "io_out[25]" "io_oeb[25]" 82.3652
cap "io_out[3]" "io_in[3]" 82.3652
cap "la_oenb[33]" "la_data_in[34]" 56.6372
cap "CTRL1" "vssa2" 3487.55
cap "io_in[25]" "io_in_3v3[25]" 82.3652
cap "la_oenb[17]" "la_data_in[18]" 56.6372
cap "wbs_dat_o[0]" "wbs_dat_i[0]" 56.6372
cap "la_oenb[54]" "la_data_in[55]" 56.6372
cap "io_analog[4]" "io_analog[4]" 21353.1
cap "la_data_in[88]" "la_data_out[88]" 56.6372
cap "la_oenb[74]" "la_data_out[74]" 56.6372
cap "la_data_in[37]" "la_data_out[37]" 56.6372
cap "io_out[6]" "io_in[6]" 82.3652
cap "la_oenb[114]" "la_data_in[115]" 56.6372
cap "la_data_in[89]" "la_data_out[89]" 56.6372
cap "la_data_in[51]" "la_data_out[51]" 56.6372
cap "la_data_out[7]" "la_oenb[7]" 56.6372
cap "wbs_dat_o[21]" "wbs_dat_i[21]" 56.6372
cap "la_data_in[69]" "la_data_out[69]" 56.6372
cap "la_oenb[46]" "la_data_in[47]" 56.6372
cap "la_oenb[119]" "la_data_out[119]" 56.6372
cap "la_data_in[99]" "la_data_out[99]" 56.6372
cap "la_oenb[26]" "la_data_in[27]" 56.6372
cap "io_in_3v3[2]" "io_in[2]" 82.3652
cap "gpio_noesd[12]" "io_in_3v3[19]" 82.9809
cap "wbs_dat_o[10]" "wbs_dat_i[10]" 56.6372
cap "wbs_adr_i[10]" "wbs_dat_o[9]" 56.6372
cap "REF" "VCTRL" 126.11
cap "io_clamp_high[0]" "io_analog[4]" 486.842
cap "la_data_out[97]" "la_oenb[97]" 56.6372
cap "la_data_in[41]" "la_data_out[41]" 56.6372
cap "wbs_adr_i[19]" "wbs_dat_o[18]" 56.6372
cap "la_oenb[127]" "user_clock2" 56.6372
cap "la_oenb[123]" "la_data_in[124]" 56.6372
cap "io_analog[7]" "io_analog[6]" 80084.7
cap "la_data_in[92]" "la_data_out[92]" 56.6372
cap "la_oenb[65]" "la_data_out[65]" 56.6372
cap "la_data_out[55]" "la_oenb[55]" 56.6372
cap "gpio_noesd[7]" "io_in_3v3[14]" 82.3652
cap "la_oenb[93]" "la_data_in[94]" 56.6372
cap "wbs_ack_o" "wbs_cyc_i" 56.6372
cap "la_data_in[122]" "la_data_out[122]" 56.6372
cap "la_oenb[2]" "la_data_out[2]" 56.6372
cap "la_oenb[104]" "la_data_out[104]" 56.6372
cap "la_oenb[87]" "la_data_out[87]" 56.6372
cap "la_data_in[24]" "la_data_out[24]" 56.6372
cap "la_data_in[1]" "la_data_out[1]" 56.6372
cap "wbs_adr_i[12]" "wbs_dat_o[11]" 56.6372
cap "wbs_adr_i[6]" "wbs_dat_i[6]" 56.6372
cap "la_data_in[112]" "la_data_out[112]" 56.6372
cap "vdda2" "gpio_analog[7]" 15768.3
cap "io_analog[7]" "m3_290506_594136#" 1343.53
cap "vccd2" "gpio_analog[7]" 24962.3
cap "io_clamp_low[2]" "io_clamp_high[2]" 486.842
cap "la_oenb[118]" "la_data_out[118]" 56.6372
cap "vdda2" "CTRL3" 7786.49
cap "la_data_in[71]" "la_data_out[71]" 56.6372
cap "la_data_in[14]" "la_data_out[14]" 56.6372
cap "vccd2" "CTRL3" 761.391
cap "io_in_3v3[8]" "gpio_noesd[1]" 82.3652
cap "la_data_out[88]" "la_oenb[88]" 56.6372
cap "wbs_adr_i[1]" "wbs_dat_i[1]" 56.6372
cap "io_analog[6]" "io_clamp_high[2]" 384.118
cap "la_oenb[18]" "la_data_out[18]" 56.6372
cap "la_data_out[114]" "la_oenb[114]" 56.6372
cap "la_oenb[95]" "la_data_out[95]" 56.6372
cap "la_data_in[80]" "la_data_out[80]" 56.6372
cap "la_data_in[64]" "la_data_out[64]" 56.6372
cap "la_oenb[106]" "la_data_in[107]" 56.6372
cap "la_oenb[81]" "la_data_in[82]" 56.6372
cap "la_data_in[56]" "la_data_out[56]" 56.6372
cap "la_oenb[32]" "la_data_out[32]" 56.6372
cap "la_data_out[83]" "la_oenb[83]" 56.6372
cap "la_data_in[36]" "la_data_out[36]" 56.6372
cap "la_oenb[16]" "la_data_in[17]" 56.6372
cap "io_out[17]" "CTRL3" 82.4471
cap "la_oenb[86]" "la_data_in[87]" 56.6372
cap "la_data_in[39]" "la_data_out[39]" 56.6372
cap "la_oenb[28]" "la_data_in[29]" 56.6372
cap "la_data_out[11]" "la_oenb[11]" 56.6372
cap "wbs_adr_i[26]" "wbs_dat_i[26]" 56.6372
cap "gpio_analog[12]" "gpio_noesd[12]" 105.459
cap "la_oenb[85]" "la_data_out[85]" 56.6372
cap "la_oenb[34]" "la_data_out[34]" 56.6372
cap "wbs_adr_i[25]" "wbs_dat_o[24]" 56.6372
cap "la_oenb[116]" "la_data_in[117]" 56.6372
cap "la_data_in[109]" "la_data_out[109]" 56.6372
cap "io_in_3v3[23]" "io_in[23]" 82.3652
cap "io_clamp_low[2]" "io_analog[6]" 5096.08
cap "io_out[13]" "io_in[13]" 92.2247
cap "vdda2" "REF" 45375.4
cap "la_data_out[36]" "la_oenb[36]" 56.6372
cap "io_out[7]" "io_in[7]" 82.3652
cap "REF" "vccd2" 57592.4
cap "la_oenb[102]" "la_data_in[103]" 56.6372
cap "wbs_dat_i[16]" "wbs_dat_o[16]" 56.6372
cap "CTRL2" "CTRL5" 294.76
cap "la_data_in[60]" "la_data_out[60]" 56.6372
cap "io_analog[6]" "io_analog[6]" 23969.9
cap "io_oeb[1]" "io_in_3v3[2]" 82.3652
cap "la_data_in[6]" "la_data_out[6]" 56.6372
cap "wbs_dat_i[11]" "wbs_adr_i[11]" 56.6372
cap "io_out[23]" "io_in[23]" 82.3652
cap "la_oenb[100]" "la_data_out[100]" 56.6372
cap "la_data_in[42]" "la_data_out[42]" 56.6372
cap "la_oenb[87]" "la_data_in[88]" 56.6372
cap "la_oenb[36]" "la_data_in[37]" 56.6372
cap "io_oeb[6]" "io_out[6]" 82.3652
cap "io_in_3v3[11]" "gpio_noesd[4]" 82.3652
cap "io_clamp_low[0]" "io_analog[4]" 486.842
cap "la_oenb[88]" "la_data_in[89]" 56.6372
cap "io_out[23]" "io_oeb[23]" 82.3652
cap "io_in_3v3[22]" "gpio_noesd[15]" 82.3652
cap "la_oenb[50]" "la_data_in[51]" 56.6372
cap "la_oenb[41]" "la_data_out[41]" 56.6372
cap "wbs_sel_i[3]" "wbs_adr_i[4]" 56.6372
cap "io_out[16]" "CTRL2" 82.6435
cap "la_oenb[68]" "la_data_in[69]" 56.6372
cap "la_oenb[61]" "la_data_out[61]" 56.6372
cap "la_oenb[3]" "la_data_out[3]" 56.6372
cap "io_oeb[5]" "io_out[5]" 82.3652
cap "io_oeb[24]" "io_out[24]" 82.3652
cap "gpio_analog[1]" "gpio_noesd[1]" 82.3652
cap "la_oenb[98]" "la_data_in[99]" 56.6372
cap "wbs_adr_i[7]" "wbs_dat_i[7]" 56.6372
cap "io_out[11]" "io_oeb[11]" 82.3652
cap "la_data_in[114]" "la_data_out[114]" 56.6372
cap "la_data_in[58]" "la_data_out[58]" 56.6372
cap "la_oenb[40]" "la_data_in[41]" 56.6372
cap "la_data_in[23]" "la_data_out[23]" 56.6372
cap "io_clamp_low[0]" "io_clamp_high[0]" 486.842
cap "la_data_in[111]" "la_data_out[111]" 56.6372
cap "la_data_in[19]" "la_data_out[19]" 56.6372
cap "wbs_dat_o[21]" "wbs_adr_i[22]" 56.6372
cap "wbs_adr_i[21]" "wbs_dat_o[20]" 56.6372
cap "wbs_dat_o[3]" "wbs_dat_i[3]" 56.6372
cap "wbs_dat_o[1]" "wbs_dat_i[1]" 56.6372
cap "io_analog[4]" "io_clamp_low[0]" 735.436
cap "la_data_in[119]" "la_data_out[119]" 56.6372
cap "CTRL1" "CTRL5" 318.42
cap "la_oenb[30]" "la_data_out[30]" 56.6372
cap "CTRL4" "gpio_analog[7]" 293.707
cap "wbs_dat_o[23]" "wbs_adr_i[24]" 56.6372
cap "CTRL4" "CTRL3" 58668.7
cap "la_oenb[111]" "la_data_out[111]" 56.6372
cap "la_oenb[91]" "la_data_in[92]" 56.6372
cap "CTRL4" "io_out[18]" 82.8227
cap "la_data_in[75]" "la_data_out[75]" 56.6372
cap "la_data_in[68]" "la_data_out[68]" 56.6372
cap "la_data_in[7]" "la_data_out[7]" 56.6372
cap "io_analog[6]" "gpio_analog[7]" 31861.3
cap "io_in_3v3[3]" "io_oeb[2]" 82.3652
cap "la_oenb[121]" "la_data_in[122]" 56.6372
cap "wbs_dat_i[13]" "wbs_adr_i[13]" 56.6372
cap "la_oenb[23]" "la_data_in[24]" 56.6372
cap "la_oenb[0]" "la_data_in[1]" 56.6372
cap "vdda2" "VCTRL" 2199.14
cap "io_analog[4]" "io_analog[4]" 26259.4
cap "io_oeb[26]" "io_out[26]" 82.3652
cap "io_out[1]" "io_in[1]" 82.3652
cap "la_oenb[111]" "la_data_in[112]" 56.6372
cap "la_data_in[105]" "la_data_out[105]" 56.6372
cap "vccd2" "VCTRL" 3080.35
cap "io_in_3v3[20]" "io_in[20]" 82.3652
cap "la_data_in[65]" "la_data_out[65]" 56.6372
cap "io_analog[6]" "io_clamp_low[2]" 486.842
cap "la_data_in[77]" "la_data_out[77]" 56.6372
cap "la_oenb[13]" "la_data_in[14]" 56.6372
cap "la_data_in[10]" "la_data_out[10]" 56.6372
cap "io_out[24]" "io_in[24]" 82.3652
cap "io_in[8]" "io_in_3v3[8]" 82.3652
cap "vssa2" "gpio_analog[7]" 14274.4
cap "la_oenb[70]" "la_data_in[71]" 56.6372
cap "vssa2" "CTRL3" 1556.91
cap "gpio_noesd[5]" "gpio_analog[5]" 82.3652
cap "io_analog[6]" "io_clamp_low[2]" 384.544
cap "OUT180" "OUT0" 2493.89
cap "la_data_out[46]" "la_oenb[46]" 56.6372
cap "la_oenb[14]" "la_data_out[14]" 56.6372
cap "wbs_dat_i[17]" "wbs_adr_i[17]" 56.6372
cap "la_oenb[93]" "la_data_out[93]" 56.6372
cap "la_data_in[20]" "la_data_out[20]" 56.6372
cap "la_data_in[15]" "la_data_out[15]" 56.6372
cap "io_analog[4]" "io_clamp_low[0]" 493.833
cap "la_oenb[79]" "la_data_in[80]" 56.6372
cap "la_oenb[63]" "la_data_in[64]" 56.6372
cap "la_data_in[5]" "la_data_out[5]" 56.6372
cap "wbs_dat_i[19]" "wbs_dat_o[19]" 56.6372
cap "la_oenb[55]" "la_data_in[56]" 56.6372
cap "la_data_in[35]" "la_data_out[35]" 56.6372
cap "wbs_adr_i[23]" "wbs_dat_o[22]" 56.6372
cap "wbs_dat_o[6]" "wbs_dat_i[6]" 56.6372
cap "la_data_out[40]" "la_oenb[40]" 56.6372
cap "CTRL4" "REF" 805.557
cap "la_data_in[95]" "la_data_out[95]" 56.6372
cap "la_oenb[63]" "la_data_out[63]" 56.6372
cap "la_oenb[35]" "la_data_out[35]" 56.6372
cap "wbs_dat_o[29]" "wbs_dat_i[29]" 56.6372
cap "io_out[12]" "io_in[12]" 82.3652
cap "la_data_in[70]" "la_data_out[70]" 56.6372
cap "la_oenb[35]" "la_data_in[36]" 56.6372
cap "la_data_in[45]" "la_data_out[45]" 56.6372
cap "la_oenb[38]" "la_data_in[39]" 56.6372
cap "la_data_in[11]" "la_data_out[11]" 56.6372
cap "wbs_dat_i[4]" "wbs_dat_o[4]" 56.6372
cap "CTRL2" "CTRL1" 83257.5
cap "REF" "io_analog[6]" 80084.7
cap "la_data_in[63]" "la_data_out[63]" 56.6372
cap "la_oenb[5]" "la_data_out[5]" 56.6372
cap "la_data_in[67]" "la_data_out[67]" 56.6372
cap "wbs_dat_i[20]" "wbs_adr_i[20]" 56.6372
cap "la_oenb[108]" "la_data_in[109]" 56.6372
cap "la_oenb[106]" "la_data_out[106]" 56.6372
cap "gpio_noesd[16]" "io_in_3v3[23]" 82.3652
cap "la_oenb[91]" "la_data_out[91]" 56.6372
cap "la_oenb[51]" "la_data_out[51]" 56.6372
cap "io_oeb[7]" "io_out[7]" 82.3652
cap "io_clamp_high[1]" "io_analog[5]" 486.842
cap "la_oenb[115]" "la_data_out[115]" 56.6372
cap "la_oenb[59]" "la_data_in[60]" 56.6372
cap "la_data_out[19]" "la_oenb[19]" 56.6372
cap "io_oeb[0]" "io_out[0]" 82.3652
cap "io_out[10]" "io_oeb[10]" 82.3652
cap "la_data_in[98]" "la_data_out[98]" 56.6372
cap "la_data_in[21]" "la_data_out[21]" 56.6372
cap "io_out[8]" "io_in[8]" 82.3652
cap "REF" "vssa2" 37113
cap "la_oenb[41]" "la_data_in[42]" 56.6372
cap "la_oenb[5]" "la_data_in[6]" 56.6372
cap "la_data_in[2]" "la_data_out[2]" 56.6372
cap "gpio_noesd[9]" "io_in_3v3[16]" 82.3652
cap "wbs_dat_o[26]" "wbs_dat_i[26]" 56.6372
cap "la_oenb[109]" "la_data_out[109]" 56.6372
cap "la_data_out[27]" "la_oenb[27]" 56.6372
cap "la_data_in[84]" "la_data_out[84]" 56.6372
cap "wbs_adr_i[23]" "wbs_dat_i[23]" 56.6372
cap "gpio_noesd[14]" "io_in_3v3[21]" 82.3652
cap "la_data_out[92]" "la_oenb[92]" 56.6372
cap "la_data_in[44]" "la_data_out[44]" 56.6372
cap "wbs_adr_i[16]" "wbs_dat_o[15]" 56.6372
cap "io_analog[5]" "io_clamp_high[1]" 735.436
cap "la_oenb[10]" "la_data_out[10]" 56.6372
cap "vdda2" "vccd2" 167724
cap "io_in_3v3[12]" "io_in[12]" 82.3652
cap "la_data_in[40]" "la_data_out[40]" 56.6372
cap "la_oenb[22]" "la_data_out[22]" 56.6372
cap "la_data_in[22]" "la_data_out[22]" 56.6372
cap "io_in[5]" "io_in_3v3[5]" 82.3652
cap "la_oenb[113]" "la_data_in[114]" 56.6372
cap "la_oenb[57]" "la_data_in[58]" 56.6372
cap "la_oenb[22]" "la_data_in[23]" 56.6372
cap "la_oenb[110]" "la_data_in[111]" 56.6372
cap "la_data_out[110]" "la_oenb[110]" 56.6372
cap "la_data_in[110]" "la_data_out[110]" 56.6372
cap "la_oenb[18]" "la_data_in[19]" 56.6372
cap "wbs_adr_i[27]" "wbs_dat_i[27]" 56.6372
cap "CTRL4" "VCTRL" 155.036
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 355.324
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 1115.78
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 1115.78
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 1115.78
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 708.852
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 709.599
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 1560.58
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 1560.58
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 1560.58
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 1766.14
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 813.491
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 490.454
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 713.036
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 490.454
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 713.036
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 490.454
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 713.036
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 497.039
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 724.942
cap "TX_line_0/OUTB" "txinb" 672.81
cap "TX_line_0/OUTB" "txinb" 867.23
cap "TX_line_0/OUTB" "txinb" 867.23
cap "TX_line_0/OUTB" "txinb" 867.23
cap "TX_line_0/OUTB" "txinb" 867.23
cap "TX_line_0/OUTB" "txinb" 867.23
cap "TX_line_0/OUTB" "txinb" 867.23
cap "TX_line_0/OUTB" "txinb" 867.23
cap "TX_line_0/OUTB" "txinb" 867.23
cap "TX_line_0/OUTB" "txinb" 867.23
cap "TX_line_0/OUTB" "txinb" 867.23
cap "txinb" "TX_line_0/OUTB" 867.23
cap "TX_line_0/OUTB" "txinb" 867.23
cap "TX_line_0/OUTB" "txinb" 867.23
cap "TX_line_0/OUTB" "TX_line_0/INB" 867.23
cap "TX_line_0/OUTB" "TX_line_0/INB" 867.23
cap "TX_line_0/OUTB" "TX_line_0/INB" 1032.43
cap "TX_line_0/OUTB" "TX_line_0/INB" 637.21
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 748.764
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1353.18
cap "VGA_routing_0/m1_443471_411908#" "TX_line_0/OUTB" 861.185
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 305.707
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 722.822
cap "TX_line_0/OUTB" "txinb" 1395.66
cap "TX_line_0/OUTB" "txinb" 1692.46
cap "TX_line_0/OUTB" "txinb" 1692.46
cap "TX_line_0/OUTB" "txinb" 1692.46
cap "txinb" "TX_line_0/OUTB" 1692.46
cap "TX_line_0/OUTB" "txinb" 1692.46
cap "TX_line_0/OUTB" "txinb" 1692.46
cap "TX_line_0/OUTB" "txinb" 1692.46
cap "TX_line_0/OUTB" "txinb" 1692.46
cap "txinb" "TX_line_0/OUTB" 1692.46
cap "TX_line_0/OUTB" "txinb" 1692.46
cap "TX_line_0/OUTB" "txinb" 1692.46
cap "TX_line_0/OUTB" "txinb" 1692.46
cap "TX_line_0/OUTB" "txinb" 1692.46
cap "TX_line_0/OUTB" "TX_line_0/INB" 1692.46
cap "TX_line_0/OUTB" "TX_line_0/INB" 1692.46
cap "TX_line_0/INB" "TX_line_0/OUTB" 1227.94
cap "TX_line_0/OUTB" "TX_line_0/INB" 1207.85
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1221.61
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 771.727
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "TX_line_0/OUTB" "txinb" 473.43
cap "TX_line_0/OUTB" "txinb" 625.45
cap "TX_line_0/OUTB" "txinb" 625.45
cap "TX_line_0/OUTB" "txinb" 625.45
cap "TX_line_0/OUTB" "txinb" 625.45
cap "TX_line_0/OUTB" "txinb" 625.45
cap "TX_line_0/OUTB" "txinb" 625.45
cap "TX_line_0/OUTB" "txinb" 625.45
cap "TX_line_0/OUTB" "txinb" 625.45
cap "txinb" "TX_line_0/OUTB" 625.45
cap "TX_line_0/OUTB" "txinb" 625.45
cap "TX_line_0/OUTB" "txinb" 625.45
cap "TX_line_0/OUTB" "txinb" 625.45
cap "TX_line_0/OUTB" "txinb" 625.45
cap "TX_line_0/OUTB" "TX_line_0/INB" 625.45
cap "TX_line_0/OUTB" "TX_line_0/INB" 625.45
cap "TX_line_0/INB" "TX_line_0/OUTB" 857.01
cap "TX_line_0/OUTB" "TX_line_0/INB" 464.66
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 531.641
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1650.05
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "VGA_routing_0/m1_443471_411908#" "TX_line_0/OUTB" 771.727
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 928.884
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 771.727
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 928.884
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 771.727
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 928.884
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 771.727
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 722.822
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 928.884
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 771.727
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 474.147
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "VGA_routing_0/m1_443471_411908#" "TX_line_0/OUTB" 928.884
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "VGA_routing_0/m1_443471_411908#" "TX_line_0/OUTB" 771.727
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "VGA_routing_0/m1_443471_411908#" "TX_line_0/OUTB" 928.884
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 771.727
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 928.884
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "VGA_routing_0/m1_443471_411908#" "TX_line_0/OUTB" 771.727
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 928.884
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 771.727
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "VGA_routing_0/m1_443471_411908#" "TX_line_0/OUTB" 928.884
cap "VGA_routing_0/m1_443471_411908#" "TX_line_0/OUTB" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 771.727
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 928.884
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 771.727
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 928.884
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 771.727
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 928.884
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 771.727
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "VGA_routing_0/m1_443471_411908#" "TX_line_0/OUTB" 928.884
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 771.727
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 928.884
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 771.727
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 928.884
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 771.727
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 928.884
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 771.727
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "VGA_routing_0/m1_443471_411908#" "TX_line_0/OUTB" 928.884
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 771.727
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 928.884
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "VGA_routing_0/m1_443471_411908#" "TX_line_0/OUTB" 771.727
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "VGA_routing_0/m1_443471_411908#" "TX_line_0/OUTB" 928.884
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 771.727
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 928.884
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "VGA_routing_0/m1_443471_411908#" "TX_line_0/OUTB" 771.727
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "VGA_routing_0/m1_443471_411908#" "TX_line_0/OUTB" 928.884
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 771.727
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 928.884
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 771.727
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 928.884
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 771.727
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 928.884
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 771.727
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 928.884
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 771.727
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "vssa2" "VCO_1/X9/XM2/a_15_n100#" 0.942058
cap "VCO_1/X9/GND" "VCO_1/CTRL1" -9.53755
cap "vssa2" "VCO_1/CTRL1" 65.5325
cap "VCO_1/CTRL2" "VCO_1/CTRL5" 9.36531
cap "VCO_1/X9/XM3/a_n33_n100#" "VCO_1/CTRL1" -11.2263
cap "VCO_1/CTRL5" "VCO_1/CTRL1" 1.552
cap "vssa2" "VCO_1/CTRL3" 0.00159515
cap "VCO_1/CTRL2" "VCO_1/CTRL1" 86.5029
cap "VCO_1/X9/GND" "vssa2" 0.825464
cap "VCO_1/CTRL2" "VCO_1/CTRL4" 11.1924
cap "VCO_1/X9/XM2/a_15_n100#" "VCO_1/CTRL1" -7.48714
cap "VCO_1/CTRL4" "VCO_1/CTRL1" 2.10716
cap "vssa2" "VCO_1/X9/XM3/a_n33_n100#" 1.87896
cap "VCO_1/CTRL2" "VCO_1/CTRL3" 18.7287
cap "VCO_1/CTRL2" "vssa2" 7.8535
cap "VCO_1/CTRL3" "VCO_1/CTRL1" 1.73225
cap "VCO_1/X9/XM3/a_n33_n100#" "VCO_1/CTRL2" -9.23895
cap "VCO_1/CTRL5" "VCO_1/CTRL1" 4.18677
cap "VCO_1/X9/GND" "vssa2" 1.28934
cap "VCO_1/X9/XM4/a_111_n100#" "vssa2" 24.6737
cap "VCO_1/CTRL1" "VCO_1/CTRL3" 0.288329
cap "VCO_1/CTRL4" "vssa2" 5.51582
cap "VCO_1/X9/XM4/a_111_n100#" "VCO_1/CTRL2" -25.4447
cap "VCO_1/X9/GND" "VCO_1/CTRL2" -38.2488
cap "VCO_1/CTRL2" "VCO_1/X9/XM2/a_15_n100#" -0.189217
cap "VCO_1/CTRL4" "VCO_1/CTRL2" 0.704011
cap "VCO_1/X9/XM5/a_159_n100#" "vssa2" 23.7943
cap "VCO_1/CTRL5" "vssa2" -0.0715268
cap "VCO_1/CTRL2" "vssa2" 25.7607
cap "vssa2" "VCO_1/CTRL3" 14.0915
cap "VCO_1/X9/XM5/a_159_n100#" "VCO_1/CTRL2" -28.6563
cap "VCO_1/CTRL5" "VCO_1/CTRL2" 0.421875
cap "VCO_1/CTRL2" "VCO_1/CTRL3" 0.961572
cap "VCO_1/CTRL4" "VCO_1/CTRL1" 2.65884
cap "VCO_1/X9/XM3/a_n33_n100#" "vssa2" 0.0843959
cap "VCO_1/CTRL1" "vssa2" 99.7552
cap "vssa2" "VCO_1/CTRL4" 8.53698
cap "VCO_1/CTRL3" "vssa2" 12.153
cap "vssa2" "VCO_1/CTRL2" 25.7607
cap "VCO_1/CTRL1" "VCO_1/CTRL5" 0.478487
cap "vssa2" "VCO_1/X9/XM5/a_159_n100#" 42.1743
cap "vssa2" "VCO_1/CTRL1" 99.7552
cap "VCO_1/X9/XM3/a_n227_n274#" "vssa2" 0.151499
cap "vssa2" "VCO_1/CTRL5" 4.62147
cap "VCO_1/CTRL2" "VCO_1/CTRL5" 0.625476
cap "VCO_1/CTRL3" "vssa2" 12.153
cap "VCO_1/CTRL2" "vssa2" 25.7607
cap "vssa2" "VCO_1/CTRL5" 4.84095
cap "vssa2" "VCO_1/X9/XM5/a_n225_n100#" 41.4619
cap "VCO_1/CTRL4" "vssa2" 8.53698
cap "VCO_1/CTRL1" "vssa2" 99.7552
cap "VCO_1/CTRL4" "vssa2" 8.53698
cap "VCO_1/CTRL5" "vssa2" 4.84095
cap "VCO_1/X9/m1_4700_270#" "vssa2" 41.4874
cap "VCO_1/X9/XC4/c2_n851_n400#" "vssa2" 0.0188803
cap "VCO_1/CTRL2" "vssa2" 25.7607
cap "VCO_1/CTRL3" "vssa2" 12.153
cap "VCO_1/CTRL1" "vssa2" 99.7552
cap "vssa2" "VCO_1/CTRL2" 25.7589
cap "vssa2" "VCO_1/CTRL3" 12.1515
cap "vssa2" "VCO_1/X9/m1_4700_270#" 16.3923
cap "vssa2" "VCO_1/CTRL1" 99.7531
cap "vssa2" "VCO_1/X11/m1_4700_270#" 1.01758
cap "vssa2" "VCO_1/CTRL4" 8.53593
cap "vssa2" "VCO_1/CTRL5" 4.84035
cap "vssa2" "VCO_1/CTRL3" 12.1515
cap "vssa2" "VCO_1/X11/XC4/m4_n951_n500#" 41.9863
cap "vssa2" "VCO_1/X11/IN" 0.0131403
cap "vssa2" "VCO_1/CTRL2" 25.7589
cap "vssa2" "VCO_1/CTRL4" 8.53593
cap "vssa2" "VCO_1/CTRL5" 4.84035
cap "vssa2" "VCO_1/CTRL1" 99.7531
cap "vssa2" "VCO_1/CTRL2" 25.7607
cap "VCO_1/X11/IN" "vssa2" 0.00573846
cap "VCO_1/X11/XC4/m4_n951_n500#" "vssa2" 41.4707
cap "vssa2" "VCO_1/CTRL4" 8.53698
cap "VCO_1/CTRL5" "vssa2" 4.84095
cap "vssa2" "VCO_1/CTRL1" 99.7552
cap "vssa2" "VCO_1/CTRL3" 12.153
cap "vssa2" "VCO_1/CTRL1" 99.7552
cap "vssa2" "VCO_1/CTRL4" 8.53698
cap "vssa2" "VCO_1/CTRL2" 25.7607
cap "VCO_1/X11/m1_4700_270#" "vssa2" 41.4619
cap "vssa2" "VCO_1/CTRL3" 12.153
cap "vssa2" "VCO_1/CTRL5" 4.84095
cap "VCO_1/X11/XM5/a_n419_n274#" "vssa2" 0.979328
cap "VCO_1/X11/XM5/a_15_122#" "vssa2" 0.000149651
cap "VCO_1/X11/m1_4700_270#" "vssa2" 39.3737
cap "VCO_1/CTRL1" "vssa2" 99.7552
cap "VCO_1/X11/XM5/a_n177_122#" "vssa2" 0.000149651
cap "VCO_1/CTRL4" "vssa2" 9.33542
cap "VCO_1/X11/XM5/a_207_122#" "vssa2" 0.000149651
cap "VCO_1/X11/m1_4820_n460#" "vssa2" 0.63291
cap "VCO_1/CTRL5" "vssa2" 1.76086
cap "VCO_1/CTRL2" "vssa2" 25.7607
cap "VCO_1/CTRL3" "vssa2" 12.153
cap "VCO_1/X11/m1_4820_n1420#" "vssa2" 0.934767
cap "vssa2" "VCO_1/X11/XM2/a_n33_n188#" 0.000149651
cap "VCO_1/CTRL4" "vssa2" 0.00084799
cap "VCO_1/X11/XM4/a_n33_122#" "vssa2" 0.000149651
cap "VCO_1/CTRL2" "vssa2" 24.6986
cap "VCO_1/X11/XM5/a_n419_n274#" "vssa2" 1.28059
cap "VCO_1/CTRL3" "vssa2" 7.56584
cap "VCO_1/X11/m1_4820_n460#" "vssa2" 24.0407
cap "VCO_1/X11/m1_4820_n890#" "vssa2" 1.94882
cap "VCO_1/X11/XM3/a_n81_n188#" "vssa2" 0.000149651
cap "VCO_1/CTRL1" "vssa2" 107.896
cap "vssa2" "VCO_1/CTRL1" 0.214821
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 928.884
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 771.727
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "CTRL5" "VCO_1/X9/GND" 39.2405
cap "VCO_1/X9/ctrll3" "vssa2" -1.76476
cap "VCO_1/X9/GND" "vssa2" 0.175191
cap "VCO_1/X9/ctrll3" "VCO_1/X9/ctrll4" 9.16192
cap "VCO_1/X9/ctrll3" "VCO_1/X9/XM1/a_n73_n100#" 0.000149331
cap "VCO_1/X9/XM2/a_15_n100#" "VCO_1/X9/ctrll2" 8.50668
cap "VCO_1/X9/ctrll1" "VCO_1/X9/ctrll2" 11.3377
cap "VCO_1/X9/ctrll4" "VCO_1/X9/XM1/a_n73_n100#" 0.563018
cap "VCO_1/X9/XM3/a_n33_n100#" "VCO_1/X9/ctrll2" -4.92118
cap "VCO_1/X9/ctrll1" "VCO_1/X9/XM2/a_15_n100#" -12.3699
cap "VCO_1/X9/GND" "VCO_1/X9/ctrll3" 25.4588
cap "VCO_1/X9/ctrll1" "VCO_1/X9/XM3/a_n33_n100#" -3.25003
cap "VCO_1/X9/GND" "VCO_1/X9/ctrll4" 20.4751
cap "VCO_1/X9/ctrll2" "VCO_1/X9/ctrll5" 63.8493
cap "VCO_1/X9/ctrll1" "VCO_1/X9/ctrll5" 74.2146
cap "VCO_1/X9/XM2/a_15_n100#" "VCO_1/X9/ctrll5" 210.07
cap "VCO_1/X9/XM3/a_n33_n100#" "VCO_1/X9/ctrll5" 196.292
cap "vssa2" "VCO_1/X9/ctrll2" 0.000354014
cap "VCO_1/X9/XM2/a_15_n100#" "vssa2" 0.366116
cap "VCO_1/X9/XM3/a_n33_n100#" "vssa2" 0.71993
cap "VCO_1/X9/ctrll3" "VCO_1/X9/ctrll2" 59.8124
cap "VCO_1/X9/ctrll4" "VCO_1/X9/ctrll2" 53.8657
cap "VCO_1/X9/ctrll1" "VCO_1/X9/ctrll3" 65.4027
cap "VCO_1/X9/ctrll1" "VCO_1/X9/ctrll4" 67.7802
cap "VCO_1/X9/XM2/a_15_n100#" "VCO_1/X9/ctrll3" 18.6013
cap "VCO_1/X9/XM3/a_n33_n100#" "VCO_1/X9/ctrll4" 22.3301
cap "VCO_1/X9/XM2/a_15_n100#" "VCO_1/X9/ctrll4" 23.1619
cap "VCO_1/X9/ctrll3" "VCO_1/X9/XM3/a_n33_n100#" 25.4993
cap "VCO_1/X9/GND" "VCO_1/X9/ctrll2" 19.0068
cap "VCO_1/X9/ctrll3" "VCO_1/X9/ctrll5" 14.6107
cap "VCO_1/X9/GND" "VCO_1/X9/ctrll1" -1.12324
cap "VCO_1/X9/XM1/a_n73_n100#" "VCO_1/X9/ctrll5" 6.40754
cap "VCO_1/X9/GND" "VCO_1/X9/XM2/a_15_n100#" 8.40706
cap "VCO_1/X9/GND" "VCO_1/X9/XM3/a_n33_n100#" 10.3059
cap "VCO_1/X9/GND" "VCO_1/X9/ctrll5" 100.424
cap "VCO_1/X9/ctrll5" "VCO_1/X9/XM1/a_n73_n100#" 3.8023
cap "VCO_1/X9/XM4/a_111_n100#" "VCO_1/X9/ctrll2" -6.56398
cap "VCO_1/X9/ctrll5" "VCO_1/X9/XC6/c2_n451_n200#" 0.634781
cap "VCO_1/X9/ctrll1" "VCO_1/X9/ctrll4" 1.36695
cap "vssa2" "VCO_1/X9/ctrll4" 0.240771
cap "VCO_1/X9/ctrll5" "VCO_1/X9/XM3/a_n33_n100#" 43.7207
cap "VCO_1/X9/XM4/a_111_n100#" "VCO_1/X9/ctrll4" 37.494
cap "VCO_1/X9/XM2/a_15_n100#" "VCO_1/X9/ctrll3" -4.68043
cap "VCO_1/X9/ctrll1" "VCO_1/X9/XM4/a_111_n100#" -4.33566
cap "VCO_1/X9/GND" "VCO_1/X9/XM3/a_n33_n100#" 8.04927
cap "VCO_1/X9/GND" "VCO_1/X9/ctrll5" 73.8618
cap "vssa2" "VCO_1/X9/XM4/a_111_n100#" 12.0513
cap "VCO_1/X9/XM5/a_159_n100#" "VCO_1/X9/ctrll5" 332.636
cap "VCO_1/X9/GND" "VCO_1/X9/XM5/a_159_n100#" 17.4057
cap "VCO_1/X9/XM3/a_n33_n100#" "VCO_1/X9/ctrll3" -19.1738
cap "VCO_1/X9/ctrll4" "VCO_1/X9/XM2/a_15_n100#" 2.75106
cap "VCO_1/X9/ctrll5" "VCO_1/X9/ctrll3" 60.8015
cap "VCO_1/X9/ctrll2" "VCO_1/X9/XM3/a_n33_n100#" -0.35617
cap "VCO_1/X9/ctrll5" "VCO_1/X9/ctrll2" 2.88759
cap "VCO_1/X9/XM1/a_n73_n100#" "VCO_1/X9/ctrll4" 0.409812
cap "VCO_1/X9/GND" "VCO_1/X9/ctrll3" -50.0214
cap "VCO_1/X9/XM5/a_159_n100#" "VCO_1/X9/ctrll3" -50.6237
cap "VCO_1/X9/XM5/a_159_n100#" "VCO_1/X9/ctrll2" -8.07356
cap "VCO_1/X9/GND" "VCO_1/X9/ctrll2" 3.31218
cap "VCO_1/X9/ctrll5" "VCO_1/X9/ctrll4" 91.0171
cap "VCO_1/X9/XM3/a_n33_n100#" "VCO_1/X9/ctrll4" 7.16184
cap "VCO_1/X9/ctrll1" "VCO_1/X9/XM3/a_n33_n100#" -0.23537
cap "VCO_1/X9/ctrll2" "VCO_1/X9/ctrll3" -2.21014
cap "VCO_1/X9/GND" "VCO_1/X9/ctrll4" 31.3356
cap "vssa2" "VCO_1/X9/XM3/a_n33_n100#" 0.0201282
cap "vssa2" "VCO_1/X9/ctrll5" 0.000563014
cap "VCO_1/X9/ctrll1" "VCO_1/X9/ctrll5" 2.19023
cap "VCO_1/X9/XM5/a_159_n100#" "VCO_1/X9/ctrll4" -11.9247
cap "VCO_1/X9/GND" "VCO_1/X9/ctrll1" 0.984691
cap "VCO_1/X9/XM4/a_111_n100#" "VCO_1/X9/ctrll5" 385.01
cap "VCO_1/X9/GND" "vssa2" 0.284284
cap "VCO_1/X9/ctrll1" "VCO_1/X9/XM5/a_159_n100#" -5.33531
cap "VCO_1/X9/XM5/a_159_n100#" "vssa2" 21.9015
cap "VCO_1/X9/ctrll4" "VCO_1/X9/ctrll3" 75.0164
cap "VCO_1/X9/GND" "VCO_1/X9/XM4/a_111_n100#" 14.2446
cap "VCO_1/X9/ctrll2" "VCO_1/X9/ctrll4" 1.609
cap "VCO_1/X9/ctrll1" "VCO_1/X9/ctrll3" 1.06996
cap "vssa2" "VCO_1/X9/ctrll3" 4.89531
cap "VCO_1/X9/XM4/a_111_n100#" "VCO_1/X9/ctrll3" -46.1907
cap "VCO_1/X9/ctrll5" "VCO_1/X9/XM2/a_15_n100#" 22.0718
cap "vssa2" "VCO_1/X9/XM3/a_n227_n274#" 0.0293161
cap "VCO_1/X9/ctrll5" "VCO_1/X9/XM3/a_63_n100#" 2.15972
cap "VCO_1/X9/ctrll4" "VCO_1/X9/XM5/a_159_n100#" -10.9433
cap "VCO_1/X9/XM4/a_111_n100#" "VCO_1/X9/ctrll5" 1.78214
cap "VCO_1/X9/XM5/a_159_n100#" "VCO_1/X9/ctrll3" -2.35312
cap "vssa2" "VCO_1/X9/XM5/a_159_n100#" 41.7383
cap "VCO_1/X9/ctrll5" "VCO_1/X9/XC6/c2_n451_n200#" 0.0319846
cap "vssa2" "VCO_1/X9/ctrll4" 3.29256
cap "VCO_1/X9/ctrll5" "VCO_1/X9/XM3/a_n227_n274#" 4.52739
cap "VCO_1/X9/ctrll5" "VCO_1/CTRL1" 1.82669
cap "VCO_1/X9/XM5/a_159_n100#" "VCO_1/CTRL2" -1.84979
cap "VCO_1/X9/m1_4820_n890#" "VCO_1/X9/ctrll5" 1.74344
cap "vssa2" "VCO_1/X9/ctrll3" 6.49773
cap "VCO_1/X9/m1_4820_n1420#" "VCO_1/X9/ctrll4" -0.139985
cap "VCO_1/X9/ctrll5" "VCO_1/X9/XM5/a_159_n100#" 74.2453
cap "VCO_1/X9/ctrll4" "VCO_1/X9/XM3/a_63_n100#" -2.76583
cap "VCO_1/X9/ctrll4" "VCO_1/X9/XM4/a_111_n100#" -3.29582
cap "VCO_1/X9/ctrll4" "VCO_1/X9/ctrll5" 25.6041
cap "VCO_1/X9/ctrll5" "VCO_1/X9/ctrll3" 3.63456
cap "vssa2" "VCO_1/X9/ctrll5" 0.448605
cap "VCO_1/X9/XM5/a_159_n100#" "VCO_1/CTRL1" -1.22241
cap "VCO_1/X9/ctrll4" "VCO_1/X9/XC6/c2_n451_n200#" -0.0617387
cap "VCO_1/X9/ctrll4" "VCO_1/X9/XM3/a_n227_n274#" -2.78899
cap "VCO_1/X9/ctrll5" "VCO_1/CTRL2" 2.40831
cap "VCO_1/X9/m1_4820_n890#" "VCO_1/X9/ctrll4" -7.65496
cap "VCO_1/X9/m1_4820_n1420#" "VCO_1/X9/ctrll5" 0.320414
cap "VCO_1/X9/XM5/a_n225_n100#" "VCO_1/X9/ctrll5" -7.10543e-15
cap "vssa2" "VCO_1/CTRL3" 6.49773
cap "vssa2" "VCO_1/X9/ctrll5" 0.944057
cap "vssa2" "VCO_1/CTRL4" 3.29256
cap "vssa2" "VCO_1/X9/XM5/a_n225_n100#" 41.4619
cap "VCO_1/X9/m1_4700_270#" "VCO_1/CTRL3" -0.107632
cap "VCO_1/X9/m1_4700_270#" "VCO_1/CTRL1" -0.0559923
cap "VCO_1/CTRL5" "vssa2" 0.944057
cap "VCO_1/CTRL4" "vssa2" 3.29256
cap "VCO_1/X9/IN" "vssa2" 0.0335434
cap "VCO_1/CTRL5" "VCO_1/X9/m1_4700_270#" -0.133253
cap "VCO_1/X9/m1_4700_270#" "VCO_1/CTRL4" -0.124926
cap "VCO_1/X9/m1_4700_270#" "VCO_1/CTRL2" -0.0846501
cap "VCO_1/CTRL3" "vssa2" 6.49773
cap "VCO_1/X9/m1_4700_270#" "vssa2" 41.4874
cap "VCO_1/X9/m1_4700_270#" "VCO_1/CTRL5" -0.0518799
cap "VCO_1/X11/m1_4700_270#" "VCO_1/CTRL1" -0.0012679
cap "VCO_1/X11/m1_4700_270#" "VCO_1/CTRL2" -0.00191684
cap "vssa2" "VCO_1/CTRL3" 6.49773
cap "VCO_1/CTRL1" "VCO_1/X9/m1_4700_270#" -0.0217998
cap "VCO_1/X11/m1_4700_270#" "VCO_1/CTRL4" -0.00282887
cap "vssa2" "VCO_1/CTRL5" 0.944057
cap "VCO_1/X9/m1_4700_270#" "VCO_1/CTRL2" -0.0329573
cap "VCO_1/X9/m1_4700_270#" "VCO_1/CTRL4" -0.0486382
cap "vssa2" "VCO_1/CTRL4" 3.29256
cap "VCO_1/X11/m1_4700_270#" "vssa2" 1.09443
cap "VCO_1/X11/m1_4700_270#" "VCO_1/CTRL3" -0.00243726
cap "VCO_1/X11/m1_4700_270#" "VCO_1/CTRL5" -0.00301741
cap "vssa2" "VCO_1/X9/m1_4700_270#" 16.8563
cap "VCO_1/X9/m1_4700_270#" "VCO_1/CTRL3" -0.0419051
cap "VCO_1/X11/XC4/m4_n951_n500#" "VCO_1/CTRL3" -0.11007
cap "vssa2" "VCO_1/X11/IN" 0.0233482
cap "VCO_1/X11/XC4/m4_n951_n500#" "vssa2" 42.3735
cap "VCO_1/X11/XC4/m4_n951_n500#" "VCO_1/CTRL4" -0.127755
cap "vssa2" "VCO_1/CTRL5" 0.944057
cap "VCO_1/X11/XC4/m4_n951_n500#" "VCO_1/CTRL2" -0.0865669
cap "vssa2" "VCO_1/CTRL3" 6.49773
cap "VCO_1/X11/XC4/m4_n951_n500#" "VCO_1/CTRL1" -0.0572602
cap "vssa2" "VCO_1/CTRL4" 3.29256
cap "VCO_1/X11/XC4/m4_n951_n500#" "VCO_1/CTRL5" -0.13627
cap "VCO_1/X11/XC4/m4_n951_n500#" "VCO_1/CTRL3" -0.0370306
cap "vssa2" "VCO_1/X11/XC4/m4_n951_n500#" 41.4707
cap "VCO_1/X11/XC4/m4_n951_n500#" "VCO_1/CTRL5" -0.0458451
cap "vssa2" "VCO_1/X11/IN" 0.0101951
cap "vssa2" "VCO_1/CTRL3" 6.49773
cap "vssa2" "VCO_1/CTRL5" 0.944057
cap "VCO_1/X11/XC4/m4_n951_n500#" "VCO_1/CTRL2" -0.0291236
cap "VCO_1/CTRL1" "VCO_1/X11/XC4/m4_n951_n500#" -0.019264
cap "VCO_1/X11/XC4/m4_n951_n500#" "VCO_1/CTRL4" -0.0429805
cap "vssa2" "VCO_1/CTRL4" 3.29256
cap "VCO_1/CTRL3" "vssa2" 6.49773
cap "VCO_1/X11/m1_4700_270#" "vssa2" 41.4619
cap "vssa2" "VCO_1/CTRL5" 0.944057
cap "VCO_1/CTRL4" "vssa2" 3.29256
cap "VCO_1/CTRL4" "VCO_1/X11/m1_4700_270#" -0.107846
cap "VCO_1/X11/XM5/a_207_122#" "vssa2" 2.52086e-05
cap "VCO_1/X11/m1_4820_n460#" "vssa2" 0.359167
cap "vssa2" "VCO_1/X11/XM5/a_n419_n274#" 0.211521
cap "VCO_1/CTRL2" "VCO_1/X11/m1_4700_270#" -0.0730168
cap "VCO_1/CTRL4" "vssa2" 3.08336
cap "VCO_1/CTRL3" "VCO_1/X11/m1_4700_270#" -0.092885
cap "VCO_1/X11/m1_4700_270#" "VCO_1/CTRL5" -0.0509955
cap "vssa2" "VCO_1/X11/XM5/a_n177_122#" 2.52086e-05
cap "VCO_1/X11/m1_4700_270#" "vssa2" 37.7369
cap "VCO_1/X11/XM5/a_15_122#" "vssa2" 2.52086e-05
cap "VCO_1/CTRL3" "vssa2" 6.49773
cap "vssa2" "VCO_1/CTRL5" 0.270982
cap "VCO_1/CTRL1" "VCO_1/X11/m1_4700_270#" -0.0482522
cap "vssa2" "VCO_1/X11/m1_4820_n460#" 12.1473
cap "VCO_1/CTRL2" "VCO_1/X11/m1_4820_n460#" -0.0227987
cap "vssa2" "VCO_1/X11/m1_4820_n890#" 1.10667
cap "vssa2" "VCO_1/X11/XM3/a_n81_n188#" 2.52086e-05
cap "vssa2" "VCO_1/CTRL4" 0.000222418
cap "VCO_1/CTRL2" "vssa2" 0.000328806
cap "VCO_1/X11/m1_4820_n460#" "VCO_1/CTRL3" -0.0290024
cap "VCO_1/CTRL1" "VCO_1/X11/m1_4820_n460#" -0.0150663
cap "vssa2" "VCO_1/X11/m1_4820_n1420#" 0.529833
cap "vssa2" "VCO_1/X11/XM5/a_n419_n274#" 0.27727
cap "vssa2" "VCO_1/CTRL3" 2.32572
cap "vssa2" "VCO_1/X11/XM2/a_n33_n188#" 2.52086e-05
cap "vssa2" "VCO_1/X11/XM4/a_n33_122#" 2.52086e-05
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 928.884
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 771.727
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "VCO_1/X9/XM2/a_15_n100#" "VCO_1/X9/ctrll5" 8.26482
cap "VCO_1/X9/GND" "VCO_1/X9/ctrll3" 2.08766
cap "VCO_1/X9/ctrll4" "VCO_1/X9/XM2/a_15_n100#" 5.93871
cap "VCO_1/X9/ctrll1" "VCO_1/X9/ctrll5" 2.12977
cap "VCO_1/X9/ctrll4" "VCO_1/X9/ctrll1" 1.03445
cap "VCO_1/X9/XM2/a_15_n100#" "VCO_1/X9/ctrll3" 3.53536
cap "VCO_1/X9/XM1/a_n73_n100#" "VCO_1/X9/ctrll2" -0.467139
cap "VCO_1/X9/ctrll1" "VCO_1/X9/ctrll3" 0.136067
cap "VCO_1/X9/XM1/a_n73_n100#" "VCO_1/X9/ctrll5" 11.647
cap "VCO_1/X9/GND" "VCO_1/X9/ctrll2" 0.369243
cap "VCO_1/X9/ctrll1" "VCO_1/X9/XM1/a_n73_n100#" -1.04179
cap "VCO_1/X9/ctrll4" "VCO_1/X9/XM1/a_n73_n100#" 4.58322
cap "VCO_1/X9/GND" "VCO_1/X9/ctrll5" 4.34317
cap "VCO_1/X9/ctrll4" "VCO_1/X9/GND" 3.09538
cap "VCO_1/X9/ctrll2" "VCO_1/X9/XM2/a_15_n100#" -0.686447
cap "VCO_1/X9/XM1/a_n73_n100#" "VCO_1/X9/ctrll3" 0.000171801
cap "VCO_1/X9/ctrll4" "VCO_1/X9/GND" 2.4286
cap "VCO_1/X9/ctrll5" "VCO_1/X9/XM1/a_n73_n100#" 3.30404
cap "VCO_1/X9/ctrll5" "VCO_1/X9/XM2/a_15_n100#" 7.27969
cap "VCO_1/X9/ctrll3" "VCO_1/X9/XM1/a_n73_n100#" -0.174238
cap "VCO_1/X9/ctrll5" "VCO_1/X9/XC6/c2_n451_n200#" 4.3068
cap "VCO_1/X9/XM2/a_15_n100#" "VCO_1/X9/ctrll3" -0.0467756
cap "VCO_1/X9/ctrll5" "VCO_1/X9/GND" 3.88176
cap "VCO_1/X9/GND" "VCO_1/X9/ctrll3" 0.106156
cap "VCO_1/X9/ctrll4" "VCO_1/X9/XM1/a_n73_n100#" 1.43453
cap "VCO_1/X9/ctrll4" "VCO_1/X9/XM2/a_15_n100#" 2.25678
cap "VCO_1/X9/ctrll4" "VCO_1/X9/XC6/c2_n451_n200#" -0.0704827
cap "VCO_1/X9/m1_4820_n890#" "VCO_1/X9/ctrll5" 7.10543e-15
cap "VCO_1/X9/XC6/c2_n451_n200#" "VCO_1/X9/ctrll5" 0.86718
cap "VCO_1/X9/XM3/a_n227_n274#" "VCO_1/X9/ctrll5" 1.08021
cap "VCO_1/X9/m1_4820_n1420#" "VCO_1/X9/ctrll5" 1.07968
cap "VGA_routing_0/m1_443471_411908#" "TX_line_0/OUTB" 928.884
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 771.727
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 722.822
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 928.884
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 771.727
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 928.884
cap "VGA_routing_0/m1_443471_411908#" "TX_line_0/OUTB" 1692.46
cap "VGA_routing_0/m1_443471_411908#" "TX_line_0/OUTB" 771.727
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 928.884
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "VGA_routing_0/m1_443471_411908#" "TX_line_0/OUTB" 771.727
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 722.822
cap "VCO_1/X6/XM1/a_15_n100#" "VCO_1/VDD" 0.033642
cap "VCO_1/X6/XM1/a_n73_n100#" "VCO_1/VDD" 0.00365458
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 928.884
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 771.727
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "VCO_1/GND" "VCO_1/VDD" 55.3791
cap "VCO_1/X6/XM1/a_n33_n188#" "VCO_1/VDD" 0.116926
cap "VCO_1/GND" "VCO_1/VDD" 6.83448
cap "VCO_1/X6/ctrll1" "VCO_1/VDD" 0.112837
cap "VCO_1/X6/XM1/a_n73_n100#" "VCO_1/VDD" 7.08966
cap "VCO_1/X3/X2/XR2/a_n703_n3602#" "VCO_1/VDD" 5.69172
cap "VCO_1/X6/ctrll2" "VCO_1/VDD" 0.232946
cap "VGA_routing_0/m1_443471_411908#" "TX_line_0/OUTB" 928.884
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 771.727
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "VCO_1/GND" "VCO_1/X3/X2/VDD" 32.9642
cap "VCO_1/X3/X2/XR2/a_n703_n3602#" "VCO_1/X3/X2/VDD" 28.9139
cap "VCO_1/X3/X2/VDD" "VCO_1/X6/XM1/a_n33_n188#" -0.253694
cap "VCO_1/X6/XM1/a_n73_n100#" "VCO_1/X3/X2/VDD" -11.4323
cap "VCO_1/X3/X2/VDD" "VCO_1/GND" -69.0694
cap "VCO_1/X3/X2/VDD" "VCO_1/X6/XM1/a_15_n100#" -0.042082
cap "VCO_1/X6/ctrll2" "VCO_1/X3/X2/VDD" -2.27325
cap "VCO_1/X6/ctrll1" "VCO_1/X3/X2/VDD" -2.46893
cap "VCO_1/GND" "VCO_1/X3/X2/XR2/a_n703_n3602#" -0.124969
cap "VCO_1/GND" "VCO_1/X3/X2/VDD" 2.97262
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 928.884
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1692.46
cap "VGA_routing_0/m1_443471_411908#" "TX_line_0/OUTB" 771.727
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "VCO_1/X3/X2/XR2/a_n703_n3602#" "vdda2" 21.006
cap "VCO_1/X3/X2/XR2/a_n703_n3602#" "VCO_1/X3/X2/VDD" 0.203795
cap "vdda2" "VCO_1/X3/X2/XR2/a_n703_n3602#" 34.2356
cap "VCO_1/X3/X2/GND" "vdda2" 34.2356
cap "VCO_1/X3/X2/GND" "vdda2" 31.4979
cap "VCO_1/X3/X2/XM4/a_207_122#" "vdda2" 0.0141687
cap "VCO_1/X3/X2/XM4/a_399_122#" "vdda2" 0.0141687
cap "VCO_1/X3/X2/XM4/a_n177_122#" "vdda2" 0.0141687
cap "VCO_1/X3/X2/XM4/a_n417_n100#" "vdda2" 4.27281
cap "VCO_1/X3/X2/XM4/a_15_122#" "vdda2" 0.0141687
cap "VCO_1/X3/X2/XM4/a_n369_122#" "vdda2" 0.0141687
cap "VCO_1/X3/X4/SUB" "vdda2" 91.9799
cap "vdda2" "VCO_1/X3/X2/BIAS" 38.0254
cap "vdda2" "VCO_1/X3/X2/INA" 0.155813
cap "VCO_1/X3/X2/XM3/a_15_n100#" "vdda2" 0.157707
cap "VCO_1/X3/I2B" "vdda2" 3.15092
cap "VCO_1/X3/X2/XM4/a_n417_n100#" "vdda2" 1.51139
cap "VCO_1/X3/X4/OUTB" "vdda2" 0.528494
cap "VCO_1/X3/X4/INB" "vdda2" 0.319537
cap "vdda2" "VCO_1/X3/X4/SUB" 4.64693
cap "vdda2" "VCO_1/X3/X4/XM3/a_15_n100#" 0.157707
cap "VCO_1/X3/X4/INA" "vdda2" 0.155813
cap "vdda2" "VCO_1/X3/X4/INB" 2.84689
cap "vdda2" "VCO_1/X3/X4/XM4/a_15_122#" 0.0141687
cap "vdda2" "VCO_1/X3/X4/OUTB" 0.528494
cap "vdda2" "VCO_1/X3/X4/GND" 59.5275
cap "vdda2" "VCO_1/X3/X4/XM4/a_399_122#" 0.0141687
cap "vdda2" "VCO_1/X3/X4/XM3/a_n73_n100#" 5.01636
cap "vdda2" "VCO_1/X3/X4/BIAS" 23.7938
cap "vdda2" "VCO_1/X3/X4/XM4/a_207_122#" 0.0141687
cap "VCO_1/X3/X4/XM4/a_n177_122#" "vdda2" 0.0141687
cap "vdda2" "VCO_1/X3/X4/BIAS" 14.2316
cap "VCO_1/X3/X4/GND" "vdda2" 55.4757
cap "vdda2" "VCO_1/X3/X4/XM3/a_n73_n100#" 0.767839
cap "vdda2" "VCO_1/X3/X4/XM4/a_n369_122#" 0.0141687
cap "vdda2" "VCO_1/X3/X4/GND" 33.1658
cap "vdda2" "VCO_1/X3/X4/XR1/a_n703_n3602#" 33.1658
cap "vdda2" "VCO_1/X3/X4/XR1/a_n703_n3602#" 22.4065
cap "VCO_1/output_buffer_0/XR3/a_n573_1640#" "vdda2" 0.519618
cap "vdda2" "VCO_1/X3/X4/XR1/a_n703_n3602#" 3.20731
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 928.884
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 1721.89
cap "VGA_routing_0/m1_443471_411908#" "TX_line_0/OUTB" 1717.09
cap "VGA_routing_0/m1_443471_411908#" "TX_line_0/OUTB" 919.486
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 919.486
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 919.486
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 919.486
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 919.486
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 919.486
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 456.536
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 919.486
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 709.115
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 709.115
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 919.486
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 709.115
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 919.486
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 919.486
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 697.467
cap "VGA_routing_0/m1_443471_411908#" "TX_line_0/OUTB" 537.95
cap "VCO_1/X3/X2/XR1/a_n703_n3602#" "vdda2" 126.442
cap "VCO_1/X3/X2/VDD" "vdda2" 642.962
cap "vdda2" "VCO_1/X3/X2/XR1/a_n703_n3602#" 86.8738
cap "VCO_1/X3/X2/GND" "vdda2" 86.8738
cap "vdda2" "VCO_1/X3/X2/GND" 483.783
cap "vdda2" "VCO_1/X3/X2/XM4/a_15_122#" 0.0858291
cap "vdda2" "VCO_1/X3/X2/XM4/a_n417_n100#" 78.0887
cap "VCO_1/X3/X2/XM4/a_399_122#" "vdda2" 0.0858291
cap "vdda2" "VCO_1/X3/X4/SUB" 230.385
cap "vdda2" "VCO_1/X3/X2/XM4/a_n369_122#" 0.0858291
cap "vdda2" "VCO_1/X3/X2/XM4/a_n177_122#" 0.085711
cap "vdda2" "VCO_1/X3/X4/OUTB" 386.179
cap "VCO_1/X3/X2/XM4/a_207_122#" "vdda2" 0.0855928
cap "vdda2" "VCO_1/X3/X2/BIAS" 173.451
cap "VCO_1/X3/X2/XM3/a_15_n100#" "vdda2" 1.06667
cap "VCO_1/X3/X2/XM4/a_n417_n100#" "vdda2" 17.9076
cap "VCO_1/X3/I1B" "vdda2" 56.3291
cap "VCO_1/X3/X3/XM3/a_n33_n188#" "vdda2" 56.3291
cap "VCO_1/X3/I4A" "vdda2" 56.3291
cap "VCO_1/X3/I3B" "vdda2" 3.69531
cap "VCO_1/X3/X4/INB" "vdda2" 25.418
cap "VCO_1/X3/X2/INA" "vdda2" 1.00405
cap "VCO_1/X3/I2B" "vdda2" 96.4846
cap "VCO_1/X3/X4/SUB" "vdda2" 61.2642
cap "VCO_1/X3/I1A" "vdda2" 3.69531
cap "VCO_1/X3/I2A" "vdda2" 56.3291
cap "VCO_1/X3/X4/OUTB" "vdda2" 879.591
cap "vdda2" "VCO_1/X3/X4/XM3/a_n73_n100#" 71.9948
cap "vdda2" "VCO_1/X3/X4/XM4/a_n177_122#" 0.085711
cap "vdda2" "VCO_1/X3/X4/XM3/a_15_n100#" 1.06667
cap "vdda2" "VCO_1/X3/X4/XM4/a_207_122#" 0.0855928
cap "vdda2" "VCO_1/X3/X4/INA" 1.00405
cap "vdda2" "VCO_1/X3/X4/GND" 202.496
cap "vdda2" "VCO_1/X3/X4/XM4/a_399_122#" 0.0858291
cap "vdda2" "VCO_1/X3/X4/OUTB" 769.886
cap "vdda2" "VCO_1/X3/X4/INB" 70.9987
cap "vdda2" "VCO_1/X3/X4/XM4/a_15_122#" 0.0858291
cap "vdda2" "VCO_1/X3/X4/BIAS" 24.5985
cap "VCO_1/X3/X4/GND" "vdda2" 540.372
cap "VCO_1/X3/X4/BIAS" "vdda2" 191.598
cap "vdda2" "VCO_1/X3/X4/XM4/a_n369_122#" 0.0858291
cap "VCO_1/X3/X4/XM3/a_n73_n100#" "vdda2" 24.0014
cap "VCO_1/X3/X4/GND" "vdda2" 83.3989
cap "vdda2" "VCO_1/X3/X4/BIAS" 96.6862
cap "VCO_1/m1_50680_31080#" "vdda2" 96.6862
cap "VCO_1/X3/X4/XR1/a_n703_n3602#" "vdda2" 83.3989
cap "VCO_1/X3/X4/VDD" "vdda2" 116.38
cap "vdda2" "VCO_1/X3/X4/XR1/a_n703_n3602#" 40.5728
cap "vdda2" "VCO_1/output_buffer_0/BIAS" 6.11035
cap "VCO_1/X3/X4/XR1/a_n703_n3602#" "vdda2" 5.75101
cap "vdda2" "VCO_1/output_buffer_0/XR3/a_n573_1640#" 0.916023
cap "VCO_1/output_buffer_0/BIAS" "vdda2" 4.93576
cap "VCO_1/X3/X4/VDD" "vdda2" 1.51439
cap "VCO_1/output_buffer_0/BIAS" "VCO_1/output_buffer_0/OUTB" 1.43104
cap "VCO_1/output_buffer_0/OUTB" "VCO_1/output_buffer_0/BIAS" 5.2428
cap "VCO_1/output_buffer_0/OUTB" "VCO_1/output_buffer_0/XM4/a_n513_n100#" 2.84392
cap "VCO_1/X3/X4/XR1/a_n703_n3602#" "VCO_1/output_buffer_0/OUTB" 0.200251
cap "VCO_1/output_buffer_0/XM4/a_n417_n100#" "VCO_1/output_buffer_0/OUTB" 1.72201
cap "VCO_1/output_buffer_0/OUTB" "VCO_1/output_buffer_0/BIAS" 2.99427
cap "VCO_1/output_buffer_0/OUTB" "VCO_1/output_buffer_0/XM3/a_n513_n100#" 4.27883
cap "VCO_1/output_buffer_0/OUTB" "VCO_1/output_buffer_0/XM4/a_n513_n100#" 1.38997
cap "VCO_1/output_buffer_0/XR3/a_n703_n2202#" "VCO_1/output_buffer_0/OUTB" 0.988616
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 924.858
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 32.0634
cap "VGA_routing_0/m1_443471_412049#" "TX_line_0/OUTB" 1535.24
cap "VGA_routing_0/m1_443471_411908#" "TX_line_0/OUTB" 83.3681
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1490.84
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_411908#" 23.8976
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 919.486
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 919.486
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 919.486
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 919.486
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 919.486
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 919.486
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 456.536
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 709.115
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 919.486
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 709.115
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 919.486
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 709.115
cap "VGA_routing_0/m1_443471_412049#" "TX_line_0/OUTB" 919.486
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 697.467
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 919.486
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 537.95
cap "vdda2" "VCO_1/X3/X2/XR1/a_n703_n3602#" 2.13515
cap "VCO_1/X3/X3/VDD" "vdda2" 2.1685
cap "VCO_1/X3/OUT90" "vdda2" 43.1673
cap "vdda2" "VCO_1/X3/X2/XR1/a_n703_n3602#" 2.72316
cap "vdda2" "VCO_1/X3/OUT90" 48.1931
cap "VCO_1/X3/X3/GND" "vdda2" 2.72316
cap "vdda2" "VCO_1/X3/OUT90" 48.1931
cap "VCO_1/X3/OUT90" "vdda2" 48.1931
cap "vdda2" "VCO_1/X3/X3/GND" 2.58008
cap "vdda2" "VCO_1/X3/X3/GND" 5.40628
cap "vdda2" "VCO_1/X3/X3/OUTA" 49.2186
cap "vdda2" "VCO_1/X3/X3/SUB" 0.666422
cap "vdda2" "VCO_1/X3/X3/OUTA" 21.7301
cap "vdda2" "VCO_1/X3/X3/SUB" 3.96413
cap "VCO_1/X3/X1/OUTA" "vdda2" 54.8082
cap "VCO_1/X3/X1/GND" "vdda2" 3.67818
cap "vdda2" "VCO_1/X3/OUT0" 48.1931
cap "VCO_1/X3/OUT0" "vdda2" 48.1931
cap "VCO_1/X3/X1/GND" "vdda2" 2.63806
cap "VCO_1/X3/OUT0" "vdda2" 48.1931
cap "vdda2" "VCO_1/X3/X4/XR1/a_n703_n3602#" 2.63806
cap "VCO_1/X3/X1/VDD" "vdda2" 0.719541
cap "VCO_1/X3/X4/XR1/a_n703_n3602#" "vdda2" 4.16462
cap "VCO_1/m1_48170_36500#" "vdda2" 26.7128
cap "VCO_1/output_buffer_0/INB" "VCO_1/output_buffer_0/OUTB" 0.201209
cap "VCO_1/X3/X1/VDD" "vdda2" 0.592765
cap "VCO_1/output_buffer_0/INA" "VCO_1/output_buffer_0/OUTB" 121.645
cap "VCO_1/output_buffer_0/BIAS" "VCO_1/output_buffer_0/OUTB" 4.45468
cap "VCO_1/X3/X4/XR1/a_n703_n3602#" "VCO_1/output_buffer_0/INA" -2.42801
cap "VCO_1/output_buffer_0/INA" "vdda2" 0.137695
cap "VCO_1/X3/X4/XR1/a_n703_n3602#" "VCO_1/output_buffer_0/OUTB" 93.9713
cap "vdda2" "VCO_1/output_buffer_0/OUTB" 112.291
cap "VCO_1/X3/X4/XR1/a_n703_n3602#" "vdda2" 1.68082
cap "VCO_1/X3/X1/VDD" "VCO_1/output_buffer_0/OUTB" 158.786
cap "VCO_1/output_buffer_0/OUTB" "VCO_1/output_buffer_0/XM4/a_n1665_n100#" 18.2546
cap "VCO_1/output_buffer_0/OUTB" "VCO_1/output_buffer_0/XM33/a_n945_n188#" 91.0093
cap "VCO_1/output_buffer_0/OUTB" "VCO_1/X3/X4/XR1/a_n703_n3602#" 82.6741
cap "VCO_1/output_buffer_0/OUTB" "VCO_1/output_buffer_0/INB" 1.00084
cap "VCO_1/output_buffer_0/OUTB" "VCO_1/output_buffer_0/INA" 7.22113
cap "VCO_1/output_buffer_0/OUTB" "VCO_1/output_buffer_0/BIAS" 13.8459
cap "VCO_1/output_buffer_0/OUTB" "VCO_1/output_buffer_0/XM4/a_n1569_n100#" 5.39819
cap "VCO_1/output_buffer_0/XM4/a_n1665_n100#" "VCO_1/output_buffer_0/OUTB" 10.4927
cap "VCO_1/output_buffer_0/SUB" "VCO_1/output_buffer_0/OUTB" 120.433
cap "VCO_1/output_buffer_0/XM33/a_n945_n188#" "VCO_1/output_buffer_0/OUTB" 69.9798
cap "VCO_1/output_buffer_0/OUTA" "VCO_1/output_buffer_0/OUTB" 851.785
cap "VCO_1/output_buffer_0/OUTA" "VCO_1/output_buffer_0/XM4/a_n1569_n100#" -8.96476e-06
cap "VCO_1/output_buffer_0/XM3/a_n1665_n100#" "VCO_1/output_buffer_0/OUTB" 29.0009
cap "VCO_1/output_buffer_0/XM32/a_n945_n188#" "VCO_1/output_buffer_0/OUTA" -0.000273142
cap "VCO_1/output_buffer_0/OUTB" "VCO_1/output_buffer_0/XM4/a_n1569_n100#" 1186.58
cap "VCO_1/output_buffer_0/XM32/a_n945_n188#" "VCO_1/output_buffer_0/OUTB" 146.057
cap "VCO_1/output_buffer_0/BIAS" "VCO_1/output_buffer_0/OUTB" 18.6867
cap "VCO_1/output_buffer_0/INA" "VCO_1/output_buffer_0/OUTB" 4.62929
cap "VCO_1/output_buffer_0/OUTB" "VCO_1/output_buffer_0/INB" 0.230178
cap "VCO_1/output_buffer_0/OUTA" "txinb" 244.786
cap "VCO_1/output_buffer_0/SUB" "txinb" 75.3721
cap "VCO_1/output_buffer_0/OUTA" "txinb" -2.84217e-14
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1031.64
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 676.224
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "vdda2" "VCO_1/X3/X3/GND" 0.0201457
cap "vdda2" "VCO_1/X3/X3/XM4/a_n417_n100#" 0.000558876
cap "VCO_1/X3/X3/SUB" "vdda2" 11.1514
cap "VCO_1/X3/X3/SUB" "vdda2" 0.0447289
cap "vdda2" "VCO_1/X3/X3/GND" 1.84248
cap "vdda2" "VCO_1/X3/X3/BIAS" 59.6129
cap "vdda2" "VCO_1/X3/X3/BIAS" 0.0166433
cap "vdda2" "VCO_1/X3/X3/XM4/a_n417_n100#" 7.35646
cap "VCO_1/X3/I2A" "vdda2" 1.17041
cap "VCO_1/X3/X3/INB" "vdda2" 7.93516
cap "VCO_1/X3/I4B" "vdda2" 0.514982
cap "vdda2" "VCO_1/X3/X3/INA" 0.00145749
cap "vdda2" "VCO_1/X3/X3/OUTA" 2.42562
cap "VCO_1/X3/X3/SUB" "vdda2" 1.41154
cap "VCO_1/X3/X3/XM4/a_n417_n100#" "vdda2" 0.00139192
cap "VCO_1/X3/X1/INA" "vdda2" 1.88769
cap "VCO_1/X3/I4A" "vdda2" 1.17041
cap "VCO_1/X3/X1/INB" "vdda2" 6.19955
cap "vdda2" "VCO_1/X3/I2B" 3.47374
cap "VCO_1/X3/X3/OUTB" "vdda2" 0.546215
cap "VCO_1/X3/X3/SUB" "vdda2" 0.0108821
cap "vdda2" "VCO_1/X3/X3/INA" 4.85488
cap "VCO_1/X3/X1/INA" "vdda2" 0.00179818
cap "VCO_1/X3/X3/XM4/a_n417_n100#" "vdda2" 2.11992
cap "VCO_1/X3/X3/SUB" "vdda2" 0.0396945
cap "vdda2" "VCO_1/X3/X1/BIAS" 0.0104073
cap "vdda2" "VCO_1/X3/X1/GND" 1.22283
cap "vdda2" "VCO_1/X3/X1/XM3/a_n73_n100#" 8.14841
cap "vdda2" "VCO_1/X3/X1/INA" 0.956401
cap "VCO_1/X3/X3/SUB" "vdda2" 7.92407
cap "vdda2" "VCO_1/X3/X1/XM3/a_n73_n100#" 0.00195079
cap "vdda2" "VCO_1/X3/X1/OUTB" 0.546215
cap "vdda2" "VCO_1/X3/X1/BIAS" 36.7584
cap "vdda2" "VCO_1/X3/I4B" 0.655432
cap "vdda2" "VCO_1/X3/X1/INB" 3.31601
cap "vdda2" "VCO_1/X3/X1/OUTA" 2.09213
cap "vdda2" "VCO_1/X3/X1/INA" 0.00096002
cap "VCO_1/X3/X1/GND" "vdda2" 1.63288
cap "vdda2" "VCO_1/X3/X1/SUB" 4.01626
cap "VCO_1/X3/X1/BIAS" "vdda2" 0.00623599
cap "vdda2" "VCO_1/X3/X1/SUB" 0.0159165
cap "vdda2" "VCO_1/X3/X1/XM3/a_n73_n100#" 1.32797
cap "VCO_1/X3/X1/BIAS" "vdda2" 22.0096
cap "VCO_1/output_buffer_0/OUTB" "VCO_1/X3/X1/VDD" 22.8054
cap "VCO_1/output_buffer_0/OUTB" "VCO_1/output_buffer_0/INA" 31.9636
cap "VCO_1/output_buffer_0/OUTB" "VCO_1/output_buffer_0/INB" 0.193392
cap "VCO_1/output_buffer_0/OUTB" "vdda2" 19.8452
cap "VCO_1/output_buffer_0/OUTB" "VCO_1/X3/X4/XR1/a_n703_n3602#" 10.4038
cap "VCO_1/output_buffer_0/INA" "VCO_1/X3/X4/XR1/a_n703_n3602#" -1.19298
cap "vdda2" "VCO_1/X3/X4/XR1/a_n703_n3602#" -0.0230982
cap "VCO_1/output_buffer_0/XM32/a_831_n100#" "VCO_1/output_buffer_0/XR2/a_n285_760#" 0.0647723
cap "VCO_1/X3/X4/XR1/a_n703_n3602#" "VCO_1/output_buffer_0/XM32/a_831_n100#" 0.0315232
cap "VCO_1/output_buffer_0/XM33/a_927_n100#" "VCO_1/output_buffer_0/OUTB" 7.23189
cap "VCO_1/output_buffer_0/XR2/a_n285_760#" "VCO_1/output_buffer_0/OUTB" 31.5002
cap "VCO_1/output_buffer_0/INB" "VCO_1/output_buffer_0/OUTB" 0.616332
cap "VCO_1/X3/X4/XR1/a_n703_n3602#" "VCO_1/output_buffer_0/OUTB" 17.8685
cap "VCO_1/output_buffer_0/XM32/a_n945_n188#" "VCO_1/output_buffer_0/OUTB" 0.439937
cap "VCO_1/output_buffer_0/INA" "VCO_1/output_buffer_0/OUTB" 3.96609
cap "VCO_1/output_buffer_0/OUTA" "VCO_1/output_buffer_0/SUB" 6.64781
cap "VCO_1/output_buffer_0/OUTA" "VCO_1/output_buffer_0/OUTB" 19.7296
cap "VCO_1/output_buffer_0/XM32/a_n945_n188#" "VCO_1/output_buffer_0/OUTB" 8.11343
cap "VCO_1/output_buffer_0/OUTA" "VCO_1/output_buffer_0/XM32/a_n945_n188#" 8.85384
cap "VCO_1/output_buffer_0/XR2/a_n285_760#" "VCO_1/output_buffer_0/XM33/a_927_n100#" -0.285707
cap "VCO_1/output_buffer_0/SUB" "VCO_1/output_buffer_0/XM33/a_927_n100#" -1.05739
cap "VCO_1/output_buffer_0/XR2/a_n285_760#" "VCO_1/output_buffer_0/OUTB" 1.53161
cap "VCO_1/output_buffer_0/INA" "VCO_1/output_buffer_0/OUTB" 0.700038
cap "VCO_1/output_buffer_0/XM33/a_927_n100#" "VCO_1/output_buffer_0/OUTB" 14.1435
cap "VCO_1/output_buffer_0/SUB" "VCO_1/output_buffer_0/OUTB" 6.30101
cap "VCO_1/output_buffer_0/XR2/a_n285_760#" "VCO_1/output_buffer_0/OUTA" 0.939923
cap "VCO_1/output_buffer_0/OUTA" "VCO_1/output_buffer_0/XM33/a_927_n100#" 7.88214
cap "VCO_1/output_buffer_0/XM32/a_n945_n188#" "VCO_1/output_buffer_0/XM33/a_927_n100#" -0.222993
cap "VCO_1/output_buffer_0/OUTA" "VCO_1/output_buffer_0/XM32/a_n945_n188#" 8.63219
cap "VCO_1/output_buffer_0/OUTA" "VCO_1/output_buffer_0/SUB" 42.1174
cap "txinb" "VCO_1/output_buffer_0/SUB" 1.95639
cap "VCO_1/output_buffer_0/OUTA" "txinb" 105.786
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1031.64
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 676.224
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.822
cap "VCO_1/X3/X3/XR2/a_n703_n3602#" "vdda2" 96.3368
cap "VCO_1/X3/OUT270" "vdda2" 367.851
cap "VCO_1/X3/VDD" "vdda2" 528.657
cap "vdda2" "VCO_1/X3/GND" 230.453
cap "vdda2" "VCO_1/X3/X3/XR2/a_n703_n3602#" 52.9947
cap "VCO_1/X3/OUT270" "vdda2" 234.429
cap "VCO_1/X3/X3/GND" "vdda2" 366.39
cap "vdda2" "VCO_1/X3/OUT270" 356.222
cap "VCO_1/X3/X3/XR2/a_n703_n3602#" "vdda2" 43.8604
cap "vdda2" "VCO_1/X3/OUT270" 343.073
cap "VCO_1/X3/X3/GND" "vdda2" 446.65
cap "VCO_1/X3/X3/XR2/a_n703_n3602#" "vdda2" 40.7989
cap "vdda2" "VCO_1/X3/X3/XM4/a_n417_n100#" 132.233
cap "VCO_1/X3/X3/BIAS" "vdda2" 145.465
cap "vdda2" "VCO_1/X3/X5/IN4" 638.593
cap "vdda2" "VCO_1/X3/X3/SUB" 107.864
cap "VCO_1/X3/X3/GND" "vdda2" 224.292
cap "vdda2" "VCO_1/X3/X3/INA" 16.3564
cap "VCO_1/X3/m3_19820_13570#" "vdda2" 334.467
cap "vdda2" "VCO_1/X3/X5/IN3" 117.733
cap "vdda2" "VCO_1/X3/X3/XM4/a_n417_n100#" 29.8079
cap "vdda2" "VCO_1/X3/I4A" 8.88233
cap "VCO_1/X3/I2A" "vdda2" 6.86362
cap "VCO_1/X3/X3/INB" "vdda2" 25.065
cap "vdda2" "VCO_1/X3/X5/SUB" 59.8067
cap "vdda2" "VCO_1/X3/X1/INA" 8.20658
cap "vdda2" "VCO_1/X3/X5/IN2" 103.24
cap "vdda2" "VCO_1/X3/I4B" 2.6647
cap "VCO_1/X3/X1/INB" "vdda2" 15.6524
cap "vdda2" "VCO_1/X3/X5/IN4" 409.673
cap "VCO_1/X3/I2B" "vdda2" 9.39963
cap "VCO_1/X3/X1/BIAS" "vdda2" 39.8669
cap "vdda2" "VCO_1/X3/X1/INA" 4.57265
cap "VCO_1/X3/X1/GND" "vdda2" 133.123
cap "VCO_1/X3/X5/IN1" "vdda2" 927.232
cap "VCO_1/X3/I4B" "vdda2" 5.06318
cap "VCO_1/X3/X1/INB" "vdda2" 11.6403
cap "VCO_1/X3/X1/XM3/a_n73_n100#" "vdda2" 121.356
cap "vdda2" "VCO_1/X3/SUB" 126.258
cap "VCO_1/X3/X5/IN2" "vdda2" 12.5799
cap "VCO_1/X3/X1/BIAS" "vdda2" 120.739
cap "VCO_1/X3/OUT180" "vdda2" 303.751
cap "VCO_1/X3/SUB" "vdda2" 70.1409
cap "vdda2" "VCO_1/m1_46335_31170#" 9.82122
cap "VCO_1/X3/X1/XM3/a_n73_n100#" "vdda2" 40.6852
cap "VCO_1/X3/X1/GND" "vdda2" 500.302
cap "VCO_1/X3/SUB" "vdda2" 56.6773
cap "VCO_1/X3/OUT180" "vdda2" 361.177
cap "VCO_1/X3/OUT180" "VCO_1/X3/X1/VDD" 361.177
cap "VCO_1/X3/X1/VDD" "VCO_1/X3/SUB" 56.6773
cap "VCO_1/X3/X1/VDD" "VCO_1/m1_47700_36500#" 118.97
cap "VCO_1/X3/X1/XR2/a_n703_n3602#" "VCO_1/X3/X1/VDD" 34.9917
cap "VCO_1/output_buffer_0/VDD" "VCO_1/output_buffer_0/BIAS" 0.0670467
cap "VCO_1/output_buffer_0/INB" "VCO_1/output_buffer_0/OUTB" 1.90141
cap "VCO_1/output_buffer_0/INB" "VCO_1/output_buffer_0/VDD" 3.15157
cap "VCO_1/output_buffer_0/VDD" "VCO_1/X3/X1/XR2/a_n703_n3602#" 3.02293
cap "VCO_1/output_buffer_0/VDD" "VCO_1/X3/X1/XR2/a_n703_n3602#" 0.0143918
cap "VCO_1/output_buffer_0/OUTB" "VCO_1/X3/X1/XR2/a_n703_n3602#" 1.30705
cap "VCO_1/output_buffer_0/INB" "VCO_1/output_buffer_0/OUTB" 3.36479
cap "VCO_1/output_buffer_0/XR2/a_n285_760#" "VCO_1/output_buffer_0/OUTB" 3.82427
cap "VCO_1/output_buffer_0/XM43/a_159_n100#" "VCO_1/output_buffer_0/OUTA" -3.81182e-06
cap "VCO_1/output_buffer_0/SUB" "VCO_1/output_buffer_0/OUTA" 0.177691
cap "VCO_1/output_buffer_0/OUTA" "VCO_1/output_buffer_0/XM32/a_n945_n188#" 0.797919
cap "VCO_1/output_buffer_0/XM43/a_159_n100#" "VCO_1/output_buffer_0/OUTB" -3.21938e-05
cap "VCO_1/output_buffer_0/SUB" "VCO_1/output_buffer_0/OUTB" -0.000244946
cap "VCO_1/output_buffer_0/INA" "VCO_1/output_buffer_0/OUTA" -6.72076e-05
cap "VCO_1/output_buffer_0/XR2/a_n285_760#" "VCO_1/output_buffer_0/OUTB" -1.85508e-05
cap "VCO_1/output_buffer_0/INB" "VCO_1/output_buffer_0/OUTB" 0.0392166
cap "VCO_1/output_buffer_0/XM32/a_n945_n188#" "VCO_1/output_buffer_0/OUTA" 3.71867
cap "VCO_1/output_buffer_0/OUTA" "VCO_1/output_buffer_0/SUB" 0.998737
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1031.64
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 676.224
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.821
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 7.13678
cap "VCO_1/X3/VDD" "vdda2" 7.04633
cap "vdda2" "VCO_1/X3/X3/XR1/a_n703_n3602#" 22.6544
cap "vdda2" "VCO_1/X3/X3/XR1/a_n703_n3602#" 32.3911
cap "VCO_1/X3/VDD" "vdda2" 31.603
cap "VCO_1/X3/X3/XR1/a_n703_n3602#" "vdda2" 25.3296
cap "VCO_1/X3/X6/VOP" "vdda2" 0.305891
cap "VCO_1/X3/X6/XM41/a_n465_122#" "vdda2" 0.569568
cap "VCO_1/X3/X6/XM41/a_n561_n188#" "vdda2" 0.16173
cap "VCO_1/X3/X6/IN" "vdda2" 81.2731
cap "VCO_1/X3/VDD" "vdda2" 33.1297
cap "VCO_1/X3/BIAS" "vdda2" 30.9741
cap "vdda2" "VCO_1/X3/X6/XM41/a_n561_n188#" 1.08699
cap "vdda2" "VCO_1/X3/X3/XM1/a_n369_122#" 33.856
cap "vdda2" "VCO_1/X3/X3/XR1/a_n703_n3602#" 26.1389
cap "vdda2" "VCO_1/X3/X6/VOP" 22.7591
cap "vdda2" "VCO_1/X3/X6/XM41/a_n465_122#" 0.0140717
cap "VCO_1/X3/X6/IN" "vdda2" 127.162
cap "vdda2" "VCO_1/X3/X6/VDD" 0.672025
cap "vdda2" "VCO_1/X3/X3/XR1/a_n703_n3602#" 34.3401
cap "vdda2" "VCO_1/X3/X5/IN4" 4.084
cap "vdda2" "VCO_1/X3/X5/XM26/a_63_n100#" 0.647456
cap "VCO_1/X3/X6/VOP" "vdda2" 16.4577
cap "vdda2" "VCO_1/X3/X5/XM26/a_159_n100#" 6.9986
cap "VCO_1/X3/m3_19820_13570#" "vdda2" 127.162
cap "vdda2" "VCO_1/X3/X3/XM1/a_n369_122#" 1.32469
cap "vdda2" "VCO_1/X3/X5/XM26/a_159_n100#" 33.2185
cap "vdda2" "VCO_1/X3/X5/IN3" 13.201
cap "VCO_1/X3/X5/SUB" "vdda2" 19.5735
cap "vdda2" "VCO_1/X3/X5/XM26/a_63_n100#" 1.78269
cap "VCO_1/X3/m3_19820_13570#" "vdda2" 87.0197
cap "vdda2" "VCO_1/X3/X5/IN2" 1.6769
cap "VCO_1/X3/X5/IN4" "vdda2" 1.67721
cap "VCO_1/X3/X5/IN1" "vdda2" 12.956
cap "vdda2" "VCO_1/X3/SUB" 32.2422
cap "VCO_1/X3/X5/VDD" "vdda2" 1.83614
cap "VCO_1/X3/X5/XM26/a_n33_n100#" "vdda2" 30.8061
cap "VCO_1/X3/X5/IN2" "vdda2" 5.99709
cap "VCO_1/X3/X5/XM27/a_159_n100#" "vdda2" 71.6568
cap "VCO_1/X3/X5/VDD" "vdda2" 0.944703
cap "vdda2" "VCO_1/X3/SUB" 35.053
cap "VCO_1/X3/X1/XM1/a_399_122#" "vdda2" 1.46511
cap "vdda2" "VCO_1/X3/X5/VDD" 4.18219
cap "vdda2" "VCO_1/X3/SUB" 35.8624
cap "vdda2" "VCO_1/X3/X1/XM1/a_15_122#" 58.339
cap "VCO_1/X3/SUB" "VCO_1/X3/X1/XR1/a_n573_3040#" 35.8624
cap "VCO_1/X3/X1/XR1/a_n573_3040#" "VCO_1/X3/BIAS" 58.339
cap "VCO_1/X3/X1/XR1/a_n703_n3602#" "VCO_1/X3/X1/XR1/a_n573_3040#" 23.3775
cap "VCO_1/m1_46210_32690#" "VCO_1/X3/X1/XR1/a_n573_3040#" 3.17022
cap "VCO_1/output_buffer_0/VDD" "VCO_1/X3/X1/XR1/a_n703_n3602#" 2.60349
cap "VCO_1/output_buffer_0/VDD" "VCO_1/output_buffer_0/BIAS" 4.18319
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1031.64
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1692.46
cap "VGA_routing_0/m1_443471_412049#" "TX_line_0/OUTB" 676.224
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 336.63
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 24.9326
cap "VCO_1/X3/VDD" "vdda2" 0.00533057
cap "VCO_1/X3/X6/XM41/a_n561_n188#" "vdda2" 0.000530037
cap "VCO_1/X3/X6/XM41/a_n465_122#" "vdda2" 0.000884808
cap "VCO_1/X3/X6/VOP" "vdda2" 0.00317458
cap "VCO_1/X3/X6/VOP" "vdda2" 0.00188352
cap "VCO_1/X3/X6/XM41/a_n465_122#" "vdda2" 5.56964e-05
cap "VCO_1/X3/X6/XM41/a_n561_n188#" "vdda2" 0.00567532
cap "VCO_1/X3/X6/VDD" "vdda2" 0.00326114
cap "VGA_routing_0/m1_443471_412049#" "TX_line_0/OUTB" 1031.64
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 676.224
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1031.64
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 676.224
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1031.64
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 676.224
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "VGA_routing_0/m4_419918_417788#" "TX_line_0/OUTB" 333.05
cap "VCO_1/X3/X6/XC2/m3_n2150_n3100#" "vdda2" 461.906
cap "VCO_1/X3/X6/XC2/c1_n2050_n3000#" "vdda2" 1337.21
cap "VCO_1/X3/X6/XC2/c1_n2050_n3000#" "vdda2" 2014.67
cap "VCO_1/X3/BIAS" "vdda2" 5.43154
cap "vdda2" "VCO_1/X3/X6/XC2/c1_n2050_n3000#" 2014.67
cap "vdda2" "VCO_1/X3/X6/XC2/m3_n2150_n3100#" 155.996
cap "vdda2" "VCO_1/X3/X6/XR21/a_n415_n4762#" 46.3858
cap "vdda2" "VCO_1/X3/X6/XC2/c1_n2050_n3000#" 437.339
cap "VCO_1/X3/VOP" "vdda2" 130.57
cap "VCO_1/X3/X5/XC1/m3_n2150_n3100#" "vdda2" 459.172
cap "VCO_1/X3/X5/XC1/c1_n2050_n3000#" "vdda2" 1150.13
cap "vdda2" "VCO_1/X3/X5/XC1/c1_n2050_n3000#" 2014.67
cap "VCO_1/X3/X5/XC1/c1_n2050_n3000#" "vdda2" 2014.67
cap "VCO_1/X3/X5/XC1/m3_n2150_n3100#" "vdda2" 134.108
cap "VCO_1/GND" "vdda2" 134.547
cap "VCO_1/X3/X5/XR18/a_n415_n4762#" "vdda2" 43.1875
cap "VCO_1/X3/X5/XC1/c1_n2050_n3000#" "vdda2" 624.461
cap "vdda2" "VCO_1/GND" 312.991
cap "VCO_1/X3/BIAS" "vdda2" 82.789
cap "VCO_1/VDD" "vdda2" 29.9143
cap "vdda2" "VCO_1/VDD" 0.184843
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1031.64
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 676.224
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "vdda2" "VCO_1/X3/X6/XC2/m3_n2150_n3100#" 461.906
cap "vdda2" "VCO_1/X3/X6/XC2/c1_n2050_n3000#" 1337.21
cap "vdda2" "VCO_1/X3/X6/XC2/c1_n2050_n3000#" 2014.67
cap "vdda2" "VCO_1/X3/X6/XC2/c1_n2050_n3000#" 2014.67
cap "vdda2" "VCO_1/X3/BIAS" 5.43154
cap "VCO_1/X3/X6/GND" "vdda2" 202.382
cap "vdda2" "VCO_1/X3/X6/XC2/c1_n2050_n3000#" 437.339
cap "vdda2" "VCO_1/X3/X5/XC1/c1_n2050_n3000#" 1150.13
cap "VCO_1/X3/X6/GND" "vdda2" 459.172
cap "VCO_1/X3/VOP" "vdda2" 130.57
cap "VCO_1/X3/X5/XC1/c1_n2050_n3000#" "vdda2" 2014.67
cap "VCO_1/X3/X5/XC1/c1_n2050_n3000#" "vdda2" 2014.67
cap "VCO_1/X3/X5/XR18/a_n415_n4762#" "vdda2" 43.1875
cap "VCO_1/GND" "vdda2" 134.547
cap "VCO_1/X3/X5/XC1/c1_n2050_n3000#" "vdda2" 624.461
cap "VCO_1/X3/X5/XC1/m3_n2150_n3100#" "vdda2" 134.108
cap "VCO_1/X3/BIAS" "vdda2" 82.789
cap "vdda2" "VCO_1/GND" 312.991
cap "VCO_1/VDD" "vdda2" 29.9143
cap "VCO_1/VDD" "vdda2" 0.184843
cap "VGA_routing_0/m1_443471_412049#" "TX_line_0/OUTB" 1031.64
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 676.224
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1031.64
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1692.46
cap "VGA_routing_0/m1_443471_412049#" "TX_line_0/OUTB" 676.224
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "VCO_1/X3/X6/XC2/c1_n2050_n3000#" "VCO_1/X3/X6/XC2/m3_n2150_n3100#" -25.1111
cap "vssa2" "VCO_1/X3/X6/XC2/c1_n2050_n3000#" 152.396
cap "vssa2" "VCO_1/X3/X6/XC2/m3_n2150_n3100#" 324.528
cap "VCO_1/GND" "VCO_1/X3/X6/XC2/c1_n2050_n3000#" 176.734
cap "VCO_1/X3/X6/XC2/c1_n2050_n3000#" "VCO_1/X3/X6/GND" 1.57113
cap "VCO_1/X3/X6/GND" "VCO_1/bias_calc_0/BIASOUT" 0.85522
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1031.64
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 676.224
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 474.147
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "VCO_1/bias_calc_0/GND" "VCO_1/bias_calc_0/BIASOUT" 1.58827
cap "VCO_1/bias_calc_0/BIAS2V" "VCO_1/bias_calc_0/VDD" 11.9387
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1031.64
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 676.224
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "VGA_routing_0/m4_419918_417788#" "TX_line_0/OUTB" 333.05
cap "VCO_1/bias_calc_0/PSUB" "VCO_1/bias_calc_0/VCTRL" 0.230014
cap "VCO_1/bias_calc_0/BIAS2V" "VCO_1/bias_calc_0/VDD" 2.17026
cap "VCO_1/bias_calc_0/BIAS2V" "VCO_1/bias_calc_0/XM38/a_n1821_n100#" 1.69336
cap "VCO_1/bias_calc_0/XM2/a_547_n100#" "VCO_1/bias_calc_0/BIAS2V" 2.57001
cap "VCO_1/bias_calc_0/VDD" "VCO_1/bias_calc_0/BIAS2V" 159.548
cap "VCO_1/bias_calc_0/XM3/a_547_n100#" "VCO_1/bias_calc_0/BIAS2V" 18.4054
cap "VCO_1/bias_calc_0/VDD" "VCO_1/bias_calc_0/XM3/a_547_n100#" -10.595
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1031.64
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1692.46
cap "VGA_routing_0/m1_443471_412049#" "TX_line_0/OUTB" 676.224
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "VCO_1/bias_calc_0/XM40/a_n369_122#" "VCTRL" 20.863
cap "VCO_1/bias_calc_0/GND" "VCO_1/bias_calc_0/XM40/a_n369_122#" -0.786884
cap "VCO_1/bias_calc_0/GND" "VCTRL" 46.5663
cap "VCO_1/bias_calc_0/XM37/a_1821_n197#" "VCO_1/bias_calc_0/w_17930_210#" -2.96979
cap "VCTRL" "VCO_1/bias_calc_0/XM38/a_1763_n100#" 0.349568
cap "VCO_1/bias_calc_0/XM37/a_1821_n197#" "VCTRL" 20.2951
cap "VCO_1/bias_calc_0/XM40/a_n369_122#" "VCO_1/bias_calc_0/XM37/a_1821_n197#" -6.89269
cap "VCTRL" "VCO_1/bias_calc_0/w_17930_210#" 11.9789
cap "VCO_1/bias_calc_0/XM40/a_n369_122#" "VCO_1/bias_calc_0/w_17930_210#" 4.75858
cap "VCO_1/bias_calc_0/XM40/a_n369_122#" "VCTRL" 52.4881
cap "VCO_1/bias_calc_0/XM38/w_n2087_n319#" "VCO_1/bias_calc_0/VCTRL" 10.3412
cap "VCO_1/bias_calc_0/XM40/a_n465_n188#" "VCO_1/bias_calc_0/VCTRL" 39.0825
cap "VCO_1/bias_calc_0/VCTRL" "VCO_1/bias_calc_0/XM38/a_1763_n100#" 0.502269
cap "VCO_1/bias_calc_0/VCTRL" "VCO_1/bias_calc_0/XM38/a_995_n100#" 0.510473
cap "VCO_1/bias_calc_0/VCTRL" "VCO_1/bias_calc_0/XM38/w_n2087_n319#" 10.3412
cap "VCO_1/bias_calc_0/VCTRL" "VCO_1/bias_calc_0/XM37/a_867_n100#" 39.0743
cap "VCO_1/bias_calc_0/VCTRL" "VCO_1/bias_calc_0/XM37/a_n413_n100#" 1.58187
cap "VCO_1/bias_calc_0/VCTRL" "VCO_1/bias_calc_0/XM38/a_n541_n100#" 2.37169
cap "VCO_1/bias_calc_0/PSUB" "VCO_1/bias_calc_0/VCTRL" 11.8438
cap "VCO_1/bias_calc_0/VDD" "VCO_1/bias_calc_0/BIAS2V" 3.29639
cap "VCO_1/bias_calc_0/XM38/a_n1821_n100#" "VCO_1/bias_calc_0/BIAS2V" 2.58597
cap "VCO_1/bias_calc_0/BIAS2V" "VCO_1/bias_calc_0/XM36/a_547_n100#" 22.5913
cap "VCO_1/bias_calc_0/VDD" "VCO_1/bias_calc_0/BIAS2V" 147.575
cap "VCO_1/bias_calc_0/XM2/a_547_n100#" "VCO_1/bias_calc_0/BIAS2V" 18.19
cap "VCO_1/bias_calc_0/VDD" "VCO_1/bias_calc_0/XM36/a_547_n100#" -6.02622
cap "VCO_1/bias_calc_0/XM2/a_547_n100#" "VCO_1/bias_calc_0/VDD" -10.6179
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1031.64
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 676.224
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 722.75
cap "VGA_routing_0/m4_419918_417788#" "TX_line_0/OUTB" 333.05
cap "VCO_1/bias_calc_0/XM39/a_303_n188#" "VCTRL" 11.891
cap "VCTRL" "VCO_1/bias_calc_0/XM39/a_n611_n274#" 21.5152
cap "VCO_1/bias_calc_0/XM39/a_399_122#" "VCTRL" 58.3604
cap "VCO_1/bias_calc_0/XM39/a_447_n100#" "VCTRL" 90.8848
cap "VCO_1/bias_calc_0/XM37/a_1763_n100#" "VCTRL" 5.94374
cap "VCO_1/bias_calc_0/w_17930_210#" "VCTRL" 32.7433
cap "VCO_1/bias_calc_0/XM39/a_303_n188#" "VCTRL" 109.347
cap "VCO_1/bias_calc_0/XM37/a_1821_n197#" "VCTRL" 28.6282
cap "VCO_1/bias_calc_0/XM39/a_399_122#" "VCO_1/bias_calc_0/VCTRL" 93.2954
cap "VCO_1/bias_calc_0/XM37/a_1763_n100#" "VCO_1/bias_calc_0/VCTRL" 8.12409
cap "VCO_1/bias_calc_0/VCTRL" "VCO_1/bias_calc_0/w_17930_210#" 35.3122
cap "VCO_1/bias_calc_0/w_17930_210#" "VCO_1/bias_calc_0/VCTRL" 35.3122
cap "VCO_1/bias_calc_0/VCTRL" "VCO_1/bias_calc_0/XM37/a_995_n100#" 8.29732
cap "VCO_1/bias_calc_0/XM37/a_867_n100#" "VCO_1/bias_calc_0/VCTRL" 93.1222
cap "VCO_1/bias_calc_0/VCTRL" "VCO_1/bias_calc_0/w_17930_210#" 2.84426
cap "VCO_1/bias_calc_0/VCTRL" "VCO_1/bias_calc_0/XM37/a_n541_n100#" 0.285229
cap "VCO_1/bias_calc_0/VCTRL" "VCO_1/bias_calc_0/XM37/a_n413_n100#" 4.1738
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1031.64
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 676.224
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1031.64
cap "VGA_routing_0/m1_443471_412049#" "TX_line_0/OUTB" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 676.224
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1031.64
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 676.224
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1031.64
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 676.224
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "VGA_routing_0/m1_443471_412049#" "TX_line_0/OUTB" 1031.64
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 676.224
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "VGA_routing_0/m4_419918_417788#" "TX_line_0/OUTB" 333.05
cap "VGA_routing_0/m1_443471_412049#" "TX_line_0/OUTB" 1031.64
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 676.224
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1031.64
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1692.46
cap "VGA_routing_0/m1_443471_412049#" "TX_line_0/OUTB" 676.224
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "VGA_routing_0/m1_443471_412049#" "TX_line_0/OUTB" 1031.64
cap "VGA_routing_0/m1_443471_412049#" "TX_line_0/OUTB" 1692.46
cap "VGA_routing_0/m1_443471_412049#" "TX_line_0/OUTB" 676.224
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "VGA_routing_0/m4_419918_417788#" "TX_line_0/OUTB" 333.05
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1031.64
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 676.224
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1031.64
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 676.224
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 474.147
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1031.64
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 676.224
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 474.147
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "VGA_routing_0/m4_419918_417788#" "TX_line_0/OUTB" 333.05
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1031.64
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 676.224
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "VGA_routing_0/m1_443471_412049#" "TX_line_0/OUTB" 1031.64
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 676.224
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "VGA_routing_0/m1_443471_412049#" "TX_line_0/OUTB" 1031.64
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 676.224
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1031.64
cap "VGA_routing_0/m1_443471_412049#" "TX_line_0/OUTB" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 676.224
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1031.64
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 676.224
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1031.64
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 676.224
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1031.64
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 676.224
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "VGA_routing_0/m4_419918_417788#" "TX_line_0/OUTB" 333.05
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1031.64
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 676.224
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "VGA_routing_0/m1_443471_412049#" "TX_line_0/OUTB" 1031.64
cap "VGA_routing_0/m1_443471_412049#" "TX_line_0/OUTB" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 676.224
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1031.64
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 676.224
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "VGA_routing_0/m1_443471_412049#" "TX_line_0/OUTB" 1031.64
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 676.224
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "VGA_routing_0/m4_419918_417788#" "TX_line_0/OUTB" 333.05
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1031.64
cap "TX_line_0/OUTB" "TX_line_0/OUTA" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 676.224
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "VGA_routing_0/m4_419918_417788#" "TX_line_0/OUTB" 333.05
cap "TX_line_0/OUTB" "txina" 1071.57
cap "TX_line_0/OUTB" "txina" 1350.79
cap "txina" "TX_line_0/OUTB" 1350.79
cap "txina" "TX_line_0/OUTB" 1350.79
cap "TX_line_0/OUTB" "txina" 1350.79
cap "TX_line_0/OUTB" "txina" 1350.79
cap "txina" "TX_line_0/OUTB" 1350.79
cap "TX_line_0/OUTB" "txina" 1350.79
cap "TX_line_0/OUTB" "txina" 1350.79
cap "TX_line_0/OUTB" "txina" 1350.79
cap "TX_line_0/OUTB" "txina" 1350.79
cap "TX_line_0/OUTB" "txina" 1350.79
cap "TX_line_0/OUTB" "txina" 1350.79
cap "TX_line_0/OUTB" "txina" 1350.79
cap "txina" "TX_line_0/OUTB" 1350.79
cap "txina" "TX_line_0/OUTB" 1350.79
cap "TX_line_0/OUTB" "txina" 1383.27
cap "TX_line_0/OUTB" "txina" 982.31
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 911.636
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1413.69
cap "TX_line_0/OUTB" "TX_line_0/OUTA" 1692.46
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 676.224
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "txina" "TX_line_0/OUTB" 1470.33
cap "TX_line_0/OUTB" "txina" 1834.35
cap "TX_line_0/OUTB" "txina" 1834.35
cap "TX_line_0/OUTB" "txina" 1834.35
cap "TX_line_0/OUTB" "txina" 1834.35
cap "txina" "TX_line_0/OUTB" 1834.35
cap "TX_line_0/OUTB" "txina" 1834.35
cap "TX_line_0/OUTB" "txina" 1834.35
cap "txina" "TX_line_0/OUTB" 1834.35
cap "TX_line_0/OUTB" "txina" 1834.35
cap "txina" "TX_line_0/OUTB" 1834.35
cap "TX_line_0/OUTB" "txina" 1834.35
cap "TX_line_0/OUTB" "txina" 1834.35
cap "TX_line_0/OUTB" "txina" 1834.35
cap "TX_line_0/OUTB" "txina" 1834.35
cap "TX_line_0/OUTB" "txina" 1834.35
cap "TX_line_0/OUTB" "txina" 1734.11
cap "txina" "TX_line_0/OUTB" 1327.41
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1169.75
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 1520.7
cap "TX_line_0/OUTB" "TX_line_0/OUTA" 1859.74
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443471_412049#" 656.084
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 722.75
cap "VGA_routing_0/m4_419918_417788#" "TX_line_0/OUTB" 333.05
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "VGA_routing_0/m4_419918_417788#" "TX_line_0/OUTB" 333.05
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "VGA_routing_0/m4_419918_417788#" "TX_line_0/OUTB" 333.05
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "VGA_routing_0/m4_419918_417788#" "TX_line_0/OUTB" 333.05
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 333.05
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 474.147
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 736.47
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 722.75
cap "VGA_routing_0/m4_419918_417788#" "TX_line_0/OUTB" 333.05
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 95.2387
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 220.15
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 220.15
cap "TX_line_0/OUTB" "VGA_routing_0/m1_443140_352045#" 220.15
cap "VGA_routing_0/m1_443140_352045#" "TX_line_0/OUTB" 170.654
cap "TX_line_0/OUTB" "VGA_routing_0/m4_419918_417788#" 47.5786
cap "VGA_routing_0/m1_443140_352045#" "vssa2" 784.454
cap "VGA_routing_0/m1_443140_352045#" "vssa2" 2492.98
cap "vssa2" "VGA_routing_0/m1_443140_352045#" 2492.98
cap "vssa2" "VGA_routing_0/m1_443140_352045#" 2492.98
cap "vssa2" "VGA_routing_0/m1_443140_352045#" 1649.83
cap "vssa2" "VGA_routing_0/m4_419918_417788#" 903.714
cap "vssa2" "VGA_routing_0/m4_419918_417788#" 2492.98
cap "vssa2" "VGA_routing_0/m4_419918_417788#" 2492.98
cap "VGA_routing_0/m4_419918_417788#" "vssa2" 2492.98
cap "VGA_routing_0/m4_419918_417788#" "vssa2" 981.592
cap "vssa2" "VGA_routing_0/m1_443140_352045#" 1130.03
cap "vssa2" "VGA_routing_0/m1_443140_352045#" 3348.17
cap "VGA_routing_0/m1_443140_352045#" "vssa2" 3348.17
cap "vssa2" "VGA_routing_0/m1_443140_352045#" 3348.17
cap "VGA_routing_0/m1_443140_352045#" "vssa2" 2292.24
cap "VGA_routing_0/m4_419918_417788#" "vssa2" 1290.18
cap "vssa2" "VGA_routing_0/m4_419918_417788#" 3348.17
cap "VGA_routing_0/m4_419918_417788#" "vssa2" 3348.17
cap "VGA_routing_0/m4_419918_417788#" "vssa2" 3348.17
cap "VGA_routing_0/m4_419918_417788#" "vssa2" 1394.58
cap "VGA_routing_0/m1_443140_352045#" "vssa2" 1130.03
cap "VGA_routing_0/m1_443140_352045#" "vssa2" 3348.17
cap "VGA_routing_0/m1_443140_352045#" "vssa2" 3348.17
cap "vssa2" "VGA_routing_0/m1_443140_352045#" 3348.17
cap "vssa2" "VGA_routing_0/m1_443140_352045#" 2292.24
cap "vssa2" "VGA_routing_0/m4_419918_417788#" 1290.18
cap "vssa2" "VGA_routing_0/m4_419918_417788#" 3348.17
cap "VGA_routing_0/m4_419918_417788#" "vssa2" 3348.17
cap "VGA_routing_0/m4_419918_417788#" "vssa2" 3348.17
cap "VGA_routing_0/m4_419918_417788#" "vssa2" 1394.58
cap "vssa2" "VGA_routing_0/m1_443140_352045#" 1130.03
cap "VGA_routing_0/m1_443140_352045#" "vssa2" 3348.17
cap "VGA_routing_0/m1_443140_352045#" "vssa2" 3348.17
cap "vssa2" "VGA_routing_0/m1_443140_352045#" 3348.17
cap "vssa2" "VGA_routing_0/m1_443140_352045#" 2292.24
cap "VGA_routing_0/m4_419918_417788#" "vssa2" 1290.18
cap "vssa2" "VGA_routing_0/m4_419918_417788#" 3348.17
cap "vssa2" "VGA_routing_0/m4_419918_417788#" 3348.17
cap "VGA_routing_0/m4_419918_417788#" "vssa2" 3348.17
cap "vssa2" "VGA_routing_0/m4_419918_417788#" 1394.58
cap "VGA_routing_0/m1_443140_352045#" "vssa2" 1130.03
cap "vssa2" "VGA_routing_0/m1_443140_352045#" 3348.17
cap "VGA_routing_0/m1_443140_352045#" "vssa2" 3348.17
cap "vssa2" "VGA_routing_0/m1_443140_352045#" 3348.17
cap "VGA_routing_0/m1_443140_352045#" "vssa2" 2292.24
cap "vssa2" "VGA_routing_0/m4_419918_417788#" 1290.18
cap "vssa2" "VGA_routing_0/m4_419918_417788#" 3348.17
cap "VGA_routing_0/m4_419918_417788#" "vssa2" 3348.17
cap "VGA_routing_0/m4_419918_417788#" "vssa2" 3348.17
cap "vssa2" "VGA_routing_0/m4_419918_417788#" 1394.58
cap "vssa2" "VGA_routing_0/m1_443140_352045#" 1130.03
cap "vssa2" "VGA_routing_0/m1_443140_352045#" 3348.17
cap "vssa2" "VGA_routing_0/m1_443140_352045#" 3348.17
cap "vssa2" "VGA_routing_0/m1_443140_352045#" 3348.17
cap "vssa2" "VGA_routing_0/m1_443140_352045#" 2292.24
cap "VGA_routing_0/m4_419918_417788#" "vssa2" 1290.18
cap "VGA_routing_0/m4_419918_417788#" "vssa2" 3348.17
cap "vssa2" "VGA_routing_0/m4_419918_417788#" 3348.17
cap "vssa2" "VGA_routing_0/m4_419918_417788#" 3348.17
cap "vssa2" "VGA_routing_0/m4_419918_417788#" 1394.58
cap "BGR_lvs_0/VSS" "vssa2" 1237.44
cap "BGR_lvs_0/VSS" "vssa2" 1136.03
cap "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" "vssa2" 101.411
cap "vssa2" "BGR_lvs_0/VSS" 1136.03
cap "vssa2" "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" 101.411
cap "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" "vssa2" 101.411
cap "BGR_lvs_0/VSS" "vssa2" 1136.03
cap "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" "vssa2" 101.411
cap "BGR_lvs_0/VSS" "vssa2" 1136.03
cap "vssa2" "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" 101.411
cap "BGR_lvs_0/VSS" "vssa2" 1136.03
cap "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" "vssa2" 101.411
cap "BGR_lvs_0/VSS" "vssa2" 1136.03
cap "BGR_lvs_0/VSS" "vssa2" 1136.03
cap "vssa2" "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" 101.411
cap "BGR_lvs_0/VSS" "vssa2" 1136.03
cap "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" "vssa2" 101.411
cap "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" "vssa2" 101.411
cap "BGR_lvs_0/VSS" "vssa2" 1136.03
cap "BGR_lvs_0/VSS" "vssa2" 1136.03
cap "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" "vssa2" 101.411
cap "vssa2" "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" 101.411
cap "BGR_lvs_0/VSS" "vssa2" 1136.03
cap "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" "vssa2" 101.411
cap "BGR_lvs_0/VSS" "vssa2" 1136.03
cap "vssa2" "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" 101.411
cap "BGR_lvs_0/VSS" "vssa2" 1136.03
cap "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_1911_10600#" 267.042
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_2/a_n200_n5500#" 951.909
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_29_n857#" 232.719
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" 200.1
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_3/a_n200_n5500#" 945.723
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_487_n857#" "vssa2" 186.507
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_3/a_n200_n5500#" "vssa2" 903.038
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_29_n857#" 247.133
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_4/a_n200_n5500#" 909.336
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_5/a_n200_n5500#" "vssa2" 982.636
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" "vssa2" 176.708
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_5/a_n200_n5500#" 960.205
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_487_n857#" 183.772
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_6/a_n200_n5500#" "vssa2" 909.336
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n429_n857#" "vssa2" 247.133
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/a_n200_n5500#" 902.16
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" 186.576
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/a_n200_n5500#" "vssa2" 940.854
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_487_n857#" "vssa2" 192.257
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/a_n200_n5500#" 956.778
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n429_n857#" "vssa2" 240.562
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" "vssa2" 174.793
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/a_n200_n5500#" "vssa2" 964.655
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/a_n200_n5500#" "vssa2" 951.909
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_29_n857#" "vssa2" 232.719
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_2/a_n200_n5500#" "vssa2" 945.723
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" "vssa2" 200.1
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_487_n857#" "vssa2" 186.507
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_2/a_n200_n5500#" "vssa2" 903.038
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_3/a_n200_n5500#" "vssa2" 909.336
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_29_n857#" 247.133
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_4/a_n200_n5500#" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" 176.87
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_4/a_n200_n5500#" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_487_n857#" 183.941
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_5/a_n200_n5500#" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n429_n857#" 247.362
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_6/a_n200_n5500#" 186.748
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_487_n857#" "vssa2" 192.257
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_6/a_n200_n5500#" "vssa2" 940.854
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_7/a_n200_n5500#" 956.778
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n429_n857#" 240.562
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" "vssa2" 174.793
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_0/a_n200_n5500#" "vssa2" 964.655
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_0/a_n200_n5500#" 951.909
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_29_n857#" 232.719
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_1/a_n200_n5500#" "vssa2" 945.723
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" "vssa2" 200.1
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_487_n857#" 186.507
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_1/a_n200_n5500#" 903.038
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_2/a_n200_n5500#" "vssa2" 909.336
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_29_n857#" "vssa2" 247.133
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" 176.708
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_3/a_n200_n5500#" 982.636
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_3/a_n200_n5500#" 960.205
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_487_n857#" 183.772
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_4/a_n200_n5500#" "vssa2" 909.336
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n429_n857#" 247.133
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_5/a_n200_n5500#" "vssa2" 902.16
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" "vssa2" 186.576
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_5/a_n200_n5500#" "vssa2" 940.854
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_487_n857#" "vssa2" 192.257
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_6/a_n200_n5500#" 956.778
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n429_n857#" 240.562
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_7/a_n200_n5500#" "vssa2" 964.655
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" "vssa2" 174.793
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_7/a_n200_n5500#" "vssa2" 951.909
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_29_n857#" "vssa2" 232.719
cap "vssa2" "VGA_routing_0/m1_443140_352045#" 1130.03
cap "VGA_routing_0/m1_443140_352045#" "vssa2" 3348.17
cap "VGA_routing_0/m1_443140_352045#" "vssa2" 3348.17
cap "vssa2" "VGA_routing_0/m1_443140_352045#" 3348.17
cap "VGA_routing_0/m1_443140_352045#" "vssa2" 2292.24
cap "VGA_routing_0/m4_419918_417788#" "vssa2" 1290.18
cap "vssa2" "VGA_routing_0/m4_419918_417788#" 3348.17
cap "VGA_routing_0/m4_419918_417788#" "vssa2" 3348.17
cap "VGA_routing_0/m4_419918_417788#" "vssa2" 3348.17
cap "VGA_routing_0/m4_419918_417788#" "vssa2" 1394.58
cap "BGR_lvs_0/VSS" "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_669_n11032#" 329.713
cap "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_1911_10600#" 347.776
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_29_n857#" 549.278
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_2/a_n200_n5500#" 545.996
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_3/a_n200_n5500#" "vssa2" 582.026
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" "vssa2" 492.097
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_487_n857#" "vssa2" 469.007
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_3/a_n200_n5500#" "vssa2" 557.239
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_4/a_n200_n5500#" 571.213
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_29_n857#" "vssa2" 571.675
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_5/a_n200_n5500#" "vssa2" 674.204
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" 450.986
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_487_n857#" 462.559
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_5/a_n200_n5500#" "vssa2" 629.834
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n429_n857#" 571.675
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_6/a_n200_n5500#" "vssa2" 571.213
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/a_n200_n5500#" "vssa2" 556.403
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" 479.38
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/a_n200_n5500#" 585.112
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_487_n857#" "vssa2" 477.072
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/a_n200_n5500#" 542.91
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n429_n857#" 564.304
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/a_n200_n5500#" 747.23
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" 441.664
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_29_n857#" "vssa2" 549.278
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/a_n200_n5500#" 545.996
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" 492.097
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_2/a_n200_n5500#" 582.026
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_487_n857#" 469.007
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_2/a_n200_n5500#" 557.239
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_3/a_n200_n5500#" 571.213
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_29_n857#" "vssa2" 571.675
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_4/a_n200_n5500#" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" 450.986
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_4/a_n200_n5500#" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_487_n857#" 462.559
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n429_n857#" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_5/a_n200_n5500#" 571.675
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_6/a_n200_n5500#" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" 479.38
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_6/a_n200_n5500#" "vssa2" 585.112
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_487_n857#" "vssa2" 477.072
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n429_n857#" "vssa2" 564.304
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_7/a_n200_n5500#" "vssa2" 542.91
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_0/a_n200_n5500#" "vssa2" 747.23
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" "vssa2" 441.664
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_0/a_n200_n5500#" 545.996
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_29_n857#" "vssa2" 549.278
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_1/a_n200_n5500#" "vssa2" 582.026
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" "vssa2" 492.097
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_1/a_n200_n5500#" "vssa2" 557.239
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_487_n857#" "vssa2" 469.007
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_29_n857#" "vssa2" 571.675
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_2/a_n200_n5500#" 571.213
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_3/a_n200_n5500#" 674.204
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" "vssa2" 450.986
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_3/a_n200_n5500#" "vssa2" 629.834
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_487_n857#" "vssa2" 462.559
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_4/a_n200_n5500#" "vssa2" 571.213
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n429_n857#" 571.675
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" "vssa2" 479.38
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_5/a_n200_n5500#" "vssa2" 556.403
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_5/a_n200_n5500#" "vssa2" 585.112
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_487_n857#" "vssa2" 477.072
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_6/a_n200_n5500#" 542.91
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n429_n857#" "vssa2" 564.304
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" 441.664
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_7/a_n200_n5500#" "vssa2" 747.23
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_29_n857#" "vssa2" 549.278
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_7/a_n200_n5500#" 545.996
cap "vssa2" "VGA_routing_0/m1_443140_352045#" 1130.03
cap "VGA_routing_0/m1_443140_352045#" "vssa2" 3348.17
cap "vssa2" "VGA_routing_0/m1_443140_352045#" 3348.17
cap "VGA_routing_0/m1_443140_352045#" "vssa2" 3348.17
cap "vssa2" "VGA_routing_0/m1_443140_352045#" 2292.24
cap "VGA_routing_0/m4_419918_417788#" "vssa2" 1290.18
cap "vssa2" "VGA_routing_0/m4_419918_417788#" 3348.17
cap "VGA_routing_0/m4_419918_417788#" "vssa2" 3348.17
cap "VGA_routing_0/m4_419918_417788#" "vssa2" 3348.17
cap "VGA_routing_0/m4_419918_417788#" "vssa2" 1394.58
cap "BGR_lvs_0/VSS" "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n1815_n11032#" 13.1807
cap "BGR_lvs_0/VSS" "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_669_n11032#" 368.37
cap "vssa2" "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n573_10600#" 320.019
cap "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_1911_10600#" "vssa2" 7.96568
cap "vssa2" "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" 58.9357
cap "BGR_lvs_0/VSS" "vssa2" 974.578
cap "vssa2" "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" 135.123
cap "vssa2" "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" 1053.58
cap "BGR_lvs_0/VSS" "vssa2" 400.606
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_0/a_n200_n5500#" 1155.75
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_429_n831#" 729.823
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_29_n857#" 68.5797
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_29_n857#" "vssa2" 271.622
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" 59.3876
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" 234.513
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n487_n831#" 741.599
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_487_n857#" "vssa2" 217.302
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" 55.9244
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_887_n831#" 680.273
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_429_n831#" "vssa2" 879.509
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_29_n857#" "vssa2" 72.2661
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_29_n857#" "vssa2" 287.917
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n487_n831#" 789.783
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" "vssa2" 52.8882
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" 206.336
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_487_n857#" 214.411
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_887_n831#" "vssa2" 741.279
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" "vssa2" 54.9653
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n29_n831#" 879.509
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n429_n857#" "vssa2" 72.2661
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n429_n857#" "vssa2" 287.917
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" "vssa2" 218.202
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n945_n831#" "vssa2" 684.583
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" "vssa2" 56.1007
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" "vssa2" 56.8206
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_487_n857#" "vssa2" 224.246
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_429_n831#" "vssa2" 739.988
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n429_n857#" 71.1467
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n29_n831#" 731.434
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n429_n857#" "vssa2" 281.889
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/a_n200_n5500#" 917.461
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" "vssa2" 202.827
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" 52.5212
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_29_n857#" "vssa2" 68.5797
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_429_n831#" "vssa2" 729.823
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_29_n857#" "vssa2" 271.622
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" "vssa2" 234.513
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n487_n831#" "vssa2" 741.599
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" "vssa2" 59.3876
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" "vssa2" 55.9244
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_887_n831#" "vssa2" 680.273
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_487_n857#" 217.302
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_29_n857#" "vssa2" 287.917
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_429_n831#" 879.509
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_29_n857#" 72.2661
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n487_n831#" "vssa2" 789.783
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" "vssa2" 52.8882
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" "vssa2" 206.336
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_487_n857#" 214.411
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_887_n831#" 741.279
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" "vssa2" 54.9653
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n29_n831#" "vssa2" 879.509
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n429_n857#" "vssa2" 72.2661
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n429_n857#" 287.917
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n945_n831#" 684.583
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" 218.202
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" 56.1007
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_429_n831#" "vssa2" 739.988
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_487_n857#" "vssa2" 224.246
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" "vssa2" 56.8206
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n429_n857#" 71.1467
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n29_n831#" 731.434
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n429_n857#" "vssa2" 281.889
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_6/a_n200_n5500#" "vssa2" 917.461
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" "vssa2" 52.5212
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" 202.827
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_29_n857#" "vssa2" 68.5797
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_29_n857#" "vssa2" 271.622
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_429_n831#" "vssa2" 729.823
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" "vssa2" 59.3876
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" 234.513
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n487_n831#" "vssa2" 741.599
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_487_n857#" 217.302
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" 55.9244
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_887_n831#" 680.273
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_429_n831#" 879.509
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_29_n857#" 72.2661
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_29_n857#" 287.917
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" "vssa2" 52.8882
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n487_n831#" "vssa2" 789.783
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" 206.336
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" "vssa2" 54.9653
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_487_n857#" "vssa2" 214.411
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_887_n831#" "vssa2" 741.279
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n29_n831#" "vssa2" 879.509
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n429_n857#" "vssa2" 72.2661
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n429_n857#" "vssa2" 287.917
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n945_n831#" "vssa2" 684.583
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" "vssa2" 218.202
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" "vssa2" 56.1007
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" "vssa2" 56.8206
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_487_n857#" 224.246
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_429_n831#" "vssa2" 739.988
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n429_n857#" 281.889
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n29_n831#" "vssa2" 731.434
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n429_n857#" "vssa2" 71.1467
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" "vssa2" 202.827
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" 52.5212
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_5/a_n200_n5500#" "vssa2" 917.461
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_429_n831#" "vssa2" 729.823
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_29_n857#" "vssa2" 68.5797
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_29_n857#" 271.622
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n887_n857#" "vssa2" 1019.13
cap "vssa2" "BGR_lvs_0/VSS" 1136.03
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_487_n857#" "vssa2" 807.66
cap "vssa2" "VGA_routing_0/m1_443140_352045#" 1130.03
cap "vssa2" "VGA_routing_0/m1_443140_352045#" 3348.17
cap "VGA_routing_0/m1_443140_352045#" "vssa2" 3348.17
cap "VGA_routing_0/m1_443140_352045#" "vssa2" 3348.17
cap "VGA_routing_0/m1_443140_352045#" "vssa2" 2292.24
cap "VGA_routing_0/m4_419918_417788#" "vssa2" 1290.18
cap "VGA_routing_0/m4_419918_417788#" "vssa2" 3348.17
cap "vssa2" "VGA_routing_0/m4_419918_417788#" 3348.17
cap "vssa2" "VGA_routing_0/m4_419918_417788#" 3348.17
cap "VGA_routing_0/m4_419918_417788#" "vssa2" 1394.58
cap "BGR_lvs_0/VSS" "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n1815_n11032#" 406.957
cap "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n573_10600#" "vssa2" 280.215
cap "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3057_10600#" "vssa2" 51.6852
cap "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" "vssa2" 56.2569
cap "BGR_lvs_0/VSS" "vssa2" 974.578
cap "vssa2" "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" 131.618
cap "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" "vssa2" 929.176
cap "BGR_lvs_0/VSS" "vssa2" 400.606
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_0/a_n200_n5500#" "vssa2" 1110.68
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_29_n857#" 275.307
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64S6GM_1/a_429_n769#" 664.822
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64S6GM_1/a_n487_n769#" "vssa2" 694.226
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" "vssa2" 237.371
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64S6GM_1/a_887_n769#" 672.988
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" "vssa2" 219.058
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_29_n857#" "vssa2" 292.456
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64S6GM_1/a_429_n769#" "vssa2" 768.189
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64S6GM_1/a_n487_n769#" "vssa2" 779.882
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" "vssa2" 208.189
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" "vssa2" 216.116
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64S6GM_1/a_887_n769#" "vssa2" 732.513
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64S6GM_1/a_n29_n769#" 768.189
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n429_n857#" 292.456
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64S6GM_1/a_n945_n769#" 672.009
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" 220.024
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64S6GM_1/a_429_n769#" "vssa2" 697.02
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" "vssa2" 227
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n429_n857#" "vssa2" 285.678
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64S6GM_1/a_n29_n769#" "vssa2" 662.029
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" 204.083
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/a_n200_n5500#" 921.816
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64S6GM_1/a_429_n769#" "vssa2" 664.822
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_29_n857#" "vssa2" 275.307
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64S6GM_1/a_n487_n769#" 694.226
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" 237.371
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64S6GM_1/a_887_n769#" "vssa2" 672.988
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" "vssa2" 219.058
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64S6GM_1/a_429_n769#" 768.189
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_29_n857#" "vssa2" 292.456
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64S6GM_1/a_n487_n769#" "vssa2" 779.882
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" "vssa2" 208.189
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64S6GM_1/a_887_n769#" "vssa2" 732.513
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" "vssa2" 216.116
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64S6GM_1/a_n29_n769#" "vssa2" 768.189
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n429_n857#" "vssa2" 292.456
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64S6GM_1/a_n945_n769#" "vssa2" 672.009
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" "vssa2" 220.024
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64S6GM_1/a_429_n769#" "vssa2" 697.02
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" "vssa2" 227
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64S6GM_1/a_n29_n769#" "vssa2" 662.029
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n429_n857#" "vssa2" 285.678
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" "vssa2" 204.083
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_6/a_n200_n5500#" "vssa2" 921.816
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64S6GM_1/a_429_n769#" "vssa2" 664.822
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_29_n857#" "vssa2" 275.307
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64S6GM_1/a_n487_n769#" "vssa2" 694.226
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" "vssa2" 237.371
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" "vssa2" 219.058
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64S6GM_1/a_887_n769#" "vssa2" 672.988
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_29_n857#" 292.456
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64S6GM_1/a_429_n769#" "vssa2" 768.189
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64S6GM_1/a_n487_n769#" "vssa2" 779.882
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" "vssa2" 208.189
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" "vssa2" 216.116
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64S6GM_1/a_887_n769#" "vssa2" 732.513
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64S6GM_1/a_n29_n769#" "vssa2" 768.189
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n429_n857#" "vssa2" 292.456
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64S6GM_1/a_n945_n769#" "vssa2" 672.009
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" "vssa2" 220.024
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" 227
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64S6GM_1/a_429_n769#" 697.02
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64S6GM_1/a_n29_n769#" 662.029
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n429_n857#" 285.678
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" "vssa2" 204.083
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_5/a_n200_n5500#" "vssa2" 921.816
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64S6GM_1/a_429_n769#" "vssa2" 664.822
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_29_n857#" "vssa2" 275.307
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" "vssa2" 914.872
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" "vssa2" 754.795
cap "BGR_lvs_0/VSS" "vssa2" 1136.03
cap "VGA_routing_0/m1_443140_352045#" "vssa2" 1130.03
cap "vssa2" "VGA_routing_0/m1_443140_352045#" 3348.17
cap "vssa2" "VGA_routing_0/m1_443140_352045#" 3348.17
cap "vssa2" "VGA_routing_0/m1_443140_352045#" 3348.17
cap "vssa2" "VGA_routing_0/m1_443140_352045#" 2292.24
cap "vssa2" "VGA_routing_0/m4_419918_417788#" 1290.18
cap "VGA_routing_0/m4_419918_417788#" "vssa2" 3348.17
cap "vssa2" "VGA_routing_0/m4_419918_417788#" 3348.17
cap "vssa2" "VGA_routing_0/m4_419918_417788#" 3348.17
cap "VGA_routing_0/m4_419918_417788#" "vssa2" 1394.58
cap "BGR_lvs_0/VSS" "BGR_lvs_0/opamp_realcomp3_usefinger_1/bias_0p7" 17.5639
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_tail_0/sky130_fd_pr__nfet_01v8_lvt_7MFZYU_0/a_n29_n1281#" "BGR_lvs_0/VSS" 0.819554
cap "BGR_lvs_0/VSS" "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n1815_n11032#" 267.371
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_diffpair_0/sky130_fd_pr__nfet_01v8_lvt_A5VCMN_0/a_29_n507#" "vssa2" 0.470184
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_diffpair_0/sky130_fd_pr__nfet_01v8_lvt_A5VCMN_0/a_n545_n481#" "vssa2" 2.734
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_diffpair_0/sky130_fd_pr__nfet_01v8_lvt_A5VCMN_0/a_n487_n507#" "vssa2" 0.470184
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/bias_0p7" "vssa2" 8.0938
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_diffpair_0/sky130_fd_pr__nfet_01v8_lvt_A5VCMN_0/a_287_n507#" "vssa2" 0.468317
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_diffpair_0/sky130_fd_pr__nfet_01v8_lvt_A5VCMN_0/a_n287_n481#" "vssa2" 0.467045
cap "BGR_lvs_0/vd4" "vssa2" 36.0903
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_diffpair_0/sky130_fd_pr__nfet_01v8_lvt_A5VCMN_0/a_n229_n507#" "vssa2" 0.470184
cap "BGR_lvs_0/VSS" "vssa2" 170.765
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_diffpair_0/sky130_fd_pr__nfet_01v8_lvt_A5VCMN_0/a_n29_n481#" "vssa2" 0.233523
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_actload2_0/sky130_fd_pr__nfet_01v8_lvt_USQY94_0/a_n716_n1403#" "vssa2" 1.29692
cap "vssa2" "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_GWJZ59_0/a_n271_n10962#" 5.43054
cap "vssa2" "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" 137.22
cap "BGR_lvs_0/vd4" "vssa2" 111.339
cap "vssa2" "BGR_lvs_0/opamp_realcomp3_usefinger_1/bias_0p7" 23.2564
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_diffpair_0/sky130_fd_pr__nfet_01v8_lvt_A5VCMN_0/a_n545_n481#" "vssa2" 0.218873
cap "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" "vssa2" 136.936
cap "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_GWJZ59_0/a_n271_n10962#" "vssa2" 5.43533
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_actload2_0/sky130_fd_pr__nfet_01v8_lvt_USQY94_0/a_n716_n1403#" "vssa2" 1.29692
cap "BGR_lvs_0/vd4" "vssa2" 103.899
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/bias_0p7" "vssa2" 31.8821
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_cs_0/sky130_fd_pr__pfet_01v8_lvt_D74VRS_0/w_n1273_n2831#" "vssa2" 29.0268
cap "vssa2" "BGR_lvs_0/opamp_realcomp3_usefinger_1/out" 14.7464
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/bias_0p7" "vssa2" 2.6559
cap "BGR_lvs_0/vd4" "vssa2" 103.899
cap "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_GWJZ59_0/a_n271_n10962#" "vssa2" 5.43533
cap "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" "vssa2" 64.1789
cap "vssa2" "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_cs_0/sky130_fd_pr__pfet_01v8_lvt_D74VRS_0/a_n1077_n2709#" 14.1781
cap "vssa2" "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_actload2_0/sky130_fd_pr__nfet_01v8_lvt_USQY94_0/a_n258_n1403#" 51.6948
cap "BGR_lvs_0/vd4" "vssa2" 103.899
cap "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_GWJZ59_0/a_n271_n10962#" "vssa2" 5.43533
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/vss" "vssa2" 51.6948
cap "vssa2" "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" 61.2991
cap "vssa2" "BGR_lvs_0/opamp_realcomp3_usefinger_1/out" 19.0241
cap "vssa2" "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_cs_0/sky130_fd_pr__pfet_01v8_lvt_D74VRS_0/w_n1273_n2831#" 38.5099
cap "vssa2" "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_cs_0/sky130_fd_pr__pfet_01v8_lvt_D74VRS_0/a_n1077_n2709#" 20.7886
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_cs_0/sky130_fd_pr__pfet_01v8_lvt_D74VRS_0/w_n1273_n2831#" "vssa2" 4.65899
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/out" "vssa2" 90.2043
cap "vssa2" "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_GWJZ59_0/a_n271_n10962#" 5.41883
cap "vssa2" "BGR_lvs_0/vd4" 103.899
cap "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" "vssa2" 119.936
cap "vssa2" "BGR_lvs_0/vd4" 103.899
cap "BGR_lvs_0/XM_bjt_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[0,0]/Base" "vssa2" 131.12
cap "vssa2" "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_GWJZ59_0/a_n271_n10962#" 5.43533
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/out" "vssa2" 84.0111
cap "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_HX7ZEK_0/a_n141_n5182#" "vssa2" 12.5992
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/sky130_fd_pr__res_high_po_2p85_7J2RPB_0/a_n285_1210#" "vssa2" 10.0832
cap "BGR_lvs_0/XM_bjt_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[0,0]/Base" "vssa2" 122.032
cap "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_GWJZ59_0/a_n271_n10962#" "vssa2" 5.43533
cap "BGR_lvs_0/m1_6080_n3700#" "vssa2" 84.0111
cap "BGR_lvs_0/vd4" "vssa2" 103.899
cap "BGR_lvs_0/XM_bjt_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[0,0]/Base" "vssa2" 85.1759
cap "BGR_lvs_0/m1_6080_n3700#" "vssa2" 84.0111
cap "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_GWJZ59_0/a_n271_n10962#" "vssa2" 5.43436
cap "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_HX7ZEK_0/a_n141_n5182#" "vssa2" 13.8946
cap "BGR_lvs_0/vd4" "vssa2" 103.899
cap "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_HX7ZEK_0/a_n141_n5182#" "vssa2" 12.024
cap "BGR_lvs_0/m1_6080_n3700#" "vssa2" 84.0111
cap "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_GWJZ59_0/a_n271_n10962#" "vssa2" 5.43533
cap "BGR_lvs_0/vd4" "vssa2" 103.899
cap "BGR_lvs_0/XM_bjt_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[0,0]/Base" "vssa2" 69.5377
cap "BGR_lvs_0/vd4" "vssa2" 103.899
cap "vssa2" "BGR_lvs_0/m1_6080_n3700#" 84.0111
cap "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_GWJZ59_0/a_n271_n10962#" "vssa2" 5.43533
cap "vssa2" "BGR_lvs_0/m1_n1770_n3060#" 12.024
cap "vssa2" "BGR_lvs_0/XM_bjt_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[0,1]/Base" 69.5377
cap "vssa2" "BGR_lvs_0/m1_n1770_n3060#" 12.024
cap "vssa2" "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_GWJZ59_0/a_n271_n10962#" 5.43533
cap "vssa2" "BGR_lvs_0/m1_6080_n3700#" 84.0111
cap "vssa2" "BGR_lvs_0/XM_bjt_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[0,2]/Base" 69.5377
cap "vssa2" "BGR_lvs_0/vd4" 103.899
cap "vssa2" "BGR_lvs_0/m1_n1770_n3060#" 12.024
cap "vssa2" "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_GWJZ59_0/a_n271_n10962#" 5.43533
cap "vssa2" "BGR_lvs_0/m1_6080_n3700#" 84.0111
cap "vssa2" "BGR_lvs_0/vd4" 103.899
cap "vssa2" "BGR_lvs_0/XM_bjt_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[0,3]/Base" 69.5377
cap "BGR_lvs_0/vd4" "vssa2" 103.899
cap "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_GWJZ59_0/a_n141_10400#" "vssa2" 28.4971
cap "BGR_lvs_0/m1_6080_n3700#" "vssa2" 72.8785
cap "BGR_lvs_0/XM_bjt_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[0,4]/Base" "vssa2" 74.9512
cap "BGR_lvs_0/vd4" "vssa2" 402.372
cap "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_GWJZ59_0/a_n141_10400#" "vssa2" 76.3093
cap "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" "vssa2" 85.4311
cap "vssa2" "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" 692.923
cap "vssa2" "BGR_lvs_0/vd4" 6.51204
cap "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" "vssa2" 1056.52
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_0/a_n200_n5500#" "vssa2" 867.537
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_2/a_n200_n5500#" 326.376
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_29_n857#" 511.634
cap "BGR_lvs_0/VSS" "vssa2" 10.8085
cap "BGR_lvs_0/VSS" "vssa2" 10.8085
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_3/a_n200_n5500#" "vssa2" 371.866
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" "vssa2" 454.92
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_3/a_n200_n5500#" 363.599
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" 432.365
cap "BGR_lvs_0/VSS" "vssa2" 10.8085
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_29_n857#" 532.936
cap "BGR_lvs_0/VSS" "vssa2" 10.8085
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_4/a_n200_n5500#" 331.53
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" 415.188
cap "BGR_lvs_0/VSS" "vssa2" 10.8085
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_5/a_n200_n5500#" "vssa2" 426.316
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" 426.925
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_5/a_n200_n5500#" 396.486
cap "vssa2" "BGR_lvs_0/VSS" 10.8085
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n429_n857#" 532.936
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_6/a_n200_n5500#" "vssa2" 331.53
cap "BGR_lvs_0/VSS" "vssa2" 10.8085
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" 439.298
cap "BGR_lvs_0/VSS" "vssa2" 10.8085
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/a_n200_n5500#" "vssa2" 363.108
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/a_n200_n5500#" "vssa2" 374.103
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" 440.427
cap "BGR_lvs_0/VSS" "vssa2" 10.8085
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/a_n200_n5500#" "vssa2" 324.139
cap "BGR_lvs_0/VSS" "vssa2" 10.8085
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n429_n857#" "vssa2" 526.127
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" "vssa2" 407.028
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/a_n200_n5500#" 456.084
cap "vssa2" "BGR_lvs_0/VSS" 10.8085
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_29_n857#" "vssa2" 511.634
cap "BGR_lvs_0/VSS" "vssa2" 11.309
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/a_n200_n5500#" "vssa2" 326.376
cap "BGR_lvs_0/VSS" "vssa2" 11.309
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_2/a_n200_n5500#" 371.866
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" "vssa2" 454.92
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" "vssa2" 432.365
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_2/a_n200_n5500#" "vssa2" 374.79
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_3/a_n200_n5500#" 343.221
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_29_n857#" "vssa2" 532.936
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" 415.188
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_4/a_n200_n5500#" "vssa2" 440.409
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" "vssa2" 426.925
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_4/a_n200_n5500#" 407.89
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n429_n857#" "vssa2" 532.936
cap "BGR_lvs_0/VSS" "vssa2" 11.309
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_5/a_n200_n5500#" "vssa2" 331.53
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" "vssa2" 439.298
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_6/a_n200_n5500#" "vssa2" 363.108
cap "BGR_lvs_0/VSS" "vssa2" 10.8085
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" 440.427
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_6/a_n200_n5500#" "vssa2" 374.103
cap "BGR_lvs_0/VSS" "vssa2" 11.309
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n429_n857#" "vssa2" 526.127
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_7/a_n200_n5500#" "vssa2" 324.139
cap "BGR_lvs_0/VSS" "vssa2" 11.309
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" "vssa2" 407.028
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_0/a_n200_n5500#" 456.084
cap "BGR_lvs_0/VSS" "vssa2" 10.8085
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_0/a_n200_n5500#" "vssa2" 326.376
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_29_n857#" 511.634
cap "vssa2" "BGR_lvs_0/VSS" 11.309
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" 454.92
cap "vssa2" "BGR_lvs_0/VSS" 10.8085
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_1/a_n200_n5500#" "vssa2" 371.866
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" "vssa2" 432.365
cap "BGR_lvs_0/VSS" "vssa2" 10.8085
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_1/a_n200_n5500#" 363.599
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_29_n857#" 532.936
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_2/a_n200_n5500#" 331.53
cap "BGR_lvs_0/VSS" "vssa2" 10.8085
cap "vssa2" "BGR_lvs_0/VSS" 10.8085
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_3/a_n200_n5500#" "vssa2" 426.316
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" "vssa2" 415.188
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_3/a_n200_n5500#" "vssa2" 396.486
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" "vssa2" 426.925
cap "BGR_lvs_0/VSS" "vssa2" 10.8085
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n429_n857#" "vssa2" 532.936
cap "BGR_lvs_0/VSS" "vssa2" 10.8085
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_4/a_n200_n5500#" "vssa2" 331.53
cap "BGR_lvs_0/VSS" "vssa2" 10.8085
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" 439.298
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_5/a_n200_n5500#" "vssa2" 363.108
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_5/a_n200_n5500#" 374.103
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" 440.427
cap "BGR_lvs_0/VSS" "vssa2" 10.8085
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n429_n857#" "vssa2" 526.127
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_6/a_n200_n5500#" 324.139
cap "vssa2" "BGR_lvs_0/VSS" 10.8085
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_7/a_n200_n5500#" 456.084
cap "BGR_lvs_0/VSS" "vssa2" 10.8085
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" 407.028
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_7/a_n200_n5500#" "vssa2" 326.376
cap "vssa2" "BGR_lvs_0/VSS" 10.8085
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_29_n857#" "vssa2" 511.634
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" 830.817
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" "vssa2" 1181.01
cap "VGA_routing_0/m1_443140_352045#" "vssa2" 623.022
cap "VGA_routing_0/m1_443140_352045#" "vssa2" 2014.67
cap "VGA_routing_0/m1_443140_352045#" "vssa2" 2014.67
cap "vssa2" "VGA_routing_0/m1_443140_352045#" 2014.67
cap "vssa2" "VGA_routing_0/m1_443140_352045#" 1322.36
cap "VGA_routing_0/m4_419918_417788#" "vssa2" 719.403
cap "VGA_routing_0/m4_419918_417788#" "vssa2" 2014.67
cap "vssa2" "VGA_routing_0/m4_419918_417788#" 2014.67
cap "vssa2" "VGA_routing_0/m4_419918_417788#" 2014.67
cap "vssa2" "VGA_routing_0/m4_419918_417788#" 782.366
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_tail_0/sky130_fd_pr__nfet_01v8_lvt_7MFZYU_0/a_n29_n1281#" "BGR_lvs_0/opamp_realcomp3_usefinger_1/vss" 32.1589
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/bias_0p7" "BGR_lvs_0/opamp_realcomp3_usefinger_1/vss" 39.9548
cap "vssa2" "BGR_lvs_0/opamp_realcomp3_usefinger_1/first_stage_out" 0.00499201
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/vss" "vssa2" 76.7066
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_diffpair_0/sky130_fd_pr__nfet_01v8_lvt_A5VCMN_0/a_n545_n481#" 0.000953033
cap "vssa2" "BGR_lvs_0/opamp_realcomp3_usefinger_1/in_p" 0.157811
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_tail_0/sky130_fd_pr__nfet_01v8_lvt_7MFZYU_0/a_n29_n1281#" "vssa2" 0.00998402
cap "vssa2" "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_diffpair_0/sky130_fd_pr__nfet_01v8_lvt_A5VCMN_0/a_n545_n481#" 0.784723
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/in_n" "vssa2" 0.157811
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/bias_0p7" "vssa2" 4.9372
cap "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" "vssa2" 56.3384
cap "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_GWJZ59_0/a_n271_n10962#" "vssa2" 4.43257
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_actload2_0/sky130_fd_pr__nfet_01v8_lvt_USQY94_0/a_n716_n1403#" "vssa2" 0.153953
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_diffpair_0/sky130_fd_pr__nfet_01v8_lvt_A5VCMN_0/a_n545_n481#" "vssa2" 0.024867
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/bias_0p7" "vssa2" 7.06887
cap "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_GWJZ59_0/a_n271_n10962#" "vssa2" 4.43257
cap "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" "vssa2" 59.8369
cap "vssa2" "BGR_lvs_0/opamp_realcomp3_usefinger_1/bias_0p7" 7.73629
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/out" "vssa2" 0.0138131
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_actload2_0/sky130_fd_pr__nfet_01v8_lvt_USQY94_0/a_n258_n1403#" "vssa2" 52.0622
cap "vssa2" "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_GWJZ59_0/a_n271_n10962#" 4.43257
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_cs_0/sky130_fd_pr__pfet_01v8_lvt_D74VRS_0/w_n1273_n2831#" "vssa2" 0.836934
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_cs_0/sky130_fd_pr__pfet_01v8_lvt_D74VRS_0/a_n1077_n2709#" "vssa2" 4.49639
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/bias_0p7" "vssa2" 0.640074
cap "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" "vssa2" 0.112843
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/out" "vssa2" 4.30107
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_cs_0/sky130_fd_pr__pfet_01v8_lvt_D74VRS_0/a_n1077_n2709#" "vssa2" 6.05805
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/vss" "vssa2" 52.0622
cap "vssa2" "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_GWJZ59_0/a_n271_n10962#" 4.43257
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/out" "vssa2" 6.07903
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_cs_0/sky130_fd_pr__pfet_01v8_lvt_D74VRS_0/w_n1273_n2831#" "vssa2" 1.15704
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_cs_0/sky130_fd_pr__pfet_01v8_lvt_D74VRS_0/w_n1273_n2831#" "vssa2" 0.0405911
cap "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" "vssa2" 52.7296
cap "vssa2" "BGR_lvs_0/opamp_realcomp3_usefinger_1/out" 1.74068
cap "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_GWJZ59_0/a_n271_n10962#" "vssa2" 4.43257
cap "vssa2" "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_GWJZ59_0/a_n271_n10962#" 4.43257
cap "vssa2" "BGR_lvs_0/XM_bjt_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[0,0]/Base" 60.0695
cap "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_HX7ZEK_0/a_n141_n5182#" "vssa2" 1.01919
cap "vssa2" "BGR_lvs_0/XM_bjt_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[0,0]/Collector" 52.5553
cap "vssa2" "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_GWJZ59_0/a_n271_n10962#" 4.43257
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/sky130_fd_pr__res_high_po_2p85_7J2RPB_0/a_n285_1210#" "vssa2" 1.06323
cap "BGR_lvs_0/XM_bjt_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[0,0]/Collector" "vssa2" 10.3229
cap "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_HX7ZEK_0/a_n141_n5182#" "vssa2" 1.91388
cap "vssa2" "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_GWJZ59_0/a_n271_n10962#" 4.43257
cap "BGR_lvs_0/XM_bjt_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[0,0]/Collector" "vssa2" 0.647584
cap "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_GWJZ59_0/a_n271_n10962#" "vssa2" 4.43257
cap "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_HX7ZEK_0/a_n141_n5182#" "vssa2" 1.77423
cap "BGR_lvs_0/XM_bjt_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[0,1]/Collector" "vssa2" 0.647584
cap "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_GWJZ59_0/a_n271_n10962#" "vssa2" 4.43257
cap "BGR_lvs_0/m1_n1770_n3060#" "vssa2" 1.77423
cap "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_GWJZ59_0/a_n271_n10962#" "vssa2" 4.43257
cap "BGR_lvs_0/XM_bjt_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[0,2]/Collector" "vssa2" 0.647584
cap "BGR_lvs_0/m1_n1770_n3060#" "vssa2" 1.77423
cap "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_GWJZ59_0/a_n271_n10962#" "vssa2" 4.43257
cap "vssa2" "BGR_lvs_0/XM_bjt_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[0,3]/Collector" 0.647584
cap "BGR_lvs_0/m1_n1770_n3060#" "vssa2" 1.77423
cap "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_GWJZ59_0/a_n141_10400#" "vssa2" 1.4846
cap "vssa2" "BGR_lvs_0/XM_bjt_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[0,4]/Collector" 5.08016
cap "vssa2" "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" 3.72089
cap "vssa2" "BGR_lvs_0/vd4" 2.96169
cap "vssa2" "BGR_lvs_0/vd4" 0.895782
cap "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" "vssa2" 3.28558
cap "vssa2" "BGR_lvs_0/XM_Rref_0/sky130_fd_pr__res_xhigh_po_5p73_UZMRKM_0/a_n3187_n11162#" 13.9006
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_0/a_n200_n5500#" 11.1825
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_2/a_n200_n5500#" "vssa2" 5.16729
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_29_n857#" 1.73433
cap "BGR_lvs_0/VSS" "vssa2" 6.13119
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" 1.49326
cap "BGR_lvs_0/VSS" "vssa2" 6.13119
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_3/a_n200_n5500#" 4.28731
cap "BGR_lvs_0/VSS" "vssa2" 6.13119
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_3/a_n200_n5500#" 4.29312
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" 1.38057
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_4/a_n200_n5500#" 4.94036
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_29_n857#" 1.84643
cap "BGR_lvs_0/VSS" "vssa2" 6.13119
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_5/a_n200_n5500#" 3.75066
cap "BGR_lvs_0/VSS" "vssa2" 6.13119
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" 1.30774
cap "BGR_lvs_0/VSS" "vssa2" 6.13119
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_5/a_n200_n5500#" "vssa2" 3.89822
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" "vssa2" 1.36521
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n429_n857#" 1.84643
cap "BGR_lvs_0/VSS" "vssa2" 6.13119
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_6/a_n200_n5500#" 4.94036
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/a_n200_n5500#" 4.24104
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" 1.38174
cap "BGR_lvs_0/VSS" "vssa2" 6.13119
cap "BGR_lvs_0/VSS" "vssa2" 6.13119
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/a_n200_n5500#" 4.14171
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" 1.43225
cap "BGR_lvs_0/VSS" "vssa2" 6.13119
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n429_n857#" 1.79533
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/a_n200_n5500#" 5.31289
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" 1.29179
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/a_n200_n5500#" 3.75952
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_0/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n945_n831#" 6.13119
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_29_n857#" 1.73433
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_0/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n945_n831#" 6.26049
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_5/XM_output_mirr_7/a_n200_n5500#" 5.16729
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_0/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n29_n831#" 6.26049
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_2/a_n200_n5500#" 4.28731
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" 1.49326
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_2/a_n200_n5500#" "vssa2" 10.4243
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" "vssa2" 1.38057
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_3/a_n200_n5500#" 11.2008
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_29_n857#" "vssa2" 1.84643
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_4/a_n200_n5500#" 10.7536
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" 1.30774
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" "vssa2" 1.36521
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_4/a_n200_n5500#" "vssa2" 10.0836
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_0/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n29_n831#" "vssa2" 6.26049
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_5/a_n200_n5500#" 4.94036
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n429_n857#" 1.84643
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_6/a_n200_n5500#" 4.24104
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_0/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n945_n831#" 6.13119
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" 1.38174
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_6/a_n200_n5500#" "vssa2" 4.14171
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_0/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_887_n831#" 6.26049
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" 1.43225
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_0/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n29_n831#" "vssa2" 6.26049
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_7/a_n200_n5500#" 5.31289
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n429_n857#" 1.79533
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" 1.29179
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_0/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n945_n831#" 6.13119
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_0/a_n200_n5500#" "vssa2" 3.75952
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_0/a_n200_n5500#" "vssa2" 5.16729
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_0/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_887_n831#" "vssa2" 6.26049
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_29_n857#" 1.73433
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_0/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_1/a_n29_n831#" 6.13119
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" 1.49326
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_1/a_n200_n5500#" 4.28731
cap "BGR_lvs_0/VSS" "vssa2" 6.13119
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_2/XM_output_mirr_7/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" "vssa2" 1.38057
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_1/a_n200_n5500#" "vssa2" 4.29312
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_29_n857#" "vssa2" 1.84643
cap "BGR_lvs_0/VSS" "vssa2" 6.13119
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_2/a_n200_n5500#" "vssa2" 4.94036
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_3/a_n200_n5500#" "vssa2" 3.75066
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" 1.30774
cap "BGR_lvs_0/VSS" "vssa2" 6.13119
cap "BGR_lvs_0/VSS" "vssa2" 6.13119
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_3/a_n200_n5500#" "vssa2" 3.89822
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" 1.36521
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n429_n857#" "vssa2" 1.84643
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_4/a_n200_n5500#" "vssa2" 4.94036
cap "BGR_lvs_0/VSS" "vssa2" 6.13119
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_5/a_n200_n5500#" "vssa2" 4.24104
cap "vssa2" "BGR_lvs_0/VSS" 6.13119
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" 1.38174
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" 1.43225
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_5/a_n200_n5500#" 4.14171
cap "BGR_lvs_0/VSS" "vssa2" 6.13119
cap "BGR_lvs_0/VSS" "vssa2" 6.13119
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n429_n857#" 1.79533
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_6/a_n200_n5500#" "vssa2" 5.31289
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_7/a_n200_n5500#" "vssa2" 3.75952
cap "BGR_lvs_0/VSS" "vssa2" 6.13119
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" 1.29179
cap "BGR_lvs_0/VSS" "vssa2" 6.13119
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_7/a_n200_n5500#" 5.16729
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_29_n857#" 1.73433
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" "vssa2" 11.9118
cap "vssa2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_8/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" 7.90541
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_tail_0/sky130_fd_pr__nfet_01v8_lvt_7MFZYU_0/a_n29_n1281#" "BGR_lvs_0/opamp_realcomp3_usefinger_1/vss" 60.9076
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/bias_0p7" "BGR_lvs_0/opamp_realcomp3_usefinger_1/vss" 41.3428
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_1/ppair_gate" 0.132141
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/in_p" "BGR_lvs_0/opamp_realcomp3_usefinger_1/vss" 0.078315
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_tail_0/sky130_fd_pr__nfet_01v8_lvt_7MFZYU_0/a_n29_n1281#" 0.0310507
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/in_n" "BGR_lvs_0/opamp_realcomp3_usefinger_1/vss" 0.102144
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_ppair_0/sky130_fd_pr__pfet_01v8_lvt_MBDTEX_0/a_n2035_n262#" 6.12108
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_ppair_0/sky130_fd_pr__pfet_01v8_lvt_MBDTEX_0/a_n1835_n236#" 3.36419
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_ppair_0/w_n220_n1060#" 79.9094
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_1/ppair_gate" 0.326221
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_tail_0/sky130_fd_pr__nfet_01v8_lvt_7MFZYU_0/a_n29_n725#" 11.8606
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_ppair_0/sky130_fd_pr__pfet_01v8_lvt_MBDTEX_0/a_n1835_n236#" 1.34455
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_ppair_0/w_n220_n1060#" 69.5293
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_tail_0/sky130_fd_pr__nfet_01v8_lvt_7MFZYU_0/a_n429_n257#" 3.80678
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_1/first_stage_out" 0.112562
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_ppair_0/w_n220_n1060#" 0.0999727
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/in_p" "BGR_lvs_0/opamp_realcomp3_usefinger_1/vss" 0.0648559
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_tail_0/sky130_fd_pr__nfet_01v8_lvt_7MFZYU_0/a_n429_n257#" 0.0230284
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_1/ppair_gate" 0.696373
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/in_n" "BGR_lvs_0/opamp_realcomp3_usefinger_1/vss" 0.0804129
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_tail_0/sky130_fd_pr__nfet_01v8_lvt_7MFZYU_0/a_n29_n725#" 0.00130271
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_ppair_0/sky130_fd_pr__pfet_01v8_lvt_MBDTEX_0/a_n1835_n236#" "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" 0.0429352
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_ppair_0/sky130_fd_pr__pfet_01v8_lvt_MBDTEX_0/a_n2035_n262#" 15.4293
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_ppair_0/w_n220_n1060#" 125.997
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_1/ppair_gate" 3.18234
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_ppair_0/sky130_fd_pr__pfet_01v8_lvt_MBDTEX_0/a_n1835_n236#" 0.0627922
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_ppair_0/w_n220_n1060#" 109.862
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_ppair_0/w_n220_n1060#" 0.0179585
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_ppair_0/sky130_fd_pr__pfet_01v8_lvt_MBDTEX_0/a_n1835_n236#" "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" 0.00110593
cap "BGR_lvs_0/opamp_realcomp3_usefinger_1/ppair_gate" "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" 0.247526
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_0/bias_0p7" 25.3607
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_0/XM_tail_0/sky130_fd_pr__nfet_01v8_lvt_7MFZYU_0/a_n29_n1281#" 15.4083
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_1/XM_ppair_0/w_n220_n1060#" 0.261655
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_0/XM_diffpair_0/sky130_fd_pr__nfet_01v8_lvt_A5VCMN_0/a_n545_n481#" 0.000637159
cap "vccd2" "BGR_lvs_0/XM_bjt_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[2,2]/Collector" 0.0552996
cap "BGR_lvs_0/XM_bjt_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[2,2]/Emitter" "vccd2" 0.0662703
cap "BGR_lvs_0/XM_bjt_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[2,3]/Emitter" "vccd2" 16.6212
cap "BGR_lvs_0/XM_bjt_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[2,3]/Collector" "vccd2" 15.3244
cap "vccd2" "BGR_lvs_0/voutb2" 30.2933
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/bias_0p7" "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" 35.4492
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/XM_tail_0/sky130_fd_pr__nfet_01v8_lvt_7MFZYU_0/a_n29_n1281#" "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" 63.3273
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/in_p" "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" 0.147523
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_0/ppair_gate" 0.124677
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/in_n" "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" 0.0661443
cap "BGR_lvs_0/XM_bjt_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[3,3]/Emitter" "vccd2" 1.37183
cap "BGR_lvs_0/XM_bjt_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[3,2]/Collector" "vccd2" 0.478815
cap "vccd2" "BGR_lvs_0/XM_bjt_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[3,3]/Collector" 57.5759
cap "vccd2" "BGR_lvs_0/XM_bjt_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[3,3]/Emitter" 34.8633
cap "BGR_lvs_0/voutb2" "vccd2" 104.831
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_0/XM_ppair_0/w_n220_n1060#" 0.0273311
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/in_n" "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" 0.00112821
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_0/XM_tail_0/sky130_fd_pr__nfet_01v8_lvt_7MFZYU_0/a_n429_n813#" 14.9354
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_0/ppair_gate" 0.121735
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_0/XM_tail_0/sky130_fd_pr__nfet_01v8_lvt_7MFZYU_0/a_n29_n725#" 26.165
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_0/ppair_gate" 0.569085
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_0/XM_tail_0/sky130_fd_pr__nfet_01v8_lvt_7MFZYU_0/a_n429_n813#" 0.024318
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_0/in_n" 0.270894
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_0/in_p" 0.114512
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_0/XM_ppair_0/w_n220_n1060#" 0.128011
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_0/XM_tail_0/sky130_fd_pr__nfet_01v8_lvt_7MFZYU_0/a_n29_n725#" 0.00170393
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_0/first_stage_out" 0.111715
cap "BGR_lvs_0/XM_bjt_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[4,2]/Collector" "vccd2" 0.573598
cap "BGR_lvs_0/XM_bjt_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[4,2]/Emitter" "vccd2" 1.24995
cap "BGR_lvs_0/XM_bjt_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[4,3]/Collector" "vccd2" 57.649
cap "BGR_lvs_0/XM_bjt_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[4,3]/Emitter" "vccd2" 29.7532
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" "BGR_lvs_0/XM_feedbackmir_0/B" 0.0292211
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/ppair_gate" "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" 0.153513
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/XM_ppair_0/sky130_fd_pr__pfet_01v8_lvt_MBDTEX_0/a_n1835_n236#" "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" -3.55271e-15
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/ppair_gate" "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" 0.462043
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" "BGR_lvs_0/XM_feedbackmir_0/B" 0.0213258
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/XM_ppair_0/sky130_fd_pr__pfet_01v8_lvt_MBDTEX_0/a_n1835_n236#" "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" 0.0578506
cap "vccd2" "BGR_lvs_0/XM_bjt_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[5,2]/Collector" 0.265216
cap "vccd2" "BGR_lvs_0/XM_bjt_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[5,3]/Collector" 68.3619
cap "BGR_lvs_0/XM_bjt_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[6,2]/Collector" "BGR_lvs_0/VDD" 0.190088
cap "BGR_lvs_0/XM_bjt_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[6,3]/Collector" "BGR_lvs_0/VDD" 79.3743
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n1003_n1257#" 1.06495
cap "gpio_analog[7]" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n803_n1160#" 0.0100909
cap "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n803_n795#" "gpio_analog[7]" 0.7124
cap "gpio_analog[7]" "BGR_lvs_0/VDD" 0.0597619
cap "io_analog[6]" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n1003_n1257#" 0.303919
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n803_n1160#" 0.00581826
cap "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n803_n795#" "BGR_lvs_0/VDD" 0.230163
cap "gpio_analog[7]" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n1003_n1257#" 2.0983
cap "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n803_n795#" "io_analog[6]" 0.0243276
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n803_n795#" 1.95126
cap "gpio_analog[7]" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n1003_n1257#" 5.035
cap "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n1003_n1257#" "io_analog[6]" 0.729519
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n1003_n1257#" 2.55584
cap "gpio_analog[7]" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n803_n1160#" 0.00973349
cap "gpio_analog[7]" "BGR_lvs_0/VDD" 0.0272715
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n803_n1160#" 0.00564074
cap "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n803_n795#" "io_analog[6]" 0.0243276
cap "gpio_analog[7]" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n803_n795#" 5.81365
cap "BGR_lvs_0/XM_feedbackmir_0/B" "BGR_lvs_0/porst" 0.357809
cap "BGR_lvs_0/vgate" "io_analog[6]" 0.362678
cap "BGR_lvs_0/vgate" "BGR_lvs_0/porst" 2.43284
cap "BGR_lvs_0/XM_feedbackmir_0/B" "BGR_lvs_0/vgate" 1.2332
cap "BGR_lvs_0/XM_feedbackmir2_0/sky130_fd_pr__pfet_01v8_lvt_9UM225_0/a_n674_n612#" "io_analog[6]" 0.0243276
cap "BGR_lvs_0/XM_feedbackmir2_0/sky130_fd_pr__pfet_01v8_lvt_9UM225_0/a_n674_n612#" "BGR_lvs_0/porst" 0.55739
cap "BGR_lvs_0/XM_feedbackmir_0/B" "BGR_lvs_0/XM_feedbackmir2_0/sky130_fd_pr__pfet_01v8_lvt_9UM225_0/a_n674_n612#" 0.166674
cap "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n287_n1160#" "BGR_lvs_0/porst" 1.04855
cap "BGR_lvs_0/XM_feedbackmir_0/B" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n287_n1160#" 0.348351
cap "BGR_lvs_0/vbg" "BGR_lvs_0/porst" 2.86197
cap "BGR_lvs_0/vgate" "BGR_lvs_0/vbg" 0.599793
cap "BGR_lvs_0/XM_feedbackmir_0/B" "BGR_lvs_0/vbg" 0.842166
cap "BGR_lvs_0/vgate" "BGR_lvs_0/porst" 4.02127
cap "BGR_lvs_0/XM_feedbackmir_0/B" "BGR_lvs_0/porst" 0.479121
cap "BGR_lvs_0/XM_feedbackmir_0/B" "BGR_lvs_0/vgate" 2.03404
cap "BGR_lvs_0/vbg" "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__nfet_01v8_Y5UG24_2/a_n50_n207#" 27.466
cap "BGR_lvs_0/vbg" "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_6ZUZ5C_0/a_n271_n1372#" 0.719114
cap "BGR_lvs_0/vbg" "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__cap_mim_m3_1_Y9W37A_0/c1_n2350_n580#" 11.0313
cap "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__nfet_01v8_Y5UG24_2/a_n50_n207#" "BGR_lvs_0/opamp_realcomp3_usefinger_0/vdd" 8.16642
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/vdd" "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__pfet_01v8_TSNZVH_0/a_50_n364#" 0.0445143
cap "BGR_lvs_0/opamp_realcomp3_usefinger_0/vdd" "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__cap_mim_m3_1_Y9W37A_0/c1_n2350_n580#" 21.276
cap "BGR_lvs_0/porst" "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__pfet_01v8_TSNZVH_0/a_50_n364#" 0.0259555
cap "BGR_lvs_0/vbg" "BGR_lvs_0/opamp_realcomp3_usefinger_0/vdd" 0.00768518
cap "BGR_lvs_0/XM_otabias_pmos_0/sky130_fd_pr__pfet_01v8_lvt_MUAP4U_0/a_100_n247#" "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__cap_mim_m3_1_Y9W37A_0/c1_n2350_n580#" -1.31644
cap "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__nfet_01v8_Y5UG24_1/a_50_n181#" "BGR_lvs_0/opamp_realcomp3_usefinger_0/vdd" 0.0082119
cap "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__nfet_01v8_Y5UG24_2/a_n50_n207#" "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_6ZUZ5C_0/a_n271_n1372#" -0.0158466
cap "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__nfet_01v8_Y5UG24_2/a_n50_n207#" "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__cap_mim_m3_1_Y9W37A_0/c1_n2350_n580#" -0.648271
cap "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_6ZUZ5C_0/a_n271_n1372#" "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__cap_mim_m3_1_Y9W37A_0/c1_n2350_n580#" -0.319389
cap "BGR_lvs_0/porst" "BGR_lvs_0/opamp_realcomp3_usefinger_0/vdd" 0.32663
cap "BGR_lvs_0/vbg" "BGR_lvs_0/XM_otabias_pmos_0/sky130_fd_pr__pfet_01v8_lvt_MUAP4U_0/a_100_n247#" 5.2896
cap "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__nfet_01v8_Y5UG24_2/a_n50_n207#" "BGR_lvs_0/opamp_realcomp3_usefinger_0/vdd" 13.8918
cap "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__cap_mim_m3_1_Y9W37A_0/c1_n2350_n580#" "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_6ZUZ5C_0/a_n271_n1372#" -0.895828
cap "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__cap_mim_m3_1_Y9W37A_0/c1_n2350_n580#" "BGR_lvs_0/XM_otabias_nmos_0/sky130_fd_pr__nfet_01v8_lvt_QA4PPD_0/a_n458_n469#" -0.611395
cap "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__cap_mim_m3_1_Y9W37A_0/c1_n2350_n580#" "BGR_lvs_0/opamp_realcomp3_usefinger_0/vdd" 43.5473
cap "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__cap_mim_m3_1_Y9W37A_0/c1_n2350_n580#" "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__nfet_01v8_Y5UG24_2/a_n50_n207#" -1.32687
cap "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__res_high_po_1p41_2TBR6S_0/a_n141_1600#" "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__res_high_po_1p41_2TBR6S_0/a_n271_n2162#" -1.32687
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__res_high_po_1p41_2TBR6S_0/a_n271_n2162#" 43.5473
cap "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__res_high_po_1p41_2TBR6S_0/a_n141_1600#" "BGR_lvs_0/VDD" 13.8918
cap "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__res_high_po_1p41_2TBR6S_0/a_n141_1600#" "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__res_high_po_1p41_2TBR6S_0/a_n271_n2162#" -0.983779
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__res_high_po_1p41_2TBR6S_0/a_n141_1600#" 11.3615
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__res_high_po_1p41_2TBR6S_0/a_n271_n2162#" 32.2872
cap "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[0,0]/Emitter" "BGR_lvs_0/VDD" 0.296335
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[0,0]/Emitter" 2.81749
cap "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[0,0]/Emitter" "BGR_lvs_0/VDD" 2.42601
cap "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[0,1]/Emitter" "BGR_lvs_0/VDD" 2.4103
cap "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[0,2]/Emitter" "BGR_lvs_0/VDD" 3.02359
cap "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[0,3]/Emitter" "BGR_lvs_0/VDD" 77.4583
cap "gpio_analog[7]" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n803_n795#" 3.20471
cap "BGR_lvs_0/XM_feedbackmir_0/B" "BGR_lvs_0/VDD" 153.618
cap "BGR_lvs_0/VDD" "io_analog[6]" 19.1329
cap "gpio_analog[7]" "BGR_lvs_0/VDD" 74.9017
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n803_n430#" 41.1797
cap "BGR_lvs_0/XM_feedbackmir_0/B" "io_analog[6]" 77.2436
cap "gpio_analog[7]" "BGR_lvs_0/XM_feedbackmir_0/B" 176.108
cap "BGR_lvs_0/XM_feedbackmir_0/B" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n803_n430#" 87.7363
cap "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n1003_n892#" "BGR_lvs_0/VDD" 38.4088
cap "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n803_n430#" "io_analog[6]" 18.4565
cap "gpio_analog[7]" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n803_n430#" 57.1238
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n803_n795#" 3.42516
cap "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n1003_n892#" "io_analog[6]" 12.7811
cap "gpio_analog[7]" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n1003_n892#" 55.8111
cap "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n1003_n892#" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n803_n430#" 15.0271
cap "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n803_n795#" "io_analog[6]" 0.0668938
cap "gpio_analog[7]" "BGR_lvs_0/VDD" 181.883
cap "io_analog[6]" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n1003_n892#" 33.2845
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n1003_n892#" 95.008
cap "gpio_analog[7]" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n803_n795#" 110.963
cap "io_analog[6]" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n803_n430#" 6.86231
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n803_n430#" 22.0721
cap "gpio_analog[7]" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n1003_n892#" 138.04
cap "io_analog[6]" "BGR_lvs_0/VDD" 108.608
cap "gpio_analog[7]" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n803_n430#" 38.0158
cap "io_analog[6]" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n803_n795#" 42.5625
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n803_n795#" -10.7462
cap "io_analog[6]" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n287_n430#" 6.57203
cap "BGR_lvs_0/porst" "BGR_lvs_0/XM_feedbackmir_0/B" 261.47
cap "BGR_lvs_0/XM_feedbackmir_0/B" "BGR_lvs_0/XM_feedbackmir2_0/sky130_fd_pr__pfet_01v8_lvt_9UM225_0/a_n674_n612#" 23.1077
cap "BGR_lvs_0/XM_feedbackmir_0/B" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n287_n430#" 1.16726
cap "io_analog[6]" "BGR_lvs_0/XM_feedbackmir_0/B" 180.178
cap "BGR_lvs_0/porst" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n745_n892#" 73.671
cap "io_analog[6]" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n745_n892#" 50.4964
cap "BGR_lvs_0/XM_feedbackmir_0/B" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n745_n892#" 84.8611
cap "BGR_lvs_0/porst" "BGR_lvs_0/XM_feedbackmir2_0/sky130_fd_pr__pfet_01v8_lvt_9UM225_0/a_n674_n612#" 19.1376
cap "BGR_lvs_0/porst" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n287_n430#" 20.1115
cap "io_analog[6]" "BGR_lvs_0/XM_feedbackmir2_0/sky130_fd_pr__pfet_01v8_lvt_9UM225_0/a_n674_n612#" 9.20415
cap "BGR_lvs_0/porst" "BGR_lvs_0/XM_feedbackmir_0/B" 354.044
cap "BGR_lvs_0/XM_feedbackmir_0/B" "BGR_lvs_0/vbg" 218.471
cap "BGR_lvs_0/XM_feedbackmir_0/B" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_803_n892#" 110.264
cap "BGR_lvs_0/porst" "BGR_lvs_0/vbg" 168.681
cap "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__nfet_01v8_Y5UG24_0/a_n210_n293#" "BGR_lvs_0/XM_feedbackmir_0/B" -0.00593648
cap "BGR_lvs_0/porst" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_803_n892#" 228.774
cap "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_803_n892#" "BGR_lvs_0/vbg" 91.3056
cap "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__nfet_01v8_Y5UG24_0/a_n210_n293#" "BGR_lvs_0/vbg" -0.0455533
cap "BGR_lvs_0/XM_otabias_pmos_0/sky130_fd_pr__pfet_01v8_lvt_MUAP4U_0/a_100_n247#" "BGR_lvs_0/vbg" 61.6737
cap "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__cap_mim_m3_1_Y9W37A_0/c1_n2350_n580#" "BGR_lvs_0/vbg" 4.7855
cap "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__pfet_01v8_TSNZVH_0/a_50_n364#" "BGR_lvs_0/porst" 0.130876
cap "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__nfet_01v8_Y5UG24_2/a_n50_n207#" "BGR_lvs_0/vbg" 26.7161
cap "BGR_lvs_0/porst" "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__nfet_01v8_Y5UG24_0/a_n210_n293#" -0.593023
cap "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__nfet_01v8_Y5UG24_0/a_n210_n293#" "BGR_lvs_0/vbg" 72.5595
cap "BGR_lvs_0/XM_otabias_pmos_0/sky130_fd_pr__pfet_01v8_lvt_MUAP4U_0/a_100_n247#" "BGR_lvs_0/VDD" 45.9576
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__cap_mim_m3_1_Y9W37A_0/c1_n2350_n580#" 21.276
cap "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__nfet_01v8_Y5UG24_2/a_n50_n207#" "BGR_lvs_0/VDD" 15.8835
cap "BGR_lvs_0/porst" "BGR_lvs_0/vbg" 23.0284
cap "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__pfet_01v8_TSNZVH_0/a_50_n364#" "BGR_lvs_0/VDD" 0.283694
cap "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__nfet_01v8_Y5UG24_0/a_n210_n293#" "BGR_lvs_0/VDD" 33.0001
cap "BGR_lvs_0/XM_feedbackmir2_0/sky130_fd_pr__pfet_01v8_lvt_9UM225_0/a_n358_386#" "BGR_lvs_0/vbg" 0.966261
cap "BGR_lvs_0/porst" "BGR_lvs_0/VDD" 56.5169
cap "BGR_lvs_0/VDD" "BGR_lvs_0/vbg" 70.333
cap "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__nfet_01v8_Y5UG24_1/a_50_n181#" "BGR_lvs_0/VDD" 0.138333
cap "BGR_lvs_0/XM_feedbackmir2_0/sky130_fd_pr__pfet_01v8_lvt_9UM225_0/a_n416_483#" "BGR_lvs_0/vbg" 0.103324
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_otabias_nmos_0/sky130_fd_pr__nfet_01v8_lvt_QA4PPD_0/a_n458_n469#" 16.9031
cap "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__nfet_01v8_Y5UG24_0/a_n210_n293#" "BGR_lvs_0/VDD" 100.702
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__cap_mim_m3_1_Y9W37A_0/c1_n2350_n580#" 43.5473
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__nfet_01v8_Y5UG24_2/a_n50_n207#" 27.0193
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_pdn_0/m1_5030_n460#" 27.0193
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__res_high_po_1p41_2TBR6S_0/a_n271_n2162#" 131.752
cap "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__res_high_po_1p41_2TBR6S_0/a_n271_n2162#" "BGR_lvs_0/VDD" 120.491
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_pdn_0/m1_5030_n460#" 22.0979
cap "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[1,0]/Collector" "BGR_lvs_0/VDD" 123.701
cap "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[1,0]/Collector" "BGR_lvs_0/VDD" 222.491
cap "BGR_lvs_0/vbe3" "BGR_lvs_0/VDD" 34.9156
cap "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[1,0]/Collector" "BGR_lvs_0/VDD" 222.421
cap "BGR_lvs_0/VDD" "BGR_lvs_0/vbe3" 86.5037
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[1,1]/Collector" 181.09
cap "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[1,2]/Collector" "BGR_lvs_0/VDD" 161.154
cap "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[1,3]/Collector" "BGR_lvs_0/VDD" 72.6421
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_2/a_n200_n5500#" "BGR_lvs_0/Iout0" 100.536
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" "BGR_lvs_0/Iout0" 18.7462
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_2/a_n200_n5500#" "BGR_lvs_0/Iout1" 24.0471
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" "BGR_lvs_0/Iout0" 13.4531
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_0/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" "BGR_lvs_0/Iout1" 4.96425
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_2/a_n200_n5500#" "BGR_lvs_0/Iout0" 73.1504
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_29_n857#" "BGR_lvs_0/Iout1" 27.2351
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_3/a_n200_n5500#" "BGR_lvs_0/Iout1" 149.639
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" "BGR_lvs_0/Iout2" 15.6032
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_4/a_n200_n5500#" "BGR_lvs_0/Iout2" 85.5218
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_4/a_n200_n5500#" "BGR_lvs_0/Iout2" 88.1643
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" "BGR_lvs_0/Iout2" 16.5961
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_5/a_n200_n5500#" "BGR_lvs_0/Iout3" 133.341
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n429_n857#" "BGR_lvs_0/Iout3" 23.8164
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" "BGR_lvs_0/Iout4" 9.6393
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_6/a_n200_n5500#" "BGR_lvs_0/Iout3" 40.5882
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_6/a_n200_n5500#" "BGR_lvs_0/Iout4" 55.4441
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" "BGR_lvs_0/Iout3" 6.6915
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" "BGR_lvs_0/Iout4" 21.4031
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_6/a_n200_n5500#" "BGR_lvs_0/Iout4" 123.723
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_6/XM_output_mirr_3/a_n200_n5500#" "BGR_lvs_0/VDD" 14.829
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_6/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" "BGR_lvs_0/VDD" 2.44624
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_6/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n429_n857#" "BGR_lvs_0/VDD" 28.0289
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_6/XM_output_mirr_4/a_n200_n5500#" "BGR_lvs_0/VDD" 119.981
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_6/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" "BGR_lvs_0/VDD" 19.6721
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_6/XM_output_mirr_5/a_n200_n5500#" "BGR_lvs_0/VDD" 94.8781
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_6/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" "BGR_lvs_0/VDD" 20.4237
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_6/XM_output_mirr_5/a_n200_n5500#" "BGR_lvs_0/VDD" 97.6404
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_6/XM_output_mirr_6/a_n200_n5500#" "BGR_lvs_0/VDD" 116.25
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_6/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n429_n857#" "BGR_lvs_0/VDD" 25.578
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_6/XM_output_mirr_7/a_n200_n5500#" "BGR_lvs_0/VDD" 95.9615
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_6/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" "BGR_lvs_0/VDD" 18.4265
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_6/XM_output_mirr_7/a_n200_n5500#" "BGR_lvs_0/VDD" 113.882
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_6/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_29_n857#" "BGR_lvs_0/VDD" 24.719
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_6/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_n887_n857#" "BGR_lvs_0/VDD" 123.041
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_6/XM_output_mirr_6/sky130_fd_pr__nfet_01v8_lvt_64DJ5N_0/a_487_n857#" "BGR_lvs_0/VDD" 77.5911
cap "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n1003_568#" "BGR_lvs_0/VDD" -22.1732
cap "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n803_665#" "BGR_lvs_0/VDD" -1.55805
cap "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n545_665#" "BGR_lvs_0/VDD" -9.81567
cap "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n1061_665#" "BGR_lvs_0/VDD" -9.81203
cap "BGR_lvs_0/XM_feedbackmir_0/B" "BGR_lvs_0/VDD" -149.735
cap "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n803_1030#" "BGR_lvs_0/VDD" -10.386
cap "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n29_665#" "BGR_lvs_0/VDD" -9.81461
cap "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_487_665#" "BGR_lvs_0/VDD" -9.80968
cap "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n803_665#" "BGR_lvs_0/VDD" -16.6261
cap "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n803_1030#" "BGR_lvs_0/VDD" -12.211
cap "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n1003_568#" "BGR_lvs_0/VDD" -54.2679
cap "BGR_lvs_0/XM_feedbackmir_0/B" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n745_568#" -1.40066
cap "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_n287_1030#" "BGR_lvs_0/XM_feedbackmir_0/B" -5.40417
cap "BGR_lvs_0/XM_feedbackmir_0/B" "BGR_lvs_0/XM_feedbackmir2_0/sky130_fd_pr__pfet_01v8_lvt_9UM225_0/a_n674_n247#" -16.8972
cap "BGR_lvs_0/XM_feedbackmir_0/B" "BGR_lvs_0/XM_feedbackmir_0/sky130_fd_pr__pfet_01v8_lvt_8URDWJ_0/a_1003_665#" -9.80661
cap "BGR_lvs_0/XM_feedbackmir_0/B" "BGR_lvs_0/XM_feedbackmir2_0/sky130_fd_pr__pfet_01v8_lvt_9UM225_0/a_n874_n344#" -58.0234
cap "BGR_lvs_0/XM_feedbackmir_0/B" "BGR_lvs_0/XM_feedbackmir2_0/sky130_fd_pr__pfet_01v8_lvt_9UM225_0/a_n874_n344#" -85.1407
cap "BGR_lvs_0/XM_feedbackmir_0/B" "BGR_lvs_0/vbg" -49.6829
cap "BGR_lvs_0/VDD" "BGR_lvs_0/porst" -197.208
cap "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_S8KB58_0/a_n271_n4801#" "BGR_lvs_0/VDD" -23.2338
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_otabias_nmos_0/sky130_fd_pr__nfet_01v8_lvt_QA4PPD_0/a_n400_n557#" -17.5884
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__cap_mim_m3_1_Y9W37A_0/m3_n2450_n680#" -2.69765
cap "BGR_lvs_0/VDD" "BGR_lvs_0/vbg" -182.43
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_otabias_nmos_0/sky130_fd_pr__nfet_01v8_lvt_QA4PPD_0/a_n458_n469#" -9.00437
cap "BGR_lvs_0/vbg" "BGR_lvs_0/porst" -56.4006
cap "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_S8KB58_0/a_n271_n4801#" "BGR_lvs_0/VDD" -36.5173
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_otabias_nmos_0/sky130_fd_pr__nfet_01v8_lvt_QA4PPD_0/a_n400_n557#" -10.3297
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__cap_mim_m3_1_Y9W37A_0/m3_n2450_n680#" -4.58896
cap "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__cap_mim_m3_1_Y9W37A_0/m3_n2450_n680#" "BGR_lvs_0/VDD" -4.58896
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_otabias_nmos_0/sky130_fd_pr__nfet_01v8_lvt_QA4PPD_0/a_n560_n643#" -28.3551
cap "BGR_lvs_0/XM_pdn_0/sky130_fd_pr__cap_mim_m3_1_Y9W37A_0/m3_n2450_n680#" "BGR_lvs_0/VDD" -3.75311
cap "BGR_lvs_0/VDD" "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_S8KB58_0/a_n271_n4801#" -28.3551
cap "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[2,0]/Collector" "BGR_lvs_0/VDD" -45.3406
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[2,0]/Emitter" -0.728744
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[2,0]/Base" -2.5151
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[2,1]/Emitter" -1.51174
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[2,1]/Base" -3.31286
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[2,0]/Collector" -89.4729
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[2,0]/Base" -5.7922
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[2,0]/Emitter" -3.94405
cap "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[2,2]/Base" "BGR_lvs_0/VDD" -4.11001
cap "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_S8KB58_0/a_n141_4239#" "BGR_lvs_0/VDD" -22.7164
cap "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[2,1]/Emitter" "BGR_lvs_0/VDD" -3.16105
cap "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[2,0]/Collector" "BGR_lvs_0/VDD" -89.4238
cap "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[2,1]/Base" "BGR_lvs_0/VDD" -4.99444
cap "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[2,2]/Emitter" "BGR_lvs_0/VDD" -2.2938
cap "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[2,2]/Emitter" "BGR_lvs_0/VDD" -2.35925
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[2,3]/Emitter" -3.07739
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[2,2]/Base" -4.18406
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[2,1]/Collector" -76.7005
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[2,3]/Base" -4.90837
cap "BGR_lvs_0/sky130_fd_pr__res_high_po_1p41_S8KB58_0/a_n141_4239#" "BGR_lvs_0/VDD" -51.3499
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[2,3]/Emitter" -1.59541
cap "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[2,4]/Base" "BGR_lvs_0/VDD" -5.70613
cap "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[2,2]/Collector" "BGR_lvs_0/VDD" -67.1642
cap "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[2,3]/Base" "BGR_lvs_0/VDD" -3.39893
cap "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[2,4]/Emitter" "BGR_lvs_0/VDD" -3.86015
cap "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[2,4]/Base" "BGR_lvs_0/VDD" -2.60117
cap "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[2,3]/Collector" "BGR_lvs_0/VDD" -23.9499
cap "BGR_lvs_0/XM_bjt_out_0/sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_0[2,4]/Emitter" "BGR_lvs_0/VDD" -0.812644
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_2/a_n200_n5500#" "BGR_lvs_0/Iout0" 198.509
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64S6GM_0/a_n887_n857#" "BGR_lvs_0/Iout0" 62.1562
cap "BGR_lvs_0/Iout0" "BGR_lvs_0/VDD" 274.414
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64S6GM_0/a_n429_n857#" "BGR_lvs_0/Iout0" 59.0362
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64S6GM_0/a_29_n857#" "BGR_lvs_0/Iout0" 14.8496
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_2/a_n200_n5500#" "BGR_lvs_0/Iout1" 46.9013
cap "BGR_lvs_0/Iout0" "BGR_lvs_0/VDD" 194.916
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64S6GM_0/a_29_n857#" "BGR_lvs_0/Iout0" 44.3367
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64S6GM_0/a_n887_n857#" "BGR_lvs_0/Iout1" 42.4274
cap "BGR_lvs_0/Iout1" "BGR_lvs_0/VDD" 64.9721
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_2/a_n200_n5500#" "BGR_lvs_0/Iout0" 152.372
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_1/sky130_fd_pr__nfet_01v8_lvt_64S6GM_0/a_487_n857#" "BGR_lvs_0/Iout0" 70.3416
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64S6GM_0/a_n887_n857#" "BGR_lvs_0/Iout1" 19.7288
cap "BGR_lvs_0/Iout1" "BGR_lvs_0/VDD" 404.358
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64S6GM_0/a_487_n857#" "BGR_lvs_0/Iout1" 70.3416
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64S6GM_0/a_n429_n857#" "BGR_lvs_0/Iout1" 59.0362
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_2/sky130_fd_pr__nfet_01v8_lvt_64S6GM_0/a_29_n857#" "BGR_lvs_0/Iout1" 59.1863
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_3/a_n200_n5500#" "BGR_lvs_0/Iout1" 303.98
cap "BGR_lvs_0/Iout2" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_4/a_n200_n5500#" 172.232
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64S6GM_0/a_n887_n857#" "BGR_lvs_0/Iout2" 62.1562
cap "BGR_lvs_0/Iout2" "BGR_lvs_0/VDD" 231.302
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64S6GM_0/a_n429_n857#" "BGR_lvs_0/Iout2" 59.0362
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64S6GM_0/a_487_n857#" "BGR_lvs_0/Iout2" 70.3416
cap "BGR_lvs_0/Iout2" "BGR_lvs_0/VDD" 238.028
cap "BGR_lvs_0/Iout2" "BGR_lvs_0/Iout3" 0.148396
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_3/sky130_fd_pr__nfet_01v8_lvt_64S6GM_0/a_29_n857#" "BGR_lvs_0/Iout2" 59.1863
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_4/a_n200_n5500#" "BGR_lvs_0/Iout2" 178.65
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64S6GM_0/a_29_n857#" "BGR_lvs_0/Iout3" 59.7674
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64S6GM_0/a_487_n857#" "BGR_lvs_0/Iout3" 28.1815
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64S6GM_0/a_n887_n857#" "BGR_lvs_0/Iout3" 31.4904
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_5/a_n200_n5500#" "BGR_lvs_0/Iout3" 271.332
cap "BGR_lvs_0/Iout3" "BGR_lvs_0/Iout4" 0.67979
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64S6GM_0/a_n429_n857#" "BGR_lvs_0/Iout3" 59.6125
cap "BGR_lvs_0/VDD" "BGR_lvs_0/Iout3" 358.941
cap "BGR_lvs_0/Iout3" "BGR_lvs_0/Iout2" 0.148396
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_4/sky130_fd_pr__nfet_01v8_lvt_64S6GM_0/a_487_n857#" "BGR_lvs_0/Iout3" 57.1968
cap "BGR_lvs_0/Iout4" "BGR_lvs_0/VDD" 143.487
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64S6GM_0/a_n429_n857#" "BGR_lvs_0/Iout4" 55.6037
cap "BGR_lvs_0/Iout3" "BGR_lvs_0/Iout4" 0.67979
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_6/a_n200_n5500#" "BGR_lvs_0/Iout3" 94.9532
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64S6GM_0/a_n887_n857#" "BGR_lvs_0/Iout4" 26.659
cap "BGR_lvs_0/Iout3" "BGR_lvs_0/VDD" 107.9
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_6/a_n200_n5500#" "BGR_lvs_0/Iout4" 115.569
cap "BGR_lvs_0/Iout4" "BGR_lvs_0/VDD" 342.744
cap "BGR_lvs_0/Iout4" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64S6GM_0/a_n429_n857#" 6.72075
cap "BGR_lvs_0/Iout4" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_6/a_n200_n5500#" 266.033
cap "BGR_lvs_0/Iout4" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64S6GM_0/a_29_n857#" 62.503
cap "BGR_lvs_0/Iout4" "BGR_lvs_0/Iout5" 14.2836
cap "BGR_lvs_0/Iout4" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_1/XM_output_mirr_5/sky130_fd_pr__nfet_01v8_lvt_64S6GM_0/a_487_n857#" 89.2529
cap "BGR_lvs_0/Iout4" "BGR_lvs_0/Iout5" 14.2836
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_6/XM_output_mirr_3/a_n200_n5500#" "BGR_lvs_0/VDD" 35.8182
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_6/XM_output_mirr_4/a_n200_n5500#" "BGR_lvs_0/VDD" 167.152
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_6/XM_output_mirr_5/a_n200_n5500#" "BGR_lvs_0/VDD" 167.152
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_6/XM_output_mirr_5/a_n200_n5500#" "BGR_lvs_0/VDD" 167.152
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_6/XM_output_mirr_6/a_n200_n5500#" "BGR_lvs_0/VDD" 167.152
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_6/XM_output_mirr_7/a_n200_n5500#" 167.152
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_6/XM_output_mirr_7/a_n200_n5500#" "BGR_lvs_0/VDD" 167.152
cap "BGR_lvs_0/VDD" "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_6/XM_output_mirr_7/a_n200_n5500#" 167.152
cap "BGR_lvs_0/XM_output_mirr_combined_with_dummy_0/XM_output_mirr_combined_6/XM_output_mirr_7/a_n200_n5500#" "BGR_lvs_0/VDD" 107.455
cap "io_out[13]" "io_in[13]" 0.482756
cap "io_out[13]" "io_in[13]" 0.248198
cap "vccd2" "VGA_routing_0/m1_444321_418953#" 1386.84
cap "vccd2" "VGA_routing_0/m1_444321_418953#" 4257.13
cap "VGA_routing_0/m1_444321_418953#" "vccd2" 4257.13
cap "VGA_routing_0/m1_444321_418953#" "vccd2" 4257.13
cap "vccd2" "VGA_routing_0/m1_444321_418953#" 4257.13
cap "vccd2" "VGA_routing_0/m1_444321_418953#" 4257.13
cap "vccd2" "VGA_routing_0/m1_444321_418953#" 4257.13
cap "VGA_routing_0/m1_444321_418953#" "vccd2" 4257.13
cap "VGA_routing_0/m1_444321_418953#" "vccd2" 3211.33
cap "m3_292774_580566#" "VGA_routing_0/m2_486048_557650#" 23.3338
cap "VGA_routing_0/m2_486048_557650#" "VGA_routing_0/m1_444321_418953#" 77.4731
cap "VGA_routing_0/m2_486048_557650#" "VGA_routing_0/m1_444321_418953#" 17.2456
cap "VGA_routing_0/m1_444321_418953#" "vccd2" 135.087
cap "vccd2" "VGA_routing_0/m2_486048_557650#" 125.258
cap "VGA_routing_0/m2_486048_557650#" "vccd2" 475.938
cap "VGA_routing_0/m1_444321_418953#" "vccd2" 505.349
cap "vccd2" "VGA_routing_0/m2_486048_557650#" 475.938
cap "vccd2" "VGA_routing_0/m1_444321_418953#" 505.349
cap "vccd2" "VGA_routing_0/m1_444321_418953#" 505.349
cap "VGA_routing_0/m2_486048_557650#" "vccd2" 475.938
cap "VGA_routing_0/m1_444321_418953#" "vccd2" 505.349
cap "VGA_routing_0/m2_486048_557650#" "vccd2" 475.938
cap "VGA_routing_0/m1_444321_418953#" "vccd2" 505.349
cap "VGA_routing_0/m2_486048_557650#" "vccd2" 475.938
cap "vccd2" "VGA_routing_0/m2_486048_557650#" 475.938
cap "vccd2" "VGA_routing_0/m1_444321_418953#" 505.349
cap "vccd2" "VGA_routing_0/m2_486048_557650#" 475.938
cap "VGA_routing_0/m1_444321_418953#" "vccd2" 505.349
cap "vccd2" "VGA_routing_0/m1_444321_418953#" 351.665
cap "VGA_routing_0/m2_486048_557650#" "vccd2" 329.232
cap "vccd2" "VGA_routing_0/m2_486048_557650#" 1293.47
cap "VGA_routing_0/m2_486048_557650#" "vccd2" 3977.73
cap "vccd2" "VGA_routing_0/m2_486048_557650#" 3977.73
cap "VGA_routing_0/m2_486048_557650#" "vccd2" 3977.73
cap "vccd2" "VGA_routing_0/m2_486048_557650#" 3977.73
cap "VGA_routing_0/m2_486048_557650#" "vccd2" 3977.73
cap "vccd2" "VGA_routing_0/m2_486048_557650#" 3977.73
cap "VGA_routing_0/m2_486048_557650#" "vccd2" 3977.73
cap "vccd2" "VGA_routing_0/m2_486048_557650#" 2998.22
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 1072.4
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 2143.81
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 2143.81
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 2143.81
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 2143.81
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 2143.81
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 2143.81
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 1684.92
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 613.013
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 2143.81
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 2143.81
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 2143.81
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 2143.81
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 2143.81
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 2143.81
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 2143.81
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 1531.79
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 1499.49
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 2954.55
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 2954.55
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 2954.55
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 2954.55
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 2954.55
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 2954.55
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 2343.65
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 866.373
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 2954.55
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 2954.55
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 2954.55
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 2954.55
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 2954.55
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 2954.55
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 2954.55
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 2132.61
cap "VGA_routing_0/m2_445625_418319#" "VGA_routing_0/m2_445625_418319#" -2.27374e-13
cap "VGA_routing_0/m2_445625_418319#" "VGA_routing_0/m2_445625_418319#" 7.10543e-15
cap "VGA_routing_0/m2_445625_418319#" "vccd1" 55.3039
cap "vccd1" "VGA_routing_0/m2_445625_418319#" 42.466
cap "VGA_routing_0/m2_445625_418319#" "vccd1" 96.2014
cap "VGA_routing_0/m2_445625_418319#" "vccd1" 125.284
cap "vccd1" "VGA_routing_0/m2_445625_418319#" 96.2014
cap "vccd1" "VGA_routing_0/m2_445625_418319#" 125.284
cap "VGA_routing_0/m2_445625_418319#" "vccd1" 125.049
cap "VGA_routing_0/m2_445625_418319#" "vccd1" 96.0211
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 2410.78
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3449.6
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3449.6
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3449.6
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3449.6
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3449.6
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3449.6
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3449.6
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3449.6
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3449.6
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3449.6
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3449.6
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 1942.62
cap "VGA_routing_0/m1_491912_626638#" "vccd2" 2258.01
cap "VGA_routing_0/m1_491912_626638#" "vccd2" 989.72
cap "VGA_routing_0/m2_445625_418319#" "vccd1" 95.033
cap "VGA_routing_0/m2_445625_418319#" "vccd1" 123.762
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 2395.16
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 1940.76
cap "vccd2" "VGA_routing_0/m1_491912_626638#" 2246.88
cap "VGA_routing_0/m1_491912_626638#" "vccd2" 1058.05
cap "VGA_routing_0/m2_445625_418319#" "vccd1" 123.762
cap "VGA_routing_0/m2_445625_418319#" "vccd1" 95.033
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 2395.16
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 1940.76
cap "VGA_routing_0/m1_491912_626638#" "vccd2" 2246.88
cap "VGA_routing_0/m1_491912_626638#" "vccd2" 1058.05
cap "VGA_routing_0/m2_445625_418319#" "vccd1" 95.033
cap "VGA_routing_0/m2_445625_418319#" "vccd1" 123.762
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 2395.16
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 1940.76
cap "vccd2" "VGA_routing_0/m1_491912_626638#" 2246.88
cap "vccd2" "VGA_routing_0/m1_491912_626638#" 1058.05
cap "VGA_routing_0/m2_445625_418319#" "vccd1" 124.432
cap "vccd1" "VGA_routing_0/m2_445625_418319#" 95.5471
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 2395.16
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 1940.76
cap "vccd2" "VGA_routing_0/m1_491912_626638#" 2246.88
cap "vccd2" "VGA_routing_0/m1_491912_626638#" 1058.05
cap "vccd1" "VGA_routing_0/m2_445625_418319#" 125.284
cap "vccd1" "VGA_routing_0/m2_445625_418319#" 96.2014
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 2395.16
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 1940.76
cap "vccd2" "VGA_routing_0/m1_491912_626638#" 2246.88
cap "VGA_routing_0/m1_491912_626638#" "vccd2" 1058.05
cap "VGA_routing_0/m2_445625_418319#" "vccd1" 125.284
cap "VGA_routing_0/m2_445625_418319#" "vccd1" 96.2014
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 2395.16
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 1940.76
cap "VGA_routing_0/m1_491912_626638#" "vccd2" 2246.88
cap "VGA_routing_0/m1_491912_626638#" "vccd2" 1058.05
cap "vccd1" "VGA_routing_0/m2_445625_418319#" 132.32
cap "vccd1" "VGA_routing_0/m2_445625_418319#" 99.1602
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 2395.16
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 3348.17
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 3348.17
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 1940.76
cap "VGA_routing_0/m1_491912_626638#" "vccd2" 2246.88
cap "vccd2" "VGA_routing_0/m1_491912_626638#" 1058.05
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 2068.61
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 2971.29
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 2971.29
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 2971.29
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 2971.29
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 2971.29
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 2971.29
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 2971.29
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 2971.29
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 2971.29
cap "vccd2" "VGA_routing_0/m1_491911_626492#" 2971.29
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 2971.29
cap "VGA_routing_0/m1_491911_626492#" "vccd2" 1665.36
cap "vccd2" "VGA_routing_0/m1_491912_626638#" 1937.02
cap "vccd2" "VGA_routing_0/m1_491912_626638#" 838.57
cap "VGA_routing_0/m4_419918_417788#" "io_analog[6]" 387.406
cap "vssa2" "VCO_0/X3/X6/XC2/m3_n2150_n3100#" 60.3872
cap "VCO_0/X3/X6/XC2/m3_n2150_n3100#" "vdda2" 646.822
cap "vdda2" "VCO_0/X3/X6/XC2/c1_n2050_n3000#" 57.9542
cap "vdda2" "VCO_0/X3/X6/XC2/m3_n2150_n3100#" 904.512
cap "VCO_0/X3/X6/XC2/c1_n2050_n3000#" "vdda2" 31.2953
cap "VCO_0/X3/X6/XC2/m3_n2150_n3100#" "vdda2" 210.398
cap "VCO_0/X3/X3/XR1/a_n573_3040#" "vdda2" 0.0213473
cap "VCO_0/X3/X3/XR1/a_n573_3040#" "vdda2" 105.213
cap "VCO_0/X3/X3/XR1/a_n703_n3602#" "vdda2" 100.415
cap "VCO_0/X3/OUT270" "vdda2" 137.498
cap "VCO_0/X3/X3/VDD" "vdda2" 482.973
cap "vdda2" "VCO_0/X3/X3/VDD" 122.381
cap "vdda2" "VCO_0/X3/X3/XR1/a_n703_n3602#" 2.05348
cap "VCO_0/X3/X3/VDD" "vdda2" 276.886
cap "VCO_0/X3/OUT90" "vdda2" 101.171
cap "VCO_0/X3/X3/XR1/a_n703_n3602#" "vdda2" 54.0462
cap "VCO_0/X3/X2/VDD" "vdda2" 263.334
cap "VCO_0/X3/X3/XR2/a_n703_n3602#" "vdda2" 82.6999
cap "VCO_0/X3/X3/XR2/a_n703_n3602#" "VCO_0/X3/X2/VDD" 15.2261
cap "VCO_0/X3/X2/XR1/a_n703_n3602#" "VCO_0/X3/X2/VDD" 23.8766
cap "VCO_0/GND" "VCO_0/X3/X2/VDD" 119.616
cap "VCO_0/VDD" "VCO_0/GND" 58.9036
cap "VCO_0/VDD" "VCO_0/X3/X2/XR2/a_n703_n3602#" 0.703389
cap "VCO_0/X9/GND" "CTRL5" 63.7456
cap "io_analog[6]" "VGA_routing_0/m4_419918_417788#" 645.9
cap "VCO_0/GND" "VCO_0/X3/X6/XC2/c1_n2050_n3000#" 103.305
cap "VCO_0/GND" "VCO_0/X3/X6/XC2/c1_n2050_n3000#" 69.1087
cap "vdda2" "VCO_0/X3/X6/XC2/c1_n2050_n3000#" 2358.1
cap "vdda2" "VCO_0/X3/X6/XC2/m3_n2150_n3100#" 59.7015
cap "VCO_0/X3/X6/IN" "vdda2" 2247.4
cap "VCO_0/X3/X6/XC2/m3_n2150_n3100#" "vdda2" 185.899
cap "VCO_0/X3/GND" "vdda2" 39.4724
cap "VCO_0/X3/X6/IN" "vdda2" 42.2256
cap "VCO_0/X3/VDD" "vdda2" 0.339617
cap "vdda2" "VCO_0/X3/VDD" 24.4983
cap "vdda2" "VCO_0/X3/VDD" 447.022
cap "vdda2" "VCO_0/X3/X3/XR1/a_n703_n3602#" 70.6318
cap "VCO_0/X3/OUT270" "vdda2" 221.194
cap "VCO_0/X3/OUT90" "vdda2" 234.954
cap "vdda2" "VCO_0/X3/X3/VDD" 259.275
cap "vdda2" "VCO_0/X3/X3/XR1/a_n703_n3602#" 27.8659
cap "VCO_0/X3/X2/VDD" "vdda2" 448.87
cap "VCO_0/X3/X3/XR2/a_n703_n3602#" "vdda2" 86.9887
cap "VCO_0/X3/X2/VDD" "VCO_0/X3/X3/XR2/a_n703_n3602#" 20.6674
cap "VCO_0/X3/X2/XR1/a_n703_n3602#" "VCO_0/X3/X2/VDD" 0.0917385
cap "VCO_0/X3/X2/VDD" "VCO_0/GND" 0.255849
cap "VCO_0/X3/X2/XR2/a_n703_n3602#" "VCO_0/VDD" 0.0333423
cap "VCO_0/VDD" "VCO_0/GND" 0.31291
cap "VCO_0/X9/GND" "VCO_0/X9/ctrll5" 0.616835
cap "VCO_0/X9/ctrll4" "VCO_0/X9/ctrll1" 1.13133
cap "VCO_0/X9/ctrll4" "VCO_0/X9/XM1/a_n73_n100#" 6.54036
cap "VCO_0/X9/GND" "VCO_0/X9/ctrll3" 0.0740888
cap "VCO_0/X9/ctrll5" "VCO_0/X9/ctrll1" 2.17473
cap "VCO_0/X9/ctrll1" "VCO_0/X9/XM1/a_n73_n100#" -1.42749
cap "VCO_0/X9/ctrll5" "VCO_0/X9/XM1/a_n73_n100#" 15.5219
cap "VCO_0/X9/ctrll1" "VCO_0/X9/ctrll3" 0.104384
cap "VCO_0/X9/ctrll3" "VCO_0/X9/XM1/a_n73_n100#" -2.2344
cap "VCO_0/X9/ctrll5" "VCO_0/X9/XC6/c2_n451_n200#" 0.64626
cap "VCO_0/X9/ctrll4" "VCO_0/X9/GND" 0.299397
cap "VCO_0/X9/ctrll2" "VCO_0/X9/XM1/a_n73_n100#" -2.54469
cap "VCO_0/X9/GND" "VCO_0/X9/ctrll4" 31.619
cap "VCO_0/X9/ctrll5" "VCO_0/X9/ctrll1" 80.8131
cap "VCO_0/X9/GND" "VCO_0/X9/ctrll2" -0.736261
cap "VCO_0/X9/XM1/a_n73_n100#" "VCO_0/X9/ctrll4" 0.585832
cap "VCO_0/X9/XM2/a_15_n100#" "VCO_0/X9/ctrll5" 94.4786
cap "VCO_0/X9/XM4/a_111_n100#" "VCO_0/X9/ctrll3" -6.06838
cap "VCO_0/X9/XM2/a_15_n100#" "VCO_0/X9/ctrll1" -11.2165
cap "VCO_0/X9/ctrll5" "VCO_0/X9/XM3/a_n33_n100#" 119.785
cap "VCO_0/X9/XM3/a_n33_n100#" "VCO_0/X9/ctrll1" -3.4523
cap "VCO_0/X9/ctrll5" "VCO_0/X9/ctrll3" 80.6513
cap "VCO_0/X9/ctrll4" "VCO_0/X9/XM4/a_111_n100#" 27.4661
cap "VCO_0/X9/ctrll2" "VCO_0/X9/XM4/a_111_n100#" -3.55433
cap "VCO_0/X9/ctrll1" "VCO_0/X9/ctrll3" 62.4623
cap "VCO_0/X9/XM2/a_15_n100#" "VCO_0/X9/ctrll3" 22.447
cap "VCO_0/X9/ctrll5" "VCO_0/X9/ctrll4" 4.35759
cap "VCO_0/X9/ctrll5" "VCO_0/X9/ctrll2" 68.261
cap "VCO_0/X9/XC6/c2_n451_n200#" "VCO_0/X9/ctrll5" 0.0175591
cap "VCO_0/X9/GND" "VCO_0/X9/ctrll5" 62.3872
cap "VCO_0/X9/XM3/a_n33_n100#" "VCO_0/X9/ctrll3" 20.5251
cap "VCO_0/X9/ctrll1" "VCO_0/X9/ctrll4" 81.8048
cap "VCO_0/X9/ctrll1" "VCO_0/X9/ctrll2" -0.455172
cap "VCO_0/X9/XM2/a_15_n100#" "VCO_0/X9/ctrll4" 30.6654
cap "VCO_0/X9/ctrll5" "VCO_0/X9/XM1/a_n73_n100#" 2.50237
cap "VCO_0/X9/GND" "VCO_0/X9/ctrll1" -4.70259
cap "VCO_0/X9/XM2/a_15_n100#" "VCO_0/X9/ctrll2" 0.00843564
cap "VCO_0/X9/XM3/a_n33_n100#" "VCO_0/X9/ctrll4" 29.9485
cap "VCO_0/X9/XM3/a_n33_n100#" "VCO_0/X9/ctrll2" -5.22203
cap "VCO_0/X9/XM5/a_159_n100#" "VCO_0/X9/ctrll3" -1.36729
cap "VCO_0/X9/ctrll4" "VCO_0/X9/ctrll3" 83.2359
cap "VCO_0/X9/GND" "VCO_0/X9/XM3/a_n33_n100#" -0.495511
cap "VCO_0/X9/ctrll2" "VCO_0/X9/ctrll3" 41.9571
cap "VCO_0/X9/ctrll5" "VCO_0/X9/XM4/a_111_n100#" 88.7286
cap "VCO_0/X9/GND" "VCO_0/X9/ctrll3" 15.5893
cap "VCO_0/X9/ctrll1" "VCO_0/X9/XM4/a_111_n100#" -2.34679
cap "VCO_0/X9/XM1/a_n73_n100#" "VCO_0/X9/ctrll3" 2.07044e-06
cap "VCO_0/X9/ctrll2" "VCO_0/X9/ctrll4" 68.2393
cap "VCO_0/CTRL2" "VCO_0/CTRL3" 68.6404
cap "VCO_0/CTRL2" "VCO_0/X9/GND" 0.965949
cap "VCO_0/CTRL1" "VCO_0/CTRL5" 6.09831
cap "VCO_0/CTRL2" "VCO_0/CTRL4" 10.0386
cap "VCO_0/X9/XM2/a_15_n100#" "VCO_0/CTRL1" -0.161706
cap "VCO_0/X9/XM3/a_n33_n100#" "VCO_0/CTRL1" -0.00220564
cap "VCO_0/CTRL2" "VCO_0/CTRL5" 8.52278
cap "VCO_0/CTRL2" "VCO_0/X9/XM4/a_111_n100#" -0.0314326
cap "VCO_0/CTRL2" "VCO_0/X9/XM2/a_15_n100#" 2.8682
cap "VCO_0/CTRL3" "VCO_0/CTRL1" 28.5429
cap "VCO_0/CTRL1" "VCO_0/X9/GND" -0.147282
cap "VCO_0/X9/XM3/a_n33_n100#" "VCO_0/CTRL2" -1.98038
cap "VCO_0/CTRL4" "VCO_0/CTRL1" 8.01168
cap "VCO_0/CTRL2" "VCO_0/CTRL1" 171.827
cap "VGA_routing_0/m4_419918_417788#" "io_analog[6]" 645.9
cap "VCO_0/GND" "VCO_0/X3/X6/XC2/c1_n2050_n3000#" 52.2047
cap "VCO_0/GND" "VCO_0/X3/X6/XC2/c1_n2050_n3000#" 34.9236
cap "vdda2" "VCO_0/X3/BIAS" 7.24205
cap "vdda2" "VCO_0/X3/X6/XC2/c1_n2050_n3000#" 2492.98
cap "VCO_0/X3/X6/IN" "vdda2" 2369.93
cap "VCO_0/X3/X6/XC2/m3_n2150_n3100#" "vdda2" 144.617
cap "VCO_0/X3/BIAS" "vdda2" 12.3155
cap "vdda2" "VCO_0/X3/GND" 28.1946
cap "vdda2" "VCO_0/X3/X6/XM41/a_495_122#" 42.5638
cap "VCO_0/X3/BIAS" "vdda2" 62.4766
cap "VCO_0/X3/VDD" "vdda2" 0.336766
cap "VCO_0/X3/GND" "vdda2" 337.663
cap "vdda2" "VCO_0/X3/VDD" 26.4412
cap "vdda2" "VCO_0/X3/VDD" 0.1159
cap "VCO_0/X3/BIAS" "vdda2" 9.67032
cap "VCO_0/X3/X6/XM41/a_n707_n274#" "vdda2" 75.6083
cap "vdda2" "VCO_0/X3/VDD" 56.4311
cap "VCO_0/X3/OUT270" "vdda2" 194.288
cap "VCO_0/X3/GND" "vdda2" 400.617
cap "VCO_0/X3/OUT90" "vdda2" 234.954
cap "vdda2" "VCO_0/X3/X3/XR1/a_n703_n3602#" 32.2627
cap "VCO_0/X3/X3/XR2/a_n703_n3602#" "vdda2" 108.551
cap "vdda2" "VCO_0/X3/X3/XR2/a_n703_n3602#" 27.2961
cap "VCO_0/X9/XM2/a_15_n100#" "VCO_0/X9/ctrll5" 3.42232
cap "VCO_0/X9/XM1/a_n73_n100#" "VCO_0/X9/ctrll4" 0.429065
cap "VCO_0/X9/XC6/c2_n451_n200#" "VCO_0/X9/ctrll5" 4.89011
cap "VCO_0/X9/XM1/a_n73_n100#" "VCO_0/X9/ctrll5" 1.65383
cap "VCO_0/X9/XC6/c2_n451_n200#" "VCO_0/X9/ctrll4" -1.13374
cap "VCO_0/X9/ctrll5" "VCO_0/X9/XM3/a_n33_n100#" 26.1316
cap "VCO_0/X9/ctrll3" "VCO_0/X9/XM2/a_15_n100#" -0.132455
cap "VCO_0/X9/XM4/a_111_n100#" "VCO_0/X9/ctrll3" -5.18228
cap "VCO_0/X9/ctrll3" "VCO_0/X9/XM5/a_159_n100#" -12.4502
cap "VCO_0/X9/XM2/a_15_n100#" "VCO_0/X9/ctrll4" 2.13
cap "VCO_0/X9/XM4/a_111_n100#" "VCO_0/X9/ctrll4" 15.208
cap "VCO_0/X9/GND" "VCO_0/X9/ctrll3" -1.59019
cap "VCO_0/X9/XM5/a_159_n100#" "VCO_0/X9/ctrll4" -16.8328
cap "VCO_0/X9/ctrll5" "VCO_0/X9/XM2/a_15_n100#" 9.82973
cap "VCO_0/X9/ctrll5" "VCO_0/X9/XM4/a_111_n100#" 116.146
cap "VCO_0/X9/GND" "VCO_0/X9/ctrll4" 6.88977
cap "VCO_0/X9/ctrll5" "VCO_0/X9/XM5/a_159_n100#" 246.716
cap "VCO_0/X9/ctrll2" "VCO_0/X9/ctrll4" 5.35975
cap "VCO_0/X9/GND" "VCO_0/X9/ctrll5" 35.3764
cap "VCO_0/X9/ctrll2" "VCO_0/X9/ctrll5" 15.8628
cap "VCO_0/X9/ctrll1" "VCO_0/X9/XM4/a_111_n100#" -1.93278
cap "VCO_0/X9/ctrll1" "VCO_0/X9/XM5/a_159_n100#" -6.46766
cap "VCO_0/X9/XM1/a_n73_n100#" "VCO_0/X9/ctrll4" 0.193973
cap "VCO_0/X9/XM1/a_n73_n100#" "VCO_0/X9/ctrll5" 0.562934
cap "VCO_0/X9/ctrll1" "VCO_0/X9/GND" -0.0616028
cap "VCO_0/X9/ctrll3" "VCO_0/X9/ctrll4" 106.728
cap "VCO_0/X9/GND" "VCO_0/X9/XM3/a_n33_n100#" -0.495511
cap "VCO_0/X9/ctrll5" "VCO_0/X9/ctrll3" 28.2261
cap "VCO_0/X9/ctrll5" "VCO_0/X9/ctrll4" 127.916
cap "VCO_0/X9/ctrll5" "VCO_0/X9/XC6/c2_n451_n200#" 0.327132
cap "VCO_0/X9/ctrll2" "VCO_0/X9/XM4/a_111_n100#" -2.92474
cap "VCO_0/X9/ctrll2" "VCO_0/X9/XM5/a_159_n100#" -9.78707
cap "VCO_0/X9/ctrll1" "VCO_0/X9/ctrll4" 4.56784
cap "VCO_0/X9/ctrll2" "VCO_0/X9/GND" -0.207212
cap "VCO_0/X9/ctrll1" "VCO_0/X9/ctrll5" 12.2199
cap "VCO_0/X9/ctrll3" "VCO_0/X9/XM3/a_n33_n100#" -0.349322
cap "VCO_0/X9/XM3/a_n33_n100#" "VCO_0/X9/ctrll4" 4.59171
cap "VCO_0/CTRL5" "VCO_0/CTRL1" 4.66105
cap "VCO_0/CTRL4" "VCO_0/CTRL2" 1.63399
cap "VCO_0/CTRL5" "VCO_0/CTRL2" 6.02634
cap "VCO_0/CTRL4" "VCO_0/CTRL1" 1.40846
cap "VGA_routing_0/m4_419918_417788#" "io_analog[6]" 645.9
cap "VCO_0/bias_calc_0/XM38/a_1891_n100#" "REF" 8.63542
cap "REF" "VCO_0/bias_calc_0/GND" 215.476
cap "REF" "VCO_0/bias_calc_0/XM39/a_n465_n188#" 222.426
cap "REF" "VCO_0/bias_calc_0/w_17930_210#" 17.3166
cap "vssa2" "VCO_0/bias_calc_0/GND" 0.0243059
cap "VCO_0/bias_calc_0/XM39/a_n465_n188#" "vssa2" 0.353454
cap "VCO_0/bias_calc_0/XM38/a_1821_n197#" "VCO_0/bias_calc_0/GND" 6.9181
cap "VCO_0/bias_calc_0/XM39/a_n465_n188#" "VCO_0/bias_calc_0/GND" 45.1924
cap "VCO_0/bias_calc_0/GND" "VCO_0/bias_calc_0/BIASOUT" 76.0545
cap "VCO_0/bias_calc_0/GND" "REF" 0.995098
cap "VCO_0/bias_calc_0/XM39/a_n465_n188#" "REF" 0.506266
cap "VCO_0/bias_calc_0/BIASOUT" "REF" 0.353811
cap "VCO_0/bias_calc_0/w_17930_210#" "REF" 0.180513
cap "VCO_0/bias_calc_0/GND" "VCO_0/bias_calc_0/XM38/a_1821_n197#" 18.6416
cap "VCO_0/bias_calc_0/GND" "VCO_0/bias_calc_0/XM39/a_207_122#" -4.54236
cap "VCO_0/bias_calc_0/GND" "VCO_0/bias_calc_0/BIASOUT" 60.0927
cap "VCO_0/bias_calc_0/BIASOUT" "VCO_0/GND" 0.178063
cap "VCO_0/X3/X6/XC2/c1_n2050_n3000#" "vdda2" 2346.07
cap "VCO_0/X3/GND" "vdda2" 195.45
cap "vdda2" "VCO_0/X3/X6/XC2/m3_n2150_n3100#" 302.027
cap "VCO_0/X3/X6/IN" "vdda2" 2279.15
cap "vdda2" "VCO_0/X3/X6/XM41/a_495_122#" 0.43023
cap "VCO_0/X3/GND" "vdda2" 26.187
cap "vdda2" "VCO_0/X3/X6/XM41/a_495_122#" 59.4174
cap "vdda2" "VCO_0/X3/X6/IN" 434.452
cap "vdda2" "VCO_0/X3/VDD" 274.473
cap "vdda2" "VCO_0/X3/X6/VOP" 82.4211
cap "VCO_0/X3/X6/SUB" "vdda2" 24.7843
cap "VCO_0/X3/X6/SUB" "vdda2" 0.000130533
cap "vdda2" "VCO_0/X3/X6/IN" 0.328175
cap "vdda2" "VCO_0/X3/VDD" 17.0672
cap "VCO_0/X3/X6/SUB" "vdda2" 1.95554
cap "vdda2" "VCO_0/X3/X6/IN" 65.3666
cap "vdda2" "VCO_0/X3/X6/VOP" 0.719035
cap "vdda2" "VCO_0/X3/VDD" 0.34756
cap "vdda2" "VCO_0/X3/X6/VOP" 5.67401
cap "VCO_0/X3/X6/IN" "vdda2" 96.7948
cap "vdda2" "VCO_0/X3/X3/BIAS" 45.6664
cap "vdda2" "VCO_0/X3/X6/VOP" 23.4529
cap "VCO_0/X3/OUT270" "vdda2" 208.816
cap "VCO_0/X3/X6/XM41/a_303_122#" "vdda2" 2.8127
cap "vdda2" "VCO_0/X3/X3/GND" 180.258
cap "vdda2" "VCO_0/X3/X6/XM41/a_207_n188#" 3.45777
cap "VCO_0/X3/VDD" "vdda2" 52.9428
cap "vdda2" "VCO_0/X3/X6/XM41/a_n707_n274#" 77.6517
cap "VCO_0/X3/OUT90" "vdda2" 234.954
cap "vdda2" "VCO_0/X3/X3/XR1/a_n703_n3602#" 32.2627
cap "vdda2" "VCO_0/X3/X2/GND" 108.551
cap "vdda2" "VCO_0/X3/X2/GND" 27.2961
cap "io_analog[6]" "VGA_routing_0/m4_419918_417788#" 645.9
cap "VCO_0/bias_calc_0/XM39/a_n465_n188#" "REF" 210.02
cap "VCO_0/bias_calc_0/XM38/a_1821_n197#" "REF" 9.46799
cap "REF" "VCO_0/bias_calc_0/XM37/a_1821_n197#" 84.1494
cap "REF" "VCO_0/bias_calc_0/w_17930_210#" 81.9039
cap "VCO_0/bias_calc_0/XM38/a_1891_n100#" "REF" 1.99532
cap "REF" "VCO_0/bias_calc_0/XM37/a_1763_n100#" 91.9039
cap "REF" "VCO_0/bias_calc_0/XM38/a_1821_n197#" 1.68758
cap "REF" "VCO_0/bias_calc_0/XM37/a_1763_n100#" 0.0367635
cap "REF" "VCO_0/bias_calc_0/XM37/a_1821_n197#" 2.20247
cap "REF" "VCO_0/bias_calc_0/BIASOUT" 0.0340996
cap "REF" "VCO_0/bias_calc_0/w_17930_210#" 1.05988
cap "VCO_0/bias_calc_0/XM38/a_1821_n197#" "VCO_0/bias_calc_0/GND" 1.4675
cap "VCO_0/bias_calc_0/XM38/a_1821_n197#" "VCO_0/bias_calc_0/GND" 3.56232
cap "VCO_0/GND" "VCO_0/bias_calc_0/XR20/a_n285_n1572#" 0.0209724
cap "vdda2" "VCO_0/X3/X5/XC1/m3_n2150_n3100#" 323.218
cap "vdda2" "VCO_0/X3/X6/XR21/a_n415_n4762#" 57.1841
cap "vdda2" "VCO_0/X3/VOP" 155.857
cap "vdda2" "VCO_0/X3/X6/XR21/a_n415_n4762#" 57.1841
cap "vdda2" "VCO_0/X3/VOP" 157.208
cap "vdda2" "VCO_0/X3/X5/XC1/m3_n2150_n3100#" 323.393
cap "VCO_0/X3/X5/XC1/m3_n2150_n3100#" "vdda2" 1.12198
cap "vdda2" "VCO_0/X3/X6/VDD" 263.24
cap "vdda2" "VCO_0/X3/X6/VOP" 134.057
cap "vdda2" "VCO_0/X3/X6/SUB" 49.6293
cap "vdda2" "VCO_0/X3/X6/SUB" 7.58576e-05
cap "vdda2" "VCO_0/X3/X6/VOP" 6.87142
cap "vdda2" "VCO_0/X3/X6/IN" 70.013
cap "vdda2" "VCO_0/X3/X6/SUB" 2.36918
cap "vdda2" "VCO_0/X3/X6/VOP" 20.9757
cap "vdda2" "VCO_0/X3/X6/VOP" 113.416
cap "VCO_0/X3/X3/BIAS" "vdda2" 93.6844
cap "VCO_0/X3/OUT270" "vdda2" 207.743
cap "VCO_0/X3/X6/IN" "vdda2" 61.9052
cap "VCO_0/X3/X3/SUB" "vdda2" 100.403
cap "VCO_0/X3/X3/XM1/a_n417_n100#" "vdda2" 13.6419
cap "VCO_0/X3/X3/GND" "vdda2" 337.006
cap "VCO_0/X3/X3/GND" "vdda2" 13.3566
cap "VCO_0/X3/X3/XM1/a_n417_n100#" "vdda2" 0.108773
cap "VCO_0/X3/X3/SUB" "vdda2" 1.16642
cap "VCO_0/X3/X3/GND" "vdda2" 0.0589003
cap "VCO_0/X3/X3/BIAS" "vdda2" 8.07367
cap "VCO_0/X3/X3/SUB" "vdda2" 0.0287145
cap "VCO_0/X3/X3/XM1/a_n417_n100#" "vdda2" 0.451372
cap "VCO_0/X3/X3/BIAS" "vdda2" 3.47466
cap "vdda2" "VCO_0/X3/OUT90" 234.954
cap "vdda2" "VCO_0/X3/X3/BIAS" 50.7721
cap "vdda2" "VCO_0/X3/X3/XM1/a_n417_n100#" 4.40623
cap "vdda2" "VCO_0/X3/X3/GND" 206.166
cap "vdda2" "VCO_0/X3/X3/SUB" 35.1406
cap "vdda2" "VCO_0/X3/X2/XM4/a_n321_n100#" 2.85396e-06
cap "vdda2" "VCO_0/X3/X2/XM4/a_n369_122#" 0.0015256
cap "vdda2" "VCO_0/X3/X2/XM4/a_n417_n100#" 3.34393e-06
cap "VCO_0/X3/X2/BIAS" "vdda2" 138.885
cap "VCO_0/X3/X2/XM1/a_n417_n100#" "vdda2" 9.85837
cap "VCO_0/X3/X2/GND" "vdda2" 539.631
cap "vdda2" "VCO_0/X3/X2/XM4/a_n509_n100#" 3.34602e-06
cap "vdda2" "VCO_0/X3/X2/XM4/a_n509_n100#" 7.9064e-08
cap "vdda2" "VCO_0/X3/X2/XM4/a_n321_n100#" 7.05464e-08
cap "VCO_0/X3/X2/XM1/a_n417_n100#" "vdda2" 0.307672
cap "vdda2" "VCO_0/X3/X2/XM4/a_n417_n100#" 7.9064e-08
cap "VCO_0/X3/X2/BIAS" "vdda2" 6.73766
cap "VCO_0/X3/X2/GND" "vdda2" 40.6791
cap "vdda2" "VCO_0/X3/X2/XM4/a_n369_122#" 0.000248087
cap "io_analog[6]" "VGA_routing_0/m4_419918_417788#" 645.9
cap "VCO_0/bias_calc_0/XM38/a_1821_n197#" "REF" 9.46024
cap "VCO_0/bias_calc_0/XM37/a_1763_n100#" "REF" 92.9591
cap "VCO_0/bias_calc_0/XM37/a_1891_n100#" "REF" 212.097
cap "VCO_0/bias_calc_0/w_17930_210#" "REF" 81.2432
cap "VCO_0/bias_calc_0/XM38/a_1891_n100#" "REF" 2.22515
cap "VCO_0/bias_calc_0/VCTRL" "REF" 84.1256
cap "REF" "VCO_0/bias_calc_0/XM38/a_1891_n100#" 0.0346559
cap "REF" "VCO_0/bias_calc_0/VCTRL" 2.18685
cap "REF" "VCO_0/bias_calc_0/XM38/a_1821_n197#" 1.68882
cap "REF" "VCO_0/bias_calc_0/XM37/a_1763_n100#" 0.0333613
cap "REF" "VCO_0/bias_calc_0/w_17930_210#" 1.06444
cap "vdda2" "VCO_0/X3/X5/XC1/m3_n2150_n3100#" 262.945
cap "vdda2" "VCO_0/X3/X5/XC1/c1_n2050_n3000#" 2126.61
cap "VCO_0/X3/X5/XC1/c1_n2050_n3000#" "vdda2" 2025.83
cap "vdda2" "VCO_0/X3/X5/XC1/m3_n2150_n3100#" 375.797
cap "vdda2" "VCO_0/X3/VOP" 12.9139
cap "VCO_0/X3/X5/XC1/c1_n2050_n3000#" "vdda2" 37.2258
cap "VCO_0/X3/X5/XC1/m3_n2150_n3100#" "vdda2" 41.7901
cap "VCO_0/X3/X5/XM26/a_63_n100#" "vdda2" 309.082
cap "vdda2" "VCO_0/X3/X5/IN4" 2.86449
cap "vdda2" "VCO_0/X3/X5/XM26/a_159_n100#" 2.47096
cap "vdda2" "VCO_0/X3/X6/SUB" 5.66347
cap "vdda2" "VCO_0/X3/X6/VOP" 64.9819
cap "VCO_0/X3/X5/IN4" "vdda2" 1.40929
cap "vdda2" "VCO_0/X3/X6/SUB" 2.67776
cap "VCO_0/X3/X5/XM26/a_159_n100#" "vdda2" 8.43843
cap "VCO_0/X3/X6/VOP" "vdda2" 2.91674
cap "VCO_0/X3/X5/XM26/a_63_n100#" "vdda2" 4.14875
cap "VCO_0/X3/X5/IN4" "vdda2" 3.38941
cap "VCO_0/X3/m3_19820_13570#" "vdda2" 47.65
cap "VCO_0/X3/X5/XM26/a_159_n100#" "vdda2" 0.0723078
cap "vdda2" "VCO_0/X3/X6/SUB" 2.11183
cap "VCO_0/X3/X5/XM26/a_63_n100#" "vdda2" 2.23698
cap "VCO_0/X3/m3_19820_13570#" "vdda2" 61.9052
cap "vdda2" "VCO_0/X3/X5/IN3" 0.649858
cap "vdda2" "VCO_0/X3/X3/GND" 73.1934
cap "vdda2" "VCO_0/X3/X5/XM26/a_63_n100#" 25.8011
cap "vdda2" "VCO_0/X3/X3/SUB" 144.579
cap "vdda2" "VCO_0/X3/X3/XM1/a_n417_n100#" 75.6445
cap "vdda2" "VCO_0/X3/X3/INB" 6.41017
cap "vdda2" "VCO_0/X3/X6/VOP" 8.7294
cap "vdda2" "VCO_0/X3/X3/BIAS" 27.3653
cap "vdda2" "VCO_0/X3/X5/IN4" 790.748
cap "vdda2" "VCO_0/X3/X5/XM26/a_159_n100#" 28.3598
cap "vdda2" "VCO_0/X3/X3/INA" 0.718462
cap "vdda2" "VCO_0/X3/X3/XM1/a_n417_n100#" 1.56644
cap "vdda2" "VCO_0/X3/X3/SUB" 3.86104
cap "vdda2" "VCO_0/X3/X3/GND" 0.459908
cap "vdda2" "VCO_0/X3/X3/BIAS" 22.1318
cap "vdda2" "VCO_0/X3/X3/INB" 3.0131
cap "vdda2" "VCO_0/X3/X3/OUTA" 0.472524
cap "vdda2" "VCO_0/X3/X3/INA" 0.111707
cap "vdda2" "VCO_0/X3/X3/SUB" 0.0961893
cap "vdda2" "VCO_0/X3/X3/BIAS" 9.38576
cap "vdda2" "VCO_0/X3/X3/XM1/a_n417_n100#" 4.61262
cap "vdda2" "VCO_0/X3/X3/OUTB" 1.04491
cap "vdda2" "VCO_0/X3/X3/GND" 27.0632
cap "vdda2" "VCO_0/X3/X3/INA" 1.39941
cap "vdda2" "VCO_0/X3/X3/OUTA" 0.0933125
cap "vdda2" "VCO_0/X3/X3/BIAS" 14.085
cap "vdda2" "VCO_0/X3/X3/XM1/a_n417_n100#" 27.5331
cap "vdda2" "VCO_0/X3/X3/OUTA" 613.191
cap "vdda2" "VCO_0/X3/X3/SUB" 56.2432
cap "vdda2" "VCO_0/X3/X3/GND" 66.4148
cap "vdda2" "VCO_0/X3/X3/INA" 3.65931
cap "VCO_0/X3/X2/XM4/a_n225_n100#" "vdda2" 3.34393e-06
cap "VCO_0/X3/X2/XM4/a_255_n100#" "vdda2" 3.34602e-06
cap "VCO_0/X3/X2/XM4/a_207_122#" "vdda2" 0.00152414
cap "VCO_0/X3/X2/XM4/a_n33_n100#" "vdda2" 3.34393e-06
cap "VCO_0/X3/X2/XM4/a_447_n100#" "vdda2" 3.34393e-06
cap "VCO_0/X3/X4/OUTB" "vdda2" 660.37
cap "VCO_0/X3/X2/XM3/a_n33_n188#" "vdda2" 0.188361
cap "VCO_0/X3/X3/OUTA" "vdda2" 103.917
cap "VCO_0/X3/X2/XM3/a_15_n100#" "vdda2" 3.34602e-06
cap "VCO_0/X3/I2B" "vdda2" 5.45223
cap "VCO_0/X3/X2/XM4/a_n321_n100#" "vdda2" 4.92062e-07
cap "VCO_0/X3/X2/XM4/a_159_n100#" "vdda2" 3.34393e-06
cap "VCO_0/X3/X2/XM4/a_15_122#" "vdda2" 0.0015256
cap "VCO_0/X3/X4/SUB" "vdda2" 208.721
cap "VCO_0/X3/X2/BIAS" "vdda2" 21.8296
cap "VCO_0/X3/X2/XM4/a_n129_n100#" "vdda2" 3.34602e-06
cap "VCO_0/X3/X2/XM4/a_351_n100#" "vdda2" 3.34393e-06
cap "VCO_0/X3/X2/XM4/a_399_122#" "vdda2" 0.0015256
cap "VCO_0/X3/X2/GND" "vdda2" 2.07361e-05
cap "VCO_0/X3/X2/XM4/a_63_n100#" "vdda2" 3.34602e-06
cap "VCO_0/X3/X2/XM3/a_n73_n100#" "vdda2" 3.34602e-06
cap "VCO_0/X3/X2/XM1/a_n417_n100#" "vdda2" 55.9973
cap "VCO_0/X3/X2/XM4/a_n177_122#" "vdda2" 0.00152487
cap "VCO_0/X3/X2/XM4/a_n129_n100#" "vdda2" 7.9064e-08
cap "vdda2" "VCO_0/X3/X2/XM1/a_n417_n100#" 3.24224
cap "vdda2" "VCO_0/X3/X2/XM4/a_n177_122#" 0.000248087
cap "VCO_0/X3/X2/XM4/a_63_n100#" "vdda2" 7.9064e-08
cap "vdda2" "VCO_0/X3/X2/XM4/a_207_122#" 0.000248087
cap "vdda2" "VCO_0/X3/X2/XM4/a_399_122#" 0.000248087
cap "VCO_0/X3/I2B" "vdda2" 2.22387
cap "VCO_0/X3/X2/XM4/a_255_n100#" "vdda2" 7.9064e-08
cap "vdda2" "VCO_0/X3/X2/XM3/a_n73_n100#" 7.1728e-08
cap "VCO_0/X3/X2/XM4/a_n225_n100#" "vdda2" 7.9064e-08
cap "vdda2" "VCO_0/X3/X2/XM3/a_n33_n188#" 0.019309
cap "VCO_0/X3/X2/GND" "vdda2" 2.67064e-06
cap "VCO_0/X3/X2/XM4/a_n33_n100#" "vdda2" 7.9064e-08
cap "vdda2" "VCO_0/X3/X2/XM4/a_15_122#" 0.000248087
cap "VCO_0/X3/X4/OUTB" "vdda2" 0.752747
cap "VCO_0/X3/X2/XM4/a_159_n100#" "vdda2" 7.9064e-08
cap "vdda2" "VCO_0/X3/X2/XM4/a_447_n100#" 8.27095e-08
cap "VCO_0/X3/X2/XM4/a_n321_n100#" "vdda2" 8.51761e-09
cap "vdda2" "VCO_0/X3/X2/BIAS" 18.3469
cap "VCO_0/X3/X4/SUB" "vdda2" 49.6138
cap "VCO_0/X3/X2/XM4/a_351_n100#" "vdda2" 7.9064e-08
cap "vdda2" "VCO_0/X3/X2/XM3/a_15_n100#" 7.1728e-08
cap "io_analog[6]" "VGA_routing_0/m4_419918_417788#" 552.571
cap "VCO_0/bias_calc_0/XM38/a_611_n100#" "REF" 1.71475
cap "VCO_0/bias_calc_0/VCTRL" "VCO_0/bias_calc_0/XM36/a_931_n100#" 0.0349523
cap "VCO_0/bias_calc_0/XM37/a_611_n100#" "REF" 161.414
cap "VCO_0/bias_calc_0/VCTRL" "VCO_0/bias_calc_0/XM38/a_611_n100#" 0.000382837
cap "VCO_0/bias_calc_0/VCTRL" "VCO_0/bias_calc_0/XM36/a_861_n197#" 0.0876228
cap "VCO_0/bias_calc_0/XM37/a_611_n100#" "VCO_0/bias_calc_0/VCTRL" 1.30276
cap "VCO_0/bias_calc_0/XM38/a_669_n197#" "REF" 7.51153
cap "VCO_0/bias_calc_0/XM36/a_803_n100#" "REF" 121.579
cap "VCO_0/bias_calc_0/w_17100_7240#" "REF" 77.5039
cap "VCO_0/bias_calc_0/VCTRL" "REF" 67.9755
cap "VCO_0/bias_calc_0/VCTRL" "VCO_0/bias_calc_0/XM36/a_803_n100#" 57.224
cap "VCO_0/bias_calc_0/VCTRL" "VCO_0/bias_calc_0/w_17100_7240#" 26.5003
cap "VCO_0/bias_calc_0/XM36/a_803_n100#" "REF" 0.0254999
cap "VCO_0/bias_calc_0/VCTRL" "VCO_0/bias_calc_0/XM38/a_611_n100#" 5.14253e-05
cap "VCO_0/bias_calc_0/VCTRL" "VCO_0/bias_calc_0/w_17100_7240#" 2.57039
cap "VCO_0/bias_calc_0/VCTRL" "REF" 1.71822
cap "VCO_0/bias_calc_0/XM38/a_669_n197#" "REF" 1.32351
cap "VCO_0/bias_calc_0/XM38/a_611_n100#" "REF" 0.0267118
cap "VCO_0/bias_calc_0/w_17100_7240#" "REF" 1.34465
cap "vdda2" "VCO_0/X3/X5/XC1/c1_n2050_n3000#" 2492.98
cap "vdda2" "VCO_0/X3/X5/XC1/m3_n2150_n3100#" 137.129
cap "vdda2" "VCO_0/X3/X5/XC1/c1_n2050_n3000#" 2373.41
cap "vdda2" "VCO_0/X3/X5/XC1/m3_n2150_n3100#" 40.5115
cap "vdda2" "VCO_0/X3/X5/XC1/c1_n2050_n3000#" 44.1662
cap "VCO_0/X3/X5/SUB" "vdda2" 8.13111
cap "VCO_0/X3/X5/VDD" "vdda2" 26.5997
cap "VCO_0/X3/X5/IN3" "vdda2" 2.86449
cap "VCO_0/X3/X5/XM26/a_159_n100#" "vdda2" 4.84388
cap "VCO_0/X3/X5/IN2" "vdda2" 2.78528
cap "VCO_0/X3/X5/SUB" "vdda2" 3.71836
cap "VCO_0/X3/X5/SUB" "vdda2" 10.6814
cap "vdda2" "VCO_0/X3/X5/VDD" 9.10155
cap "VCO_0/X3/X5/XM26/a_159_n100#" "vdda2" 0.157649
cap "VCO_0/X3/X5/VDD" "vdda2" 1.06698
cap "VCO_0/X3/X5/XM26/a_159_n100#" "vdda2" 22.9567
cap "vdda2" "VCO_0/X3/X5/IN3" 1.45036
cap "VCO_0/X3/m3_19820_13570#" "vdda2" 24.7574
cap "VCO_0/X3/X5/IN3" "vdda2" 7.80015
cap "vdda2" "VCO_0/X3/X5/IN2" 1.4243
cap "VCO_0/X3/X5/IN2" "vdda2" 7.16588
cap "vdda2" "VCO_0/X3/X5/IN2" 87.3849
cap "VCO_0/X3/m3_19820_13570#" "vdda2" 292.084
cap "vdda2" "VCO_0/X3/X5/IN3" 79.8073
cap "VCO_0/X3/I2B" "vdda2" 4.14028
cap "vdda2" "VCO_0/X3/X3/INA" 4.53195
cap "VCO_0/X3/I4B" "vdda2" 3.40392
cap "vdda2" "VCO_0/X3/X1/INB" 16.4561
cap "VCO_0/X3/X5/XM26/a_159_n100#" "vdda2" 53.7344
cap "VCO_0/X3/I4A" "vdda2" 3.91243
cap "vdda2" "VCO_0/X3/X3/INB" 10.4625
cap "vdda2" "VCO_0/X3/X5/VDD" 40.1401
cap "vdda2" "VCO_0/X3/X5/IN4" 41.7663
cap "vdda2" "VCO_0/X3/X1/XM2/a_n73_n100#" 7.36267
cap "vdda2" "VCO_0/X3/X1/INA" 3.45258
cap "VCO_0/X3/X5/IN1" "vdda2" 282.855
cap "VCO_0/X3/I2A" "vdda2" 3.02324
cap "VCO_0/X3/X5/SUB" "vdda2" 62.3142
cap "vdda2" "VCO_0/X3/X1/XM2/a_n73_n100#" 0.874975
cap "vdda2" "VCO_0/X3/X3/OUTA" 11.0224
cap "vdda2" "VCO_0/X3/X1/INA" 1.07065
cap "VCO_0/X3/I2B" "vdda2" 1.52174
cap "vdda2" "VCO_0/X3/X3/INA" 1.5296
cap "vdda2" "VCO_0/X3/X3/INB" 6.0639
cap "VCO_0/X3/I4A" "vdda2" 1.21904
cap "vdda2" "VCO_0/X3/X1/INB" 8.58368
cap "vdda2" "VCO_0/X3/X1/XM2/a_n73_n100#" 0.378082
cap "vdda2" "VCO_0/X3/X3/OUTA" 2.50628
cap "vdda2" "VCO_0/X3/X1/INA" 4.96297
cap "vdda2" "VCO_0/X3/X1/OUTA" 11.071
cap "VCO_0/X3/X3/SUB" "vdda2" 0.624356
cap "vdda2" "VCO_0/X3/X3/INA" 2.70427
cap "VCO_0/X3/I2A" "vdda2" 0.714527
cap "vdda2" "VCO_0/X3/X1/OUTB" 1.04491
cap "VCO_0/X3/I4B" "vdda2" 1.01723
cap "vdda2" "VCO_0/X3/X1/OUTA" 2.51908
cap "VCO_0/X3/X3/SUB" "vdda2" 0.0223203
cap "VCO_0/X3/X3/SUB" "vdda2" 17.8607
cap "vdda2" "VCO_0/X3/X3/INB" 1.09749
cap "vdda2" "VCO_0/X3/I4A" 33.495
cap "vdda2" "VCO_0/X3/X3/INA" 39.8597
cap "vdda2" "VCO_0/X3/I1B" 35.1747
cap "vdda2" "VCO_0/X3/X1/OUTA" 203.527
cap "vdda2" "VCO_0/X3/X4/OUTB" 153.004
cap "vdda2" "VCO_0/X3/I2A" 30.6955
cap "VCO_0/X3/I2B" "vdda2" 45.0997
cap "vdda2" "VCO_0/X3/I4B" 43.0993
cap "vdda2" "VCO_0/X3/X1/INA" 16.1689
cap "vdda2" "VCO_0/X3/X1/XM2/a_n73_n100#" 3.94004
cap "vdda2" "VCO_0/X3/X3/OUTA" 33.7261
cap "VCO_0/X3/X4/OUTB" "vdda2" 816.212
cap "VCO_0/X3/I1A" "vdda2" 3.84776
cap "vdda2" "VCO_0/X3/X4/INB" 76.6968
cap "VCO_0/X3/X4/XM3/a_n73_n100#" "vdda2" 3.34602e-06
cap "VCO_0/X3/I2A" "vdda2" 57.6401
cap "VCO_0/X3/I1B" "vdda2" 57.6401
cap "vdda2" "VCO_0/X3/X3/XM3/a_n33_n188#" 57.6401
cap "VCO_0/X3/X4/XM2/a_n73_n100#" "vdda2" 5.95615
cap "vdda2" "VCO_0/X3/X4/XM3/a_n33_n188#" 0.202545
cap "VCO_0/X3/X1/OUTA" "vdda2" 42.1607
cap "vdda2" "VCO_0/X3/X2/XM3/a_n33_n188#" 0.0141836
cap "vdda2" "VCO_0/X3/I2B" 71.3428
cap "vdda2" "VCO_0/X3/X4/XM3/a_15_n100#" 3.34602e-06
cap "VCO_0/X3/X4/SUB" "vdda2" 46.9592
cap "VCO_0/X3/I3B" "vdda2" 3.84776
cap "VCO_0/X3/I4A" "vdda2" 57.6401
cap "vdda2" "VCO_0/X3/X3/OUTA" 8.29453
cap "vdda2" "VCO_0/X3/X4/OUTB" 0.752747
cap "vdda2" "VCO_0/X3/X4/XM2/a_n73_n100#" 0.611847
cap "vdda2" "VCO_0/X3/X2/XM3/a_n33_n188#" 0.00125825
cap "VCO_0/X3/X4/XM3/a_n73_n100#" "vdda2" 7.1728e-08
cap "vdda2" "VCO_0/X3/X4/SUB" 1.58092
cap "vdda2" "VCO_0/X3/I2B" 1.01521
cap "vdda2" "VCO_0/X3/X4/INB" 3.24791
cap "VCO_0/X3/X4/XM3/a_15_n100#" "vdda2" 7.1728e-08
cap "vdda2" "VCO_0/X3/X4/XM3/a_n33_n188#" 0.0205672
cap "REF" "VCO_0/bias_calc_0/VCTRL" -1.77636e-15
cap "VCO_0/bias_calc_0/BIAS2V" "VCO_0/bias_calc_0/VCTRL" 0.157064
cap "REF" "VCO_0/bias_calc_0/XM36/a_803_n100#" 415.747
cap "VCO_0/bias_calc_0/VDD" "VCO_0/bias_calc_0/VCTRL" 0.699439
cap "VCO_0/bias_calc_0/XM36/a_803_n100#" "VCO_0/bias_calc_0/BIAS2V" -0.0553194
cap "VCO_0/bias_calc_0/XM36/a_803_n100#" "VCO_0/bias_calc_0/VCTRL" 0.0240786
cap "VCO_0/bias_calc_0/BIAS2V" "VCO_0/bias_calc_0/XM37/a_n925_n100#" -0.017135
cap "REF" "VCO_0/bias_calc_0/BIAS2V" 164.712
cap "REF" "VCO_0/bias_calc_0/VDD" 293.983
cap "VCO_0/bias_calc_0/VDD" "VCO_0/bias_calc_0/BIAS2V" -0.0177673
cap "VCO_0/bias_calc_0/BIAS2V" "REF" 2.33205
cap "REF" "VCO_0/bias_calc_0/VDD" 3.04648
cap "VCO_0/bias_calc_0/XM36/a_803_n100#" "REF" 0.360046
cap "VCO_0/X3/m2_20210_20620#" "vdda2" 38.4743
cap "VCO_0/X3/X5/XC1/c1_n2050_n3000#" "vdda2" 2577.62
cap "VCO_0/X3/m2_20210_20620#" "vdda2" 159.69
cap "VCO_0/X3/X5/XC1/c1_n2050_n3000#" "vdda2" 2497.17
cap "VCO_0/X3/m2_20210_20620#" "vdda2" 36.1709
cap "VCO_0/X3/X5/XC1/c1_n2050_n3000#" "vdda2" 29.7175
cap "vdda2" "VCO_0/X3/X5/IN1" 2.86449
cap "vdda2" "VCO_0/X3/X5/VDD" 69.095
cap "vdda2" "VCO_0/X3/X5/XR18/a_n285_4200#" 867.475
cap "vdda2" "VCO_0/X3/X5/IN2" 0.0792087
cap "vdda2" "VCO_0/X3/SUB" 6.51197
cap "vdda2" "VCO_0/X3/SUB" 5.84567
cap "VCO_0/X3/X5/IN1" "vdda2" 17.7845
cap "vdda2" "VCO_0/X3/X5/IN2" 0.0584082
cap "VCO_0/X3/X5/XR18/a_n285_4200#" "vdda2" 2.22035
cap "vdda2" "VCO_0/X3/X5/VDD" 3.58486
cap "vdda2" "VCO_0/X3/SUB" 3.43731
cap "VCO_0/X3/X5/XR18/a_n285_4200#" "vdda2" 55.7557
cap "VCO_0/X3/X5/IN1" "vdda2" 1.45036
cap "vdda2" "VCO_0/X3/X5/IN2" 0.0260685
cap "vdda2" "VCO_0/X3/X5/VDD" 0.606484
cap "VCO_0/X3/X1/XM2/a_n73_n100#" "vdda2" 81.9237
cap "VCO_0/X3/SUB" "vdda2" 126.854
cap "VCO_0/X3/X5/IN2" "vdda2" 0.680511
cap "VCO_0/X3/X1/GND" "vdda2" 100.358
cap "VCO_0/X3/X5/IN1" "vdda2" 608.855
cap "VCO_0/X3/X1/BIAS" "vdda2" 36.1947
cap "VCO_0/X3/X5/VDD" "vdda2" 24.0861
cap "VCO_0/X3/X5/XR18/a_n285_4200#" "vdda2" 104.58
cap "VCO_0/X3/X1/BIAS" "vdda2" 29.8284
cap "VCO_0/X3/X1/XM2/a_n73_n100#" "vdda2" 1.29713
cap "VCO_0/X3/X1/GND" "vdda2" 0.518808
cap "VCO_0/X3/SUB" "vdda2" 0.0995485
cap "VCO_0/X3/X1/XM2/a_n73_n100#" "vdda2" 4.18901
cap "VCO_0/X3/X1/GND" "vdda2" 36.5765
cap "VCO_0/X3/SUB" "vdda2" 4.32264
cap "VCO_0/X3/X1/BIAS" "vdda2" 12.6951
cap "VCO_0/X3/X1/GND" "vdda2" 90.8086
cap "VCO_0/X3/X1/OUTA" "vdda2" 489.309
cap "VCO_0/X3/X1/BIAS" "vdda2" 18.5616
cap "VCO_0/X3/X1/XM2/a_n73_n100#" "vdda2" 27.9993
cap "vdda2" "VCO_0/X3/X3/SUB" 48.032
cap "VCO_0/X3/X4/XM4/a_n509_n100#" "vdda2" 3.34602e-06
cap "VCO_0/X3/X4/XM4/a_351_n100#" "vdda2" 3.34393e-06
cap "vdda2" "VCO_0/X3/X4/XM4/a_n321_n100#" 3.34602e-06
cap "VCO_0/X3/X4/XM4/a_399_122#" "vdda2" 0.0015256
cap "vdda2" "VCO_0/X3/X4/XM2/a_n73_n100#" 59.8995
cap "vdda2" "VCO_0/X3/X4/XM4/a_159_n100#" 3.34393e-06
cap "VCO_0/X3/X4/GND" "vdda2" 2.07361e-05
cap "VCO_0/X3/X4/GND" "vdda2" 212.253
cap "vdda2" "VCO_0/X3/X4/XM4/a_n33_n100#" 3.34393e-06
cap "vdda2" "VCO_0/X3/X4/XM4/a_15_122#" 0.0015256
cap "vdda2" "VCO_0/X3/X4/XM4/a_n225_n100#" 3.34393e-06
cap "VCO_0/X3/X4/XM4/a_447_n100#" "vdda2" 3.34393e-06
cap "vdda2" "VCO_0/X3/X4/XM4/a_n369_122#" 0.0015256
cap "VCO_0/X3/X4/BIAS" "vdda2" 28.8377
cap "vdda2" "VCO_0/X3/X4/XM4/a_255_n100#" 3.34602e-06
cap "vdda2" "VCO_0/X3/X4/XM4/a_n417_n100#" 3.34393e-06
cap "vdda2" "VCO_0/X3/X4/OUTB" 436.339
cap "vdda2" "VCO_0/X3/X1/OUTA" 70.0714
cap "vdda2" "VCO_0/X3/X4/XM4/a_63_n100#" 3.34602e-06
cap "vdda2" "VCO_0/X3/X4/XM4/a_207_122#" 0.00152414
cap "vdda2" "VCO_0/X3/X4/XM4/a_n129_n100#" 3.34602e-06
cap "vdda2" "VCO_0/X3/X4/XM4/a_n177_122#" 0.00152487
cap "VCO_0/X3/X4/XM4/a_255_n100#" "vdda2" 7.9064e-08
cap "VCO_0/X3/X4/XM4/a_n321_n100#" "vdda2" 7.9064e-08
cap "VCO_0/X3/X4/GND" "vdda2" 2.67064e-06
cap "VCO_0/X3/X4/XM4/a_n417_n100#" "vdda2" 7.9064e-08
cap "VCO_0/X3/X4/XM4/a_n369_122#" "vdda2" 0.000248087
cap "VCO_0/X3/X4/XM4/a_207_122#" "vdda2" 0.000248087
cap "VCO_0/X3/X4/XM4/a_n33_n100#" "vdda2" 7.9064e-08
cap "VCO_0/X3/X4/BIAS" "vdda2" 24.7667
cap "VCO_0/X3/X4/XM4/a_351_n100#" "vdda2" 7.9064e-08
cap "VCO_0/X3/X4/XM4/a_n177_122#" "vdda2" 0.000248087
cap "VCO_0/X3/X4/XM4/a_n225_n100#" "vdda2" 7.9064e-08
cap "VCO_0/X3/X4/GND" "vdda2" 64.7565
cap "VCO_0/X3/X4/XM4/a_159_n100#" "vdda2" 7.9064e-08
cap "VCO_0/X3/X4/XM4/a_63_n100#" "vdda2" 7.9064e-08
cap "VCO_0/X3/X4/XM4/a_n509_n100#" "vdda2" 7.9064e-08
cap "VCO_0/X3/X4/XM4/a_399_122#" "vdda2" 0.000248087
cap "VCO_0/X3/X4/XM2/a_n73_n100#" "vdda2" 2.93806
cap "VCO_0/X3/X4/XM4/a_447_n100#" "vdda2" 8.27095e-08
cap "VCO_0/X3/X4/XM4/a_15_122#" "vdda2" 0.000248087
cap "VCO_0/X3/X4/XM4/a_n129_n100#" "vdda2" 7.9064e-08
cap "VCO_0/bias_calc_0/BIAS2V" "VCO_0/bias_calc_0/XM36/a_803_n100#" 291.899
cap "VCO_0/bias_calc_0/VDD" "VCO_0/bias_calc_0/BIAS2V" 355.86
cap "VCO_0/bias_calc_0/VDD" "VCO_0/bias_calc_0/XM36/a_803_n100#" -12.5521
cap "VCO_0/bias_calc_0/BIAS2V" "VCO_0/bias_calc_0/XM36/a_803_n100#" 18.7058
cap "VCO_0/bias_calc_0/VDD" "VCO_0/bias_calc_0/XM36/a_803_n100#" -14.1196
cap "VCO_0/bias_calc_0/XR19/a_n415_n1322#" "VCO_0/bias_calc_0/BIAS2V" 0.000165168
cap "VCO_0/bias_calc_0/BIAS2V" "VCO_0/bias_calc_0/XR19/a_n285_760#" 0.000125011
cap "VCO_0/bias_calc_0/VDD" "VCO_0/bias_calc_0/BIAS2V" 88.8717
cap "VCO_0/bias_calc_0/VDD" "VCO_0/bias_calc_0/BIAS2V" 0.000170458
cap "VCO_0/bias_calc_0/BIAS2V" "VCO_0/bias_calc_0/XR19/a_n415_n1322#" 3.1119e-05
cap "VCO_0/bias_calc_0/BIAS2V" "VCO_0/bias_calc_0/XR19/a_n285_760#" 2.49437e-05
cap "VCO_0/X3/X5/XR18/a_n415_n4762#" "vdda2" 55.2515
cap "vdda2" "VCO_0/X3/m2_20210_20620#" 127.792
cap "vdda2" "VCO_0/GND" 424.15
cap "VCO_0/X3/X5/XR18/a_n415_n4762#" "vdda2" 50.0551
cap "vdda2" "VCO_0/X3/m2_20210_20620#" 251.267
cap "VCO_0/GND" "vdda2" 424.15
cap "vdda2" "VCO_0/X3/m2_20210_20620#" 3.53028
cap "VCO_0/X3/X5/VDD" "vdda2" 79.7193
cap "vdda2" "VCO_0/GND" 223.864
cap "VCO_0/X3/X5/XR18/a_n285_4200#" "vdda2" 23.3346
cap "vdda2" "VCO_0/X3/SUB" 40.7583
cap "vdda2" "VCO_0/X3/X1/GND" 312.968
cap "VCO_0/X3/SUB" "vdda2" 3.0089
cap "VCO_0/X3/X5/XR18/a_n285_4200#" "vdda2" 3.2914
cap "VCO_0/X3/SUB" "vdda2" 0.29747
cap "VCO_0/X3/X5/VDD" "vdda2" 0.0320968
cap "VCO_0/X3/X5/XR18/a_n285_4200#" "vdda2" 13.8029
cap "VCO_0/X3/OUT180" "vdda2" 209.003
cap "vdda2" "VCO_0/X3/X1/GND" 379.613
cap "VCO_0/X3/X5/VDD" "vdda2" 0.166442
cap "VCO_0/X3/X5/XR18/a_n285_4200#" "vdda2" 86.4972
cap "vdda2" "VCO_0/X3/X1/BIAS" 87.7198
cap "VCO_0/X3/SUB" "vdda2" 98.6171
cap "VCO_0/m1_46335_31170#" "vdda2" 16.287
cap "VCO_0/X3/SUB" "vdda2" 0.0804688
cap "VCO_0/X3/X1/BIAS" "vdda2" 0.165358
cap "VCO_0/X3/SUB" "vdda2" 0.00303494
cap "VCO_0/X3/X1/GND" "vdda2" 3.8433
cap "VCO_0/X3/X1/BIAS" "vdda2" 0.377045
cap "VCO_0/X3/OUT0" "vdda2" 234.954
cap "VCO_0/X3/X1/BIAS" "vdda2" 46.2955
cap "VCO_0/X3/X1/GND" "vdda2" 181.772
cap "VCO_0/X3/X1/XR1/a_n703_n3602#" "vdda2" 31.6833
cap "VCO_0/X3/X4/BIAS" "vdda2" 232.856
cap "VCO_0/X3/X4/GND" "vdda2" 508.895
cap "VCO_0/X3/X4/BIAS" "vdda2" 0.317882
cap "vdda2" "VCO_0/X3/X4/GND" 28.8666
cap "VCO_0/bias_calc_0/XM36/a_291_n100#" "VCO_0/bias_calc_0/BIAS2V" 36.2743
cap "VCO_0/bias_calc_0/XM2/a_291_n100#" "VCO_0/bias_calc_0/BIAS2V" 8.15412
cap "VCO_0/bias_calc_0/VDD" "VCO_0/bias_calc_0/BIAS2V" 86.6371
cap "VCO_0/bias_calc_0/VDD" "VCO_0/bias_calc_0/BIAS2V" 105.705
cap "VCO_0/bias_calc_0/XM3/a_291_n100#" "VCO_0/bias_calc_0/BIAS2V" 32.3775
cap "VCO_0/bias_calc_0/XM2/a_291_n100#" "VCO_0/bias_calc_0/BIAS2V" 14.2313
cap "VCO_0/bias_calc_0/VDD" "VCO_0/bias_calc_0/BIAS2V" 8.75282
cap "vdda2" "VCO_0/X3/BIAS" 105.347
cap "vdda2" "VCO_0/GND" 119.32
cap "vdda2" "VCO_0/X3/BIAS" 105.347
cap "vdda2" "VCO_0/GND" 119.32
cap "VCO_0/GND" "vdda2" 415.718
cap "vdda2" "VCO_0/X3/X5/VDD" 83.7758
cap "VCO_0/X3/BIAS" "vdda2" 38.7591
cap "vdda2" "VCO_0/X3/X5/VDD" 0.0576215
cap "VCO_0/X3/X1/BIAS" "vdda2" 66.6326
cap "VCO_0/X3/X5/VDD" "vdda2" 0.167429
cap "VCO_0/X3/OUT180" "vdda2" 221.194
cap "VCO_0/X3/SUB" "vdda2" 81.5185
cap "VCO_0/X3/X1/XR1/a_n703_n3602#" "vdda2" 31.6925
cap "VCO_0/X3/OUT0" "vdda2" 234.954
cap "vdda2" "VCO_0/X3/X4/BIAS" 131.653
cap "vdda2" "VCO_0/X3/X4/GND" 105.025
cap "VCO_0/X3/X4/GND" "vdda2" 26.4431
cap "VCO_0/X3/X1/XR1/a_n573_3040#" "VCO_0/GND" 382.291
cap "VCO_0/X3/X1/VDD" "VCO_0/X3/OUT180" 221.194
cap "VCO_0/X3/X1/VDD" "VCO_0/X3/BIAS" 57.8737
cap "VCO_0/X3/X1/VDD" "VCO_0/X3/X1/XR1/a_n703_n3602#" 81.5185
cap "VCO_0/X3/OUT0" "vdda2" 234.954
cap "VCO_0/X3/X1/XR1/a_n703_n3602#" "vdda2" 31.6925
cap "vdda2" "VCO_0/m1_50680_31080#" 131.653
cap "vdda2" "VCO_0/X3/X1/XR2/a_n703_n3602#" 105.025
cap "VCO_0/X3/X1/XR2/a_n703_n3602#" "vdda2" 26.4431
cap "VCO_0/X11/XM4/a_n33_122#" "VCO_0/GND" -2.71051e-20
cap "VCO_0/X11/XM4/a_111_n100#" "VCO_0/GND" 1.38778e-17
cap "VCO_0/X11/XM4/a_n33_122#" "VCO_0/GND" 1.35525e-20
cap "VCO_0/X11/XM4/a_63_n188#" "VCO_0/GND" 0.000963296
cap "VCO_0/GND" "VCO_0/GND" 4.33681e-19
cap "vdda2" "VCO_0/VDD" 39.8858
cap "VCO_0/VDD" "vdda2" 39.8858
cap "VCO_0/output_buffer_0/VDD" "VCO_0/output_buffer_0/GND" 4.94547
cap "VCO_0/output_buffer_0/XR2/a_n415_n1322#" "VCO_0/output_buffer_0/VDD" 22.7056
cap "VCO_0/m1_47700_36500#" "VCO_0/output_buffer_0/VDD" 55.7516
cap "VCO_0/m1_46210_32690#" "VCO_0/output_buffer_0/VDD" 15.7913
cap "VCO_0/output_buffer_0/OUTB" "VCO_0/X3/X1/VDD" 9.22733
cap "VCO_0/output_buffer_0/XR2/a_n415_n1322#" "vdda2" -0.00409666
cap "VCO_0/output_buffer_0/OUTB" "vdda2" 44.4719
cap "vdda2" "VCO_0/m1_48170_36500#" 64.1088
cap "VCO_0/X3/X1/XR1/a_n703_n3602#" "VCO_0/output_buffer_0/OUTB" 16.9572
cap "vdda2" "VCO_0/output_buffer_0/OUTB" 125.954
cap "vdda2" "VCO_0/X3/X1/VDD" 44.7105
cap "vdda2" "VCO_0/X3/X1/XR1/a_n703_n3602#" 8.83774
cap "VCO_0/X3/X1/VDD" "VCO_0/output_buffer_0/OUTB" 85.636
cap "VCO_0/output_buffer_0/BIAS" "vdda2" 20.2526
cap "VCO_0/X3/X4/VDD" "vdda2" 114.171
cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/XR3/a_n703_n2202#" 9.73779
cap "vdda2" "VCO_0/output_buffer_0/OUTB" 0.447962
cap "VCO_0/X3/X4/VDD" "VCO_0/output_buffer_0/OUTB" 33.7419
cap "vdda2" "VCO_0/output_buffer_0/XR3/a_n703_n2202#" 19.3101
cap "vdda2" "VCO_0/X3/X1/XR2/a_n703_n3602#" 7.21518
cap "VCO_0/GND" "VCO_0/X11/XM2/a_n33_n188#" 0.100962
cap "VCO_0/GND" "VCO_0/X11/XM4/a_n275_n274#" 0.194171
cap "VCO_0/GND" "VCO_0/X11/XM3/a_15_122#" 0.0272999
cap "VCO_0/CTRL1" "VCO_0/GND" 0.256564
cap "VCO_0/GND" "VCO_0/X11/XM2/a_15_n100#" -2.84217e-14
cap "VCO_0/CTRL1" "VCO_0/GND" 0.258619
cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/XM2/a_n1091_n274#" 0.233479
cap "VCO_0/output_buffer_0/XR2/a_n285_760#" "VCO_0/output_buffer_0/OUTB" -0.0897258
cap "VCO_0/output_buffer_0/OUTB" "VCO_0/X3/X1/VDD" 24.498
cap "VCO_0/output_buffer_0/OUTB" "vdda2" 28.0698
cap "VCO_0/output_buffer_0/XR2/a_n415_n1322#" "VCO_0/output_buffer_0/INA" 0.0765442
cap "VCO_0/output_buffer_0/XR2/a_n415_n1322#" "VCO_0/output_buffer_0/OUTB" 32.7192
cap "VCO_0/output_buffer_0/INB" "VCO_0/output_buffer_0/OUTB" 12.7575
cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/INA" 87.8801
cap "VCO_0/output_buffer_0/BIAS" "VCO_0/output_buffer_0/OUTB" 4.15793
cap "VCO_0/X3/X1/XR1/a_n703_n3602#" "VCO_0/output_buffer_0/INA" -3.27754
cap "VCO_0/X3/X1/VDD" "VCO_0/output_buffer_0/OUTB" 187.096
cap "vdda2" "VCO_0/output_buffer_0/OUTB" 66.7825
cap "VCO_0/output_buffer_0/INA" "VCO_0/output_buffer_0/OUTB" 155.385
cap "VCO_0/X3/X1/XR1/a_n703_n3602#" "VCO_0/output_buffer_0/OUTB" 128.498
cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/VDD" 103.12
cap "VCO_0/X3/X4/VDD" "VCO_0/output_buffer_0/OUTB" 87.3999
cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/BIAS" 116.418
cap "VCO_0/output_buffer_0/XR3/a_n703_n2202#" "VCO_0/output_buffer_0/OUTB" 68.6636
cap "vdda2" "VCO_0/output_buffer_0/OUTB" 0.254108
cap "VCO_0/X3/X1/XR2/a_n703_n3602#" "VCO_0/output_buffer_0/VDD" -1.19988
cap "VCO_0/output_buffer_0/VDD" "OUT180" 76.0187
cap "VCO_0/output_buffer_0/BIAS" "VCO_0/output_buffer_0/VDD" -0.0604315
cap "VCO_0/X3/X1/XR2/a_n703_n3602#" "OUT180" 0.0329709
cap "VCO_0/output_buffer_0/XR2/a_n285_760#" "VCO_0/output_buffer_0/OUTB" 4.51812
cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/SUB" 2.63342
cap "VCO_0/output_buffer_0/SUB" "VCO_0/output_buffer_0/XR29/a_n573_n2072#" 0.0279802
cap "VCO_0/output_buffer_0/XR2/a_n285_760#" "VCO_0/output_buffer_0/XR29/a_n573_n2072#" 0.864664
cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/XR29/a_n573_n2072#" 13.4968
cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/INA" 16.3144
cap "VCO_0/output_buffer_0/XM33/a_n989_n100#" "VCO_0/output_buffer_0/OUTB" 85.2244
cap "VCO_0/output_buffer_0/XM33/a_n989_n100#" "VCO_0/output_buffer_0/XR29/a_n573_n2072#" 0.000867213
cap "VCO_0/output_buffer_0/INB" "VCO_0/output_buffer_0/OUTB" 9.25257
cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/XR1/a_n285_760#" 7.52053
cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/SUB" 48.4075
cap "VCO_0/output_buffer_0/XR2/a_n285_760#" "VCO_0/output_buffer_0/OUTB" 65.6156
cap "VCO_0/output_buffer_0/XM32/a_n945_n188#" "VCO_0/output_buffer_0/OUTB" 21.2919
cap "VCO_0/output_buffer_0/XM33/a_n989_n100#" "VCO_0/output_buffer_0/OUTB" 458.827
cap "VCO_0/output_buffer_0/SUB" "VCO_0/output_buffer_0/OUTB" 143.86
cap "VCO_0/output_buffer_0/XR29/a_n573_n2072#" "VCO_0/output_buffer_0/XM33/a_n945_n188#" 8.68357
cap "VCO_0/output_buffer_0/XR29/a_n573_n2072#" "VCO_0/output_buffer_0/OUTB" 38.1132
cap "VCO_0/output_buffer_0/SUB" "VCO_0/output_buffer_0/XR29/a_n573_n2072#" 0.278207
cap "VCO_0/output_buffer_0/BIAS" "VCO_0/output_buffer_0/OUTB" 3.00295
cap "VCO_0/output_buffer_0/XR29/a_n573_n2072#" "VCO_0/output_buffer_0/XM33/a_n989_n100#" 3.50188
cap "VCO_0/output_buffer_0/XM33/a_n945_n188#" "VCO_0/output_buffer_0/OUTB" 250.496
cap "VCO_0/output_buffer_0/BIAS" "VCO_0/output_buffer_0/OUTB" 244.309
cap "VCO_0/output_buffer_0/XM33/a_n945_n188#" "VCO_0/output_buffer_0/OUTB" 26.3833
cap "VCO_0/output_buffer_0/VDD" "VCO_0/output_buffer_0/OUTB" 141.959
cap "VCO_0/output_buffer_0/XM33/a_n609_n100#" "VCO_0/output_buffer_0/OUTB" 592.755
cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/XR3/a_n703_n2202#" 82.7644
cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/XM4/a_n2817_n100#" 719.223
cap "OUT180" "VCO_0/output_buffer_0/VDD" 109.042
cap "VCO_0/output_buffer_0/BIAS" "VCO_0/output_buffer_0/VDD" -7.73432
cap "VCO_0/output_buffer_0/XM33/a_735_n100#" "VCO_0/output_buffer_0/VDD" -23.2508
cap "OUT180" "VCO_0/output_buffer_0/XM4/a_n2817_n100#" 1.77969
cap "VCO_0/output_buffer_0/BIAS" "OUT180" 0.539922
cap "OUT180" "VCO_0/output_buffer_0/XM33/a_735_n100#" 1.29939
cap "VCO_0/X3/X1/XR2/a_n703_n3602#" "VCO_0/output_buffer_0/VDD" -0.655573
cap "VCO_0/X3/X1/XR2/a_n703_n3602#" "OUT180" 0.0587963
cap "VCO_0/output_buffer_0/XM4/a_n2817_n100#" "VCO_0/output_buffer_0/VDD" -33.4069
cap "VCO_0/output_buffer_0/XR1/a_n285_760#" "VCO_0/output_buffer_0/OUTA" 0.117913
cap "VCO_0/output_buffer_0/SUB" "VCO_0/output_buffer_0/OUTA" 0.3148
cap "VCO_0/output_buffer_0/XM33/a_n989_n100#" "VCO_0/output_buffer_0/OUTB" 0.809397
cap "VCO_0/output_buffer_0/XR1/a_n285_760#" "VCO_0/output_buffer_0/OUTA" 4.05345
cap "VCO_0/output_buffer_0/SUB" "VCO_0/output_buffer_0/OUTA" 6.01503
cap "VCO_0/output_buffer_0/OUTA" "VCO_0/output_buffer_0/XR2/a_n285_760#" 0.164928
cap "VCO_0/output_buffer_0/XR1/a_n285_760#" "VCO_0/output_buffer_0/OUTB" 3.62001
cap "VCO_0/output_buffer_0/OUTA" "VCO_0/output_buffer_0/XM33/a_n989_n100#" -0.0329953
cap "VCO_0/output_buffer_0/SUB" "VCO_0/output_buffer_0/OUTB" 0.575771
cap "VCO_0/output_buffer_0/OUTA" "VCO_0/output_buffer_0/OUTB" 5.42724
cap "VCO_0/output_buffer_0/XM33/a_n989_n100#" "VCO_0/output_buffer_0/OUTA" 34.6674
cap "VCO_0/output_buffer_0/SUB" "VCO_0/output_buffer_0/OUTB" 9.06023
cap "VCO_0/output_buffer_0/XM32/a_n945_n188#" "VCO_0/output_buffer_0/OUTB" 70.8565
cap "VCO_0/output_buffer_0/XM33/a_n989_n100#" "VCO_0/output_buffer_0/OUTB" 251.508
cap "VCO_0/output_buffer_0/OUTA" "VCO_0/output_buffer_0/OUTB" 304.945
cap "VCO_0/output_buffer_0/SUB" "VCO_0/output_buffer_0/OUTA" 53.1156
cap "VCO_0/output_buffer_0/XM32/a_n945_n188#" "VCO_0/output_buffer_0/OUTA" 92.6853
cap "VCO_0/output_buffer_0/OUTA" "VCO_0/output_buffer_0/XM33/a_n945_n188#" 1.51388
cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/OUTA" 120.933
cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/BIAS" 139.734
cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/XM33/a_n609_n100#" 825.994
cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/VDD" 127.154
cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/XR3/a_n703_n2202#" 91.7768
cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/XM3/a_n2817_n100#" 726.943
cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/XM32/a_n945_n188#" 25.7306
cap "VCO_0/output_buffer_0/XM3/a_n2817_n100#" "VCO_0/output_buffer_0/VDD" -33.6933
cap "OUT180" "VCO_0/output_buffer_0/XM33/a_735_n100#" 1.30939
cap "VCO_0/output_buffer_0/XM33/a_735_n100#" "VCO_0/output_buffer_0/VDD" -30.5877
cap "OUT180" "VCO_0/output_buffer_0/XR3/a_n703_n2202#" 0.0602982
cap "OUT180" "VCO_0/output_buffer_0/VDD" 102.313
cap "VCO_0/output_buffer_0/XR3/a_n703_n2202#" "VCO_0/output_buffer_0/VDD" -0.721516
cap "OUT180" "VCO_0/output_buffer_0/BIAS" 0.550143
cap "OUT180" "VCO_0/output_buffer_0/XM3/a_n2817_n100#" 1.78666
cap "VCO_0/output_buffer_0/BIAS" "VCO_0/output_buffer_0/VDD" -7.63391
cap "VCO_0/output_buffer_0/SUB" "VCO_0/output_buffer_0/OUTA" 0.108577
cap "VCO_0/output_buffer_0/XR1/a_n285_760#" "VCO_0/output_buffer_0/OUTA" 0.0175955
cap "VCO_0/output_buffer_0/XR1/a_n285_760#" "VCO_0/output_buffer_0/OUTA" -0.209379
cap "VCO_0/output_buffer_0/SUB" "VCO_0/output_buffer_0/OUTA" 36.9643
cap "OUT180" "VCO_0/output_buffer_0/OUTA" 4.50491
cap "VCO_0/output_buffer_0/SUB" "OUT180" 12.7592
cap "VCO_0/output_buffer_0/SUB" "VCO_0/output_buffer_0/OUTA" 116.053
cap "VCO_0/output_buffer_0/OUTA" "OUT180" 13.5609
cap "OUT180" "VCO_0/output_buffer_0/XM33/a_n1091_n274#" 95.9679
cap "OUT180" "VCO_0/output_buffer_0/VDD" 114.712
cap "OUT180" "VCO_0/output_buffer_0/VDD" 82.2858
cap "OUT180" "VCO_0/output_buffer_0/XM33/a_n1091_n274#" 0.0353427
cap "io_analog[5]" "VGA_routing_0/m1_491911_626492#" 189.031
cap "io_analog[5]" "VGA_routing_0/m1_491911_626492#" 367.156
cap "io_analog[5]" "io_analog[5]" 298.48
cap "io_analog[5]" "io_analog[5]" 579.74
cap "io_analog[5]" "io_analog[5]" 579.74
cap "io_analog[5]" "io_analog[5]" 298.48
cap "io_analog[5]" "io_analog[5]" 579.74
cap "io_analog[5]" "io_analog[5]" 298.48
cap "io_analog[5]" "io_analog[5]" 169.446
cap "io_analog[5]" "io_analog[5]" 633.573
cap "io_analog[5]" "io_clamp_low[1]" 1419.22
cap "io_analog[5]" "io_clamp_low[1]" -161.747
cap "io_analog[5]" "io_clamp_low[1]" 3834.65
cap "io_clamp_low[1]" "io_analog[5]" 595.498
cap "io_analog[5]" "io_clamp_high[1]" 2545.69
cap "io_analog[5]" "io_clamp_high[1]" 3562.93
cap "io_analog[5]" "io_analog[5]" 321.244
cap "io_analog[5]" "io_clamp_high[1]" -259.254
cap "io_clamp_high[1]" "io_analog[5]" -161.747
cap "io_analog[5]" "io_analog[5]" 928.412
cap "io_analog[5]" "io_analog[5]" 579.74
cap "io_analog[5]" "io_analog[5]" 298.48
cap "io_analog[5]" "io_analog[5]" 298.48
cap "io_analog[5]" "io_analog[5]" 579.74
cap "io_analog[5]" "io_analog[5]" 791.543
cap "io_analog[5]" "io_analog[5]" 407.527
cap "io_analog[4]" "VGA_routing_0/m1_491912_626638#" 173.186
cap "io_analog[4]" "VGA_routing_0/m1_491912_626638#" 336.381
cap "io_analog[4]" "io_analog[4]" 579.74
cap "io_analog[4]" "io_analog[4]" 298.48
cap "io_analog[4]" "io_analog[4]" 298.48
cap "io_analog[4]" "io_analog[4]" 579.74
cap "io_analog[4]" "io_clamp_low[0]" -89.5878
cap "io_analog[4]" "io_analog[4]" 725.503
cap "io_analog[4]" "io_analog[4]" 319.36
cap "io_clamp_low[0]" "io_analog[4]" -55.8932
cap "io_clamp_low[0]" "io_analog[4]" 1463.99
cap "io_clamp_high[0]" "io_analog[4]" 30.0662
cap "io_clamp_low[0]" "io_analog[4]" 1463.91
cap "io_clamp_high[0]" "io_analog[4]" 1845.02
cap "io_analog[4]" "io_clamp_high[0]" -55.8932
cap "io_analog[4]" "io_clamp_high[0]" 963.232
cap "io_analog[4]" "io_analog[4]" 274.962
cap "io_analog[4]" "io_analog[4]" 87.3981
cap "io_analog[4]" "io_analog[4]" 298.48
cap "io_analog[4]" "io_analog[4]" 579.74
cap "io_analog[4]" "io_analog[4]" 298.48
cap "io_analog[4]" "io_analog[4]" 579.74
cap "io_analog[4]" "io_analog[4]" 579.74
cap "io_analog[4]" "io_analog[4]" 298.48
cap "io_analog[4]" "VGA_routing_0/m1_491912_626638#" 181.646
cap "io_analog[4]" "VGA_routing_0/m1_491912_626638#" 352.813
merge "VCO_0/VSUBS" "BGR_lvs_0/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "BGR_lvs_0/VSUBS" "VCO_1/VSUBS"
merge "VCO_1/VSUBS" "TX_line_0/VSUBS"
merge "TX_line_0/VSUBS" "VGA_routing_0/VSUBS"
merge "VGA_routing_0/VSUBS" "VSUBS"
merge "VGA_routing_0/m4_419918_417788#" "BGR_lvs_0/vbg" -114239 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -29982000 -21460 -24720050 -16405 -263660000 -50200 -183800472 -68036 0 0
merge "BGR_lvs_0/vbg" "io_analog[6]"
merge "VCO_0/output_buffer_0/VDD" "VCO_0/X3/X1/VDD" -96516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10860400 -18058 -162407034 -350072 0 0
merge "VCO_0/X3/X1/VDD" "VCO_0/VDD"
merge "VCO_0/VDD" "VCO_0/X3/X2/VDD"
merge "VCO_0/X3/X2/VDD" "VCO_1/output_buffer_0/VDD"
merge "VCO_1/output_buffer_0/VDD" "VCO_1/X3/X1/VDD"
merge "VCO_1/X3/X1/VDD" "VCO_1/X3/X2/VDD"
merge "VCO_1/X3/X2/VDD" "VCO_1/VDD"
merge "VCO_1/VDD" "vdda2"
merge "VGA_routing_0/m1_448364_344480#" "io_analog[0]" -4425.07 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4272604 -15144 0 0 0 0 0 0
merge "BGR_lvs_0/Iout0" "VCO_1/bias_calc_0/BIAS2V" -6403.03 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1740600 -7914 -3880900 -9894 -1520000 -5688 0 0 0 0
merge "VCO_1/bias_calc_0/BIAS2V" "REF2"
merge "TX_line_0/OUTA" "VGA_routing_0/m1_443471_412049#" -50821.5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -73770910 -80702 -4000000 -10000 -15263386 -29174 0 0
merge "VGA_routing_0/m1_443471_412049#" "VCO_1/output_buffer_0/OUTA"
merge "VCO_1/output_buffer_0/OUTA" "txina"
merge "VCO_0/m1_33455_32800#" "VCO_0/bias_calc_0/BIAS2V" -7726.12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -37824 -778 -2592900 -8126 -2102000 -21220 0 0 0 0
merge "VCO_0/bias_calc_0/BIAS2V" "BGR_lvs_0/Iout1"
merge "BGR_lvs_0/Iout1" "REF"
merge "VGA_routing_0/m2_445625_418319#" "vccd1" -20368.4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -34259500 -47688 0 0 0 0 0 0
merge "VCO_0/CTRL1" "VCO_0/X9/ctrll1" -881.525 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -13598 -694 -272200 -4190 0 0 0 0 0 0 0 0
merge "VCO_0/X9/ctrll1" "VCO_1/X9/ctrll1"
merge "VCO_1/X9/ctrll1" "VCO_1/CTRL1"
merge "VCO_1/CTRL1" "CTRL1"
merge "BGR_lvs_0/Iout2" "io_analog[7]" -5658.43 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10200900 -14006 0 0 0 0 0 0
merge "VCO_1/output_buffer_0/OUTB" "TX_line_0/INB" -50956.5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -64166750 -69080 -1405000 -6120 -4039840 -14024 0 0
merge "TX_line_0/INB" "VGA_routing_0/m1_443471_411908#"
merge "VGA_routing_0/m1_443471_411908#" "txinb"
merge "VCO_0/X3/X6/GND" "VCO_0/bias_calc_0/GND" -338272 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -330346886 -384175 -1284640000 -156400 0 0
merge "VCO_0/bias_calc_0/GND" "VCO_0/GND"
merge "VCO_0/GND" "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss"
merge "BGR_lvs_0/opamp_realcomp3_usefinger_0/vss" "BGR_lvs_0/opamp_realcomp3_usefinger_1/vss"
merge "BGR_lvs_0/opamp_realcomp3_usefinger_1/vss" "BGR_lvs_0/VSS"
merge "BGR_lvs_0/VSS" "VGA_routing_0/m3_426670_449375#"
merge "VGA_routing_0/m3_426670_449375#" "VCO_1/bias_calc_0/GND"
merge "VCO_1/bias_calc_0/GND" "VCO_1/X3/X6/GND"
merge "VCO_1/X3/X6/GND" "VCO_1/GND"
merge "VCO_1/GND" "vssa2"
merge "BGR_lvs_0/opamp_realcomp3_usefinger_0/vdd" "BGR_lvs_0/XM_feedbackmir_0/B" -175952 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -383837220 -190670 -338400000 -68400 0 0
merge "BGR_lvs_0/XM_feedbackmir_0/B" "BGR_lvs_0/VDD"
merge "BGR_lvs_0/VDD" "vccd2"
merge "VCO_0/CTRL2" "VCO_0/X9/ctrll2" -789.953 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -14193 -714 -468200 -6990 0 0 0 0 0 0 0 0
merge "VCO_0/X9/ctrll2" "VCO_1/X9/ctrll2"
merge "VCO_1/X9/ctrll2" "VCO_1/CTRL2"
merge "VCO_1/CTRL2" "CTRL2"
merge "VGA_routing_0/m2_486048_557650#" "BGR_lvs_0/Iout3" -5504.96 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -9282400 -15688 0 0 0 0 0 0
merge "BGR_lvs_0/Iout3" "m3_290506_594136#"
merge "VCO_0/output_buffer_0/OUTB" "OUT180" -6018.51 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -532855 -3346 -2295200 -5782 0 0 0 0
merge "VGA_routing_0/m1_465142_344633#" "io_analog[1]" -2174.54 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -319488 -10128 0 0 0 0 0 0
merge "VCO_0/CTRL3" "VCO_0/X9/ctrll3" -801.807 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -12983 -674 -468200 -6990 0 0 0 0 0 0 0 0
merge "VCO_0/X9/ctrll3" "VCO_1/X9/ctrll3"
merge "VCO_1/X9/ctrll3" "VCO_1/CTRL3"
merge "VCO_1/CTRL3" "CTRL3"
merge "VGA_routing_0/m1_444321_418953#" "BGR_lvs_0/Iout4" -5133.63 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -7206218 -15687 0 0 0 0 0 0
merge "BGR_lvs_0/Iout4" "m3_292774_580566#"
merge "VCO_0/bias_calc_0/VCTRL" "VCO_1/bias_calc_0/VCTRL" -3261.69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -916100 -12110 0 0 0 0 0 0 0 0 0 0
merge "VCO_1/bias_calc_0/VCTRL" "VCTRL"
merge "VGA_routing_0/m1_491912_626638#" "io_analog[4]" -15870.5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4015000 -10712 -16264000 -36916 -4015000 -10712 0 0
merge "VCO_0/X9/ctrll4" "VCO_0/CTRL4" -926.453 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -14820 -734 -636200 -9790 0 0 0 0 0 0 0 0
merge "VCO_0/CTRL4" "VCO_1/X9/ctrll4"
merge "VCO_1/X9/ctrll4" "VCO_1/CTRL4"
merge "VCO_1/CTRL4" "CTRL4"
merge "VCO_0/CTRL5" "VCO_0/X9/ctrll5" -2928.16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -14223 -754 -832200 -12590 0 0 0 0 0 0 0 0
merge "VCO_0/X9/ctrll5" "VCO_1/X9/ctrll5"
merge "VCO_1/X9/ctrll5" "VCO_1/CTRL5"
merge "VCO_1/CTRL5" "CTRL5"
merge "VCO_0/output_buffer_0/OUTA" "OUT0" -1560.5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -549020 -3474 0 0 0 0 0 0
merge "VGA_routing_0/m1_491911_626492#" "io_analog[5]" -16380.2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2000000 -6600 -26278816 -38514 -2000000 -6600 0 0
merge "VGA_routing_0/m1_443140_352045#" "io_analog[3]" -5744.9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1706048 -4894 -4523344 -17876 0 0 0 0
merge "BGR_lvs_0/porst" "gpio_analog[7]" -4133.13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -9913160 -16126 0 0 0 0 0 0
merge "VGA_routing_0/m1_467461_355277#" "io_analog[2]" -2715.89 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1342344 -11226 0 0 0 0 0 0
merge "VGA_routing_0/m3_441966_382352#" "io_in[13]" -1128.51 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -731264 -4080 0 0 0 0 0 0