Warning: Equate pins:  cell sky130_fd_pr__nfet_01v8_lvt is a placeholder, treated as a black box.
Warning: Equate pins:  cell sky130_fd_pr__nfet_01v8_lvt is a placeholder, treated as a black box.

Subcircuit pins:
Circuit 1: sky130_fd_pr__nfet_01v8_lvt     |Circuit 2: sky130_fd_pr__nfet_01v8_lvt     
-------------------------------------------|-------------------------------------------
1                                          |1                                          
2                                          |2                                          
3                                          |3                                          
4                                          |4                                          
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_pr__nfet_01v8_lvt and sky130_fd_pr__nfet_01v8_lvt are equivalent.
Warning: Equate pins:  cell sky130_fd_pr__res_high_po_2p85 is a placeholder, treated as a black box.
Warning: Equate pins:  cell sky130_fd_pr__res_high_po_2p85 is a placeholder, treated as a black box.

Subcircuit pins:
Circuit 1: sky130_fd_pr__res_high_po_2p85  |Circuit 2: sky130_fd_pr__res_high_po_2p85  
-------------------------------------------|-------------------------------------------
1                                          |1                                          
2                                          |2                                          
3                                          |3                                          
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_pr__res_high_po_2p85 and sky130_fd_pr__res_high_po_2p85 are equivalent.
Warning: Equate pins:  cell sky130_fd_pr__res_high_po_5p73 is a placeholder, treated as a black box.
Warning: Equate pins:  cell sky130_fd_pr__res_high_po_5p73 is a placeholder, treated as a black box.

Subcircuit pins:
Circuit 1: sky130_fd_pr__res_high_po_5p73  |Circuit 2: sky130_fd_pr__res_high_po_5p73  
-------------------------------------------|-------------------------------------------
1                                          |1                                          
2                                          |2                                          
3                                          |3                                          
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_pr__res_high_po_5p73 and sky130_fd_pr__res_high_po_5p73 are equivalent.
Warning: Equate pins:  cell sky130_fd_pr__cap_mim_m3_1 is a placeholder, treated as a black box.
Warning: Equate pins:  cell sky130_fd_pr__cap_mim_m3_1 is a placeholder, treated as a black box.

Subcircuit pins:
Circuit 1: sky130_fd_pr__cap_mim_m3_1      |Circuit 2: sky130_fd_pr__cap_mim_m3_1      
-------------------------------------------|-------------------------------------------
1                                          |1                                          
2                                          |2                                          
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_pr__cap_mim_m3_1 and sky130_fd_pr__cap_mim_m3_1 are equivalent.
Warning: Equate pins:  cell sky130_fd_pr__cap_mim_m3_2 is a placeholder, treated as a black box.
Warning: Equate pins:  cell sky130_fd_pr__cap_mim_m3_2 is a placeholder, treated as a black box.

Subcircuit pins:
Circuit 1: sky130_fd_pr__cap_mim_m3_2      |Circuit 2: sky130_fd_pr__cap_mim_m3_2      
-------------------------------------------|-------------------------------------------
1                                          |1                                          
2                                          |2                                          
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_pr__cap_mim_m3_2 and sky130_fd_pr__cap_mim_m3_2 are equivalent.
Warning: Equate pins:  cell sky130_fd_pr__pfet_01v8_lvt is a placeholder, treated as a black box.
Warning: Equate pins:  cell sky130_fd_pr__pfet_01v8_lvt is a placeholder, treated as a black box.

Subcircuit pins:
Circuit 1: sky130_fd_pr__pfet_01v8_lvt     |Circuit 2: sky130_fd_pr__pfet_01v8_lvt     
-------------------------------------------|-------------------------------------------
1                                          |1                                          
2                                          |2                                          
3                                          |3                                          
4                                          |4                                          
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_pr__pfet_01v8_lvt and sky130_fd_pr__pfet_01v8_lvt are equivalent.
Flattening unmatched subcell sky130_fd_pr__nfet_01v8_lvt_YTLFGX in circuit core_osc_amp (0)(2 instances)
Flattening unmatched subcell sky130_fd_pr__nfet_01v8_lvt_HNLS5R in circuit core_osc_amp (0)(2 instances)
Flattening unmatched subcell sky130_fd_pr__res_high_po_2p85_P79JE3 in circuit core_osc_amp (0)(2 instances)

Class core_osc_amp (0):  Merged 45 parallel devices.
Class core_osc_amp (1):  Merged 1 parallel devices.
Subcircuit summary:
Circuit 1: core_osc_amp                    |Circuit 2: core_osc_amp                    
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8_lvt (48->3)        |sky130_fd_pr__nfet_01v8_lvt (4->3)         
sky130_fd_pr__res_high_po_2p85 (2)         |sky130_fd_pr__res_high_po_2p85 (2)         
Number of devices: 5                       |Number of devices: 5                       
Number of nets: 9                          |Number of nets: 9                          
---------------------------------------------------------------------------------------
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match uniquely.
Circuits match correctly.

Subcircuit pins:
Circuit 1: core_osc_amp                    |Circuit 2: core_osc_amp                    
-------------------------------------------|-------------------------------------------
OUTB                                       |OUTB                                       
OUTA                                       |OUTA                                       
VDD                                        |VDD                                        
SUB                                        |SUB                                        
INB                                        |INB                                        
INA                                        |INA                                        
BIAS                                       |BIAS                                       
GND                                        |GND                                        
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes core_osc_amp and core_osc_amp are equivalent.
Flattening unmatched subcell sky130_fd_pr__res_high_po_5p73_YZEQ6M in circuit buffer_amp (0)(2 instances)
Flattening unmatched subcell sky130_fd_pr__nfet_01v8_lvt_9DHFGX in circuit buffer_amp (0)(2 instances)
Flattening unmatched subcell sky130_fd_pr__nfet_01v8_lvt_648S5X in circuit buffer_amp (0)(2 instances)

Class buffer_amp (0):  Merged 19 parallel devices.
Class buffer_amp (1):  Merged 1 parallel devices.
Subcircuit summary:
Circuit 1: buffer_amp                      |Circuit 2: buffer_amp                      
-------------------------------------------|-------------------------------------------
sky130_fd_pr__res_high_po_5p73 (2)         |sky130_fd_pr__res_high_po_5p73 (2)         
sky130_fd_pr__nfet_01v8_lvt (22->3)        |sky130_fd_pr__nfet_01v8_lvt (4->3)         
Number of devices: 5                       |Number of devices: 5                       
Number of nets: 9                          |Number of nets: 9                          
---------------------------------------------------------------------------------------
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match uniquely.
Circuits match correctly.

Subcircuit pins:
Circuit 1: buffer_amp                      |Circuit 2: buffer_amp                      
-------------------------------------------|-------------------------------------------
BIAS                                       |BIAS                                       
GND                                        |GND                                        
INA                                        |INA                                        
INB                                        |INB                                        
SUB                                        |SUB                                        
OUTA                                       |OUTA                                       
OUTB                                       |OUTB                                       
VDD                                        |VDD                                        
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes buffer_amp and buffer_amp are equivalent.
Flattening unmatched subcell sky130_fd_pr__nfet_01v8_lvt_HNLS5R in circuit amp_dec (0)(4 instances)
Flattening unmatched subcell sky130_fd_pr__res_high_po_2p85_MXEQGY in circuit amp_dec (0)(1 instance)
Flattening unmatched subcell sky130_fd_pr__cap_mim_m3_1_4RCNTW in circuit amp_dec (0)(1 instance)

Class amp_dec (0):  Merged 12 parallel devices.
Subcircuit summary:
Circuit 1: amp_dec                         |Circuit 2: amp_dec                         
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8_lvt (16->4)        |sky130_fd_pr__nfet_01v8_lvt (4)            
sky130_fd_pr__res_high_po_2p85 (1)         |sky130_fd_pr__res_high_po_2p85 (1)         
sky130_fd_pr__cap_mim_m3_1 (1)             |sky130_fd_pr__cap_mim_m3_1 (1)             
Number of devices: 6                       |Number of devices: 6                       
Number of nets: 8                          |Number of nets: 8                          
---------------------------------------------------------------------------------------
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match uniquely.
Circuits match correctly.

Subcircuit pins:
Circuit 1: amp_dec                         |Circuit 2: amp_dec                         
-------------------------------------------|-------------------------------------------
GND                                        |GND                                        
IN1                                        |IN1                                        
IN2                                        |IN2                                        
IN3                                        |IN3                                        
IN4                                        |IN4                                        
VDD                                        |VDD                                        
SUB                                        |SUB                                        
AMP                                        |AMP                                        
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes amp_dec and amp_dec are equivalent.
Flattening unmatched subcell sky130_fd_pr__res_high_po_2p85_MXEQGY in circuit vop_dec (0)(1 instance)
Flattening unmatched subcell sky130_fd_pr__cap_mim_m3_1_4RCNTW in circuit vop_dec (0)(1 instance)
Flattening unmatched subcell sky130_fd_pr__nfet_01v8_lvt_6BNFGK in circuit vop_dec (0)(1 instance)

Class vop_dec (0):  Merged 11 parallel devices.
Subcircuit summary:
Circuit 1: vop_dec                         |Circuit 2: vop_dec                         
-------------------------------------------|-------------------------------------------
sky130_fd_pr__res_high_po_2p85 (1)         |sky130_fd_pr__res_high_po_2p85 (1)         
sky130_fd_pr__cap_mim_m3_1 (1)             |sky130_fd_pr__cap_mim_m3_1 (1)             
sky130_fd_pr__nfet_01v8_lvt (12->1)        |sky130_fd_pr__nfet_01v8_lvt (1)            
Number of devices: 3                       |Number of devices: 3                       
Number of nets: 5                          |Number of nets: 5                          
---------------------------------------------------------------------------------------
Circuits match uniquely.
Netlists match uniquely.

Subcircuit pins:
Circuit 1: vop_dec                         |Circuit 2: vop_dec                         
-------------------------------------------|-------------------------------------------
VDD                                        |VDD                                        
IN                                         |IN                                         
VOP                                        |VOP                                        
SUB                                        |SUB                                        
GND                                        |GND                                        
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes vop_dec and vop_dec are equivalent.
Flattening unmatched subcell sky130_fd_pr__nfet_01v8_lvt_648S5X in circuit cap_bank (0)(2 instances)
Flattening unmatched subcell sky130_fd_pr__nfet_01v8_lvt_DJ7QE5 in circuit cap_bank (0)(1 instance)
Flattening unmatched subcell sky130_fd_pr__nfet_01v8_lvt_BX7S53 in circuit cap_bank (0)(1 instance)
Flattening unmatched subcell sky130_fd_pr__nfet_01v8_lvt_B6HS5D in circuit cap_bank (0)(1 instance)
Flattening unmatched subcell sky130_fd_pr__cap_mim_m3_2_WCTBV5 in circuit cap_bank (0)(1 instance)
Flattening unmatched subcell sky130_fd_pr__cap_mim_m3_2_WCTZRP in circuit cap_bank (0)(1 instance)
Flattening unmatched subcell sky130_fd_pr__cap_mim_m3_2_3ZFDVT in circuit cap_bank (0)(1 instance)
Flattening unmatched subcell sky130_fd_pr__cap_mim_m3_2_VCH7EQ in circuit cap_bank (0)(1 instance)
Flattening unmatched subcell sky130_fd_pr__cap_mim_m3_2_FJFAMD in circuit cap_bank (0)(1 instance)

Class cap_bank (0):  Merged 8 parallel devices.
Subcircuit summary:
Circuit 1: cap_bank                        |Circuit 2: cap_bank                        
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8_lvt (13->5)        |sky130_fd_pr__nfet_01v8_lvt (5)            
sky130_fd_pr__cap_mim_m3_2 (5)             |sky130_fd_pr__cap_mim_m3_2 (5)             
Number of devices: 10                      |Number of devices: 10                      
Number of nets: 12                         |Number of nets: 12                         
---------------------------------------------------------------------------------------
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match uniquely.
Circuits match correctly.

Subcircuit pins:
Circuit 1: cap_bank                        |Circuit 2: cap_bank                        
-------------------------------------------|-------------------------------------------
IN                                         |IN                                         
GND                                        |GND                                        
ctrll5                                     |ctrll5                                     
ctrll4                                     |ctrll4                                     
ctrll3                                     |ctrll3                                     
ctrll2                                     |ctrll2                                     
ctrll1                                     |ctrll1                                     
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes cap_bank and cap_bank are equivalent.
Flattening unmatched subcell sky130_fd_pr__res_high_po_2p85_P79JE3 in circuit output_buffer (0)(2 instances)
Flattening unmatched subcell sky130_fd_pr__res_high_po_5p73_W59YBA in circuit output_buffer (0)(2 instances)
Flattening unmatched subcell sky130_fd_pr__nfet_01v8_lvt_YTLFGX in circuit output_buffer (0)(4 instances)
Flattening unmatched subcell sky130_fd_pr__nfet_01v8_lvt_LELFGX in circuit output_buffer (0)(2 instances)
Flattening unmatched subcell sky130_fd_pr__nfet_01v8_lvt_HNLS5R in circuit output_buffer (0)(2 instances)

Class output_buffer (0):  Merged 202 parallel devices.
Class output_buffer (1):  Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: output_buffer                   |Circuit 2: output_buffer                   
-------------------------------------------|-------------------------------------------
sky130_fd_pr__res_high_po_2p85 (2)         |sky130_fd_pr__res_high_po_2p85 (2)         
sky130_fd_pr__res_high_po_5p73 (2)         |sky130_fd_pr__res_high_po_5p73 (2)         
sky130_fd_pr__nfet_01v8_lvt (208->6)       |sky130_fd_pr__nfet_01v8_lvt (8->6)         
Number of devices: 10                      |Number of devices: 10                      
Number of nets: 12                         |Number of nets: 12                         
---------------------------------------------------------------------------------------
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match uniquely.
Circuits match correctly.

Subcircuit pins:
Circuit 1: output_buffer                   |Circuit 2: output_buffer                   
-------------------------------------------|-------------------------------------------
INA                                        |INA                                        
INB                                        |INB                                        
OUTA                                       |OUTA                                       
OUTB                                       |OUTB                                       
BIAS                                       |BIAS                                       
GND                                        |GND                                        
SUB                                        |SUB                                        
VDD                                        |VDD                                        
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes output_buffer and output_buffer are equivalent.
Flattening unmatched subcell sky130_fd_pr__pfet_01v8_lvt_D3M934 in circuit bias_calc (0)(5 instances)
Flattening unmatched subcell sky130_fd_pr__pfet_01v8_lvt_D3Z634 in circuit bias_calc (0)(2 instances)
Flattening unmatched subcell sky130_fd_pr__nfet_01v8_lvt_9DHFGX in circuit bias_calc (0)(2 instances)
Flattening unmatched subcell sky130_fd_pr__res_high_po_2p85_MM89SS in circuit bias_calc (0)(1 instance)
Flattening unmatched subcell sky130_fd_pr__res_high_po_2p85_P79JE3 in circuit bias_calc (0)(1 instance)
Flattening unmatched subcell sky130_fd_pr__pfet_01v8_lvt_D3ZSZ4 in circuit bias_calc (0)(2 instances)

Class bias_calc (0):  Merged 167 parallel devices.
Class bias_calc (1):  Merged 3 parallel devices.
Subcircuit summary:
Circuit 1: bias_calc                       |Circuit 2: bias_calc                       
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_lvt (155->6)       |sky130_fd_pr__pfet_01v8_lvt (9->6)         
sky130_fd_pr__nfet_01v8_lvt (20->2)        |sky130_fd_pr__nfet_01v8_lvt (2)            
sky130_fd_pr__res_high_po_2p85 (2)         |sky130_fd_pr__res_high_po_2p85 (2)         
Number of devices: 10                      |Number of devices: 10                      
Number of nets: 14                         |Number of nets: 14                         
---------------------------------------------------------------------------------------
Circuits match uniquely.
Netlists match uniquely.

Subcircuit pins:
Circuit 1: bias_calc                       |Circuit 2: bias_calc                       
-------------------------------------------|-------------------------------------------
GND                                        |GND                                        
SUB                                        |SUB                                        
VOP                                        |VOP                                        
AMP                                        |AMP                                        
VCTRL                                      |VCTRL                                      
PSUB                                       |PSUB                                       
BIAS2V                                     |BIAS2V                                     
VDD                                        |VDD                                        
BIASOUT                                    |BIASOUT                                    
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes bias_calc and bias_calc are equivalent.

Subcircuit summary:
Circuit 1: core_osc                        |Circuit 2: core_osc                        
-------------------------------------------|-------------------------------------------
core_osc_amp (4)                           |core_osc_amp (4)                           
Number of devices: 4                       |Number of devices: 4                       
Number of nets: 12                         |Number of nets: 12                         
---------------------------------------------------------------------------------------
Circuits match uniquely.
Netlists match uniquely.

Subcircuit pins:
Circuit 1: core_osc                        |Circuit 2: core_osc                        
-------------------------------------------|-------------------------------------------
BIAS                                       |BIAS                                       
VDD                                        |VDD                                        
GND                                        |GND                                        
SUB                                        |SUB                                        
S4B                                        |S4B                                        
S4A                                        |S4A                                        
S2A                                        |S2A                                        
S1A                                        |S1A                                        
S3A                                        |S3A                                        
S2B                                        |S2B                                        
S1B                                        |S1B                                        
S3B                                        |S3B                                        
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes core_osc and core_osc are equivalent.

Subcircuit summary:
Circuit 1: buffer_amp_vop                  |Circuit 2: buffer_amp_vop                  
-------------------------------------------|-------------------------------------------
buffer_amp (4)                             |buffer_amp (4)                             
amp_dec (1)                                |amp_dec (1)                                
vop_dec (1)                                |vop_dec (1)                                
Number of devices: 6                       |Number of devices: 6                       
Number of nets: 19                         |Number of nets: 19                         
---------------------------------------------------------------------------------------
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match uniquely.
Circuits match correctly.

Subcircuit pins:
Circuit 1: buffer_amp_vop                  |Circuit 2: buffer_amp_vop                  
-------------------------------------------|-------------------------------------------
OUT0                                       |OUT0                                       
OUT180                                     |OUT180                                     
BIAS                                       |BIAS                                       
VDD                                        |VDD                                        
GND                                        |GND                                        
SUB                                        |SUB                                        
I2A                                        |I2A                                        
I4A                                        |I4A                                        
I2B                                        |I2B                                        
I4B                                        |I4B                                        
I3A                                        |I3A                                        
I1A                                        |I1A                                        
I3B                                        |I3B                                        
I1B                                        |I1B                                        
AMP                                        |AMP                                        
VOP                                        |VOP                                        
(no matching pin)                          |OUT90                                      
(no matching pin)                          |OUT270                                     
---------------------------------------------------------------------------------------
Cell pin lists for buffer_amp_vop and buffer_amp_vop altered to match.
Flattening unmatched subcell sky130_fd_pr__pfet_01v8_lvt_75KH85 in circuit VCO (0)(1 instance)

Class VCO (0):  Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: VCO                             |Circuit 2: VCO                             
-------------------------------------------|-------------------------------------------
cap_bank (8)                               |cap_bank (8)                               
output_buffer (1)                          |output_buffer (1)                          
bias_calc (1)                              |bias_calc (1)                              
sky130_fd_pr__pfet_01v8_lvt (3->1)         |sky130_fd_pr__pfet_01v8_lvt (1)            
core_osc (1)                               |core_osc (1)                               
buffer_amp_vop (1)                         |buffer_amp_vop (1)                         
Number of devices: 13                      |Number of devices: 13                      
Number of nets: 26                         |Number of nets: 26                         
---------------------------------------------------------------------------------------
Circuits match uniquely.
Netlists match uniquely.

Subcircuit pins:
Circuit 1: VCO                             |Circuit 2: VCO                             
-------------------------------------------|-------------------------------------------
bias_calc_0/VCTRL                          |VCTRL **Mismatch**                         
output_buffer_0/OUTA                       |OUT0 **Mismatch**                          
output_buffer_0/OUTB                       |OUT180 **Mismatch**                        
VDD                                        |VDD                                        
GND                                        |GND                                        
bias_calc_0/BIAS2V                         |REF **Mismatch**                           
CTRL1                                      |CTRL1                                      
CTRL2                                      |CTRL2                                      
CTRL3                                      |CTRL3                                      
CTRL4                                      |CTRL4                                      
CTRL5                                      |CTRL5                                      
---------------------------------------------------------------------------------------
Cell pin lists for VCO and VCO altered to match.

Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[0]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[10]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[11]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[12]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[13]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[14]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[15]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[16]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[17]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[1]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[2]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[3]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[4]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[5]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[6]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[7]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[8]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[9]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[0]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[10]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[11]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[12]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[13]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[14]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[15]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[16]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[17]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[1]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[2]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[3]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[4]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[5]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[6]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[7]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[8]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[9]
Cell user_analog_project_wrapper (0) disconnected node: io_analog[0]
Cell user_analog_project_wrapper (0) disconnected node: io_analog[1]
Cell user_analog_project_wrapper (0) disconnected node: io_analog[2]
Cell user_analog_project_wrapper (0) disconnected node: io_analog[3]
Cell user_analog_project_wrapper (0) disconnected node: io_analog[7]
Cell user_analog_project_wrapper (0) disconnected node: io_analog[4]
Cell user_analog_project_wrapper (0) disconnected node: io_analog[5]
Cell user_analog_project_wrapper (0) disconnected node: io_analog[6]
Cell user_analog_project_wrapper (0) disconnected node: io_clamp_high[0]
Cell user_analog_project_wrapper (0) disconnected node: io_clamp_high[1]
Cell user_analog_project_wrapper (0) disconnected node: io_clamp_high[2]
Cell user_analog_project_wrapper (0) disconnected node: io_clamp_low[0]
Cell user_analog_project_wrapper (0) disconnected node: io_clamp_low[1]
Cell user_analog_project_wrapper (0) disconnected node: io_clamp_low[2]
Cell user_analog_project_wrapper (0) disconnected node: io_in[0]
Cell user_analog_project_wrapper (0) disconnected node: io_in[10]
Cell user_analog_project_wrapper (0) disconnected node: io_in[11]
Cell user_analog_project_wrapper (0) disconnected node: io_in[12]
Cell user_analog_project_wrapper (0) disconnected node: io_in[13]
Cell user_analog_project_wrapper (0) disconnected node: io_in[15]
Cell user_analog_project_wrapper (0) disconnected node: io_in[19]
Cell user_analog_project_wrapper (0) disconnected node: io_in[1]
Cell user_analog_project_wrapper (0) disconnected node: io_in[20]
Cell user_analog_project_wrapper (0) disconnected node: io_in[21]
Cell user_analog_project_wrapper (0) disconnected node: io_in[22]
Cell user_analog_project_wrapper (0) disconnected node: io_in[23]
Cell user_analog_project_wrapper (0) disconnected node: io_in[24]
Cell user_analog_project_wrapper (0) disconnected node: io_in[25]
Cell user_analog_project_wrapper (0) disconnected node: io_in[26]
Cell user_analog_project_wrapper (0) disconnected node: io_in[2]
Cell user_analog_project_wrapper (0) disconnected node: io_in[3]
Cell user_analog_project_wrapper (0) disconnected node: io_in[4]
Cell user_analog_project_wrapper (0) disconnected node: io_in[5]
Cell user_analog_project_wrapper (0) disconnected node: io_in[6]
Cell user_analog_project_wrapper (0) disconnected node: io_in[7]
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Cell user_analog_project_wrapper (0) disconnected node: io_oeb[0]
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Cell user_analog_project_wrapper (0) disconnected node: io_out[0]
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Cell user_analog_project_wrapper (0) disconnected node: io_out[9]
Cell user_analog_project_wrapper (0) disconnected node: la_data_in[0]
Cell user_analog_project_wrapper (0) disconnected node: la_data_in[100]
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Cell user_analog_project_wrapper (0) disconnected node: la_data_in[12]
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Cell user_analog_project_wrapper (0) disconnected node: la_data_in[15]
Cell user_analog_project_wrapper (0) disconnected node: la_data_in[16]
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Cell user_analog_project_wrapper (0) disconnected node: la_data_in[1]
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Cell user_analog_project_wrapper (0) disconnected node: la_data_out[89]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[8]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[90]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[91]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[92]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[93]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[94]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[95]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[96]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[97]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[98]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[99]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[9]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[0]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[100]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[101]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[102]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[103]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[104]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[105]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[106]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[107]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[108]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[109]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[10]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[110]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[111]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[112]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[113]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[114]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[115]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[116]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[117]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[118]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[119]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[11]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[120]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[121]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[122]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[123]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[124]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[125]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[126]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[127]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[12]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[13]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[14]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[15]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[16]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[17]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[18]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[19]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[1]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[20]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[21]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[22]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[23]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[24]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[25]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[26]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[27]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[28]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[29]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[2]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[30]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[31]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[32]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[33]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[34]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[35]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[36]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[37]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[38]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[39]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[3]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[40]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[41]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[42]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[43]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[44]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[45]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[46]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[47]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[48]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[49]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[4]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[50]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[51]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[52]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[53]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[54]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[55]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[56]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[57]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[58]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[59]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[5]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[60]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[61]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[62]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[63]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[64]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[65]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[66]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[67]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[68]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[69]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[6]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[70]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[71]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[72]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[73]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[74]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[75]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[76]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[77]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[78]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[79]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[7]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[80]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[81]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[82]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[83]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[84]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[85]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[86]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[87]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[88]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[89]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[8]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[90]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[91]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[92]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[93]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[94]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[95]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[96]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[97]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[98]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[99]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[9]
Cell user_analog_project_wrapper (0) disconnected node: user_clock2
Cell user_analog_project_wrapper (0) disconnected node: user_irq[0]
Cell user_analog_project_wrapper (0) disconnected node: user_irq[1]
Cell user_analog_project_wrapper (0) disconnected node: user_irq[2]
Cell user_analog_project_wrapper (0) disconnected node: vccd1
Cell user_analog_project_wrapper (0) disconnected node: vdda1
Cell user_analog_project_wrapper (0) disconnected node: vdda2
Cell user_analog_project_wrapper (0) disconnected node: vssa1
Cell user_analog_project_wrapper (0) disconnected node: vssd1
Cell user_analog_project_wrapper (0) disconnected node: vssd2
Cell user_analog_project_wrapper (0) disconnected node: wb_clk_i
Cell user_analog_project_wrapper (0) disconnected node: wb_rst_i
Cell user_analog_project_wrapper (0) disconnected node: wbs_ack_o
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[0]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[10]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[11]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[12]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[13]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[14]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[15]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[16]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[17]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[18]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[19]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[1]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[20]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[21]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[22]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[23]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[24]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[25]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[26]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[27]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[28]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[29]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[2]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[30]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[31]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[3]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[4]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[5]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[6]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[7]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[8]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[9]
Cell user_analog_project_wrapper (0) disconnected node: wbs_cyc_i
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[0]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[10]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[11]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[12]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[13]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[14]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[15]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[16]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[17]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[18]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[19]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[1]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[20]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[21]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[22]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[23]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[24]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[25]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[26]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[27]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[28]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[29]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[2]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[30]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[31]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[3]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[4]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[5]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[6]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[7]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[8]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[9]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[0]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[10]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[11]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[12]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[13]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[14]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[15]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[16]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[17]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[18]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[19]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[1]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[20]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[21]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[22]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[23]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[24]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[25]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[26]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[27]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[28]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[29]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[2]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[30]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[31]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[3]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[4]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[5]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[6]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[7]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[8]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[9]
Cell user_analog_project_wrapper (0) disconnected node: wbs_sel_i[0]
Cell user_analog_project_wrapper (0) disconnected node: wbs_sel_i[1]
Cell user_analog_project_wrapper (0) disconnected node: wbs_sel_i[2]
Cell user_analog_project_wrapper (0) disconnected node: wbs_sel_i[3]
Cell user_analog_project_wrapper (0) disconnected node: wbs_stb_i
Cell user_analog_project_wrapper (0) disconnected node: wbs_we_i
Flattening instances of VCO in cell user_analog_project_wrapper (0) makes a better match
Making another compare attempt.

Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[0]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[10]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[11]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[12]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[13]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[14]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[15]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[16]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[17]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[1]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[2]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[3]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[4]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[5]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[6]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[7]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[8]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[9]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[0]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[10]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[11]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[12]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[13]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[14]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[15]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[16]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[17]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[1]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[2]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[3]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[4]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[5]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[6]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[7]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[8]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[9]
Cell user_analog_project_wrapper (0) disconnected node: io_analog[0]
Cell user_analog_project_wrapper (0) disconnected node: io_analog[1]
Cell user_analog_project_wrapper (0) disconnected node: io_analog[2]
Cell user_analog_project_wrapper (0) disconnected node: io_analog[3]
Cell user_analog_project_wrapper (0) disconnected node: io_analog[7]
Cell user_analog_project_wrapper (0) disconnected node: io_analog[4]
Cell user_analog_project_wrapper (0) disconnected node: io_analog[5]
Cell user_analog_project_wrapper (0) disconnected node: io_analog[6]
Cell user_analog_project_wrapper (0) disconnected node: io_clamp_high[0]
Cell user_analog_project_wrapper (0) disconnected node: io_clamp_high[1]
Cell user_analog_project_wrapper (0) disconnected node: io_clamp_high[2]
Cell user_analog_project_wrapper (0) disconnected node: io_clamp_low[0]
Cell user_analog_project_wrapper (0) disconnected node: io_clamp_low[1]
Cell user_analog_project_wrapper (0) disconnected node: io_clamp_low[2]
Cell user_analog_project_wrapper (0) disconnected node: io_in[0]
Cell user_analog_project_wrapper (0) disconnected node: io_in[10]
Cell user_analog_project_wrapper (0) disconnected node: io_in[11]
Cell user_analog_project_wrapper (0) disconnected node: io_in[12]
Cell user_analog_project_wrapper (0) disconnected node: io_in[13]
Cell user_analog_project_wrapper (0) disconnected node: io_in[15]
Cell user_analog_project_wrapper (0) disconnected node: io_in[19]
Cell user_analog_project_wrapper (0) disconnected node: io_in[1]
Cell user_analog_project_wrapper (0) disconnected node: io_in[20]
Cell user_analog_project_wrapper (0) disconnected node: io_in[21]
Cell user_analog_project_wrapper (0) disconnected node: io_in[22]
Cell user_analog_project_wrapper (0) disconnected node: io_in[23]
Cell user_analog_project_wrapper (0) disconnected node: io_in[24]
Cell user_analog_project_wrapper (0) disconnected node: io_in[25]
Cell user_analog_project_wrapper (0) disconnected node: io_in[26]
Cell user_analog_project_wrapper (0) disconnected node: io_in[2]
Cell user_analog_project_wrapper (0) disconnected node: io_in[3]
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Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[2]
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Cell user_analog_project_wrapper (0) disconnected node: io_oeb[0]
Cell user_analog_project_wrapper (0) disconnected node: io_oeb[10]
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Cell user_analog_project_wrapper (0) disconnected node: io_out[0]
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Cell user_analog_project_wrapper (0) disconnected node: la_data_in[0]
Cell user_analog_project_wrapper (0) disconnected node: la_data_in[100]
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Cell user_analog_project_wrapper (0) disconnected node: la_data_in[12]
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Cell user_analog_project_wrapper (0) disconnected node: la_data_out[85]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[86]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[87]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[88]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[89]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[8]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[90]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[91]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[92]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[93]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[94]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[95]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[96]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[97]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[98]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[99]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[9]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[0]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[100]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[101]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[102]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[103]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[104]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[105]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[106]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[107]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[108]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[109]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[10]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[110]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[111]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[112]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[113]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[114]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[115]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[116]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[117]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[118]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[119]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[11]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[120]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[121]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[122]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[123]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[124]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[125]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[126]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[127]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[12]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[13]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[14]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[15]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[16]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[17]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[18]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[19]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[1]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[20]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[21]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[22]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[23]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[24]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[25]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[26]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[27]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[28]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[29]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[2]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[30]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[31]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[32]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[33]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[34]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[35]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[36]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[37]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[38]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[39]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[3]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[40]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[41]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[42]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[43]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[44]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[45]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[46]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[47]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[48]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[49]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[4]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[50]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[51]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[52]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[53]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[54]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[55]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[56]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[57]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[58]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[59]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[5]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[60]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[61]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[62]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[63]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[64]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[65]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[66]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[67]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[68]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[69]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[6]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[70]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[71]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[72]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[73]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[74]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[75]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[76]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[77]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[78]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[79]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[7]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[80]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[81]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[82]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[83]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[84]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[85]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[86]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[87]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[88]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[89]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[8]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[90]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[91]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[92]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[93]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[94]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[95]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[96]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[97]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[98]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[99]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[9]
Cell user_analog_project_wrapper (0) disconnected node: user_clock2
Cell user_analog_project_wrapper (0) disconnected node: user_irq[0]
Cell user_analog_project_wrapper (0) disconnected node: user_irq[1]
Cell user_analog_project_wrapper (0) disconnected node: user_irq[2]
Cell user_analog_project_wrapper (0) disconnected node: vccd1
Cell user_analog_project_wrapper (0) disconnected node: vdda1
Cell user_analog_project_wrapper (0) disconnected node: vdda2
Cell user_analog_project_wrapper (0) disconnected node: vssa1
Cell user_analog_project_wrapper (0) disconnected node: vssd1
Cell user_analog_project_wrapper (0) disconnected node: vssd2
Cell user_analog_project_wrapper (0) disconnected node: wb_clk_i
Cell user_analog_project_wrapper (0) disconnected node: wb_rst_i
Cell user_analog_project_wrapper (0) disconnected node: wbs_ack_o
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[0]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[10]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[11]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[12]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[13]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[14]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[15]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[16]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[17]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[18]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[19]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[1]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[20]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[21]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[22]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[23]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[24]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[25]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[26]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[27]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[28]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[29]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[2]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[30]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[31]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[3]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[4]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[5]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[6]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[7]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[8]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[9]
Cell user_analog_project_wrapper (0) disconnected node: wbs_cyc_i
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[0]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[10]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[11]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[12]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[13]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[14]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[15]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[16]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[17]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[18]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[19]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[1]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[20]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[21]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[22]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[23]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[24]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[25]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[26]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[27]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[28]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[29]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[2]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[30]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[31]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[3]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[4]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[5]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[6]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[7]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[8]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[9]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[0]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[10]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[11]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[12]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[13]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[14]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[15]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[16]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[17]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[18]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[19]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[1]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[20]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[21]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[22]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[23]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[24]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[25]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[26]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[27]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[28]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[29]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[2]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[30]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[31]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[3]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[4]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[5]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[6]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[7]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[8]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[9]
Cell user_analog_project_wrapper (0) disconnected node: wbs_sel_i[0]
Cell user_analog_project_wrapper (0) disconnected node: wbs_sel_i[1]
Cell user_analog_project_wrapper (0) disconnected node: wbs_sel_i[2]
Cell user_analog_project_wrapper (0) disconnected node: wbs_sel_i[3]
Cell user_analog_project_wrapper (0) disconnected node: wbs_stb_i
Cell user_analog_project_wrapper (0) disconnected node: wbs_we_i
Flattening instances of core_osc in cell user_analog_project_wrapper (0) makes a better match
Flattening instances of cap_bank in cell user_analog_project_wrapper (0) makes a better match
Flattening instances of buffer_amp_vop in cell user_analog_project_wrapper (0) makes a better match
Flattening instances of output_buffer in cell user_analog_project_wrapper (0) makes a better match
Making another compare attempt.

Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[0]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[10]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[11]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[12]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[13]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[14]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[15]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[16]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[17]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[1]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[2]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[3]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[4]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[5]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[6]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[7]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[8]
Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[9]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[0]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[10]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[11]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[12]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[13]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[14]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[15]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[16]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[17]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[1]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[2]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[3]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[4]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[5]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[6]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[7]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[8]
Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[9]
Cell user_analog_project_wrapper (0) disconnected node: io_analog[0]
Cell user_analog_project_wrapper (0) disconnected node: io_analog[1]
Cell user_analog_project_wrapper (0) disconnected node: io_analog[2]
Cell user_analog_project_wrapper (0) disconnected node: io_analog[3]
Cell user_analog_project_wrapper (0) disconnected node: io_analog[7]
Cell user_analog_project_wrapper (0) disconnected node: io_analog[4]
Cell user_analog_project_wrapper (0) disconnected node: io_analog[5]
Cell user_analog_project_wrapper (0) disconnected node: io_analog[6]
Cell user_analog_project_wrapper (0) disconnected node: io_clamp_high[0]
Cell user_analog_project_wrapper (0) disconnected node: io_clamp_high[1]
Cell user_analog_project_wrapper (0) disconnected node: io_clamp_high[2]
Cell user_analog_project_wrapper (0) disconnected node: io_clamp_low[0]
Cell user_analog_project_wrapper (0) disconnected node: io_clamp_low[1]
Cell user_analog_project_wrapper (0) disconnected node: io_clamp_low[2]
Cell user_analog_project_wrapper (0) disconnected node: io_in[0]
Cell user_analog_project_wrapper (0) disconnected node: io_in[10]
Cell user_analog_project_wrapper (0) disconnected node: io_in[11]
Cell user_analog_project_wrapper (0) disconnected node: io_in[12]
Cell user_analog_project_wrapper (0) disconnected node: io_in[13]
Cell user_analog_project_wrapper (0) disconnected node: io_in[15]
Cell user_analog_project_wrapper (0) disconnected node: io_in[19]
Cell user_analog_project_wrapper (0) disconnected node: io_in[1]
Cell user_analog_project_wrapper (0) disconnected node: io_in[20]
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Cell user_analog_project_wrapper (0) disconnected node: io_in[2]
Cell user_analog_project_wrapper (0) disconnected node: io_in[3]
Cell user_analog_project_wrapper (0) disconnected node: io_in[4]
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Cell user_analog_project_wrapper (0) disconnected node: io_in[7]
Cell user_analog_project_wrapper (0) disconnected node: io_in[8]
Cell user_analog_project_wrapper (0) disconnected node: io_in[9]
Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[0]
Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[10]
Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[11]
Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[12]
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Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[16]
Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[17]
Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[18]
Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[19]
Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[1]
Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[20]
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Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[25]
Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[26]
Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[2]
Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[3]
Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[4]
Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[5]
Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[6]
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Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[8]
Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[9]
Cell user_analog_project_wrapper (0) disconnected node: io_oeb[0]
Cell user_analog_project_wrapper (0) disconnected node: io_oeb[10]
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Cell user_analog_project_wrapper (0) disconnected node: io_oeb[18]
Cell user_analog_project_wrapper (0) disconnected node: io_oeb[19]
Cell user_analog_project_wrapper (0) disconnected node: io_oeb[1]
Cell user_analog_project_wrapper (0) disconnected node: io_oeb[20]
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Cell user_analog_project_wrapper (0) disconnected node: io_oeb[8]
Cell user_analog_project_wrapper (0) disconnected node: io_oeb[9]
Cell user_analog_project_wrapper (0) disconnected node: io_out[0]
Cell user_analog_project_wrapper (0) disconnected node: io_out[10]
Cell user_analog_project_wrapper (0) disconnected node: io_out[11]
Cell user_analog_project_wrapper (0) disconnected node: io_out[12]
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Cell user_analog_project_wrapper (0) disconnected node: io_out[19]
Cell user_analog_project_wrapper (0) disconnected node: io_out[1]
Cell user_analog_project_wrapper (0) disconnected node: io_out[20]
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Cell user_analog_project_wrapper (0) disconnected node: io_out[22]
Cell user_analog_project_wrapper (0) disconnected node: io_out[23]
Cell user_analog_project_wrapper (0) disconnected node: io_out[24]
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Cell user_analog_project_wrapper (0) disconnected node: io_out[2]
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Cell user_analog_project_wrapper (0) disconnected node: io_out[8]
Cell user_analog_project_wrapper (0) disconnected node: io_out[9]
Cell user_analog_project_wrapper (0) disconnected node: la_data_in[0]
Cell user_analog_project_wrapper (0) disconnected node: la_data_in[100]
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Cell user_analog_project_wrapper (0) disconnected node: la_data_in[105]
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Cell user_analog_project_wrapper (0) disconnected node: la_data_in[110]
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Cell user_analog_project_wrapper (0) disconnected node: la_data_in[117]
Cell user_analog_project_wrapper (0) disconnected node: la_data_in[118]
Cell user_analog_project_wrapper (0) disconnected node: la_data_in[119]
Cell user_analog_project_wrapper (0) disconnected node: la_data_in[11]
Cell user_analog_project_wrapper (0) disconnected node: la_data_in[120]
Cell user_analog_project_wrapper (0) disconnected node: la_data_in[121]
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Cell user_analog_project_wrapper (0) disconnected node: la_data_in[12]
Cell user_analog_project_wrapper (0) disconnected node: la_data_in[13]
Cell user_analog_project_wrapper (0) disconnected node: la_data_in[14]
Cell user_analog_project_wrapper (0) disconnected node: la_data_in[15]
Cell user_analog_project_wrapper (0) disconnected node: la_data_in[16]
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Cell user_analog_project_wrapper (0) disconnected node: la_data_in[18]
Cell user_analog_project_wrapper (0) disconnected node: la_data_in[19]
Cell user_analog_project_wrapper (0) disconnected node: la_data_in[1]
Cell user_analog_project_wrapper (0) disconnected node: la_data_in[20]
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Cell user_analog_project_wrapper (0) disconnected node: la_data_in[2]
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Cell user_analog_project_wrapper (0) disconnected node: la_data_in[33]
Cell user_analog_project_wrapper (0) disconnected node: la_data_in[34]
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Cell user_analog_project_wrapper (0) disconnected node: la_data_in[48]
Cell user_analog_project_wrapper (0) disconnected node: la_data_in[49]
Cell user_analog_project_wrapper (0) disconnected node: la_data_in[4]
Cell user_analog_project_wrapper (0) disconnected node: la_data_in[50]
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Cell user_analog_project_wrapper (0) disconnected node: la_data_out[0]
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Cell user_analog_project_wrapper (0) disconnected node: la_data_out[1]
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Cell user_analog_project_wrapper (0) disconnected node: la_data_out[79]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[7]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[80]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[81]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[82]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[83]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[84]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[85]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[86]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[87]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[88]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[89]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[8]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[90]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[91]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[92]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[93]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[94]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[95]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[96]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[97]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[98]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[99]
Cell user_analog_project_wrapper (0) disconnected node: la_data_out[9]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[0]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[100]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[101]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[102]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[103]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[104]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[105]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[106]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[107]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[108]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[109]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[10]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[110]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[111]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[112]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[113]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[114]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[115]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[116]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[117]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[118]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[119]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[11]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[120]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[121]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[122]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[123]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[124]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[125]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[126]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[127]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[12]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[13]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[14]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[15]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[16]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[17]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[18]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[19]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[1]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[20]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[21]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[22]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[23]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[24]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[25]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[26]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[27]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[28]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[29]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[2]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[30]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[31]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[32]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[33]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[34]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[35]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[36]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[37]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[38]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[39]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[3]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[40]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[41]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[42]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[43]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[44]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[45]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[46]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[47]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[48]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[49]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[4]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[50]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[51]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[52]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[53]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[54]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[55]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[56]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[57]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[58]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[59]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[5]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[60]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[61]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[62]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[63]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[64]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[65]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[66]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[67]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[68]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[69]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[6]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[70]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[71]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[72]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[73]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[74]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[75]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[76]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[77]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[78]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[79]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[7]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[80]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[81]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[82]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[83]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[84]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[85]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[86]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[87]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[88]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[89]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[8]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[90]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[91]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[92]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[93]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[94]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[95]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[96]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[97]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[98]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[99]
Cell user_analog_project_wrapper (0) disconnected node: la_oenb[9]
Cell user_analog_project_wrapper (0) disconnected node: user_clock2
Cell user_analog_project_wrapper (0) disconnected node: user_irq[0]
Cell user_analog_project_wrapper (0) disconnected node: user_irq[1]
Cell user_analog_project_wrapper (0) disconnected node: user_irq[2]
Cell user_analog_project_wrapper (0) disconnected node: vccd1
Cell user_analog_project_wrapper (0) disconnected node: vdda1
Cell user_analog_project_wrapper (0) disconnected node: vdda2
Cell user_analog_project_wrapper (0) disconnected node: vssa1
Cell user_analog_project_wrapper (0) disconnected node: vssd1
Cell user_analog_project_wrapper (0) disconnected node: vssd2
Cell user_analog_project_wrapper (0) disconnected node: wb_clk_i
Cell user_analog_project_wrapper (0) disconnected node: wb_rst_i
Cell user_analog_project_wrapper (0) disconnected node: wbs_ack_o
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[0]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[10]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[11]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[12]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[13]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[14]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[15]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[16]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[17]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[18]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[19]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[1]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[20]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[21]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[22]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[23]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[24]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[25]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[26]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[27]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[28]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[29]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[2]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[30]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[31]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[3]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[4]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[5]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[6]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[7]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[8]
Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[9]
Cell user_analog_project_wrapper (0) disconnected node: wbs_cyc_i
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[0]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[10]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[11]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[12]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[13]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[14]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[15]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[16]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[17]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[18]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[19]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[1]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[20]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[21]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[22]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[23]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[24]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[25]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[26]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[27]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[28]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[29]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[2]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[30]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[31]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[3]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[4]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[5]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[6]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[7]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[8]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[9]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[0]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[10]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[11]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[12]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[13]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[14]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[15]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[16]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[17]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[18]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[19]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[1]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[20]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[21]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[22]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[23]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[24]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[25]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[26]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[27]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[28]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[29]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[2]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[30]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[31]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[3]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[4]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[5]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[6]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[7]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[8]
Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[9]
Cell user_analog_project_wrapper (0) disconnected node: wbs_sel_i[0]
Cell user_analog_project_wrapper (0) disconnected node: wbs_sel_i[1]
Cell user_analog_project_wrapper (0) disconnected node: wbs_sel_i[2]
Cell user_analog_project_wrapper (0) disconnected node: wbs_sel_i[3]
Cell user_analog_project_wrapper (0) disconnected node: wbs_stb_i
Cell user_analog_project_wrapper (0) disconnected node: wbs_we_i
Equate pins:  cell user_analog_project_wrapper and/or ../xschem/user_analog_project_wrapper.spice has no elements.

Subcircuit pins:
Circuit 1: user_analog_project_wrapper     |Circuit 2: ../xschem/user_analog_project_w 
-------------------------------------------|-------------------------------------------
gpio_analog[0]                             |(no matching pin)                          
gpio_analog[10]                            |(no matching pin)                          
gpio_analog[11]                            |(no matching pin)                          
gpio_analog[12]                            |(no matching pin)                          
gpio_analog[13]                            |(no matching pin)                          
gpio_analog[14]                            |(no matching pin)                          
gpio_analog[15]                            |(no matching pin)                          
gpio_analog[16]                            |(no matching pin)                          
gpio_analog[17]                            |(no matching pin)                          
gpio_analog[1]                             |(no matching pin)                          
gpio_analog[2]                             |(no matching pin)                          
gpio_analog[3]                             |(no matching pin)                          
gpio_analog[4]                             |(no matching pin)                          
gpio_analog[5]                             |(no matching pin)                          
gpio_analog[6]                             |(no matching pin)                          
gpio_analog[7]                             |(no matching pin)                          
gpio_analog[8]                             |(no matching pin)                          
gpio_analog[9]                             |(no matching pin)                          
gpio_noesd[0]                              |(no matching pin)                          
gpio_noesd[10]                             |(no matching pin)                          
gpio_noesd[11]                             |(no matching pin)                          
gpio_noesd[12]                             |(no matching pin)                          
gpio_noesd[13]                             |(no matching pin)                          
gpio_noesd[14]                             |(no matching pin)                          
gpio_noesd[15]                             |(no matching pin)                          
gpio_noesd[16]                             |(no matching pin)                          
gpio_noesd[17]                             |(no matching pin)                          
gpio_noesd[1]                              |(no matching pin)                          
gpio_noesd[2]                              |(no matching pin)                          
gpio_noesd[3]                              |(no matching pin)                          
gpio_noesd[4]                              |(no matching pin)                          
gpio_noesd[5]                              |(no matching pin)                          
gpio_noesd[6]                              |(no matching pin)                          
gpio_noesd[7]                              |(no matching pin)                          
gpio_noesd[8]                              |(no matching pin)                          
gpio_noesd[9]                              |(no matching pin)                          
io_analog[0]                               |(no matching pin)                          
io_analog[1]                               |(no matching pin)                          
io_analog[2]                               |(no matching pin)                          
io_analog[3]                               |(no matching pin)                          
io_analog[7]                               |(no matching pin)                          
io_analog[8]                               |(no matching pin)                          
io_analog[9]                               |(no matching pin)                          
io_analog[4]                               |(no matching pin)                          
io_analog[5]                               |(no matching pin)                          
io_analog[6]                               |(no matching pin)                          
io_clamp_high[0]                           |(no matching pin)                          
io_clamp_high[1]                           |(no matching pin)                          
io_clamp_high[2]                           |(no matching pin)                          
io_clamp_low[0]                            |(no matching pin)                          
io_clamp_low[1]                            |(no matching pin)                          
io_clamp_low[2]                            |(no matching pin)                          
io_in[0]                                   |(no matching pin)                          
io_in[10]                                  |(no matching pin)                          
io_in[11]                                  |(no matching pin)                          
io_in[12]                                  |(no matching pin)                          
io_in[13]                                  |(no matching pin)                          
io_in[14]                                  |(no matching pin)                          
io_in[15]                                  |(no matching pin)                          
io_in[16]                                  |(no matching pin)                          
io_in[17]                                  |(no matching pin)                          
io_in[18]                                  |(no matching pin)                          
io_in[19]                                  |(no matching pin)                          
io_in[1]                                   |(no matching pin)                          
io_in[20]                                  |(no matching pin)                          
io_in[21]                                  |(no matching pin)                          
io_in[22]                                  |(no matching pin)                          
io_in[23]                                  |(no matching pin)                          
io_in[24]                                  |(no matching pin)                          
io_in[25]                                  |(no matching pin)                          
io_in[26]                                  |(no matching pin)                          
io_in[2]                                   |(no matching pin)                          
io_in[3]                                   |(no matching pin)                          
io_in[4]                                   |(no matching pin)                          
io_in[5]                                   |(no matching pin)                          
io_in[6]                                   |(no matching pin)                          
io_in[7]                                   |(no matching pin)                          
io_in[8]                                   |(no matching pin)                          
io_in[9]                                   |(no matching pin)                          
io_in_3v3[0]                               |(no matching pin)                          
io_in_3v3[10]                              |(no matching pin)                          
io_in_3v3[11]                              |(no matching pin)                          
io_in_3v3[12]                              |(no matching pin)                          
io_in_3v3[13]                              |(no matching pin)                          
io_in_3v3[14]                              |(no matching pin)                          
io_in_3v3[15]                              |(no matching pin)                          
io_in_3v3[16]                              |(no matching pin)                          
io_in_3v3[17]                              |(no matching pin)                          
io_in_3v3[18]                              |(no matching pin)                          
io_in_3v3[19]                              |(no matching pin)                          
io_in_3v3[1]                               |(no matching pin)                          
io_in_3v3[20]                              |(no matching pin)                          
io_in_3v3[21]                              |(no matching pin)                          
io_in_3v3[22]                              |(no matching pin)                          
io_in_3v3[23]                              |(no matching pin)                          
io_in_3v3[24]                              |(no matching pin)                          
io_in_3v3[25]                              |(no matching pin)                          
io_in_3v3[26]                              |(no matching pin)                          
io_in_3v3[2]                               |(no matching pin)                          
io_in_3v3[3]                               |(no matching pin)                          
io_in_3v3[4]                               |(no matching pin)                          
io_in_3v3[5]                               |(no matching pin)                          
io_in_3v3[6]                               |(no matching pin)                          
io_in_3v3[7]                               |(no matching pin)                          
io_in_3v3[8]                               |(no matching pin)                          
io_in_3v3[9]                               |(no matching pin)                          
io_oeb[0]                                  |(no matching pin)                          
io_oeb[10]                                 |(no matching pin)                          
io_oeb[11]                                 |(no matching pin)                          
io_oeb[12]                                 |(no matching pin)                          
io_oeb[13]                                 |(no matching pin)                          
io_oeb[14]                                 |(no matching pin)                          
io_oeb[15]                                 |(no matching pin)                          
io_oeb[16]                                 |(no matching pin)                          
io_oeb[17]                                 |(no matching pin)                          
io_oeb[18]                                 |(no matching pin)                          
io_oeb[19]                                 |(no matching pin)                          
io_oeb[1]                                  |(no matching pin)                          
io_oeb[20]                                 |(no matching pin)                          
io_oeb[21]                                 |(no matching pin)                          
io_oeb[22]                                 |(no matching pin)                          
io_oeb[23]                                 |(no matching pin)                          
io_oeb[24]                                 |(no matching pin)                          
io_oeb[25]                                 |(no matching pin)                          
io_oeb[26]                                 |(no matching pin)                          
io_oeb[2]                                  |(no matching pin)                          
io_oeb[3]                                  |(no matching pin)                          
io_oeb[4]                                  |(no matching pin)                          
io_oeb[5]                                  |(no matching pin)                          
io_oeb[6]                                  |(no matching pin)                          
io_oeb[7]                                  |(no matching pin)                          
io_oeb[8]                                  |(no matching pin)                          
io_oeb[9]                                  |(no matching pin)                          
io_out[0]                                  |(no matching pin)                          
io_out[10]                                 |(no matching pin)                          
io_out[11]                                 |(no matching pin)                          
io_out[12]                                 |(no matching pin)                          
io_out[13]                                 |(no matching pin)                          
io_out[14]                                 |(no matching pin)                          
io_out[15]                                 |(no matching pin)                          
io_out[16]                                 |(no matching pin)                          
io_out[17]                                 |(no matching pin)                          
io_out[18]                                 |(no matching pin)                          
io_out[19]                                 |(no matching pin)                          
io_out[1]                                  |(no matching pin)                          
io_out[20]                                 |(no matching pin)                          
io_out[21]                                 |(no matching pin)                          
io_out[22]                                 |(no matching pin)                          
io_out[23]                                 |(no matching pin)                          
io_out[24]                                 |(no matching pin)                          
io_out[25]                                 |(no matching pin)                          
io_out[26]                                 |(no matching pin)                          
io_out[2]                                  |(no matching pin)                          
io_out[3]                                  |(no matching pin)                          
io_out[4]                                  |(no matching pin)                          
io_out[5]                                  |(no matching pin)                          
io_out[6]                                  |(no matching pin)                          
io_out[7]                                  |(no matching pin)                          
io_out[8]                                  |(no matching pin)                          
io_out[9]                                  |(no matching pin)                          
la_data_in[0]                              |(no matching pin)                          
la_data_in[100]                            |(no matching pin)                          
la_data_in[101]                            |(no matching pin)                          
la_data_in[102]                            |(no matching pin)                          
la_data_in[103]                            |(no matching pin)                          
la_data_in[104]                            |(no matching pin)                          
la_data_in[105]                            |(no matching pin)                          
la_data_in[106]                            |(no matching pin)                          
la_data_in[107]                            |(no matching pin)                          
la_data_in[108]                            |(no matching pin)                          
la_data_in[109]                            |(no matching pin)                          
la_data_in[10]                             |(no matching pin)                          
la_data_in[110]                            |(no matching pin)                          
la_data_in[111]                            |(no matching pin)                          
la_data_in[112]                            |(no matching pin)                          
la_data_in[113]                            |(no matching pin)                          
la_data_in[114]                            |(no matching pin)                          
la_data_in[115]                            |(no matching pin)                          
la_data_in[116]                            |(no matching pin)                          
la_data_in[117]                            |(no matching pin)                          
la_data_in[118]                            |(no matching pin)                          
la_data_in[119]                            |(no matching pin)                          
la_data_in[11]                             |(no matching pin)                          
la_data_in[120]                            |(no matching pin)                          
la_data_in[121]                            |(no matching pin)                          
la_data_in[122]                            |(no matching pin)                          
la_data_in[123]                            |(no matching pin)                          
la_data_in[124]                            |(no matching pin)                          
la_data_in[125]                            |(no matching pin)                          
la_data_in[126]                            |(no matching pin)                          
la_data_in[127]                            |(no matching pin)                          
la_data_in[12]                             |(no matching pin)                          
la_data_in[13]                             |(no matching pin)                          
la_data_in[14]                             |(no matching pin)                          
la_data_in[15]                             |(no matching pin)                          
la_data_in[16]                             |(no matching pin)                          
la_data_in[17]                             |(no matching pin)                          
la_data_in[18]                             |(no matching pin)                          
la_data_in[19]                             |(no matching pin)                          
la_data_in[1]                              |(no matching pin)                          
la_data_in[20]                             |(no matching pin)                          
la_data_in[21]                             |(no matching pin)                          
la_data_in[22]                             |(no matching pin)                          
la_data_in[23]                             |(no matching pin)                          
la_data_in[24]                             |(no matching pin)                          
la_data_in[25]                             |(no matching pin)                          
la_data_in[26]                             |(no matching pin)                          
la_data_in[27]                             |(no matching pin)                          
la_data_in[28]                             |(no matching pin)                          
la_data_in[29]                             |(no matching pin)                          
la_data_in[2]                              |(no matching pin)                          
la_data_in[30]                             |(no matching pin)                          
la_data_in[31]                             |(no matching pin)                          
la_data_in[32]                             |(no matching pin)                          
la_data_in[33]                             |(no matching pin)                          
la_data_in[34]                             |(no matching pin)                          
la_data_in[35]                             |(no matching pin)                          
la_data_in[36]                             |(no matching pin)                          
la_data_in[37]                             |(no matching pin)                          
la_data_in[38]                             |(no matching pin)                          
la_data_in[39]                             |(no matching pin)                          
la_data_in[3]                              |(no matching pin)                          
la_data_in[40]                             |(no matching pin)                          
la_data_in[41]                             |(no matching pin)                          
la_data_in[42]                             |(no matching pin)                          
la_data_in[43]                             |(no matching pin)                          
la_data_in[44]                             |(no matching pin)                          
la_data_in[45]                             |(no matching pin)                          
la_data_in[46]                             |(no matching pin)                          
la_data_in[47]                             |(no matching pin)                          
la_data_in[48]                             |(no matching pin)                          
la_data_in[49]                             |(no matching pin)                          
la_data_in[4]                              |(no matching pin)                          
la_data_in[50]                             |(no matching pin)                          
la_data_in[51]                             |(no matching pin)                          
la_data_in[52]                             |(no matching pin)                          
la_data_in[53]                             |(no matching pin)                          
la_data_in[54]                             |(no matching pin)                          
la_data_in[55]                             |(no matching pin)                          
la_data_in[56]                             |(no matching pin)                          
la_data_in[57]                             |(no matching pin)                          
la_data_in[58]                             |(no matching pin)                          
la_data_in[59]                             |(no matching pin)                          
la_data_in[5]                              |(no matching pin)                          
la_data_in[60]                             |(no matching pin)                          
la_data_in[61]                             |(no matching pin)                          
la_data_in[62]                             |(no matching pin)                          
la_data_in[63]                             |(no matching pin)                          
la_data_in[64]                             |(no matching pin)                          
la_data_in[65]                             |(no matching pin)                          
la_data_in[66]                             |(no matching pin)                          
la_data_in[67]                             |(no matching pin)                          
la_data_in[68]                             |(no matching pin)                          
la_data_in[69]                             |(no matching pin)                          
la_data_in[6]                              |(no matching pin)                          
la_data_in[70]                             |(no matching pin)                          
la_data_in[71]                             |(no matching pin)                          
la_data_in[72]                             |(no matching pin)                          
la_data_in[73]                             |(no matching pin)                          
la_data_in[74]                             |(no matching pin)                          
la_data_in[75]                             |(no matching pin)                          
la_data_in[76]                             |(no matching pin)                          
la_data_in[77]                             |(no matching pin)                          
la_data_in[78]                             |(no matching pin)                          
la_data_in[79]                             |(no matching pin)                          
la_data_in[7]                              |(no matching pin)                          
la_data_in[80]                             |(no matching pin)                          
la_data_in[81]                             |(no matching pin)                          
la_data_in[82]                             |(no matching pin)                          
la_data_in[83]                             |(no matching pin)                          
la_data_in[84]                             |(no matching pin)                          
la_data_in[85]                             |(no matching pin)                          
la_data_in[86]                             |(no matching pin)                          
la_data_in[87]                             |(no matching pin)                          
la_data_in[88]                             |(no matching pin)                          
la_data_in[89]                             |(no matching pin)                          
la_data_in[8]                              |(no matching pin)                          
la_data_in[90]                             |(no matching pin)                          
la_data_in[91]                             |(no matching pin)                          
la_data_in[92]                             |(no matching pin)                          
la_data_in[93]                             |(no matching pin)                          
la_data_in[94]                             |(no matching pin)                          
la_data_in[95]                             |(no matching pin)                          
la_data_in[96]                             |(no matching pin)                          
la_data_in[97]                             |(no matching pin)                          
la_data_in[98]                             |(no matching pin)                          
la_data_in[99]                             |(no matching pin)                          
la_data_in[9]                              |(no matching pin)                          
la_data_out[0]                             |(no matching pin)                          
la_data_out[100]                           |(no matching pin)                          
la_data_out[101]                           |(no matching pin)                          
la_data_out[102]                           |(no matching pin)                          
la_data_out[103]                           |(no matching pin)                          
la_data_out[104]                           |(no matching pin)                          
la_data_out[105]                           |(no matching pin)                          
la_data_out[106]                           |(no matching pin)                          
la_data_out[107]                           |(no matching pin)                          
la_data_out[108]                           |(no matching pin)                          
la_data_out[109]                           |(no matching pin)                          
la_data_out[10]                            |(no matching pin)                          
la_data_out[110]                           |(no matching pin)                          
la_data_out[111]                           |(no matching pin)                          
la_data_out[112]                           |(no matching pin)                          
la_data_out[113]                           |(no matching pin)                          
la_data_out[114]                           |(no matching pin)                          
la_data_out[115]                           |(no matching pin)                          
la_data_out[116]                           |(no matching pin)                          
la_data_out[117]                           |(no matching pin)                          
la_data_out[118]                           |(no matching pin)                          
la_data_out[119]                           |(no matching pin)                          
la_data_out[11]                            |(no matching pin)                          
la_data_out[120]                           |(no matching pin)                          
la_data_out[121]                           |(no matching pin)                          
la_data_out[122]                           |(no matching pin)                          
la_data_out[123]                           |(no matching pin)                          
la_data_out[124]                           |(no matching pin)                          
la_data_out[125]                           |(no matching pin)                          
la_data_out[126]                           |(no matching pin)                          
la_data_out[127]                           |(no matching pin)                          
la_data_out[12]                            |(no matching pin)                          
la_data_out[13]                            |(no matching pin)                          
la_data_out[14]                            |(no matching pin)                          
la_data_out[15]                            |(no matching pin)                          
la_data_out[16]                            |(no matching pin)                          
la_data_out[17]                            |(no matching pin)                          
la_data_out[18]                            |(no matching pin)                          
la_data_out[19]                            |(no matching pin)                          
la_data_out[1]                             |(no matching pin)                          
la_data_out[20]                            |(no matching pin)                          
la_data_out[21]                            |(no matching pin)                          
la_data_out[22]                            |(no matching pin)                          
la_data_out[23]                            |(no matching pin)                          
la_data_out[24]                            |(no matching pin)                          
la_data_out[25]                            |(no matching pin)                          
la_data_out[26]                            |(no matching pin)                          
la_data_out[27]                            |(no matching pin)                          
la_data_out[28]                            |(no matching pin)                          
la_data_out[29]                            |(no matching pin)                          
la_data_out[2]                             |(no matching pin)                          
la_data_out[30]                            |(no matching pin)                          
la_data_out[31]                            |(no matching pin)                          
la_data_out[32]                            |(no matching pin)                          
la_data_out[33]                            |(no matching pin)                          
la_data_out[34]                            |(no matching pin)                          
la_data_out[35]                            |(no matching pin)                          
la_data_out[36]                            |(no matching pin)                          
la_data_out[37]                            |(no matching pin)                          
la_data_out[38]                            |(no matching pin)                          
la_data_out[39]                            |(no matching pin)                          
la_data_out[3]                             |(no matching pin)                          
la_data_out[40]                            |(no matching pin)                          
la_data_out[41]                            |(no matching pin)                          
la_data_out[42]                            |(no matching pin)                          
la_data_out[43]                            |(no matching pin)                          
la_data_out[44]                            |(no matching pin)                          
la_data_out[45]                            |(no matching pin)                          
la_data_out[46]                            |(no matching pin)                          
la_data_out[47]                            |(no matching pin)                          
la_data_out[48]                            |(no matching pin)                          
la_data_out[49]                            |(no matching pin)                          
la_data_out[4]                             |(no matching pin)                          
la_data_out[50]                            |(no matching pin)                          
la_data_out[51]                            |(no matching pin)                          
la_data_out[52]                            |(no matching pin)                          
la_data_out[53]                            |(no matching pin)                          
la_data_out[54]                            |(no matching pin)                          
la_data_out[55]                            |(no matching pin)                          
la_data_out[56]                            |(no matching pin)                          
la_data_out[57]                            |(no matching pin)                          
la_data_out[58]                            |(no matching pin)                          
la_data_out[59]                            |(no matching pin)                          
la_data_out[5]                             |(no matching pin)                          
la_data_out[60]                            |(no matching pin)                          
la_data_out[61]                            |(no matching pin)                          
la_data_out[62]                            |(no matching pin)                          
la_data_out[63]                            |(no matching pin)                          
la_data_out[64]                            |(no matching pin)                          
la_data_out[65]                            |(no matching pin)                          
la_data_out[66]                            |(no matching pin)                          
la_data_out[67]                            |(no matching pin)                          
la_data_out[68]                            |(no matching pin)                          
la_data_out[69]                            |(no matching pin)                          
la_data_out[6]                             |(no matching pin)                          
la_data_out[70]                            |(no matching pin)                          
la_data_out[71]                            |(no matching pin)                          
la_data_out[72]                            |(no matching pin)                          
la_data_out[73]                            |(no matching pin)                          
la_data_out[74]                            |(no matching pin)                          
la_data_out[75]                            |(no matching pin)                          
la_data_out[76]                            |(no matching pin)                          
la_data_out[77]                            |(no matching pin)                          
la_data_out[78]                            |(no matching pin)                          
la_data_out[79]                            |(no matching pin)                          
la_data_out[7]                             |(no matching pin)                          
la_data_out[80]                            |(no matching pin)                          
la_data_out[81]                            |(no matching pin)                          
la_data_out[82]                            |(no matching pin)                          
la_data_out[83]                            |(no matching pin)                          
la_data_out[84]                            |(no matching pin)                          
la_data_out[85]                            |(no matching pin)                          
la_data_out[86]                            |(no matching pin)                          
la_data_out[87]                            |(no matching pin)                          
la_data_out[88]                            |(no matching pin)                          
la_data_out[89]                            |(no matching pin)                          
la_data_out[8]                             |(no matching pin)                          
la_data_out[90]                            |(no matching pin)                          
la_data_out[91]                            |(no matching pin)                          
la_data_out[92]                            |(no matching pin)                          
la_data_out[93]                            |(no matching pin)                          
la_data_out[94]                            |(no matching pin)                          
la_data_out[95]                            |(no matching pin)                          
la_data_out[96]                            |(no matching pin)                          
la_data_out[97]                            |(no matching pin)                          
la_data_out[98]                            |(no matching pin)                          
la_data_out[99]                            |(no matching pin)                          
la_data_out[9]                             |(no matching pin)                          
la_oenb[0]                                 |(no matching pin)                          
la_oenb[100]                               |(no matching pin)                          
la_oenb[101]                               |(no matching pin)                          
la_oenb[102]                               |(no matching pin)                          
la_oenb[103]                               |(no matching pin)                          
la_oenb[104]                               |(no matching pin)                          
la_oenb[105]                               |(no matching pin)                          
la_oenb[106]                               |(no matching pin)                          
la_oenb[107]                               |(no matching pin)                          
la_oenb[108]                               |(no matching pin)                          
la_oenb[109]                               |(no matching pin)                          
la_oenb[10]                                |(no matching pin)                          
la_oenb[110]                               |(no matching pin)                          
la_oenb[111]                               |(no matching pin)                          
la_oenb[112]                               |(no matching pin)                          
la_oenb[113]                               |(no matching pin)                          
la_oenb[114]                               |(no matching pin)                          
la_oenb[115]                               |(no matching pin)                          
la_oenb[116]                               |(no matching pin)                          
la_oenb[117]                               |(no matching pin)                          
la_oenb[118]                               |(no matching pin)                          
la_oenb[119]                               |(no matching pin)                          
la_oenb[11]                                |(no matching pin)                          
la_oenb[120]                               |(no matching pin)                          
la_oenb[121]                               |(no matching pin)                          
la_oenb[122]                               |(no matching pin)                          
la_oenb[123]                               |(no matching pin)                          
la_oenb[124]                               |(no matching pin)                          
la_oenb[125]                               |(no matching pin)                          
la_oenb[126]                               |(no matching pin)                          
la_oenb[127]                               |(no matching pin)                          
la_oenb[12]                                |(no matching pin)                          
la_oenb[13]                                |(no matching pin)                          
la_oenb[14]                                |(no matching pin)                          
la_oenb[15]                                |(no matching pin)                          
la_oenb[16]                                |(no matching pin)                          
la_oenb[17]                                |(no matching pin)                          
la_oenb[18]                                |(no matching pin)                          
la_oenb[19]                                |(no matching pin)                          
la_oenb[1]                                 |(no matching pin)                          
la_oenb[20]                                |(no matching pin)                          
la_oenb[21]                                |(no matching pin)                          
la_oenb[22]                                |(no matching pin)                          
la_oenb[23]                                |(no matching pin)                          
la_oenb[24]                                |(no matching pin)                          
la_oenb[25]                                |(no matching pin)                          
la_oenb[26]                                |(no matching pin)                          
la_oenb[27]                                |(no matching pin)                          
la_oenb[28]                                |(no matching pin)                          
la_oenb[29]                                |(no matching pin)                          
la_oenb[2]                                 |(no matching pin)                          
la_oenb[30]                                |(no matching pin)                          
la_oenb[31]                                |(no matching pin)                          
la_oenb[32]                                |(no matching pin)                          
la_oenb[33]                                |(no matching pin)                          
la_oenb[34]                                |(no matching pin)                          
la_oenb[35]                                |(no matching pin)                          
la_oenb[36]                                |(no matching pin)                          
la_oenb[37]                                |(no matching pin)                          
la_oenb[38]                                |(no matching pin)                          
la_oenb[39]                                |(no matching pin)                          
la_oenb[3]                                 |(no matching pin)                          
la_oenb[40]                                |(no matching pin)                          
la_oenb[41]                                |(no matching pin)                          
la_oenb[42]                                |(no matching pin)                          
la_oenb[43]                                |(no matching pin)                          
la_oenb[44]                                |(no matching pin)                          
la_oenb[45]                                |(no matching pin)                          
la_oenb[46]                                |(no matching pin)                          
la_oenb[47]                                |(no matching pin)                          
la_oenb[48]                                |(no matching pin)                          
la_oenb[49]                                |(no matching pin)                          
la_oenb[4]                                 |(no matching pin)                          
la_oenb[50]                                |(no matching pin)                          
la_oenb[51]                                |(no matching pin)                          
la_oenb[52]                                |(no matching pin)                          
la_oenb[53]                                |(no matching pin)                          
la_oenb[54]                                |(no matching pin)                          
la_oenb[55]                                |(no matching pin)                          
la_oenb[56]                                |(no matching pin)                          
la_oenb[57]                                |(no matching pin)                          
la_oenb[58]                                |(no matching pin)                          
la_oenb[59]                                |(no matching pin)                          
la_oenb[5]                                 |(no matching pin)                          
la_oenb[60]                                |(no matching pin)                          
la_oenb[61]                                |(no matching pin)                          
la_oenb[62]                                |(no matching pin)                          
la_oenb[63]                                |(no matching pin)                          
la_oenb[64]                                |(no matching pin)                          
la_oenb[65]                                |(no matching pin)                          
la_oenb[66]                                |(no matching pin)                          
la_oenb[67]                                |(no matching pin)                          
la_oenb[68]                                |(no matching pin)                          
la_oenb[69]                                |(no matching pin)                          
la_oenb[6]                                 |(no matching pin)                          
la_oenb[70]                                |(no matching pin)                          
la_oenb[71]                                |(no matching pin)                          
la_oenb[72]                                |(no matching pin)                          
la_oenb[73]                                |(no matching pin)                          
la_oenb[74]                                |(no matching pin)                          
la_oenb[75]                                |(no matching pin)                          
la_oenb[76]                                |(no matching pin)                          
la_oenb[77]                                |(no matching pin)                          
la_oenb[78]                                |(no matching pin)                          
la_oenb[79]                                |(no matching pin)                          
la_oenb[7]                                 |(no matching pin)                          
la_oenb[80]                                |(no matching pin)                          
la_oenb[81]                                |(no matching pin)                          
la_oenb[82]                                |(no matching pin)                          
la_oenb[83]                                |(no matching pin)                          
la_oenb[84]                                |(no matching pin)                          
la_oenb[85]                                |(no matching pin)                          
la_oenb[86]                                |(no matching pin)                          
la_oenb[87]                                |(no matching pin)                          
la_oenb[88]                                |(no matching pin)                          
la_oenb[89]                                |(no matching pin)                          
la_oenb[8]                                 |(no matching pin)                          
la_oenb[90]                                |(no matching pin)                          
la_oenb[91]                                |(no matching pin)                          
la_oenb[92]                                |(no matching pin)                          
la_oenb[93]                                |(no matching pin)                          
la_oenb[94]                                |(no matching pin)                          
la_oenb[95]                                |(no matching pin)                          
la_oenb[96]                                |(no matching pin)                          
la_oenb[97]                                |(no matching pin)                          
la_oenb[98]                                |(no matching pin)                          
la_oenb[99]                                |(no matching pin)                          
la_oenb[9]                                 |(no matching pin)                          
user_clock2                                |(no matching pin)                          
user_irq[0]                                |(no matching pin)                          
user_irq[1]                                |(no matching pin)                          
user_irq[2]                                |(no matching pin)                          
vccd1                                      |(no matching pin)                          
vccd2                                      |(no matching pin)                          
vdda1                                      |(no matching pin)                          
vdda2                                      |(no matching pin)                          
vssa1                                      |(no matching pin)                          
vssa2                                      |(no matching pin)                          
vssd1                                      |(no matching pin)                          
vssd2                                      |(no matching pin)                          
wb_clk_i                                   |(no matching pin)                          
wb_rst_i                                   |(no matching pin)                          
wbs_ack_o                                  |(no matching pin)                          
wbs_adr_i[0]                               |(no matching pin)                          
wbs_adr_i[10]                              |(no matching pin)                          
wbs_adr_i[11]                              |(no matching pin)                          
wbs_adr_i[12]                              |(no matching pin)                          
wbs_adr_i[13]                              |(no matching pin)                          
wbs_adr_i[14]                              |(no matching pin)                          
wbs_adr_i[15]                              |(no matching pin)                          
wbs_adr_i[16]                              |(no matching pin)                          
wbs_adr_i[17]                              |(no matching pin)                          
wbs_adr_i[18]                              |(no matching pin)                          
wbs_adr_i[19]                              |(no matching pin)                          
wbs_adr_i[1]                               |(no matching pin)                          
wbs_adr_i[20]                              |(no matching pin)                          
wbs_adr_i[21]                              |(no matching pin)                          
wbs_adr_i[22]                              |(no matching pin)                          
wbs_adr_i[23]                              |(no matching pin)                          
wbs_adr_i[24]                              |(no matching pin)                          
wbs_adr_i[25]                              |(no matching pin)                          
wbs_adr_i[26]                              |(no matching pin)                          
wbs_adr_i[27]                              |(no matching pin)                          
wbs_adr_i[28]                              |(no matching pin)                          
wbs_adr_i[29]                              |(no matching pin)                          
wbs_adr_i[2]                               |(no matching pin)                          
wbs_adr_i[30]                              |(no matching pin)                          
wbs_adr_i[31]                              |(no matching pin)                          
wbs_adr_i[3]                               |(no matching pin)                          
wbs_adr_i[4]                               |(no matching pin)                          
wbs_adr_i[5]                               |(no matching pin)                          
wbs_adr_i[6]                               |(no matching pin)                          
wbs_adr_i[7]                               |(no matching pin)                          
wbs_adr_i[8]                               |(no matching pin)                          
wbs_adr_i[9]                               |(no matching pin)                          
wbs_cyc_i                                  |(no matching pin)                          
wbs_dat_i[0]                               |(no matching pin)                          
wbs_dat_i[10]                              |(no matching pin)                          
wbs_dat_i[11]                              |(no matching pin)                          
wbs_dat_i[12]                              |(no matching pin)                          
wbs_dat_i[13]                              |(no matching pin)                          
wbs_dat_i[14]                              |(no matching pin)                          
wbs_dat_i[15]                              |(no matching pin)                          
wbs_dat_i[16]                              |(no matching pin)                          
wbs_dat_i[17]                              |(no matching pin)                          
wbs_dat_i[18]                              |(no matching pin)                          
wbs_dat_i[19]                              |(no matching pin)                          
wbs_dat_i[1]                               |(no matching pin)                          
wbs_dat_i[20]                              |(no matching pin)                          
wbs_dat_i[21]                              |(no matching pin)                          
wbs_dat_i[22]                              |(no matching pin)                          
wbs_dat_i[23]                              |(no matching pin)                          
wbs_dat_i[24]                              |(no matching pin)                          
wbs_dat_i[25]                              |(no matching pin)                          
wbs_dat_i[26]                              |(no matching pin)                          
wbs_dat_i[27]                              |(no matching pin)                          
wbs_dat_i[28]                              |(no matching pin)                          
wbs_dat_i[29]                              |(no matching pin)                          
wbs_dat_i[2]                               |(no matching pin)                          
wbs_dat_i[30]                              |(no matching pin)                          
wbs_dat_i[31]                              |(no matching pin)                          
wbs_dat_i[3]                               |(no matching pin)                          
wbs_dat_i[4]                               |(no matching pin)                          
wbs_dat_i[5]                               |(no matching pin)                          
wbs_dat_i[6]                               |(no matching pin)                          
wbs_dat_i[7]                               |(no matching pin)                          
wbs_dat_i[8]                               |(no matching pin)                          
wbs_dat_i[9]                               |(no matching pin)                          
wbs_dat_o[0]                               |(no matching pin)                          
wbs_dat_o[10]                              |(no matching pin)                          
wbs_dat_o[11]                              |(no matching pin)                          
wbs_dat_o[12]                              |(no matching pin)                          
wbs_dat_o[13]                              |(no matching pin)                          
wbs_dat_o[14]                              |(no matching pin)                          
wbs_dat_o[15]                              |(no matching pin)                          
wbs_dat_o[16]                              |(no matching pin)                          
wbs_dat_o[17]                              |(no matching pin)                          
wbs_dat_o[18]                              |(no matching pin)                          
wbs_dat_o[19]                              |(no matching pin)                          
wbs_dat_o[1]                               |(no matching pin)                          
wbs_dat_o[20]                              |(no matching pin)                          
wbs_dat_o[21]                              |(no matching pin)                          
wbs_dat_o[22]                              |(no matching pin)                          
wbs_dat_o[23]                              |(no matching pin)                          
wbs_dat_o[24]                              |(no matching pin)                          
wbs_dat_o[25]                              |(no matching pin)                          
wbs_dat_o[26]                              |(no matching pin)                          
wbs_dat_o[27]                              |(no matching pin)                          
wbs_dat_o[28]                              |(no matching pin)                          
wbs_dat_o[29]                              |(no matching pin)                          
wbs_dat_o[2]                               |(no matching pin)                          
wbs_dat_o[30]                              |(no matching pin)                          
wbs_dat_o[31]                              |(no matching pin)                          
wbs_dat_o[3]                               |(no matching pin)                          
wbs_dat_o[4]                               |(no matching pin)                          
wbs_dat_o[5]                               |(no matching pin)                          
wbs_dat_o[6]                               |(no matching pin)                          
wbs_dat_o[7]                               |(no matching pin)                          
wbs_dat_o[8]                               |(no matching pin)                          
wbs_dat_o[9]                               |(no matching pin)                          
wbs_sel_i[0]                               |(no matching pin)                          
wbs_sel_i[1]                               |(no matching pin)                          
wbs_sel_i[2]                               |(no matching pin)                          
wbs_sel_i[3]                               |(no matching pin)                          
wbs_stb_i                                  |(no matching pin)                          
wbs_we_i                                   |(no matching pin)                          
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes user_analog_project_wrapper and ../xschem/user_analog_project_wrapper.spice are equivalent.
Cells failed matching, or top level cell failed pin matching.