)]}'
{
  "commit": "1f729999abc809f3df6f249ba69648d55c96f92c",
  "tree": "3318bd376d12f1e1fc8329e1bfae339c6d62b272",
  "parents": [
    "e53eacf2965566f9bdfe51d04a0680ef7458ae7f"
  ],
  "author": {
    "name": "NohealthyBBQ",
    "email": "zexil@andrew.cmu.edu",
    "time": "Wed Nov 30 15:35:52 2022 -0500"
  },
  "committer": {
    "name": "NohealthyBBQ",
    "email": "zexil@andrew.cmu.edu",
    "time": "Wed Nov 30 15:35:52 2022 -0500"
  },
  "message": "Use GPIO_MODE_USER_STD_ANALOG mode for all GPIO\u0027s. This will make direct connections from the chip core to the pad\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "ee44b08843530ec77806ee6f6108e153f787af0e",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_defines.v",
      "new_id": "5eb64351e75485aa73c1a2397d1eedf609c6a121",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_defines.v"
    }
  ]
}