diff --git a/drc/gds.info b/drc/gds.info
new file mode 100644
index 0000000..bb62513
--- /dev/null
+++ b/drc/gds.info
@@ -0,0 +1 @@
+user_analog_project_wrapper.gds: 506c050c23c111a6cdbc7bf8a5f8707754735e03
\ No newline at end of file
diff --git a/drc/klayout_beol_check.log b/drc/klayout_beol_check.log
new file mode 100644
index 0000000..29c3e79
--- /dev/null
+++ b/drc/klayout_beol_check.log
@@ -0,0 +1,1005 @@
+/home/zexi/mpw_precheck/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::FEOL
+/home/zexi/mpw_precheck/checks/tech-files/sky130A_mr.drc:40: warning: previous definition of FEOL was here
+/home/zexi/mpw_precheck/checks/tech-files/sky130A_mr.drc:54: warning: already initialized constant DRC::DRCEngine::BEOL
+/home/zexi/mpw_precheck/checks/tech-files/sky130A_mr.drc:41: warning: previous definition of BEOL was here
+/home/zexi/mpw_precheck/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/home/zexi/mpw_precheck/checks/tech-files/sky130A_mr.drc:42: warning: previous definition of OFFGRID was here
+/home/zexi/mpw_precheck/checks/tech-files/sky130A_mr.drc:68: warning: already initialized constant DRC::DRCEngine::SEAL
+/home/zexi/mpw_precheck/checks/tech-files/sky130A_mr.drc:43: warning: previous definition of SEAL was here
+/home/zexi/mpw_precheck/checks/tech-files/sky130A_mr.drc:74: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/home/zexi/mpw_precheck/checks/tech-files/sky130A_mr.drc:44: warning: previous definition of FLOATING_MET was here
+"input" in: sky130A_mr.drc:124
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+START: 67/44 (mcon)
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+"interacting" in: sky130A_mr.drc:609
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+"output" in: sky130A_mr.drc:610
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1220.00M
+END: 70/44 (via3)
+START: 71/20 (m4)
+"width" in: sky130A_mr.drc:616
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1220.00M
+"output" in: sky130A_mr.drc:616
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1220.00M
+"sized" in: sky130A_mr.drc:618
+    Polygons (raw): 44 (flat)  31 (hierarchical)
+    Elapsed: 0.010s  Memory: 1220.00M
+"sized" in: sky130A_mr.drc:618
+    Polygons (raw): 44 (flat)  31 (hierarchical)
+    Elapsed: 0.010s  Memory: 1220.00M
+"snap" in: sky130A_mr.drc:618
+    Polygons (raw): 44 (flat)  31 (hierarchical)
+    Elapsed: 0.020s  Memory: 1220.00M
+"&" in: sky130A_mr.drc:618
+    Polygons (raw): 44 (flat)  31 (hierarchical)
+    Elapsed: 0.020s  Memory: 1220.00M
+"edges" in: sky130A_mr.drc:619
+    Edges: 875 (flat)  514 (hierarchical)
+    Elapsed: 0.020s  Memory: 1220.00M
+"-" in: sky130A_mr.drc:619
+    Edges: 602 (flat)  308 (hierarchical)
+    Elapsed: 0.020s  Memory: 1220.00M
+"edges" in: sky130A_mr.drc:620
+    Edges: 236 (flat)  184 (hierarchical)
+    Elapsed: 0.010s  Memory: 1220.00M
+"merged" in: sky130A_mr.drc:620
+    Polygons (raw): 88 (flat)  50 (hierarchical)
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+"outside_part" in: sky130A_mr.drc:620
+    Edges: 258 (flat)  199 (hierarchical)
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+"with_area" in: sky130A_mr.drc:624
+    Polygons (raw): 0 (flat)  0 (hierarchical)
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+"output" in: sky130A_mr.drc:624
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+    Elapsed: 0.010s  Memory: 1220.00M
+"separation" in: sky130A_mr.drc:626
+    Edge pairs: 0 (flat)  0 (hierarchical)
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+"space" in: sky130A_mr.drc:626
+    Edge pairs: 0 (flat)  0 (hierarchical)
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+    Edge pairs: 0 (flat)  0 (hierarchical)
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+"output" in: sky130A_mr.drc:626
+    Edge pairs: 0 (flat)  0 (hierarchical)
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+"enclosing" in: sky130A_mr.drc:631
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.780s  Memory: 1220.00M
+"output" in: sky130A_mr.drc:631
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+"not" in: sky130A_mr.drc:632
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+"output" in: sky130A_mr.drc:632
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1220.00M
+END: 71/20 (m4)
+START: 71/44 (via4)
+"not" in: sky130A_mr.drc:645
+    Polygons (raw): 5736 (flat)  5610 (hierarchical)
+    Elapsed: 0.010s  Memory: 1220.00M
+"non_rectangles" in: sky130A_mr.drc:646
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+    Edge pairs: 0 (flat)  0 (hierarchical)
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+"drc" in: sky130A_mr.drc:648
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+"space" in: sky130A_mr.drc:650
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+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1220.00M
+END: 71/44 (via4)
+START: 72/20 (m5)
+"width" in: sky130A_mr.drc:664
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1220.00M
+"output" in: sky130A_mr.drc:664
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1220.00M
+"space" in: sky130A_mr.drc:666
+    Edge pairs: 0 (flat)  0 (hierarchical)
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+"output" in: sky130A_mr.drc:666
+    Edge pairs: 0 (flat)  0 (hierarchical)
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+"enclosing" in: sky130A_mr.drc:668
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.080s  Memory: 1220.00M
+"output" in: sky130A_mr.drc:668
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+"output" in: sky130A_mr.drc:669
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+    Elapsed: 0.010s  Memory: 1220.00M
+"with_area" in: sky130A_mr.drc:673
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1220.00M
+"output" in: sky130A_mr.drc:673
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1220.00M
+END: 72/20 (m5)
+START: 76/20 (pad)
+"space" in: sky130A_mr.drc:678
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1220.00M
+"output" in: sky130A_mr.drc:678
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1220.00M
+END: 76/20 (pad)
+Writing report database: /home/zexi/project/sloci_caravel/precheck_results/12_SEP_2022___13_36_36/outputs/reports/klayout_beol_check.xml ..
+Total elapsed: 23.380s  Memory: 1218.00M
+ 
+Cell exclusion list:
+   rule    | cell
+   nwell.6 | sky130_fd_io__gpiov2_amux, sky130_fd_io__simple_pad_and_busses, sram
+   nsd.1   | sram
+   nsd.2   | sram
+   psd.1   | sram
+   psd.2   | sram
+ 
+release 2022.6.30_01.07
diff --git a/drc/klayout_beol_check.total b/drc/klayout_beol_check.total
new file mode 100644
index 0000000..19c7bdb
--- /dev/null
+++ b/drc/klayout_beol_check.total
@@ -0,0 +1 @@
+16
\ No newline at end of file
diff --git a/drc/klayout_beol_check.xml b/drc/klayout_beol_check.xml
new file mode 100644
index 0000000..6ade9d3
--- /dev/null
+++ b/drc/klayout_beol_check.xml
@@ -0,0 +1,633 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/home/zexi/mpw_precheck/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>li.1</name>
+   <description>li.1 : min. li width : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.3</name>
+   <description>li.3 : min. li spacing : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.5</name>
+   <description>li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.6</name>
+   <description>li.6 : min. li area : 0.0561um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1</name>
+   <description>ct.1: non-ring mcon should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1_a</name>
+   <description>ct.1_a : minimum width of mcon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1_b</name>
+   <description>ct.1_b : maximum length of mcon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.2</name>
+   <description>ct.2 : min. mcon spacing : 0.19um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.4</name>
+   <description>ct.4 : mcon should covered by li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.1</name>
+   <description>m1.1 : min. m1 width : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.2</name>
+   <description>m1.2 : min. m1 spacing : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.3ab</name>
+   <description>m1.3ab : min. 3um.m1 spacing m1 : 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>791_m1.4</name>
+   <description>791_m1.4 : min. m1 enclosure of mcon : 0.03um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4</name>
+   <description>m1.4 : mcon periphery must be enclosed by m1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4a</name>
+   <description>m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4a_a</name>
+   <description>m1.4a_a : mcon periph must be enclosed by met1 for specific cells</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.6</name>
+   <description>m1.6 : min. m1 area : 0.083um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.7</name>
+   <description>m1.7 : min. m1 with holes area : 0.14um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.5</name>
+   <description>m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a</name>
+   <description>via.1a : via outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a_a</name>
+   <description>via.1a_a : min. width of via outside of moduleCut : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a_b</name>
+   <description>via.1a_b : maximum length of via : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.2</name>
+   <description>via.2 : min. via spacing : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.4a</name>
+   <description>via.4a : min. m1 enclosure of 0.15um via : 0.055um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.4a_a</name>
+   <description>via.4a_a : 0.15um via must be enclosed by met1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.5a</name>
+   <description>via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.1</name>
+   <description>m2.1 : min. m2 width : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.2</name>
+   <description>m2.2 : min. m2 spacing : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.3ab</name>
+   <description>m2.3ab : min. 3um.m2 spacing m2 : 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.6</name>
+   <description>m2.6 : min. m2 area : 0.0676um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.7</name>
+   <description>m2.7 : min. m2 holes area : 0.14um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.4</name>
+   <description>m2.4 : min. m2 enclosure of via : 0.055um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.4_a</name>
+   <description>m2.4_a : via in periphery must be enclosed by met2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.5</name>
+   <description>m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a</name>
+   <description>via2.1a : via2 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a_a</name>
+   <description>via2.1a_a : min. width of via2 outside of moduleCut : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a_b</name>
+   <description>via2.1a_b : maximum length of via2 : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.2</name>
+   <description>via2.2 : min. via2 spacing : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.4</name>
+   <description>via2.4 : min. m2 enclosure of via2 : 0.04um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.4_a</name>
+   <description>via2.4_a : via must be enclosed by met2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.5</name>
+   <description>via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.1</name>
+   <description>m3.1 : min. m3 width : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.2</name>
+   <description>m3.2 : min. m3 spacing : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.3cd</name>
+   <description>m3.3cd : min. 3um.m3 spacing m3 : 0.4um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.4</name>
+   <description>m3.4 : min. m3 enclosure of via2 : 0.065um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.4_a</name>
+   <description>m3.4_a : via2 must be enclosed by met3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1</name>
+   <description>via3.1 : via3 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1_a</name>
+   <description>via3.1_a : min. width of via3 outside of moduleCut : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1_b</name>
+   <description>via3.1_b : maximum length of via3 : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.2</name>
+   <description>via3.2 : min. via3 spacing : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.4</name>
+   <description>via3.4 : min. m3 enclosure of via3 : 0.06um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.4_a</name>
+   <description>via3.4_a : non-ring via3 must be enclosed by met3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.5</name>
+   <description>via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.1</name>
+   <description>m4.1 : min. m4 width : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.2</name>
+   <description>m4.2 : min. m4 spacing : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.4a</name>
+   <description>m4.4a : min. m4 area : 0.240um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.5ab</name>
+   <description>m4.5ab : min. 3um.m4 spacing m4 : 0.4um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.3</name>
+   <description>m4.3 : min. m4 enclosure of via3 : 0.065um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.3_a</name>
+   <description>m4.3_a : via3 must be enclosed by met4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1</name>
+   <description>via4.1 : via4 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1_a</name>
+   <description>via4.1_a : min. width of via4 outside of moduleCut : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1_b</name>
+   <description>via4.1_b : maximum length of via4 : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.2</name>
+   <description>via4.2 : min. via4 spacing : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.4</name>
+   <description>via4.4 : min. m4 enclosure of via4 : 0.19um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.4_a</name>
+   <description>via4.4_a : m4 must enclose all via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.1</name>
+   <description>m5.1 : min. m5 width : 1.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.2</name>
+   <description>m5.2 : min. m5 spacing : 1.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.3</name>
+   <description>m5.3 : min. m5 enclosure of via4 : 0.31um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.3_a</name>
+   <description>m5.3_a : via must be enclosed by m5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.4</name>
+   <description>m5.4 : min. m5 area : 4.0um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad.2</name>
+   <description>pad.2 : min. pad spacing : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_analog_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+  <cell>
+   <name>VCO</name>
+   <variant/>
+   <references>
+    <ref>
+     <parent>user_analog_project_wrapper</parent>
+     <trans>r0 *1 -39.185,3193.71</trans>
+    </ref>
+   </references>
+  </cell>
+ </cells>
+ <items>
+  <item>
+   <tags/>
+   <category>'m2.3ab'</category>
+   <cell>VCO</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>edge-pair: (313.2,181.175;313.2,181.342)/(312.975,181.175;312.975,181.008)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'m2.3ab'</category>
+   <cell>VCO</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>edge-pair: (302.7,181.175;302.7,181.342)/(302.475,181.175;302.475,181.008)</value>
+   </values>
+  </item>
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+   <category>'m2.3ab'</category>
+   <cell>VCO</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>edge-pair: (295.9,181.342;295.9,181.175)/(296.125,181.008;296.125,181.175)</value>
+   </values>
+  </item>
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+   <category>'m2.3ab'</category>
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+   <image/>
+   <values>
+    <value>edge-pair: (292.2,181.175;292.2,181.342)/(291.975,181.175;291.975,181.008)</value>
+   </values>
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+   <image/>
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+   </values>
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+   <category>'m2.3ab'</category>
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+   <visited>false</visited>
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+   <image/>
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+   </values>
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+   <category>'m2.3ab'</category>
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+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
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+    <value>edge-pair: (285.4,106.975;285.4,106.808)/(285.625,106.975;285.625,107.142)</value>
+   </values>
+  </item>
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+   <category>'m2.3ab'</category>
+   <cell>VCO</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>edge-pair: (316.9,106.975;316.9,106.808)/(317.125,106.975;317.125,107.142)</value>
+   </values>
+  </item>
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+   <tags/>
+   <category>'m2.3ab'</category>
+   <cell>VCO</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>edge-pair: (292.2,106.808;292.2,106.975)/(291.975,107.142;291.975,106.975)</value>
+   </values>
+  </item>
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+   <category>'m2.3ab'</category>
+   <cell>VCO</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>edge-pair: (316.9,181.342;316.9,181.175)/(317.125,181.008;317.125,181.175)</value>
+   </values>
+  </item>
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+   <tags/>
+   <category>'m2.3ab'</category>
+   <cell>VCO</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>edge-pair: (281.7,181.175;281.7,181.342)/(281.475,181.175;281.475,181.008)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'m2.3ab'</category>
+   <cell>VCO</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>edge-pair: (285.4,181.342;285.4,181.175)/(285.625,181.008;285.625,181.175)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'m2.3ab'</category>
+   <cell>VCO</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>edge-pair: (306.4,181.342;306.4,181.175)/(306.625,181.008;306.625,181.175)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'m2.3ab'</category>
+   <cell>VCO</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>edge-pair: (295.9,106.975;295.9,106.808)/(296.125,106.975;296.125,107.142)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'m2.3ab'</category>
+   <cell>VCO</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>edge-pair: (302.7,106.808;302.7,106.975)/(302.475,107.142;302.475,106.975)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'m2.3ab'</category>
+   <cell>VCO</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>edge-pair: (306.4,106.975;306.4,106.808)/(306.625,106.975;306.625,107.142)</value>
+   </values>
+  </item>
+ </items>
+</report-database>
diff --git a/drc/klayout_feol_check.log b/drc/klayout_feol_check.log
new file mode 100644
index 0000000..5dd3ccd
--- /dev/null
+++ b/drc/klayout_feol_check.log
@@ -0,0 +1,817 @@
+/home/zexi/mpw_precheck/checks/tech-files/sky130A_mr.drc:48: warning: already initialized constant DRC::DRCEngine::FEOL
+/home/zexi/mpw_precheck/checks/tech-files/sky130A_mr.drc:40: warning: previous definition of FEOL was here
+/home/zexi/mpw_precheck/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::BEOL
+/home/zexi/mpw_precheck/checks/tech-files/sky130A_mr.drc:41: warning: previous definition of BEOL was here
+/home/zexi/mpw_precheck/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/home/zexi/mpw_precheck/checks/tech-files/sky130A_mr.drc:42: warning: previous definition of OFFGRID was here
+/home/zexi/mpw_precheck/checks/tech-files/sky130A_mr.drc:68: warning: already initialized constant DRC::DRCEngine::SEAL
+/home/zexi/mpw_precheck/checks/tech-files/sky130A_mr.drc:43: warning: previous definition of SEAL was here
+/home/zexi/mpw_precheck/checks/tech-files/sky130A_mr.drc:74: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/home/zexi/mpw_precheck/checks/tech-files/sky130A_mr.drc:44: warning: previous definition of FLOATING_MET was here
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+START: 97/44 (cap2m)
+"width" in: sky130A_mr.drc:380
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1096.00M
+"output" in: sky130A_mr.drc:380
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1096.00M
+"space" in: sky130A_mr.drc:381
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1096.00M
+"output" in: sky130A_mr.drc:381
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1096.00M
+"interacting" in: sky130A_mr.drc:382
+    Polygons (raw): 40 (flat)  5 (hierarchical)
+    Elapsed: 0.010s  Memory: 1096.00M
+"isolated" in: sky130A_mr.drc:382
+    Edge pairs: 64 (flat)  8 (hierarchical)
+    Elapsed: 0.020s  Memory: 1096.00M
+"output" in: sky130A_mr.drc:382
+    Edge pairs: 64 (flat)  8 (hierarchical)
+    Elapsed: 0.010s  Memory: 1096.00M
+"interacting" in: sky130A_mr.drc:383
+    Polygons (raw): 40 (flat)  5 (hierarchical)
+    Elapsed: 0.010s  Memory: 1096.00M
+"isolated" in: sky130A_mr.drc:383
+    Edge pairs: 64 (flat)  8 (hierarchical)
+    Elapsed: 0.020s  Memory: 1096.00M
+"output" in: sky130A_mr.drc:383
+    Edge pairs: 64 (flat)  8 (hierarchical)
+    Elapsed: 0.010s  Memory: 1096.00M
+"and" in: sky130A_mr.drc:384
+    Polygons (raw): 40 (flat)  5 (hierarchical)
+    Elapsed: 0.010s  Memory: 1096.00M
+"enclosing" in: sky130A_mr.drc:384
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.020s  Memory: 1096.00M
+"output" in: sky130A_mr.drc:384
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1096.00M
+"enclosing" in: sky130A_mr.drc:385
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1096.00M
+"output" in: sky130A_mr.drc:385
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1096.00M
+"enclosing" in: sky130A_mr.drc:386
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1096.00M
+"output" in: sky130A_mr.drc:386
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1096.00M
+"separation" in: sky130A_mr.drc:387
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1096.00M
+"output" in: sky130A_mr.drc:387
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1096.00M
+"not_interacting" in: sky130A_mr.drc:388
+    Polygons (raw): 48 (flat)  39 (hierarchical)
+    Elapsed: 0.010s  Memory: 1096.00M
+"separation" in: sky130A_mr.drc:388
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1096.00M
+"output" in: sky130A_mr.drc:388
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1096.00M
+END: 97/44 (cap2m)
+FEOL section
+START: 75/20 (hvi)
+"not" in: sky130A_mr.drc:688
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1096.00M
+"width" in: sky130A_mr.drc:689
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1096.00M
+"output" in: sky130A_mr.drc:689
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1096.00M
+"space" in: sky130A_mr.drc:690
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1096.00M
+"output" in: sky130A_mr.drc:690
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1096.00M
+END: 75/20 (hvi)
+START: 125/20 (hvntm)
+"not" in: sky130A_mr.drc:695
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1096.00M
+"width" in: sky130A_mr.drc:696
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1096.00M
+"output" in: sky130A_mr.drc:696
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1096.00M
+"space" in: sky130A_mr.drc:697
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1096.00M
+"output" in: sky130A_mr.drc:697
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1096.00M
+END: 125/20 (hvntm)
+Writing report database: /home/zexi/project/sloci_caravel/precheck_results/12_SEP_2022___13_36_36/outputs/reports/klayout_feol_check.xml ..
+Total elapsed: 3.960s  Memory: 1094.00M
+ 
+Cell exclusion list:
+   rule    | cell
+   nwell.6 | sky130_fd_io__gpiov2_amux, sky130_fd_io__simple_pad_and_busses, sram
+   nsd.1   | sram
+   nsd.2   | sram
+   psd.1   | sram
+   psd.2   | sram
+ 
+release 2022.6.30_01.07
diff --git a/drc/klayout_feol_check.total b/drc/klayout_feol_check.total
new file mode 100644
index 0000000..8e2afd3
--- /dev/null
+++ b/drc/klayout_feol_check.total
@@ -0,0 +1 @@
+17
\ No newline at end of file
diff --git a/drc/klayout_feol_check.xml b/drc/klayout_feol_check.xml
new file mode 100644
index 0000000..6cee646
--- /dev/null
+++ b/drc/klayout_feol_check.xml
@@ -0,0 +1,602 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/home/zexi/mpw_precheck/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>dnwell.2</name>
+   <description>dnwell.2 : min. dnwell width : 3.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell.1</name>
+   <description>nwell.1 : min. nwell width : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell.2a</name>
+   <description>nwell.2a : min. nwell spacing (merged if less) : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell.6</name>
+   <description>nwell.6 : min enclosure of nwellHole by dnwell : 1.03um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp.1</name>
+   <description>hvtp.1 : min. hvtp width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp.2</name>
+   <description>hvtp.2 : min. hvtp spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.1</name>
+   <description>hvtr.1 : min. hvtr width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.2</name>
+   <description>hvtr.2 : min. hvtr spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.2_a</name>
+   <description>hvtr.2_a : hvtr must not overlap hvtp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn.1a</name>
+   <description>lvtn.1a : min. lvtn width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn.2</name>
+   <description>lvtn.2 : min. lvtn spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm.1</name>
+   <description>ncm.1 : min. ncm width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm.2a</name>
+   <description>ncm.2a : min. ncm spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1</name>
+   <description>difftap.1 : min. diff width across areaid:ce : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_a</name>
+   <description>difftap.1_a : min. diff width in periphery : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_b</name>
+   <description>difftap.1_b : min. tap width across areaid:ce : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_c</name>
+   <description>difftap.1_c : min. tap width in periphery : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.3</name>
+   <description>difftap.3 : min. difftap spacing : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm.1</name>
+   <description>tunm.1 : min. tunm width : 0.41um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm.2</name>
+   <description>tunm.2 : min. tunm spacing : 0.5um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly.1a</name>
+   <description>poly.1a : min. poly width : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly.2</name>
+   <description>poly.2 : min. poly spacing : 0.21um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm.1a</name>
+   <description>rpm.1a : min. rpm width : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm.2</name>
+   <description>rpm.2 : min. rpm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>urpm.1a</name>
+   <description>urpm.1a : min. rpm width : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>urpm.2</name>
+   <description>urpm.2 : min. rpm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc.1</name>
+   <description>npc.1 : min. npc width : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc.2</name>
+   <description>npc.2 : min. npc spacing, should be manually merged if less than : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsd.1</name>
+   <description>nsd.1 : min. nsdm width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsd.2</name>
+   <description>nsd.2 : min. nsdm spacing, should be manually merged if less than : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psd.1</name>
+   <description>psd.1 : min. psdm width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psd.2</name>
+   <description>psd.2 : min. psdm spacing, should be manually merged if less than : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.1</name>
+   <description>licon.1 : licon should be rectangle</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.1_a/b</name>
+   <description>licon.1_a/b : minimum/maximum width of licon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.13</name>
+   <description>licon.13 : min. difftap licon spacing to npc : 0.09um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.13_a</name>
+   <description>licon.13_a : licon of diffTap in periphery must not overlap npc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.17</name>
+   <description>licon.17 : Licons may not overlap both poly and (diff or tap)</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.1</name>
+   <description>capm.1 : min. capm width : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2a</name>
+   <description>capm.2a : min. capm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2b</name>
+   <description>capm.2b : min. capm spacing : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2b_a</name>
+   <description>capm.2b_a : min. spacing of m3_bot_plate : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.3</name>
+   <description>capm.3 : min. capm and m3 enclosure of m3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.3_a</name>
+   <description>capm.3_a : min. m3 enclosure of capm : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.4</name>
+   <description>capm.4 : min. capm enclosure of via3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.5</name>
+   <description>capm.5 : min. capm spacing to via3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.11</name>
+   <description>capm.11 : Min spacing of capm and met3 not overlapping capm : 0.5um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.1</name>
+   <description>cap2m.1 : min. cap2m width : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2a</name>
+   <description>cap2m.2a : min. cap2m spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2b</name>
+   <description>cap2m.2b : min. cap2m spacing : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2b_a</name>
+   <description>cap2m.2b_a : min. spacing of m4_bot_plate : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.3</name>
+   <description>cap2m.3 : min. m4 enclosure of cap2m : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.3_a</name>
+   <description>cap2m.3_a : min. m4 enclosure of cap2m : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.4</name>
+   <description>cap2m.4 : min. cap2m enclosure of via4 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.5</name>
+   <description>cap2m.5 : min. cap2m spacing to via4 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.11</name>
+   <description>cap2m.11 : Min spacing of cap2m and met4 not overlapping cap2m : 0.5um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi.1</name>
+   <description>hvi.1 : min. hvi width : 0.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi.2a</name>
+   <description>hvi.2a : min. hvi spacing : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm.1</name>
+   <description>hvntm.1 : min. hvntm width : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm.2</name>
+   <description>hvntm.2 : min. hvntm spacing : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_analog_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+  <cell>
+   <name>BGR_lvs</name>
+   <variant/>
+   <references>
+    <ref>
+     <parent>user_analog_project_wrapper</parent>
+     <trans>r0 *1 1271.15,2842.015</trans>
+    </ref>
+   </references>
+  </cell>
+  <cell>
+   <name>VCO</name>
+   <variant/>
+   <references>
+    <ref>
+     <parent>user_analog_project_wrapper</parent>
+     <trans>r0 *1 -39.185,3193.71</trans>
+    </ref>
+   </references>
+  </cell>
+  <cell>
+   <name>cap_bank</name>
+   <variant/>
+   <references>
+    <ref>
+     <parent>user_analog_project_wrapper</parent>
+     <trans>r0 *1 232.84,3308.235</trans>
+    </ref>
+   </references>
+  </cell>
+  <cell>
+   <name>sky130_fd_pr__cap_mim_m3_2_WCTBV5</name>
+   <variant/>
+   <references>
+    <ref>
+     <parent>user_analog_project_wrapper</parent>
+     <trans>r0 *1 252.095,3311.74</trans>
+    </ref>
+   </references>
+  </cell>
+ </cells>
+ <items>
+  <item>
+   <tags/>
+   <category>'psd.2'</category>
+   <cell>BGR_lvs</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>edge-pair: (-10.35,-13.1;-10.35,-13.095)|(-10.375,-13.095;-10.375,-13.479)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'cap2m.2b'</category>
+   <cell>cap_bank</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>edge-pair: (24.75,0.3;24.75,13.862)|(24.45,12.7;24.45,0)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'cap2m.2b'</category>
+   <cell>cap_bank</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>edge-pair: (22.55,-3.717;22.55,1.427)|(22.01,0.355;22.01,-2.645)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'cap2m.2b'</category>
+   <cell>cap_bank</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>edge-pair: (24.45,0;25.55,0)|(25.55,0.3;24.75,0.3)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'cap2m.2b'</category>
+   <cell>cap_bank</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>edge-pair: (23.35,-3.15;25.55,-3.15)|(25.55,-2.8;23.65,-2.8)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'cap2m.2b'</category>
+   <cell>cap_bank</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>edge-pair: (23.65,-2.8;23.65,10.812)|(23.35,9.65;23.35,-3.15)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'cap2m.2b'</category>
+   <cell>cap_bank</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>edge-pair: (23.65,8.635;23.65,10.67)|(23.01,9.655;23.01,9.65)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'cap2m.2b'</category>
+   <cell>cap_bank</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>edge-pair: (22.55,0.933;22.55,6.077)|(22.01,5.005;22.01,2.005)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'cap2m.2b'</category>
+   <cell>sky130_fd_pr__cap_mim_m3_2_WCTBV5</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>edge-pair: (3.295,-2.572;3.295,2.572)|(2.755,1.5;2.755,-1.5)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'cap2m.2b_a'</category>
+   <cell>cap_bank</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>edge-pair: (24.75,0.3;24.75,13.862)|(24.45,12.7;24.45,0)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'cap2m.2b_a'</category>
+   <cell>cap_bank</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>edge-pair: (22.55,-3.717;22.55,1.427)|(22.01,0.355;22.01,-2.645)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'cap2m.2b_a'</category>
+   <cell>cap_bank</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>edge-pair: (24.45,0;25.55,0)|(25.55,0.3;24.75,0.3)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'cap2m.2b_a'</category>
+   <cell>cap_bank</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>edge-pair: (23.35,-3.15;25.55,-3.15)|(25.55,-2.8;23.65,-2.8)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'cap2m.2b_a'</category>
+   <cell>cap_bank</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>edge-pair: (23.65,-2.8;23.65,10.812)|(23.35,9.65;23.35,-3.15)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'cap2m.2b_a'</category>
+   <cell>cap_bank</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>edge-pair: (23.65,8.635;23.65,10.67)|(23.01,9.655;23.01,9.65)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'cap2m.2b_a'</category>
+   <cell>cap_bank</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>edge-pair: (22.55,0.933;22.55,6.077)|(22.01,5.005;22.01,2.005)</value>
+   </values>
+  </item>
+  <item>
+   <tags/>
+   <category>'cap2m.2b_a'</category>
+   <cell>sky130_fd_pr__cap_mim_m3_2_WCTBV5</cell>
+   <visited>false</visited>
+   <multiplicity>1</multiplicity>
+   <image/>
+   <values>
+    <value>edge-pair: (3.295,-2.572;3.295,2.572)|(2.755,1.5;2.755,-1.5)</value>
+   </values>
+  </item>
+ </items>
+</report-database>
diff --git a/drc/klayout_met_min_ca_density_check.log b/drc/klayout_met_min_ca_density_check.log
new file mode 100644
index 0000000..43c2164
--- /dev/null
+++ b/drc/klayout_met_min_ca_density_check.log
@@ -0,0 +1,79 @@
+"polygons" in: met_min_ca_density.lydrc:35
+    Polygons (raw): 18154 (flat)  1648 (hierarchical)
+    Elapsed: 0.010s  Memory: 525.00M
+"polygons" in: met_min_ca_density.lydrc:36
+    Polygons (raw): 53602 (flat)  7485 (hierarchical)
+    Elapsed: 0.020s  Memory: 525.00M
+"polygons" in: met_min_ca_density.lydrc:38
+    Polygons (raw): 14244 (flat)  3746 (hierarchical)
+    Elapsed: 0.010s  Memory: 525.00M
+"polygons" in: met_min_ca_density.lydrc:39
+    Polygons (raw): 7063 (flat)  2969 (hierarchical)
+    Elapsed: 0.010s  Memory: 525.00M
+"polygons" in: met_min_ca_density.lydrc:41
+    Polygons (raw): 3321 (flat)  1828 (hierarchical)
+    Elapsed: 0.010s  Memory: 525.00M
+"polygons" in: met_min_ca_density.lydrc:42
+    Polygons (raw): 12714 (flat)  11541 (hierarchical)
+    Elapsed: 0.020s  Memory: 526.00M
+"polygons" in: met_min_ca_density.lydrc:44
+    Polygons (raw): 921 (flat)  771 (hierarchical)
+    Elapsed: 0.000s  Memory: 526.00M
+"polygons" in: met_min_ca_density.lydrc:45
+    Polygons (raw): 88908 (flat)  82922 (hierarchical)
+    Elapsed: 0.090s  Memory: 529.00M
+"polygons" in: met_min_ca_density.lydrc:47
+    Polygons (raw): 254 (flat)  140 (hierarchical)
+    Elapsed: 0.010s  Memory: 529.00M
+"polygons" in: met_min_ca_density.lydrc:48
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 529.00M
+"polygons" in: met_min_ca_density.lydrc:49
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+    Elapsed: 0.010s  Memory: 529.00M
+"polygons" in: met_min_ca_density.lydrc:51
+    Polygons (raw): 181 (flat)  69 (hierarchical)
+    Elapsed: 0.010s  Memory: 529.00M
+"input" in: met_min_ca_density.lydrc:53
+    Polygons (raw): 206 (flat)  43 (hierarchical)
+    Elapsed: 0.010s  Memory: 529.00M
+"area" in: met_min_ca_density.lydrc:55
+    Elapsed: 0.010s  Memory: 529.00M
+"polygons" in: met_min_ca_density.lydrc:59
+    Polygons (raw): 18154 (flat)  1648 (hierarchical)
+    Elapsed: 0.010s  Memory: 529.00M
+"area" in: met_min_ca_density.lydrc:59
+    Elapsed: 0.060s  Memory: 530.00M
+li1_ca_density is 0.9991218441634885
+"polygons" in: met_min_ca_density.lydrc:69
+    Polygons (raw): 14244 (flat)  3746 (hierarchical)
+    Elapsed: 0.020s  Memory: 530.00M
+"area" in: met_min_ca_density.lydrc:69
+    Elapsed: 0.070s  Memory: 530.00M
+m1_ca_density is 0.9992609633381655
+"polygons" in: met_min_ca_density.lydrc:79
+    Polygons (raw): 3321 (flat)  1828 (hierarchical)
+    Elapsed: 0.010s  Memory: 530.00M
+"area" in: met_min_ca_density.lydrc:79
+    Elapsed: 0.030s  Memory: 530.00M
+m2_ca_density is 0.998401196591882
+"polygons" in: met_min_ca_density.lydrc:89
+    Polygons (raw): 921 (flat)  771 (hierarchical)
+    Elapsed: 0.010s  Memory: 530.00M
+"area" in: met_min_ca_density.lydrc:89
+    Elapsed: 0.010s  Memory: 530.00M
+m3_ca_density is 0.9844766714834021
+"polygons" in: met_min_ca_density.lydrc:99
+    Polygons (raw): 254 (flat)  140 (hierarchical)
+    Elapsed: 0.010s  Memory: 530.00M
+"area" in: met_min_ca_density.lydrc:99
+    Elapsed: 0.010s  Memory: 530.00M
+m4_ca_density is 0.9732189436415201
+"polygons" in: met_min_ca_density.lydrc:109
+    Polygons (raw): 181 (flat)  69 (hierarchical)
+    Elapsed: 0.000s  Memory: 530.00M
+"area" in: met_min_ca_density.lydrc:109
+    Elapsed: 0.010s  Memory: 530.00M
+m5_ca_density is 0.964013536503736
+Writing report database: /home/zexi/project/sloci_caravel/precheck_results/12_SEP_2022___13_36_36/outputs/reports/klayout_met_min_ca_density_check.xml ..
+Total elapsed: 0.620s  Memory: 528.00M
diff --git a/drc/klayout_met_min_ca_density_check.total b/drc/klayout_met_min_ca_density_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/drc/klayout_met_min_ca_density_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/drc/klayout_offgrid_check.log b/drc/klayout_offgrid_check.log
new file mode 100644
index 0000000..b63f5a1
--- /dev/null
+++ b/drc/klayout_offgrid_check.log
@@ -0,0 +1,765 @@
+/home/zexi/mpw_precheck/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::FEOL
+/home/zexi/mpw_precheck/checks/tech-files/sky130A_mr.drc:40: warning: previous definition of FEOL was here
+/home/zexi/mpw_precheck/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::BEOL
+/home/zexi/mpw_precheck/checks/tech-files/sky130A_mr.drc:41: warning: previous definition of BEOL was here
+/home/zexi/mpw_precheck/checks/tech-files/sky130A_mr.drc:60: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/home/zexi/mpw_precheck/checks/tech-files/sky130A_mr.drc:42: warning: previous definition of OFFGRID was here
+/home/zexi/mpw_precheck/checks/tech-files/sky130A_mr.drc:68: warning: already initialized constant DRC::DRCEngine::SEAL
+/home/zexi/mpw_precheck/checks/tech-files/sky130A_mr.drc:43: warning: previous definition of SEAL was here
+/home/zexi/mpw_precheck/checks/tech-files/sky130A_mr.drc:74: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/home/zexi/mpw_precheck/checks/tech-files/sky130A_mr.drc:44: warning: previous definition of FLOATING_MET was here
+"input" in: sky130A_mr.drc:124
+    Polygons (raw): 507 (flat)  52 (hierarchical)
+    Elapsed: 0.010s  Memory: 528.00M
+"polygons" in: sky130A_mr.drc:125
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+    Elapsed: 0.010s  Memory: 528.00M
+"polygons" in: sky130A_mr.drc:126
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+"polygons" in: sky130A_mr.drc:127
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+    Elapsed: 0.010s  Memory: 555.00M
+"with_angle" in: sky130A_mr.drc:769
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 555.00M
+"output" in: sky130A_mr.drc:769
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 555.00M
+"ongrid" in: sky130A_mr.drc:770
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 555.00M
+"output" in: sky130A_mr.drc:770
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 555.00M
+"with_angle" in: sky130A_mr.drc:771
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 555.00M
+"output" in: sky130A_mr.drc:771
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 555.00M
+"ongrid" in: sky130A_mr.drc:772
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 555.00M
+"output" in: sky130A_mr.drc:772
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 555.00M
+"with_angle" in: sky130A_mr.drc:773
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 555.00M
+"output" in: sky130A_mr.drc:773
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 555.00M
+"ongrid" in: sky130A_mr.drc:774
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 555.00M
+"output" in: sky130A_mr.drc:774
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 555.00M
+"with_angle" in: sky130A_mr.drc:775
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 555.00M
+"output" in: sky130A_mr.drc:775
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 555.00M
+"ongrid" in: sky130A_mr.drc:776
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 555.00M
+"output" in: sky130A_mr.drc:776
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 555.00M
+"with_angle" in: sky130A_mr.drc:777
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 555.00M
+"output" in: sky130A_mr.drc:777
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 555.00M
+"ongrid" in: sky130A_mr.drc:778
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 555.00M
+"output" in: sky130A_mr.drc:778
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 555.00M
+"with_angle" in: sky130A_mr.drc:779
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 555.00M
+"output" in: sky130A_mr.drc:779
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 555.00M
+"ongrid" in: sky130A_mr.drc:780
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 555.00M
+"output" in: sky130A_mr.drc:780
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 555.00M
+"with_angle" in: sky130A_mr.drc:781
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 555.00M
+"output" in: sky130A_mr.drc:781
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 555.00M
+"ongrid" in: sky130A_mr.drc:782
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 555.00M
+"output" in: sky130A_mr.drc:782
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 555.00M
+Writing report database: /home/zexi/project/sloci_caravel/precheck_results/12_SEP_2022___13_36_36/outputs/reports/klayout_offgrid_check.xml ..
+Total elapsed: 4.130s  Memory: 553.00M
+ 
+Cell exclusion list:
+   rule    | cell
+   nwell.6 | sky130_fd_io__gpiov2_amux, sky130_fd_io__simple_pad_and_busses, sram
+   nsd.1   | sram
+   nsd.2   | sram
+   psd.1   | sram
+   psd.2   | sram
+ 
+release 2022.6.30_01.07
diff --git a/drc/klayout_offgrid_check.total b/drc/klayout_offgrid_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/drc/klayout_offgrid_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/drc/klayout_pin_label_purposes_overlapping_drawing_check.log b/drc/klayout_pin_label_purposes_overlapping_drawing_check.log
new file mode 100644
index 0000000..a16159f
--- /dev/null
+++ b/drc/klayout_pin_label_purposes_overlapping_drawing_check.log
@@ -0,0 +1,30 @@
+Running pin_label_purposes_overlapping_drawing.rb.drc on file=/home/zexi/project/sloci_caravel/gds/user_analog_project_wrapper.gds, topcell=user_analog_project_wrapper, output to /home/zexi/project/sloci_caravel/precheck_results/12_SEP_2022___13_36_36/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
+  deep:true tiled:false threads:4
+--- #err|description, table for cell: user_analog_project_wrapper
+NO-Check ----        pwell:64/44/EMP   122/16/EMP    64/59/EMP    44/16/EMP     44/5/EMP
+         ----        nwell:64/20/dat    64/16/EMP     64/5/dat
+         ----         diff:65/20/dat    65/16/EMP     65/6/EMP
+         ----          tap:65/44/dat    65/48/EMP     65/5/EMP
+         ----         poly:66/20/dat    66/16/EMP     66/5/EMP
+         ----       licon1:66/44/dat    66/58/EMP
+         ----          li1:67/20/dat    67/16/dat     67/5/dat
+         ----         mcon:67/44/dat    67/48/EMP
+         ----         met1:68/20/dat    68/16/dat     68/5/dat
+         ----          via:68/44/dat    68/58/EMP
+         ----         met2:69/20/dat    69/16/dat     69/5/dat
+         ----         via2:69/44/dat    69/58/EMP
+       1 70/16: met3, pin/label not-over drawing:70/20
+         ----         met3:70/20/dat    70/16/dat     70/5/dat
+         ----         via3:70/44/dat    70/48/EMP
+         ----         met4:71/20/dat    71/16/dat     71/5/dat
+         ----         via4:71/44/dat    71/48/EMP
+         ----         met5:72/20/dat    72/16/dat     72/5/dat
+         ----          pad:76/20/EMP     76/5/EMP    76/16/EMP
+         ----          pnp:82/44/dat    82/59/EMP
+         ----          npn:82/20/EMP     82/5/EMP
+         ----          rdl:74/20/EMP    74/16/EMP     74/5/EMP
+         ----     inductor:82/24/EMP    82/25/EMP
+       1 total error(s) among 1 error type(s), 33 checks, cell: user_analog_project_wrapper
+Writing report...
+VmPeak:	 1193744 kB
+VmHWM:	  263748 kB
diff --git a/drc/klayout_pin_label_purposes_overlapping_drawing_check.total b/drc/klayout_pin_label_purposes_overlapping_drawing_check.total
new file mode 100644
index 0000000..56a6051
--- /dev/null
+++ b/drc/klayout_pin_label_purposes_overlapping_drawing_check.total
@@ -0,0 +1 @@
+1
\ No newline at end of file
diff --git a/drc/klayout_zeroarea_check.log b/drc/klayout_zeroarea_check.log
new file mode 100644
index 0000000..ee55e41
--- /dev/null
+++ b/drc/klayout_zeroarea_check.log
@@ -0,0 +1,6 @@
+writing to /home/zexi/project/sloci_caravel/precheck_results/12_SEP_2022___13_36_36/outputs/user_analog_project_wrapper_no_zero_areas.gds
+0 zero-area shapes
+0 zero-length paths,  0 zero-length paths deleted.
+0 total zero-area objects,  0 total objects deleted.
+VmPeak:	  558172 kB
+VmHWM:	  275120 kB
diff --git a/drc/klayout_zeroarea_check.total b/drc/klayout_zeroarea_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/drc/klayout_zeroarea_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/drc/magic_drc_check.log b/drc/magic_drc_check.log
new file mode 100644
index 0000000..4dc8f18
--- /dev/null
+++ b/drc/magic_drc_check.log
@@ -0,0 +1,25 @@
+
+Magic 8.3 revision 315 - Compiled on Fri Sep  2 23:28:49 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Error parsing "/home/zexi/mpw_precheck/checks/tech-files/sky130A.magicrc": invalid command name "EF"
+Bad local startup file "/home/zexi/mpw_precheck/checks/tech-files/sky130A.magicrc", continuing without.
+Loading "/home/zexi/mpw_precheck/checks/drc_checks/magic/magic_drc_check.tcl" from command line.
+Don't know how to read GDS-II:
+Nothing in "cifinput" section of tech file.
+[INFO]: Loading user_analog_project_wrapper
+
+File user_analog_project_wrapper.mag couldn't be read
+No such file or directory
+Creating new cell
+"drc(full)" is not one of the DRC styles Magic knows.
+The current style is "default".
+The DRC styles are: default.
+No errors found.
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+[INFO]: DRC Checking DONE (/home/zexi/project/sloci_caravel/precheck_results/12_SEP_2022___13_36_36/outputs/reports/magic_drc_check.drc.report)
+[INFO]: Saving mag view with DRC errors(/home/zexi/project/sloci_caravel/precheck_results/12_SEP_2022___13_36_36/outputs/user_analog_project_wrapper.magic.drc.mag)
+[INFO]: Saved
diff --git a/drc/magic_drc_check.total b/drc/magic_drc_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/drc/magic_drc_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/drc/pdks.info b/drc/pdks.info
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/drc/pdks.info
diff --git a/drc/precheck.log b/drc/precheck.log
new file mode 100644
index 0000000..35c6919
--- /dev/null
+++ b/drc/precheck.log
@@ -0,0 +1,58 @@
+2022-09-12 13:36:36 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: /home/zexi/project/sloci_caravel
+2022-09-12 13:36:36 - [INFO] - {{Project Type Info}} analog
+2022-09-12 13:36:36 - [INFO] - {{Project GDS Info}} user_analog_project_wrapper: 506c050c23c111a6cdbc7bf8a5f8707754735e03
+2022-09-12 13:36:37 - [INFO] - {{Tools Info}} KLayout: v0.27.10 | Magic: v8.3.315
+2022-09-12 13:36:37 - [ERROR] - MPW Precheck failed to get Open PDKs & Skywater PDK versions: Command '['git', '-C', '/pdk/open_pdks', 'rev-parse', '--verify', 'HEAD']' returned non-zero exit status 128.
+2022-09-12 13:36:37 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in '/home/zexi/project/sloci_caravel/precheck_results/12_SEP_2022___13_36_36/logs'
+2022-09-12 13:36:37 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
+2022-09-12 13:36:37 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License
+2022-09-12 13:36:39 - [INFO] - An approved LICENSE (Apache-2.0) was found in /home/zexi/project/sloci_caravel.
+2022-09-12 13:36:39 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
+2022-09-12 13:36:42 - [INFO] - An approved LICENSE (Apache-2.0) was found in /home/zexi/project/sloci_caravel.
+2022-09-12 13:36:42 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
+2022-09-12 13:36:42 - [INFO] - {{SPDX COMPLIANCE CHECK PASSED}} Project is compliant with the SPDX Standard
+2022-09-12 13:36:42 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile
+2022-09-12 13:36:42 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
+2022-09-12 13:36:42 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default
+2022-09-12 13:36:42 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
+2022-09-12 13:36:42 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
+2022-09-12 13:36:42 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation
+2022-09-12 13:36:42 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
+2022-09-12 13:36:42 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency
+2022-09-12 13:36:47 - [INFO] - HIERARCHY CHECK PASSED: Module user_analog_project_wrapper is instantiated in caravan. 
+2022-09-12 13:36:47 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravan contains at least 8 instances (68 instances). 
+2022-09-12 13:36:47 - [INFO] - MODELING CHECK PASSED: Netlist caravan is structural.
+2022-09-12 13:36:47 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_analog_project_wrapper are correctly connected in the top level netlist caravan.
+2022-09-12 13:36:47 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravan netlist passed all consistency checks.
+2022-09-12 13:36:47 - [INFO] - PORTS CHECK PASSED: Netlist user_analog_project_wrapper ports match the golden wrapper ports
+2022-09-12 13:36:47 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_analog_project_wrapper contains at least 1 instances (11 instances). 
+2022-09-12 13:36:47 - [INFO] - MODELING CHECK PASSED: Netlist user_analog_project_wrapper is structural.
+2022-09-12 13:36:47 - [WARNING] - LAYOUT CHECK FAILED: The GDS layout for user_analog_project_wrapper doesn't match the provided structural netlist. Mismatching modules are: ['BGR_lvs' 'VCO']
+2022-09-12 13:36:47 - [WARNING] - {{NETLIST CONSISTENCY CHECK FAILED}} user_analog_project_wrapper netlist failed 1 consistency check(s): ['LAYOUT'].
+2022-09-12 13:36:47 - [WARNING] - {{CONSISTENCY CHECK FAILED}} The user netlist and the top netlist are not valid.
+2022-09-12 13:36:47 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 13: XOR
+2022-09-12 13:36:52 - [INFO] - {{XOR CHECK UPDATE}} Total XOR differences: 0, for more details view /home/zexi/project/sloci_caravel/precheck_results/12_SEP_2022___13_36_36/outputs/user_analog_project_wrapper.xor.gds
+2022-09-12 13:36:52 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
+2022-09-12 13:36:52 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC
+2022-09-12 13:36:52 - [INFO] - 0 DRC violations
+2022-09-12 13:36:52 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-09-12 13:36:52 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL
+2022-09-12 13:36:57 - [ERROR] - Total # of DRC violations is 17 Please check /home/zexi/project/sloci_caravel/precheck_results/12_SEP_2022___13_36_36/outputs/reports/klayout_feol_check.xml For more details
+2022-09-12 13:36:57 - [WARNING] - {{Klayout FEOL CHECK FAILED}} The GDS file, user_analog_project_wrapper.gds, has DRC violations.
+2022-09-12 13:36:57 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL
+2022-09-12 13:37:20 - [ERROR] - Total # of DRC violations is 16 Please check /home/zexi/project/sloci_caravel/precheck_results/12_SEP_2022___13_36_36/outputs/reports/klayout_beol_check.xml For more details
+2022-09-12 13:37:20 - [WARNING] - {{Klayout BEOL CHECK FAILED}} The GDS file, user_analog_project_wrapper.gds, has DRC violations.
+2022-09-12 13:37:20 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid
+2022-09-12 13:37:26 - [INFO] - No DRC Violations found
+2022-09-12 13:37:26 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-09-12 13:37:26 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density
+2022-09-12 13:37:28 - [INFO] - No DRC Violations found
+2022-09-12 13:37:28 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-09-12 13:37:28 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing
+2022-09-12 13:37:30 - [ERROR] - Total # of DRC violations is 1 Please check /home/zexi/project/sloci_caravel/precheck_results/12_SEP_2022___13_36_36/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml For more details
+2022-09-12 13:37:30 - [WARNING] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK FAILED}} The GDS file, user_analog_project_wrapper.gds, has DRC violations.
+2022-09-12 13:37:30 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea
+2022-09-12 13:37:33 - [INFO] - No DRC Violations found
+2022-09-12 13:37:33 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-09-12 13:37:33 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in '/home/zexi/project/sloci_caravel/precheck_results/12_SEP_2022___13_36_36/logs'
+2022-09-12 13:37:33 - [CRITICAL] - {{FAILURE}} 4 Check(s) Failed: ['Consistency', 'Klayout FEOL', 'Klayout BEOL', 'Klayout Pin Label Purposes Overlapping Drawing'] !!!
diff --git a/drc/tools.info b/drc/tools.info
new file mode 100644
index 0000000..91cb193
--- /dev/null
+++ b/drc/tools.info
@@ -0,0 +1,2 @@
+KLayout: 0.27.10
+Magic: 8.3.315
\ No newline at end of file
diff --git a/drc/xor_check.log b/drc/xor_check.log
new file mode 100644
index 0000000..97f249d
--- /dev/null
+++ b/drc/xor_check.log
@@ -0,0 +1,238 @@
+Reading file /home/zexi/project/sloci_caravel/gds/user_analog_project_wrapper.gds for cell user_analog_project_wrapper
+dbu=0.001
+cell user_analog_project_wrapper dbu-bbox(ll;ur)=(-4000,-4000;2924000,3524000)
+cell user_analog_project_wrapper dbu-bbox(left,bottom,right,top)=(-4000,-4000,2924000,3524000)
+cell user_analog_project_wrapper dbu-size(width,height)=(2928000,3528000)
+cell user_analog_project_wrapper micron-bbox(left,bottom,right,top)=(-4.0,-4.0,2924.0,3524.0)
+cell user_analog_project_wrapper micron-size(width,height)=(2928.0,3528.0)
+Done.
+
+Magic 8.3 revision 315 - Compiled on Fri Sep  2 23:28:49 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/home/zexi/mpw_precheck/checks/xor_check/erase_box.tcl" from command line.
+CIF input style is now "sky130(vendor)"
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_analog_project_wrapper
+Reading "sky130_fd_pr__pfet_01v8_lvt_D3M934".
+Reading "sky130_fd_pr__pfet_01v8_lvt_D3Z634".
+Reading "sky130_fd_pr__nfet_01v8_lvt_9DHFGX".
+Reading "sky130_fd_pr__res_high_po_2p85_P79JE3".
+Reading "sky130_fd_pr__res_high_po_2p85_MM89SS".
+Reading "sky130_fd_pr__pfet_01v8_lvt_D3ZSZ4".
+Reading "bias_calc".
+CIF file read warning: CIF style sky130(vendor): units rescaled by factor of 5 / 1
+Reading "sky130_fd_pr__nfet_01v8_lvt_B6HS5D".
+Reading "sky130_fd_pr__nfet_01v8_lvt_BX7S53".
+Reading "sky130_fd_pr__nfet_01v8_lvt_DJ7QE5".
+Reading "sky130_fd_pr__nfet_01v8_lvt_648S5X".
+Reading "sky130_fd_pr__cap_mim_m3_2_FJFAMD".
+Reading "sky130_fd_pr__cap_mim_m3_2_VCH7EQ".
+Reading "sky130_fd_pr__cap_mim_m3_2_3ZFDVT".
+Reading "sky130_fd_pr__cap_mim_m3_2_WCTZRP".
+Reading "sky130_fd_pr__cap_mim_m3_2_WCTBV5".
+Reading "cap_bank".
+Reading "sky130_fd_pr__nfet_01v8_lvt_YTLFGX".
+Reading "sky130_fd_pr__nfet_01v8_lvt_HNLS5R".
+Reading "core_osc_amp".
+Reading "core_osc".
+Reading "sky130_fd_pr__res_high_po_5p73_W59YBA".
+Reading "sky130_fd_pr__nfet_01v8_lvt_LELFGX".
+Reading "output_buffer".
+Reading "sky130_fd_pr__pfet_01v8_lvt_75KH85".
+Reading "sky130_fd_pr__res_high_po_2p85_MXEQGY".
+Reading "sky130_fd_pr__nfet_01v8_lvt_6BNFGK".
+Reading "sky130_fd_pr__cap_mim_m3_1_4RCNTW".
+Reading "vop_dec".
+Reading "amp_dec".
+Reading "sky130_fd_pr__res_high_po_5p73_YZEQ6M".
+Reading "buffer_amp".
+Reading "buffer_amp_vop".
+Reading "VCO".
+Reading "sky130_fd_pr__res_xhigh_po_5p73_UZMRKM".
+Reading "XM_Rref".
+Reading "sky130_fd_pr__rf_pnp_05v5_W3p40L3p40".
+Reading "XM_bjt".
+Reading "sky130_fd_pr__pfet_01v8_lvt_Q24T46".
+Reading "sky130_fd_pr__pfet_01v8_lvt_MUVY4U".
+Reading "XM_current_gate".
+Reading "XM_current_gate_with_dummy".
+Reading "sky130_fd_pr__res_high_po_2p85_7J2RPB".
+Reading "sky130_fd_pr__cap_mim_m3_1_EN3Q86".
+Reading "sky130_fd_pr__nfet_01v8_lvt_7MFZYU".
+Reading "XM_tail".
+Reading "sky130_fd_pr__pfet_01v8_lvt_MBDTEX".
+Reading "sky130_fd_pr__pfet_01v8_lvt_B64SAM".
+Reading "XM_ppair".
+Reading "sky130_fd_pr__nfet_01v8_lvt_E96B6C".
+Reading "sky130_fd_pr__nfet_01v8_lvt_A5VCMN".
+Reading "XM_diffpair".
+Reading "sky130_fd_pr__pfet_01v8_lvt_D74VRS".
+Reading "XM_cs".
+Reading "sky130_fd_pr__nfet_01v8_lvt_USQY94".
+Reading "XM_actload2".
+Reading "opamp_realcomp3_usefinger".
+Reading "sky130_fd_pr__res_high_po_1p41_GWJZ59".
+Reading "sky130_fd_pr__res_high_po_1p41_HX7ZEK".
+Reading "XM_bjt_out".
+Reading "sky130_fd_pr__pfet_01v8_lvt_9UM225".
+Reading "XM_feedbackmir2".
+Reading "sky130_fd_pr__pfet_01v8_lvt_8URDWJ".
+Reading "XM_feedbackmir".
+Reading "sky130_fd_pr__nfet_01v8_lvt_QA4PPD".
+Reading "XM_otabias_nmos".
+Reading "sky130_fd_pr__pfet_01v8_lvt_MUAP4U".
+Reading "XM_otabias_pmos".
+Reading "sky130_fd_pr__res_high_po_1p41_2TBR6S".
+Reading "sky130_fd_pr__pfet_01v8_TSNZVH".
+Reading "sky130_fd_pr__nfet_01v8_Y5UG24".
+Reading "sky130_fd_pr__cap_mim_m3_1_Y9W37A".
+Reading "XM_pdn".
+Reading "sky130_fd_pr__res_high_po_1p41_6ZUZ5C".
+Reading "sky130_fd_pr__res_high_po_1p41_S8KB58".
+Reading "sky130_fd_pr__nfet_01v8_lvt_64S6GM".
+Reading "sky130_fd_pr__nfet_01v8_lvt_64DJ5N".
+Reading "XM_output_mirr".
+Reading "XM_output_mirr_combined".
+Reading "XM_output_mirr_combined_with_dummy".
+Reading "BGR_lvs".
+Reading "user_analog_project_wrapper".
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  42.880 x 3520.000  (-42.880,  0.000), ( 0.000,  3520.000)  150937.594
+lambda:   4288.00 x 352000.00  (-4288.00,  0.00 ), (  0.00,  352000.00)  1509376000.00
+internal:   8576 x 704000  ( -8576,  0    ), (     0,  704000)  6037504000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  42.500 x 3520.000  ( 2920.000,  0.000), ( 2962.500,  3520.000)  149600.000
+lambda:   4250.00 x 352000.00  ( 292000.00,  0.00 ), ( 296250.00,  352000.00)  1496000000.00
+internal:   8500 x 704000  ( 584000,  0    ), ( 592500,  704000)  5984000000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.380 x 37.530  (-42.880, -37.530), ( 2962.500,  0.000)  112791.906
+lambda:   300538.00 x 3753.00  (-4288.00, -3753.00), ( 296250.00,  0.00 )  1127919104.00
+internal: 601076 x 7506    ( -8576, -7506 ), ( 592500,  0    )  4511676456
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.380 x 37.210  (-42.880,  3520.000), ( 2962.500,  3557.210)  111830.188
+lambda:   300538.00 x 3721.00  (-4288.00,  352000.00), ( 296250.00,  355721.00)  1118301952.00
+internal: 601076 x 7442    ( -8576,  704000), ( 592500,  711442)  4473207592
+   Generating output for cell xor_target
+
+Magic 8.3 revision 315 - Compiled on Fri Sep  2 23:28:49 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/home/zexi/mpw_precheck/checks/xor_check/erase_box.tcl" from command line.
+CIF input style is now "sky130(vendor)"
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 6.0
+Library name: user_analog_project_wrapper_empty
+Reading "user_analog_project_wrapper".
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  42.880 x 3520.000  (-42.880,  0.000), ( 0.000,  3520.000)  150937.594
+lambda:   4288.00 x 352000.00  (-4288.00,  0.00 ), (  0.00,  352000.00)  1509376000.00
+internal:   8576 x 704000  ( -8576,  0    ), (     0,  704000)  6037504000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  42.500 x 3520.000  ( 2920.000,  0.000), ( 2962.500,  3520.000)  149600.000
+lambda:   4250.00 x 352000.00  ( 292000.00,  0.00 ), ( 296250.00,  352000.00)  1496000000.00
+internal:   8500 x 704000  ( 584000,  0    ), ( 592500,  704000)  5984000000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.380 x 37.530  (-42.880, -37.530), ( 2962.500,  0.000)  112791.906
+lambda:   300538.00 x 3753.00  (-4288.00, -3753.00), ( 296250.00,  0.00 )  1127919104.00
+internal: 601076 x 7506    ( -8576, -7506 ), ( 592500,  0    )  4511676456
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.380 x 37.210  (-42.880,  3520.000), ( 2962.500,  3557.210)  111830.188
+lambda:   300538.00 x 3721.00  (-4288.00,  352000.00), ( 296250.00,  355721.00)  1118301952.00
+internal: 601076 x 7442    ( -8576,  704000), ( 592500,  711442)  4473207592
+   Generating output for cell xor_target
+Reading /home/zexi/project/sloci_caravel/precheck_results/12_SEP_2022___13_36_36/outputs/user_analog_project_wrapper_erased.gds ..
+Reading /home/zexi/project/sloci_caravel/precheck_results/12_SEP_2022___13_36_36/outputs/user_analog_project_wrapper_empty_erased.gds ..
+--- Running XOR for 69/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 494 (flat)  494 (hierarchical)
+    Elapsed: 0.010s  Memory: 521.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 494 (flat)  494 (hierarchical)
+    Elapsed: 0.010s  Memory: 521.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 521.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 521.00M
+--- Running XOR for 70/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 184 (flat)  184 (hierarchical)
+    Elapsed: 0.010s  Memory: 521.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 184 (flat)  184 (hierarchical)
+    Elapsed: 0.010s  Memory: 521.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 521.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 521.00M
+--- Running XOR for 72/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 6 (flat)  6 (hierarchical)
+    Elapsed: 0.000s  Memory: 521.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 6 (flat)  6 (hierarchical)
+    Elapsed: 0.010s  Memory: 521.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 521.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 521.00M
+--- Running XOR for 81/14 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 1 (flat)  1 (hierarchical)
+    Elapsed: 0.010s  Memory: 521.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 1 (flat)  1 (hierarchical)
+    Elapsed: 0.010s  Memory: 521.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 521.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 521.00M
+Writing layout file: /home/zexi/project/sloci_caravel/precheck_results/12_SEP_2022___13_36_36/outputs/user_analog_project_wrapper.xor.gds ..
+Total elapsed: 0.150s  Memory: 521.00M
diff --git a/drc/xor_check.total b/drc/xor_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/drc/xor_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds
index 764b362..d7b2d50 100644
--- a/gds/user_analog_project_wrapper.gds
+++ b/gds/user_analog_project_wrapper.gds
Binary files differ