/root/hehecore_resubmission/Makefile
/root/hehecore_resubmission/docs/Makefile
/root/hehecore_resubmission/docs/environment.yml
/root/hehecore_resubmission/docs/source/conf.py
/root/hehecore_resubmission/docs/source/index.rst
/root/hehecore_resubmission/docs/source/quickstart.rst
/root/hehecore_resubmission/final/sdc/user_project_wrapper.sdc
/root/hehecore_resubmission/final/sdf/user_project_wrapper.sdf
/root/hehecore_resubmission/final/spef/user_project_wrapper.spef
/root/hehecore_resubmission/openlane/Makefile
/root/hehecore_resubmission/openlane/top/base.sdc
/root/hehecore_resubmission/openlane/top/config.tcl
/root/hehecore_resubmission/openlane/user_proj_example/config.json
/root/hehecore_resubmission/openlane/user_project_wrapper/base.sdc
/root/hehecore_resubmission/openlane/user_project_wrapper/config.json
/root/hehecore_resubmission/openlane/user_project_wrapper/config.tcl
/root/hehecore_resubmission/openlane/user_project_wrapper/fixed_dont_change/default_wrapper_cfgs.tcl
/root/hehecore_resubmission/openlane/user_project_wrapper/fixed_dont_change/fixed_wrapper_cfgs.tcl
/root/hehecore_resubmission/signoff/top/openlane-signoff/spef/top.max.spef
/root/hehecore_resubmission/signoff/top/openlane-signoff/spef/top.min.spef
/root/hehecore_resubmission/signoff/top/openlane-signoff/spef/top.nom.spef
/root/hehecore_resubmission/signoff/user_project_wrapper/openlane-signoff/spef/user_project_wrapper.max.spef
/root/hehecore_resubmission/signoff/user_project_wrapper/openlane-signoff/spef/user_project_wrapper.min.spef
/root/hehecore_resubmission/signoff/user_project_wrapper/openlane-signoff/spef/user_project_wrapper.nom.spef
/root/hehecore_resubmission/verilog/base.sdc
/root/hehecore_resubmission/verilog/dv/Makefile
/root/hehecore_resubmission/verilog/dv/io_ports/Makefile
/root/hehecore_resubmission/verilog/dv/io_ports/io_ports.c
/root/hehecore_resubmission/verilog/dv/io_ports/io_ports_tb.v
/root/hehecore_resubmission/verilog/dv/la_test1/Makefile
/root/hehecore_resubmission/verilog/dv/la_test1/la_test1.c
/root/hehecore_resubmission/verilog/dv/la_test1/la_test1_tb.v
/root/hehecore_resubmission/verilog/dv/la_test2/Makefile
/root/hehecore_resubmission/verilog/dv/la_test2/la_test2.c
/root/hehecore_resubmission/verilog/dv/la_test2/la_test2_tb.v
/root/hehecore_resubmission/verilog/dv/mprj_stimulus/Makefile
/root/hehecore_resubmission/verilog/dv/mprj_stimulus/mprj_stimulus.c
/root/hehecore_resubmission/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
/root/hehecore_resubmission/verilog/dv/wb_port/Makefile
/root/hehecore_resubmission/verilog/dv/wb_port/wb_port.c
/root/hehecore_resubmission/verilog/dv/wb_port/wb_port_tb.v
/root/hehecore_resubmission/verilog/includes/includes.gl+sdf.caravel_user_project
/root/hehecore_resubmission/verilog/includes/includes.gl.caravel_user_project
/root/hehecore_resubmission/verilog/includes/includes.rtl.caravel_user_project
/root/hehecore_resubmission/verilog/rtl/defines.v
/root/hehecore_resubmission/verilog/rtl/uprj_netlists.v
/root/hehecore_resubmission/verilog/rtl/user_defines.v
/root/hehecore_resubmission/verilog/rtl/user_proj_example.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/bus_arbiter.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/caravel_defines.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/data_ram_mux.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/gpio.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/instr_ram_mux.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/params.vh
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/rvj1_caravel_soc.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/timer.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/to.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/top.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/user_project_wrapper.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/wishbone_mux.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/base.sdc
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/params.vh
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/cache/l1dcache.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/cache/l1icache_32.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/cache/params.vh
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/cache/cacheblock/sky130_sram_1kbyte_1rw1r_32x256_8.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/cache/cacheblock/sky130_sram_1rw1r_64x256_8.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/cache/cacheblock/std_dffe.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/cache/cacheblock/std_dffr.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/core_empty/core_empty.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/core_empty/params.vh
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/ac.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/agu.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/cu.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/lr.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/lsq.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/nblsu.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/params.vh
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/core_empty/mmu/leaf_pte_check.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/core_empty/mmu/mmu_sv39.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/core_empty/mmu/ptw.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/core_empty/pipeline/backend.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/core_empty/pipeline/frontend.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/btb.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/counter.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/counter_rob.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/counter_tmp.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/csr.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/decode.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/excep_ctrl.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/fake_icache.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/fetch.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/fifo.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/fifo_tmp.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/gshare.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/ins_buffer.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/new_alu.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/new_fu.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/physical_regfile.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/rcu.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/macros/verilog/sky130_sram_1kbyte_1rw1r_32x256_8.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/hehe/src/macros/verilog/sky130_sram_1rw1r_64x256_8.v
/root/hehecore_resubmission/verilog/rtl_sram_out_cache/inc/rvj1_defines.v