tree 557ab072a95e657e28b30ef3c55bf8e1fc3058f5
parent 2c3a86ec906d20d517302fb36a6610311ce95e4c
author Tim Edwards <tim@opencircuitdesign.com> 1661709199 -0400
committer Tim Edwards <tim@opencircuitdesign.com> 1661709199 -0400

Rewrote the top level verilog for a 30x30 array;  moved the original
30x50 array to "user_project_wrapper_30x50.v" for safekeeping.