)]}'
{
  "commit": "c4c82e6d091a59ce3ed83a713702ec83f9d43dfa",
  "tree": "557ab072a95e657e28b30ef3c55bf8e1fc3058f5",
  "parents": [
    "2c3a86ec906d20d517302fb36a6610311ce95e4c"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Sun Aug 28 13:53:19 2022 -0400"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Sun Aug 28 13:53:19 2022 -0400"
  },
  "message": "Rewrote the top level verilog for a 30x30 array;  moved the original\n30x50 array to \"user_project_wrapper_30x50.v\" for safekeeping.\n",
  "tree_diff": [
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}