)]}'
{
  "commit": "b2ffae950cb0391bb7838c912e06e32ea17f91a1",
  "tree": "8244dd649dfedaa1731502bd9b03c4b01a051ea5",
  "parents": [
    "6644e40c26d5441eef64aef10485f8ae0f87aad2"
  ],
  "author": {
    "name": "AlexanderJGoldstein",
    "email": "Alex_Goldstein@outlook.com",
    "time": "Thu Aug 11 12:00:05 2022 -0400"
  },
  "committer": {
    "name": "AlexanderJGoldstein",
    "email": "Alex_Goldstein@outlook.com",
    "time": "Thu Aug 11 12:00:05 2022 -0400"
  },
  "message": "Macros not found user_proj_wrapper\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "625ab9a0df3b508e1a5231e9b143626db33124d5",
      "old_mode": 33188,
      "old_path": "openlane/user_project_wrapper/macro.cfg",
      "new_id": "f300848e2d646cd750b27db119c77c09a35216bf",
      "new_mode": 33188,
      "new_path": "openlane/user_project_wrapper/macro.cfg"
    },
    {
      "type": "modify",
      "old_id": "70b3e3741c7c9dc10073402ef9346ba326c72f30",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "f83774ee8210729007b559530b8e6e092df1fbdf",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project_wrapper.v"
    }
  ]
}