)]}'
{
  "commit": "2c3a86ec906d20d517302fb36a6610311ce95e4c",
  "tree": "20482c979adbcf7a1eca3cf29881f0d6ac28dcf9",
  "parents": [
    "1335d16b338a47e3b355c82e886d701dd3716ba2"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Sat Aug 27 09:27:23 2022 -0400"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Sat Aug 27 09:27:23 2022 -0400"
  },
  "message": "Made a handful of corrections to the array connectivity;  the\narray now passes tests 2 and 3.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "cb6c608cb6facd7ee02e1b1fce9dbcb2a33f1cbb",
      "old_mode": 33188,
      "old_path": "verilog/dv/README.local",
      "new_id": "20c407b0519c2635cb1cfb8919f6abf85575f4a5",
      "new_mode": 33188,
      "new_path": "verilog/dv/README.local"
    },
    {
      "type": "modify",
      "old_id": "cacb5649561501382af7059a82b0edc5d6256453",
      "old_mode": 33188,
      "old_path": "verilog/dv/chaos_test1/chaos_test1_tb.v",
      "new_id": "fd26ef6fc9530dfef22e45bea964dbb12416b6d0",
      "new_mode": 33188,
      "new_path": "verilog/dv/chaos_test1/chaos_test1_tb.v"
    },
    {
      "type": "modify",
      "old_id": "a80b495cb9a98c1a487c361410f1489c15e8dc06",
      "old_mode": 33188,
      "old_path": "verilog/dv/chaos_test3/chaos_test3.c",
      "new_id": "f4445c38381558cb9243b1c1f74ca4041891bd44",
      "new_mode": 33188,
      "new_path": "verilog/dv/chaos_test3/chaos_test3.c"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "7cd54c1368bf1ccef0a045fd2b00de06d3a961fd",
      "new_mode": 33188,
      "new_path": "verilog/dv/local-install.md"
    },
    {
      "type": "modify",
      "old_id": "b9bf3950551ef4744532c67600623a2948686536",
      "old_mode": 33261,
      "old_path": "verilog/rtl/chaos_subarray.v",
      "new_id": "252007c0bb7c4ea2d17c4eccaa1c7aaca6a6a4f4",
      "new_mode": 33261,
      "new_path": "verilog/rtl/chaos_subarray.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "43ed500bf3eed92db5bcb94c06504a8918c45a5a",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_defines.v"
    },
    {
      "type": "modify",
      "old_id": "c5e0dd84a82f2e8e69b0db315f59ce889dc556be",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "09691b60b746a8f8b5ac4e4d48d6b27791681bbb",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project_wrapper.v"
    }
  ]
}
