timestamp 1662151999
version 8.3
tech sky130B
style ngspice()
scale 1000 1 500000
resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
use bias_cell bias_cell_0 1 0 24660 0 1 691160
use adc adc_0 1 0 52980 0 1 205530
use 8bit_sens 8bit_sens_0 1 0 52880 0 1 199490
port "io_analog[4]" 41 329294 702300 334294 704800 m5
port "io_analog[4]" 47 318994 702300 323994 704800 m5
port "io_analog[5]" 42 227594 702300 232594 704800 m5
port "io_analog[5]" 48 217294 702300 222294 704800 m5
port "io_analog[6]" 43 175894 702300 180894 704800 m5
port "io_analog[6]" 49 165594 702300 170594 704800 m5
port "io_analog[4]" 41 329294 702300 334294 704800 m4
port "io_analog[5]" 42 227594 702300 232594 704800 m4
port "io_analog[6]" 43 175894 702300 180894 704800 m4
port "io_in_3v3[0]" 83 583520 1544 584800 1656 m3
port "io_oeb[26]" 128 -800 1544 480 1656 m3
port "io_in[0]" 56 583520 2726 584800 2838 m3
port "io_out[26]" 155 -800 2726 480 2838 m3
port "io_out[0]" 137 583520 3908 584800 4020 m3
port "io_in[26]" 74 -800 3908 480 4020 m3
port "io_oeb[0]" 110 583520 5090 584800 5202 m3
port "io_in_3v3[26]" 101 -800 5090 480 5202 m3
port "io_in_3v3[1]" 94 583520 6272 584800 6384 m3
port "io_oeb[25]" 127 -800 6272 480 6384 m3
port "io_in[1]" 67 583520 7454 584800 7566 m3
port "io_out[25]" 154 -800 7454 480 7566 m3
port "io_out[1]" 148 583520 8636 584800 8748 m3
port "io_in[25]" 73 -800 8636 480 8748 m3
port "io_oeb[1]" 121 583520 9818 584800 9930 m3
port "io_in_3v3[25]" 100 -800 9818 480 9930 m3
port "io_in_3v3[2]" 102 583520 11000 584800 11112 m3
port "io_oeb[24]" 126 -800 11000 480 11112 m3
port "io_in[2]" 75 583520 12182 584800 12294 m3
port "io_out[24]" 153 -800 12182 480 12294 m3
port "io_out[2]" 156 583520 13364 584800 13476 m3
port "io_in[24]" 72 -800 13364 480 13476 m3
port "io_oeb[2]" 129 583520 14546 584800 14658 m3
port "io_in_3v3[24]" 99 -800 14546 480 14658 m3
port "io_in_3v3[3]" 103 583520 15728 584800 15840 m3
port "gpio_noesd[17]" 26 -800 15728 480 15840 m3
port "io_in[3]" 76 583520 16910 584800 17022 m3
port "gpio_analog[17]" 8 -800 16910 480 17022 m3
port "io_out[3]" 157 583520 18092 584800 18204 m3
port "io_oeb[3]" 130 583520 19274 584800 19386 m3
port "io_in_3v3[4]" 104 583520 20456 584800 20568 m3
port "io_in[4]" 77 583520 21638 584800 21750 m3
port "io_out[4]" 158 583520 22820 584800 22932 m3
port "io_oeb[4]" 131 583520 24002 584800 24114 m3
port "io_oeb[23]" 125 -800 32422 480 32534 m3
port "io_out[23]" 152 -800 33604 480 33716 m3
port "io_in[23]" 71 -800 34786 480 34898 m3
port "io_in_3v3[23]" 98 -800 35968 480 36080 m3
port "gpio_noesd[16]" 25 -800 37150 480 37262 m3
port "gpio_analog[16]" 7 -800 38332 480 38444 m3
port "io_in_3v3[5]" 105 583520 46914 584800 47026 m3
port "io_in[5]" 78 583520 48096 584800 48208 m3
port "io_out[5]" 159 583520 49278 584800 49390 m3
port "io_oeb[5]" 132 583520 50460 584800 50572 m3
port "io_oeb[22]" 124 -800 75644 480 75756 m3
port "io_out[22]" 151 -800 76826 480 76938 m3
port "io_in[22]" 70 -800 78008 480 78120 m3
port "io_in_3v3[22]" 97 -800 79190 480 79302 m3
port "gpio_noesd[15]" 24 -800 80372 480 80484 m3
port "gpio_analog[15]" 6 -800 81554 480 81666 m3
port "io_in_3v3[6]" 106 583520 91572 584800 91684 m3
port "io_in[6]" 79 583520 92754 584800 92866 m3
port "io_out[6]" 160 583520 93936 584800 94048 m3
port "io_oeb[6]" 133 583520 95118 584800 95230 m3
port "io_oeb[21]" 123 -800 118866 480 118978 m3
port "io_out[21]" 150 -800 120048 480 120160 m3
port "io_in[21]" 69 -800 121230 480 121342 m3
port "io_in_3v3[21]" 96 -800 122412 480 122524 m3
port "gpio_noesd[14]" 23 -800 123594 480 123706 m3
port "gpio_analog[14]" 5 -800 124776 480 124888 m3
port "vssa1" 565 582340 136830 584800 141630 m3
port "vssa1" 564 582340 146830 584800 151630 m3
port "vssd1" 569 582340 181430 584800 186230 m3
port "vssd1" 568 582340 191430 584800 196230 m3
port "vssd2" 571 0 162888 1660 167688 m3
port "vssd2" 570 0 172888 1660 177688 m3
port "vdda1" 559 582340 225230 584800 230030 m3
port "vdda1" 558 582340 235230 584800 240030 m3
port "gpio_analog[0]" 0 583520 269230 584800 269342 m3
port "gpio_noesd[0]" 18 583520 270412 584800 270524 m3
port "io_in_3v3[7]" 107 583520 271594 584800 271706 m3
port "io_in[7]" 80 583520 272776 584800 272888 m3
port "io_out[7]" 161 583520 273958 584800 274070 m3
port "io_oeb[7]" 134 583520 275140 584800 275252 m3
port "gpio_analog[1]" 9 583520 313652 584800 313764 m3
port "gpio_noesd[1]" 27 583520 314834 584800 314946 m3
port "io_in_3v3[8]" 108 583520 316016 584800 316128 m3
port "io_in[8]" 81 583520 317198 584800 317310 m3
port "io_out[8]" 162 583520 318380 584800 318492 m3
port "io_oeb[8]" 135 583520 319562 584800 319674 m3
port "gpio_analog[2]" 10 583520 358874 584800 358986 m3
port "gpio_noesd[2]" 28 583520 360056 584800 360168 m3
port "io_in_3v3[9]" 109 583520 361238 584800 361350 m3
port "io_in[9]" 82 583520 362420 584800 362532 m3
port "io_out[9]" 163 583520 363602 584800 363714 m3
port "io_oeb[9]" 136 583520 364784 584800 364896 m3
port "gpio_analog[3]" 11 583520 405296 584800 405408 m3
port "gpio_noesd[3]" 29 583520 406478 584800 406590 m3
port "io_in_3v3[10]" 84 583520 407660 584800 407772 m3
port "io_in[10]" 57 583520 408842 584800 408954 m3
port "io_out[10]" 138 583520 410024 584800 410136 m3
port "io_oeb[10]" 111 583520 411206 584800 411318 m3
port "gpio_analog[4]" 12 583520 449718 584800 449830 m3
port "gpio_noesd[4]" 30 583520 450900 584800 451012 m3
port "io_in_3v3[11]" 85 583520 452082 584800 452194 m3
port "io_in[11]" 58 583520 453264 584800 453376 m3
port "io_out[11]" 139 583520 454446 584800 454558 m3
port "io_oeb[11]" 112 583520 455628 584800 455740 m3
port "gpio_analog[5]" 13 583520 494140 584800 494252 m3
port "gpio_noesd[5]" 31 583520 495322 584800 495434 m3
port "io_in_3v3[12]" 86 583520 496504 584800 496616 m3
port "io_in[12]" 59 583520 497686 584800 497798 m3
port "io_out[12]" 140 583520 498868 584800 498980 m3
port "io_oeb[12]" 113 583520 500050 584800 500162 m3
port "vdda1" 556 582340 540562 584800 545362 m3
port "vdda1" 557 582340 550562 584800 555362 m3
port "gpio_analog[6]" 14 583520 583562 584800 583674 m3
port "gpio_noesd[6]" 32 583520 584744 584800 584856 m3
port "io_in_3v3[13]" 87 583520 585926 584800 586038 m3
port "io_in[13]" 60 583520 587108 584800 587220 m3
port "io_out[13]" 141 583520 588290 584800 588402 m3
port "io_oeb[13]" 114 583520 589472 584800 589584 m3
port "vdda2" 560 0 204888 1660 209688 m3
port "io_analog[0]" 36 582300 677984 584800 682984 m3
port "vdda2" 561 0 214888 1660 219688 m3
port "io_oeb[20]" 122 -800 246488 480 246600 m3
port "io_out[20]" 149 -800 247670 480 247782 m3
port "io_in[20]" 68 -800 248852 480 248964 m3
port "io_in_3v3[20]" 95 -800 250034 480 250146 m3
port "gpio_noesd[13]" 22 -800 251216 480 251328 m3
port "gpio_analog[13]" 4 -800 252398 480 252510 m3
port "io_oeb[19]" 120 -800 289510 480 289622 m3
port "io_out[19]" 147 -800 290692 480 290804 m3
port "io_in[19]" 66 -800 291874 480 291986 m3
port "io_in_3v3[19]" 93 -800 293056 480 293168 m3
port "gpio_noesd[12]" 21 -800 294238 480 294350 m3
port "gpio_analog[12]" 3 -800 295420 480 295532 m3
port "io_oeb[18]" 119 -800 332732 480 332844 m3
port "io_out[18]" 146 -800 333914 480 334026 m3
port "io_in[18]" 65 -800 335096 480 335208 m3
port "io_in_3v3[18]" 92 -800 336278 480 336390 m3
port "gpio_noesd[11]" 20 -800 337460 480 337572 m3
port "gpio_analog[11]" 2 -800 338642 480 338754 m3
port "io_oeb[17]" 118 -800 375954 480 376066 m3
port "io_out[17]" 145 -800 377136 480 377248 m3
port "io_in[17]" 64 -800 378318 480 378430 m3
port "io_in_3v3[17]" 91 -800 379500 480 379612 m3
port "gpio_noesd[10]" 19 -800 380682 480 380794 m3
port "gpio_analog[10]" 1 -800 381864 480 381976 m3
port "io_oeb[16]" 117 -800 419176 480 419288 m3
port "io_out[16]" 144 -800 420358 480 420470 m3
port "io_in[16]" 63 -800 421540 480 421652 m3
port "io_in_3v3[16]" 90 -800 422722 480 422834 m3
port "gpio_noesd[9]" 35 -800 423904 480 424016 m3
port "gpio_analog[9]" 17 -800 425086 480 425198 m3
port "io_oeb[15]" 116 -800 462398 480 462510 m3
port "io_out[15]" 143 -800 463580 480 463692 m3
port "io_in[15]" 62 -800 464762 480 464874 m3
port "io_in_3v3[15]" 89 -800 465944 480 466056 m3
port "gpio_noesd[8]" 34 -800 467126 480 467238 m3
port "gpio_analog[8]" 16 -800 468308 480 468420 m3
port "io_oeb[14]" 115 -800 505620 480 505732 m3
port "io_out[14]" 142 -800 506802 480 506914 m3
port "io_in[14]" 61 -800 507984 480 508096 m3
port "io_in_3v3[14]" 88 -800 509166 480 509278 m3
port "gpio_noesd[7]" 33 -800 510348 480 510460 m3
port "gpio_analog[7]" 15 -800 511530 480 511642 m3
port "io_analog[5]" 48 217294 702300 222294 704800 m4
port "io_analog[4]" 47 318994 702300 323994 704800 m4
port "io_analog[1]" 38 566594 702300 571594 704800 m3
port "vssa1" 562 520594 702340 525394 704800 m3
port "vssa1" 563 510594 702340 515394 704800 m3
port "io_analog[2]" 39 465394 702300 470394 704800 m3
port "io_analog[3]" 40 413394 702300 418394 704800 m3
port "io_analog[4]" 41 329294 702300 334294 704800 m3
port "io_clamp_high[0]" 50 326794 702300 328994 704800 m3
port "io_clamp_low[0]" 53 324294 702300 326494 704800 m3
port "io_analog[4]" 47 318994 702300 323994 704800 m3
port "io_analog[5]" 42 227594 702300 232594 704800 m3
port "io_clamp_high[1]" 51 225094 702300 227294 704800 m3
port "io_clamp_low[1]" 54 222594 702300 224794 704800 m3
port "io_analog[5]" 48 217294 702300 222294 704800 m3
port "io_analog[6]" 43 175894 702300 180894 704800 m3
port "io_clamp_high[2]" 52 173394 702300 175594 704800 m3
port "io_clamp_low[2]" 55 170894 702300 173094 704800 m3
port "io_analog[6]" 49 165594 702300 170594 704800 m3
port "io_analog[7]" 44 120194 702300 125194 704800 m3
port "io_analog[8]" 45 68194 702300 73194 704800 m3
port "io_analog[9]" 46 16194 702300 21194 704800 m3
port "user_irq[2]" 551 583250 -800 583362 480 m2
port "user_irq[1]" 550 582068 -800 582180 480 m2
port "user_irq[0]" 549 580886 -800 580998 480 m2
port "user_clock2" 548 579704 -800 579816 480 m2
port "la_oenb[127]" 450 578522 -800 578634 480 m2
port "la_data_out[127]" 322 577340 -800 577452 480 m2
port "la_oenb[126]" 449 574976 -800 575088 480 m2
port "la_data_out[126]" 321 573794 -800 573906 480 m2
port "la_oenb[125]" 448 571430 -800 571542 480 m2
port "la_data_out[125]" 320 570248 -800 570360 480 m2
port "la_oenb[124]" 447 567884 -800 567996 480 m2
port "la_data_out[124]" 319 566702 -800 566814 480 m2
port "la_data_in[125]" 192 569066 -800 569178 480 m2
port "la_oenb[123]" 446 564338 -800 564450 480 m2
port "la_data_out[123]" 318 563156 -800 563268 480 m2
port "la_oenb[122]" 445 560792 -800 560904 480 m2
port "la_data_out[122]" 317 559610 -800 559722 480 m2
port "la_data_in[123]" 190 561974 -800 562086 480 m2
port "la_oenb[121]" 444 557246 -800 557358 480 m2
port "la_data_out[121]" 316 556064 -800 556176 480 m2
port "la_oenb[120]" 443 553700 -800 553812 480 m2
port "la_data_out[120]" 315 552518 -800 552630 480 m2
port "la_data_in[121]" 188 554882 -800 554994 480 m2
port "la_data_in[127]" 194 576158 -800 576270 480 m2
port "la_oenb[119]" 441 550154 -800 550266 480 m2
port "la_data_out[119]" 313 548972 -800 549084 480 m2
port "la_data_in[119]" 185 547790 -800 547902 480 m2
port "la_oenb[118]" 440 546608 -800 546720 480 m2
port "la_data_out[118]" 312 545426 -800 545538 480 m2
port "la_data_in[118]" 184 544244 -800 544356 480 m2
port "la_oenb[117]" 439 543062 -800 543174 480 m2
port "la_data_out[117]" 311 541880 -800 541992 480 m2
port "la_data_in[117]" 183 540698 -800 540810 480 m2
port "la_oenb[116]" 438 539516 -800 539628 480 m2
port "la_data_out[116]" 310 538334 -800 538446 480 m2
port "la_data_in[116]" 182 537152 -800 537264 480 m2
port "la_oenb[115]" 437 535970 -800 536082 480 m2
port "la_data_out[115]" 309 534788 -800 534900 480 m2
port "la_data_in[115]" 181 533606 -800 533718 480 m2
port "la_oenb[114]" 436 532424 -800 532536 480 m2
port "la_data_out[114]" 308 531242 -800 531354 480 m2
port "la_data_in[114]" 180 530060 -800 530172 480 m2
port "la_oenb[113]" 435 528878 -800 528990 480 m2
port "la_data_out[113]" 307 527696 -800 527808 480 m2
port "la_data_in[113]" 179 526514 -800 526626 480 m2
port "la_oenb[112]" 434 525332 -800 525444 480 m2
port "la_data_out[112]" 306 524150 -800 524262 480 m2
port "la_data_in[112]" 178 522968 -800 523080 480 m2
port "la_oenb[111]" 433 521786 -800 521898 480 m2
port "la_data_out[111]" 305 520604 -800 520716 480 m2
port "la_data_in[111]" 177 519422 -800 519534 480 m2
port "la_oenb[110]" 432 518240 -800 518352 480 m2
port "la_data_out[110]" 304 517058 -800 517170 480 m2
port "la_data_in[110]" 176 515876 -800 515988 480 m2
port "la_oenb[109]" 430 514694 -800 514806 480 m2
port "la_data_out[109]" 302 513512 -800 513624 480 m2
port "la_data_in[109]" 174 512330 -800 512442 480 m2
port "la_oenb[108]" 429 511148 -800 511260 480 m2
port "la_data_out[108]" 301 509966 -800 510078 480 m2
port "la_data_in[108]" 173 508784 -800 508896 480 m2
port "la_oenb[107]" 428 507602 -800 507714 480 m2
port "la_data_out[107]" 300 506420 -800 506532 480 m2
port "la_data_in[107]" 172 505238 -800 505350 480 m2
port "la_oenb[106]" 427 504056 -800 504168 480 m2
port "la_data_out[106]" 299 502874 -800 502986 480 m2
port "la_data_in[106]" 171 501692 -800 501804 480 m2
port "la_oenb[105]" 426 500510 -800 500622 480 m2
port "la_data_out[105]" 298 499328 -800 499440 480 m2
port "la_data_in[105]" 170 498146 -800 498258 480 m2
port "la_oenb[104]" 425 496964 -800 497076 480 m2
port "la_data_out[104]" 297 495782 -800 495894 480 m2
port "la_data_in[104]" 169 494600 -800 494712 480 m2
port "la_oenb[103]" 424 493418 -800 493530 480 m2
port "la_data_out[103]" 296 492236 -800 492348 480 m2
port "la_data_in[103]" 168 491054 -800 491166 480 m2
port "la_oenb[102]" 423 489872 -800 489984 480 m2
port "la_data_out[102]" 295 488690 -800 488802 480 m2
port "la_data_in[102]" 167 487508 -800 487620 480 m2
port "la_oenb[101]" 422 486326 -800 486438 480 m2
port "la_data_out[101]" 294 485144 -800 485256 480 m2
port "la_data_in[101]" 166 483962 -800 484074 480 m2
port "la_oenb[100]" 421 482780 -800 482892 480 m2
port "la_data_out[100]" 293 481598 -800 481710 480 m2
port "la_data_in[100]" 165 480416 -800 480528 480 m2
port "la_oenb[99]" 546 479234 -800 479346 480 m2
port "la_data_out[99]" 418 478052 -800 478164 480 m2
port "la_data_in[99]" 290 476870 -800 476982 480 m2
port "la_oenb[98]" 545 475688 -800 475800 480 m2
port "la_data_out[98]" 417 474506 -800 474618 480 m2
port "la_data_in[98]" 289 473324 -800 473436 480 m2
port "la_oenb[97]" 544 472142 -800 472254 480 m2
port "la_data_out[97]" 416 470960 -800 471072 480 m2
port "la_data_in[97]" 288 469778 -800 469890 480 m2
port "la_oenb[96]" 543 468596 -800 468708 480 m2
port "la_data_out[96]" 415 467414 -800 467526 480 m2
port "la_data_in[96]" 287 466232 -800 466344 480 m2
port "la_oenb[95]" 542 465050 -800 465162 480 m2
port "la_data_out[95]" 414 463868 -800 463980 480 m2
port "la_data_in[95]" 286 462686 -800 462798 480 m2
port "la_oenb[94]" 541 461504 -800 461616 480 m2
port "la_data_out[94]" 413 460322 -800 460434 480 m2
port "la_data_in[94]" 285 459140 -800 459252 480 m2
port "la_oenb[93]" 540 457958 -800 458070 480 m2
port "la_data_out[93]" 412 456776 -800 456888 480 m2
port "la_data_in[93]" 284 455594 -800 455706 480 m2
port "la_oenb[92]" 539 454412 -800 454524 480 m2
port "la_data_out[92]" 411 453230 -800 453342 480 m2
port "la_data_in[92]" 283 452048 -800 452160 480 m2
port "la_oenb[91]" 538 450866 -800 450978 480 m2
port "la_data_out[91]" 410 449684 -800 449796 480 m2
port "la_data_in[91]" 282 448502 -800 448614 480 m2
port "la_oenb[90]" 537 447320 -800 447432 480 m2
port "la_data_out[90]" 409 446138 -800 446250 480 m2
port "la_data_in[90]" 281 444956 -800 445068 480 m2
port "la_oenb[89]" 535 443774 -800 443886 480 m2
port "la_data_out[89]" 407 442592 -800 442704 480 m2
port "la_data_in[89]" 279 441410 -800 441522 480 m2
port "la_oenb[88]" 534 440228 -800 440340 480 m2
port "la_data_out[88]" 406 439046 -800 439158 480 m2
port "la_data_in[88]" 278 437864 -800 437976 480 m2
port "la_oenb[87]" 533 436682 -800 436794 480 m2
port "la_data_out[87]" 405 435500 -800 435612 480 m2
port "la_data_in[87]" 277 434318 -800 434430 480 m2
port "la_oenb[86]" 532 433136 -800 433248 480 m2
port "la_data_out[86]" 404 431954 -800 432066 480 m2
port "la_data_in[86]" 276 430772 -800 430884 480 m2
port "la_oenb[85]" 531 429590 -800 429702 480 m2
port "la_data_out[85]" 403 428408 -800 428520 480 m2
port "la_data_in[85]" 275 427226 -800 427338 480 m2
port "la_oenb[84]" 530 426044 -800 426156 480 m2
port "la_data_out[84]" 402 424862 -800 424974 480 m2
port "la_data_in[84]" 274 423680 -800 423792 480 m2
port "la_oenb[83]" 529 422498 -800 422610 480 m2
port "la_data_out[83]" 401 421316 -800 421428 480 m2
port "la_data_in[83]" 273 420134 -800 420246 480 m2
port "la_oenb[82]" 528 418952 -800 419064 480 m2
port "la_data_out[82]" 400 417770 -800 417882 480 m2
port "la_data_in[82]" 272 416588 -800 416700 480 m2
port "la_oenb[81]" 527 415406 -800 415518 480 m2
port "la_data_out[81]" 399 414224 -800 414336 480 m2
port "la_data_in[81]" 271 413042 -800 413154 480 m2
port "la_oenb[80]" 526 411860 -800 411972 480 m2
port "la_data_out[80]" 398 410678 -800 410790 480 m2
port "la_data_in[80]" 270 409496 -800 409608 480 m2
port "la_oenb[79]" 524 408314 -800 408426 480 m2
port "la_data_out[79]" 396 407132 -800 407244 480 m2
port "la_data_in[79]" 268 405950 -800 406062 480 m2
port "la_oenb[78]" 523 404768 -800 404880 480 m2
port "la_data_out[78]" 395 403586 -800 403698 480 m2
port "la_data_in[78]" 267 402404 -800 402516 480 m2
port "la_oenb[77]" 522 401222 -800 401334 480 m2
port "la_data_out[77]" 394 400040 -800 400152 480 m2
port "la_data_in[77]" 266 398858 -800 398970 480 m2
port "la_oenb[76]" 521 397676 -800 397788 480 m2
port "la_data_out[76]" 393 396494 -800 396606 480 m2
port "la_data_in[76]" 265 395312 -800 395424 480 m2
port "la_oenb[75]" 520 394130 -800 394242 480 m2
port "la_data_out[75]" 392 392948 -800 393060 480 m2
port "la_data_in[75]" 264 391766 -800 391878 480 m2
port "la_oenb[74]" 519 390584 -800 390696 480 m2
port "la_data_out[74]" 391 389402 -800 389514 480 m2
port "la_data_in[74]" 263 388220 -800 388332 480 m2
port "la_oenb[73]" 518 387038 -800 387150 480 m2
port "la_data_out[73]" 390 385856 -800 385968 480 m2
port "la_data_in[73]" 262 384674 -800 384786 480 m2
port "la_oenb[72]" 517 383492 -800 383604 480 m2
port "la_data_out[72]" 389 382310 -800 382422 480 m2
port "la_data_in[72]" 261 381128 -800 381240 480 m2
port "la_oenb[71]" 516 379946 -800 380058 480 m2
port "la_data_out[71]" 388 378764 -800 378876 480 m2
port "la_data_in[71]" 260 377582 -800 377694 480 m2
port "la_oenb[70]" 515 376400 -800 376512 480 m2
port "la_data_out[70]" 387 375218 -800 375330 480 m2
port "la_data_in[70]" 259 374036 -800 374148 480 m2
port "la_oenb[69]" 513 372854 -800 372966 480 m2
port "la_data_out[69]" 385 371672 -800 371784 480 m2
port "la_data_in[69]" 257 370490 -800 370602 480 m2
port "la_oenb[68]" 512 369308 -800 369420 480 m2
port "la_data_out[68]" 384 368126 -800 368238 480 m2
port "la_data_in[68]" 256 366944 -800 367056 480 m2
port "la_oenb[67]" 511 365762 -800 365874 480 m2
port "la_data_out[67]" 383 364580 -800 364692 480 m2
port "la_data_in[67]" 255 363398 -800 363510 480 m2
port "la_oenb[66]" 510 362216 -800 362328 480 m2
port "la_data_out[66]" 382 361034 -800 361146 480 m2
port "la_data_in[66]" 254 359852 -800 359964 480 m2
port "la_oenb[65]" 509 358670 -800 358782 480 m2
port "la_data_out[65]" 381 357488 -800 357600 480 m2
port "la_data_in[65]" 253 356306 -800 356418 480 m2
port "la_oenb[64]" 508 355124 -800 355236 480 m2
port "la_data_out[64]" 380 353942 -800 354054 480 m2
port "la_data_in[64]" 252 352760 -800 352872 480 m2
port "la_oenb[63]" 507 351578 -800 351690 480 m2
port "la_data_out[63]" 379 350396 -800 350508 480 m2
port "la_data_in[63]" 251 349214 -800 349326 480 m2
port "la_oenb[62]" 506 348032 -800 348144 480 m2
port "la_data_out[62]" 378 346850 -800 346962 480 m2
port "la_data_in[62]" 250 345668 -800 345780 480 m2
port "la_oenb[61]" 505 344486 -800 344598 480 m2
port "la_data_out[61]" 377 343304 -800 343416 480 m2
port "la_data_in[61]" 249 342122 -800 342234 480 m2
port "la_oenb[60]" 504 340940 -800 341052 480 m2
port "la_data_out[60]" 376 339758 -800 339870 480 m2
port "la_data_in[60]" 248 338576 -800 338688 480 m2
port "la_oenb[59]" 502 337394 -800 337506 480 m2
port "la_data_out[59]" 374 336212 -800 336324 480 m2
port "la_data_in[59]" 246 335030 -800 335142 480 m2
port "la_oenb[58]" 501 333848 -800 333960 480 m2
port "la_data_out[58]" 373 332666 -800 332778 480 m2
port "la_data_in[58]" 245 331484 -800 331596 480 m2
port "la_oenb[57]" 500 330302 -800 330414 480 m2
port "la_data_out[57]" 372 329120 -800 329232 480 m2
port "la_data_in[57]" 244 327938 -800 328050 480 m2
port "la_oenb[56]" 499 326756 -800 326868 480 m2
port "la_data_out[56]" 371 325574 -800 325686 480 m2
port "la_data_in[56]" 243 324392 -800 324504 480 m2
port "la_oenb[55]" 498 323210 -800 323322 480 m2
port "la_data_out[55]" 370 322028 -800 322140 480 m2
port "la_data_in[55]" 242 320846 -800 320958 480 m2
port "la_oenb[54]" 497 319664 -800 319776 480 m2
port "la_data_out[54]" 369 318482 -800 318594 480 m2
port "la_data_in[54]" 241 317300 -800 317412 480 m2
port "la_oenb[53]" 496 316118 -800 316230 480 m2
port "la_data_out[53]" 368 314936 -800 315048 480 m2
port "la_data_in[53]" 240 313754 -800 313866 480 m2
port "la_oenb[52]" 495 312572 -800 312684 480 m2
port "la_data_out[52]" 367 311390 -800 311502 480 m2
port "la_data_in[52]" 239 310208 -800 310320 480 m2
port "la_oenb[51]" 494 309026 -800 309138 480 m2
port "la_data_out[51]" 366 307844 -800 307956 480 m2
port "la_data_in[51]" 238 306662 -800 306774 480 m2
port "la_oenb[50]" 493 305480 -800 305592 480 m2
port "la_data_out[50]" 365 304298 -800 304410 480 m2
port "la_data_in[50]" 237 303116 -800 303228 480 m2
port "la_oenb[49]" 491 301934 -800 302046 480 m2
port "la_data_out[49]" 363 300752 -800 300864 480 m2
port "la_data_in[49]" 235 299570 -800 299682 480 m2
port "la_oenb[48]" 490 298388 -800 298500 480 m2
port "la_data_out[48]" 362 297206 -800 297318 480 m2
port "la_data_in[48]" 234 296024 -800 296136 480 m2
port "la_oenb[47]" 489 294842 -800 294954 480 m2
port "la_data_out[47]" 361 293660 -800 293772 480 m2
port "la_data_in[47]" 233 292478 -800 292590 480 m2
port "la_oenb[46]" 488 291296 -800 291408 480 m2
port "la_data_out[46]" 360 290114 -800 290226 480 m2
port "la_data_in[46]" 232 288932 -800 289044 480 m2
port "la_oenb[45]" 487 287750 -800 287862 480 m2
port "la_data_out[45]" 359 286568 -800 286680 480 m2
port "la_data_in[45]" 231 285386 -800 285498 480 m2
port "la_oenb[44]" 486 284204 -800 284316 480 m2
port "la_data_out[44]" 358 283022 -800 283134 480 m2
port "la_data_in[44]" 230 281840 -800 281952 480 m2
port "la_oenb[43]" 485 280658 -800 280770 480 m2
port "la_data_out[43]" 357 279476 -800 279588 480 m2
port "la_data_in[43]" 229 278294 -800 278406 480 m2
port "la_oenb[42]" 484 277112 -800 277224 480 m2
port "la_data_out[42]" 356 275930 -800 276042 480 m2
port "la_data_in[42]" 228 274748 -800 274860 480 m2
port "la_oenb[41]" 483 273566 -800 273678 480 m2
port "la_data_out[41]" 355 272384 -800 272496 480 m2
port "la_data_in[41]" 227 271202 -800 271314 480 m2
port "la_oenb[40]" 482 270020 -800 270132 480 m2
port "la_data_out[40]" 354 268838 -800 268950 480 m2
port "la_data_in[40]" 226 267656 -800 267768 480 m2
port "la_oenb[39]" 480 266474 -800 266586 480 m2
port "la_data_out[39]" 352 265292 -800 265404 480 m2
port "la_data_in[39]" 224 264110 -800 264222 480 m2
port "la_oenb[38]" 479 262928 -800 263040 480 m2
port "la_data_out[38]" 351 261746 -800 261858 480 m2
port "la_data_in[38]" 223 260564 -800 260676 480 m2
port "la_oenb[37]" 478 259382 -800 259494 480 m2
port "la_data_out[37]" 350 258200 -800 258312 480 m2
port "la_data_in[37]" 222 257018 -800 257130 480 m2
port "la_oenb[36]" 477 255836 -800 255948 480 m2
port "la_data_out[36]" 349 254654 -800 254766 480 m2
port "la_data_in[36]" 221 253472 -800 253584 480 m2
port "la_oenb[35]" 476 252290 -800 252402 480 m2
port "la_data_out[35]" 348 251108 -800 251220 480 m2
port "la_data_in[35]" 220 249926 -800 250038 480 m2
port "la_oenb[34]" 475 248744 -800 248856 480 m2
port "la_data_out[34]" 347 247562 -800 247674 480 m2
port "la_data_in[34]" 219 246380 -800 246492 480 m2
port "la_oenb[33]" 474 245198 -800 245310 480 m2
port "la_data_out[33]" 346 244016 -800 244128 480 m2
port "la_data_in[33]" 218 242834 -800 242946 480 m2
port "la_oenb[32]" 473 241652 -800 241764 480 m2
port "la_data_out[32]" 345 240470 -800 240582 480 m2
port "la_data_in[32]" 217 239288 -800 239400 480 m2
port "la_oenb[31]" 472 238106 -800 238218 480 m2
port "la_data_out[31]" 344 236924 -800 237036 480 m2
port "la_data_in[31]" 216 235742 -800 235854 480 m2
port "la_oenb[30]" 471 234560 -800 234672 480 m2
port "la_data_out[30]" 343 233378 -800 233490 480 m2
port "la_data_in[30]" 215 232196 -800 232308 480 m2
port "la_oenb[29]" 469 231014 -800 231126 480 m2
port "la_data_out[29]" 341 229832 -800 229944 480 m2
port "la_data_in[29]" 213 228650 -800 228762 480 m2
port "la_oenb[28]" 468 227468 -800 227580 480 m2
port "la_data_out[28]" 340 226286 -800 226398 480 m2
port "la_data_in[28]" 212 225104 -800 225216 480 m2
port "la_oenb[27]" 467 223922 -800 224034 480 m2
port "la_data_out[27]" 339 222740 -800 222852 480 m2
port "la_data_in[27]" 211 221558 -800 221670 480 m2
port "la_oenb[26]" 466 220376 -800 220488 480 m2
port "la_data_out[26]" 338 219194 -800 219306 480 m2
port "la_data_in[26]" 210 218012 -800 218124 480 m2
port "la_oenb[25]" 465 216830 -800 216942 480 m2
port "la_data_out[25]" 337 215648 -800 215760 480 m2
port "la_data_in[25]" 209 214466 -800 214578 480 m2
port "la_oenb[24]" 464 213284 -800 213396 480 m2
port "la_data_out[24]" 336 212102 -800 212214 480 m2
port "la_data_in[24]" 208 210920 -800 211032 480 m2
port "la_oenb[23]" 463 209738 -800 209850 480 m2
port "la_data_out[23]" 335 208556 -800 208668 480 m2
port "la_data_in[23]" 207 207374 -800 207486 480 m2
port "la_oenb[22]" 462 206192 -800 206304 480 m2
port "la_data_out[22]" 334 205010 -800 205122 480 m2
port "la_data_in[22]" 206 203828 -800 203940 480 m2
port "la_oenb[21]" 461 202646 -800 202758 480 m2
port "la_data_out[21]" 333 201464 -800 201576 480 m2
port "la_data_in[21]" 205 200282 -800 200394 480 m2
port "la_oenb[20]" 460 199100 -800 199212 480 m2
port "la_data_out[20]" 332 197918 -800 198030 480 m2
port "la_data_in[20]" 204 196736 -800 196848 480 m2
port "la_oenb[19]" 458 195554 -800 195666 480 m2
port "la_data_out[19]" 330 194372 -800 194484 480 m2
port "la_data_in[19]" 202 193190 -800 193302 480 m2
port "la_oenb[18]" 457 192008 -800 192120 480 m2
port "la_data_out[18]" 329 190826 -800 190938 480 m2
port "la_data_in[18]" 201 189644 -800 189756 480 m2
port "la_oenb[17]" 456 188462 -800 188574 480 m2
port "la_data_out[17]" 328 187280 -800 187392 480 m2
port "la_data_in[17]" 200 186098 -800 186210 480 m2
port "la_oenb[16]" 455 184916 -800 185028 480 m2
port "la_data_out[16]" 327 183734 -800 183846 480 m2
port "la_data_in[16]" 199 182552 -800 182664 480 m2
port "la_oenb[15]" 454 181370 -800 181482 480 m2
port "la_data_out[15]" 326 180188 -800 180300 480 m2
port "la_data_in[15]" 198 179006 -800 179118 480 m2
port "la_oenb[14]" 453 177824 -800 177936 480 m2
port "la_data_out[14]" 325 176642 -800 176754 480 m2
port "la_data_in[14]" 197 175460 -800 175572 480 m2
port "la_oenb[13]" 452 174278 -800 174390 480 m2
port "la_data_out[13]" 324 173096 -800 173208 480 m2
port "la_data_in[13]" 196 171914 -800 172026 480 m2
port "la_oenb[12]" 451 170732 -800 170844 480 m2
port "la_data_out[12]" 323 169550 -800 169662 480 m2
port "la_data_in[12]" 195 168368 -800 168480 480 m2
port "la_oenb[11]" 442 167186 -800 167298 480 m2
port "la_data_out[11]" 314 166004 -800 166116 480 m2
port "la_data_in[11]" 186 164822 -800 164934 480 m2
port "la_oenb[10]" 431 163640 -800 163752 480 m2
port "la_data_out[10]" 303 162458 -800 162570 480 m2
port "la_data_in[10]" 175 161276 -800 161388 480 m2
port "la_oenb[9]" 547 160094 -800 160206 480 m2
port "la_data_out[9]" 419 158912 -800 159024 480 m2
port "la_data_in[9]" 291 157730 -800 157842 480 m2
port "la_oenb[8]" 536 156548 -800 156660 480 m2
port "la_data_in[8]" 280 154184 -800 154296 480 m2
port "la_oenb[7]" 525 153002 -800 153114 480 m2
port "la_data_in[7]" 269 150638 -800 150750 480 m2
port "la_oenb[6]" 514 149456 -800 149568 480 m2
port "la_data_in[6]" 258 147092 -800 147204 480 m2
port "la_oenb[5]" 503 145910 -800 146022 480 m2
port "la_data_in[5]" 247 143546 -800 143658 480 m2
port "la_oenb[4]" 492 142364 -800 142476 480 m2
port "la_data_in[4]" 236 140000 -800 140112 480 m2
port "la_oenb[3]" 481 138818 -800 138930 480 m2
port "la_data_in[3]" 225 136454 -800 136566 480 m2
port "la_oenb[2]" 470 135272 -800 135384 480 m2
port "la_data_in[2]" 214 132908 -800 133020 480 m2
port "la_oenb[1]" 459 131726 -800 131838 480 m2
port "la_data_in[1]" 203 129362 -800 129474 480 m2
port "la_oenb[0]" 420 128180 -800 128292 480 m2
port "la_data_out[0]" 292 126998 -800 127110 480 m2
port "la_data_in[0]" 164 125816 -800 125928 480 m2
port "wbs_dat_o[31]" 664 124634 -800 124746 480 m2
port "wbs_dat_i[31]" 632 123452 -800 123564 480 m2
port "wbs_adr_i[31]" 599 122270 -800 122382 480 m2
port "wbs_dat_o[30]" 663 121088 -800 121200 480 m2
port "wbs_dat_i[30]" 631 119906 -800 120018 480 m2
port "wbs_adr_i[30]" 598 118724 -800 118836 480 m2
port "wbs_dat_o[29]" 661 117542 -800 117654 480 m2
port "wbs_dat_i[29]" 629 116360 -800 116472 480 m2
port "wbs_adr_i[29]" 596 115178 -800 115290 480 m2
port "wbs_dat_o[28]" 660 113996 -800 114108 480 m2
port "wbs_dat_i[28]" 628 112814 -800 112926 480 m2
port "wbs_adr_i[28]" 595 111632 -800 111744 480 m2
port "wbs_dat_o[27]" 659 110450 -800 110562 480 m2
port "wbs_dat_i[27]" 627 109268 -800 109380 480 m2
port "wbs_adr_i[27]" 594 108086 -800 108198 480 m2
port "wbs_dat_o[26]" 658 106904 -800 107016 480 m2
port "wbs_dat_i[26]" 626 105722 -800 105834 480 m2
port "wbs_adr_i[26]" 593 104540 -800 104652 480 m2
port "wbs_dat_o[25]" 657 103358 -800 103470 480 m2
port "wbs_dat_i[25]" 625 102176 -800 102288 480 m2
port "wbs_adr_i[25]" 592 100994 -800 101106 480 m2
port "wbs_dat_o[24]" 656 99812 -800 99924 480 m2
port "wbs_dat_i[24]" 624 98630 -800 98742 480 m2
port "wbs_adr_i[24]" 591 97448 -800 97560 480 m2
port "wbs_dat_o[23]" 655 96266 -800 96378 480 m2
port "wbs_dat_i[23]" 623 95084 -800 95196 480 m2
port "wbs_adr_i[23]" 590 93902 -800 94014 480 m2
port "wbs_dat_o[22]" 654 92720 -800 92832 480 m2
port "wbs_dat_i[22]" 622 91538 -800 91650 480 m2
port "wbs_adr_i[22]" 589 90356 -800 90468 480 m2
port "wbs_dat_o[21]" 653 89174 -800 89286 480 m2
port "wbs_dat_i[21]" 621 87992 -800 88104 480 m2
port "wbs_adr_i[21]" 588 86810 -800 86922 480 m2
port "wbs_dat_o[20]" 652 85628 -800 85740 480 m2
port "wbs_dat_i[20]" 620 84446 -800 84558 480 m2
port "wbs_adr_i[20]" 587 83264 -800 83376 480 m2
port "wbs_dat_o[19]" 650 82082 -800 82194 480 m2
port "wbs_dat_i[19]" 618 80900 -800 81012 480 m2
port "wbs_adr_i[19]" 585 79718 -800 79830 480 m2
port "wbs_dat_o[18]" 649 78536 -800 78648 480 m2
port "wbs_dat_i[18]" 617 77354 -800 77466 480 m2
port "wbs_adr_i[18]" 584 76172 -800 76284 480 m2
port "wbs_dat_o[17]" 648 74990 -800 75102 480 m2
port "wbs_dat_i[17]" 616 73808 -800 73920 480 m2
port "wbs_adr_i[17]" 583 72626 -800 72738 480 m2
port "wbs_dat_o[16]" 647 71444 -800 71556 480 m2
port "wbs_dat_i[16]" 615 70262 -800 70374 480 m2
port "wbs_adr_i[16]" 582 69080 -800 69192 480 m2
port "wbs_dat_o[15]" 646 67898 -800 68010 480 m2
port "wbs_dat_i[15]" 614 66716 -800 66828 480 m2
port "wbs_adr_i[15]" 581 65534 -800 65646 480 m2
port "wbs_dat_o[14]" 645 64352 -800 64464 480 m2
port "wbs_dat_i[14]" 613 63170 -800 63282 480 m2
port "wbs_adr_i[14]" 580 61988 -800 62100 480 m2
port "wbs_dat_o[13]" 644 60806 -800 60918 480 m2
port "wbs_dat_i[13]" 612 59624 -800 59736 480 m2
port "wbs_adr_i[13]" 579 58442 -800 58554 480 m2
port "wbs_dat_o[12]" 643 57260 -800 57372 480 m2
port "wbs_dat_i[12]" 611 56078 -800 56190 480 m2
port "wbs_adr_i[12]" 578 54896 -800 55008 480 m2
port "wbs_dat_o[11]" 642 53714 -800 53826 480 m2
port "wbs_dat_i[11]" 610 52532 -800 52644 480 m2
port "wbs_adr_i[11]" 577 51350 -800 51462 480 m2
port "wbs_dat_o[10]" 641 50168 -800 50280 480 m2
port "wbs_dat_i[10]" 609 48986 -800 49098 480 m2
port "wbs_adr_i[10]" 576 47804 -800 47916 480 m2
port "wbs_dat_o[9]" 671 46622 -800 46734 480 m2
port "wbs_dat_i[9]" 639 45440 -800 45552 480 m2
port "wbs_adr_i[9]" 606 44258 -800 44370 480 m2
port "wbs_dat_o[8]" 670 43076 -800 43188 480 m2
port "wbs_dat_i[8]" 638 41894 -800 42006 480 m2
port "wbs_adr_i[8]" 605 40712 -800 40824 480 m2
port "wbs_dat_o[7]" 669 39530 -800 39642 480 m2
port "wbs_dat_i[7]" 637 38348 -800 38460 480 m2
port "wbs_adr_i[7]" 604 37166 -800 37278 480 m2
port "wbs_dat_o[6]" 668 35984 -800 36096 480 m2
port "wbs_dat_i[6]" 636 34802 -800 34914 480 m2
port "wbs_adr_i[6]" 603 33620 -800 33732 480 m2
port "wbs_dat_o[5]" 667 32438 -800 32550 480 m2
port "wbs_dat_i[5]" 635 31256 -800 31368 480 m2
port "wbs_adr_i[5]" 602 30074 -800 30186 480 m2
port "wbs_dat_o[4]" 666 28892 -800 29004 480 m2
port "wbs_dat_i[4]" 634 27710 -800 27822 480 m2
port "wbs_adr_i[4]" 601 26528 -800 26640 480 m2
port "wbs_sel_i[3]" 675 25346 -800 25458 480 m2
port "wbs_dat_o[3]" 665 24164 -800 24276 480 m2
port "wbs_dat_i[3]" 633 22982 -800 23094 480 m2
port "wbs_adr_i[3]" 600 21800 -800 21912 480 m2
port "wbs_sel_i[2]" 674 20618 -800 20730 480 m2
port "wbs_dat_o[2]" 662 19436 -800 19548 480 m2
port "wbs_dat_i[2]" 630 18254 -800 18366 480 m2
port "wbs_adr_i[2]" 597 17072 -800 17184 480 m2
port "wbs_sel_i[1]" 673 15890 -800 16002 480 m2
port "wbs_dat_o[1]" 651 14708 -800 14820 480 m2
port "wbs_dat_i[1]" 619 13526 -800 13638 480 m2
port "wbs_adr_i[1]" 586 12344 -800 12456 480 m2
port "wbs_sel_i[0]" 672 11162 -800 11274 480 m2
port "wbs_dat_o[0]" 640 9980 -800 10092 480 m2
port "wbs_dat_i[0]" 608 8798 -800 8910 480 m2
port "wbs_adr_i[0]" 575 7616 -800 7728 480 m2
port "wbs_we_i" 677 6434 -800 6546 480 m2
port "wbs_stb_i" 676 5252 -800 5364 480 m2
port "wbs_cyc_i" 607 4070 -800 4182 480 m2
port "wbs_ack_o" 574 2888 -800 3000 480 m2
port "wb_rst_i" 573 1706 -800 1818 480 m2
port "wb_clk_i" 572 524 -800 636 480 m2
port "la_data_out[1]" 331 130544 -800 130656 480 m2
port "la_data_out[2]" 342 134090 -800 134202 480 m2
port "la_data_out[3]" 353 137636 -800 137748 480 m2
port "la_data_out[4]" 364 141182 -800 141294 480 m2
port "la_data_out[5]" 375 144728 -800 144840 480 m2
port "la_data_out[6]" 386 148274 -800 148386 480 m2
port "la_data_out[7]" 397 151820 -800 151932 480 m2
port "la_data_out[8]" 408 155366 -800 155478 480 m2
port "la_data_in[120]" 187 551336 -800 551448 480 m2
port "la_data_in[122]" 189 558428 -800 558540 480 m2
port "la_data_in[124]" 191 565520 -800 565632 480 m2
port "la_data_in[126]" 193 572612 -800 572724 480 m2
port "io_analog[10]" 37 0 680242 1700 685242 m3
port "io_analog[6]" 49 165594 702300 170594 704800 m4
port "vccd1" 553 582340 629784 584800 634584 m3
port "vccd1" 552 582340 639784 584800 644584 m3
port "vssa2" 567 0 549442 1660 554242 m3
port "vssa2" 566 0 559442 1660 564242 m3
port "vccd2" 555 0 633842 1660 638642 m3
port "vccd2" 554 0 643842 1660 648642 m3
node "io_analog[4]" 0 2435.52 329294 702300 m5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0
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node "wbs_sel_i[2]" 1 455.301 20618 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_dat_o[2]" 1 455.301 19436 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_dat_i[2]" 1 455.301 18254 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_adr_i[2]" 1 455.301 17072 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_sel_i[1]" 1 455.301 15890 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_dat_o[1]" 1 455.301 14708 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_dat_i[1]" 1 455.301 13526 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_adr_i[1]" 1 455.301 12344 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_sel_i[0]" 1 455.301 11162 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_dat_o[0]" 1 455.301 9980 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_dat_i[0]" 1 455.301 8798 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_adr_i[0]" 1 455.301 7616 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_we_i" 1 455.301 6434 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_stb_i" 1 455.301 5252 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_cyc_i" 1 455.301 4070 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wbs_ack_o" 1 455.301 2888 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wb_rst_i" 1 455.301 1706 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wb_clk_i" 1 483.17 524 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "la_data_out[1]" 0 72022.3 130544 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9969568 178252 15616 500 12880224 409700 0 0 0 0
node "la_data_out[2]" 0 46731.7 134090 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10045280 179604 15616 500 12595224 403060 0 0 0 0
node "la_data_out[3]" 0 51444 137636 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10237472 183036 15616 500 12159104 397380 0 0 0 0
node "la_data_out[4]" 0 53966.5 141182 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10314304 184408 15616 500 12309664 398360 0 0 0 0
node "la_data_out[5]" 0 59539.2 144728 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10610656 189700 15616 500 12672824 405040 0 0 0 0
node "la_data_out[6]" 0 60995.6 148274 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10229408 182892 15616 500 12898264 408360 0 0 0 0
node "la_data_out[7]" 0 63423.1 151820 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10396960 185884 15616 500 13183504 410640 0 0 0 0
node "la_data_out[8]" 0 86544.8 155366 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11543040 221284 25500 640 11560176 385458 0 0 0 0
node "m2_55523_202892#" 1 328.021 55523 202892 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11584 508 13200 460 40056 1454 0 0 0 0
node "m2_54833_202912#" 1 205.7 54833 202912 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12784 548 9900 400 23136 890 0 0 0 0
node "m2_54170_202730#" 1 224.617 54170 202730 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17292 534 17418 536 19776 778 0 0 0 0
node "m2_53493_202942#" 1 210.588 53493 202942 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15184 628 12000 440 29616 1106 0 0 0 0
node "m2_54520_202790#" 2 137.546 54520 202790 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18470 1188 0 0 0 0 0 0 0 0
node "m2_55208_202785#" 1 61.8604 55208 202785 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13752 692 0 0 0 0 0 0 0 0
node "m2_53840_202790#" 3 77.9433 53840 202790 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32400 1700 0 0 0 0 0 0 0 0
node "m2_53160_202790#" 4 107.853 53160 202790 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34470 2178 0 0 0 0 0 0 0 0
node "la_data_in[120]" 18 218299 551336 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1405992 28316 41216 1140 204800 2560 223233384 1395358 0 0
node "la_data_in[122]" 16 263082 558428 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1134072 24152 57016 1320 204800 2560 230294528 1439952 0 0
node "la_data_in[124]" 20 279711 565520 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1015352 25092 36416 1080 204800 2560 237509568 1485046 0 0
node "la_data_in[126]" 25 290738 572612 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1125912 29612 44416 1180 204800 2560 243689088 1523668 0 0
node "m2_34420_199220#" 2 167592 34420 199220 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40770400 1014420 526200 9260 0 0 0 0 0 0
node "m2_33290_207480#" 0 135557 33290 207480 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38580000 964660 1536576 51338 0 0 0 0 0 0
node "io_analog[10]" 0 36628.6 0 680242 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 53231170 65142 20750000 21600 0 0 0 0 0 0
node "io_analog[6]" 0 101230 165594 702300 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6244920 9996 158693890 301340 25275000 25220 0 0 0 0
node "m1_49580_204344#" 24 151166 49580 204344 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 262920 8884 39701400 992860 59400 1360 1140768 38142 0 0 0 0
node "vccd1" 0 2.0063e+06 582340 639784 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1256388700 1069330 1239652700 993160 2892727300 1960740 0 0 0 0 0 0
node "vssa2" 0 813276 0 559442 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 75036427 208680 34002391 62844 332296207 305910 1870720968 1510314 0 0 0 0
node "vccd2" 1 232955 0 643842 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9203100 13140 9203100 13140 247956140 230800 12976664 27088 472105605 378896 0 0
substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
cap "io_in_3v3[14]" "gpio_noesd[7]" 67.2299
cap "vssa2" "vccd1" 6.18595
cap "la_data_out[11]" "la_data_in[11]" 46.7738
cap "la_oenb[46]" "la_data_out[46]" 46.7738
cap "la_data_in[124]" "la_data_in[126]" 587.278
cap "m2_53160_202790#" "m2_54170_202730#" 3.72999
cap "la_oenb[108]" "la_data_in[109]" 46.7738
cap "gpio_analog[4]" "gpio_noesd[4]" 67.2299
cap "wbs_sel_i[0]" "wbs_adr_i[1]" 46.7738
cap "la_oenb[46]" "la_data_in[47]" 46.7738
cap "la_data_in[122]" "la_data_in[126]" 12.9992
cap "la_data_out[82]" "la_oenb[82]" 46.7738
cap "m2_53493_202942#" "m2_54170_202730#" 28.1398
cap "la_data_in[126]" "la_oenb[125]" 46.7738
cap "gpio_analog[15]" "gpio_noesd[15]" 67.2299
cap "io_in_3v3[4]" "io_oeb[3]" 67.2299
cap "m2_54170_202730#" "m2_54833_202912#" 39.2811
cap "la_oenb[80]" "la_data_out[80]" 46.7738
cap "io_analog[6]" "io_analog[6]" 22388.4
cap "la_data_in[82]" "la_data_out[82]" 46.7738
cap "io_oeb[4]" "io_out[4]" 67.2299
cap "la_oenb[80]" "la_data_in[81]" 46.7738
cap "la_oenb[47]" "la_data_in[48]" 46.7738
cap "la_data_out[81]" "la_data_in[81]" 46.7738
cap "m2_53493_202942#" "m2_53160_202790#" 113.43
cap "la_data_out[11]" "la_oenb[11]" 46.7738
cap "la_oenb[45]" "la_data_out[45]" 46.7738
cap "la_data_out[47]" "la_data_in[47]" 46.7738
cap "la_oenb[81]" "la_data_out[81]" 46.7738
cap "la_data_out[8]" "la_data_out[7]" 37030.3
cap "m2_53160_202790#" "m2_54833_202912#" 1.04826
cap "la_oenb[105]" "la_data_out[105]" 46.7738
cap "la_data_in[82]" "la_oenb[81]" 46.7738
cap "la_data_out[6]" "la_data_out[7]" 38749.5
cap "la_oenb[104]" "la_data_out[104]" 46.7738
cap "io_analog[5]" "io_clamp_low[1]" 735.436
cap "m2_53493_202942#" "m2_54833_202912#" 8.08772
cap "la_oenb[108]" "la_data_out[108]" 46.7738
cap "m2_54520_202790#" "m2_54170_202730#" 15.5886
cap "wbs_cyc_i" "wbs_stb_i" 46.7738
cap "la_data_out[13]" "la_data_in[13]" 46.7738
cap "wb_clk_i" "wb_rst_i" 46.7738
cap "la_data_out[2]" "la_data_in[2]" 46.7738
cap "la_data_out[2]" "la_oenb[2]" 46.7738
cap "la_oenb[11]" "la_data_in[12]" 46.7738
cap "la_data_in[53]" "la_oenb[52]" 46.7738
cap "la_oenb[104]" "la_data_in[105]" 46.7738
cap "la_data_out[58]" "la_data_in[58]" 46.7738
cap "wbs_adr_i[0]" "wbs_dat_i[0]" 46.7738
cap "la_oenb[47]" "la_data_out[47]" 46.7738
cap "la_oenb[10]" "la_data_in[11]" 46.7738
cap "la_data_in[109]" "la_data_out[109]" 46.7738
cap "m1_49580_204344#" "gpio_analog[7]" 160.193
cap "la_data_out[6]" "la_data_out[5]" 40267.9
cap "la_data_out[66]" "la_oenb[66]" 46.7738
cap "m2_53493_202942#" "m2_54520_202790#" 2.14488
cap "la_data_in[65]" "la_data_out[65]" 46.7738
cap "io_analog[4]" "vccd2" 1212.09
cap "io_out[2]" "io_oeb[2]" 67.2299
cap "m2_54520_202790#" "m2_54833_202912#" 32.9276
cap "la_data_in[105]" "la_data_out[105]" 46.7738
cap "la_data_in[107]" "la_oenb[106]" 46.7738
cap "io_in_3v3[8]" "gpio_noesd[1]" 67.2299
cap "m1_49580_204344#" "io_analog[5]" 0.690053
cap "la_data_out[12]" "la_data_in[12]" 46.7738
cap "vccd2" "io_analog[6]" 12755
cap "la_data_in[124]" "io_analog[2]" 1.4621
cap "la_data_out[113]" "la_oenb[113]" 46.7738
cap "la_data_out[12]" "la_oenb[12]" 46.7738
cap "gpio_analog[11]" "gpio_noesd[11]" 67.2299
cap "io_analog[2]" "la_data_in[122]" 1.4621
cap "la_data_out[43]" "la_data_in[43]" 46.7738
cap "la_data_out[118]" "la_data_in[118]" 46.7738
cap "la_data_in[125]" "la_data_in[123]" 980.991
cap "io_analog[2]" "m2_54170_202730#" 0.161373
cap "m2_55208_202785#" "vccd1" 6.16121
cap "la_oenb[57]" "la_data_in[58]" 46.7738
cap "la_data_out[4]" "la_data_out[3]" 43187.7
cap "la_data_out[43]" "la_oenb[43]" 46.7738
cap "wbs_dat_i[2]" "wbs_dat_o[2]" 46.7738
cap "la_oenb[7]" "la_data_out[7]" 46.7738
cap "la_data_out[55]" "la_data_in[55]" 46.7738
cap "la_data_out[111]" "la_oenb[111]" 46.7738
cap "la_data_in[123]" "vccd1" 2112.75
cap "la_data_in[8]" "la_data_out[8]" 46.7738
cap "io_clamp_high[1]" "io_analog[5]" 468.333
cap "io_oeb[0]" "io_in_3v3[1]" 67.2299
cap "io_analog[2]" "m2_53160_202790#" 0.362355
cap "la_data_out[60]" "la_data_in[60]" 46.7738
cap "la_oenb[8]" "la_data_out[8]" 46.7738
cap "la_oenb[12]" "la_data_in[13]" 46.7738
cap "io_in_3v3[10]" "gpio_noesd[3]" 67.2299
cap "m2_53493_202942#" "io_analog[2]" 0.227745
cap "io_analog[2]" "la_data_in[126]" 1.4621
cap "io_in[26]" "io_in_3v3[26]" 67.2299
cap "io_analog[2]" "m2_54833_202912#" 0.147405
cap "la_oenb[43]" "la_data_in[44]" 46.7738
cap "la_data_in[108]" "la_data_out[108]" 46.7738
cap "la_data_in[107]" "la_data_out[107]" 46.7738
cap "la_data_in[7]" "la_data_out[7]" 46.7738
cap "la_data_in[5]" "la_data_out[5]" 46.7738
cap "la_data_out[45]" "la_data_in[45]" 46.7738
cap "la_data_out[5]" "la_oenb[5]" 46.7738
cap "la_data_out[2]" "la_data_out[3]" 23122.2
cap "io_analog[2]" "m2_54520_202790#" 0.165659
cap "la_data_out[107]" "la_oenb[107]" 46.7738
cap "la_data_out[122]" "la_oenb[122]" 46.7738
cap "la_data_in[111]" "la_data_out[111]" 46.7738
cap "la_data_out[6]" "la_data_in[6]" 46.7738
cap "la_data_out[6]" "la_oenb[6]" 46.7738
cap "la_data_in[9]" "la_oenb[8]" 46.7738
cap "la_data_in[43]" "la_oenb[42]" 46.7738
cap "la_data_in[9]" "la_data_out[9]" 46.7738
cap "io_analog[5]" "io_analog[5]" 22388.4
cap "la_data_out[9]" "la_oenb[9]" 46.7738
cap "la_oenb[10]" "la_data_out[10]" 46.7738
cap "la_data_out[44]" "la_data_in[44]" 46.7738
cap "la_data_in[108]" "la_oenb[107]" 46.7738
cap "la_data_out[117]" "la_oenb[117]" 46.7738
cap "la_data_in[8]" "la_oenb[7]" 46.7738
cap "la_oenb[9]" "la_data_in[10]" 46.7738
cap "vssa2" "vccd2" 88369.5
cap "la_data_out[44]" "la_oenb[44]" 46.7738
cap "vccd2" "io_analog[8]" 781.607
cap "la_data_out[10]" "la_data_in[10]" 46.7738
cap "io_out[5]" "io_oeb[5]" 67.2299
cap "la_data_in[45]" "la_oenb[44]" 46.7738
cap "wbs_sel_i[0]" "wbs_dat_o[0]" 46.7738
cap "la_data_in[115]" "la_data_out[115]" 46.7738
cap "io_in[24]" "io_in_3v3[24]" 67.2299
cap "io_analog[5]" "io_clamp_low[1]" 493.833
cap "la_data_in[5]" "la_oenb[4]" 46.7738
cap "io_analog[5]" "io_analog[5]" 26259.4
cap "io_out[14]" "io_in[14]" 67.2299
cap "la_data_in[127]" "la_oenb[126]" 46.7738
cap "io_in[16]" "io_out[16]" 67.2299
cap "m3_51655_199490#" "m2_34420_199220#" 286.62
cap "la_data_out[123]" "la_data_in[123]" 46.7738
cap "la_data_in[101]" "la_data_out[101]" 46.7738
cap "io_out[3]" "io_in[3]" 67.2299
cap "la_oenb[3]" "la_data_in[4]" 46.7738
cap "la_oenb[5]" "la_data_in[6]" 46.7738
cap "la_oenb[83]" "la_data_out[83]" 46.7738
cap "io_analog[7]" "vccd2" 10115.8
cap "la_data_out[59]" "la_oenb[59]" 46.7738
cap "io_out[15]" "io_oeb[15]" 67.2299
cap "io_out[6]" "io_in[6]" 67.2299
cap "la_data_in[84]" "la_oenb[83]" 46.7738
cap "io_analog[6]" "io_clamp_low[2]" 493.833
cap "la_data_in[7]" "la_oenb[6]" 46.7738
cap "la_data_out[40]" "la_oenb[40]" 46.7738
cap "io_out[7]" "io_in[7]" 67.2299
cap "la_data_out[100]" "la_oenb[100]" 46.7738
cap "io_in_3v3[24]" "gpio_noesd[17]" 67.2299
cap "gpio_analog[3]" "gpio_noesd[3]" 67.2299
cap "m1_49580_204344#" "vccd1" 0.88795
cap "la_oenb[40]" "la_data_in[41]" 46.7738
cap "io_in[23]" "io_in_3v3[23]" 67.2299
cap "la_oenb[0]" "la_data_out[0]" 46.7738
cap "la_data_out[120]" "la_data_in[120]" 46.7738
cap "la_data_in[120]" "la_data_in[121]" 86330.4
cap "la_data_out[62]" "la_oenb[62]" 46.7738
cap "la_data_in[41]" "la_data_out[41]" 46.7738
cap "la_data_in[111]" "la_oenb[110]" 46.7738
cap "la_data_in[127]" "la_data_in[120]" 0.481245
cap "la_data_out[84]" "la_data_in[84]" 46.7738
cap "io_analog[4]" "m2_33290_207480#" 2.08078
cap "la_oenb[0]" "la_data_in[1]" 46.7738
cap "io_analog[4]" "io_analog[4]" 26922
cap "la_oenb[42]" "la_data_out[42]" 46.7738
cap "la_data_in[120]" "la_oenb[119]" 46.7738
cap "io_out[1]" "io_oeb[1]" 67.2299
cap "la_data_out[0]" "la_data_in[0]" 46.7738
cap "io_in_3v3[7]" "io_in[7]" 67.2299
cap "la_oenb[41]" "la_data_out[41]" 46.7738
cap "io_out[10]" "io_in[10]" 67.2299
cap "la_data_in[121]" "m2_33290_207480#" 3.42049
cap "la_oenb[1]" "la_data_in[2]" 46.7738
cap "la_data_out[115]" "la_oenb[115]" 46.7738
cap "la_data_out[40]" "la_data_in[40]" 46.7738
cap "la_oenb[41]" "la_data_in[42]" 46.7738
cap "la_data_in[3]" "la_oenb[2]" 46.7738
cap "la_data_in[127]" "m2_33290_207480#" 3.28801
cap "io_in_3v3[6]" "io_in[6]" 67.2299
cap "la_data_in[83]" "la_data_out[83]" 46.7738
cap "la_oenb[114]" "la_data_out[114]" 46.7738
cap "gpio_analog[17]" "gpio_noesd[17]" 67.2299
cap "wbs_adr_i[30]" "wbs_dat_o[29]" 46.7738
cap "la_oenb[63]" "la_data_in[64]" 46.7738
cap "wbs_dat_i[30]" "wbs_adr_i[30]" 46.7738
cap "la_data_in[42]" "la_data_out[42]" 46.7738
cap "gpio_analog[6]" "gpio_noesd[6]" 67.2299
cap "wbs_stb_i" "wbs_we_i" 46.7738
cap "wbs_dat_i[30]" "wbs_dat_o[30]" 46.7738
cap "io_analog[6]" "io_clamp_high[2]" 493.833
cap "vccd2" "m3_26500_684896#" 205.187
cap "wbs_dat_o[31]" "la_data_in[0]" 46.7738
cap "la_data_in[112]" "la_data_out[112]" 46.7738
cap "wbs_adr_i[31]" "wbs_dat_o[30]" 46.7738
cap "la_data_in[110]" "la_data_out[110]" 46.7738
cap "wbs_dat_i[31]" "wbs_adr_i[31]" 46.7738
cap "wbs_dat_i[29]" "wbs_dat_o[29]" 46.7738
cap "la_data_out[56]" "la_oenb[56]" 46.7738
cap "vssa2" "la_data_out[4]" 893.783
cap "wbs_dat_i[31]" "wbs_dat_o[31]" 46.7738
cap "vccd2" "gpio_analog[7]" 743.088
cap "la_data_in[125]" "vccd1" 2064.36
cap "la_oenb[51]" "la_data_in[52]" 46.7738
cap "la_oenb[110]" "la_data_out[110]" 46.7738
cap "vccd2" "io_analog[5]" 2114.88
cap "la_oenb[3]" "la_data_out[3]" 46.7738
cap "io_in[3]" "io_in_3v3[3]" 67.2299
cap "la_data_in[127]" "la_data_out[127]" 46.7738
cap "la_data_out[2]" "la_data_out[1]" 27417.9
cap "io_analog[4]" "io_clamp_high[0]" 468.333
cap "io_analog[4]" "io_clamp_high[0]" 493.833
cap "io_in[16]" "io_in_3v3[16]" 67.2299
cap "wbs_adr_i[27]" "wbs_dat_i[27]" 46.7738
cap "la_oenb[59]" "la_data_in[60]" 46.7738
cap "la_data_in[124]" "la_data_in[121]" 17.9665
cap "la_data_in[3]" "la_data_out[3]" 46.7738
cap "vssa2" "m2_33290_207480#" 4013.42
cap "wbs_dat_o[1]" "wbs_sel_i[1]" 46.7738
cap "la_data_in[124]" "la_data_in[127]" 50.9691
cap "la_data_in[122]" "la_data_in[121]" 49581.4
cap "wbs_dat_o[27]" "wbs_dat_i[27]" 46.7738
cap "wbs_adr_i[29]" "wbs_dat_i[29]" 46.7738
cap "la_data_out[2]" "vssa2" 870.097
cap "wbs_dat_o[26]" "wbs_adr_i[27]" 46.7738
cap "la_data_in[127]" "la_data_in[122]" 41.1623
cap "wbs_dat_o[27]" "wbs_adr_i[28]" 46.7738
cap "wbs_dat_i[28]" "wbs_adr_i[28]" 46.7738
cap "vssa2" "io_analog[10]" 2072.82
cap "wbs_dat_o[28]" "wbs_dat_i[28]" 46.7738
cap "io_analog[6]" "io_analog[6]" 26259.4
cap "la_data_in[121]" "la_data_in[126]" 9.37546
cap "wbs_dat_o[28]" "wbs_adr_i[29]" 46.7738
cap "la_data_out[86]" "la_data_in[86]" 46.7738
cap "la_data_out[98]" "la_oenb[98]" 46.7738
cap "la_data_in[127]" "la_data_in[126]" 27401.1
cap "la_data_out[59]" "la_data_in[59]" 46.7738
cap "la_oenb[124]" "la_data_in[125]" 46.7738
cap "wbs_dat_i[24]" "wbs_dat_o[24]" 46.7738
cap "io_out[25]" "io_in[25]" 67.2299
cap "la_data_in[40]" "la_oenb[39]" 46.7738
cap "m1_49580_204344#" "vccd2" 394.016
cap "wbs_dat_o[24]" "wbs_adr_i[25]" 46.7738
cap "io_in_3v3[15]" "io_in[15]" 67.2299
cap "la_oenb[37]" "la_data_in[38]" 46.7738
cap "io_in[4]" "io_in_3v3[4]" 67.2299
cap "wbs_adr_i[1]" "wbs_dat_i[1]" 46.7738
cap "io_analog[9]" "vssa2" 1623.5
cap "wbs_adr_i[25]" "wbs_dat_i[25]" 46.7738
cap "m2_55208_202785#" "m2_55523_202892#" 32.4727
cap "la_oenb[86]" "la_data_out[86]" 46.7738
cap "io_analog[9]" "io_analog[8]" 1693.25
cap "gpio_analog[0]" "gpio_noesd[0]" 67.2299
cap "io_in[8]" "io_in_3v3[8]" 67.2299
cap "gpio_noesd[11]" "io_in_3v3[18]" 67.2299
cap "la_data_in[120]" "la_data_in[123]" 6.54701
cap "wbs_dat_o[25]" "wbs_dat_i[25]" 46.7738
cap "wbs_dat_o[26]" "wbs_dat_i[26]" 46.7738
cap "la_oenb[84]" "la_data_in[85]" 46.7738
cap "m2_53840_202790#" "m2_55523_202892#" 2.37837
cap "la_data_in[38]" "la_data_out[38]" 46.7738
cap "io_in[5]" "io_out[5]" 67.2299
cap "io_in[5]" "io_in_3v3[5]" 67.2299
cap "wbs_adr_i[24]" "wbs_dat_i[24]" 46.7738
cap "la_data_in[101]" "la_oenb[100]" 46.7738
cap "io_out[12]" "io_in[12]" 67.2299
cap "m2_55208_202785#" "m2_33290_207480#" 0.757998
cap "la_oenb[37]" "la_data_out[37]" 46.7738
cap "la_data_out[125]" "la_oenb[125]" 46.7738
cap "io_oeb[6]" "io_out[6]" 67.2299
cap "la_oenb[38]" "la_data_out[38]" 46.7738
cap "io_out[23]" "io_oeb[23]" 67.2299
cap "io_analog[2]" "la_data_in[121]" 2.11832
cap "vssa2" "la_data_out[7]" 874.91
cap "m2_33290_207480#" "la_data_in[123]" 3.42049
cap "la_oenb[86]" "la_data_in[87]" 46.7738
cap "la_data_in[127]" "io_analog[2]" 74.5519
cap "io_in_3v3[12]" "io_in[12]" 67.2299
cap "m2_53840_202790#" "m2_33290_207480#" 1.95285
cap "la_oenb[38]" "la_data_in[39]" 46.7738
cap "la_oenb[85]" "la_data_in[86]" 46.7738
cap "io_analog[7]" "io_analog[9]" 1.41681
cap "wbs_dat_o[25]" "wbs_adr_i[26]" 46.7738
cap "m2_53160_202790#" "vssa2" 111.446
cap "la_data_in[57]" "la_oenb[56]" 46.7738
cap "vssa2" "m2_34420_199220#" 4724.99
cap "io_analog[6]" "io_analog[6]" 26792.4
cap "m2_53493_202942#" "vssa2" 113.123
cap "la_data_out[87]" "la_data_in[87]" 46.7738
cap "la_data_out[87]" "la_oenb[87]" 46.7738
cap "la_data_out[39]" "la_data_in[39]" 46.7738
cap "io_in[24]" "io_out[24]" 67.2299
cap "la_data_out[39]" "la_oenb[39]" 46.7738
cap "la_data_in[112]" "la_oenb[111]" 46.7738
cap "vssa2" "la_data_out[5]" 894.594
cap "wbs_dat_i[26]" "wbs_adr_i[26]" 46.7738
cap "la_oenb[109]" "la_data_out[109]" 46.7738
cap "vssa2" "la_data_out[8]" 1498.48
cap "io_out[21]" "io_oeb[21]" 67.2299
cap "la_oenb[124]" "la_data_out[124]" 46.7738
cap "la_data_out[6]" "vssa2" 886.965
cap "io_in_3v3[26]" "io_oeb[25]" 67.2299
cap "io_in_3v3[19]" "gpio_noesd[12]" 67.2299
cap "io_analog[6]" "io_clamp_high[2]" 735.436
cap "wbs_adr_i[22]" "wbs_dat_o[21]" 46.7738
cap "la_oenb[57]" "la_data_out[57]" 46.7738
cap "wbs_adr_i[22]" "wbs_dat_i[22]" 46.7738
cap "wbs_adr_i[24]" "wbs_dat_o[23]" 46.7738
cap "io_oeb[0]" "io_out[0]" 67.2299
cap "la_oenb[85]" "la_data_out[85]" 46.7738
cap "gpio_analog[13]" "gpio_noesd[13]" 67.2299
cap "gpio_analog[7]" "m2_33290_207480#" 153.875
cap "wbs_dat_o[22]" "wbs_dat_i[22]" 46.7738
cap "la_data_out[63]" "la_oenb[63]" 46.7738
cap "la_data_in[118]" "la_oenb[117]" 46.7738
cap "io_in_3v3[20]" "gpio_noesd[13]" 67.2299
cap "m3_26500_684896#" "io_analog[10]" 38.7515
cap "wbs_dat_o[22]" "wbs_adr_i[23]" 46.7738
cap "la_data_out[37]" "la_data_in[37]" 46.7738
cap "la_data_out[35]" "la_data_in[35]" 46.7738
cap "io_in_3v3[2]" "io_oeb[1]" 67.2299
cap "la_data_out[57]" "la_data_in[57]" 46.7738
cap "io_in_3v3[20]" "io_in[20]" 67.2299
cap "wbs_dat_i[21]" "wbs_dat_o[21]" 46.7738
cap "gpio_analog[10]" "gpio_noesd[10]" 67.2299
cap "gpio_noesd[2]" "io_in_3v3[9]" 67.2299
cap "m2_55208_202785#" "m2_54170_202730#" 2.66226
cap "wbs_adr_i[23]" "wbs_dat_i[23]" 46.7738
cap "la_data_out[35]" "la_oenb[35]" 46.7738
cap "la_data_in[124]" "la_data_in[123]" 30971.2
cap "io_analog[2]" "vssa2" 72.4962
cap "wbs_dat_o[23]" "wbs_dat_i[23]" 46.7738
cap "la_data_in[36]" "la_oenb[35]" 46.7738
cap "la_data_in[122]" "la_data_in[123]" 32987.8
cap "la_data_in[36]" "la_data_out[36]" 46.7738
cap "la_data_out[36]" "la_oenb[36]" 46.7738
cap "la_data_out[0]" "la_data_out[1]" 5.79259
cap "la_oenb[36]" "la_data_in[37]" 46.7738
cap "la_data_out[54]" "la_data_in[54]" 46.7738
cap "la_oenb[116]" "la_data_in[117]" 46.7738
cap "la_data_in[122]" "la_oenb[121]" 46.7738
cap "gpio_analog[5]" "gpio_noesd[5]" 67.2299
cap "m2_53840_202790#" "m2_54170_202730#" 83.6871
cap "io_out[7]" "io_oeb[7]" 67.2299
cap "m2_55208_202785#" "m2_53493_202942#" 0.24742
cap "la_oenb[0]" "la_data_out[1]" 5.79259
cap "la_oenb[87]" "la_data_in[88]" 46.7738
cap "la_data_out[117]" "la_data_in[117]" 46.7738
cap "la_oenb[34]" "la_data_in[35]" 46.7738
cap "m2_55208_202785#" "m2_54833_202912#" 26.4727
cap "la_data_out[56]" "la_data_in[56]" 46.7738
cap "la_data_in[1]" "la_data_out[1]" 52.5664
cap "la_oenb[1]" "la_data_out[1]" 46.7738
cap "io_analog[4]" "io_analog[3]" 14425.7
cap "m2_53160_202790#" "m2_53840_202790#" 82.4543
cap "io_analog[5]" "io_analog[5]" 26792.4
cap "la_data_in[123]" "la_data_in[126]" 27.9166
cap "m2_53493_202942#" "m2_53840_202790#" 41.1462
cap "la_data_in[0]" "la_data_out[1]" 5.79259
cap "la_data_out[1]" "wbs_dat_o[29]" 5.79259
cap "wbs_adr_i[30]" "la_data_out[1]" 5.79259
cap "io_in_3v3[15]" "gpio_noesd[8]" 67.2299
cap "m2_53840_202790#" "m2_54833_202912#" 8.15576
cap "wbs_dat_i[30]" "la_data_out[1]" 5.79259
cap "la_oenb[88]" "la_data_in[89]" 46.7738
cap "user_irq[2]" "user_irq[1]" 46.7738
cap "io_analog[4]" "io_clamp_low[0]" 468.333
cap "io_in_3v3[14]" "io_in[14]" 67.2299
cap "m2_55208_202785#" "m2_54520_202790#" 8.16064
cap "la_data_out[1]" "wbs_dat_o[30]" 5.79259
cap "wbs_adr_i[31]" "la_data_out[1]" 5.79259
cap "wbs_adr_i[19]" "wbs_dat_i[19]" 46.7738
cap "la_oenb[109]" "la_data_in[110]" 46.7738
cap "io_analog[4]" "io_clamp_high[0]" 735.436
cap "wbs_dat_i[31]" "la_data_out[1]" 5.79259
cap "wbs_dat_o[31]" "la_data_out[1]" 5.79259
cap "la_data_in[99]" "la_oenb[98]" 46.7738
cap "wbs_adr_i[21]" "wbs_dat_i[21]" 46.7738
cap "wbs_dat_o[19]" "wbs_dat_i[19]" 46.7738
cap "wbs_adr_i[20]" "wbs_dat_o[19]" 46.7738
cap "wbs_dat_i[29]" "la_data_out[1]" 5.79259
cap "m2_54520_202790#" "m2_53840_202790#" 21.0574
cap "m1_49580_204344#" "m2_33290_207480#" 30589.7
cap "wbs_adr_i[27]" "la_data_out[1]" 5.79259
cap "la_data_out[89]" "la_data_in[89]" 46.7738
cap "wbs_dat_o[18]" "wbs_adr_i[19]" 46.7738
cap "la_oenb[88]" "la_data_out[88]" 46.7738
cap "wbs_dat_i[20]" "wbs_adr_i[20]" 46.7738
cap "la_oenb[32]" "la_data_out[32]" 46.7738
cap "io_clamp_low[1]" "io_analog[5]" 468.333
cap "io_out[17]" "io_oeb[17]" 67.2299
cap "la_data_out[89]" "la_oenb[89]" 46.7738
cap "io_clamp_high[2]" "io_clamp_low[2]" 468.333
cap "wbs_dat_i[27]" "la_data_out[1]" 5.79259
cap "wbs_dat_o[27]" "la_data_out[1]" 5.79259
cap "la_data_in[90]" "la_oenb[89]" 46.7738
cap "wbs_dat_i[20]" "wbs_dat_o[20]" 46.7738
cap "la_data_in[33]" "la_oenb[32]" 46.7738
cap "la_data_in[90]" "la_data_out[90]" 46.7738
cap "wbs_adr_i[28]" "la_data_out[1]" 5.79259
cap "wbs_ack_o" "wb_rst_i" 46.7738
cap "la_data_in[33]" "la_data_out[33]" 46.7738
cap "la_oenb[34]" "la_data_out[34]" 46.7738
cap "la_data_out[98]" "la_data_in[98]" 46.7738
cap "wbs_dat_i[28]" "la_data_out[1]" 5.79259
cap "wbs_dat_o[28]" "la_data_out[1]" 5.79259
cap "wbs_dat_o[20]" "wbs_adr_i[21]" 46.7738
cap "wbs_dat_o[26]" "la_data_out[1]" 5.79259
cap "wbs_adr_i[29]" "la_data_out[1]" 5.79259
cap "m2_55208_202785#" "io_analog[2]" 0.0603769
cap "la_data_in[32]" "la_data_out[32]" 46.7738
cap "wbs_dat_i[24]" "la_data_out[1]" 5.79259
cap "la_oenb[33]" "la_data_out[33]" 46.7738
cap "wbs_dat_o[24]" "la_data_out[1]" 5.79259
cap "io_in_3v3[10]" "io_in[10]" 67.2299
cap "io_in_3v3[13]" "io_in[13]" 67.2299
cap "io_analog[5]" "io_clamp_high[1]" 493.833
cap "gpio_analog[7]" "m2_34420_199220#" 4360.58
cap "m3_51655_199490#" "vssa2" 160.694
cap "wbs_adr_i[25]" "la_data_out[1]" 5.79259
cap "la_oenb[33]" "la_data_in[34]" 46.7738
cap "io_analog[2]" "la_data_in[123]" 2.11832
cap "io_in_3v3[13]" "gpio_noesd[6]" 67.2299
cap "wbs_dat_i[25]" "la_data_out[1]" 5.79259
cap "la_data_in[114]" "la_oenb[113]" 46.7738
cap "la_data_in[88]" "la_data_out[88]" 46.7738
cap "io_analog[2]" "m2_53840_202790#" 0.0675945
cap "wbs_dat_o[2]" "wbs_sel_i[2]" 46.7738
cap "la_data_out[1]" "la_data_out[3]" 0.370339
cap "la_data_out[34]" "la_data_in[34]" 46.7738
cap "la_data_out[91]" "la_oenb[91]" 46.7738
cap "wbs_dat_o[25]" "la_data_out[1]" 5.79259
cap "la_oenb[90]" "la_data_out[90]" 46.7738
cap "la_oenb[91]" "la_data_in[92]" 46.7738
cap "la_oenb[29]" "la_data_in[30]" 46.7738
cap "io_analog[4]" "io_analog[4]" 26259.4
cap "io_clamp_low[2]" "io_analog[6]" 468.333
cap "vssa2" "io_analog[3]" 6607.54
cap "wbs_dat_i[18]" "wbs_dat_o[18]" 46.7738
cap "la_data_out[30]" "la_data_in[30]" 46.7738
cap "la_data_out[51]" "la_data_in[51]" 46.7738
cap "io_analog[4]" "io_analog[4]" 21353.1
cap "la_data_in[120]" "la_data_in[125]" 1.94287
cap "la_data_out[1]" "wbs_adr_i[26]" 5.79259
cap "wbs_dat_i[26]" "la_data_out[1]" 5.79259
cap "wbs_adr_i[24]" "la_data_out[1]" 5.79259
cap "wbs_dat_i[16]" "wbs_dat_o[16]" 46.7738
cap "la_data_in[100]" "la_oenb[99]" 46.7738
cap "vssa2" "la_data_out[3]" 883.584
cap "wbs_adr_i[17]" "wbs_dat_o[16]" 46.7738
cap "la_data_out[30]" "la_oenb[30]" 46.7738
cap "la_data_in[32]" "la_oenb[31]" 46.7738
cap "la_data_out[92]" "la_data_in[92]" 46.7738
cap "gpio_noesd[14]" "io_in_3v3[21]" 67.2299
cap "wbs_adr_i[17]" "wbs_dat_i[17]" 46.7738
cap "la_oenb[30]" "la_data_in[31]" 46.7738
cap "la_data_out[91]" "la_data_in[91]" 46.7738
cap "m2_55523_202892#" "vccd1" 42.2459
cap "io_in[0]" "io_in_3v3[0]" 67.2299
cap "la_data_in[31]" "la_data_out[31]" 46.7738
cap "la_data_out[116]" "la_oenb[116]" 46.7738
cap "la_data_in[120]" "vccd1" 75630.8
cap "wbs_dat_o[21]" "la_data_out[1]" 5.79259
cap "la_data_out[92]" "la_oenb[92]" 46.7738
cap "gpio_analog[1]" "gpio_noesd[1]" 67.2299
cap "wbs_adr_i[22]" "la_data_out[1]" 5.79259
cap "la_oenb[29]" "la_data_out[29]" 46.7738
cap "la_data_in[61]" "la_oenb[60]" 46.7738
cap "io_in_3v3[17]" "gpio_noesd[10]" 67.2299
cap "wbs_dat_i[16]" "wbs_adr_i[16]" 46.7738
cap "la_data_out[126]" "la_oenb[126]" 46.7738
cap "io_oeb[24]" "io_in_3v3[25]" 67.2299
cap "wbs_dat_o[17]" "wbs_dat_i[17]" 46.7738
cap "la_data_in[93]" "la_oenb[92]" 46.7738
cap "wbs_dat_i[22]" "la_data_out[1]" 5.79259
cap "m2_33290_207480#" "la_data_in[125]" 3.42049
cap "wbs_dat_o[22]" "la_data_out[1]" 5.79259
cap "la_data_out[31]" "la_oenb[31]" 46.7738
cap "io_in[17]" "io_in_3v3[17]" 67.2299
cap "wbs_dat_o[17]" "wbs_adr_i[18]" 46.7738
cap "wbs_adr_i[23]" "la_data_out[1]" 5.79259
cap "io_analog[6]" "io_analog[6]" 21353.1
cap "la_data_out[1]" "wbs_dat_i[23]" 5.79259
cap "wbs_dat_i[18]" "wbs_adr_i[18]" 46.7738
cap "la_oenb[90]" "la_data_in[91]" 46.7738
cap "io_in[0]" "io_out[0]" 67.2299
cap "la_oenb[65]" "la_data_out[65]" 46.7738
cap "io_in[23]" "io_out[23]" 67.2299
cap "wbs_dat_o[23]" "la_data_out[1]" 5.79259
cap "m2_33290_207480#" "vccd1" 87.7272
cap "m2_53160_202790#" "m1_49580_204344#" 1.11147
cap "wbs_dat_o[0]" "wbs_dat_i[0]" 46.7738
cap "wbs_dat_i[21]" "la_data_out[1]" 5.79259
cap "la_data_in[61]" "la_data_out[61]" 46.7738
cap "m1_49580_204344#" "m2_34420_199220#" 52.3618
cap "m2_53493_202942#" "m1_49580_204344#" 1.85563
cap "la_data_in[27]" "la_data_out[27]" 46.7738
cap "wbs_adr_i[19]" "la_data_out[1]" 5.79259
cap "la_oenb[27]" "la_data_out[27]" 46.7738
cap "io_analog[5]" "io_analog[5]" 21353.1
cap "wbs_dat_o[13]" "wbs_adr_i[14]" 46.7738
cap "wbs_dat_i[19]" "la_data_out[1]" 5.79259
cap "wbs_dat_o[19]" "la_data_out[1]" 5.79259
cap "la_oenb[27]" "la_data_in[28]" 46.7738
cap "la_data_out[51]" "la_oenb[51]" 46.7738
cap "wbs_adr_i[20]" "la_data_out[1]" 5.79259
cap "la_data_out[94]" "la_data_in[94]" 46.7738
cap "la_data_out[28]" "la_data_in[28]" 46.7738
cap "wbs_dat_i[20]" "la_data_out[1]" 5.79259
cap "wbs_dat_o[20]" "la_data_out[1]" 5.79259
cap "la_data_out[28]" "la_oenb[28]" 46.7738
cap "la_data_in[29]" "la_data_out[29]" 46.7738
cap "la_data_in[127]" "la_data_in[121]" 7.83251
cap "wbs_adr_i[21]" "la_data_out[1]" 5.79259
cap "la_data_out[93]" "la_data_in[93]" 46.7738
cap "io_in[22]" "io_out[22]" 67.2299
cap "wbs_dat_o[18]" "la_data_out[1]" 5.79259
cap "wbs_dat_i[14]" "wbs_adr_i[14]" 46.7738
cap "la_data_out[94]" "la_oenb[94]" 46.7738
cap "la_data_in[29]" "la_oenb[28]" 46.7738
cap "wbs_adr_i[16]" "wbs_dat_o[15]" 46.7738
cap "la_data_in[27]" "la_oenb[26]" 46.7738
cap "la_data_out[120]" "la_oenb[120]" 46.7738
cap "la_data_out[52]" "la_oenb[52]" 46.7738
cap "la_data_out[119]" "la_oenb[119]" 46.7738
cap "la_oenb[120]" "la_data_in[121]" 46.7738
cap "wbs_dat_o[14]" "wbs_dat_i[14]" 46.7738
cap "la_data_out[121]" "la_data_in[121]" 46.7738
cap "la_data_out[52]" "la_data_in[52]" 46.7738
cap "la_data_in[54]" "la_oenb[53]" 46.7738
cap "wbs_dat_o[13]" "wbs_dat_i[13]" 46.7738
cap "la_data_out[119]" "la_data_in[119]" 46.7738
cap "io_oeb[24]" "io_out[24]" 67.2299
cap "wbs_dat_i[16]" "la_data_out[1]" 5.79259
cap "wbs_dat_o[16]" "la_data_out[1]" 5.79259
cap "wbs_adr_i[17]" "la_data_out[1]" 5.79259
cap "la_data_in[119]" "la_oenb[118]" 46.7738
cap "wbs_dat_i[17]" "la_data_out[1]" 5.79259
cap "la_data_in[95]" "la_oenb[94]" 46.7738
cap "la_data_in[124]" "la_data_in[125]" 40363.9
cap "la_oenb[58]" "la_data_in[59]" 46.7738
cap "la_data_out[95]" "la_data_in[95]" 46.7738
cap "wbs_dat_o[17]" "la_data_out[1]" 5.79259
cap "wbs_adr_i[18]" "la_data_out[1]" 5.79259
cap "wbs_dat_o[14]" "wbs_adr_i[15]" 46.7738
cap "la_data_in[122]" "la_data_in[125]" 34.4614
cap "wbs_adr_i[16]" "la_data_out[1]" 5.79259
cap "wbs_dat_i[18]" "la_data_out[1]" 5.79259
cap "la_data_out[95]" "la_oenb[95]" 46.7738
cap "io_analog[2]" "m1_49580_204344#" 22.2661
cap "wbs_dat_o[13]" "la_data_out[1]" 5.79259
cap "la_data_out[53]" "la_data_in[53]" 46.7738
cap "la_data_in[124]" "vccd1" 2122.7
cap "wbs_dat_i[15]" "wbs_adr_i[15]" 46.7738
cap "la_data_out[116]" "la_data_in[116]" 46.7738
cap "la_data_in[122]" "vccd1" 2490.74
cap "la_oenb[24]" "la_data_out[24]" 46.7738
cap "m2_54170_202730#" "vccd1" 0.00723639
cap "la_oenb[24]" "la_data_in[25]" 46.7738
cap "wbs_dat_i[15]" "wbs_dat_o[15]" 46.7738
cap "wbs_adr_i[14]" "la_data_out[1]" 5.79259
cap "la_data_in[125]" "la_data_in[126]" 41930.2
cap "la_data_in[25]" "la_data_out[25]" 46.7738
cap "io_clamp_low[0]" "io_clamp_high[0]" 468.333
cap "wbs_dat_i[14]" "la_data_out[1]" 5.79259
cap "la_oenb[26]" "la_data_out[26]" 46.7738
cap "la_data_in[24]" "la_data_out[24]" 46.7738
cap "la_oenb[96]" "la_data_in[97]" 46.7738
cap "io_analog[4]" "vssa2" 12792.7
cap "wbs_dat_o[14]" "la_data_out[1]" 5.79259
cap "la_oenb[25]" "la_data_out[25]" 46.7738
cap "io_analog[5]" "io_clamp_high[1]" 735.436
cap "m2_53493_202942#" "vccd1" 0.0162526
cap "la_data_in[83]" "la_oenb[82]" 46.7738
cap "la_data_out[99]" "la_oenb[99]" 46.7738
cap "la_data_in[122]" "la_data_out[122]" 46.7738
cap "vssa2" "io_analog[6]" 10672.1
cap "la_data_in[126]" "vccd1" 2146.23
cap "la_data_in[26]" "la_oenb[25]" 46.7738
cap "la_data_in[26]" "la_data_out[26]" 46.7738
cap "m2_54833_202912#" "vccd1" 1.79184
cap "wbs_adr_i[15]" "la_data_out[1]" 5.79259
cap "la_data_in[65]" "la_oenb[64]" 46.7738
cap "la_data_in[96]" "la_oenb[95]" 46.7738
cap "wbs_ack_o" "wbs_cyc_i" 46.7738
cap "wbs_adr_i[11]" "wbs_dat_i[11]" 46.7738
cap "wbs_dat_i[15]" "la_data_out[1]" 5.79259
cap "gpio_analog[7]" "io_analog[3]" 84.3
cap "io_out[3]" "io_oeb[3]" 67.2299
cap "wbs_dat_o[11]" "wbs_dat_i[11]" 46.7738
cap "wbs_dat_o[15]" "la_data_out[1]" 5.79259
cap "la_data_in[22]" "la_oenb[21]" 46.7738
cap "wbs_dat_i[13]" "la_data_out[1]" 5.79259
cap "wbs_adr_i[11]" "la_data_out[1]" 5.79259
cap "la_data_out[64]" "la_oenb[64]" 46.7738
cap "m2_54520_202790#" "vccd1" 0.152921
cap "la_data_out[1]" "wbs_dat_i[11]" 5.79259
cap "wbs_dat_o[11]" "wbs_adr_i[12]" 46.7738
cap "wbs_dat_o[11]" "la_data_out[1]" 5.79259
cap "wbs_dat_i[13]" "wbs_adr_i[13]" 46.7738
cap "io_in_3v3[22]" "io_in[22]" 67.2299
cap "la_data_in[22]" "la_data_out[22]" 46.7738
cap "io_in[2]" "io_in_3v3[2]" 67.2299
cap "la_data_in[114]" "la_data_out[114]" 46.7738
cap "wbs_adr_i[12]" "la_data_out[1]" 5.79259
cap "io_in[18]" "io_in_3v3[18]" 67.2299
cap "la_data_in[24]" "la_oenb[23]" 46.7738
cap "io_analog[7]" "io_analog[6]" 2427.12
cap "wbs_adr_i[11]" "wbs_dat_o[10]" 46.7738
cap "wbs_dat_i[12]" "wbs_adr_i[12]" 46.7738
cap "io_out[18]" "io_in[18]" 67.2299
cap "wbs_dat_o[12]" "la_data_out[1]" 5.79259
cap "la_oenb[22]" "la_data_out[22]" 46.7738
cap "la_data_in[67]" "la_oenb[66]" 46.7738
cap "vccd2" "m2_33290_207480#" 366.573
cap "wbs_dat_i[12]" "la_data_out[1]" 5.79259
cap "la_data_in[124]" "la_data_out[124]" 46.7738
cap "wbs_adr_i[13]" "la_data_out[1]" 5.79259
cap "la_data_in[63]" "la_oenb[62]" 46.7738
cap "la_oenb[21]" "la_data_out[21]" 46.7738
cap "io_analog[2]" "la_data_in[125]" 2.11832
cap "la_oenb[22]" "la_data_in[23]" 46.7738
cap "la_data_in[64]" "la_data_out[64]" 46.7738
cap "io_in_3v3[9]" "io_in[9]" 67.2299
cap "wbs_dat_o[12]" "wbs_dat_i[12]" 46.7738
cap "io_in_3v3[7]" "gpio_noesd[0]" 67.2299
cap "wbs_dat_o[12]" "wbs_adr_i[13]" 46.7738
cap "io_in[8]" "io_out[8]" 67.2299
cap "wbs_dat_o[10]" "la_data_out[1]" 5.79259
cap "la_data_out[126]" "la_data_in[126]" 46.7738
cap "io_analog[2]" "vccd1" 2251.66
cap "vssa2" "la_data_out[1]" 1495.21
cap "io_oeb[26]" "io_out[26]" 67.2299
cap "la_data_in[23]" "la_data_out[23]" 46.7738
cap "io_oeb[22]" "io_out[22]" 67.2299
cap "gpio_noesd[9]" "io_in_3v3[16]" 67.2299
cap "vccd2" "io_analog[10]" 13360.7
cap "la_data_in[85]" "la_data_out[85]" 46.7738
cap "la_data_out[69]" "la_data_in[69]" 46.7738
cap "wbs_adr_i[9]" "la_data_out[1]" 5.79259
cap "wbs_dat_i[9]" "la_data_out[1]" 5.79259
cap "la_data_out[123]" "la_oenb[123]" 46.7738
cap "wbs_dat_o[9]" "la_data_out[1]" 5.79259
cap "la_data_in[66]" "la_data_out[66]" 46.7738
cap "io_in_3v3[12]" "gpio_noesd[5]" 67.2299
cap "la_oenb[23]" "la_data_out[23]" 46.7738
cap "wbs_adr_i[10]" "la_data_out[1]" 5.79259
cap "la_oenb[61]" "la_data_out[61]" 46.7738
cap "gpio_noesd[12]" "gpio_analog[12]" 67.2299
cap "gpio_noesd[8]" "gpio_analog[8]" 67.2299
cap "wbs_dat_i[10]" "la_data_out[1]" 5.79259
cap "io_in[26]" "io_out[26]" 67.2299
cap "user_irq[0]" "user_irq[1]" 46.7738
cap "io_out[25]" "io_oeb[25]" 67.2299
cap "io_out[10]" "io_oeb[10]" 67.2299
cap "wbs_adr_i[3]" "wbs_sel_i[2]" 46.7738
cap "vssa2" "io_analog[8]" 1645.69
cap "la_data_in[67]" "la_data_out[67]" 46.7738
cap "io_clamp_low[2]" "io_analog[6]" 735.436
cap "la_data_in[116]" "la_oenb[115]" 46.7738
cap "la_data_in[121]" "la_data_in[123]" 372.972
cap "la_data_in[96]" "la_data_out[96]" 46.7738
cap "wbs_dat_i[8]" "wbs_dat_o[8]" 46.7738
cap "la_oenb[93]" "la_data_in[94]" 46.7738
cap "io_analog[9]" "vccd2" 1461.73
cap "la_oenb[114]" "la_data_in[115]" 46.7738
cap "la_data_in[127]" "la_data_in[123]" 16.4928
cap "io_in_3v3[19]" "io_in[19]" 67.2299
cap "wbs_dat_o[8]" "wbs_adr_i[9]" 46.7738
cap "la_oenb[68]" "la_data_in[69]" 46.7738
cap "wbs_dat_o[10]" "wbs_dat_i[10]" 46.7738
cap "io_out[2]" "io_in[2]" 67.2299
cap "io_analog[4]" "io_analog[4]" 22465.6
cap "wbs_dat_i[9]" "wbs_adr_i[9]" 46.7738
cap "la_oenb[67]" "la_data_out[67]" 46.7738
cap "la_data_out[19]" "la_data_in[19]" 46.7738
cap "la_data_out[19]" "la_oenb[19]" 46.7738
cap "io_out[15]" "io_in[15]" 67.2299
cap "io_in[19]" "io_out[19]" 67.2299
cap "wbs_dat_i[8]" "wbs_adr_i[8]" 46.7738
cap "io_in_3v3[3]" "io_oeb[2]" 67.2299
cap "wbs_dat_i[9]" "wbs_dat_o[9]" 46.7738
cap "io_oeb[19]" "io_out[19]" 67.2299
cap "la_oenb[19]" "la_data_in[20]" 46.7738
cap "wbs_adr_i[10]" "wbs_dat_o[9]" 46.7738
cap "la_oenb[67]" "la_data_in[68]" 46.7738
cap "la_data_out[21]" "la_data_in[21]" 46.7738
cap "io_oeb[8]" "io_out[8]" 67.2299
cap "la_data_out[121]" "la_oenb[121]" 46.7738
cap "wbs_adr_i[10]" "wbs_dat_i[10]" 46.7738
cap "io_oeb[9]" "io_out[9]" 67.2299
cap "io_analog[7]" "vssa2" 6815.3
cap "la_data_in[20]" "la_data_out[20]" 46.7738
cap "la_data_out[69]" "la_oenb[69]" 46.7738
cap "la_data_out[68]" "la_data_in[68]" 46.7738
cap "gpio_analog[7]" "gpio_noesd[7]" 67.2299
cap "la_data_out[93]" "la_oenb[93]" 46.7738
cap "io_analog[7]" "io_analog[8]" 3486.67
cap "la_oenb[20]" "la_data_out[20]" 46.7738
cap "io_in[20]" "io_out[20]" 67.2299
cap "wbs_adr_i[6]" "wbs_dat_o[5]" 46.7738
cap "io_out[9]" "io_in[9]" 67.2299
cap "la_oenb[68]" "la_data_out[68]" 46.7738
cap "io_out[21]" "io_in[21]" 67.2299
cap "wbs_adr_i[6]" "wbs_dat_i[6]" 46.7738
cap "la_oenb[20]" "la_data_in[21]" 46.7738
cap "vccd2" "m2_34420_199220#" 425.076
cap "la_oenb[18]" "la_data_in[19]" 46.7738
cap "io_in[17]" "io_out[17]" 67.2299
cap "wbs_dat_o[6]" "wbs_dat_i[6]" 46.7738
cap "io_analog[4]" "io_analog[5]" 15915.8
cap "gpio_noesd[2]" "gpio_analog[2]" 67.2299
cap "la_oenb[54]" "la_data_in[55]" 46.7738
cap "wbs_dat_o[6]" "wbs_adr_i[7]" 46.7738
cap "wbs_dat_i[2]" "wbs_adr_i[2]" 46.7738
cap "wbs_adr_i[8]" "wbs_dat_o[7]" 46.7738
cap "la_data_in[113]" "la_data_out[113]" 46.7738
cap "la_oenb[71]" "la_data_in[72]" 46.7738
cap "io_analog[5]" "io_analog[6]" 5298.76
cap "io_out[20]" "io_oeb[20]" 67.2299
cap "wbs_dat_o[5]" "wbs_dat_i[5]" 46.7738
cap "la_data_in[113]" "la_oenb[112]" 46.7738
cap "wbs_dat_i[7]" "wbs_adr_i[7]" 46.7738
cap "la_data_out[60]" "la_oenb[60]" 46.7738
cap "io_in[11]" "io_out[11]" 67.2299
cap "la_oenb[112]" "la_data_out[112]" 46.7738
cap "vssa2" "m2_53840_202790#" 0.938238
cap "wbs_dat_o[7]" "wbs_dat_i[7]" 46.7738
cap "la_oenb[97]" "la_data_in[98]" 46.7738
cap "la_oenb[55]" "la_data_in[56]" 46.7738
cap "la_data_in[70]" "la_oenb[69]" 46.7738
cap "wbs_dat_o[1]" "wbs_dat_i[1]" 46.7738
cap "io_out[18]" "io_oeb[18]" 67.2299
cap "la_data_out[71]" "la_oenb[71]" 46.7738
cap "user_clock2" "la_oenb[127]" 46.7738
cap "io_oeb[16]" "io_out[16]" 67.2299
cap "io_clamp_low[1]" "io_clamp_high[1]" 468.333
cap "io_analog[4]" "io_clamp_low[0]" 735.436
cap "io_in_3v3[1]" "io_in[1]" 67.2299
cap "wbs_dat_i[3]" "wbs_dat_o[3]" 46.7738
cap "wbs_sel_i[3]" "wbs_dat_o[3]" 46.7738
cap "la_data_in[63]" "la_data_out[63]" 46.7738
cap "la_data_in[66]" "la_oenb[65]" 46.7738
cap "la_data_in[70]" "la_data_out[70]" 46.7738
cap "wbs_sel_i[3]" "wbs_adr_i[4]" 46.7738
cap "la_data_out[72]" "la_data_in[72]" 46.7738
cap "m2_33290_207480#" "m2_55523_202892#" 6.94958
cap "la_data_in[120]" "m2_33290_207480#" 2.65181
cap "la_data_out[16]" "la_oenb[16]" 46.7738
cap "la_oenb[70]" "la_data_out[70]" 46.7738
cap "io_analog[2]" "vccd2" 10711.3
cap "io_out[14]" "io_oeb[14]" 67.2299
cap "wbs_dat_i[4]" "wbs_adr_i[4]" 46.7738
cap "la_data_in[62]" "la_data_out[62]" 46.7738
cap "vssa2" "m3_26500_684896#" 1183.07
cap "io_out[1]" "io_in[1]" 67.2299
cap "wbs_adr_i[5]" "wbs_dat_i[5]" 46.7738
cap "wbs_dat_i[4]" "wbs_dat_o[4]" 46.7738
cap "la_oenb[70]" "la_data_in[71]" 46.7738
cap "wbs_adr_i[3]" "wbs_dat_i[3]" 46.7738
cap "la_data_in[62]" "la_oenb[61]" 46.7738
cap "la_oenb[50]" "la_data_out[50]" 46.7738
cap "wbs_sel_i[1]" "wbs_adr_i[2]" 46.7738
cap "la_data_out[118]" "la_oenb[118]" 46.7738
cap "la_data_out[71]" "la_data_in[71]" 46.7738
cap "la_data_in[17]" "la_oenb[16]" 46.7738
cap "vssa2" "gpio_analog[7]" 39652.2
cap "wbs_adr_i[5]" "wbs_dat_o[4]" 46.7738
cap "la_data_out[54]" "la_oenb[54]" 46.7738
cap "la_oenb[74]" "la_data_out[74]" 46.7738
cap "vssa2" "io_analog[5]" 14585.2
cap "la_oenb[127]" "la_data_out[127]" 46.7738
cap "io_in_3v3[23]" "gpio_noesd[16]" 67.2299
cap "la_data_out[100]" "la_data_in[100]" 46.7738
cap "la_oenb[72]" "la_data_out[72]" 46.7738
cap "user_irq[0]" "user_clock2" 46.7738
cap "m2_55208_202785#" "m2_53840_202790#" 0.236247
cap "la_data_out[18]" "la_oenb[18]" 46.7738
cap "la_data_out[58]" "la_oenb[58]" 46.7738
cap "io_in[11]" "io_in_3v3[11]" 67.2299
cap "la_data_in[17]" "la_data_out[17]" 46.7738
cap "la_data_in[16]" "la_data_out[16]" 46.7738
cap "la_data_in[74]" "la_data_out[74]" 46.7738
cap "la_oenb[72]" "la_data_in[73]" 46.7738
cap "la_data_out[48]" "la_oenb[48]" 46.7738
cap "la_data_in[75]" "la_oenb[74]" 46.7738
cap "la_data_in[49]" "la_oenb[48]" 46.7738
cap "la_data_out[73]" "la_data_in[73]" 46.7738
cap "io_oeb[12]" "io_out[12]" 67.2299
cap "la_oenb[17]" "la_data_out[17]" 46.7738
cap "wbs_adr_i[0]" "wbs_we_i" 46.7738
cap "la_data_in[123]" "la_oenb[122]" 46.7738
cap "la_oenb[73]" "la_data_out[73]" 46.7738
cap "io_in_3v3[21]" "io_in[21]" 67.2299
cap "io_oeb[11]" "io_out[11]" 67.2299
cap "la_data_in[74]" "la_oenb[73]" 46.7738
cap "la_data_in[18]" "la_oenb[17]" 46.7738
cap "la_oenb[50]" "la_data_in[51]" 46.7738
cap "io_in_3v3[22]" "gpio_noesd[15]" 67.2299
cap "m2_54170_202730#" "m2_55523_202892#" 3.85136
cap "la_data_in[122]" "la_data_in[120]" 53.131
cap "la_data_in[77]" "la_data_out[77]" 46.7738
cap "la_data_out[53]" "la_oenb[53]" 46.7738
cap "gpio_noesd[14]" "gpio_analog[14]" 67.2299
cap "la_data_out[49]" "la_data_in[49]" 46.7738
cap "la_data_out[4]" "la_data_out[5]" 41443
cap "la_data_in[75]" "la_data_out[75]" 46.7738
cap "la_data_out[75]" "la_oenb[75]" 46.7738
cap "la_data_in[124]" "m2_33290_207480#" 2.87201
cap "m2_53160_202790#" "m2_55523_202892#" 0.270747
cap "la_data_in[77]" "la_oenb[76]" 46.7738
cap "gpio_noesd[9]" "gpio_analog[9]" 67.2299
cap "la_data_in[76]" "la_oenb[75]" 46.7738
cap "la_oenb[96]" "la_data_out[96]" 46.7738
cap "m1_49580_204344#" "vssa2" 4217.68
cap "la_data_in[121]" "la_data_in[125]" 18.8163
cap "m2_53493_202942#" "m2_55523_202892#" 0.157044
cap "la_data_in[18]" "la_data_out[18]" 46.7738
cap "la_data_in[76]" "la_data_out[76]" 46.7738
cap "la_oenb[77]" "la_data_out[77]" 46.7738
cap "la_data_in[122]" "m2_33290_207480#" 2.87201
cap "m2_54170_202730#" "m2_33290_207480#" 6.99285
cap "m2_54833_202912#" "m2_55523_202892#" 53.9085
cap "la_data_in[127]" "la_data_in[125]" 817.487
cap "la_oenb[76]" "la_data_out[76]" 46.7738
cap "la_data_in[121]" "vccd1" 4804.4
cap "la_oenb[79]" "la_data_in[80]" 46.7738
cap "la_oenb[77]" "la_data_in[78]" 46.7738
cap "m2_53160_202790#" "m2_33290_207480#" 3.33846
cap "la_data_in[127]" "vccd1" 2058.2
cap "la_data_out[48]" "la_data_in[48]" 46.7738
cap "vccd2" "io_analog[3]" 1369.55
cap "la_data_out[49]" "la_oenb[49]" 46.7738
cap "la_data_out[78]" "la_data_in[78]" 46.7738
cap "la_data_in[106]" "la_data_out[106]" 46.7738
cap "m2_33290_207480#" "m2_34420_199220#" 9072.85
cap "m2_53493_202942#" "m2_33290_207480#" 2.99625
cap "m2_33290_207480#" "la_data_in[126]" 2.87201
cap "m2_54520_202790#" "m2_55523_202892#" 2.3884
cap "m2_54833_202912#" "m2_33290_207480#" 7.50519
cap "la_data_in[50]" "la_oenb[49]" 46.7738
cap "la_data_in[14]" "la_oenb[13]" 46.7738
cap "la_data_out[78]" "la_oenb[78]" 46.7738
cap "la_data_in[50]" "la_data_out[50]" 46.7738
cap "io_out[13]" "io_oeb[13]" 67.2299
cap "la_data_out[84]" "la_oenb[84]" 46.7738
cap "la_data_in[16]" "la_oenb[15]" 46.7738
cap "la_data_in[103]" "la_oenb[102]" 46.7738
cap "io_out[13]" "io_in[13]" 67.2299
cap "la_data_in[14]" "la_data_out[14]" 46.7738
cap "la_data_in[99]" "la_data_out[99]" 46.7738
cap "la_oenb[14]" "la_data_out[14]" 46.7738
cap "io_in_3v3[25]" "io_in[25]" 67.2299
cap "la_oenb[14]" "la_data_in[15]" 46.7738
cap "la_data_out[103]" "la_data_in[103]" 46.7738
cap "m2_54520_202790#" "m2_33290_207480#" 1.36477
cap "la_data_out[13]" "la_oenb[13]" 46.7738
cap "la_oenb[105]" "la_data_in[106]" 46.7738
cap "la_data_out[4]" "la_data_in[4]" 46.7738
cap "la_data_in[15]" "la_data_out[15]" 46.7738
cap "la_oenb[55]" "la_data_out[55]" 46.7738
cap "la_data_in[79]" "la_oenb[78]" 46.7738
cap "la_data_out[97]" "la_data_in[97]" 46.7738
cap "la_oenb[79]" "la_data_out[79]" 46.7738
cap "io_in_3v3[11]" "gpio_noesd[4]" 67.2299
cap "la_data_out[4]" "la_oenb[4]" 46.7738
cap "la_oenb[103]" "la_data_in[104]" 46.7738
cap "la_data_in[102]" "la_oenb[101]" 46.7738
cap "la_oenb[15]" "la_data_out[15]" 46.7738
cap "la_data_out[97]" "la_oenb[97]" 46.7738
cap "gpio_analog[16]" "gpio_noesd[16]" 67.2299
cap "la_data_in[102]" "la_data_out[102]" 46.7738
cap "io_analog[2]" "m2_55523_202892#" 0.147298
cap "la_data_in[80]" "la_data_out[80]" 46.7738
cap "io_analog[2]" "la_data_in[120]" 4.42856
cap "la_oenb[106]" "la_data_out[106]" 46.7738
cap "la_oenb[101]" "la_data_out[101]" 46.7738
cap "la_oenb[102]" "la_data_out[102]" 46.7738
cap "la_data_in[125]" "la_data_out[125]" 46.7738
cap "la_data_in[124]" "la_data_in[122]" 302.51
cap "la_data_in[79]" "la_data_out[79]" 46.7738
cap "la_data_in[104]" "la_data_out[104]" 46.7738
cap "io_in[4]" "io_out[4]" 67.2299
cap "la_data_in[124]" "la_oenb[123]" 46.7738
cap "la_oenb[103]" "la_data_out[103]" 46.7738
cap "la_oenb[45]" "la_data_in[46]" 46.7738
cap "io_analog[2]" "m2_33290_207480#" 3359.84
cap "io_analog[6]" "io_clamp_high[2]" 468.333
cap "la_data_in[46]" "la_data_out[46]" 46.7738
cap "io_analog[4]" "io_clamp_low[0]" 493.833
cap "8bit_sens_0/GND" "8bit_sens_0/OUTx6x" 8.88178e-16
cap "8bit_sens_0/GND" "8bit_sens_0/OUTx5x" 8.88178e-16
cap "8bit_sens_0/OUTx2x" "8bit_sens_0/GND" -5.55112e-17
cap "8bit_sens_0/OUTx6x" "8bit_sens_0/GND" -1.11022e-16
cap "8bit_sens_0/OUTx0x" "8bit_sens_0/GND" 3.33067e-16
cap "8bit_sens_0/OUTx1x" "8bit_sens_0/GND" 1.77636e-15
cap "8bit_sens_0/OUTx5x" "8bit_sens_0/GND" 1.11022e-16
cap "8bit_sens_0/OUTx2x" "8bit_sens_0/GND" -6.88338e-15
cap "8bit_sens_0/OUTx4x" "8bit_sens_0/GND" -8.88178e-16
cap "8bit_sens_0/sens_amp_7/GND" "8bit_sens_0/OUTx0x" 1.33227e-15
cap "8bit_sens_0/OUTx5x" "8bit_sens_0/OUTx6x" -12.6429
cap "8bit_sens_0/VREF" "8bit_sens_0/GND" -2.43448
cap "8bit_sens_0/OUTx3x" "8bit_sens_0/GND" 0.097116
cap "8bit_sens_0/OUTx7x" "8bit_sens_0/SA_IREF" 25.0196
cap "8bit_sens_0/OUTx2x" "8bit_sens_0/GND" 0.0265611
cap "8bit_sens_0/OUTx4x" "8bit_sens_0/GND" 0.281005
cap "8bit_sens_0/OUTx7x" "8bit_sens_0/OUTx6x" -12.6429
cap "8bit_sens_0/VREF" "8bit_sens_0/SA_IREF" -7.306
cap "8bit_sens_0/SA_IREF" "8bit_sens_0/GND" 89.5079
cap "8bit_sens_0/OUTx5x" "8bit_sens_0/OUTx4x" -6.32143
cap "8bit_sens_0/sens_amp_3/net2" "8bit_sens_0/GND" 0.0331839
cap "8bit_sens_0/sens_amp_2/net2" "8bit_sens_0/GND" 0.169501
cap "8bit_sens_0/sens_amp_1/net2" "8bit_sens_0/GND" 0.287108
cap "8bit_sens_0/sens_amp_0/net2" "8bit_sens_0/GND" 0.373021
cap "8bit_sens_0/OUTx5x" "8bit_sens_0/GND" 19.0329
cap "8bit_sens_0/OUTx6x" "8bit_sens_0/GND" 24.4068
cap "8bit_sens_0/OUTx5x" "8bit_sens_0/SA_IREF" 9.36696
cap "8bit_sens_0/OUTx7x" "8bit_sens_0/GND" 74.051
cap "8bit_sens_0/sens_amp_0/GN" "8bit_sens_0/GND" -0.577617
cap "8bit_sens_0/SA_IREF" "8bit_sens_0/OUTx6x" 10.8301
cap "8bit_sens_0/OUTx1x" "8bit_sens_0/GND" 0.00477041
cap "8bit_sens_0/OUTx3x" "8bit_sens_0/OUTx2x" -12.6429
cap "8bit_sens_0/OUTx1x" "8bit_sens_0/OUTx0x" -6.32143
cap "8bit_sens_0/SA_IREF" "8bit_sens_0/GND" 76.6531
cap "8bit_sens_0/OUTx4x" "8bit_sens_0/GND" 14.8476
cap "8bit_sens_0/GND" "vccd1" 3.21876
cap "8bit_sens_0/OUTx1x" "8bit_sens_0/OUTx2x" -12.6429
cap "8bit_sens_0/OUTx5x" "8bit_sens_0/GND" 0.16042
cap "8bit_sens_0/GND" "8bit_sens_0/OUTx0x" 0.118975
cap "8bit_sens_0/OUTx3x" "8bit_sens_0/GND" 13.5713
cap "8bit_sens_0/GND" "8bit_sens_0/OUTx2x" 13.3401
cap "8bit_sens_0/SA_IREF" "8bit_sens_0/OUTx4x" 8.38595
cap "8bit_sens_0/SA_IREF" "vccd1" 3.31434
cap "8bit_sens_0/OUTx1x" "8bit_sens_0/GND" 13.1055
cap "8bit_sens_0/GND" "8bit_sens_0/OUTx7x" 0.0664863
cap "8bit_sens_0/OUTx5x" "8bit_sens_0/OUTx4x" -6.32143
cap "8bit_sens_0/OUTx3x" "vccd1" 0.00125677
cap "8bit_sens_0/OUTx3x" "8bit_sens_0/OUTx4x" -12.6429
cap "8bit_sens_0/OUTx3x" "8bit_sens_0/SA_IREF" 7.99533
cap "vccd1" "8bit_sens_0/OUTx2x" 1.35388
cap "8bit_sens_0/SA_IREF" "8bit_sens_0/OUTx2x" 7.99091
cap "8bit_sens_0/OUTx1x" "vccd1" 3.96202
cap "8bit_sens_0/SA_IREF" "8bit_sens_0/OUTx1x" 7.99091
cap "8bit_sens_0/GND" "8bit_sens_0/OUTx6x" 0.112585
cap "8bit_sens_0/OUTx0x" "8bit_sens_0/sens_amp_7/GND" 12.924
cap "8bit_sens_0/sens_amp_7/SA_IREF" "8bit_sens_0/sens_amp_7/GND" 21.394
cap "8bit_sens_0/sens_amp_7/GND" "vccd1" 60.8494
cap "8bit_sens_0/sens_amp_4/net2" "vccd1" 0.000830487
cap "8bit_sens_0/OUTx2x" "8bit_sens_0/sens_amp_7/GND" 0.0469076
cap "8bit_sens_0/OUTx3x" "vccd1" 0.00133855
cap "8bit_sens_0/OUTx4x" "8bit_sens_0/sens_amp_7/GND" 0.0201973
cap "8bit_sens_0/OUTx0x" "8bit_sens_0/OUTx1x" -6.32143
cap "vccd1" "8bit_sens_0/OUTx1x" 0.97411
cap "8bit_sens_0/sens_amp_7/net2" "vccd1" 0.349358
cap "8bit_sens_0/OUTx0x" "8bit_sens_0/sens_amp_7/SA_IREF" 7.90954
cap "8bit_sens_0/OUTx0x" "vccd1" 28.0943
cap "8bit_sens_0/sens_amp_7/SA_IREF" "vccd1" 30.0592
cap "8bit_sens_0/sens_amp_7/GND" "8bit_sens_0/OUTx5x" 0.00265253
cap "8bit_sens_0/sens_amp_6/net2" "vccd1" 0.251959
cap "8bit_sens_0/sens_amp_5/net2" "vccd1" 0.126747
cap "8bit_sens_0/OUTx2x" "vccd1" 0.498735
cap "8bit_sens_0/OUTx3x" "8bit_sens_0/sens_amp_7/GND" 0.0355126
cap "8bit_sens_0/sens_amp_7/GND" "8bit_sens_0/OUTx1x" 0.0531246
cap "8bit_sens_0/sens_amp_3/net2" "8bit_sens_0/GND" 0.921743
cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_1/net2" 11.1413
cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_2/net2" 6.11903
cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_0/GN" 160.955
cap "8bit_sens_0/sens_amp_2/GN" "8bit_sens_0/GND" 6.14071
cap "8bit_sens_0/sens_amp_0/net2" "8bit_sens_0/VREF" 0.346563
cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_3/V_IN" 0.0624547
cap "8bit_sens_0/VREF" "8bit_sens_0/SA_IREF" -7.306
cap "8bit_sens_0/sens_amp_1/net1" "8bit_sens_0/GND" 8.43054
cap "8bit_sens_0/VREF" "8bit_sens_0/sens_amp_2/net2" 0.059207
cap "8bit_sens_0/VREF" "8bit_sens_0/sens_amp_1/net2" 0.140127
cap "8bit_sens_0/sens_amp_1/GN" "8bit_sens_0/GND" 9.68531
cap "8bit_sens_0/OUTx6x" "8bit_sens_0/GND" 17.2805
cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_0/net1" 12.9026
cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_2/V_IN" 1.73793
cap "8bit_sens_0/OUTx5x" "8bit_sens_0/GND" 7.8019
cap "8bit_sens_0/OUTx6x" "8bit_sens_0/VREF" 4.41884
cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_3/net1" 0.0454266
cap "8bit_sens_0/VREF" "8bit_sens_0/sens_amp_2/V_IN" 0.030099
cap "8bit_sens_0/sens_amp_1/V_IN" "8bit_sens_0/GND" 9.68278
cap "8bit_sens_0/OUTx5x" "8bit_sens_0/VREF" 2.69102
cap "8bit_sens_0/sens_amp_2/net1" "8bit_sens_0/GND" 2.94126
cap "8bit_sens_0/sens_amp_3/GN" "8bit_sens_0/GND" 1.83476
cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_0/V_IN" 20.9299
cap "8bit_sens_0/sens_amp_1/V_IN" "8bit_sens_0/VREF" 0.956371
cap "8bit_sens_0/sens_amp_0/V_IN" "8bit_sens_0/VREF" 1.64367
cap "8bit_sens_0/GND" "8bit_sens_0/VREF" 31.9201
cap "8bit_sens_0/OUTx7x" "8bit_sens_0/GND" 87.5014
cap "8bit_sens_0/OUTx4x" "8bit_sens_0/GND" 0.20749
cap "8bit_sens_0/OUTx7x" "8bit_sens_0/VREF" 20.7466
cap "8bit_sens_0/sens_amp_0/net2" "8bit_sens_0/GND" 19.9562
cap "8bit_sens_0/OUTx4x" "8bit_sens_0/VREF" 1.51852
cap "8bit_sens_0/OUTx2x" "8bit_sens_0/VREF" 1.02099
cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_6/GN" 1.35525
cap "8bit_sens_0/sens_amp_2/net1" "8bit_sens_0/GND" 1.05257
cap "8bit_sens_0/OUTx1x" "8bit_sens_0/VREF" 1.02099
cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_5/GN" 1.35525
cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_3/V_IN" 0.130599
cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_3/net1" 0.00487782
cap "8bit_sens_0/GND" "8bit_sens_0/VREF" 13.8517
cap "8bit_sens_0/sens_amp_3/V_IN" "8bit_sens_0/VREF" 0.0968678
cap "8bit_sens_0/sens_amp_6/V_IN" "vccd1" 0.514685
cap "8bit_sens_0/OUTx3x" "8bit_sens_0/VREF" 1.03075
cap "8bit_sens_0/sens_amp_5/V_IN" "vccd1" 3.12832
cap "8bit_sens_0/sens_amp_6/net2" "vccd1" 2.27431
cap "8bit_sens_0/sens_amp_5/net2" "vccd1" 0.800337
cap "8bit_sens_0/sens_amp_4/net2" "vccd1" 0.00039027
cap "8bit_sens_0/sens_amp_4/V_IN" "vccd1" 0.200479
cap "8bit_sens_0/OUTx2x" "vccd1" 3.91462
cap "8bit_sens_0/sens_amp_4/net1" "vccd1" 0.0396777
cap "8bit_sens_0/sens_amp_4/GN" "8bit_sens_0/GND" 0.968036
cap "8bit_sens_0/OUTx1x" "vccd1" 9.65709
cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_3/GN" 0.787218
cap "8bit_sens_0/sens_amp_6/GN" "vccd1" 0.846347
cap "8bit_sens_0/sens_amp_6/net1" "vccd1" 0.130132
cap "8bit_sens_0/sens_amp_5/GN" "vccd1" 0.223338
cap "8bit_sens_0/sens_amp_2/V_IN" "8bit_sens_0/GND" 2.43521
cap "8bit_sens_0/GND" "vccd1" 2.92156
cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_3/net2" 0.086469
cap "8bit_sens_0/OUTx4x" "8bit_sens_0/GND" 0.346226
cap "8bit_sens_0/OUTx3x" "vccd1" 0.012011
cap "8bit_sens_0/sens_amp_2/V_IN" "8bit_sens_0/VREF" 0.382231
cap "8bit_sens_0/VREF" "vccd1" 0.489321
cap "8bit_sens_0/sens_amp_3/net2" "8bit_sens_0/VREF" 0.0197323
cap "8bit_sens_0/sens_amp_4/net2" "8bit_sens_0/VREF" 0.00050636
cap "8bit_sens_0/sens_amp_5/net1" "vccd1" 0.530241
cap "vccd1" "8bit_sens_0/sens_amp_7/net2" 21.9497
cap "vccd1" "8bit_sens_0/sens_amp_5/net2" 4.35189
cap "vccd1" "8bit_sens_0/sens_amp_6/net2" 8.6511
cap "8bit_sens_0/sens_amp_7/V_IN" "8bit_sens_0/sens_amp_7/net1" -0.0342863
cap "vccd1" "8bit_sens_0/OUTx1x" 3.43359
cap "8bit_sens_0/sens_amp_7/REF" "8bit_sens_0/sens_amp_7/GND" 3.85327
cap "vccd1" "8bit_sens_0/sens_amp_7/net1" 123.385
cap "vccd1" "8bit_sens_0/sens_amp_4/net1" 0.887485
cap "vccd1" "8bit_sens_0/sens_amp_7/GND" 14.7299
cap "vccd1" "8bit_sens_0/sens_amp_6/net1" 9.33374
cap "vccd1" "8bit_sens_0/sens_amp_5/net1" 4.88252
cap "vccd1" "8bit_sens_0/sens_amp_5/GN" 2.57483
cap "vccd1" "8bit_sens_0/sens_amp_6/GN" 6.69563
cap "vccd1" "8bit_sens_0/sens_amp_7/GN" 11.7452
cap "vccd1" "8bit_sens_0/sens_amp_4/V_IN" 0.33888
cap "8bit_sens_0/OUTx0x" "8bit_sens_0/sens_amp_7/REF" 1.02099
cap "8bit_sens_0/sens_amp_7/V_IN" "8bit_sens_0/sens_amp_7/REF" -0.194099
cap "vccd1" "8bit_sens_0/OUTx2x" 1.82132
cap "8bit_sens_0/OUTx0x" "vccd1" 63.5416
cap "vccd1" "8bit_sens_0/sens_amp_7/REF" 16.8039
cap "vccd1" "8bit_sens_0/sens_amp_4/net2" 0.00868596
cap "8bit_sens_0/sens_amp_7/V_IN" "vccd1" 65.3675
cap "vccd1" "8bit_sens_0/OUTx3x" 0.0708511
cap "vccd1" "8bit_sens_0/sens_amp_6/V_IN" 10.5086
cap "vccd1" "8bit_sens_0/sens_amp_5/V_IN" 2.473
cap "8bit_sens_0/sens_amp_7/GN" "8bit_sens_0/sens_amp_7/GND" 1.16164
cap "adc_0/GND" "8bit_sens_0/VDD" 156.822
cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 66.3972
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_sens_0/VDD" 0.00356583
cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 0.62612
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "adc_0/GND" 11.7749
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_sens_0/VDD" 0.00392936
cap "8bit_sens_0/sens_amp_0/GN" "adc_0/GND" 91.2977
cap "8bit_sens_0/sens_amp_0/GN" "8bit_sens_0/VDD" -5.14306
cap "adc_0/GND" "8bit_sens_0/sens_amp_1/GN" 12.1075
cap "adc_0/GND" "8bit_sens_0/sens_amp_2/GN" 4.07279
cap "adc_0/GND" "8bit_sens_0/sens_amp_3/GN" 0.494835
cap "8bit_sens_0/sens_amp_2/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.000145326
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_2/GN" 0.000722111
cap "adc_0/GND" "8bit_sens_0/sens_amp_0/net1" 39.1704
cap "adc_0/GND" "8bit_sens_0/sens_amp_1/net1" 5.5773
cap "adc_0/GND" "8bit_sens_0/sens_amp_3/net1" 0.467675
cap "8bit_sens_0/sens_amp_2/net1" "adc_0/GND" 2.89451
cap "8bit_sens_0/VDD" "8bit_sens_0/sens_amp_0/net1" -12.2782
cap "8bit_sens_0/sens_amp_0/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.102927
cap "adc_0/GND" "8bit_sens_0/sens_amp_2/OUT" 5.10821
cap "adc_0/GND" "8bit_sens_0/sens_amp_1/OUT" 12.0665
cap "adc_0/GND" "8bit_sens_0/sens_amp_0/OUT" 52.9101
cap "8bit_sens_0/sens_amp_2/GN" "adc_0/READ" 1.99139
cap "adc_0/GND" "8bit_sens_0/sens_amp_3/OUT" 0.19763
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_sens_0/sens_amp_1/GN" 0.303566
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_sens_0/sens_amp_2/GN" 0.273461
cap "8bit_sens_0/sens_amp_2/net1" "adc_0/READ" 0.0843564
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_sens_0/sens_amp_0/net1" 0.175357
cap "8bit_sens_0/sens_amp_1/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.0627715
cap "8bit_sens_0/sens_amp_2/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.0483017
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_sens_0/sens_amp_2/OUT" 0.000423023
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_sens_0/sens_amp_1/OUT" 0.00211512
cap "8bit_sens_0/sens_amp_2/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.111884
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_sens_0/sens_amp_1/GN" 0.157883
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_sens_0/sens_amp_2/GN" 0.457219
cap "8bit_sens_0/sens_amp_2/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.0282082
cap "8bit_sens_0/sens_amp_2/OUT" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.000927367
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_sens_0/sens_amp_2/net1" 0.0992089
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_sens_0/sens_amp_1/net1" 0.246821
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_sens_0/sens_amp_2/OUT" 0.00159606
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_sens_0/sens_amp_1/OUT" 0.00570518
cap "8bit_sens_0/sens_amp_0/GN" "8bit_sens_0/sens_amp_0/net1" -4.61959
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "8bit_sens_0/sens_amp_5/GN" 1.14389
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_sens_0/sens_amp_4/OUT" 0.000506156
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_sens_0/sens_amp_5/GN" 1.22164
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_sens_0/sens_amp_5/GN" 0.0808306
cap "8bit_sens_0/sens_amp_5/GN" "adc_0/READ" 0.591551
cap "8bit_sens_0/VDD" "8bit_sens_0/sens_amp_4/OUT" 0.0357335
cap "8bit_sens_0/VDD" "8bit_sens_0/sens_amp_5/GN" 0.708908
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_4/OUT" 6.3654e-05
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_5/GN" 0.0014115
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "8bit_sens_0/sens_amp_5/GN" 0.0400408
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_sens_0/sens_amp_6/GN" 0.435347
cap "8bit_sens_0/sens_amp_6/GN" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 1.42888
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_sens_0/sens_amp_6/GN" 0.683984
cap "8bit_sens_0/sens_amp_2/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.0409452
cap "8bit_sens_0/sens_amp_3/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.490914
cap "8bit_sens_0/sens_amp_2/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" 0.0425475
cap "8bit_sens_0/sens_amp_6/GN" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 0.0158366
cap "8bit_sens_0/sens_amp_6/GN" "adc_0/READ" 1.95307
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_sens_0/sens_amp_3/GN" 2.41969
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_sens_0/sens_amp_3/GN" 0.121543
cap "8bit_sens_0/sens_amp_2/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.0144699
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_sens_0/sens_amp_3/GN" 0.0331687
cap "8bit_sens_0/sens_amp_3/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 0.579283
cap "8bit_sens_0/sens_amp_2/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.36833
cap "8bit_sens_0/sens_amp_2/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 0.1354
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_sens_0/sens_amp_3/GN" 0.48721
cap "8bit_sens_0/VDD" "8bit_sens_0/sens_amp_6/GN" 0.582767
cap "8bit_sens_0/sens_amp_2/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" 0.440383
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_6/GN" 0.00218938
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "8bit_sens_0/sens_amp_6/GN" 0.00147748
cap "8bit_sens_0/sens_amp_3/GN" "adc_0/READ" 0.536569
cap "8bit_sens_0/sens_amp_2/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.0612079
cap "8bit_sens_0/sens_amp_2/net1" "adc_0/GND" 0.0571292
cap "8bit_sens_0/sens_amp_3/GN" "adc_0/GND" 0.0418919
cap "8bit_sens_0/sens_amp_2/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 0.0711138
cap "8bit_sens_0/VDD" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 4.39768
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_3/GN" 0.123162
cap "8bit_sens_0/sens_amp_2/GN" "adc_0/READ" 0.0421109
cap "8bit_sens_0/sens_amp_2/GN" "adc_0/GND" 0.497005
cap "8bit_sens_0/sens_amp_2/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.0338702
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "8bit_sens_0/VDD" 0.00493103
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "adc_0/GND" 3.21112
cap "8bit_sens_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 0.00237033
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_sens_0/VDD" 0.0168158
cap "8bit_sens_0/VDD" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" 0.296232
cap "8bit_sens_0/VDD" "adc_0/GND" 0.580863
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_sens_0/sens_amp_3/OUT" 0.000537226
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_sens_0/sens_amp_3/OUT" 0.0117192
cap "8bit_sens_0/sens_amp_3/OUT" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 0.00533579
cap "8bit_sens_0/sens_amp_6/OUT" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 0.00750245
cap "8bit_sens_0/sens_amp_3/OUT" "adc_0/GND" 0.0928868
cap "8bit_sens_0/sens_amp_6/OUT" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.000115921
cap "8bit_sens_0/sens_amp_5/OUT" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 0.0343946
cap "8bit_sens_0/sens_amp_6/OUT" "8bit_sens_0/VDD" 2.72813
cap "8bit_sens_0/sens_amp_4/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" 0.414702
cap "8bit_sens_0/sens_amp_4/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 1.86122
cap "8bit_sens_0/sens_amp_4/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 0.529835
cap "8bit_sens_0/sens_amp_4/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 0.57267
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_sens_0/sens_amp_5/OUT" 0.000337437
cap "8bit_sens_0/sens_amp_5/OUT" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" 0.00133403
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_sens_0/sens_amp_4/GN" 0.703745
cap "8bit_sens_0/sens_amp_4/GN" "adc_0/READ" 0.306517
cap "8bit_sens_0/VDD" "8bit_sens_0/sens_amp_5/OUT" 1.83224
cap "8bit_sens_0/sens_amp_4/GN" "8bit_sens_0/VDD" 0.0246887
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_sens_0/sens_amp_3/net1" 0.244359
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_sens_0/sens_amp_3/net1" 0.237107
cap "8bit_sens_0/sens_amp_4/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.246526
cap "8bit_sens_0/sens_amp_4/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 0.179271
cap "8bit_sens_0/sens_amp_3/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 0.000359135
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_sens_0/sens_amp_3/net1" 0.124794
cap "8bit_sens_0/sens_amp_3/net1" "adc_0/READ" 0.0140308
cap "8bit_sens_0/sens_amp_3/net1" "adc_0/GND" 0.0484713
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_3/net1" 0.0220289
cap "8bit_sens_0/sens_amp_5/net1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 0.447979
cap "8bit_sens_0/sens_amp_4/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" 0.0713977
cap "8bit_sens_0/sens_amp_4/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 0.166987
cap "8bit_sens_0/sens_amp_2/OUT" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.00466909
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_sens_0/sens_amp_6/net1" 0.236328
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "8bit_sens_0/sens_amp_5/net1" 0.136542
cap "8bit_sens_0/sens_amp_2/OUT" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" 0.00815426
cap "8bit_sens_0/sens_amp_4/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 0.00233038
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_sens_0/sens_amp_2/OUT" 0.00169209
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_sens_0/sens_amp_6/net1" 0.196463
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_sens_0/sens_amp_4/net1" 0.0723122
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_sens_0/sens_amp_5/net1" 0.024713
cap "8bit_sens_0/sens_amp_5/net1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" 0.10959
cap "8bit_sens_0/sens_amp_4/net1" "adc_0/READ" 0.0127659
cap "8bit_sens_0/sens_amp_5/net1" "adc_0/READ" 0.0126424
cap "8bit_sens_0/VDD" "8bit_sens_0/sens_amp_5/net1" 0.373979
cap "8bit_sens_0/sens_amp_4/net1" "8bit_sens_0/VDD" 0.00176569
cap "8bit_sens_0/sens_amp_4/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.0100531
cap "adc_0/READ" "8bit_sens_0/sens_amp_6/net1" 0.0604473
cap "8bit_sens_0/VDD" "8bit_sens_0/sens_amp_6/net1" 0.962288
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_sens_0/sens_amp_5/GN" 2.34629
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_sens_0/sens_amp_4/OUT" 0.00133464
cap "8bit_sens_0/sens_amp_4/net1" "8bit_sens_0/sens_amp_7/VDD" 0.0228878
cap "8bit_sens_0/sens_amp_7/VDD" "8bit_sens_0/sens_amp_5/GN" 3.30792
cap "8bit_sens_0/sens_amp_6/net1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 0.0289867
cap "8bit_sens_0/sens_amp_6/net1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 0.139851
cap "8bit_sens_0/sens_amp_7/VDD" "8bit_sens_0/sens_amp_4/GN" 0.22836
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_sens_0/sens_amp_7/VDD" 0.199942
cap "8bit_sens_0/sens_amp_7/OUT" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 0.0232407
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_sens_0/sens_amp_7/GN" 0.228534
cap "8bit_sens_0/sens_amp_6/net1" "8bit_sens_0/sens_amp_7/VDD" 4.92012
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_sens_0/sens_amp_6/GN" 0.0650655
cap "8bit_sens_0/sens_amp_7/GN" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 0.684429
cap "8bit_sens_0/sens_amp_7/net1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -0.793108
cap "8bit_sens_0/sens_amp_7/OUT" "8bit_sens_0/sens_amp_7/VDD" 56.0737
cap "8bit_sens_0/sens_amp_6/OUT" "8bit_sens_0/sens_amp_7/VDD" 7.2726
cap "8bit_sens_0/sens_amp_4/OUT" "8bit_sens_0/sens_amp_7/VDD" 0.267803
cap "8bit_sens_0/sens_amp_5/OUT" "8bit_sens_0/sens_amp_7/VDD" 3.55975
cap "8bit_sens_0/sens_amp_6/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.011391
cap "8bit_sens_0/sens_amp_7/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.266718
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_sens_0/sens_amp_6/GN" 0.0802203
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_sens_0/sens_amp_7/GN" 0.345086
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_sens_0/sens_amp_7/VDD" 65.8171
cap "8bit_sens_0/sens_amp_7/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.0113439
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_sens_0/sens_amp_7/VDD" 12.8326
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_sens_0/sens_amp_6/net1" 0.0215808
cap "8bit_sens_0/sens_amp_7/GN" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" 2.27861
cap "8bit_sens_0/sens_amp_7/net1" "8bit_sens_0/sens_amp_7/GN" -2.48043
cap "8bit_sens_0/sens_amp_7/net1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.140414
cap "8bit_sens_0/sens_amp_6/GN" "8bit_sens_0/sens_amp_7/VDD" 8.31155
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_7/GN" 0.103561
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_sens_0/sens_amp_7/VDD" 1.02129
cap "8bit_sens_0/sens_amp_7/GN" "8bit_sens_0/sens_amp_7/VDD" 34.3183
cap "8bit_sens_0/sens_amp_5/net1" "8bit_sens_0/sens_amp_7/VDD" 2.18103
cap "8bit_sens_0/sens_amp_7/VDD" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.00113212
cap "8bit_sens_0/sens_amp_7/net1" "8bit_sens_0/sens_amp_7/VDD" 92.266
cap "adc_0/GND" "8bit_sens_0/VDD" 476.975
cap "8bit_sens_0/sens_amp_2/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.00663047
cap "8bit_sens_0/sens_amp_3/net1" "adc_0/GND" 0.0215565
cap "adc_0/GND" "8bit_sens_0/sens_amp_2/net1" 0.839293
cap "8bit_sens_0/sens_amp_0/net1" "8bit_sens_0/VDD" -4.58957
cap "adc_0/V_IN" "8bit_sens_0/VDD" 0.179184
cap "adc_0/GND" "8bit_sens_0/sens_amp_3/GN" 0.256578
cap "8bit_sens_0/sens_amp_0/net1" "adc_0/GND" 15.7267
cap "adc_0/GND" "8bit_sens_0/sens_amp_1/net1" 7.83787
cap "8bit_sens_0/sens_amp_2/GN" "adc_0/GND" 1.31407
cap "adc_0/V_RAMP" "adc_0/GND" -0.00166719
cap "adc_0/BIAS2" "adc_0/OUTx6x" -0.690007
cap "adc_0/OUTx6x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.045174
cap "adc_0/GND" "8bit_sens_0/sens_amp_0/GN" 14.8289
cap "8bit_sens_0/sens_amp_1/GN" "adc_0/GND" 13.9906
cap "adc_0/GND" "adc_0/OUTx4x" 1.68602
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/VDD" 0.529274
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/OUTx7x" 0.0410053
cap "8bit_sens_0/sens_amp_2/OUT" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.0055825
cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 2.24459
cap "adc_0/READ" "adc_0/OUTx6x" 31.322
cap "adc_0/OUTx5x" "adc_0/OUTx6x" -2.45627
cap "adc_0/OUTx6x" "adc_0/BIAS1" -0.464168
cap "vccd1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.00125642
cap "8bit_sens_0/sens_amp_2/GN" "adc_0/V_IN" 0.000545017
cap "8bit_sens_0/sens_amp_0/net1" "8bit_sens_0/sens_amp_0/GN" -1.44537
cap "vccd1" "adc_0/READ" 0.260488
cap "8bit_sens_0/sens_amp_2/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.0469935
cap "8bit_sens_0/VDD" "adc_0/OUTx7x" 10.2713
cap "adc_0/GND" "adc_0/OUTx7x" 52.0699
cap "adc_0/OUTx1x" "adc_0/GND" 0.171874
cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 0.181686
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "adc_0/GND" 0.0047473
cap "8bit_sens_0/sens_amp_1/OUT" "adc_0/OUTx7x" 0.00725774
cap "8bit_sens_0/sens_amp_2/net1" "adc_0/OUTx7x" 0.0467264
cap "8bit_sens_0/sens_amp_2/GN" "adc_0/OUTx7x" 0.498847
cap "8bit_sens_0/sens_amp_1/net1" "adc_0/OUTx7x" 0.323423
cap "8bit_sens_0/sens_amp_0/net1" "adc_0/OUTx7x" 0.0577243
cap "adc_0/V_IN" "adc_0/OUTx7x" 0.183996
cap "adc_0/OUTx4x" "adc_0/OUTx7x" 0.253751
cap "adc_0/V_RAMP" "adc_0/OUTx7x" -0.0338338
cap "8bit_sens_0/sens_amp_1/GN" "adc_0/OUTx7x" 0.615347
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/OUTx7x" 0.275768
cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 2.05896
cap "adc_0/GRAY_INx4x" "adc_0/GND" 0.970299
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "8bit_sens_0/VDD" 4.01677
cap "adc_0/BIAS2" "8bit_sens_0/VDD" 0.0520965
cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 2.09686
cap "adc_0/GRAY_INx7x" "adc_0/GND" 9.08509
cap "8bit_sens_0/sens_amp_2/OUT" "adc_0/OUTx6x" 0.173705
cap "adc_0/GND" "adc_0/GRAY_INx5x" 2.95633
cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 1.10418
cap "adc_0/OUTx0x" "adc_0/GND" 0.170792
cap "vccd1" "adc_0/OUTx6x" 0.145948
cap "adc_0/READ" "8bit_sens_0/VDD" 46.7899
cap "adc_0/READ" "adc_0/VDD" 0.139243
cap "adc_0/GND" "adc_0/GRAY_INx6x" 2.27164
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "8bit_sens_0/sens_amp_2/net1" 0.163076
cap "adc_0/READ" "adc_0/GND" 137.881
cap "adc_0/OUTx5x" "adc_0/GND" 4.74121
cap "adc_0/GND" "adc_0/BIAS1" -0.00241621
cap "adc_0/GND" "adc_0/OUTx3x" 2.45492
cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.0901808
cap "8bit_sens_0/sens_amp_2/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.446446
cap "adc_0/GRAY_INx2x" "adc_0/GND" 0.369575
cap "adc_0/V_RAMP" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.00793409
cap "adc_0/READ" "8bit_sens_0/sens_amp_2/net1" 0.415491
cap "8bit_sens_0/sens_amp_2/GN" "adc_0/READ" 13.1914
cap "adc_0/V_RAMP" "adc_0/READ" 0.291005
cap "adc_0/OUTx6x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.0227248
cap "adc_0/BIAS2" "adc_0/OUTx7x" 0.00123831
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/OUTx7x" 0.0824328
cap "adc_0/GRAY_INx7x" "adc_0/OUTx7x" 0.029749
cap "adc_0/GRAY_INx5x" "adc_0/OUTx7x" 0.0144116
cap "adc_0/READ" "adc_0/OUTx7x" 37.2468
cap "adc_0/OUTx5x" "adc_0/OUTx7x" -0.17
cap "adc_0/BIAS1" "adc_0/OUTx7x" -0.100564
cap "adc_0/OUTx6x" "adc_0/VDD" 0.0631894
cap "adc_0/OUTx6x" "8bit_sens_0/VDD" 96.7482
cap "adc_0/OUTx6x" "adc_0/GND" 118.315
cap "adc_0/GND" "adc_0/OUTx2x" 1.01954
cap "adc_0/OUTx6x" "8bit_sens_0/sens_amp_1/OUT" 0.302986
cap "adc_0/OUTx6x" "8bit_sens_0/sens_amp_2/net1" 1.57896
cap "vccd1" "adc_0/GND" -0.000898652
cap "8bit_sens_0/sens_amp_2/GN" "adc_0/OUTx6x" 9.01557
cap "adc_0/OUTx6x" "8bit_sens_0/sens_amp_1/net1" 6.40104
cap "adc_0/OUTx6x" "adc_0/OUTx4x" -0.961303
cap "adc_0/V_RAMP" "adc_0/OUTx6x" 0.034461
cap "adc_0/V_IN" "adc_0/OUTx6x" 0.141758
cap "8bit_sens_0/sens_amp_1/GN" "adc_0/OUTx6x" 3.78179
cap "adc_0/GRAY_INx3x" "adc_0/GND" 1.27589
cap "adc_0/OUTx6x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.4948
cap "adc_0/BIAS2" "adc_0/READ" 2.42618
cap "adc_0/READ" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" -0.179839
cap "adc_0/BIAS1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.0164328
cap "adc_0/OUTx2x" "adc_0/OUTx7x" -0.00174371
cap "adc_0/OUTx6x" "adc_0/OUTx7x" -5.68191
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_sens_0/VDD" 0.156399
cap "adc_0/READ" "adc_0/BIAS1" 2.551
cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 2.6439
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "adc_0/GND" 0.0950629
cap "8bit_sens_0/sens_amp_2/OUT" "adc_0/OUTx7x" 0.00241902
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "adc_0/VDD" 7.27989
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "adc_0/VDD" 2.61852
cap "adc_0/GND" "adc_0/VDD" 11.5888
cap "adc_0/V_IN" "adc_0/VDD" 2.39161
cap "adc_0/a_1000_n1450#" "adc_0/VDD" 0.334655
cap "adc_0/a_1720_n1450#" "adc_0/VDD" 0.256808
cap "8bit_sens_0/sens_amp_6/OUT" "adc_0/OUTx0x" 0.750956
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "8bit_sens_0/sens_amp_2/GN" 1.1903
cap "adc_0/OUTx6x" "8bit_sens_0/sens_amp_2/GN" 3.05663
cap "adc_0/OUTx6x" "adc_0/GRAY_INx4x" -0.00119257
cap "adc_0/OUTx6x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" -1.77485
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/GRAY_INx6x" -0.0161971
cap "adc_0/GRAY_INx4x" "adc_0/OUTx4x" -0.0014868
cap "adc_0/GRAY_INx1x" "adc_0/GRAY_INx4x" -0.00384267
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/OUTx7x" 1.659
cap "adc_0/OUTx7x" "8bit_sens_0/sens_amp_2/GN" 0.177705
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/GRAY_INx7x" -2.35733
cap "adc_0/GRAY_INx4x" "adc_0/GRAY_INx7x" -0.00135158
cap "adc_0/OUTx3x" "adc_0/GRAY_INx4x" 14.5447
cap "adc_0/GRAY_INx5x" "adc_0/GRAY_INx4x" -0.00153296
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/OUTx5x" 3.70053
cap "adc_0/OUTx5x" "adc_0/GRAY_INx4x" 0.538846
cap "adc_0/GRAY_INx3x" "adc_0/GRAY_INx4x" -0.00496884
cap "adc_0/OUTx6x" "adc_0/GRAY_INx6x" -0.00119747
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "adc_0/OUTx4x" 3.80667
cap "adc_0/OUTx6x" "adc_0/OUTx4x" -6.18725
cap "adc_0/GRAY_INx6x" "adc_0/OUTx4x" -0.000998441
cap "adc_0/READ" "8bit_sens_0/sens_amp_2/GN" 1.47446
cap "adc_0/GRAY_INx1x" "adc_0/GRAY_INx6x" -0.000390028
cap "adc_0/READ" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" -0.00239769
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/BIAS1" 0.103354
cap "adc_0/OUTx5x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 2.29712
cap "adc_0/OUTx6x" "adc_0/OUTx7x" 20.3389
cap "adc_0/READ" "adc_0/GRAY_INx4x" -2.92799
cap "adc_0/GRAY_INx5x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" -0.934061
cap "adc_0/OUTx7x" "adc_0/GRAY_INx6x" -7.09689
cap "adc_0/OUTx6x" "adc_0/GRAY_INx7x" -0.498991
cap "adc_0/OUTx6x" "adc_0/OUTx5x" 5.77365
cap "adc_0/OUTx6x" "adc_0/OUTx3x" -0.117724
cap "adc_0/OUTx3x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 1.90521
cap "adc_0/OUTx7x" "adc_0/OUTx4x" -0.453278
cap "adc_0/GRAY_INx6x" "adc_0/GRAY_INx7x" 0.00252296
cap "adc_0/GRAY_INx5x" "adc_0/GRAY_INx6x" -0.000956435
cap "adc_0/GRAY_INx3x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" -2.48031
cap "adc_0/OUTx5x" "adc_0/GRAY_INx6x" 59.832
cap "adc_0/OUTx5x" "adc_0/OUTx4x" 17.379
cap "adc_0/GRAY_INx3x" "adc_0/GRAY_INx6x" -0.000739663
cap "adc_0/OUTx3x" "adc_0/OUTx4x" -2.43468
cap "adc_0/OUTx6x" "adc_0/OUTx1x" -0.024305
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_sens_0/sens_amp_2/GN" 0.00205703
cap "adc_0/OUTx1x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.318626
cap "8bit_sens_0/sens_amp_6/net1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.00685071
cap "adc_0/READ" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" -2.54453
cap "adc_0/OUTx5x" "adc_0/GRAY_INx1x" -0.000778297
cap "8bit_sens_0/sens_amp_6/net1" "adc_0/GND" 0.00585743
cap "adc_0/READ" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" -2.90901
cap "adc_0/READ" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" -0.132168
cap "adc_0/OUTx7x" "adc_0/GRAY_INx7x" -0.675707
cap "adc_0/OUTx6x" "adc_0/READ" 0.2005
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "8bit_sens_0/sens_amp_5/net1" 0.281215
cap "adc_0/OUTx1x" "adc_0/OUTx4x" 0.450912
cap "adc_0/OUTx6x" "adc_0/BIAS1" -0.0275125
cap "adc_0/OUTx5x" "adc_0/OUTx7x" 13.9109
cap "adc_0/GRAY_INx5x" "adc_0/OUTx7x" 0.422993
cap "adc_0/GND" "8bit_sens_0/sens_amp_5/net1" 0.00878094
cap "adc_0/OUTx7x" "adc_0/GRAY_INx3x" 0.182126
cap "adc_0/OUTx5x" "adc_0/GRAY_INx7x" 14.0586
cap "adc_0/OUTx3x" "adc_0/GRAY_INx7x" 0.0232261
cap "adc_0/READ" "adc_0/GRAY_INx6x" 0.00898644
cap "adc_0/a_1100_n1450#" "adc_0/OUTx4x" 0.193556
cap "adc_0/BIAS1" "adc_0/OUTx4x" -0.922934
cap "adc_0/GRAY_INx5x" "adc_0/OUTx3x" 1.60864
cap "adc_0/READ" "adc_0/OUTx4x" 31.9477
cap "adc_0/GRAY_INx5x" "adc_0/OUTx5x" 0.0100576
cap "adc_0/OUTx5x" "adc_0/OUTx3x" -3.28179
cap "adc_0/GRAY_INx3x" "adc_0/OUTx3x" 0.0234924
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/OUTx6x" -0.0868261
cap "adc_0/READ" "adc_0/GRAY_INx1x" -0.0114114
cap "adc_0/OUTx5x" "adc_0/GRAY_INx3x" 0.00905904
cap "adc_0/BIAS2" "adc_0/OUTx4x" 0.208944
cap "adc_0/OUTx1x" "adc_0/GRAY_INx7x" 0.00858993
cap "adc_0/OUTx5x" "adc_0/OUTx1x" -0.118123
cap "8bit_sens_0/sens_amp_5/net1" "adc_0/VDD" 0.175788
cap "adc_0/OUTx3x" "adc_0/OUTx1x" -1.50771
cap "adc_0/GRAY_INx5x" "adc_0/OUTx1x" 0.0157817
cap "adc_0/READ" "adc_0/OUTx7x" 0.624011
cap "adc_0/OUTx7x" "adc_0/BIAS1" -0.206538
cap "adc_0/GRAY_INx3x" "adc_0/OUTx1x" 0.0201386
cap "adc_0/OUTx5x" "adc_0/a_1100_n1450#" 1.28942
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "adc_0/OUTx4x" 1.10244
cap "adc_0/READ" "adc_0/GRAY_INx7x" -1.24273
cap "adc_0/READ" "adc_0/OUTx5x" 40.5383
cap "adc_0/OUTx3x" "adc_0/a_1100_n1450#" 0.643658
cap "adc_0/OUTx3x" "adc_0/BIAS1" -0.385619
cap "adc_0/OUTx5x" "adc_0/BIAS1" 3.40646
cap "adc_0/BIAS2" "adc_0/OUTx7x" 0.207787
cap "adc_0/GRAY_INx5x" "adc_0/READ" -1.38451
cap "adc_0/READ" "adc_0/OUTx3x" 25.3042
cap "adc_0/GND" "8bit_sens_0/sens_amp_4/net1" 0.00371336
cap "adc_0/READ" "adc_0/GRAY_INx3x" -2.0571
cap "adc_0/BIAS2" "adc_0/OUTx5x" 0.951676
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/OUTx7x" 0.314181
cap "adc_0/READ" "adc_0/OUTx1x" 0.163117
cap "adc_0/BIAS2" "adc_0/OUTx3x" 0.948413
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/GRAY_INx7x" -1.33305
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/OUTx5x" 1.93238
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "adc_0/OUTx5x" 1.01317
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "adc_0/GRAY_INx5x" -0.366214
cap "8bit_sens_0/sens_amp_4/net1" "adc_0/VDD" 0.00706276
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/BIAS1" 0.04391
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "8bit_sens_0/sens_amp_6/GN" 0.0674098
cap "adc_0/GND" "8bit_sens_0/sens_amp_6/GN" 0.10187
cap "8bit_sens_0/sens_amp_5/GN" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.118608
cap "adc_0/GND" "8bit_sens_0/sens_amp_4/GN" 0.142041
cap "8bit_sens_0/sens_amp_5/GN" "adc_0/GND" 0.0673912
cap "adc_0/GND" "8bit_sens_0/sens_amp_3/net1" 0.00444633
cap "adc_0/a_1870_n1400#" "adc_0/OUTx0x" 0.0180222
cap "8bit_sens_0/sens_amp_6/GN" "adc_0/VDD" 0.0699164
cap "adc_0/OUTx0x" "adc_0/V_RAMP" -0.134294
cap "8bit_sens_0/sens_amp_5/GN" "adc_0/VDD" 0.0278411
cap "8bit_sens_0/sens_amp_4/GN" "adc_0/VDD" 2.8147e-05
cap "adc_0/OUTx2x" "adc_0/a_1870_n1400#" 0.784228
cap "adc_0/OUTx2x" "adc_0/V_RAMP" -0.134338
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "adc_0/OUTx0x" 0.0767923
cap "adc_0/GND" "adc_0/OUTx0x" 0.956117
cap "adc_0/GRAY_INx2x" "adc_0/GND" 0.355663
cap "adc_0/OUTx0x" "adc_0/VDD" 42.8299
cap "adc_0/GRAY_INx2x" "adc_0/VDD" 43.2998
cap "adc_0/OUTx2x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 5.34939
cap "adc_0/OUTx2x" "adc_0/GND" 7.98103
cap "8bit_sens_0/sens_amp_2/net1" "adc_0/GND" 0.23223
cap "adc_0/V_IN" "8bit_sens_0/sens_amp_3/GN" 0.00522501
cap "adc_0/GND" "8bit_sens_0/sens_amp_3/GN" 0.0729032
cap "adc_0/OUTx2x" "adc_0/VDD" 98.3794
cap "adc_0/OUTx2x" "adc_0/a_1720_n1450#" 0.756483
cap "adc_0/OUTx2x" "8bit_sens_0/sens_amp_5/OUT" 1.78456
cap "adc_0/GRAY_INx6x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -5.5826e-05
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/OUTx4x" 0.725899
cap "8bit_sens_0/sens_amp_6/net1" "adc_0/OUTx0x" 8.42612
cap "adc_0/OUTx7x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.716144
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/GRAY_INx7x" -0.871526
cap "adc_0/GRAY_INx5x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.23391
cap "adc_0/OUTx3x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.40563
cap "adc_0/OUTx5x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 4.76156
cap "adc_0/GRAY_INx3x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.850562
cap "adc_0/READ" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.591716
cap "adc_0/OUTx2x" "8bit_sens_0/sens_amp_5/net1" 18.0563
cap "adc_0/GRAY_INx4x" "8bit_sens_0/sens_amp_4/OUT" 0.0162939
cap "8bit_sens_0/sens_amp_6/GN" "adc_0/OUTx0x" 9.18392
cap "adc_0/GRAY_INx2x" "8bit_sens_0/sens_amp_6/GN" 0.454578
cap "adc_0/OUTx2x" "8bit_sens_0/sens_amp_5/GN" 19.2186
cap "adc_0/GRAY_INx5x" "8bit_sens_0/sens_amp_4/OUT" 0.0458033
cap "adc_0/GRAY_INx0x" "adc_0/OUTx0x" -0.0952982
cap "adc_0/GRAY_INx2x" "adc_0/OUTx0x" -0.00319922
cap "adc_0/OUTx2x" "adc_0/OUTx0x" -9.90548
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_sens_0/sens_amp_6/OUT" 0.0134536
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/V_RAMP" 0.0513499
cap "adc_0/OUTx6x" "adc_0/V_RAMP" 0.0744745
cap "adc_0/GND" "adc_0/GRAY_INx4x" 3.06306
cap "adc_0/OUTx4x" "adc_0/V_RAMP" -0.146449
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/GND" 6.89687
cap "adc_0/OUTx7x" "adc_0/V_RAMP" -0.00905909
cap "adc_0/GRAY_INx4x" "adc_0/VDD" 31.2316
cap "adc_0/OUTx5x" "adc_0/V_RAMP" -0.0183478
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/VDD" 55.0151
cap "adc_0/OUTx3x" "adc_0/V_RAMP" 0.325178
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "adc_0/GND" 1.24398
cap "adc_0/OUTx6x" "adc_0/GND" 1.65607
cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.266949
cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.00159236
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_4/OUT" 0.00017554
cap "adc_0/GND" "adc_0/GRAY_INx6x" 8.93649
cap "adc_0/GND" "adc_0/OUTx4x" 17.6465
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "adc_0/VDD" 61.0801
cap "adc_0/OUTx6x" "adc_0/VDD" 29.9881
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "adc_0/VDD" 59.0096
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "adc_0/VDD" 33.6348
cap "adc_0/OUTx7x" "adc_0/V_IN" 0.842577
cap "adc_0/GRAY_INx6x" "adc_0/VDD" 28.4936
cap "adc_0/OUTx3x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.909544
cap "adc_0/OUTx7x" "adc_0/GND" 31.3875
cap "adc_0/OUTx5x" "adc_0/V_IN" 1.78702
cap "adc_0/OUTx4x" "adc_0/VDD" 93.8213
cap "adc_0/GRAY_INx3x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" -0.931227
cap "adc_0/GND" "adc_0/GRAY_INx7x" 19.8029
cap "adc_0/OUTx5x" "adc_0/GND" 11.4116
cap "adc_0/OUTx4x" "adc_0/a_1000_n1450#" 0.014368
cap "adc_0/GND" "adc_0/OUTx3x" 2.77818
cap "adc_0/GRAY_INx5x" "adc_0/GND" 9.21274
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/V_RAMP" 0.0338576
cap "adc_0/GND" "adc_0/GRAY_INx3x" 1.91467
cap "adc_0/GND" "adc_0/OUTx1x" 0.0160753
cap "adc_0/OUTx7x" "adc_0/VDD" 17.395
cap "adc_0/OUTx5x" "adc_0/VDD" 34.2796
cap "adc_0/GRAY_INx7x" "adc_0/VDD" 41.927
cap "adc_0/OUTx3x" "adc_0/VDD" 69.4918
cap "adc_0/GRAY_INx5x" "adc_0/VDD" 36.5092
cap "adc_0/READ" "adc_0/GND" 6.80631
cap "adc_0/OUTx3x" "adc_0/a_1000_n1450#" 0.113861
cap "adc_0/GRAY_INx3x" "adc_0/VDD" 26.5269
cap "adc_0/OUTx5x" "adc_0/a_1000_n1450#" 1.36774
cap "adc_0/OUTx1x" "adc_0/VDD" 9.54271
cap "adc_0/OUTx3x" "adc_0/a_1720_n1450#" 1.03866
cap "adc_0/READ" "adc_0/VDD" 245.208
cap "adc_0/BIAS1" "adc_0/VDD" 3.88585
cap "adc_0/a_1100_n1450#" "adc_0/VDD" 2.23919
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "adc_0/GND" 0.708267
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/GND" 3.21855
cap "adc_0/BIAS2" "adc_0/VDD" 4.8223
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "adc_0/VDD" 7.59596
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/VDD" 7.51779
cap "8bit_sens_0/sens_amp_5/OUT" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.0131309
cap "adc_0/OUTx3x" "8bit_sens_0/sens_amp_5/OUT" 0.0650129
cap "adc_0/GRAY_INx3x" "8bit_sens_0/sens_amp_5/OUT" 0.0010894
cap "8bit_sens_0/sens_amp_6/net1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 1.83968
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "8bit_sens_0/sens_amp_5/net1" 2.65252
cap "adc_0/GRAY_INx4x" "8bit_sens_0/sens_amp_4/net1" 2.96639
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "8bit_sens_0/sens_amp_4/net1" 0.153801
cap "adc_0/OUTx3x" "8bit_sens_0/sens_amp_5/net1" 0.94854
cap "8bit_sens_0/sens_amp_3/OUT" "adc_0/GRAY_INx6x" 0.0118911
cap "8bit_sens_0/sens_amp_6/net1" "adc_0/OUTx1x" 1.56932
cap "8bit_sens_0/sens_amp_3/OUT" "adc_0/OUTx4x" 0.59734
cap "adc_0/GRAY_INx3x" "8bit_sens_0/sens_amp_5/net1" 1.49853
cap "8bit_sens_0/sens_amp_6/net1" "adc_0/READ" 3.65718
cap "adc_0/READ" "8bit_sens_0/sens_amp_5/net1" 1.02277
cap "8bit_sens_0/sens_amp_4/GN" "adc_0/GRAY_INx4x" 1.64367
cap "8bit_sens_0/sens_amp_3/OUT" "adc_0/OUTx5x" 0.0413391
cap "adc_0/OUTx5x" "8bit_sens_0/sens_amp_4/net1" 0.00775749
cap "adc_0/GRAY_INx5x" "8bit_sens_0/sens_amp_4/net1" 1.73986
cap "adc_0/BIAS2" "8bit_sens_0/sens_amp_5/net1" 0.000396814
cap "8bit_sens_0/sens_amp_6/GN" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 4.64724
cap "8bit_sens_0/sens_amp_2/OUT" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.0204091
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "8bit_sens_0/sens_amp_4/GN" 4.73773
cap "adc_0/READ" "8bit_sens_0/sens_amp_4/net1" 1.59082
cap "8bit_sens_0/sens_amp_5/GN" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 5.40068
cap "8bit_sens_0/sens_amp_3/net1" "adc_0/GRAY_INx6x" 0.315457
cap "8bit_sens_0/sens_amp_3/net1" "adc_0/OUTx4x" 4.15902
cap "8bit_sens_0/sens_amp_4/GN" "adc_0/OUTx4x" 1.89637
cap "adc_0/GRAY_INx4x" "adc_0/OUTx0x" -0.00443477
cap "8bit_sens_0/sens_amp_2/OUT" "adc_0/OUTx6x" 0.340759
cap "8bit_sens_0/sens_amp_3/net1" "adc_0/GRAY_INx7x" 0.045347
cap "adc_0/OUTx5x" "8bit_sens_0/sens_amp_4/GN" 0.522041
cap "8bit_sens_0/sens_amp_5/GN" "adc_0/GRAY_INx3x" 0.123248
cap "adc_0/OUTx5x" "8bit_sens_0/sens_amp_3/net1" 0.669192
cap "adc_0/GRAY_INx5x" "8bit_sens_0/sens_amp_4/GN" 6.58442
cap "8bit_sens_0/sens_amp_5/GN" "adc_0/OUTx3x" 11.33
cap "8bit_sens_0/sens_amp_6/GN" "adc_0/OUTx1x" 0.216952
cap "adc_0/READ" "8bit_sens_0/sens_amp_6/GN" 17.575
cap "8bit_sens_0/sens_amp_2/OUT" "adc_0/OUTx7x" 0.00466911
cap "adc_0/OUTx6x" "adc_0/OUTx0x" -7.28584e-16
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "adc_0/OUTx0x" 0.161983
cap "8bit_sens_0/sens_amp_5/GN" "adc_0/READ" 2.65106
cap "adc_0/OUTx2x" "adc_0/GRAY_INx4x" -0.00518706
cap "adc_0/READ" "8bit_sens_0/sens_amp_3/net1" 5.25867
cap "8bit_sens_0/sens_amp_4/GN" "adc_0/BIAS1" 0.447368
cap "adc_0/READ" "8bit_sens_0/sens_amp_4/GN" 3.72963
cap "adc_0/BIAS2" "8bit_sens_0/sens_amp_6/GN" 0.165584
cap "adc_0/OUTx4x" "adc_0/OUTx0x" 0.152769
cap "adc_0/GRAY_INx6x" "adc_0/OUTx0x" -0.000555492
cap "adc_0/GRAY_INx1x" "adc_0/OUTx0x" -0.0216959
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "8bit_sens_0/sens_amp_3/GN" 0.153156
cap "8bit_sens_0/sens_amp_2/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 4.30704
cap "8bit_sens_0/sens_amp_5/GN" "adc_0/BIAS2" 0.35808
cap "adc_0/GRAY_INx2x" "adc_0/GRAY_INx1x" -0.00306463
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "8bit_sens_0/sens_amp_4/GN" 0.683638
cap "adc_0/OUTx7x" "adc_0/OUTx0x" -0.165415
cap "adc_0/OUTx2x" "adc_0/OUTx6x" 8.88178e-16
cap "adc_0/OUTx5x" "adc_0/OUTx0x" -0.182552
cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 4.2083
cap "adc_0/OUTx2x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 7.90201
cap "adc_0/OUTx3x" "adc_0/OUTx0x" -0.171818
cap "adc_0/OUTx2x" "adc_0/GRAY_INx6x" -0.000853634
cap "adc_0/GRAY_INx2x" "adc_0/OUTx3x" -7.09593
cap "8bit_sens_0/sens_amp_2/net1" "adc_0/OUTx6x" 7.90944
cap "adc_0/OUTx1x" "adc_0/OUTx0x" 4.34163
cap "adc_0/OUTx2x" "adc_0/OUTx4x" -9.94157
cap "adc_0/GRAY_INx0x" "adc_0/READ" -0.0807173
cap "adc_0/GRAY_INx2x" "adc_0/OUTx1x" 0.203364
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/VDD" 60.6555
cap "adc_0/GRAY_INx6x" "8bit_sens_0/sens_amp_3/GN" 6.09883
cap "adc_0/OUTx4x" "8bit_sens_0/sens_amp_3/GN" 2.91383
cap "adc_0/READ" "adc_0/OUTx0x" 2.54988
cap "adc_0/BIAS1" "adc_0/OUTx0x" -0.400078
cap "adc_0/OUTx2x" "adc_0/OUTx7x" -0.522468
cap "adc_0/GRAY_INx2x" "adc_0/READ" -3.47051
cap "adc_0/OUTx2x" "adc_0/OUTx5x" -0.232732
cap "adc_0/BIAS2" "adc_0/OUTx0x" 0.0661293
cap "adc_0/OUTx2x" "adc_0/OUTx3x" 23.7209
cap "adc_0/OUTx7x" "8bit_sens_0/sens_amp_3/GN" 0.00390518
cap "8bit_sens_0/sens_amp_2/net1" "adc_0/OUTx7x" 0.609511
cap "8bit_sens_0/sens_amp_2/net1" "adc_0/OUTx5x" 0.0389332
cap "adc_0/OUTx2x" "adc_0/GRAY_INx3x" 56.5709
cap "8bit_sens_0/sens_amp_3/GN" "adc_0/GRAY_INx7x" 3.25119
cap "adc_0/OUTx5x" "8bit_sens_0/sens_amp_3/GN" 1.20005
cap "adc_0/OUTx2x" "adc_0/OUTx1x" -2.9493
cap "adc_0/OUTx2x" "adc_0/READ" 37.8257
cap "adc_0/OUTx2x" "adc_0/BIAS1" -2.47224
cap "8bit_sens_0/sens_amp_2/net1" "adc_0/READ" 4.37209
cap "adc_0/READ" "8bit_sens_0/sens_amp_3/GN" 11.2252
cap "adc_0/OUTx2x" "adc_0/BIAS2" 3.59631
cap "8bit_sens_0/sens_amp_2/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.15041
cap "8bit_sens_0/sens_amp_6/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.00884229
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_5/net1" 0.0113099
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_4/net1" 1.05086
cap "8bit_sens_0/sens_amp_6/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.138556
cap "8bit_sens_0/sens_amp_5/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.128619
cap "8bit_sens_0/sens_amp_4/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.352258
cap "8bit_sens_0/sens_amp_3/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.0201185
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/OUTx0x" 0.295252
cap "adc_0/OUTx2x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 2.6445
cap "8bit_sens_0/sens_amp_2/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.0236306
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_3/GN" 1.52549
cap "adc_0/a_1870_n1400#" "adc_0/VDD" 0.32181
cap "adc_0/VDD" "adc_0/V_RAMP" 0.12972
cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.168165
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "adc_0/GND" 0.00251029
cap "8bit_sens_0/sens_amp_7/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 9.04343
cap "adc_0/GRAY_INx1x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" -0.437982
cap "8bit_sens_0/sens_amp_7/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.0810341
cap "adc_0/GRAY_INx1x" "8bit_sens_0/sens_amp_7/GN" 1.15023
cap "adc_0/GRAY_INx1x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" -1.13467
cap "adc_0/VDD" "8bit_sens_0/sens_amp_4/GN" 0.00136439
cap "8bit_sens_0/sens_amp_5/net1" "adc_0/VDD" 0.888871
cap "8bit_sens_0/sens_amp_4/net1" "adc_0/VDD" 0.110949
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_sens_0/sens_amp_7/GN" 0.0675601
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "adc_0/VDD" 0.848429
cap "8bit_sens_0/sens_amp_5/GN" "adc_0/VDD" 0.807124
cap "adc_0/VDD" "8bit_sens_0/sens_amp_6/net1" 2.24439
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_6/net1" 0.0032509
cap "8bit_sens_0/sens_amp_6/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 1.08478
cap "8bit_sens_0/sens_amp_6/net1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.00342536
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_sens_0/sens_amp_6/net1" 0.527436
cap "adc_0/GND" "adc_0/OUTx0x" 0.581515
cap "adc_0/GND" "adc_0/OUTx1x" 0.123497
cap "adc_0/OUTx2x" "adc_0/OUTx0x" -0.465476
cap "adc_0/OUTx2x" "adc_0/OUTx1x" -2.93762
cap "adc_0/GRAY_INx0x" "adc_0/OUTx0x" 7.84213
cap "adc_0/GRAY_INx0x" "adc_0/OUTx1x" -3.20485
cap "adc_0/OUTx0x" "adc_0/OUTx1x" 0.0988289
cap "adc_0/GND" "adc_0/VDD" 0.224545
cap "adc_0/BIAS2" "adc_0/OUTx0x" 0.677825
cap "adc_0/OUTx2x" "adc_0/VDD" 0.387613
cap "adc_0/BIAS2" "adc_0/OUTx1x" 0.040046
cap "adc_0/BIAS1" "adc_0/OUTx0x" -0.631704
cap "adc_0/BIAS1" "adc_0/OUTx1x" -0.12899
cap "adc_0/GRAY_INx0x" "adc_0/VDD" 75.1741
cap "adc_0/OUTx0x" "adc_0/VDD" 157.842
cap "adc_0/VDD" "adc_0/OUTx1x" 24.4041
cap "adc_0/a_1870_n1400#" "adc_0/OUTx0x" 0.395936
cap "adc_0/OUTx0x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 13.6045
cap "adc_0/OUTx1x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.108829
cap "adc_0/a_1870_n1400#" "adc_0/OUTx1x" 0.184272
cap "adc_0/V_RAMP" "adc_0/OUTx1x" -0.0432902
cap "adc_0/BIAS2" "adc_0/VDD" 0.568848
cap "adc_0/OUTx3x" "adc_0/OUTx1x" -0.251285
cap "adc_0/OUTx0x" "8bit_sens_0/sens_amp_6/GN" 1.0749
cap "adc_0/OUTx1x" "adc_0/GRAY_INx5x" -0.00186608
cap "8bit_sens_0/sens_amp_6/GN" "adc_0/OUTx1x" 0.118384
cap "adc_0/OUTx5x" "adc_0/OUTx1x" -0.118123
cap "adc_0/GRAY_INx0x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.0107875
cap "adc_0/OUTx0x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 6.84134
cap "adc_0/GRAY_INx3x" "adc_0/OUTx1x" -0.00282864
cap "adc_0/a_1870_n1400#" "adc_0/VDD" 0.167769
cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 27.1321
cap "adc_0/OUTx1x" "adc_0/GRAY_INx7x" -0.000568322
cap "adc_0/OUTx1x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 11.3443
cap "adc_0/GRAY_INx1x" "adc_0/GRAY_INx0x" 0.00047027
cap "adc_0/OUTx3x" "adc_0/VDD" 0.126884
cap "adc_0/OUTx1x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.00257041
cap "adc_0/OUTx0x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 2.28298
cap "adc_0/GRAY_INx1x" "adc_0/OUTx1x" -0.0484037
cap "adc_0/GRAY_INx1x" "adc_0/OUTx0x" 60.6016
cap "adc_0/OUTx4x" "adc_0/OUTx0x" 0.0575966
cap "adc_0/OUTx4x" "adc_0/OUTx1x" -0.0759572
cap "adc_0/OUTx6x" "adc_0/OUTx1x" -0.020233
cap "adc_0/GRAY_INx0x" "8bit_sens_0/sens_amp_7/GN" 8.14737
cap "8bit_sens_0/sens_amp_7/net1" "adc_0/OUTx0x" 15.5606
cap "8bit_sens_0/sens_amp_6/GN" "adc_0/VDD" 1.78378
cap "adc_0/GRAY_INx0x" "8bit_sens_0/sens_amp_7/net1" 0.412847
cap "adc_0/OUTx0x" "8bit_sens_0/sens_amp_7/GN" 16.3165
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "adc_0/OUTx0x" 2.94733
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "adc_0/OUTx1x" 1.13133
cap "adc_0/GRAY_INx3x" "adc_0/VDD" 0.745508
cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 59.4963
cap "adc_0/OUTx1x" "adc_0/GRAY_INx2x" 0.203364
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "adc_0/VDD" 0.202701
cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 7.04787
cap "adc_0/GRAY_INx1x" "adc_0/VDD" 61.1837
cap "adc_0/VDD" "8bit_sens_0/sens_amp_7/GN" 3.4502
cap "8bit_sens_0/sens_amp_7/net1" "adc_0/VDD" 17.927
cap "adc_0/GRAY_INx1x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.434238
cap "adc_0/GND" "8bit_sens_0/sens_amp_6/net1" 0.000928339
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "adc_0/VDD" 30.0801
cap "8bit_sens_0/sens_amp_7/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.360981
cap "8bit_sens_0/sens_amp_6/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.545507
cap "8bit_sens_0/sens_amp_7/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.00627251
cap "adc_0/GRAY_INx1x" "adc_0/OUTx3x" 0.0199684
cap "adc_0/VDD" "adc_0/GRAY_INx2x" 1.68103
cap "adc_0/GRAY_INx1x" "adc_0/OUTx5x" 0.00721156
cap "adc_0/OUTx0x" "8bit_sens_0/sens_amp_7/OUT" 1.51098
cap "adc_0/OUTx7x" "adc_0/GRAY_INx1x" 0.0224807
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_sens_0/sens_amp_6/GN" 0.173762
cap "adc_0/OUTx0x" "8bit_sens_0/sens_amp_6/net1" 1.62315
cap "adc_0/OUTx1x" "8bit_sens_0/sens_amp_6/net1" 0.707811
cap "adc_0/GRAY_INx1x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.155666
cap "io_analog[2]" "adc_0/GND" 0.00691822
cap "adc_0/GND" "m2_33290_207480#" 0.0254068
cap "adc_0/BIAS2" "adc_0/GRAY_INx5x" 0.692629
cap "adc_0/BIAS2" "adc_0/OUTx3x" 0.353329
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/BIAS1" 0.0639255
cap "adc_0/GND" "adc_0/V_RAMP" 1.43581
cap "adc_0/BIAS2" "adc_0/BIAS1" 9.18833
cap "adc_0/BIAS2" "adc_0/OUTx2x" 0.528351
cap "adc_0/GND" "8bit_sens_0/sens_amp_2/GN" 0.0103339
cap "adc_0/BIAS2" "adc_0/OUTx0x" 0.171096
cap "adc_0/GRAY_INx6x" "adc_0/GND" 5.21166
cap "adc_0/BIAS2" "adc_0/OUTx6x" 11.6304
cap "adc_0/BIAS1" "adc_0/OUTx6x" 23.7114
cap "adc_0/V_IN" "adc_0/GND" 30.8154
cap "adc_0/GND" "adc_0/GRAY_INx4x" 3.35427
cap "adc_0/OUTx4x" "adc_0/GND" 4.8424
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/V_RAMP" 0.0376022
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "adc_0/GND" 1.35734
cap "adc_0/BIAS2" "adc_0/GRAY_INx2x" 0.323507
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_sens_0/sens_amp_2/GN" 0.0255192
cap "adc_0/OUTx5x" "adc_0/GND" 4.22452
cap "adc_0/VDD" "adc_0/V_RAMP" -0.105008
cap "adc_0/BIAS2" "adc_0/READ" 0.16815
cap "adc_0/BIAS1" "adc_0/READ" 7.47213
cap "adc_0/VDD" "adc_0/V_IN" 0.622585
cap "8bit_sens_0/VDD" "adc_0/V_IN" 0.11189
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/V_RAMP" 0.00378144
cap "adc_0/BIAS2" "adc_0/V_RAMP" 3.94799
cap "adc_0/OUTx6x" "adc_0/V_RAMP" 22.084
cap "adc_0/BIAS2" "adc_0/OUTx4x" 0.782367
cap "adc_0/BIAS2" "adc_0/V_IN" 14.8936
cap "adc_0/BIAS2" "adc_0/GRAY_INx6x" 0.889568
cap "adc_0/BIAS2" "adc_0/GRAY_INx4x" 0.673636
cap "adc_0/V_IN" "adc_0/BIAS1" 1.52674
cap "adc_0/V_IN" "adc_0/OUTx6x" -0.00316111
cap "adc_0/BIAS2" "adc_0/OUTx5x" 0.585344
cap "adc_0/READ" "adc_0/V_RAMP" 0.50167
cap "vccd1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.485072
cap "adc_0/OUTx7x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.350313
cap "adc_0/V_IN" "adc_0/V_RAMP" 0.240334
cap "adc_0/V_IN" "8bit_sens_0/sens_amp_2/GN" 0.000283854
cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 69.1744
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "adc_0/GND" 0.118527
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.0118577
cap "vccd1" "adc_0/GND" -0.249633
cap "adc_0/GRAY_INx7x" "adc_0/GND" 14.9717
cap "adc_0/OUTx7x" "adc_0/GND" 36.5851
cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.897105
cap "vccd1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.072571
cap "8bit_sens_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 3.18713
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/OUTx7x" 0.0257985
cap "adc_0/OUTx1x" "adc_0/GND" 0.0679257
cap "adc_0/GRAY_INx3x" "adc_0/GND" 2.80485
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/GND" 16.7483
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.018809
cap "adc_0/VDD" "adc_0/GND" -2.08868
cap "adc_0/BIAS1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 9.4509
cap "adc_0/BIAS2" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.127801
cap "adc_0/a_1870_n1400#" "adc_0/GND" 0.132542
cap "adc_0/a_1720_n1450#" "adc_0/GND" 0.977945
cap "vccd1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.000453928
cap "8bit_sens_0/sens_amp_2/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.0582996
cap "adc_0/OUTx6x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.188055
cap "8bit_sens_0/VDD" "adc_0/GND" 0.831031
cap "adc_0/a_1000_n1450#" "adc_0/GND" 2.03303
cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.100071
cap "adc_0/BIAS2" "vccd1" 0.691863
cap "adc_0/BIAS2" "adc_0/GRAY_INx7x" 0.879863
cap "vccd1" "adc_0/OUTx6x" 7.7258
cap "adc_0/a_1100_n1450#" "adc_0/GND" 4.44552
cap "8bit_sens_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.943646
cap "adc_0/BIAS2" "adc_0/OUTx7x" 0.750125
cap "adc_0/OUTx7x" "adc_0/BIAS1" 0.905213
cap "adc_0/READ" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.0785371
cap "vccd1" "adc_0/READ" 0.277243
cap "adc_0/OUTx1x" "adc_0/BIAS2" 0.0874398
cap "adc_0/BIAS2" "adc_0/GRAY_INx3x" 0.38098
cap "adc_0/GRAY_INx5x" "adc_0/GND" 6.17564
cap "adc_0/OUTx3x" "adc_0/GND" 2.30368
cap "adc_0/BIAS2" "adc_0/GND" 3.21007
cap "adc_0/BIAS1" "adc_0/GND" 188.732
cap "adc_0/OUTx2x" "adc_0/GND" 2.94139
cap "8bit_sens_0/sens_amp_2/net1" "adc_0/GND" 0.000620416
cap "adc_0/GND" "adc_0/OUTx6x" 200.75
cap "adc_0/OUTx0x" "adc_0/GND" 0.503927
cap "adc_0/BIAS2" "adc_0/GRAY_INx1x" 0.00711746
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/BIAS1" 0.184857
cap "adc_0/GRAY_INx2x" "adc_0/GND" 1.27402
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/V_RAMP" 0.170305
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/OUTx6x" 0.0167998
cap "8bit_sens_0/sens_amp_2/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.02792
cap "adc_0/BIAS2" "adc_0/VDD" 7.03064
cap "adc_0/VDD" "adc_0/BIAS1" -0.101831
cap "adc_0/BIAS2" "adc_0/a_1720_n1450#" 3.69327
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_2/GN" 0.394808
cap "8bit_sens_0/VDD" "adc_0/BIAS2" 0.189809
cap "adc_0/READ" "adc_0/GND" 13.5743
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "adc_0/GND" 2.51318
cap "adc_0/VDD" "adc_0/OUTx6x" 1.08208
cap "adc_0/BIAS2" "adc_0/a_1870_n1400#" 2.60796
cap "adc_0/V_IN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.691028
cap "adc_0/BIAS2" "adc_0/a_1000_n1450#" 6.66027
cap "adc_0/BIAS2" "adc_0/a_1100_n1450#" 5.6902
cap "vccd1" "adc_0/V_IN" 0.383251
cap "adc_0/VDD" "adc_0/READ" 0.157368
cap "adc_0/V_IN" "adc_0/OUTx7x" 0.00795876
cap "adc_0/BIAS2" "adc_0/a_2260_n1450#" 0.71284
cap "adc_0/OUTx6x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -2.46916
cap "adc_0/V_RAMP" "adc_0/OUTx3x" -1.22185
cap "adc_0/a_1720_n1450#" "adc_0/OUTx6x" -0.0039073
cap "8bit_sens_0/sens_amp_4/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.521457
cap "adc_0/V_RAMP" "adc_0/GRAY_INx7x" -1.4115
cap "adc_0/GRAY_INx2x" "adc_0/a_1870_n1400#" -0.258898
cap "adc_0/OUTx3x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 3.83413
cap "adc_0/GRAY_INx7x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 2.78091
cap "adc_0/a_1720_n1450#" "adc_0/OUTx3x" 0.0324566
cap "adc_0/GRAY_INx2x" "adc_0/V_RAMP" -2.59343
cap "adc_0/GRAY_INx2x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 3.01736
cap "adc_0/GRAY_INx2x" "adc_0/a_1720_n1450#" -0.374624
cap "adc_0/VDD" "adc_0/OUTx1x" 4.43665
cap "adc_0/V_RAMP" "adc_0/a_1870_n1400#" -0.868431
cap "adc_0/V_RAMP" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.774957
cap "adc_0/GRAY_INx6x" "adc_0/OUTx0x" -0.00564446
cap "adc_0/GND" "adc_0/OUTx0x" 0.328734
cap "adc_0/V_RAMP" "adc_0/a_1720_n1450#" -2.34235
cap "adc_0/GRAY_INx0x" "adc_0/OUTx0x" -0.00309223
cap "adc_0/OUTx7x" "adc_0/OUTx0x" -0.00287057
cap "8bit_sens_0/sens_amp_6/net1" "adc_0/GND" 0.0116736
cap "adc_0/BIAS1" "adc_0/OUTx0x" -0.076852
cap "adc_0/VDD" "adc_0/GRAY_INx1x" -0.000655092
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "adc_0/OUTx0x" 0.237223
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.53528
cap "adc_0/BIAS2" "adc_0/OUTx0x" 0.098673
cap "adc_0/GRAY_INx4x" "adc_0/OUTx0x" -0.0090045
cap "8bit_sens_0/sens_amp_6/net1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.0797386
cap "adc_0/GND" "8bit_sens_0/sens_amp_4/net1" 0.0238539
cap "adc_0/GND" "8bit_sens_0/sens_amp_2/net1" 0.00864429
cap "adc_0/OUTx3x" "adc_0/OUTx0x" -0.00585898
cap "adc_0/GRAY_INx2x" "adc_0/OUTx0x" -0.0102886
cap "adc_0/a_1870_n1400#" "adc_0/OUTx0x" 0.0347412
cap "adc_0/VDD" "adc_0/a_1000_n1450#" 67.3169
cap "adc_0/V_RAMP" "adc_0/OUTx0x" -1.81075
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/OUTx0x" 3.05952
cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 13.7358
cap "8bit_sens_0/sens_amp_6/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.322553
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_sens_0/sens_amp_2/net1" 0.481951
cap "adc_0/VDD" "adc_0/OUTx5x" 21.2422
cap "8bit_sens_0/sens_amp_4/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.832171
cap "adc_0/VDD" "adc_0/a_1100_n1450#" 23.3587
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_2/net1" 0.779593
cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.0932343
cap "adc_0/VDD" "adc_0/GRAY_INx6x" -5.94381
cap "adc_0/VDD" "adc_0/GRAY_INx3x" 1.52812
cap "adc_0/VDD" "adc_0/GND" 34.8106
cap "adc_0/OUTx1x" "adc_0/GRAY_INx3x" 0.0514982
cap "adc_0/GND" "adc_0/OUTx1x" 0.00175627
cap "adc_0/GRAY_INx1x" "adc_0/OUTx5x" -0.00217775
cap "adc_0/OUTx4x" "adc_0/VDD" 28.2314
cap "adc_0/OUTx4x" "adc_0/OUTx1x" -0.00278335
cap "adc_0/VDD" "adc_0/OUTx7x" 38.4304
cap "adc_0/VDD" "adc_0/GRAY_INx0x" -0.000468515
cap "adc_0/OUTx7x" "adc_0/OUTx1x" -0.383333
cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 12.0239
cap "adc_0/VDD" "adc_0/BIAS1" -1.63654
cap "adc_0/OUTx1x" "adc_0/BIAS1" 0.117885
cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.0927804
cap "adc_0/VDD" "adc_0/OUTx2x" 35.095
cap "adc_0/OUTx2x" "adc_0/OUTx1x" -0.00404213
cap "adc_0/VDD" "adc_0/GRAY_INx5x" -4.67059
cap "adc_0/GRAY_INx5x" "adc_0/OUTx1x" 0.0397904
cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 8.42068
cap "adc_0/VDD" "adc_0/BIAS2" 27.9299
cap "adc_0/OUTx1x" "adc_0/BIAS2" 0.0461409
cap "adc_0/VDD" "adc_0/GRAY_INx4x" 3.58556
cap "adc_0/GRAY_INx1x" "adc_0/GRAY_INx6x" -0.0388247
cap "adc_0/GRAY_INx1x" "adc_0/GRAY_INx3x" -4.72
cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 10.1777
cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 0.0932343
cap "adc_0/VDD" "adc_0/V_IN" 20.226
cap "adc_0/READ" "adc_0/VDD" 2.66143
cap "adc_0/GRAY_INx1x" "adc_0/OUTx7x" 0.0120092
cap "adc_0/a_1000_n1450#" "adc_0/OUTx5x" 0.0876459
cap "adc_0/VDD" "adc_0/OUTx6x" 26.5805
cap "adc_0/OUTx6x" "adc_0/OUTx1x" -0.00239261
cap "adc_0/VDD" "adc_0/OUTx3x" 20.9427
cap "adc_0/VDD" "adc_0/GRAY_INx7x" 6.37109
cap "adc_0/GRAY_INx7x" "adc_0/OUTx1x" -0.045179
cap "adc_0/VDD" "adc_0/GRAY_INx2x" 2.98684
cap "adc_0/GRAY_INx2x" "adc_0/OUTx1x" 2.125
cap "adc_0/GRAY_INx1x" "adc_0/BIAS2" -0.000416707
cap "adc_0/VDD" "adc_0/a_1870_n1400#" 15.8
cap "adc_0/GRAY_INx1x" "adc_0/GRAY_INx4x" -0.0747682
cap "adc_0/VDD" "adc_0/V_RAMP" -73.6423
cap "adc_0/V_RAMP" "adc_0/OUTx1x" -0.33173
cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 122.325
cap "adc_0/OUTx1x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.412947
cap "adc_0/VDD" "adc_0/a_1720_n1450#" 20.7118
cap "adc_0/GND" "adc_0/a_1000_n1450#" 0.621255
cap "adc_0/a_1000_n1450#" "adc_0/GRAY_INx6x" -0.506943
cap "adc_0/OUTx4x" "adc_0/a_1000_n1450#" 0.029255
cap "adc_0/GRAY_INx3x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" -0.0372119
cap "adc_0/GRAY_INx1x" "adc_0/OUTx3x" -0.00316169
cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 1.64121
cap "adc_0/GRAY_INx2x" "adc_0/GRAY_INx1x" -0.119647
cap "adc_0/a_1100_n1450#" "adc_0/OUTx5x" 3.77589
cap "adc_0/a_1000_n1450#" "adc_0/BIAS1" 3.91615
cap "8bit_sens_0/sens_amp_5/GN" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.42532
cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.0353042
cap "8bit_sens_0/sens_amp_5/net1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.134469
cap "adc_0/OUTx2x" "adc_0/a_1000_n1450#" 0.00697881
cap "adc_0/GRAY_INx5x" "adc_0/a_1000_n1450#" 0.4578
cap "adc_0/a_1000_n1450#" "adc_0/BIAS2" 5.14751
cap "adc_0/a_1000_n1450#" "adc_0/GRAY_INx4x" -0.493464
cap "adc_0/OUTx2x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.498606
cap "adc_0/OUTx5x" "adc_0/GRAY_INx3x" -0.0047554
cap "adc_0/OUTx5x" "adc_0/GRAY_INx6x" 0.431919
cap "adc_0/GND" "adc_0/OUTx5x" 12.8379
cap "adc_0/OUTx4x" "adc_0/OUTx5x" -0.00694119
cap "adc_0/OUTx6x" "adc_0/a_1000_n1450#" -0.0163236
cap "adc_0/a_1100_n1450#" "adc_0/GRAY_INx6x" 1.54794
cap "adc_0/GND" "adc_0/a_1100_n1450#" 5.26434
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "adc_0/OUTx5x" 0.37756
cap "adc_0/OUTx3x" "adc_0/a_1000_n1450#" 0.0255662
cap "adc_0/GRAY_INx7x" "adc_0/a_1000_n1450#" 0.803113
cap "adc_0/OUTx4x" "adc_0/a_1100_n1450#" 4.09496
cap "adc_0/OUTx5x" "adc_0/BIAS1" 0.670808
cap "adc_0/a_1100_n1450#" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 3.0484
cap "adc_0/OUTx3x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.224953
cap "adc_0/OUTx2x" "adc_0/OUTx5x" -0.00585898
cap "adc_0/GRAY_INx5x" "adc_0/OUTx5x" -0.00536871
cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.638007
cap "adc_0/GRAY_INx3x" "adc_0/GRAY_INx6x" -0.170256
cap "adc_0/OUTx5x" "adc_0/BIAS2" 1.31886
cap "adc_0/VDD" "adc_0/OUTx0x" 40.1956
cap "adc_0/GND" "adc_0/GRAY_INx3x" 6.31398
cap "adc_0/GND" "adc_0/GRAY_INx6x" 11.3685
cap "adc_0/OUTx1x" "adc_0/OUTx0x" 0.0150278
cap "adc_0/a_1100_n1450#" "adc_0/BIAS1" 7.07985
cap "adc_0/V_RAMP" "adc_0/a_1000_n1450#" -5.2222
cap "8bit_sens_0/sens_amp_6/GN" "adc_0/GND" 0.0421513
cap "adc_0/OUTx5x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.690966
cap "adc_0/OUTx4x" "adc_0/GRAY_INx6x" -0.00961801
cap "adc_0/OUTx4x" "adc_0/GND" 22.3976
cap "adc_0/a_1100_n1450#" "adc_0/GRAY_INx5x" 4.69768
cap "adc_0/GRAY_INx0x" "adc_0/GRAY_INx3x" -0.173544
cap "adc_0/OUTx7x" "adc_0/GRAY_INx3x" 0.11361
cap "adc_0/a_1100_n1450#" "adc_0/BIAS2" 0.578953
cap "adc_0/OUTx7x" "adc_0/GRAY_INx6x" 12.576
cap "adc_0/GND" "adc_0/OUTx7x" 55.431
cap "adc_0/V_IN" "adc_0/OUTx5x" 1.35219
cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 5.39888
cap "adc_0/a_1100_n1450#" "adc_0/GRAY_INx4x" 2.40226
cap "8bit_sens_0/sens_amp_3/GN" "adc_0/GRAY_INx6x" 0.00628184
cap "adc_0/GND" "8bit_sens_0/sens_amp_5/GN" 0.012717
cap "adc_0/GND" "8bit_sens_0/sens_amp_3/GN" 0.012717
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.14728
cap "adc_0/GND" "8bit_sens_0/sens_amp_5/net1" 0.0505881
cap "adc_0/a_1100_n1450#" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 2.29299
cap "adc_0/OUTx4x" "adc_0/GRAY_INx0x" -0.00144721
cap "adc_0/OUTx6x" "adc_0/OUTx5x" -0.010886
cap "adc_0/OUTx4x" "adc_0/OUTx7x" -0.00676338
cap "adc_0/OUTx4x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 1.3797
cap "adc_0/GND" "adc_0/BIAS1" 42.9459
cap "adc_0/GRAY_INx6x" "adc_0/BIAS1" -0.0321626
cap "adc_0/GRAY_INx3x" "adc_0/BIAS1" -0.738573
cap "8bit_sens_0/sens_amp_3/net1" "adc_0/GRAY_INx6x" 0.0299014
cap "adc_0/GND" "8bit_sens_0/sens_amp_3/net1" 0.00940778
cap "adc_0/GRAY_INx7x" "adc_0/OUTx5x" -0.00726852
cap "adc_0/READ" "adc_0/a_1100_n1450#" 4.37015
cap "adc_0/OUTx2x" "adc_0/GRAY_INx6x" -0.00838425
cap "adc_0/OUTx2x" "adc_0/GND" 9.38513
cap "adc_0/GRAY_INx5x" "adc_0/GRAY_INx3x" -9.44
cap "adc_0/OUTx4x" "adc_0/BIAS1" -0.156277
cap "adc_0/GRAY_INx5x" "adc_0/GRAY_INx6x" -0.32439
cap "adc_0/GRAY_INx3x" "adc_0/BIAS2" 0.708909
cap "adc_0/GND" "adc_0/GRAY_INx5x" 18.3809
cap "adc_0/GND" "adc_0/BIAS2" 5.08116
cap "adc_0/GRAY_INx6x" "adc_0/BIAS2" 2.15791
cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.0306163
cap "adc_0/OUTx7x" "adc_0/BIAS1" 14.3381
cap "adc_0/GRAY_INx4x" "adc_0/GRAY_INx3x" -0.221482
cap "adc_0/GRAY_INx4x" "adc_0/GRAY_INx6x" -4.35655
cap "adc_0/a_1100_n1450#" "adc_0/OUTx3x" 0.42129
cap "adc_0/GND" "adc_0/GRAY_INx4x" 4.91741
cap "8bit_sens_0/sens_amp_6/GN" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.100669
cap "8bit_sens_0/sens_amp_6/GN" "adc_0/BIAS2" 0.165584
cap "adc_0/a_1100_n1450#" "adc_0/GRAY_INx7x" 0.979723
cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 2.09615
cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 9.77621
cap "adc_0/OUTx2x" "adc_0/GRAY_INx0x" -0.00249368
cap "adc_0/OUTx2x" "adc_0/OUTx7x" -0.00529229
cap "adc_0/OUTx4x" "adc_0/BIAS2" 1.43092
cap "adc_0/GRAY_INx5x" "adc_0/GRAY_INx0x" -0.119988
cap "adc_0/OUTx7x" "adc_0/GRAY_INx5x" 0.163627
cap "adc_0/OUTx4x" "adc_0/GRAY_INx4x" -0.00656107
cap "adc_0/OUTx7x" "adc_0/BIAS2" 8.42633
cap "adc_0/GRAY_INx0x" "adc_0/BIAS2" -0.000422549
cap "adc_0/GRAY_INx5x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" -0.0015652
cap "adc_0/V_RAMP" "adc_0/OUTx5x" -0.334144
cap "adc_0/V_IN" "adc_0/GRAY_INx6x" 1.67684
cap "adc_0/V_IN" "adc_0/GND" 12.3007
cap "adc_0/BIAS1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.887439
cap "adc_0/READ" "adc_0/GRAY_INx6x" 0.0427375
cap "8bit_sens_0/sens_amp_5/GN" "adc_0/BIAS2" 0.339041
cap "adc_0/OUTx5x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 5.3114
cap "adc_0/READ" "adc_0/GND" 1.81993
cap "8bit_sens_0/sens_amp_5/net1" "adc_0/BIAS2" 0.00135237
cap "adc_0/OUTx7x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" -0.35102
cap "adc_0/GND" "adc_0/OUTx6x" -0.0988091
cap "adc_0/OUTx6x" "adc_0/GRAY_INx6x" 0.0718316
cap "adc_0/OUTx2x" "adc_0/BIAS1" -2.97995
cap "adc_0/GRAY_INx5x" "adc_0/BIAS1" 0.142296
cap "adc_0/BIAS2" "adc_0/BIAS1" 7.02243
cap "adc_0/GND" "8bit_sens_0/sens_amp_4/GN" 0.276916
cap "adc_0/OUTx3x" "adc_0/GRAY_INx3x" -0.00536871
cap "adc_0/V_IN" "adc_0/OUTx7x" 1.95822
cap "adc_0/GND" "adc_0/OUTx3x" 3.24878
cap "adc_0/READ" "adc_0/OUTx7x" -1.22611
cap "adc_0/GRAY_INx4x" "adc_0/BIAS1" 0.205244
cap "adc_0/GRAY_INx7x" "adc_0/GRAY_INx6x" -0.456465
cap "adc_0/a_1100_n1450#" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 5.3603
cap "adc_0/GND" "adc_0/GRAY_INx7x" 32.8055
cap "adc_0/V_IN" "8bit_sens_0/sens_amp_3/GN" 0.0093189
cap "adc_0/OUTx2x" "adc_0/BIAS2" 1.03207
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/BIAS1" 1.75346
cap "adc_0/OUTx6x" "adc_0/GRAY_INx0x" 0.00185566
cap "adc_0/OUTx7x" "adc_0/OUTx6x" -2.31355
cap "adc_0/GRAY_INx2x" "adc_0/GRAY_INx3x" -0.247084
cap "adc_0/GRAY_INx5x" "adc_0/BIAS2" 1.10186
cap "adc_0/OUTx2x" "adc_0/GRAY_INx4x" -0.0105103
cap "adc_0/GRAY_INx2x" "adc_0/GND" 2.71802
cap "adc_0/OUTx4x" "adc_0/OUTx3x" -0.00683876
cap "adc_0/GRAY_INx5x" "adc_0/GRAY_INx4x" -0.44335
cap "adc_0/GRAY_INx4x" "adc_0/BIAS2" 1.43604
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "8bit_sens_0/sens_amp_4/GN" 0.165875
cap "adc_0/V_IN" "adc_0/BIAS1" -1.6388
cap "adc_0/GRAY_INx7x" "adc_0/GRAY_INx0x" -0.0156495
cap "adc_0/OUTx7x" "adc_0/GRAY_INx7x" -1.79215
cap "adc_0/READ" "adc_0/BIAS1" 0.0964531
cap "adc_0/V_IN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 3.2382
cap "adc_0/OUTx4x" "adc_0/GRAY_INx2x" -0.00527605
cap "adc_0/a_1870_n1400#" "adc_0/GRAY_INx3x" -0.0350848
cap "adc_0/GND" "adc_0/a_1870_n1400#" 0.000155045
cap "adc_0/GRAY_INx2x" "adc_0/GRAY_INx0x" -3.21709
cap "adc_0/OUTx6x" "adc_0/BIAS1" 13.2975
cap "adc_0/V_IN" "adc_0/BIAS2" 0.000833376
cap "adc_0/V_RAMP" "adc_0/GRAY_INx3x" -2.85436
cap "adc_0/V_RAMP" "adc_0/GND" 0.311667
cap "adc_0/V_RAMP" "adc_0/GRAY_INx6x" -1.15454
cap "8bit_sens_0/sens_amp_4/GN" "adc_0/BIAS1" 0.223684
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.53528
cap "adc_0/OUTx3x" "adc_0/BIAS1" -0.0236294
cap "adc_0/GRAY_INx3x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 2.85889
cap "adc_0/GRAY_INx7x" "adc_0/BIAS1" 0.109954
cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 15.6831
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/GRAY_INx6x" 3.4409
cap "adc_0/a_1720_n1450#" "adc_0/GRAY_INx3x" -0.112858
cap "adc_0/a_1720_n1450#" "adc_0/GND" 0.0869556
cap "adc_0/OUTx6x" "adc_0/BIAS2" -0.179115
cap "adc_0/V_IN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 3.93029
cap "8bit_sens_0/sens_amp_6/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.7696
cap "adc_0/OUTx4x" "adc_0/V_RAMP" 0.443272
cap "adc_0/OUTx2x" "adc_0/OUTx3x" -0.00787517
cap "adc_0/GRAY_INx2x" "adc_0/BIAS1" -0.303442
cap "adc_0/OUTx6x" "adc_0/GRAY_INx4x" 0.0948886
cap "adc_0/GRAY_INx5x" "adc_0/OUTx3x" -0.0081548
cap "adc_0/V_RAMP" "adc_0/OUTx7x" 11.1757
cap "adc_0/GRAY_INx5x" "adc_0/GRAY_INx7x" -3.14667
cap "adc_0/OUTx3x" "adc_0/BIAS2" 0.533499
cap "adc_0/OUTx4x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 7.09042
cap "adc_0/GRAY_INx7x" "adc_0/BIAS2" 1.538
cap "adc_0/OUTx6x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.0358097
cap "adc_0/OUTx7x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.830997
cap "adc_0/READ" "adc_0/V_IN" 0.839431
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.14728
cap "adc_0/OUTx2x" "adc_0/GRAY_INx2x" -0.00656107
cap "adc_0/GRAY_INx7x" "adc_0/GRAY_INx4x" -0.102108
cap "adc_0/GRAY_INx2x" "adc_0/GRAY_INx5x" -0.2044
cap "8bit_sens_0/sens_amp_5/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.574617
cap "adc_0/a_1870_n1400#" "adc_0/BIAS1" 0.0626166
cap "adc_0/GRAY_INx2x" "adc_0/BIAS2" 1.09507
cap "8bit_sens_0/sens_amp_3/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.08216
cap "8bit_sens_0/sens_amp_5/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.361432
cap "adc_0/V_IN" "adc_0/OUTx6x" 3.83505
cap "adc_0/GRAY_INx7x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" -0.616512
cap "adc_0/GRAY_INx2x" "adc_0/GRAY_INx4x" -3.95949
cap "adc_0/V_RAMP" "adc_0/BIAS1" -664.117
cap "adc_0/V_RAMP" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.106864
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/BIAS1" 11.1342
cap "8bit_sens_0/sens_amp_3/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.301637
cap "adc_0/V_IN" "adc_0/GRAY_INx7x" 4.313
cap "adc_0/OUTx2x" "adc_0/a_1870_n1400#" 0.190204
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 1.52405
cap "adc_0/READ" "adc_0/GRAY_INx7x" -1.02775
cap "adc_0/a_1720_n1450#" "adc_0/BIAS1" 0.488532
cap "adc_0/a_1870_n1400#" "adc_0/BIAS2" 0.15769
cap "adc_0/OUTx2x" "adc_0/V_RAMP" -0.82752
cap "adc_0/V_RAMP" "adc_0/GRAY_INx5x" -2.06275
cap "adc_0/OUTx3x" "adc_0/OUTx6x" -0.00664346
cap "adc_0/GRAY_INx7x" "adc_0/OUTx6x" -0.665321
cap "adc_0/V_RAMP" "adc_0/BIAS2" 3.36643
cap "adc_0/OUTx2x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 6.27281
cap "adc_0/GRAY_INx5x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 2.93195
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 1.14728
cap "adc_0/V_RAMP" "adc_0/GRAY_INx4x" -2.15318
cap "adc_0/OUTx2x" "adc_0/a_1720_n1450#" 0.189804
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/BIAS2" -0.315697
cap "adc_0/GRAY_INx2x" "adc_0/OUTx6x" 0.0583673
cap "adc_0/OUTx3x" "adc_0/GRAY_INx7x" -0.00626754
cap "adc_0/a_1720_n1450#" "adc_0/BIAS2" 0.636786
cap "adc_0/GRAY_INx4x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 3.0844
cap "adc_0/V_RAMP" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.385079
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.53528
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 1.14469
cap "adc_0/GRAY_INx2x" "adc_0/GRAY_INx7x" -0.0728974
cap "adc_0/V_IN" "adc_0/V_RAMP" 0.485135
cap "adc_0/READ" "adc_0/V_RAMP" 0.0142196
cap "adc_0/V_IN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 4.10722
cap "adc_0/OUTx6x" "adc_0/a_1870_n1400#" -0.000808123
cap "adc_0/OUTx5x" "adc_0/OUTx0x" -0.00458679
cap "adc_0/READ" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.77255
cap "adc_0/V_RAMP" "adc_0/OUTx6x" 7.77541
cap "adc_0/VDD" "adc_0/GRAY_INx1x" 68.1305
cap "adc_0/GRAY_INx0x" "adc_0/GND" -0.0424416
cap "adc_0/VDD" "adc_0/a_1870_n1400#" 14.0906
cap "adc_0/GRAY_INx0x" "adc_0/OUTx4x" -0.00159611
cap "adc_0/OUTx7x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -9.4198e-05
cap "adc_0/GND" "adc_0/VDD" 7.25567
cap "adc_0/BIAS1" "adc_0/OUTx1x" 7.08287
cap "adc_0/VDD" "adc_0/OUTx4x" 0.0069177
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "adc_0/VDD" 11.1423
cap "adc_0/GRAY_INx1x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 5.87334
cap "adc_0/a_1870_n1400#" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.00247492
cap "adc_0/GRAY_INx0x" "adc_0/GRAY_INx7x" -0.0198035
cap "adc_0/GRAY_INx0x" "adc_0/BIAS2" 4.54572
cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.0870435
cap "adc_0/GRAY_INx4x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.000349614
cap "adc_0/BIAS2" "adc_0/VDD" 10.1046
cap "adc_0/GRAY_INx1x" "adc_0/GRAY_INx2x" -0.124801
cap "adc_0/OUTx4x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.000240055
cap "adc_0/GRAY_INx0x" "adc_0/BIAS1" 10.405
cap "8bit_sens_0/sens_amp_6/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.102219
cap "adc_0/GRAY_INx0x" "adc_0/OUTx1x" 3.62037
cap "adc_0/GRAY_INx3x" "adc_0/GRAY_INx1x" -4.72
cap "adc_0/BIAS2" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 5.82764
cap "adc_0/GRAY_INx7x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.00015116
cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.792228
cap "adc_0/BIAS1" "adc_0/VDD" -14.9879
cap "adc_0/OUTx1x" "adc_0/VDD" 37.931
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "adc_0/BIAS2" 2.38282
cap "adc_0/OUTx0x" "adc_0/a_1870_n1400#" 0.0383805
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.0957691
cap "adc_0/OUTx0x" "adc_0/GND" 0.0136061
cap "adc_0/BIAS1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 12.1482
cap "adc_0/a_1100_n1450#" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.00171971
cap "adc_0/GRAY_INx1x" "adc_0/OUTx5x" -0.00111014
cap "adc_0/OUTx1x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 2.60045
cap "adc_0/OUTx0x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.0796942
cap "adc_0/OUTx3x" "adc_0/GRAY_INx1x" -0.00159371
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "adc_0/BIAS1" 1.62116
cap "adc_0/OUTx1x" "adc_0/OUTx2x" -0.00411871
cap "adc_0/GRAY_INx0x" "adc_0/VDD" 7.91641
cap "adc_0/OUTx1x" "adc_0/GRAY_INx2x" 2.125
cap "adc_0/V_RAMP" "adc_0/GRAY_INx1x" -3.30576
cap "adc_0/OUTx0x" "adc_0/BIAS2" 0.582774
cap "adc_0/V_RAMP" "adc_0/a_1870_n1400#" -0.138808
cap "adc_0/GRAY_INx6x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.000211158
cap "adc_0/GRAY_INx3x" "adc_0/OUTx1x" 0.0289899
cap "adc_0/GRAY_INx0x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 4.37088
cap "adc_0/OUTx0x" "adc_0/BIAS1" -0.19389
cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 131.301
cap "adc_0/OUTx0x" "adc_0/OUTx1x" 0.0267024
cap "adc_0/GRAY_INx0x" "adc_0/OUTx2x" -0.00278237
cap "adc_0/GRAY_INx1x" "adc_0/OUTx7x" 0.031177
cap "adc_0/GRAY_INx0x" "adc_0/GRAY_INx2x" -3.21709
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "adc_0/VDD" 0.611897
cap "adc_0/VDD" "adc_0/OUTx2x" 0.106822
cap "adc_0/VDD" "adc_0/GRAY_INx2x" 0.914055
cap "adc_0/OUTx1x" "adc_0/GRAY_INx5x" 0.0222222
cap "adc_0/a_1720_n1450#" "adc_0/VDD" 1.32721
cap "adc_0/GRAY_INx3x" "adc_0/GRAY_INx0x" -0.232955
cap "adc_0/OUTx1x" "adc_0/OUTx6x" -0.0244687
cap "adc_0/GND" "adc_0/GRAY_INx1x" -0.0298699
cap "adc_0/V_RAMP" "adc_0/BIAS1" -168.6
cap "adc_0/OUTx2x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.000368924
cap "adc_0/GRAY_INx3x" "adc_0/VDD" 1.0876
cap "adc_0/GRAY_INx4x" "adc_0/GRAY_INx1x" -0.0970765
cap "adc_0/OUTx0x" "adc_0/GRAY_INx0x" 0.0964878
cap "adc_0/V_RAMP" "adc_0/OUTx1x" -1.84773
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "adc_0/GRAY_INx1x" -0.341106
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/GRAY_INx2x" -0.000439698
cap "adc_0/a_1720_n1450#" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.00188537
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_7/GN" 0.920638
cap "adc_0/OUTx0x" "adc_0/VDD" 1.7365
cap "adc_0/GRAY_INx0x" "adc_0/GRAY_INx5x" -0.159847
cap "adc_0/BIAS2" "adc_0/GRAY_INx1x" 5.16337
cap "adc_0/GRAY_INx3x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.00040454
cap "adc_0/BIAS2" "adc_0/a_1870_n1400#" 0.314414
cap "adc_0/GRAY_INx0x" "adc_0/OUTx6x" 0.00169993
cap "8bit_sens_0/sens_amp_6/net1" "adc_0/GND" 0.00254282
cap "adc_0/VDD" "adc_0/GRAY_INx5x" 0.0207213
cap "adc_0/BIAS2" "adc_0/GND" 0.0418438
cap "adc_0/OUTx0x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 2.54482
cap "adc_0/OUTx1x" "adc_0/OUTx7x" -0.383333
cap "adc_0/OUTx3x" "adc_0/VDD" 0.10052
cap "adc_0/a_1000_n1450#" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.000739431
cap "8bit_sens_0/sens_amp_6/net1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.0887912
cap "adc_0/V_RAMP" "adc_0/GRAY_INx0x" -6.4132
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "adc_0/BIAS2" 3.22123
cap "adc_0/V_IN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.000607848
cap "adc_0/BIAS1" "adc_0/GRAY_INx1x" 11.739
cap "adc_0/OUTx1x" "adc_0/GRAY_INx1x" 0.0740505
cap "adc_0/BIAS1" "adc_0/a_1870_n1400#" 2.43712
cap "adc_0/V_RAMP" "adc_0/VDD" 41.8575
cap "adc_0/OUTx5x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.000222031
cap "adc_0/OUTx1x" "adc_0/a_1870_n1400#" 0.351124
cap "adc_0/GRAY_INx5x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.000305267
cap "8bit_sens_0/sens_amp_7/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.211299
cap "adc_0/OUTx3x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.000309981
cap "adc_0/BIAS1" "adc_0/GND" 1.189
cap "adc_0/OUTx6x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.000249469
cap "adc_0/OUTx1x" "adc_0/GND" 0.0702307
cap "adc_0/BIAS1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 2.71877
cap "adc_0/OUTx1x" "adc_0/OUTx4x" -0.00277148
cap "adc_0/V_RAMP" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.00533453
cap "adc_0/OUTx1x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.648694
cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.321641
cap "adc_0/BIAS2" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.54716
cap "adc_0/GRAY_INx6x" "adc_0/GRAY_INx1x" -0.0561326
cap "adc_0/BIAS1" "adc_0/BIAS2" 2.29663
cap "adc_0/OUTx1x" "adc_0/GRAY_INx7x" -0.0468572
cap "adc_0/GRAY_INx0x" "adc_0/GRAY_INx1x" -0.648975
cap "adc_0/OUTx1x" "adc_0/BIAS2" 2.42069
cap "adc_0/OUTx6x" "adc_0/VDD" 0.0650559
cap "adc_0/V_IN" "adc_0/VDD" 0.0861568
cap "adc_0/VDD" "adc_0/GRAY_INx2x" 0.0352946
cap "adc_0/VDD" "adc_0/OUTx6x" 0.435178
cap "adc_0/GRAY_INx3x" "adc_0/VDD" 0.00770497
cap "adc_0/OUTx1x" "adc_0/VDD" 0.0891085
cap "adc_0/OUTx4x" "adc_0/VDD" 0.345473
cap "adc_0/V_RAMP" "adc_0/VDD" 0.744138
cap "adc_0/GND" "adc_0/VDD" 0.0020662
cap "adc_0/OUTx3x" "adc_0/VDD" 0.378163
cap "adc_0/a_1870_n1400#" "adc_0/VDD" 1.9288
cap "adc_0/VDD" "adc_0/a_1720_n1450#" 0.243918
cap "adc_0/a_1100_n1450#" "adc_0/VDD" 0.0315693
cap "adc_0/a_1000_n1450#" "adc_0/VDD" 4.26443
cap "adc_0/VDD" "adc_0/BIAS1" 0.0621333
cap "adc_0/V_IN" "adc_0/VDD" 0.177323
cap "adc_0/GRAY_INx7x" "adc_0/VDD" 0.00511569
cap "adc_0/OUTx2x" "adc_0/VDD" 0.10155
cap "adc_0/GRAY_INx5x" "adc_0/VDD" 0.0184919
cap "adc_0/V_RAMP" "adc_0/GRAY_INx0x" 1.00873
cap "adc_0/GRAY_INx1x" "adc_0/GRAY_INx0x" 0.0130141
cap "adc_0/BIAS1" "adc_0/VDD" -0.00247074
cap "adc_0/BIAS1" "adc_0/GRAY_INx0x" 0.90487
cap "adc_0/VDD" "adc_0/OUTx1x" 0.334081
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/VDD" 0.655295
cap "adc_0/BIAS2" "adc_0/GRAY_INx0x" 0.165109
cap "adc_0/GRAY_INx0x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.64773
cap "adc_0/GND" "adc_0/VDD" 0.00229578
cap "adc_0/GRAY_INx0x" "adc_0/VDD" 66.3076
cap "adc_0/a_1870_n1400#" "adc_0/VDD" 0.570974
cap "adc_0/V_RAMP" "adc_0/VDD" 0.0132055
cap "adc_0/VDD" "adc_0/GRAY_INx0x" 0.00886991
cap "bias_cell_0/SF_IB" "bias_cell_0/GND" 0.256901
cap "bias_cell_0/SF_IB" "bias_cell_0/NB1" 6.33874
cap "bias_cell_0/SF_IB" "bias_cell_0/GND" -140.721
cap "bias_cell_0/GND" "bias_cell_0/NB1" 33.2328
cap "bias_cell_0/SF_IB" "bias_cell_0/NB1" 6.25887
cap "bias_cell_0/NB2" "bias_cell_0/GND" 33.6137
cap "bias_cell_0/GND" "bias_cell_0/OUT_IB" 34.4609
cap "bias_cell_0/BIAS2_OUT" "bias_cell_0/GND" -157.602
cap "bias_cell_0/GND" "bias_cell_0/AMP_IB" 32.2337
cap "bias_cell_0/BIAS2_OUT" "bias_cell_0/BIAS1_OUT" -14.8202
cap "bias_cell_0/BIAS1_OUT" "bias_cell_0/BIAS2_OUT" -14.8202
cap "bias_cell_0/BIAS1_OUT" "bias_cell_0/GND" -146.696
cap "bias_cell_0/BIAS1_OUT" "bias_cell_0/SA_IREF_OUT" -8.93714
cap "bias_cell_0/SA_IREF_OUT" "bias_cell_0/BIAS1_OUT" -8.93714
cap "bias_cell_0/SA_IREF_OUT" "bias_cell_0/GND" -169.728
cap "bias_cell_0/GND" "vssa2" 18.5439
cap "bias_cell_0/GND" "vssa2" 9.56063
cap "bias_cell_0/GND" "bias_cell_0/ADC_ON" 4.81302
cap "bias_cell_0/VDD" "bias_cell_0/GND" 0.792477
cap "bias_cell_0/VDD" "bias_cell_0/SF_IB" 38.4234
cap "vssa2" "bias_cell_0/SF_IB" 0.538961
cap "bias_cell_0/NB1" "bias_cell_0/SF_IB" 5.91555
cap "bias_cell_0/SF_IB" "bias_cell_0/GND" 2.2669
cap "bias_cell_0/SF_IB" "bias_cell_0/GND" -37.6206
cap "bias_cell_0/SF_IB" "vssa2" 3.22459
cap "bias_cell_0/SF_IB" "bias_cell_0/NB1" 5.55812
cap "bias_cell_0/VDD" "vssa2" 0.0234239
cap "bias_cell_0/VDD" "bias_cell_0/GND" -51.1204
cap "bias_cell_0/NB2" "bias_cell_0/VDD" -4.74647
cap "bias_cell_0/VDD" "bias_cell_0/NB1" -78.5225
cap "bias_cell_0/GND" "bias_cell_0/NB1" 9.19156
cap "vssa2" "bias_cell_0/NB1" 4.94416
cap "bias_cell_0/VDD" "bias_cell_0/SF_IB" 200.542
cap "bias_cell_0/VDD" "bias_cell_0/OUT_IB" 0.0172511
cap "bias_cell_0/NB2" "vssa2" 6.07279
cap "bias_cell_0/NB1" "bias_cell_0/OUT_IB" -1.17125
cap "bias_cell_0/NB1" "bias_cell_0/NB2" -36.2581
cap "bias_cell_0/GND" "bias_cell_0/NB1" 0.542014
cap "bias_cell_0/NB2" "bias_cell_0/OUT_IB" 10.6338
cap "bias_cell_0/VDD" "bias_cell_0/OUT_IB" 0.0156279
cap "bias_cell_0/GND" "bias_cell_0/OUT_IB" 6.09794
cap "bias_cell_0/NB1" "vssa2" 1.12863
cap "vssa2" "bias_cell_0/OUT_IB" 42.3191
cap "bias_cell_0/NB2" "bias_cell_0/VDD" -4.08557
cap "bias_cell_0/GND" "bias_cell_0/NB2" 10.5885
cap "bias_cell_0/GND" "bias_cell_0/AMP_IB" 0.66512
cap "bias_cell_0/AMP_IB" "bias_cell_0/GND" 2.69373
cap "vssa2" "bias_cell_0/AMP_IB" 0.066909
cap "vssa2" "bias_cell_0/AMP_IB" 8.09548
cap "bias_cell_0/AMP_IB" "bias_cell_0/OUT_IB" -3.28442
cap "bias_cell_0/GND" "bias_cell_0/OUT_IB" -16.3199
cap "vssa2" "bias_cell_0/OUT_IB" 23.3593
cap "bias_cell_0/BIAS2" "bias_cell_0/AMP_IB" 5.74422
cap "bias_cell_0/OUT_IB" "bias_cell_0/AMP_IB" -3.28442
cap "bias_cell_0/AMP_IB" "bias_cell_0/GND" -34.3506
cap "bias_cell_0/ADC_ON" "bias_cell_0/AMP_IB" 36.8352
cap "bias_cell_0/BIAS2_OUT" "bias_cell_0/AMP_IB" 13.8897
cap "vssa2" "bias_cell_0/AMP_IB" 49.3466
cap "bias_cell_0/AMP_IB" "bias_cell_0/BIAS2_OUT" 11.6294
cap "bias_cell_0/AMP_IB" "bias_cell_0/ADC_ON" 4.00333
cap "bias_cell_0/AMP_IB" "bias_cell_0/BIAS2" 4.6525
cap "bias_cell_0/BIAS2_OUT" "bias_cell_0/BIAS2" 21.3879
cap "bias_cell_0/BIAS2_OUT" "vssa2" 18.5098
cap "bias_cell_0/AMP_IB" "vssa2" 9.22212
cap "bias_cell_0/ADC_ON" "vssa2" 0.341618
cap "bias_cell_0/GND" "bias_cell_0/BIAS2" 0.1402
cap "bias_cell_0/GND" "bias_cell_0/BIAS2_OUT" -26.3677
cap "bias_cell_0/GND" "bias_cell_0/AMP_IB" 17.5678
cap "bias_cell_0/GND" "bias_cell_0/ADC_ON" 0.00108548
cap "bias_cell_0/BIAS2_OUT" "bias_cell_0/BIAS1_OUT" -10.4056
cap "bias_cell_0/SA_IREF_OUT" "bias_cell_0/BIAS1_OUT" -6.14429
cap "bias_cell_0/BIAS1_OUT" "bias_cell_0/BIAS2_OUT" -10.4056
cap "bias_cell_0/GND" "bias_cell_0/ADC_ON" 0.0119403
cap "bias_cell_0/BIAS1_OUT" "vssa2" 18.4787
cap "bias_cell_0/BIAS1" "bias_cell_0/ADC_ON" 0.0869176
cap "bias_cell_0/AMP_IB" "bias_cell_0/ADC_ON" 0.00352505
cap "vssa2" "bias_cell_0/ADC_ON" 3.58664
cap "bias_cell_0/BIAS1_OUT" "bias_cell_0/GND" -27.7692
cap "bias_cell_0/BIAS1" "bias_cell_0/GND" -0.233896
cap "bias_cell_0/BIAS1_OUT" "bias_cell_0/BIAS1" 20.6427
cap "bias_cell_0/SA_IREF_OUT" "bias_cell_0/BIAS1_OUT" -6.14429
cap "vssa2" "bias_cell_0/SA_IREF_OUT" 20.4287
cap "vssa2" "bias_cell_0/ADC_ON" 27.4138
cap "vssa2" "bias_cell_0/SA_IREF_OUT" 0.641032
cap "bias_cell_0/SA_IREF" "bias_cell_0/SA_IREF_OUT" 14.3705
cap "bias_cell_0/SA_IREF" "bias_cell_0/ADC_ON" 92.588
cap "bias_cell_0/BIAS1" "bias_cell_0/ADC_ON" 2.09649
cap "bias_cell_0/SA_IREF_OUT" "bias_cell_0/ADC_ON" 47.842
cap "vssa2" "bias_cell_0/GND" 0.000288907
cap "bias_cell_0/SA_IREF" "bias_cell_0/GND" 0.18249
cap "bias_cell_0/GND" "bias_cell_0/SA_IREF_OUT" -37.4895
cap "bias_cell_0/GND" "bias_cell_0/ADC_ON" 0.435573
cap "bias_cell_0/ADC_ON" "bias_cell_0/SA_IREF_OUT" 59.7718
cap "bias_cell_0/GND" "bias_cell_0/SA_IREF" 0.233775
cap "bias_cell_0/ADC_ON" "bias_cell_0/GND" 16.9242
cap "bias_cell_0/ADC_ON" "vssa2" 1.45503
cap "bias_cell_0/ADC_ON" "bias_cell_0/SA_IREF" 12.645
cap "bias_cell_0/SA_IREF_OUT" "vssa2" 1.50161
cap "vssa2" "bias_cell_0/GND" 17.77
cap "vssa2" "bias_cell_0/GND" 10.0505
cap "bias_cell_0/SF_IB" "vssa2" 0.0132899
cap "vssa2" "bias_cell_0/VDD" 1.23346
cap "vssa2" "bias_cell_0/SF_IB" 3.00398
cap "vssa2" "bias_cell_0/VDD" 31.9333
cap "bias_cell_0/VDD" "bias_cell_0/NB2" 0.767235
cap "bias_cell_0/NB1" "vssa2" 21.9783
cap "bias_cell_0/SF_IB" "vssa2" 18.4645
cap "bias_cell_0/VDD" "vssa2" 89.2973
cap "bias_cell_0/VDD" "bias_cell_0/NB1" 4.02895
cap "bias_cell_0/OUT_IB" "vssa2" 63.8166
cap "bias_cell_0/NB1" "vssa2" 3.00308
cap "bias_cell_0/NB2" "vssa2" 26.3678
cap "bias_cell_0/VDD" "bias_cell_0/NB2" 0.905514
cap "vssa2" "bias_cell_0/AMP_IB" 1.87345
cap "vssa2" "bias_cell_0/AMP_IB" 8.86286
cap "vssa2" "bias_cell_0/OUT_IB" 75.4627
cap "bias_cell_0/AMP_IB" "bias_cell_0/BIAS2" 37.7595
cap "bias_cell_0/AMP_IB" "vssa2" 110.172
cap "bias_cell_0/GND" "bias_cell_0/BIAS2" -0.693635
cap "vssa2" "bias_cell_0/AMP_IB" 15.0888
cap "bias_cell_0/AMP_IB" "bias_cell_0/BIAS2" 46.2444
cap "bias_cell_0/ADC_ON" "vssa2" 25.5775
cap "bias_cell_0/BIAS2_OUT" "vssa2" 149.849
cap "bias_cell_0/BIAS2_OUT" "bias_cell_0/BIAS2" -0.421773
cap "vssa2" "bias_cell_0/BIAS2" 356.305
cap "bias_cell_0/BIAS1" "bias_cell_0/BIAS2" -2.06618
cap "bias_cell_0/BIAS1" "bias_cell_0/BIAS1_OUT" -1.27181
cap "bias_cell_0/BIAS1" "bias_cell_0/BIAS2" -2.06618
cap "bias_cell_0/BIAS1" "bias_cell_0/SA_IREF" 4.30371
cap "vssa2" "bias_cell_0/BIAS2_OUT" 0.223042
cap "vssa2" "bias_cell_0/ADC_ON" 35.1064
cap "bias_cell_0/BIAS1" "bias_cell_0/ADC_ON" 2.0004
cap "bias_cell_0/BIAS1" "bias_cell_0/GND" -1.37507
cap "vssa2" "bias_cell_0/BIAS1_OUT" 144.426
cap "vssa2" "bias_cell_0/BIAS2" 4.80252
cap "vssa2" "bias_cell_0/SA_IREF_OUT" 0.635558
cap "vssa2" "bias_cell_0/SA_IREF" 25.7364
cap "vssa2" "bias_cell_0/BIAS1" 333.113
cap "bias_cell_0/ADC_ON" "bias_cell_0/BIAS1" 7.04389
cap "bias_cell_0/BIAS1" "bias_cell_0/SA_IREF" 78.741
cap "bias_cell_0/ADC_ON" "bias_cell_0/SA_IREF" 94.5125
cap "bias_cell_0/SA_IREF_OUT" "vssa2" 143.895
cap "bias_cell_0/ADC_ON" "vssa2" 72.9397
cap "vssa2" "bias_cell_0/SA_IREF" 314.086
cap "bias_cell_0/GND" "bias_cell_0/SA_IREF" -3.20091
cap "bias_cell_0/SA_IREF" "bias_cell_0/GND" 0.507614
cap "bias_cell_0/ADC_ON" "vssa2" 4.43082
cap "bias_cell_0/SA_IREF" "bias_cell_0/ADC_ON" -15.455
cap "bias_cell_0/SA_IREF" "vssa2" 5.68434e-14
merge "bias_cell_0/GND" "adc_0/GND" -25256.3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -12092932 -46068 -1031481 -2893 -3028671 -7344 -21586463 -38390 0 0 0 0
merge "adc_0/GND" "8bit_sens_0/VSUBS"
merge "8bit_sens_0/VSUBS" "VSUBS"
merge "VSUBS" "8bit_sens_0/sens_amp_7/GND"
merge "8bit_sens_0/sens_amp_7/GND" "8bit_sens_0/GND"
merge "8bit_sens_0/GND" "vssa2"
merge "adc_0/GRAY_INx7x" "la_data_in[127]" -103.239 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0
merge "8bit_sens_0/OUTx7x" "la_data_out[1]" -181.166 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0
merge "adc_0/OUTx6x" "8bit_sens_0/INx6x" -499.999 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2680 -220 0 0 -4800 -280 0 0 0 0
merge "8bit_sens_0/INx6x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL"
merge "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "m2_53493_202942#"
merge "adc_0/OUTx7x" "8bit_sens_0/INx7x" -282.02 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2500 -280 0 0 0 0 0 0 0 0
merge "8bit_sens_0/INx7x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL"
merge "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "m2_53160_202790#"
merge "adc_0/GRAY_INx6x" "la_data_in[126]" -63.6356 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1600 -160 0 0 0 0 0 0 0 0
merge "bias_cell_0/SA_IREF" "io_analog[3]" -625.112 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -297970 -2692 0 0 0 0 0 0
merge "adc_0/GRAY_INx5x" "la_data_in[125]" -68.8285 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0
merge "8bit_sens_0/OUTx6x" "la_data_out[2]" -52.7968 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0
merge "adc_0/GRAY_INx4x" "la_data_in[124]" -51.3026 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1600 -160 0 0 0 0 0 0 0 0
merge "bias_cell_0/BIAS1_OUT" "adc_0/BIAS1" -640.29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -64800 -1780 -260460 -8862 0 0 0 0 0 0
merge "adc_0/BIAS1" "m2_33290_207480#"
merge "8bit_sens_0/OUTx5x" "la_data_out[3]" -39.5135 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0
merge "adc_0/VDD" "8bit_sens_0/sens_amp_7/VDD" -1916.98 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -172600 -4180 0 0 -21600 -530 0 0 0 0 0 0
merge "8bit_sens_0/sens_amp_7/VDD" "8bit_sens_0/VDD"
merge "8bit_sens_0/VDD" "vccd1"
merge "adc_0/GRAY_INx3x" "la_data_in[123]" -56.4941 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0
merge "8bit_sens_0/OUTx4x" "la_data_out[4]" -29.9959 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0
merge "adc_0/OUTx2x" "8bit_sens_0/INx2x" -265.697 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2340 -200 0 0 -3600 -240 0 0 0 0
merge "8bit_sens_0/INx2x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL"
merge "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "m2_54833_202912#"
merge "adc_0/OUTx4x" "8bit_sens_0/INx4x" -221.133 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3700 -280 0 0 -4200 -260 0 0 0 0
merge "8bit_sens_0/INx4x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL"
merge "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "m2_54170_202730#"
merge "adc_0/GRAY_INx2x" "la_data_in[122]" -52.0208 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1600 -160 0 0 0 0 0 0 0 0
merge "bias_cell_0/VDD" "vccd2" -1730.53 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -567100 -3200 -567100 -3200 0 0 0 0 0 0 0 0
merge "8bit_sens_0/OUTx3x" "la_data_out[5]" -28.0956 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0
merge "bias_cell_0/BIAS2_OUT" "adc_0/BIAS2" -182.147 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 -64800 -1780 0 0 0 0 0 0 0 0
merge "adc_0/BIAS2" "m1_49580_204344#"
merge "adc_0/GRAY_INx1x" "la_data_in[121]" -199.389 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 -7360 -776 0 0
merge "8bit_sens_0/OUTx2x" "la_data_out[6]" -32.3036 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0
merge "adc_0/OUTx3x" "8bit_sens_0/INx3x" -142.241 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2675 -290 0 0 0 0 0 0 0 0
merge "8bit_sens_0/INx3x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL"
merge "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "m2_54520_202790#"
merge "adc_0/GRAY_INx0x" "la_data_in[120]" -105.319 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -7600 -460 0 0 0 0 0 0 0 0
merge "8bit_sens_0/OUTx1x" "la_data_out[7]" -39.3084 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0
merge "8bit_sens_0/OUTx0x" "la_data_out[8]" -107.04 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0
merge "8bit_sens_0/VREF" "m3_51655_199490#" -69.5571 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4900 -280 0 0 0 0 0 0
merge "bias_cell_0/ADC_ON" "gpio_analog[7]" -310.454 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -40000 -800 0 0 0 0 0 0
merge "bias_cell_0/SF_IB" "io_analog[10]" -991.29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -911650 -2952 -76410 -1878 0 0 0 0 0 0
merge "io_analog[10]" "m3_26500_684896#"
merge "bias_cell_0/SA_IREF_OUT" "8bit_sens_0/SA_IREF" -287.093 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -64800 -1780 -4800 -280 0 0 0 0 0 0
merge "8bit_sens_0/SA_IREF" "m2_34420_199220#"
merge "bias_cell_0/OUT_IB" "io_analog[7]" -922.811 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -614640 -4302 0 0 0 0 0 0
merge "adc_0/OUTx5x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -67.2694 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2800 -300 0 0 0 0 0 0 0 0
merge "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_sens_0/INx5x"
merge "8bit_sens_0/INx5x" "m2_53840_202790#"
merge "bias_cell_0/NB1" "io_analog[9]" -236.091 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -146200 -2062 0 0 0 0 0 0
merge "bias_cell_0/NB2" "io_analog[8]" -312.951 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -140200 -2002 0 0 0 0 0 0
merge "adc_0/OUTx1x" "8bit_sens_0/INx1x" -86.6236 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2490 -284 0 0 0 0 0 0 0 0
merge "8bit_sens_0/INx1x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL"
merge "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "m2_55208_202785#"
merge "adc_0/OUTx0x" "8bit_sens_0/INx0x" -449.058 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2340 -200 0 0 -3600 -240 0 0 0 0
merge "8bit_sens_0/INx0x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL"
merge "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "m2_55523_202892#"
merge "bias_cell_0/AMP_IB" "io_analog[6]" -999.921 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -623220 -4282 0 0 0 0 0 0
merge "bias_cell_0/BIAS2" "io_analog[5]" -220.761 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -23500 -1040 0 0 0 0 0 0
merge "bias_cell_0/BIAS1" "io_analog[4]" -1187.48 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -935770 -5392 0 0 0 0 0 0
merge "adc_0/V_RAMP" "io_analog[2]" -1253.17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -350400 -11800 0 0 0 0 0 0