diff --git a/verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v b/verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v
index bc0cdf0..593bc46 100644
--- a/verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v
+++ b/verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v
@@ -54,7 +54,6 @@
       wmask0_reg = wmask0;
       addr0_reg = addr0;
       din0_reg = din0;
-      #(T_HOLD) dout0 = 32'bx;
       if ( !csb0_reg && web0_reg && VERBOSE ) 
         $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
       if ( !csb0_reg && !web0_reg && VERBOSE )
@@ -72,7 +71,6 @@
       addr1_reg = addr1;
       if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
            $display($time," WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!",addr0,addr1);
-      #(T_HOLD) dout1 = 32'bx;
       if ( !csb1_reg && VERBOSE ) 
         $display($time," Reading %m addr1=%b dout1=%b",addr1_reg,mem[addr1_reg]);
     end
@@ -100,7 +98,7 @@
     always @ (negedge clk0)
     begin : MEM_READ0
       if (!csb0_reg && web0_reg)
-         dout0 <= #(DELAY) mem[addr0_reg];
+         dout0 <=  mem[addr0_reg];
     end
   
     // Memory Read Block Port 1
@@ -108,7 +106,7 @@
     always @ (negedge clk1)
     begin : MEM_READ1
       if (!csb1_reg)
-         dout1 <= #(DELAY) mem[addr1_reg];
+         dout1 <=  mem[addr1_reg];
     end
   
   endmodule