diff --git a/verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v b/verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v
index 19337a3..ce7c30f 100644
--- a/verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v
+++ b/verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v
@@ -33,7 +33,7 @@
       input [NUM_WMASKS-1:0]   wmask0; // write mask
       input [ADDR_WIDTH-1:0]  addr0;
       input [DATA_WIDTH-1:0]  din0;
-      output reg [DATA_WIDTH-1:0] dout0;
+      output [DATA_WIDTH-1:0] dout0;
       input  clk1; // clock
       input   csb1; // active low chip select
       input [ADDR_WIDTH-1:0]  addr1;
@@ -44,6 +44,7 @@
       reg [NUM_WMASKS-1:0]   wmask0_reg;
       reg [ADDR_WIDTH-1:0]  addr0_reg;
       reg [DATA_WIDTH-1:0]  din0_reg;
+      reg [DATA_WIDTH-1:0]  dout0;
     
       // All inputs are registers
       always @(posedge clk0)
@@ -53,7 +54,7 @@
         wmask0_reg = wmask0;
         addr0_reg = addr0;
         din0_reg = din0;
-        #(T_HOLD) dout0 = 32'bx;
+        #(T_HOLD) dout0 <= 32'bx;
         if ( !csb0_reg && web0_reg && VERBOSE ) 
           $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
         if ( !csb0_reg && !web0_reg && VERBOSE )