v {xschem version=2.9.8 file_version=1.2

* Copyright 2021 Stefan Frederik Schippers
* 
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
*     https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.

}
G {type=stdcell
vhdl_stop=true
verilog_stop=true
format="@name @pinlist @VCCPIN @VSSPIN @VCCBPIN @VSSBPIN @symname"
template="name=x1 VCCPIN=VCC VSSPIN=VSS VCCBPIN=VCC VSSBPIN=VSS"
generic_type="VCCPIN=string VSSPIN=string VCCBPIN=string VSSBPIN=string"
extra="VCCPIN VSSPIN VCCBPIN VSSBPIN"}
V {}
S {}
E {}
L 4 20 0 40 0 {}
L 4 -40 -20 -20 -20 {}
L 4 -40 20 -20 20 {}
L 4 -40 60 0 60 {}
L 4 -20 -30 -20 30 {}
L 4 -20 30 20 15 {}
L 4 20 -15 20 15 {}
L 4 -20 -30 20 -15 {}
L 4 0 22.5 0 60 {}
B 5 37.5 -2.5 42.5 2.5 {name=Y dir=out verilog_type=wire}
B 5 -42.5 -22.5 -37.5 -17.5 {name=A dir=in}
B 5 -42.5 17.5 -37.5 22.5 {name=B dir=in}
B 5 -42.5 57.5 -37.5 62.5 {name=C dir=in}
T {@name} -18.75 -5 0 0 0.2 0.2 {}
T {@symname} -15 -45 0 0 0.2 0.2 {}
T {0} -18.75 -25 0 0 0.2 0.2 {}
T {1} -18.75 15 0 0 0.2 0.2 {}