final gds oasis
diff --git a/gds/user_proj_example.gds b/gds/user_proj_example.gds
deleted file mode 100644
index 8b542fd..0000000
--- a/gds/user_proj_example.gds
+++ /dev/null
Binary files differ
diff --git a/gds/user_proj_example.gds.gz b/gds/user_proj_example.gds.gz
new file mode 100644
index 0000000..c14b010
--- /dev/null
+++ b/gds/user_proj_example.gds.gz
Binary files differ
diff --git a/gds/user_project_wrapper.gds b/gds/user_project_wrapper.gds
deleted file mode 100644
index a90e82f..0000000
--- a/gds/user_project_wrapper.gds
+++ /dev/null
Binary files differ
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
new file mode 100644
index 0000000..07da4d7
--- /dev/null
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/mpw_precheck/logs/gds.info b/mpw_precheck/logs/gds.info
new file mode 100644
index 0000000..44ebb87
--- /dev/null
+++ b/mpw_precheck/logs/gds.info
@@ -0,0 +1 @@
+user_project_wrapper.gds: 3372b133a5c761f8ca13bb9929c32f761e549d75
\ No newline at end of file
diff --git a/mpw_precheck/logs/git.info b/mpw_precheck/logs/git.info
new file mode 100644
index 0000000..e50362e
--- /dev/null
+++ b/mpw_precheck/logs/git.info
@@ -0,0 +1,3 @@
+Repository: https://github.com/AllenDBoston/PMU_caravel_mpw7.git
+Branch: main
+Commit: a98d42ceb9735e29c75fba3db675698033cab1ac
diff --git a/mpw_precheck/logs/klayout_beol_check.log b/mpw_precheck/logs/klayout_beol_check.log
new file mode 100644
index 0000000..86e7132
--- /dev/null
+++ b/mpw_precheck/logs/klayout_beol_check.log
@@ -0,0 +1,1005 @@
+/opt/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::FEOL
+/opt/checks/tech-files/sky130A_mr.drc:40: warning: previous definition of FEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:54: warning: already initialized constant DRC::DRCEngine::BEOL
+/opt/checks/tech-files/sky130A_mr.drc:41: warning: previous definition of BEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/checks/tech-files/sky130A_mr.drc:42: warning: previous definition of OFFGRID was here
+/opt/checks/tech-files/sky130A_mr.drc:68: warning: already initialized constant DRC::DRCEngine::SEAL
+/opt/checks/tech-files/sky130A_mr.drc:43: warning: previous definition of SEAL was here
+/opt/checks/tech-files/sky130A_mr.drc:74: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/opt/checks/tech-files/sky130A_mr.drc:44: warning: previous definition of FLOATING_MET was here
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+DRC section
+BEOL section
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+END: 72/20 (m5)
+START: 76/20 (pad)
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+    Edge pairs: 0 (flat)  0 (hierarchical)
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+END: 76/20 (pad)
+Writing report database: /mnt/uffs/user/u7041_allendb/design/fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/outputs/reports/klayout_beol_check.xml ..
+Total elapsed: 3911.990s  Memory: 7321.00M
+ 
+Cell exclusion list:
+   rule    | cell
+   nwell.6 | sky130_fd_io__gpiov2_amux, sky130_fd_io__simple_pad_and_busses, sram
+   nsd.1   | sram
+   nsd.2   | sram
+   psd.1   | sram
+   psd.2   | sram
+ 
+release 2022.6.30_01.07
diff --git a/mpw_precheck/logs/klayout_beol_check.total b/mpw_precheck/logs/klayout_beol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_beol_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_feol_check.log b/mpw_precheck/logs/klayout_feol_check.log
new file mode 100644
index 0000000..630905f
--- /dev/null
+++ b/mpw_precheck/logs/klayout_feol_check.log
@@ -0,0 +1,817 @@
+/opt/checks/tech-files/sky130A_mr.drc:48: warning: already initialized constant DRC::DRCEngine::FEOL
+/opt/checks/tech-files/sky130A_mr.drc:40: warning: previous definition of FEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::BEOL
+/opt/checks/tech-files/sky130A_mr.drc:41: warning: previous definition of BEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/checks/tech-files/sky130A_mr.drc:42: warning: previous definition of OFFGRID was here
+/opt/checks/tech-files/sky130A_mr.drc:68: warning: already initialized constant DRC::DRCEngine::SEAL
+/opt/checks/tech-files/sky130A_mr.drc:43: warning: previous definition of SEAL was here
+/opt/checks/tech-files/sky130A_mr.drc:74: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/opt/checks/tech-files/sky130A_mr.drc:44: warning: previous definition of FLOATING_MET was here
+"input" in: sky130A_mr.drc:124
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+"output" in: sky130A_mr.drc:375
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+    Elapsed: 0.130s  Memory: 2395.00M
+END: 89/44 (capm)
+START: 97/44 (cap2m)
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+END: 97/44 (cap2m)
+FEOL section
+START: 75/20 (hvi)
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+END: 75/20 (hvi)
+START: 125/20 (hvntm)
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+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.130s  Memory: 2395.00M
+END: 125/20 (hvntm)
+Writing report database: /mnt/uffs/user/u7041_allendb/design/fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/outputs/reports/klayout_feol_check.xml ..
+Total elapsed: 433.170s  Memory: 2371.00M
+ 
+Cell exclusion list:
+   rule    | cell
+   nwell.6 | sky130_fd_io__gpiov2_amux, sky130_fd_io__simple_pad_and_busses, sram
+   nsd.1   | sram
+   nsd.2   | sram
+   psd.1   | sram
+   psd.2   | sram
+ 
+release 2022.6.30_01.07
diff --git a/mpw_precheck/logs/klayout_feol_check.total b/mpw_precheck/logs/klayout_feol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_feol_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_met_min_ca_density_check.log b/mpw_precheck/logs/klayout_met_min_ca_density_check.log
new file mode 100644
index 0000000..22d2fdb
--- /dev/null
+++ b/mpw_precheck/logs/klayout_met_min_ca_density_check.log
@@ -0,0 +1,79 @@
+"polygons" in: met_min_ca_density.lydrc:35
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+    Elapsed: 0.590s  Memory: 1431.00M
+"polygons" in: met_min_ca_density.lydrc:36
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+    Elapsed: 0.350s  Memory: 1431.00M
+"polygons" in: met_min_ca_density.lydrc:38
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+"polygons" in: met_min_ca_density.lydrc:39
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+    Elapsed: 0.410s  Memory: 1437.00M
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+    Elapsed: 0.390s  Memory: 1456.00M
+"area" in: met_min_ca_density.lydrc:59
+    Elapsed: 76.460s  Memory: 2227.00M
+li1_ca_density is 0.4552959159402241
+"polygons" in: met_min_ca_density.lydrc:69
+    Polygons (raw): 19457156 (flat)  237811 (hierarchical)
+    Elapsed: 0.660s  Memory: 2227.00M
+"area" in: met_min_ca_density.lydrc:69
+    Elapsed: 80.270s  Memory: 2299.00M
+m1_ca_density is 0.8022285228075381
+"polygons" in: met_min_ca_density.lydrc:79
+    Polygons (raw): 1095160 (flat)  143779 (hierarchical)
+    Elapsed: 0.630s  Memory: 2299.00M
+"area" in: met_min_ca_density.lydrc:79
+    Elapsed: 5.600s  Memory: 2299.00M
+m2_ca_density is 0.979456729104238
+"polygons" in: met_min_ca_density.lydrc:89
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+    Elapsed: 0.450s  Memory: 2299.00M
+"area" in: met_min_ca_density.lydrc:89
+    Elapsed: 1.700s  Memory: 2299.00M
+m3_ca_density is 0.9942516700775412
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+    Elapsed: 0.320s  Memory: 2299.00M
+"area" in: met_min_ca_density.lydrc:99
+    Elapsed: 1.260s  Memory: 2299.00M
+m4_ca_density is 0.8429465059153176
+"polygons" in: met_min_ca_density.lydrc:109
+    Polygons (raw): 3484 (flat)  345 (hierarchical)
+    Elapsed: 0.270s  Memory: 2299.00M
+"area" in: met_min_ca_density.lydrc:109
+    Elapsed: 0.680s  Memory: 2299.00M
+m5_ca_density is 0.8455329452054794
+Writing report database: /mnt/uffs/user/u7041_allendb/design/fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/outputs/reports/klayout_met_min_ca_density_check.xml ..
+Total elapsed: 192.240s  Memory: 2275.00M
diff --git a/mpw_precheck/logs/klayout_met_min_ca_density_check.total b/mpw_precheck/logs/klayout_met_min_ca_density_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_met_min_ca_density_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_offgrid_check.log b/mpw_precheck/logs/klayout_offgrid_check.log
new file mode 100644
index 0000000..4dd6552
--- /dev/null
+++ b/mpw_precheck/logs/klayout_offgrid_check.log
@@ -0,0 +1,765 @@
+/opt/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::FEOL
+/opt/checks/tech-files/sky130A_mr.drc:40: warning: previous definition of FEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::BEOL
+/opt/checks/tech-files/sky130A_mr.drc:41: warning: previous definition of BEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:60: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/checks/tech-files/sky130A_mr.drc:42: warning: previous definition of OFFGRID was here
+/opt/checks/tech-files/sky130A_mr.drc:68: warning: already initialized constant DRC::DRCEngine::SEAL
+/opt/checks/tech-files/sky130A_mr.drc:43: warning: previous definition of SEAL was here
+/opt/checks/tech-files/sky130A_mr.drc:74: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/opt/checks/tech-files/sky130A_mr.drc:44: warning: previous definition of FLOATING_MET was here
+"input" in: sky130A_mr.drc:124
+    Polygons (raw): 6301459 (flat)  1797 (hierarchical)
+    Elapsed: 0.570s  Memory: 1434.00M
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+    Elapsed: 0.130s  Memory: 5983.00M
+"ongrid" in: sky130A_mr.drc:750
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 1.620s  Memory: 5983.00M
+"output" in: sky130A_mr.drc:750
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.130s  Memory: 5983.00M
+"with_angle" in: sky130A_mr.drc:751
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 5983.00M
+"output" in: sky130A_mr.drc:751
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.130s  Memory: 5983.00M
+"ongrid" in: sky130A_mr.drc:752
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 5.990s  Memory: 5983.00M
+"output" in: sky130A_mr.drc:752
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.130s  Memory: 5983.00M
+"with_angle" in: sky130A_mr.drc:753
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.130s  Memory: 5983.00M
+"output" in: sky130A_mr.drc:753
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.130s  Memory: 5983.00M
+"ongrid" in: sky130A_mr.drc:754
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 1.340s  Memory: 5983.00M
+"output" in: sky130A_mr.drc:754
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.130s  Memory: 5983.00M
+"with_angle" in: sky130A_mr.drc:755
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 5983.00M
+"output" in: sky130A_mr.drc:755
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.130s  Memory: 5983.00M
+"ongrid" in: sky130A_mr.drc:756
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 1.960s  Memory: 5983.00M
+"output" in: sky130A_mr.drc:756
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.130s  Memory: 5983.00M
+"with_angle" in: sky130A_mr.drc:757
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.020s  Memory: 5983.00M
+"output" in: sky130A_mr.drc:757
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.130s  Memory: 5983.00M
+"ongrid" in: sky130A_mr.drc:758
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 1.250s  Memory: 5983.00M
+"output" in: sky130A_mr.drc:758
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.130s  Memory: 5983.00M
+"with_angle" in: sky130A_mr.drc:759
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 5983.00M
+"output" in: sky130A_mr.drc:759
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.140s  Memory: 5983.00M
+"ongrid" in: sky130A_mr.drc:760
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.820s  Memory: 5983.00M
+"output" in: sky130A_mr.drc:760
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.140s  Memory: 5983.00M
+"with_angle" in: sky130A_mr.drc:761
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 5983.00M
+"output" in: sky130A_mr.drc:761
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.130s  Memory: 5983.00M
+"ongrid" in: sky130A_mr.drc:762
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 1.450s  Memory: 5983.00M
+"output" in: sky130A_mr.drc:762
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.130s  Memory: 5983.00M
+"with_angle" in: sky130A_mr.drc:763
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 5983.00M
+"output" in: sky130A_mr.drc:763
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.130s  Memory: 5983.00M
+"ongrid" in: sky130A_mr.drc:764
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 1.150s  Memory: 5983.00M
+"output" in: sky130A_mr.drc:764
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.130s  Memory: 5983.00M
+"with_angle" in: sky130A_mr.drc:765
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 5983.00M
+"output" in: sky130A_mr.drc:765
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.130s  Memory: 5983.00M
+"ongrid" in: sky130A_mr.drc:766
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.890s  Memory: 5983.00M
+"output" in: sky130A_mr.drc:766
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.130s  Memory: 5983.00M
+"with_angle" in: sky130A_mr.drc:767
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 5983.00M
+"output" in: sky130A_mr.drc:767
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.130s  Memory: 5983.00M
+"ongrid" in: sky130A_mr.drc:768
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.820s  Memory: 5983.00M
+"output" in: sky130A_mr.drc:768
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.130s  Memory: 5983.00M
+"with_angle" in: sky130A_mr.drc:769
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 5983.00M
+"output" in: sky130A_mr.drc:769
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.130s  Memory: 5983.00M
+"ongrid" in: sky130A_mr.drc:770
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.820s  Memory: 5983.00M
+"output" in: sky130A_mr.drc:770
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.130s  Memory: 5983.00M
+"with_angle" in: sky130A_mr.drc:771
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 5983.00M
+"output" in: sky130A_mr.drc:771
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.140s  Memory: 5983.00M
+"ongrid" in: sky130A_mr.drc:772
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.830s  Memory: 5983.00M
+"output" in: sky130A_mr.drc:772
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.130s  Memory: 5983.00M
+"with_angle" in: sky130A_mr.drc:773
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 5983.00M
+"output" in: sky130A_mr.drc:773
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.130s  Memory: 5983.00M
+"ongrid" in: sky130A_mr.drc:774
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.830s  Memory: 5983.00M
+"output" in: sky130A_mr.drc:774
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.130s  Memory: 5983.00M
+"with_angle" in: sky130A_mr.drc:775
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 5983.00M
+"output" in: sky130A_mr.drc:775
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.130s  Memory: 5983.00M
+"ongrid" in: sky130A_mr.drc:776
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.830s  Memory: 5983.00M
+"output" in: sky130A_mr.drc:776
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.130s  Memory: 5983.00M
+"with_angle" in: sky130A_mr.drc:777
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 5983.00M
+"output" in: sky130A_mr.drc:777
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.130s  Memory: 5983.00M
+"ongrid" in: sky130A_mr.drc:778
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.840s  Memory: 5983.00M
+"output" in: sky130A_mr.drc:778
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.130s  Memory: 5983.00M
+"with_angle" in: sky130A_mr.drc:779
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 5983.00M
+"output" in: sky130A_mr.drc:779
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.130s  Memory: 5983.00M
+"ongrid" in: sky130A_mr.drc:780
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.820s  Memory: 5983.00M
+"output" in: sky130A_mr.drc:780
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.130s  Memory: 5983.00M
+"with_angle" in: sky130A_mr.drc:781
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 5983.00M
+"output" in: sky130A_mr.drc:781
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.130s  Memory: 5983.00M
+"ongrid" in: sky130A_mr.drc:782
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.830s  Memory: 5983.00M
+"output" in: sky130A_mr.drc:782
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.130s  Memory: 5983.00M
+Writing report database: /mnt/uffs/user/u7041_allendb/design/fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/outputs/reports/klayout_offgrid_check.xml ..
+Total elapsed: 567.100s  Memory: 5831.00M
+ 
+Cell exclusion list:
+   rule    | cell
+   nwell.6 | sky130_fd_io__gpiov2_amux, sky130_fd_io__simple_pad_and_busses, sram
+   nsd.1   | sram
+   nsd.2   | sram
+   psd.1   | sram
+   psd.2   | sram
+ 
+release 2022.6.30_01.07
diff --git a/mpw_precheck/logs/klayout_offgrid_check.total b/mpw_precheck/logs/klayout_offgrid_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_offgrid_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.log b/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
new file mode 100644
index 0000000..c2c8842
--- /dev/null
+++ b/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
@@ -0,0 +1,29 @@
+Running pin_label_purposes_overlapping_drawing.rb.drc on file=/root/fpga_programming_management_unit/gds/user_project_wrapper.gds, topcell=user_project_wrapper, output to /mnt/uffs/user/u7041_allendb/design/fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
+  deep:true tiled:false threads:8
+--- #err|description, table for cell: user_project_wrapper
+NO-Check ----        pwell:64/44/EMP   122/16/dat    64/59/EMP    44/16/EMP     44/5/EMP
+         ----        nwell:64/20/dat    64/16/dat     64/5/EMP
+         ----         diff:65/20/dat    65/16/EMP     65/6/EMP
+         ----          tap:65/44/dat    65/48/EMP     65/5/EMP
+         ----         poly:66/20/dat    66/16/EMP     66/5/EMP
+         ----       licon1:66/44/dat    66/58/EMP
+         ----          li1:67/20/dat    67/16/dat     67/5/EMP
+         ----         mcon:67/44/dat    67/48/EMP
+         ----         met1:68/20/dat    68/16/dat     68/5/EMP
+         ----          via:68/44/dat    68/58/EMP
+         ----         met2:69/20/dat    69/16/dat     69/5/EMP
+         ----         via2:69/44/dat    69/58/EMP
+         ----         met3:70/20/dat    70/16/dat     70/5/EMP
+         ----         via3:70/44/dat    70/48/EMP
+         ----         met4:71/20/dat    71/16/dat     71/5/EMP
+         ----         via4:71/44/dat    71/48/EMP
+         ----         met5:72/20/dat    72/16/dat     72/5/EMP
+         ----          pad:76/20/EMP     76/5/EMP    76/16/EMP
+         ----          pnp:82/44/EMP    82/59/EMP
+         ----          npn:82/20/EMP     82/5/EMP
+         ----          rdl:74/20/EMP    74/16/EMP     74/5/EMP
+         ----     inductor:82/24/EMP    82/25/EMP
+       0 total error(s) among 0 error type(s), 33 checks, cell: user_project_wrapper
+Writing report...
+VmPeak:	 3472012 kB
+VmHWM:	 2133708 kB
diff --git a/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.total b/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_zeroarea_check.log b/mpw_precheck/logs/klayout_zeroarea_check.log
new file mode 100644
index 0000000..98e7b28
--- /dev/null
+++ b/mpw_precheck/logs/klayout_zeroarea_check.log
@@ -0,0 +1,6 @@
+writing to /mnt/uffs/user/u7041_allendb/design/fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/outputs/user_project_wrapper_no_zero_areas.gds
+0 zero-area shapes
+0 zero-length paths,  0 zero-length paths deleted.
+0 total zero-area objects,  0 total objects deleted.
+VmPeak:	 2343528 kB
+VmHWM:	 2038728 kB
diff --git a/mpw_precheck/logs/klayout_zeroarea_check.total b/mpw_precheck/logs/klayout_zeroarea_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_zeroarea_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/magic_drc_check.log b/mpw_precheck/logs/magic_drc_check.log
new file mode 100644
index 0000000..f6c217a
--- /dev/null
+++ b/mpw_precheck/logs/magic_drc_check.log
@@ -0,0 +1,28 @@
+
+Magic 8.3 revision 340 - Compiled on Thu Nov 17 13:45:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Error parsing "/opt/checks/tech-files/sky130A.magicrc": can't read "::env(PDK_PATH)": no such variable
+Bad local startup file "/opt/checks/tech-files/sky130A.magicrc", continuing without.
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/opt/checks/drc_checks/magic/magic_drc_check.tcl" from command line.
+Don't know how to read GDS-II:
+Nothing in "cifinput" section of tech file.
+[INFO]: Loading user_project_wrapper
+
+File user_project_wrapper.mag couldn't be read
+No such file or directory
+Creating new cell
+"drc(full)" is not one of the DRC styles Magic knows.
+The current style is "default".
+The DRC styles are: default.
+No errors found.
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+[INFO]: DRC Checking DONE (/mnt/uffs/user/u7041_allendb/design/fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/outputs/reports/magic_drc_check.drc.report)
+[INFO]: Saving mag view with DRC errors(/mnt/uffs/user/u7041_allendb/design/fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/outputs/user_project_wrapper.magic.drc.mag)
+[INFO]: Saved
diff --git a/mpw_precheck/logs/magic_drc_check.total b/mpw_precheck/logs/magic_drc_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/magic_drc_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/pdks.info b/mpw_precheck/logs/pdks.info
new file mode 100644
index 0000000..f65aecb
--- /dev/null
+++ b/mpw_precheck/logs/pdks.info
@@ -0,0 +1,2 @@
+Open PDKs 0059588eebfc704681dc2368bd1d33d96281d10f
+SKY130A PDK f70d8ca46961ff92719d8870a18a076370b85f6c
\ No newline at end of file
diff --git a/mpw_precheck/logs/precheck.log b/mpw_precheck/logs/precheck.log
new file mode 100644
index 0000000..c99e8b4
--- /dev/null
+++ b/mpw_precheck/logs/precheck.log
@@ -0,0 +1,76 @@
+2022-12-05 17:26:01 - [INFO] - {{Project Git Info}} Repository: https://github.com/AllenDBoston/PMU_caravel_mpw7.git | Branch: main | Commit: a98d42ceb9735e29c75fba3db675698033cab1ac
+2022-12-05 17:26:01 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: fpga_programming_management_unit
+2022-12-05 17:26:01 - [INFO] - {{Project Type Info}} digital
+2022-12-05 17:26:02 - [INFO] - {{Project GDS Info}} user_project_wrapper: 3372b133a5c761f8ca13bb9929c32f761e549d75
+2022-12-05 17:26:02 - [INFO] - {{Tools Info}} KLayout: v0.27.12 | Magic: v8.3.340
+2022-12-05 17:26:02 - [INFO] - {{PDKs Info}} SKY130A: f70d8ca46961ff92719d8870a18a076370b85f6c | Open PDKs: 0059588eebfc704681dc2368bd1d33d96281d10f
+2022-12-05 17:26:02 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/logs'
+2022-12-05 17:26:02 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, GPIO-Defines, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
+2022-12-05 17:26:02 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 14: License
+2022-12-05 17:26:03 - [INFO] - An approved LICENSE (Apache-2.0) was found in fpga_programming_management_unit.
+2022-12-05 17:26:03 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
+2022-12-05 17:26:04 - [INFO] - An approved LICENSE (Apache-2.0) was found in fpga_programming_management_unit.
+2022-12-05 17:26:04 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
+2022-12-05 17:26:14 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 2759 non-compliant file(s) with the SPDX Standard.
+2022-12-05 17:26:14 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['fpga_programming_management_unit/dependencies/pdks/volare/sky130/current', 'fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/SOURCES', 'fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/.config/nodeinfo.json', 'fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/libs.ref/sky130_fd_io/cdl/sky130_ef_io.cdl', 'fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib', 'fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_wrapped_ff_ff_100C_1v95_5v50.lib', 'fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_wrapped_ff_ff_n40C_1v95_5v50.lib', 'fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_wrapped_ff_ff_n40C_1v95_5v50_nointpwr.lib', 'fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_wrapped_ff_ss_100C_1v65_1v65.lib', 'fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_wrapped_ff_ss_100C_1v95_1v65.lib', 'fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_wrapped_ff_ss_100C_1v95_1v95.lib', 'fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_wrapped_ff_ss_n40C_1v65_1v65.lib', 'fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_wrapped_ff_ss_n40C_1v95_1v65.lib', 'fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_wrapped_ff_ss_n40C_1v95_1v95.lib', 'fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_wrapped_ss_ff_100C_1v40_5v50.lib']
+2022-12-05 17:26:14 - [INFO] - For the full SPDX compliance report check: fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/logs/spdx_compliance_report.log
+2022-12-05 17:26:14 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 14: Makefile
+2022-12-05 17:26:14 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
+2022-12-05 17:26:14 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 14: Default
+2022-12-05 17:26:14 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
+2022-12-05 17:26:16 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
+2022-12-05 17:26:16 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 14: Documentation
+2022-12-05 17:26:16 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
+2022-12-05 17:26:16 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 14: Consistency
+2022-12-05 17:26:29 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in caravel are connected to power
+2022-12-05 17:26:29 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravel netlist passed all consistency checks.
+2022-12-05 17:26:29 - [INFO] - PORTS CHECK PASSED: Netlist user_project_wrapper ports match the golden wrapper ports
+2022-12-05 17:26:29 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_project_wrapper contains at least 1 instances (304 instances). 
+2022-12-05 17:26:29 - [INFO] - MODELING CHECK PASSED: Netlist user_project_wrapper is structural.
+2022-12-05 17:26:29 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_project_wrapper matches the provided structural netlist.
+2022-12-05 17:26:29 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in user_project_wrapper are connected to power
+2022-12-05 17:26:29 - [INFO] - PORT TYPES CHECK PASSED: Netlist user_project_wrapper port types match the golden wrapper port types.
+2022-12-05 17:26:29 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_project_wrapper netlist passed all consistency checks.
+2022-12-05 17:26:30 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
+2022-12-05 17:26:30 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 14: GPIO-Defines
+2022-12-05 17:26:30 - [INFO] - GPIO-DEFINES: Checking verilog/rtl/user_defines.v, parsing files: ['/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_base.v', 'fpga_programming_management_unit/verilog/rtl/user_defines.v', '/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_observe.v']
+2022-12-05 17:26:32 - [INFO] - GPIO-DEFINES report path: fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/outputs/reports/gpio_defines.report
+2022-12-05 17:26:32 - [INFO] - {{GPIO-DEFINES CHECK PASSED}} The user verilog/rtl/user_defines.v is valid.
+2022-12-05 17:26:32 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 14: XOR
+2022-12-05 17:29:00 - [INFO] - {{XOR CHECK UPDATE}} Total XOR differences: 0, for more details view fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/outputs/user_project_wrapper.xor.gds
+2022-12-05 17:29:00 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
+2022-12-05 17:29:00 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 14: Magic DRC
+2022-12-05 17:29:02 - [INFO] - 0 DRC violations
+2022-12-05 17:29:02 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-05 17:29:02 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 14: Klayout FEOL
+2022-12-05 17:29:02 - [INFO] - in CUSTOM klayout_gds_drc_check
+2022-12-05 17:29:02 - [INFO] - run: klayout -b -r /opt/checks/tech-files/sky130A_mr.drc -rd input=fpga_programming_management_unit/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/outputs/reports/klayout_feol_check.xml -rd feol=true >& fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/logs/klayout_feol_check.log
+2022-12-05 17:35:48 - [INFO] - No DRC Violations found
+2022-12-05 17:35:48 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-05 17:35:48 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 14: Klayout BEOL
+2022-12-05 17:35:48 - [INFO] - in CUSTOM klayout_gds_drc_check
+2022-12-05 17:35:48 - [INFO] - run: klayout -b -r /opt/checks/tech-files/sky130A_mr.drc -rd input=fpga_programming_management_unit/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/outputs/reports/klayout_beol_check.xml -rd beol=true >& fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/logs/klayout_beol_check.log
+2022-12-05 18:25:41 - [INFO] - No DRC Violations found
+2022-12-05 18:25:41 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-05 18:25:41 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 14: Klayout Offgrid
+2022-12-05 18:25:41 - [INFO] - in CUSTOM klayout_gds_drc_check
+2022-12-05 18:25:41 - [INFO] - run: klayout -b -r /opt/checks/tech-files/sky130A_mr.drc -rd input=fpga_programming_management_unit/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/outputs/reports/klayout_offgrid_check.xml -rd offgrid=true >& fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/logs/klayout_offgrid_check.log
+2022-12-05 18:35:11 - [INFO] - No DRC Violations found
+2022-12-05 18:35:11 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-05 18:35:11 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 14: Klayout Metal Minimum Clear Area Density
+2022-12-05 18:35:11 - [INFO] - in CUSTOM klayout_gds_drc_check
+2022-12-05 18:35:11 - [INFO] - run: klayout -b -r /opt/checks/drc_checks/klayout/met_min_ca_density.lydrc -rd input=fpga_programming_management_unit/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/outputs/reports/klayout_met_min_ca_density_check.xml >& fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/logs/klayout_met_min_ca_density_check.log
+2022-12-05 18:38:27 - [INFO] - No DRC Violations found
+2022-12-05 18:38:27 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-05 18:38:27 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 14: Klayout Pin Label Purposes Overlapping Drawing
+2022-12-05 18:38:27 - [INFO] - in CUSTOM klayout_gds_drc_check
+2022-12-05 18:38:27 - [INFO] - run: klayout -b -r /opt/checks/drc_checks/klayout/pin_label_purposes_overlapping_drawing.rb.drc -rd input=fpga_programming_management_unit/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml -rd top_cell_name=user_project_wrapper >& fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
+2022-12-05 18:40:02 - [INFO] - No DRC Violations found
+2022-12-05 18:40:02 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-05 18:40:02 - [INFO] - {{STEP UPDATE}} Executing Check 14 of 14: Klayout ZeroArea
+2022-12-05 18:40:02 - [INFO] - in CUSTOM klayout_gds_drc_check
+2022-12-05 18:40:02 - [INFO] - run: klayout -b -r /opt/checks/drc_checks/klayout/zeroarea.rb.drc -rd input=fpga_programming_management_unit/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/outputs/reports/klayout_zeroarea_check.xml -rd cleaned_output=fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/outputs/user_project_wrapper_no_zero_areas.gds >& fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/logs/klayout_zeroarea_check.log
+2022-12-05 18:40:24 - [INFO] - No DRC Violations found
+2022-12-05 18:40:24 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-05 18:40:24 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/logs'
+2022-12-05 18:40:24 - [INFO] - {{SUCCESS}} All Checks Passed !!!
diff --git a/mpw_precheck/logs/spdx_compliance_report.log b/mpw_precheck/logs/spdx_compliance_report.log
new file mode 100644
index 0000000..44191bd
--- /dev/null
+++ b/mpw_precheck/logs/spdx_compliance_report.log
@@ -0,0 +1,2759 @@
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+/root/fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/SOURCES
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+/root/fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130B/libs.tech/xschem/stdcells/OR5.sym
+/root/fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130B/libs.tech/xschem/stdcells/OR8.sym
+/root/fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130B/libs.tech/xschem/stdcells/SDFF.sym
+/root/fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130B/libs.tech/xschem/stdcells/SDFFQ.sym
+/root/fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130B/libs.tech/xschem/stdcells/TBUF.sym
+/root/fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130B/libs.tech/xschem/stdcells/TBUFI.sym
+/root/fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130B/libs.tech/xschem/stdcells/XNOR2.sym
+/root/fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130B/libs.tech/xschem/stdcells/XOR2.sym
+/root/fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130B/libs.tech/xschem/xschem_verilog_import/audiodac.sch
+/root/fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130B/libs.tech/xschem/xschem_verilog_import/audiodac.sym
+/root/fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130B/libs.tech/xschem/xschem_verilog_import/audiodac.v
+/root/fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130B/libs.tech/xschem/xschem_verilog_import/audiodac_clean.sch
+/root/fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130B/libs.tech/xschem/xschem_verilog_import/count_nets.awk
+/root/fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130B/libs.tech/xschem/xschem_verilog_import/counter.sch
+/root/fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130B/libs.tech/xschem/xschem_verilog_import/counter.sym
+/root/fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130B/libs.tech/xschem/xschem_verilog_import/counter.v
+/root/fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130B/libs.tech/xschem/xschem_verilog_import/counter_clean.sch
+/root/fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130B/libs.tech/xschem/xschem_verilog_import/make_sky130_sch_from_spice.awk
+/root/fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130B/libs.tech/xschem/xschem_verilog_import/make_sky130_sch_from_verilog.awk
+/root/fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130B/libs.tech/xschem/xschem_verilog_import/sky130_fd_sc_hvl__lsbuflv2hv_1.sch
+/root/fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130B/libs.tech/xschem/xschem_verilog_import/sky130_fd_sc_hvl__lsbuflv2hv_1.sym
+/root/fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130B/libs.tech/xschem/xschem_verilog_import/sky130_fd_sc_hvl__lsbuflv2hv_1_redraw.sch
+/root/fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130B/libs.tech/xschem/xschem_verilog_import/sky130_fd_sc_hvl__lsbuflv2hv_1_redraw_fix.sch
+/root/fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130B/libs.tech/xschem/xschem_verilog_import/spm.sch
+/root/fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130B/libs.tech/xschem/xschem_verilog_import/spm.sym
+/root/fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130B/libs.tech/xschem/xschem_verilog_import/spm.v
+/root/fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130B/libs.tech/xschem/xschem_verilog_import/xschemrc
+/root/fpga_programming_management_unit/verilog/includes/includes.gl+sdf.caravel_user_project
+/root/fpga_programming_management_unit/verilog/includes/includes.gl.caravel_user_project
+/root/fpga_programming_management_unit/verilog/includes/includes.rtl.caravel_user_project
diff --git a/mpw_precheck/logs/tools.info b/mpw_precheck/logs/tools.info
new file mode 100644
index 0000000..4056146
--- /dev/null
+++ b/mpw_precheck/logs/tools.info
@@ -0,0 +1,2 @@
+KLayout: 0.27.12
+Magic: 8.3.340
\ No newline at end of file
diff --git a/mpw_precheck/logs/xor_check.log b/mpw_precheck/logs/xor_check.log
new file mode 100644
index 0000000..6e8caf3
--- /dev/null
+++ b/mpw_precheck/logs/xor_check.log
@@ -0,0 +1,679 @@
+Reading file /root/fpga_programming_management_unit/gds/user_project_wrapper.gds for cell user_project_wrapper
+dbu=0.0009999999999999998
+cell user_project_wrapper dbu-bbox(ll;ur)=(-43630,-38270;2963250,3557950)
+cell user_project_wrapper dbu-bbox(left,bottom,right,top)=(-43630,-38270,2963250,3557950)
+cell user_project_wrapper dbu-size(width,height)=(3006880,3596220)
+cell user_project_wrapper micron-bbox(left,bottom,right,top)=(-43.62999999999999,-38.269999999999996,2963.2499999999995,3557.9499999999994)
+cell user_project_wrapper micron-size(width,height)=(3006.879999999999,3596.2199999999993)
+Done.
+
+Magic 8.3 revision 340 - Compiled on Thu Nov 17 13:45:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/checks/xor_check/erase_box.tcl" from command line.
+CIF input style is now "sky130(vendor)"
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 6.0
+Library name: LIB
+Reading "VIA_M3M4_PR".
+Reading "VIA_M1M2_PR_MR".
+Reading "sky130_fd_sc_hd__nand3_2".
+Reading "sky130_fd_sc_hd__xor2_2".
+Reading "sky130_fd_sc_hd__ebufn_8".
+Reading "sky130_fd_sc_hd__ebufn_4".
+Reading "sky130_fd_sc_hd__and4_4".
+Reading "sky130_fd_sc_hd__ebufn_2".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__nor4b_4".
+Reading "sky130_fd_sc_hd__o32a_4".
+Reading "sky130_fd_sc_hd__o32a_2".
+Reading "sky130_fd_sc_hd__sdfrtp_1".
+Reading "sky130_fd_sc_hd__a41o_2".
+Reading "sky130_fd_sc_hd__dfstp_2".
+Reading "sky130_fd_sc_hd__or2b_4".
+Reading "sky130_fd_sc_hd__o211a_4".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__or4bb_4".
+Reading "sky130_fd_sc_hd__or4bb_2".
+Reading "sky130_fd_sc_hd__a21boi_4".
+Reading "sky130_fd_sc_hd__bufbuf_16".
+Reading "sky130_fd_sc_hd__nand2b_4".
+Reading "sky130_fd_sc_hd__a21boi_2".
+Reading "sky130_fd_sc_hd__and4bb_4".
+Reading "sky130_fd_sc_hd__nand2b_2".
+Reading "sky130_fd_sc_hd__and4bb_2".
+Reading "sky130_fd_sc_hd__inv_8".
+Reading "sky130_fd_sc_hd__inv_6".
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__inv_1".
+Reading "sky130_fd_sc_hd__o211ai_4".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__or3_4".
+Reading "sky130_fd_sc_hd__a311o_2".
+Reading "sky130_fd_sc_hd__o211ai_2".
+Reading "sky130_fd_sc_hd__a21oi_2".
+Reading "sky130_fd_sc_hd__or3_2".
+Reading "sky130_fd_sc_hd__a221o_4".
+Reading "sky130_fd_sc_hd__o31ai_4".
+Reading "sky130_fd_sc_hd__a221o_2".
+Reading "sky130_fd_sc_hd__o31ai_2".
+Reading "sky130_fd_sc_hd__or3b_4".
+Reading "sky130_fd_sc_hd__o22ai_4".
+Reading "sky130_fd_sc_hd__o41a_4".
+Reading "sky130_fd_sc_hd__or3b_2".
+Reading "sky130_fd_sc_hd__o22ai_2".
+Reading "sky130_fd_sc_hd__o41a_2".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__nor3_2".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__a221oi_4".
+Reading "sky130_fd_sc_hd__nand3b_4".
+Reading "sky130_fd_sc_hd__a221oi_2".
+Reading "sky130_fd_sc_hd__nand3b_2".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__a21bo_4".
+Reading "sky130_fd_sc_hd__a21bo_2".
+Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__a21o_2".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__and3_2".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "sky130_fd_sc_hd__o21bai_4".
+Reading "sky130_fd_sc_hd__sdfbbp_1".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__o21bai_2".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__or4b_4".
+Reading "sky130_fd_sc_hd__o2bb2a_2".
+Reading "sky130_fd_sc_hd__or4b_2".
+Reading "sky130_fd_sc_hd__o2111a_2".
+Reading "sky130_fd_sc_hd__and2b_4".
+Reading "sky130_fd_sc_hd__nand4b_4".
+Reading "sky130_fd_sc_hd__and2b_2".
+Reading "sky130_fd_sc_hd__nand4b_2".
+Reading "sky130_fd_sc_hd__o311a_4".
+Reading "sky130_fd_sc_hd__o311a_2".
+Reading "sky130_fd_sc_hd__o221a_4".
+Reading "sky130_fd_sc_hd__a22o_4".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__a22o_2".
+Reading "sky130_fd_sc_hd__inv_16".
+Reading "sky130_fd_sc_hd__inv_12".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__o21a_2".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__o221ai_4".
+Reading "sky130_fd_sc_hd__a31oi_4".
+Reading "sky130_fd_sc_hd__o221ai_2".
+Reading "sky130_fd_sc_hd__a31oi_2".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__o21ba_4".
+Reading "sky130_fd_sc_hd__a22oi_2".
+Reading "sky130_fd_sc_hd__o21ba_2".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__and3b_4".
+Reading "sky130_fd_sc_hd__a2bb2o_4".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__and3b_2".
+Reading "sky130_fd_sc_hd__a2bb2o_2".
+Reading "sky130_fd_sc_hd__o32ai_4".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__a2111o_2".
+Reading "sky130_fd_sc_hd__a2111oi_4".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__nand4_4".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__nand4_2".
+Reading "sky130_fd_sc_hd__o22a_2".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__a31o_4".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__dfrtp_2".
+Reading "sky130_fd_sc_hd__and4b_4".
+Reading "sky130_fd_sc_hd__and4b_2".
+Reading "sky130_fd_sc_hd__xnor2_4".
+Reading "sky130_fd_sc_hd__xnor2_2".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__a32o_4".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__a32o_2".
+Reading "sky130_fd_sc_hd__a211o_2".
+Reading "sky130_fd_sc_hd__o2bb2ai_4".
+Reading "sky130_fd_sc_hd__o2bb2ai_2".
+Reading "sky130_fd_sc_hd__or4_4".
+Reading "sky130_fd_sc_hd__nor3b_4".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__o31a_4".
+Reading "sky130_fd_sc_hd__or4_2".
+Reading "sky130_fd_sc_hd__nor3b_2".
+Reading "sky130_fd_sc_hd__o21ai_2".
+Reading "sky130_fd_sc_hd__o31a_2".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__a32oi_4".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__dfxtp_4".
+Reading "sky130_fd_sc_hd__a211oi_4".
+Reading "sky130_fd_sc_hd__dfxtp_2".
+Reading "sky130_fd_sc_hd__a211oi_2".
+Reading "sky130_fd_sc_hd__nor4_4".
+Reading "sky130_fd_sc_hd__nor4_2".
+Reading "sky130_fd_sc_hd__o2111ai_4".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__o2111ai_2".
+Reading "sky130_fd_sc_hd__xor2_4".
+Reading "VIA_L1M1_PR".
+Reading "VIA_M2M3_PR".
+Reading "VIA_L1M1_PR_MR".
+Reading "VIA_M1M2_PR".
+Reading "sky130_fd_sc_hd__buf_1".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "VIA_via4_3100x3100".
+Reading "VIA_via2_3_3100_480_1_9_320_320".
+Reading "VIA_via3_4_3100_480_1_7_400_400".
+Reading "VIA_via4_5_3100_480_1_7_400_400".
+Reading "sha256".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+    75000 uses
+    80000 uses
+    85000 uses
+    90000 uses
+    95000 uses
+    100000 uses
+    105000 uses
+    110000 uses
+    115000 uses
+    120000 uses
+    125000 uses
+    130000 uses
+    135000 uses
+Reading "pmu".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+Reading "fpga_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+    75000 uses
+    80000 uses
+    85000 uses
+    90000 uses
+    95000 uses
+    100000 uses
+    105000 uses
+    110000 uses
+    115000 uses
+    120000 uses
+    125000 uses
+    130000 uses
+    135000 uses
+    140000 uses
+    145000 uses
+    150000 uses
+    155000 uses
+    160000 uses
+    165000 uses
+    170000 uses
+    175000 uses
+Reading "aes".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+    75000 uses
+    80000 uses
+    85000 uses
+    90000 uses
+    95000 uses
+    100000 uses
+    105000 uses
+    110000 uses
+    115000 uses
+    120000 uses
+    125000 uses
+    130000 uses
+    135000 uses
+    140000 uses
+    145000 uses
+    150000 uses
+    155000 uses
+    160000 uses
+    165000 uses
+    170000 uses
+    175000 uses
+    180000 uses
+    185000 uses
+    190000 uses
+    195000 uses
+    200000 uses
+    205000 uses
+    210000 uses
+    215000 uses
+    220000 uses
+    225000 uses
+    230000 uses
+    235000 uses
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "user_project_wrapper".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+    75000 uses
+    80000 uses
+    85000 uses
+    90000 uses
+    95000 uses
+    100000 uses
+    105000 uses
+    110000 uses
+    115000 uses
+    120000 uses
+    125000 uses
+    130000 uses
+    135000 uses
+    140000 uses
+    145000 uses
+    150000 uses
+    155000 uses
+    160000 uses
+    165000 uses
+    170000 uses
+    175000 uses
+    180000 uses
+    185000 uses
+    190000 uses
+    195000 uses
+    200000 uses
+    205000 uses
+    210000 uses
+    215000 uses
+    220000 uses
+    225000 uses
+    230000 uses
+    235000 uses
+    240000 uses
+    245000 uses
+    250000 uses
+    255000 uses
+    260000 uses
+    265000 uses
+    270000 uses
+    275000 uses
+    280000 uses
+    285000 uses
+    290000 uses
+    295000 uses
+    300000 uses
+    305000 uses
+    310000 uses
+    315000 uses
+    320000 uses
+    325000 uses
+    330000 uses
+    335000 uses
+    340000 uses
+    345000 uses
+    350000 uses
+    355000 uses
+    360000 uses
+    365000 uses
+    370000 uses
+    375000 uses
+    380000 uses
+    385000 uses
+    390000 uses
+    395000 uses
+    400000 uses
+    405000 uses
+    410000 uses
+    415000 uses
+    420000 uses
+    425000 uses
+    430000 uses
+    435000 uses
+    440000 uses
+    445000 uses
+    450000 uses
+    455000 uses
+    460000 uses
+    465000 uses
+    470000 uses
+    475000 uses
+    480000 uses
+    485000 uses
+    490000 uses
+    495000 uses
+    500000 uses
+    505000 uses
+    510000 uses
+    515000 uses
+    520000 uses
+    525000 uses
+    530000 uses
+    535000 uses
+    540000 uses
+    545000 uses
+    550000 uses
+    555000 uses
+    560000 uses
+    565000 uses
+    570000 uses
+    575000 uses
+    580000 uses
+    585000 uses
+    590000 uses
+    595000 uses
+    600000 uses
+    605000 uses
+    610000 uses
+    615000 uses
+    620000 uses
+    625000 uses
+    630000 uses
+    635000 uses
+    640000 uses
+    645000 uses
+    650000 uses
+    655000 uses
+    660000 uses
+    665000 uses
+    670000 uses
+    675000 uses
+    680000 uses
+    685000 uses
+    690000 uses
+    695000 uses
+    700000 uses
+    705000 uses
+    710000 uses
+    715000 uses
+    720000 uses
+    725000 uses
+    730000 uses
+    735000 uses
+    740000 uses
+    745000 uses
+    750000 uses
+    755000 uses
+    760000 uses
+    765000 uses
+    770000 uses
+    775000 uses
+    780000 uses
+    785000 uses
+    790000 uses
+    795000 uses
+    800000 uses
+    805000 uses
+    810000 uses
+    815000 uses
+    820000 uses
+    825000 uses
+    830000 uses
+    835000 uses
+    840000 uses
+    845000 uses
+    850000 uses
+    855000 uses
+    860000 uses
+    865000 uses
+    870000 uses
+    875000 uses
+    880000 uses
+    885000 uses
+    890000 uses
+    895000 uses
+    900000 uses
+    905000 uses
+    910000 uses
+    915000 uses
+    920000 uses
+    925000 uses
+    930000 uses
+    935000 uses
+    940000 uses
+    945000 uses
+    950000 uses
+    955000 uses
+    960000 uses
+    965000 uses
+    970000 uses
+    975000 uses
+    980000 uses
+    985000 uses
+    990000 uses
+    995000 uses
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  42.880 x 3520.000  (-42.880,  0.000), ( 0.000,  3520.000)  150937.594
+lambda:   4288.00 x 352000.00  (-4288.00,  0.00 ), (  0.00,  352000.00)  1509376000.00
+internal:   8576 x 704000  ( -8576,  0    ), (     0,  704000)  6037504000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  42.500 x 3520.000  ( 2920.000,  0.000), ( 2962.500,  3520.000)  149600.000
+lambda:   4250.00 x 352000.00  ( 292000.00,  0.00 ), ( 296250.00,  352000.00)  1496000000.00
+internal:   8500 x 704000  ( 584000,  0    ), ( 592500,  704000)  5984000000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.380 x 37.530  (-42.880, -37.530), ( 2962.500,  0.000)  112791.906
+lambda:   300538.00 x 3753.00  (-4288.00, -3753.00), ( 296250.00,  0.00 )  1127919104.00
+internal: 601076 x 7506    ( -8576, -7506 ), ( 592500,  0    )  4511676456
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.380 x 37.210  (-42.880,  3520.000), ( 2962.500,  3557.210)  111830.188
+lambda:   300538.00 x 3721.00  (-4288.00,  352000.00), ( 296250.00,  355721.00)  1118301952.00
+internal: 601076 x 7442    ( -8576,  704000), ( 592500,  711442)  4473207592
+   Generating output for cell xor_target
+
+Magic 8.3 revision 340 - Compiled on Thu Nov 17 13:45:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/checks/xor_check/erase_box.tcl" from command line.
+CIF input style is now "sky130(vendor)"
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_project_wrapper
+Reading "user_project_wrapper".
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  42.880 x 3520.000  (-42.880,  0.000), ( 0.000,  3520.000)  150937.594
+lambda:   4288.00 x 352000.00  (-4288.00,  0.00 ), (  0.00,  352000.00)  1509376000.00
+internal:   8576 x 704000  ( -8576,  0    ), (     0,  704000)  6037504000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  42.500 x 3520.000  ( 2920.000,  0.000), ( 2962.500,  3520.000)  149600.000
+lambda:   4250.00 x 352000.00  ( 292000.00,  0.00 ), ( 296250.00,  352000.00)  1496000000.00
+internal:   8500 x 704000  ( 584000,  0    ), ( 592500,  704000)  5984000000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.380 x 37.530  (-42.880, -37.530), ( 2962.500,  0.000)  112791.906
+lambda:   300538.00 x 3753.00  (-4288.00, -3753.00), ( 296250.00,  0.00 )  1127919104.00
+internal: 601076 x 7506    ( -8576, -7506 ), ( 592500,  0    )  4511676456
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.380 x 37.210  (-42.880,  3520.000), ( 2962.500,  3557.210)  111830.188
+lambda:   300538.00 x 3721.00  (-4288.00,  352000.00), ( 296250.00,  355721.00)  1118301952.00
+internal: 601076 x 7442    ( -8576,  704000), ( 592500,  711442)  4473207592
+   Generating output for cell xor_target
+Reading /mnt/uffs/user/u7041_allendb/design/fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/outputs/user_project_wrapper_erased.gds ..
+Reading /mnt/uffs/user/u7041_allendb/design/fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/outputs/user_project_wrapper_empty_erased.gds ..
+--- Running XOR for 69/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 530 (flat)  530 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 530 (flat)  530 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+--- Running XOR for 70/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 107 (flat)  107 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 107 (flat)  107 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+--- Running XOR for 71/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 16 (flat)  16 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 16 (flat)  16 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+--- Running XOR for 71/44 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 116 (flat)  116 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 116 (flat)  116 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+--- Running XOR for 72/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 16 (flat)  16 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 16 (flat)  16 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+--- Running XOR for 81/14 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 1 (flat)  1 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 1 (flat)  1 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+Writing layout file: /mnt/uffs/user/u7041_allendb/design/fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/outputs/user_project_wrapper.xor.gds ..
+Total elapsed: 0.160s  Memory: 524.00M
diff --git a/mpw_precheck/logs/xor_check.total b/mpw_precheck/logs/xor_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/xor_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/outputs/reports/gpio_defines.report b/mpw_precheck/outputs/reports/gpio_defines.report
new file mode 100644
index 0000000..6900155
--- /dev/null
+++ b/mpw_precheck/outputs/reports/gpio_defines.report
@@ -0,0 +1,33 @@
+USER_CONFIG_GPIO_5_INIT    13'h1808
+USER_CONFIG_GPIO_6_INIT    13'h1808
+USER_CONFIG_GPIO_7_INIT    13'h1808
+USER_CONFIG_GPIO_8_INIT    13'h1808
+USER_CONFIG_GPIO_9_INIT    13'h1808
+USER_CONFIG_GPIO_10_INIT   13'h1808
+USER_CONFIG_GPIO_11_INIT   13'h1808
+USER_CONFIG_GPIO_12_INIT   13'h1808
+USER_CONFIG_GPIO_13_INIT   13'h1808
+USER_CONFIG_GPIO_14_INIT   13'h1808
+USER_CONFIG_GPIO_15_INIT   13'h1808
+USER_CONFIG_GPIO_16_INIT   13'h1808
+USER_CONFIG_GPIO_17_INIT   13'h1808
+USER_CONFIG_GPIO_18_INIT   13'h1808
+USER_CONFIG_GPIO_19_INIT   13'h1808
+USER_CONFIG_GPIO_20_INIT   13'h1808
+USER_CONFIG_GPIO_21_INIT   13'h1808
+USER_CONFIG_GPIO_22_INIT   13'h1808
+USER_CONFIG_GPIO_23_INIT   13'h1808
+USER_CONFIG_GPIO_24_INIT   13'h1808
+USER_CONFIG_GPIO_25_INIT   13'h1808
+USER_CONFIG_GPIO_26_INIT   13'h1808
+USER_CONFIG_GPIO_27_INIT   13'h1808
+USER_CONFIG_GPIO_28_INIT   13'h1808
+USER_CONFIG_GPIO_29_INIT   13'h1808
+USER_CONFIG_GPIO_30_INIT   13'h1808
+USER_CONFIG_GPIO_31_INIT   13'h1808
+USER_CONFIG_GPIO_32_INIT   13'h1808
+USER_CONFIG_GPIO_33_INIT   13'h1808
+USER_CONFIG_GPIO_34_INIT   13'h1808
+USER_CONFIG_GPIO_35_INIT   13'h1808
+USER_CONFIG_GPIO_36_INIT   13'h1808
+USER_CONFIG_GPIO_37_INIT   13'h1808
diff --git a/mpw_precheck/outputs/reports/klayout_beol_check.xml b/mpw_precheck/outputs/reports/klayout_beol_check.xml
new file mode 100644
index 0000000..5ffd971
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_beol_check.xml
@@ -0,0 +1,447 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>li.1</name>
+   <description>li.1 : min. li width : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.3</name>
+   <description>li.3 : min. li spacing : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.5</name>
+   <description>li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.6</name>
+   <description>li.6 : min. li area : 0.0561um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1</name>
+   <description>ct.1: non-ring mcon should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1_a</name>
+   <description>ct.1_a : minimum width of mcon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1_b</name>
+   <description>ct.1_b : maximum length of mcon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.2</name>
+   <description>ct.2 : min. mcon spacing : 0.19um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.4</name>
+   <description>ct.4 : mcon should covered by li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.1</name>
+   <description>m1.1 : min. m1 width : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.2</name>
+   <description>m1.2 : min. m1 spacing : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.3ab</name>
+   <description>m1.3ab : min. 3um.m1 spacing m1 : 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>791_m1.4</name>
+   <description>791_m1.4 : min. m1 enclosure of mcon : 0.03um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4</name>
+   <description>m1.4 : mcon periphery must be enclosed by m1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4a</name>
+   <description>m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4a_a</name>
+   <description>m1.4a_a : mcon periph must be enclosed by met1 for specific cells</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.6</name>
+   <description>m1.6 : min. m1 area : 0.083um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.7</name>
+   <description>m1.7 : min. m1 with holes area : 0.14um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.5</name>
+   <description>m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a</name>
+   <description>via.1a : via outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a_a</name>
+   <description>via.1a_a : min. width of via outside of moduleCut : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a_b</name>
+   <description>via.1a_b : maximum length of via : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.2</name>
+   <description>via.2 : min. via spacing : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.4a</name>
+   <description>via.4a : min. m1 enclosure of 0.15um via : 0.055um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.4a_a</name>
+   <description>via.4a_a : 0.15um via must be enclosed by met1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.5a</name>
+   <description>via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.1</name>
+   <description>m2.1 : min. m2 width : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.2</name>
+   <description>m2.2 : min. m2 spacing : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.3ab</name>
+   <description>m2.3ab : min. 3um.m2 spacing m2 : 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.6</name>
+   <description>m2.6 : min. m2 area : 0.0676um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.7</name>
+   <description>m2.7 : min. m2 holes area : 0.14um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.4</name>
+   <description>m2.4 : min. m2 enclosure of via : 0.055um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.4_a</name>
+   <description>m2.4_a : via in periphery must be enclosed by met2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.5</name>
+   <description>m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a</name>
+   <description>via2.1a : via2 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a_a</name>
+   <description>via2.1a_a : min. width of via2 outside of moduleCut : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a_b</name>
+   <description>via2.1a_b : maximum length of via2 : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.2</name>
+   <description>via2.2 : min. via2 spacing : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.4</name>
+   <description>via2.4 : min. m2 enclosure of via2 : 0.04um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.4_a</name>
+   <description>via2.4_a : via must be enclosed by met2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.5</name>
+   <description>via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.1</name>
+   <description>m3.1 : min. m3 width : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.2</name>
+   <description>m3.2 : min. m3 spacing : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.3cd</name>
+   <description>m3.3cd : min. 3um.m3 spacing m3 : 0.4um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.4</name>
+   <description>m3.4 : min. m3 enclosure of via2 : 0.065um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.4_a</name>
+   <description>m3.4_a : via2 must be enclosed by met3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1</name>
+   <description>via3.1 : via3 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1_a</name>
+   <description>via3.1_a : min. width of via3 outside of moduleCut : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1_b</name>
+   <description>via3.1_b : maximum length of via3 : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.2</name>
+   <description>via3.2 : min. via3 spacing : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.4</name>
+   <description>via3.4 : min. m3 enclosure of via3 : 0.06um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.4_a</name>
+   <description>via3.4_a : non-ring via3 must be enclosed by met3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.5</name>
+   <description>via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.1</name>
+   <description>m4.1 : min. m4 width : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.2</name>
+   <description>m4.2 : min. m4 spacing : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.4a</name>
+   <description>m4.4a : min. m4 area : 0.240um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.5ab</name>
+   <description>m4.5ab : min. 3um.m4 spacing m4 : 0.4um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.3</name>
+   <description>m4.3 : min. m4 enclosure of via3 : 0.065um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.3_a</name>
+   <description>m4.3_a : via3 must be enclosed by met4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1</name>
+   <description>via4.1 : via4 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1_a</name>
+   <description>via4.1_a : min. width of via4 outside of moduleCut : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1_b</name>
+   <description>via4.1_b : maximum length of via4 : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.2</name>
+   <description>via4.2 : min. via4 spacing : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.4</name>
+   <description>via4.4 : min. m4 enclosure of via4 : 0.19um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.4_a</name>
+   <description>via4.4_a : m4 must enclose all via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.1</name>
+   <description>m5.1 : min. m5 width : 1.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.2</name>
+   <description>m5.2 : min. m5 spacing : 1.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.3</name>
+   <description>m5.3 : min. m5 enclosure of via4 : 0.31um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.3_a</name>
+   <description>m5.3_a : via must be enclosed by m5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.4</name>
+   <description>m5.4 : min. m5 area : 4.0um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad.2</name>
+   <description>pad.2 : min. pad spacing : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_feol_check.xml b/mpw_precheck/outputs/reports/klayout_feol_check.xml
new file mode 100644
index 0000000..71b30a8
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_feol_check.xml
@@ -0,0 +1,375 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>dnwell.2</name>
+   <description>dnwell.2 : min. dnwell width : 3.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell.1</name>
+   <description>nwell.1 : min. nwell width : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell.2a</name>
+   <description>nwell.2a : min. nwell spacing (merged if less) : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell.6</name>
+   <description>nwell.6 : min enclosure of nwellHole by dnwell : 1.03um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp.1</name>
+   <description>hvtp.1 : min. hvtp width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp.2</name>
+   <description>hvtp.2 : min. hvtp spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.1</name>
+   <description>hvtr.1 : min. hvtr width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.2</name>
+   <description>hvtr.2 : min. hvtr spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.2_a</name>
+   <description>hvtr.2_a : hvtr must not overlap hvtp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn.1a</name>
+   <description>lvtn.1a : min. lvtn width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn.2</name>
+   <description>lvtn.2 : min. lvtn spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm.1</name>
+   <description>ncm.1 : min. ncm width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm.2a</name>
+   <description>ncm.2a : min. ncm spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1</name>
+   <description>difftap.1 : min. diff width across areaid:ce : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_a</name>
+   <description>difftap.1_a : min. diff width in periphery : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_b</name>
+   <description>difftap.1_b : min. tap width across areaid:ce : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_c</name>
+   <description>difftap.1_c : min. tap width in periphery : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.3</name>
+   <description>difftap.3 : min. difftap spacing : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm.1</name>
+   <description>tunm.1 : min. tunm width : 0.41um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm.2</name>
+   <description>tunm.2 : min. tunm spacing : 0.5um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly.1a</name>
+   <description>poly.1a : min. poly width : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly.2</name>
+   <description>poly.2 : min. poly spacing : 0.21um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm.1a</name>
+   <description>rpm.1a : min. rpm width : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm.2</name>
+   <description>rpm.2 : min. rpm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>urpm.1a</name>
+   <description>urpm.1a : min. rpm width : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>urpm.2</name>
+   <description>urpm.2 : min. rpm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc.1</name>
+   <description>npc.1 : min. npc width : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc.2</name>
+   <description>npc.2 : min. npc spacing, should be manually merged if less than : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsd.1</name>
+   <description>nsd.1 : min. nsdm width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsd.2</name>
+   <description>nsd.2 : min. nsdm spacing, should be manually merged if less than : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psd.1</name>
+   <description>psd.1 : min. psdm width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psd.2</name>
+   <description>psd.2 : min. psdm spacing, should be manually merged if less than : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.1</name>
+   <description>licon.1 : licon should be rectangle</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.1_a/b</name>
+   <description>licon.1_a/b : minimum/maximum width of licon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.13</name>
+   <description>licon.13 : min. difftap licon spacing to npc : 0.09um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.13_a</name>
+   <description>licon.13_a : licon of diffTap in periphery must not overlap npc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.17</name>
+   <description>licon.17 : Licons may not overlap both poly and (diff or tap)</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.1</name>
+   <description>capm.1 : min. capm width : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2a</name>
+   <description>capm.2a : min. capm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2b</name>
+   <description>capm.2b : min. capm spacing : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2b_a</name>
+   <description>capm.2b_a : min. spacing of m3_bot_plate : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.3</name>
+   <description>capm.3 : min. capm and m3 enclosure of m3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.3_a</name>
+   <description>capm.3_a : min. m3 enclosure of capm : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.4</name>
+   <description>capm.4 : min. capm enclosure of via3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.5</name>
+   <description>capm.5 : min. capm spacing to via3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.11</name>
+   <description>capm.11 : Min spacing of capm and met3 not overlapping capm : 0.5um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.1</name>
+   <description>cap2m.1 : min. cap2m width : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2a</name>
+   <description>cap2m.2a : min. cap2m spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2b</name>
+   <description>cap2m.2b : min. cap2m spacing : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2b_a</name>
+   <description>cap2m.2b_a : min. spacing of m4_bot_plate : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.3</name>
+   <description>cap2m.3 : min. m4 enclosure of cap2m : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.3_a</name>
+   <description>cap2m.3_a : min. m4 enclosure of cap2m : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.4</name>
+   <description>cap2m.4 : min. cap2m enclosure of via4 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.5</name>
+   <description>cap2m.5 : min. cap2m spacing to via4 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.11</name>
+   <description>cap2m.11 : Min spacing of cap2m and met4 not overlapping cap2m : 0.5um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi.1</name>
+   <description>hvi.1 : min. hvi width : 0.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi.2a</name>
+   <description>hvi.2a : min. hvi spacing : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm.1</name>
+   <description>hvntm.1 : min. hvntm width : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm.2</name>
+   <description>hvntm.2 : min. hvntm spacing : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_met_min_ca_density_check.xml b/mpw_precheck/outputs/reports/klayout_met_min_ca_density_check.xml
new file mode 100644
index 0000000..698a39a
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_met_min_ca_density_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>Density Checks</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/drc_checks/klayout/met_min_ca_density.lydrc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_offgrid_check.xml b/mpw_precheck/outputs/reports/klayout_offgrid_check.xml
new file mode 100644
index 0000000..95ebbc9
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_offgrid_check.xml
@@ -0,0 +1,483 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>dnwell_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on dnwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>dnwell_angle</name>
+   <description>x.3a : non 45 degree angle dnwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on nwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell_angle</name>
+   <description>x.3a : non 45 degree angle nwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwbm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pwbm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwbm_angle</name>
+   <description>x.3a : non 45 degree angle pwbm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwde_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pwde</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwde_angle</name>
+   <description>x.3a : non 45 degree angle pwde</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvtp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp_angle</name>
+   <description>x.3a : non 45 degree angle hvtp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvtr</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr_angle</name>
+   <description>x.3a : non 45 degree angle hvtr</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on lvtn</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn_angle</name>
+   <description>x.3a : non 45 degree angle lvtn</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on ncm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm_angle</name>
+   <description>x.3a : non 45 degree angle ncm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diff_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on diff</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tap_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on tap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diff_angle</name>
+   <description>x.2 : non 90 degree angle diff</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diff_angle</name>
+   <description>x.2c : non 45 degree angle diff</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tap_angle</name>
+   <description>x.2 : non 90 degree angle tap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tap_angle</name>
+   <description>x.2c : non 45 degree angle tap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on tunm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm_angle</name>
+   <description>x.3a : non 45 degree angle tunm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on poly</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly_angle</name>
+   <description>x.2 : non 90 degree angle poly</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on rpm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm_angle</name>
+   <description>x.3a : non 45 degree angle rpm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on npc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc_angle</name>
+   <description>x.3a : non 45 degree angle npc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsdm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on nsdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsdm_angle</name>
+   <description>x.3a : non 45 degree angle nsdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psdm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on psdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psdm_angle</name>
+   <description>x.3a : non 45 degree angle psdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on licon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon_angle</name>
+   <description>x.2 : non 90 degree angle licon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li_angle</name>
+   <description>x.3a : non 45 degree angle li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on mcon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct_angle</name>
+   <description>x.2 : non 90 degree angle mcon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vpp_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on vpp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vpp_angle</name>
+   <description>x.3a : non 45 degree angle vpp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1_angle</name>
+   <description>x.3a : non 45 degree angle m1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via_angle</name>
+   <description>x.2 : non 90 degree angle via</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2_angle</name>
+   <description>x.3a : non 45 degree angle m2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2_angle</name>
+   <description>x.2 : non 90 degree angle via2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3_angle</name>
+   <description>x.3a : non 45 degree angle m3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3_angle</name>
+   <description>x.2 : non 90 degree angle via3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on nsm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm_angle</name>
+   <description>x.3a : non 45 degree angle nsm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4_angle</name>
+   <description>x.3a : non 45 degree angle m4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4_angle</name>
+   <description>x.2 : non 90 degree angle via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5_angle</name>
+   <description>x.3a : non 45 degree angle m5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pad</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad_angle</name>
+   <description>x.3a : non 45 degree angle pad</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mf_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on mf</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mf_angle</name>
+   <description>x.2 : non 90 degree angle mf</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi_angle</name>
+   <description>x.3a : non 45 degree angle hvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvntm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm_angle</name>
+   <description>x.3a : non 45 degree angle hvntm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vhvi_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on vhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vhvi_angle</name>
+   <description>x.3a : non 45 degree angle vhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>uhvi_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on uhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>uhvi_angle</name>
+   <description>x.3a : non 45 degree angle uhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwell_rs_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pwell_rs</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwell_rs_angle</name>
+   <description>x.3a : non 45 degree angle pwell_rs</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>areaid_re_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on areaid.re</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml b/mpw_precheck/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
new file mode 100644
index 0000000..5e090c1
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>pin_label_purposes_overlapping_drawing.rb.drc, input=/root/fpga_programming_management_unit/gds/user_project_wrapper.gds, topcell=user_project_wrapper</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/drc_checks/klayout/pin_label_purposes_overlapping_drawing.rb.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_zeroarea_check.xml b/mpw_precheck/outputs/reports/klayout_zeroarea_check.xml
new file mode 100644
index 0000000..7f95f69
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_zeroarea_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>zero area check</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/drc_checks/klayout/zeroarea.rb.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.drc.report b/mpw_precheck/outputs/reports/magic_drc_check.drc.report
new file mode 100644
index 0000000..46ca7f3
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.drc.report
@@ -0,0 +1,5 @@
+user_project_wrapper
+----------------------------------------
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.rdb b/mpw_precheck/outputs/reports/magic_drc_check.rdb
new file mode 100644
index 0000000..ac5b3c4
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.rdb
@@ -0,0 +1,2 @@
+$user_project_wrapper
+ 100
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.tcl b/mpw_precheck/outputs/reports/magic_drc_check.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.tcl
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.tr b/mpw_precheck/outputs/reports/magic_drc_check.tr
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.tr
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.xml b/mpw_precheck/outputs/reports/magic_drc_check.xml
new file mode 100644
index 0000000..0eff265
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" ?>
+<report-database>
+    <categories/>
+    <cells>
+        <cell>
+            <name>user_project_wrapper</name>
+        </cell>
+    </cells>
+    <items/>
+</report-database>
diff --git a/mpw_precheck/outputs/user_project_wrapper.filtered.v b/mpw_precheck/outputs/user_project_wrapper.filtered.v
new file mode 100644
index 0000000..8d85d2b
--- /dev/null
+++ b/mpw_precheck/outputs/user_project_wrapper.filtered.v
@@ -0,0 +1,1565 @@
+module user_project_wrapper (user_clock2,
+    vccd1,
+    vccd2,
+    vdda1,
+    vdda2,
+    vssa1,
+    vssa2,
+    vssd1,
+    vssd2,
+    wb_clk_i,
+    wb_rst_i,
+    wbs_ack_o,
+    wbs_cyc_i,
+    wbs_stb_i,
+    wbs_we_i,
+    analog_io,
+    io_in,
+    io_oeb,
+    io_out,
+    la_data_in,
+    la_data_out,
+    la_oenb,
+    user_irq,
+    wbs_adr_i,
+    wbs_dat_i,
+    wbs_dat_o,
+    wbs_sel_i);
+ input user_clock2;
+ input vccd1;
+ input vccd2;
+ input vdda1;
+ input vdda2;
+ input vssa1;
+ input vssa2;
+ input vssd1;
+ input vssd2;
+ input wb_clk_i;
+ input wb_rst_i;
+ output wbs_ack_o;
+ input wbs_cyc_i;
+ input wbs_stb_i;
+ input wbs_we_i;
+ inout [28:0] analog_io;
+ input [37:0] io_in;
+ output [37:0] io_oeb;
+ output [37:0] io_out;
+ input [127:0] la_data_in;
+ output [127:0] la_data_out;
+ input [127:0] la_oenb;
+ output [2:0] user_irq;
+ input [31:0] wbs_adr_i;
+ input [31:0] wbs_dat_i;
+ output [31:0] wbs_dat_o;
+ input [3:0] wbs_sel_i;
+
+ wire _001_;
+ wire \aes_address_w[0] ;
+ wire \aes_address_w[1] ;
+ wire aes_init_w;
+ wire aes_next_w;
+ wire \aes_read_data_w[0] ;
+ wire \aes_read_data_w[10] ;
+ wire \aes_read_data_w[11] ;
+ wire \aes_read_data_w[12] ;
+ wire \aes_read_data_w[13] ;
+ wire \aes_read_data_w[14] ;
+ wire \aes_read_data_w[15] ;
+ wire \aes_read_data_w[16] ;
+ wire \aes_read_data_w[17] ;
+ wire \aes_read_data_w[18] ;
+ wire \aes_read_data_w[19] ;
+ wire \aes_read_data_w[1] ;
+ wire \aes_read_data_w[20] ;
+ wire \aes_read_data_w[21] ;
+ wire \aes_read_data_w[22] ;
+ wire \aes_read_data_w[23] ;
+ wire \aes_read_data_w[24] ;
+ wire \aes_read_data_w[25] ;
+ wire \aes_read_data_w[26] ;
+ wire \aes_read_data_w[27] ;
+ wire \aes_read_data_w[28] ;
+ wire \aes_read_data_w[29] ;
+ wire \aes_read_data_w[2] ;
+ wire \aes_read_data_w[30] ;
+ wire \aes_read_data_w[31] ;
+ wire \aes_read_data_w[3] ;
+ wire \aes_read_data_w[4] ;
+ wire \aes_read_data_w[5] ;
+ wire \aes_read_data_w[6] ;
+ wire \aes_read_data_w[7] ;
+ wire \aes_read_data_w[8] ;
+ wire \aes_read_data_w[9] ;
+ wire aes_ready_w;
+ wire aes_reset_dec_w;
+ wire aes_reset_n_w;
+ wire aes_wc_w;
+ wire aes_we_w;
+ wire \aes_write_data_w[0] ;
+ wire \aes_write_data_w[10] ;
+ wire \aes_write_data_w[11] ;
+ wire \aes_write_data_w[12] ;
+ wire \aes_write_data_w[13] ;
+ wire \aes_write_data_w[14] ;
+ wire \aes_write_data_w[15] ;
+ wire \aes_write_data_w[16] ;
+ wire \aes_write_data_w[17] ;
+ wire \aes_write_data_w[18] ;
+ wire \aes_write_data_w[19] ;
+ wire \aes_write_data_w[1] ;
+ wire \aes_write_data_w[20] ;
+ wire \aes_write_data_w[21] ;
+ wire \aes_write_data_w[22] ;
+ wire \aes_write_data_w[23] ;
+ wire \aes_write_data_w[24] ;
+ wire \aes_write_data_w[25] ;
+ wire \aes_write_data_w[26] ;
+ wire \aes_write_data_w[27] ;
+ wire \aes_write_data_w[28] ;
+ wire \aes_write_data_w[29] ;
+ wire \aes_write_data_w[2] ;
+ wire \aes_write_data_w[30] ;
+ wire \aes_write_data_w[31] ;
+ wire \aes_write_data_w[3] ;
+ wire \aes_write_data_w[4] ;
+ wire \aes_write_data_w[5] ;
+ wire \aes_write_data_w[6] ;
+ wire \aes_write_data_w[7] ;
+ wire \aes_write_data_w[8] ;
+ wire \aes_write_data_w[9] ;
+ wire clknet_0_user_clock2;
+ wire clknet_1_0_0_user_clock2;
+ wire clknet_1_0_1_user_clock2;
+ wire clknet_1_0_2_user_clock2;
+ wire clknet_1_0_3_user_clock2;
+ wire clknet_1_1_0_user_clock2;
+ wire clknet_1_1_1_user_clock2;
+ wire clknet_1_1_2_user_clock2;
+ wire clknet_1_1_3_user_clock2;
+ wire net1;
+ wire net10;
+ wire net11;
+ wire net12;
+ wire net13;
+ wire net14;
+ wire net15;
+ wire net16;
+ wire net17;
+ wire net18;
+ wire net19;
+ wire net2;
+ wire net20;
+ wire net21;
+ wire net22;
+ wire net23;
+ wire net24;
+ wire net25;
+ wire net26;
+ wire net27;
+ wire net28;
+ wire net29;
+ wire net3;
+ wire net30;
+ wire net31;
+ wire net32;
+ wire net33;
+ wire net34;
+ wire net35;
+ wire net36;
+ wire net37;
+ wire net38;
+ wire net39;
+ wire net4;
+ wire net40;
+ wire net41;
+ wire net42;
+ wire net43;
+ wire net44;
+ wire net45;
+ wire net46;
+ wire net47;
+ wire net48;
+ wire net49;
+ wire net5;
+ wire net50;
+ wire net51;
+ wire net52;
+ wire net53;
+ wire net54;
+ wire net55;
+ wire net56;
+ wire net57;
+ wire net58;
+ wire net59;
+ wire net6;
+ wire net60;
+ wire net61;
+ wire net62;
+ wire net63;
+ wire net64;
+ wire net65;
+ wire net66;
+ wire net67;
+ wire net68;
+ wire net69;
+ wire net7;
+ wire net70;
+ wire net71;
+ wire net72;
+ wire net73;
+ wire net74;
+ wire net75;
+ wire net76;
+ wire net77;
+ wire net78;
+ wire net79;
+ wire net8;
+ wire net80;
+ wire net81;
+ wire net82;
+ wire net83;
+ wire net84;
+ wire net85;
+ wire net86;
+ wire net87;
+ wire net88;
+ wire net89;
+ wire net9;
+ wire net90;
+ wire \sha_address_w[0] ;
+ wire \sha_address_w[1] ;
+ wire \sha_address_w[2] ;
+ wire sha_cs_w;
+ wire sha_reset_n_w;
+ wire sha_wc_w;
+ wire sha_we_w;
+ wire \sha_write_data_w[0] ;
+ wire \sha_write_data_w[10] ;
+ wire \sha_write_data_w[11] ;
+ wire \sha_write_data_w[12] ;
+ wire \sha_write_data_w[13] ;
+ wire \sha_write_data_w[14] ;
+ wire \sha_write_data_w[15] ;
+ wire \sha_write_data_w[16] ;
+ wire \sha_write_data_w[17] ;
+ wire \sha_write_data_w[18] ;
+ wire \sha_write_data_w[19] ;
+ wire \sha_write_data_w[1] ;
+ wire \sha_write_data_w[20] ;
+ wire \sha_write_data_w[21] ;
+ wire \sha_write_data_w[22] ;
+ wire \sha_write_data_w[23] ;
+ wire \sha_write_data_w[24] ;
+ wire \sha_write_data_w[25] ;
+ wire \sha_write_data_w[26] ;
+ wire \sha_write_data_w[27] ;
+ wire \sha_write_data_w[28] ;
+ wire \sha_write_data_w[29] ;
+ wire \sha_write_data_w[2] ;
+ wire \sha_write_data_w[30] ;
+ wire \sha_write_data_w[31] ;
+ wire \sha_write_data_w[3] ;
+ wire \sha_write_data_w[4] ;
+ wire \sha_write_data_w[5] ;
+ wire \sha_write_data_w[6] ;
+ wire \sha_write_data_w[7] ;
+ wire \sha_write_data_w[8] ;
+ wire \sha_write_data_w[9] ;
+ sky130_fd_sc_hd__and2_2 _184_ (.A(net79),
+    .B(clknet_1_0_3_user_clock2),
+    .X(_001_),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _185_ (.LO(io_oeb[34]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _186_ (.LO(io_oeb[35]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _187_ (.LO(io_oeb[36]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _188_ (.LO(io_oeb[37]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _189_ (.LO(io_out[36]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _190_ (.LO(io_out[37]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _191_ (.LO(la_data_out[0]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _192_ (.LO(la_data_out[1]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _193_ (.LO(la_data_out[2]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _194_ (.LO(la_data_out[3]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _195_ (.LO(la_data_out[4]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _196_ (.LO(la_data_out[5]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _197_ (.LO(la_data_out[6]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _198_ (.LO(la_data_out[7]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _199_ (.LO(la_data_out[8]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _200_ (.LO(la_data_out[9]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _201_ (.LO(la_data_out[10]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _202_ (.LO(la_data_out[11]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _203_ (.LO(la_data_out[12]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _204_ (.LO(la_data_out[13]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _205_ (.LO(la_data_out[14]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _206_ (.LO(la_data_out[15]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _207_ (.LO(la_data_out[16]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _208_ (.LO(la_data_out[17]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _209_ (.LO(la_data_out[18]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _210_ (.LO(la_data_out[19]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _211_ (.LO(la_data_out[20]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _212_ (.LO(la_data_out[21]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _213_ (.LO(la_data_out[22]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _214_ (.LO(la_data_out[23]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _215_ (.LO(la_data_out[24]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _216_ (.LO(la_data_out[25]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _217_ (.LO(la_data_out[26]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _218_ (.LO(la_data_out[27]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _219_ (.LO(la_data_out[28]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _220_ (.LO(la_data_out[29]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _221_ (.LO(la_data_out[30]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _222_ (.LO(la_data_out[31]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _223_ (.LO(la_data_out[32]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _224_ (.LO(la_data_out[33]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _225_ (.LO(la_data_out[34]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _226_ (.LO(la_data_out[35]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _227_ (.LO(la_data_out[36]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _228_ (.LO(la_data_out[37]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _229_ (.LO(la_data_out[38]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _230_ (.LO(la_data_out[39]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _231_ (.LO(la_data_out[40]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _232_ (.LO(la_data_out[41]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _233_ (.LO(la_data_out[42]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _234_ (.LO(la_data_out[43]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _235_ (.LO(la_data_out[44]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _236_ (.LO(la_data_out[45]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _237_ (.LO(la_data_out[46]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _238_ (.LO(la_data_out[47]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _239_ (.LO(la_data_out[48]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _240_ (.LO(la_data_out[49]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _241_ (.LO(la_data_out[50]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _242_ (.LO(la_data_out[51]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _243_ (.LO(la_data_out[52]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _244_ (.LO(la_data_out[53]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _245_ (.LO(la_data_out[54]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _246_ (.LO(la_data_out[55]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _247_ (.LO(la_data_out[56]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _248_ (.LO(la_data_out[57]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _249_ (.LO(la_data_out[58]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _250_ (.LO(la_data_out[59]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _251_ (.LO(la_data_out[60]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _252_ (.LO(la_data_out[61]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _253_ (.LO(la_data_out[62]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _254_ (.LO(la_data_out[63]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _255_ (.LO(la_data_out[64]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _256_ (.LO(la_data_out[65]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _257_ (.LO(la_data_out[66]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _258_ (.LO(la_data_out[67]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _259_ (.LO(la_data_out[68]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _260_ (.LO(la_data_out[69]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _261_ (.LO(la_data_out[70]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _262_ (.LO(la_data_out[71]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _263_ (.LO(la_data_out[72]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _264_ (.LO(la_data_out[73]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _265_ (.LO(la_data_out[74]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _266_ (.LO(la_data_out[75]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _267_ (.LO(la_data_out[76]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _268_ (.LO(la_data_out[77]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _269_ (.LO(la_data_out[78]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _270_ (.LO(la_data_out[79]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _271_ (.LO(la_data_out[80]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _272_ (.LO(la_data_out[81]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _273_ (.LO(la_data_out[82]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _274_ (.LO(la_data_out[83]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _275_ (.LO(la_data_out[84]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _276_ (.LO(la_data_out[85]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _277_ (.LO(la_data_out[86]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _278_ (.LO(la_data_out[87]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _279_ (.LO(la_data_out[88]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _280_ (.LO(la_data_out[89]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _281_ (.LO(la_data_out[90]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _282_ (.LO(la_data_out[91]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _283_ (.LO(la_data_out[92]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _284_ (.LO(la_data_out[93]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _285_ (.LO(la_data_out[94]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _286_ (.LO(la_data_out[95]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _287_ (.LO(la_data_out[96]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _288_ (.LO(la_data_out[97]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _289_ (.LO(la_data_out[98]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _290_ (.LO(la_data_out[99]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _291_ (.LO(la_data_out[100]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _292_ (.LO(la_data_out[101]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _293_ (.LO(la_data_out[102]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _294_ (.LO(la_data_out[103]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _295_ (.LO(la_data_out[104]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _296_ (.LO(la_data_out[105]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _297_ (.LO(la_data_out[106]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _298_ (.LO(la_data_out[107]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _299_ (.LO(la_data_out[108]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _300_ (.LO(la_data_out[109]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _301_ (.LO(la_data_out[110]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _302_ (.LO(la_data_out[111]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _303_ (.LO(la_data_out[112]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _304_ (.LO(la_data_out[113]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _305_ (.LO(la_data_out[114]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _306_ (.LO(la_data_out[115]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _307_ (.LO(la_data_out[116]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _308_ (.LO(la_data_out[117]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _309_ (.LO(la_data_out[118]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _310_ (.LO(la_data_out[119]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _311_ (.LO(la_data_out[120]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _312_ (.LO(la_data_out[121]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _313_ (.LO(la_data_out[122]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _314_ (.LO(la_data_out[123]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _315_ (.LO(la_data_out[124]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _316_ (.LO(la_data_out[125]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _317_ (.LO(la_data_out[126]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _318_ (.LO(la_data_out[127]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _319_ (.LO(user_irq[0]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _320_ (.LO(user_irq[1]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _321_ (.LO(user_irq[2]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _322_ (.LO(wbs_ack_o),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _323_ (.LO(wbs_dat_o[0]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _324_ (.LO(wbs_dat_o[1]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _325_ (.LO(wbs_dat_o[2]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _326_ (.LO(wbs_dat_o[3]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _327_ (.LO(wbs_dat_o[4]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _328_ (.LO(wbs_dat_o[5]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _329_ (.LO(wbs_dat_o[6]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _330_ (.LO(wbs_dat_o[7]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _331_ (.LO(wbs_dat_o[8]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _332_ (.LO(wbs_dat_o[9]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _333_ (.LO(wbs_dat_o[10]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _334_ (.LO(wbs_dat_o[11]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _335_ (.LO(wbs_dat_o[12]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _336_ (.LO(wbs_dat_o[13]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _337_ (.LO(wbs_dat_o[14]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _338_ (.LO(wbs_dat_o[15]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _339_ (.LO(wbs_dat_o[16]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _340_ (.LO(wbs_dat_o[17]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _341_ (.LO(wbs_dat_o[18]),
+    .VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 _342_ (.LO(wbs_dat_o[19]),