| 2022-11-28 23:48:18 - [INFO] - {{Project Git Info}} Repository: https://gitlab.com/carllb52/mixed-signal-reram-mpw7-2.git | Branch: main | Commit: f68599a694b235559cbdf8ecdda08144cb44ab50 |
| 2022-11-28 23:48:18 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: mixed_signal_circuits-jun13 |
| 2022-11-28 23:48:18 - [INFO] - {{Project Type Info}} analog |
| 2022-11-28 23:48:18 - [INFO] - {{Project GDS Info}} user_analog_project_wrapper: 94b6ca623f863196471e194445b4875966ebd3c2 |
| 2022-11-28 23:48:18 - [INFO] - {{Tools Info}} KLayout: v0.27.12 | Magic: v8.3.340 |
| 2022-11-28 23:48:18 - [INFO] - {{PDKs Info}} SKY130A: f70d8ca46961ff92719d8870a18a076370b85f6c | Open PDKs: 0059588eebfc704681dc2368bd1d33d96281d10f |
| 2022-11-28 23:48:18 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'mixed_signal_circuits-jun13/jobs/mpw_precheck/6d37c5ff-fdd6-43f7-ada1-383a0cb0a5dc/logs' |
| 2022-11-28 23:48:18 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, GPIO-Defines, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea] |
| 2022-11-28 23:48:18 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 14: License |
| 2022-11-28 23:48:19 - [INFO] - An approved LICENSE (Apache-2.0) was found in mixed_signal_circuits-jun13. |
| 2022-11-28 23:48:19 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root. |
| 2022-11-28 23:48:20 - [INFO] - An approved LICENSE (Apache-2.0) was found in mixed_signal_circuits-jun13. |
| 2022-11-28 23:48:20 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules |
| 2022-11-28 23:48:20 - [ERROR] - SPDX COMPLIANCE SYMLINK FILE NOT FOUND in mixed_signal_circuits-jun13/openlane/Makefile |
| 2022-11-28 23:48:20 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 39 non-compliant file(s) with the SPDX Standard. |
| 2022-11-28 23:48:20 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['mixed_signal_circuits-jun13/netgen/sky130B_setup.tcl', 'mixed_signal_circuits-jun13/xschem/.spiceinit', 'mixed_signal_circuits-jun13/xschem/1T1R_2x2.sch', 'mixed_signal_circuits-jun13/xschem/1T1R_2x2.sym', 'mixed_signal_circuits-jun13/xschem/C4.sch', 'mixed_signal_circuits-jun13/xschem/C4.sym', 'mixed_signal_circuits-jun13/xschem/FG_pfet.sch', 'mixed_signal_circuits-jun13/xschem/FG_pfet.sym', 'mixed_signal_circuits-jun13/xschem/amux.sch', 'mixed_signal_circuits-jun13/xschem/amux.sym', 'mixed_signal_circuits-jun13/xschem/analog_wrapper_tb.sch', 'mixed_signal_circuits-jun13/xschem/example_por.sch', 'mixed_signal_circuits-jun13/xschem/example_por.sym', 'mixed_signal_circuits-jun13/xschem/example_por_tb.sch', 'mixed_signal_circuits-jun13/xschem/example_por_tb.spice.orig'] |
| 2022-11-28 23:48:20 - [INFO] - For the full SPDX compliance report check: mixed_signal_circuits-jun13/jobs/mpw_precheck/6d37c5ff-fdd6-43f7-ada1-383a0cb0a5dc/logs/spdx_compliance_report.log |
| 2022-11-28 23:48:20 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 14: Makefile |
| 2022-11-28 23:48:20 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid. |
| 2022-11-28 23:48:20 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 14: Default |
| 2022-11-28 23:48:20 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md' |
| 2022-11-28 23:48:20 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds' |
| 2022-11-28 23:48:20 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 14: Documentation |
| 2022-11-28 23:48:20 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate. |
| 2022-11-28 23:48:20 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 14: Consistency |
| 2022-11-28 23:48:22 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravan netlist passed all consistency checks. |
| 2022-11-28 23:48:22 - [INFO] - PORTS CHECK PASSED: Netlist user_analog_project_wrapper ports match the golden wrapper ports |
| 2022-11-28 23:48:22 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_analog_project_wrapper contains at least 1 instances (6 instances). |
| 2022-11-28 23:48:22 - [INFO] - MODELING CHECK PASSED: Netlist user_analog_project_wrapper is structural. |
| 2022-11-28 23:48:22 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_analog_project_wrapper matches the provided structural netlist. |
| 2022-11-28 23:48:22 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_analog_project_wrapper netlist passed all consistency checks. |
| 2022-11-28 23:48:22 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid. |
| 2022-11-28 23:48:22 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 14: GPIO-Defines |
| 2022-11-28 23:48:22 - [INFO] - GPIO-DEFINES: Checking verilog/rtl/user_defines.v, parsing files: ['/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_base.v', 'mixed_signal_circuits-jun13/verilog/rtl/user_defines.v', '/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_observe.v'] |
| 2022-11-28 23:48:23 - [INFO] - GPIO-DEFINES report path: mixed_signal_circuits-jun13/jobs/mpw_precheck/6d37c5ff-fdd6-43f7-ada1-383a0cb0a5dc/outputs/reports/gpio_defines.report |
| 2022-11-28 23:48:23 - [INFO] - {{GPIO-DEFINES CHECK PASSED}} The user verilog/rtl/user_defines.v is valid. |
| 2022-11-28 23:48:23 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 14: XOR |
| 2022-11-28 23:48:26 - [INFO] - {{XOR CHECK UPDATE}} Total XOR differences: 0, for more details view mixed_signal_circuits-jun13/jobs/mpw_precheck/6d37c5ff-fdd6-43f7-ada1-383a0cb0a5dc/outputs/user_analog_project_wrapper.xor.gds |
| 2022-11-28 23:48:26 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations. |
| 2022-11-28 23:48:26 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 14: Magic DRC |
| 2022-11-28 23:48:26 - [INFO] - 0 DRC violations |
| 2022-11-28 23:48:26 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations. |
| 2022-11-28 23:48:26 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 14: Klayout FEOL |
| 2022-11-28 23:48:26 - [INFO] - in CUSTOM klayout_gds_drc_check |
| 2022-11-28 23:48:26 - [INFO] - run: klayout -b -r /opt/checks/tech-files/sky130A_mr.drc -rd input=mixed_signal_circuits-jun13/gds/user_analog_project_wrapper.gds -rd topcell=user_analog_project_wrapper -rd report=mixed_signal_circuits-jun13/jobs/mpw_precheck/6d37c5ff-fdd6-43f7-ada1-383a0cb0a5dc/outputs/reports/klayout_feol_check.xml -rd feol=true >& mixed_signal_circuits-jun13/jobs/mpw_precheck/6d37c5ff-fdd6-43f7-ada1-383a0cb0a5dc/logs/klayout_feol_check.log |
| 2022-11-28 23:48:29 - [INFO] - No DRC Violations found |
| 2022-11-28 23:48:29 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations. |
| 2022-11-28 23:48:29 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 14: Klayout BEOL |
| 2022-11-28 23:48:29 - [INFO] - in CUSTOM klayout_gds_drc_check |
| 2022-11-28 23:48:29 - [INFO] - run: klayout -b -r /opt/checks/tech-files/sky130A_mr.drc -rd input=mixed_signal_circuits-jun13/gds/user_analog_project_wrapper.gds -rd topcell=user_analog_project_wrapper -rd report=mixed_signal_circuits-jun13/jobs/mpw_precheck/6d37c5ff-fdd6-43f7-ada1-383a0cb0a5dc/outputs/reports/klayout_beol_check.xml -rd beol=true >& mixed_signal_circuits-jun13/jobs/mpw_precheck/6d37c5ff-fdd6-43f7-ada1-383a0cb0a5dc/logs/klayout_beol_check.log |
| 2022-11-28 23:48:33 - [INFO] - No DRC Violations found |
| 2022-11-28 23:48:33 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations. |
| 2022-11-28 23:48:33 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 14: Klayout Offgrid |
| 2022-11-28 23:48:33 - [INFO] - in CUSTOM klayout_gds_drc_check |
| 2022-11-28 23:48:33 - [INFO] - run: klayout -b -r /opt/checks/tech-files/sky130A_mr.drc -rd input=mixed_signal_circuits-jun13/gds/user_analog_project_wrapper.gds -rd topcell=user_analog_project_wrapper -rd report=mixed_signal_circuits-jun13/jobs/mpw_precheck/6d37c5ff-fdd6-43f7-ada1-383a0cb0a5dc/outputs/reports/klayout_offgrid_check.xml -rd offgrid=true >& mixed_signal_circuits-jun13/jobs/mpw_precheck/6d37c5ff-fdd6-43f7-ada1-383a0cb0a5dc/logs/klayout_offgrid_check.log |
| 2022-11-28 23:48:35 - [INFO] - No DRC Violations found |
| 2022-11-28 23:48:35 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations. |
| 2022-11-28 23:48:35 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 14: Klayout Metal Minimum Clear Area Density |
| 2022-11-28 23:48:35 - [INFO] - in CUSTOM klayout_gds_drc_check |
| 2022-11-28 23:48:35 - [INFO] - run: klayout -b -r /opt/checks/drc_checks/klayout/met_min_ca_density.lydrc -rd input=mixed_signal_circuits-jun13/gds/user_analog_project_wrapper.gds -rd topcell=user_analog_project_wrapper -rd report=mixed_signal_circuits-jun13/jobs/mpw_precheck/6d37c5ff-fdd6-43f7-ada1-383a0cb0a5dc/outputs/reports/klayout_met_min_ca_density_check.xml >& mixed_signal_circuits-jun13/jobs/mpw_precheck/6d37c5ff-fdd6-43f7-ada1-383a0cb0a5dc/logs/klayout_met_min_ca_density_check.log |
| 2022-11-28 23:48:36 - [INFO] - No DRC Violations found |
| 2022-11-28 23:48:36 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations. |
| 2022-11-28 23:48:36 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 14: Klayout Pin Label Purposes Overlapping Drawing |
| 2022-11-28 23:48:36 - [INFO] - in CUSTOM klayout_gds_drc_check |
| 2022-11-28 23:48:36 - [INFO] - run: klayout -b -r /opt/checks/drc_checks/klayout/pin_label_purposes_overlapping_drawing.rb.drc -rd input=mixed_signal_circuits-jun13/gds/user_analog_project_wrapper.gds -rd topcell=user_analog_project_wrapper -rd report=mixed_signal_circuits-jun13/jobs/mpw_precheck/6d37c5ff-fdd6-43f7-ada1-383a0cb0a5dc/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml -rd top_cell_name=user_analog_project_wrapper >& mixed_signal_circuits-jun13/jobs/mpw_precheck/6d37c5ff-fdd6-43f7-ada1-383a0cb0a5dc/logs/klayout_pin_label_purposes_overlapping_drawing_check.log |
| 2022-11-28 23:48:38 - [INFO] - No DRC Violations found |
| 2022-11-28 23:48:38 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations. |
| 2022-11-28 23:48:38 - [INFO] - {{STEP UPDATE}} Executing Check 14 of 14: Klayout ZeroArea |
| 2022-11-28 23:48:38 - [INFO] - in CUSTOM klayout_gds_drc_check |
| 2022-11-28 23:48:38 - [INFO] - run: klayout -b -r /opt/checks/drc_checks/klayout/zeroarea.rb.drc -rd input=mixed_signal_circuits-jun13/gds/user_analog_project_wrapper.gds -rd topcell=user_analog_project_wrapper -rd report=mixed_signal_circuits-jun13/jobs/mpw_precheck/6d37c5ff-fdd6-43f7-ada1-383a0cb0a5dc/outputs/reports/klayout_zeroarea_check.xml -rd cleaned_output=mixed_signal_circuits-jun13/jobs/mpw_precheck/6d37c5ff-fdd6-43f7-ada1-383a0cb0a5dc/outputs/user_analog_project_wrapper_no_zero_areas.gds >& mixed_signal_circuits-jun13/jobs/mpw_precheck/6d37c5ff-fdd6-43f7-ada1-383a0cb0a5dc/logs/klayout_zeroarea_check.log |
| 2022-11-28 23:48:39 - [INFO] - No DRC Violations found |
| 2022-11-28 23:48:39 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations. |
| 2022-11-28 23:48:39 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'mixed_signal_circuits-jun13/jobs/mpw_precheck/6d37c5ff-fdd6-43f7-ada1-383a0cb0a5dc/logs' |
| 2022-11-28 23:48:39 - [INFO] - {{SUCCESS}} All Checks Passed !!! |
