)]}'
{
  "commit": "b652c6bfd40cfe68534a987761ae244acb7b4933",
  "tree": "969abcc359ea2f4372252ec36ee90102fb94f7eb",
  "parents": [
    "5049748691c49e4c46127cda4456770410486c2e"
  ],
  "author": {
    "name": "mbaykenar",
    "email": "aykenar.burak@gmail.com",
    "time": "Mon Sep 05 13:52:30 2022 +0300"
  },
  "committer": {
    "name": "mbaykenar",
    "email": "aykenar.burak@gmail.com",
    "time": "Mon Sep 05 13:52:30 2022 +0300"
  },
  "message": "update macro wrappers and config.tcl\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "f47761b8a54fc8c8c0b8c3e5fb70bc90be3f45e5",
      "old_mode": 33261,
      "old_path": "openlane/user_project_wrapper/config.tcl",
      "new_id": "45880290cde1b0d04090a232f7a6c3d89b3d2987",
      "new_mode": 33261,
      "new_path": "openlane/user_project_wrapper/config.tcl"
    },
    {
      "type": "modify",
      "old_id": "c6ecb6f70c105e9dc245d02e34ea8f0584d1af19",
      "old_mode": 33188,
      "old_path": "verilog/rtl/rtl/axi_node_intf_wrap.v",
      "new_id": "6c406388918dc84e98a78c9332380a53b82f3a19",
      "new_mode": 33188,
      "new_path": "verilog/rtl/rtl/axi_node_intf_wrap.v"
    },
    {
      "type": "modify",
      "old_id": "4c86e2d6951fd65179456fd8ba75fbfd738be791",
      "old_mode": 33188,
      "old_path": "verilog/rtl/rtl/clk_rst_gen.v",
      "new_id": "c19e80480c28ac3acd7ad5294eee7e3d9414e522",
      "new_mode": 33188,
      "new_path": "verilog/rtl/rtl/clk_rst_gen.v"
    },
    {
      "type": "modify",
      "old_id": "c4a3e62891b00d36d3d22f366550aa4db9a4ee82",
      "old_mode": 33188,
      "old_path": "verilog/rtl/rtl/components/sky130_sram_2kbyte_1rw1r_32x512_8.v",
      "new_id": "b6bb3a107ab2d938d542378462f1a8e1a4168a21",
      "new_mode": 33188,
      "new_path": "verilog/rtl/rtl/components/sky130_sram_2kbyte_1rw1r_32x512_8.v"
    },
    {
      "type": "modify",
      "old_id": "d6d955f4e8195c22371ee9e0bccfa6aae9109c0c",
      "old_mode": 33188,
      "old_path": "verilog/rtl/rtl/mba_core_region.v",
      "new_id": "4e085200811edb27661efee168c25356c7b1089a",
      "new_mode": 33188,
      "new_path": "verilog/rtl/rtl/mba_core_region.v"
    },
    {
      "type": "modify",
      "old_id": "0658e178e8eabe2573b03ac5e729df00f1410b05",
      "old_mode": 33188,
      "old_path": "verilog/rtl/rtl/peripherals.v",
      "new_id": "0fd7055930ae952c09dff49ad4586f90aef2bedb",
      "new_mode": 33188,
      "new_path": "verilog/rtl/rtl/peripherals.v"
    },
    {
      "type": "modify",
      "old_id": "a6f406a74decfc09b071de55b827d2acb8345e4e",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "ed4a35585d5c4b889e86c60e13dc7760a1806acb",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project_wrapper.v"
    }
  ]
}
