update wrapper
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 13516ee..a37a8fd 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -509,7 +509,7 @@
.clk_standalone_i(la_data_in[1]),
.testmode_i(la_data_in[2]),
// .scan_i(1'b0),
-.scan_i(wb_dat_i[0]),
+.scan_i(io_in[21]),
.scan_o(scan_o),
.scan_en_i(la_data_in[3]),
.fll_req_i(cfgreq_fll_int),
@@ -781,7 +781,7 @@
.addr0(mba_instr_mem_addr0_o[10:2]),
.din0(mba_instr_mem_din0_o),
.dout0(mba_instr_mem_dout0_i),
- .clk1(wb_dat_i[0]),
+ .clk1(io_in[21]),
.csb1(mba_instr_mem_csb1_o),
.addr1(mba_instr_mem_addr1_o[10:2]),
.dout1(instr_ram_dout1)
@@ -800,7 +800,7 @@
.addr0(mba_data_mem_addr0_o[10:2]),
.din0(mba_data_mem_din0_o),
.dout0(mba_data_mem_dout0_i),
- .clk1(wb_dat_i[0]),
+ .clk1(io_in[21]),
.csb1(mba_data_mem_csb1_o),
.addr1(mba_data_mem_addr1_o[10:2]),
.dout1(data_ram_dout1)
@@ -881,9 +881,9 @@
.spi_sdo2_o(spi_sdo2_o),
.spi_sdo3_o(spi_sdo3_o),
.spi_sdi0_i(io_in[19]),
- .spi_sdi1_i(wb_dat_i[0]),
- .spi_sdi2_i(wb_dat_i[0]),
- .spi_sdi3_i(wb_dat_i[0]),
+ .spi_sdi1_i(io_in[21]),
+ .spi_sdi2_i(io_in[21]),
+ .spi_sdi3_i(io_in[21]),
.slave_aw_addr(slaves_02_aw_addr),
.slave_aw_prot(slaves_02_aw_prot),
.slave_aw_region(slaves_02_aw_region),
@@ -945,9 +945,9 @@
.spi_master_sdo2(spi_master_sdo2),
.spi_master_sdo3(spi_master_sdo3),
.spi_master_sdi0(io_in[21]),
- .spi_master_sdi1(wb_dat_i[0]),
- .spi_master_sdi2(wb_dat_i[0]),
- .spi_master_sdi3(wb_dat_i[0]),
+ .spi_master_sdi1(io_in[21]),
+ .spi_master_sdi2(io_in[21]),
+ .spi_master_sdi3(io_in[21]),
.scl_pad_i(io_in[22]),
.scl_pad_o(io_out[28]),
.scl_padoen_o(scl_padoen_o),
