)]}'
{
  "commit": "7d9d1a710c047929de922fcc7164b01113406ce3",
  "tree": "6b494ef427c2bba9c5b062de499e7018bb8490b2",
  "parents": [
    "65913b4f9ab11b1edb03caadd8faf297a5877552"
  ],
  "author": {
    "name": "mbaykenar",
    "email": "aykenar.burak@gmail.com",
    "time": "Thu Sep 08 14:03:40 2022 +0300"
  },
  "committer": {
    "name": "mbaykenar",
    "email": "aykenar.burak@gmail.com",
    "time": "Thu Sep 08 14:03:40 2022 +0300"
  },
  "message": "move clk_rst_gen inside peripherals\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "fd49555162ff69d2d9446052a5827f460b78c46f",
      "old_mode": 33188,
      "old_path": "verilog/rtl/rtl/clk_rst_gen.v",
      "new_id": "b81fb960257ffc87d6bc7b0093cb17eb0c7d4d51",
      "new_mode": 33188,
      "new_path": "verilog/rtl/rtl/clk_rst_gen.v"
    },
    {
      "type": "modify",
      "old_id": "0fd7055930ae952c09dff49ad4586f90aef2bedb",
      "old_mode": 33188,
      "old_path": "verilog/rtl/rtl/peripherals.v",
      "new_id": "99884df4ebf8237eb80a68b02719153f6b0873fe",
      "new_mode": 33188,
      "new_path": "verilog/rtl/rtl/peripherals.v"
    },
    {
      "type": "modify",
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      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "41299a0e5787fd3f65932f76a88d40c20ca53a04",
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      "new_path": "verilog/rtl/user_project_wrapper.v"
    }
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}