move clk_rst_gen inside peripherals
diff --git a/verilog/rtl/rtl/clk_rst_gen.v b/verilog/rtl/rtl/clk_rst_gen.v
index fd49555..b81fb96 100644
--- a/verilog/rtl/rtl/clk_rst_gen.v
+++ b/verilog/rtl/rtl/clk_rst_gen.v
@@ -1,10 +1,10 @@
//`define USE_POWER_PINS
module clk_rst_gen (
-`ifdef USE_POWER_PINS
- vccd1, // User area 1 1.8V supply
- vssd1, // User area 1 digital ground
-`endif
+//`ifdef USE_POWER_PINS
+// vccd1, // User area 1 1.8V supply
+// vssd1, // User area 1 digital ground
+//`endif
clk_i,
rstn_i,
clk_sel_i,
@@ -32,10 +32,10 @@
la_data_out
// MBA END
);
-`ifdef USE_POWER_PINS
- inout wire vccd1;
- inout wire vssd1;
-`endif
+//`ifdef USE_POWER_PINS
+// inout wire vccd1;
+// inout wire vssd1;
+//`endif
input wire clk_i;
input wire rstn_i;
input wire clk_sel_i;
diff --git a/verilog/rtl/rtl/peripherals.v b/verilog/rtl/rtl/peripherals.v
index 0fd7055..99884df 100644
--- a/verilog/rtl/rtl/peripherals.v
+++ b/verilog/rtl/rtl/peripherals.v
@@ -14,6 +14,31 @@
vccd1, // User area 1 1.8V supply
vssd1, // User area 1 digital ground
`endif
+// MBA START
+ clk_i_pll,
+ rstn_i_pll,
+ clk_sel_i_pll,
+ clk_standalone_i_pll,
+ testmode_i_pll,
+ scan_en_i_pll,
+ scan_i_pll,
+ scan_o_pll,
+ fll_req_i_pll,
+ fll_wrn_i_pll,
+ fll_add_i_pll,
+ fll_data_i_pll,
+ fll_ack_o_pll,
+ fll_r_data_o_pll,
+ fll_lock_o_pll,
+ clk_o_pll,
+ rstn_o_pll,
+ user_irq_pll,
+ io_oeb_pll,
+ io_out_pll,
+ wbs_ack_o_pll,
+ wbs_dat_o_pll,
+ la_data_out_pll,
+// MBA END
clk_i,
rst_n,
axi_spi_master_aw_addr,
@@ -183,6 +208,31 @@
inout wire vccd1;
inout wire vssd1;
`endif
+// MBA START
+ input wire clk_i_pll;
+ input wire rstn_i_pll;
+ input wire clk_sel_i_pll;
+ input wire clk_standalone_i_pll;
+ input wire testmode_i_pll;
+ input wire scan_en_i_pll;
+ input wire scan_i_pll;
+ output wire scan_o_pll;
+ input wire fll_req_i_pll;
+ input wire fll_wrn_i_pll;
+ input wire [1:0] fll_add_i_pll;
+ input wire [31:0] fll_data_i_pll;
+ output wire fll_ack_o_pll;
+ output wire [31:0] fll_r_data_o_pll;
+ output wire fll_lock_o_pll;
+ output wire clk_o_pll;
+ output wire rstn_o_pll;
+ output wire [2:0] user_irq_pll;
+ output wire [37:0] io_oeb_pll;
+ output wire [25:0] io_out_pll;
+ output wire wbs_ack_o_pll;
+ output wire [31:0] wbs_dat_o_pll;
+ output wire [63:0] la_data_out_pll;
+// MBA END
input wire clk_i;
input wire rst_n;
output wire [AXI_ADDR_WIDTH - 1:0] axi_spi_master_aw_addr;
@@ -437,6 +487,37 @@
);
end
endgenerate
+
+
+// MBA START
+ clk_rst_gen clk_rst_gen_i(
+ .clk_i(clk_i_pll),
+ .rstn_i(rstn_i_pll),
+ .clk_sel_i(clk_sel_i_pll),
+ .clk_standalone_i(clk_standalone_i_pll),
+ .testmode_i(testmode_i_pll),
+ .scan_i(scan_i_pll),
+ .scan_o(scan_o_pll),
+ .scan_en_i(scan_en_i_pll),
+ .fll_req_i(fll_req_i_pll),
+ .fll_wrn_i(fll_wrn_i_pll),
+ .fll_add_i(fll_add_i_pll),
+ .fll_data_i(fll_data_i_pll),
+ .fll_ack_o(fll_ack_o_pll),
+ .fll_r_data_o(fll_r_data_o_pll),
+ .fll_lock_o(fll_lock_o_pll),
+ .clk_o(clk_o_pll),
+ .rstn_o(rstn_o_pll),
+ .user_irq(user_irq_pll),
+ .io_oeb(io_oeb_pll),
+ .io_out(io_out_pll),
+ .wbs_ack_o(wbs_ack_o_pll),
+ .wbs_dat_o(wbs_dat_o_pll),
+ .la_data_out(la_data_out_pll)
+ );
+// MBA END
+
+
axi_spi_slave_wrap #(
.AXI_ADDRESS_WIDTH(AXI_ADDR_WIDTH),
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index e61b98f..41299a0 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -498,39 +498,38 @@
/*--------------------------------------*/
/* User project is instantiated here */
/*--------------------------------------*/
- clk_rst_gen clk_rst_gen_i(
- `ifdef USE_POWER_PINS
- .vccd1(vccd1), // User area 1 1.8V supply
- .vssd1(vssd1), // User area 1 digital ground
- `endif
- .clk_i(user_clock2),
- .rstn_i(wb_rst_i),
- .clk_sel_i(la_data_in[0]),
- .clk_standalone_i(la_data_in[1]),
- .testmode_i(la_data_in[2]),
-// .scan_i(1'b0),
-.scan_i(io_in[21]),
- .scan_o(scan_o),
- .scan_en_i(la_data_in[3]),
- .fll_req_i(cfgreq_fll_int),
- .fll_wrn_i(cfgweb_n_fll_int),
- .fll_add_i(cfgad_fll_int),
- .fll_data_i(cfgd_fll_int),
- .fll_ack_o(cfgack_fll_int),
- .fll_r_data_o(cfgq_fll_int),
- .fll_lock_o(lock_fll_int),
- .clk_o(clk_int),
- .rstn_o(rstn_int),
+// clk_rst_gen clk_rst_gen_i(
+// `ifdef USE_POWER_PINS
+// .vccd1(vccd1), // User area 1 1.8V supply
+// .vssd1(vssd1), // User area 1 digital ground
+// `endif
+// .clk_i(user_clock2),
+// .rstn_i(wb_rst_i),
+// .clk_sel_i(la_data_in[0]),
+// .clk_standalone_i(la_data_in[1]),
+// .testmode_i(la_data_in[2]),
+// .scan_i(io_in[21]),
+// .scan_o(scan_o),
+// .scan_en_i(la_data_in[3]),
+// .fll_req_i(cfgreq_fll_int),
+// .fll_wrn_i(cfgweb_n_fll_int),
+// .fll_add_i(cfgad_fll_int),
+// .fll_data_i(cfgd_fll_int),
+// .fll_ack_o(cfgack_fll_int),
+// .fll_r_data_o(cfgq_fll_int),
+// .fll_lock_o(lock_fll_int),
+// .clk_o(clk_int),
+// .rstn_o(rstn_int),
// MBA START
// constant assignments
- .user_irq(user_irq),
- .io_oeb(io_oeb),
- .io_out(io_out[25:0]),
- .wbs_ack_o(wbs_ack_o),
- .wbs_dat_o(wbs_dat_o),
- .la_data_out(la_data_out[63:0])
+// .user_irq(user_irq),
+// .io_oeb(io_oeb),
+// .io_out(io_out[25:0]),
+// .wbs_ack_o(wbs_ack_o),
+// .wbs_dat_o(wbs_dat_o),
+// .la_data_out(la_data_out[63:0])
// MBA END
- );
+// );
mba_core_region #(
.AXI_ADDR_WIDTH (`AXI_ADDR_WIDTH ),
@@ -820,6 +819,31 @@
.vccd1(vccd1),
.vssd1(vssd1),
`endif
+// MBA START
+ .clk_i_pll(user_clock2),
+ .rstn_i_pll(wb_rst_i),
+ .clk_sel_i_pll(la_data_in[0]),
+ .clk_standalone_i_pll(la_data_in[1]),
+ .testmode_i_pll(la_data_in[2]),
+ .scan_i_pll(io_in[21]),
+ .scan_o_pll(scan_o),
+ .scan_en_i_pll(la_data_in[3]),
+ .fll_req_i_pll(cfgreq_fll_int),
+ .fll_wrn_i_pll(cfgweb_n_fll_int),
+ .fll_add_i_pll(cfgad_fll_int),
+ .fll_data_i_pll(cfgd_fll_int),
+ .fll_ack_o_pll(cfgack_fll_int),
+ .fll_r_data_o_pll(cfgq_fll_int),
+ .fll_lock_o_pll(lock_fll_int),
+ .clk_o_pll(clk_int),
+ .rstn_o_pll(rstn_int),
+ .user_irq_pll(user_irq),
+ .io_oeb_pll(io_oeb),
+ .io_out_pll(io_out[25:0]),
+ .wbs_ack_o_pll(wbs_ack_o),
+ .wbs_dat_o_pll(wbs_dat_o),
+ .la_data_out_pll(la_data_out[63:0]),
+// MBA END
.clk_i(clk_int),
.rst_n(rstn_int),
.axi_spi_master_aw_addr(masters_02_aw_addr),
