)]}'
{
  "commit": "65913b4f9ab11b1edb03caadd8faf297a5877552",
  "tree": "7dfa0085cfe4fdb76aff3ed8dda626bbca2bb66f",
  "parents": [
    "860d5275fc5b5a7d75818912cdf3017261284290"
  ],
  "author": {
    "name": "mbaykenar",
    "email": "aykenar.burak@gmail.com",
    "time": "Wed Sep 07 16:27:55 2022 +0300"
  },
  "committer": {
    "name": "mbaykenar",
    "email": "aykenar.burak@gmail.com",
    "time": "Wed Sep 07 16:27:55 2022 +0300"
  },
  "message": "update wrapper\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "cfb83834157c19ea5eaa2d3c224fa52f8e0f76be",
      "old_mode": 33188,
      "old_path": "verilog/rtl/rtl/clk_rst_gen.v",
      "new_id": "fd49555162ff69d2d9446052a5827f460b78c46f",
      "new_mode": 33188,
      "new_path": "verilog/rtl/rtl/clk_rst_gen.v"
    },
    {
      "type": "modify",
      "old_id": "a37a8fd9f7f4376d8ad05cbe2f8bc1638ad9e4a1",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "e61b98ff04f1e7a4202e9d1c3908efa9e6ec06ad",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project_wrapper.v"
    }
  ]
}