diff --git a/verilog/rtl/decoder.sv b/verilog/rtl/decoder.sv
index 45e2556..9564e49 100644
--- a/verilog/rtl/decoder.sv
+++ b/verilog/rtl/decoder.sv
@@ -14,8 +14,24 @@
 module decoder #(input logic [31:0] target,
                     output logic [255:0] fullTarget);
 
-	logic [7:0] size;
-    size<=target[31:24];
+	logic [3:0] sizeTens;
+    logic [3:0] sizeOnes;
+
+    sizeTens<=target[31:28];
+    sizeOnes<=target[27:24];
+
+    //IDK if this is legal
+    integer spacing  = sizeTens*16+sizeOnes;
+
+    integer leftBuffer = 32-spacing;
+
+    //Todo figure out how to set all these values to 0
+    fullTarget[255:255-leftBuffer] = 0;
     
+    //Todo figure out how to set all these values to target[23:0]
+    fullTarget[255-leftBuffer-1:255-leftBuffer-25] = target[23:0];
+
+    fullTarget[255-leftBuffer-26:0]=0;
+
 
 endmodule