diff --git a/openlane/sha1_top/config.tcl b/openlane/sha1_top/config.tcl
index 68f34d5..81972bb 100755
--- a/openlane/sha1_top/config.tcl
+++ b/openlane/sha1_top/config.tcl
@@ -37,13 +37,13 @@
 # no matter what PL or GLB parameters I set. tried increasing both HOLD_MAX_BUFFER_PERCENT and HOLD_SLACK_MARGIN to 80% and 0.3ns
 set ::env(FP_SIZING) absolute
 # max area in wrapper: 0 0 2920 3520
-set ::env(DIE_AREA) "0 0 2900 3500"
+set ::env(DIE_AREA) "0 0 2920 3520"
 
 set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
 
 set ::env(PL_BASIC_PLACEMENT) 0
 # set ::env(PL_TARGET_DENSITY) 0.6
-set ::env(FP_CORE_UTIL) 90
+set ::env(FP_CORE_UTIL) 94
 # with 10%: detailed placement faild and had setup violations
 # with 50%: detailed placement faild and had setup violations
 # with 100% and 0.7: "Utilization exceeds 100%." Ran out of space?
@@ -281,6 +281,23 @@
 
 # DIE_AREA: "0 0 2920 3520" (absolute and commented out eerything except PL_RANDOM_GLB_PLACEMENT == 0 and all buffer % = 80)
 # with 94% and default PL_TARGET_DENSITY:
+# [STEP 21]
+# [INFO]: Running Global Routing...
+# [ERROR]: during executing openroad script /openlane/scripts/openroad/groute.tcl
+# [ERROR]: Exit code: 1
+# [ERROR]: full log: ../Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/sha1_top/runs/22_08_27_15_07/logs/routing/21-global.log
+# [ERROR]: Last 10 lines:
+# [INFO GRT-0101] Running extra iterations to remove overflow.
+# [INFO GRT-0103] Extra Run for hard benchmark.
+# [INFO GRT-0197] Via related to pin nodes: 83898
+# [INFO GRT-0198] Via related Steiner nodes: 8049
+# [INFO GRT-0199] Via filling finished.
+# [INFO GRT-0111] Final number of vias: 165868
+# [INFO GRT-0112] Final usage 3D: 949355
+# [ERROR GRT-0118] Routing congestion too high.
+# Error: groute.tcl, 55 GRT-0118
+
+
 # TODO 
 
 
diff --git a/verilog/dv/btc_miner_top_test1/btc_miner_top_test1_tb.v b/verilog/dv/btc_miner_top_test1/btc_miner_top_test1_tb.v
index 531afe1..0316a57 100644
--- a/verilog/dv/btc_miner_top_test1/btc_miner_top_test1_tb.v
+++ b/verilog/dv/btc_miner_top_test1/btc_miner_top_test1_tb.v
@@ -18,132 +18,132 @@
 `timescale 1 ns / 1 ps
 
 module btc_miner_top_test1_tb;
-	reg clock;
-	reg RSTB;
-	reg CSB;
-	reg power1, power2;
-	reg power3, power4;
+  reg clock;
+  reg RSTB;
+  reg CSB;
+  reg power1, power2;
+  reg power3, power4;
 
-	wire gpio;
-	wire [37:0] mprj_io;
-	wire [7:0] mprj_io_0;
-	wire [15:0] checkbits;
+  wire gpio;
+  wire [37:0] mprj_io;
+  wire [7:0] mprj_io_0;
+  wire [15:0] checkbits;
 
-	// TODO assign check bits
-	assign checkbits = mprj_io[31:16];
+  // TODO assign check bits
+  assign checkbits = mprj_io[31:16];
 
-	assign mprj_io[3] = 1'b1;
+  assign mprj_io[3] = 1'b1;
 
-	// External clock is used by default.  Make this artificially fast for the
-	// simulation.  Normally this would be a slow clock and the digital PLL
-	// would be the fast clock.
+  // External clock is used by default.  Make this artificially fast for the
+  // simulation.  Normally this would be a slow clock and the digital PLL
+  // would be the fast clock.
 
-	always #12.5 clock <= (clock === 1'b0);
+  always #12.5 clock <= (clock === 1'b0);
 
-	initial begin
-		clock = 0;
-	end
+  initial begin
+    clock = 0;
+  end
 
-	initial begin
-		$dumpfile("btc_miner_top_test1.vcd");
-		$dumpvars(0, btc_miner_top_test1_tb);
+  initial begin
+    $dumpfile("btc_miner_top_test1.vcd");
+    $dumpvars(0, btc_miner_top_test1_tb);
 
-		// Repeat cycles of 1000 clock edges as needed to complete testbench
-		repeat (100) begin
-			repeat (1000) @(posedge clock);
-			// $display("+1000 cycles");
-		end
-		$display("%c[1;31m",27);
-		`ifdef GL
-			$display ("Monitor: Timeout, Miner Test 1 (GL) Failed");
-		`else
-			$display ("Monitor: Timeout, Miner Test 1 (RTL) Failed");
-		`endif
-		$display("%c[0m",27);
-		$finish;
-	end
+    // Repeat cycles of 1000 clock edges as needed to complete testbench
+    repeat (100) begin
+      repeat (1000) @(posedge clock);
+      // $display("+1000 cycles");
+    end
+    $display("%c[1;31m",27);
+    `ifdef GL
+      $display ("Monitor: Timeout, Miner Test 1 (GL) Failed");
+    `else
+      $display ("Monitor: Timeout, Miner Test 1 (RTL) Failed");
+    `endif
+    $display("%c[0m",27);
+    $finish;
+  end
 
-	// TODO change finish conditions
-	initial begin
-	  wait(checkbits == 16'hFEED);
-		$display("Monitor: Miner Test 1 Started");
-		wait(checkbits == 16'hDEAD);
-		`ifdef GL
-				$display("Monitor: Miner Test 1 (GL) Passed");
-		`else
-				$display("Monitor: Miner Test 1 (RTL) Passed");
-		`endif
-			$finish;
-	end
+  // TODO change finish conditions
+  initial begin
+    wait(checkbits == 16'hFEED);
+    $display("Monitor: Miner Test 1 Started");
+    wait(checkbits == 16'hDEAD);
+    `ifdef GL
+        $display("Monitor: Miner Test 1 (GL) Passed");
+    `else
+        $display("Monitor: Miner Test 1 (RTL) Passed");
+    `endif
+      $finish;
+  end
 
-	initial begin
-		RSTB <= 1'b0;
-		CSB  <= 1'b1;		// Force CSB high
-		#2000;
-		RSTB <= 1'b1;	    	// Release reset
-		#100000;
-		CSB = 1'b0;		// CSB can be released
-	end
+  initial begin
+    RSTB <= 1'b0;
+    CSB  <= 1'b1;		// Force CSB high
+    #2000;
+    RSTB <= 1'b1;	    	// Release reset
+    #100000;
+    CSB = 1'b0;		// CSB can be released
+  end
 
-	initial begin		// Power-up sequence
-		power1 <= 1'b0;
-		power2 <= 1'b0;
-		#200;
-		power1 <= 1'b1;
-		#200;
-		power2 <= 1'b1;
-	end
+  initial begin		// Power-up sequence
+    power1 <= 1'b0;
+    power2 <= 1'b0;
+    #200;
+    power1 <= 1'b1;
+    #200;
+    power2 <= 1'b1;
+  end
 
-	wire flash_csb;
-	wire flash_clk;
-	wire flash_io0;
-	wire flash_io1;
+  wire flash_csb;
+  wire flash_clk;
+  wire flash_io0;
+  wire flash_io1;
 
-	wire VDD3V3 = power1;
-	wire VDD1V8 = power2;
-	wire USER_VDD3V3 = power3;
-	wire USER_VDD1V8 = power4;
-	wire VSS = 1'b0;
+  wire VDD3V3 = power1;
+  wire VDD1V8 = power2;
+  wire USER_VDD3V3 = power3;
+  wire USER_VDD1V8 = power4;
+  wire VSS = 1'b0;
 
-	caravel uut (
-		.vddio	  (VDD3V3),
-		.vddio_2  (VDD3V3),
-		.vssio	  (VSS),
-		.vssio_2  (VSS),
-		.vdda	  (VDD3V3),
-		.vssa	  (VSS),
-		.vccd	  (VDD1V8),
-		.vssd	  (VSS),
-		.vdda1    (VDD3V3),
-		.vdda1_2  (VDD3V3),
-		.vdda2    (VDD3V3),
-		.vssa1	  (VSS),
-		.vssa1_2  (VSS),
-		.vssa2	  (VSS),
-		.vccd1	  (VDD1V8),
-		.vccd2	  (VDD1V8),
-		.vssd1	  (VSS),
-		.vssd2	  (VSS),
-		.clock    (clock),
-		.gpio     (gpio),
-		.mprj_io  (mprj_io),
-		.flash_csb(flash_csb),
-		.flash_clk(flash_clk),
-		.flash_io0(flash_io0),
-		.flash_io1(flash_io1),
-		.resetb	  (RSTB)
-	);
+  caravel uut (
+    .vddio	  (VDD3V3),
+    .vddio_2  (VDD3V3),
+    .vssio	  (VSS),
+    .vssio_2  (VSS),
+    .vdda	  (VDD3V3),
+    .vssa	  (VSS),
+    .vccd	  (VDD1V8),
+    .vssd	  (VSS),
+    .vdda1    (VDD3V3),
+    .vdda1_2  (VDD3V3),
+    .vdda2    (VDD3V3),
+    .vssa1	  (VSS),
+    .vssa1_2  (VSS),
+    .vssa2	  (VSS),
+    .vccd1	  (VDD1V8),
+    .vccd2	  (VDD1V8),
+    .vssd1	  (VSS),
+    .vssd2	  (VSS),
+    .clock    (clock),
+    .gpio     (gpio),
+    .mprj_io  (mprj_io),
+    .flash_csb(flash_csb),
+    .flash_clk(flash_clk),
+    .flash_io0(flash_io0),
+    .flash_io1(flash_io1),
+    .resetb	  (RSTB)
+  );
 
-	spiflash #(
-		.FILENAME("btc_miner_top_test1.hex")
-	) spiflash (
-		.csb(flash_csb),
-		.clk(flash_clk),
-		.io0(flash_io0),
-		.io1(flash_io1),
-		.io2(),			// not used
-		.io3()			// not used
-	);
+  spiflash #(
+    .FILENAME("btc_miner_top_test1.hex")
+  ) spiflash (
+    .csb(flash_csb),
+    .clk(flash_clk),
+    .io0(flash_io0),
+    .io1(flash_io1),
+    .io2(),			// not used
+    .io3()			// not used
+  );
 
 endmodule
 `default_nettype wire
\ No newline at end of file
diff --git a/verilog/dv/sha1_top_test1/Makefile b/verilog/dv/sha1_top_test1/Makefile
new file mode 100644
index 0000000..2bff07e
--- /dev/null
+++ b/verilog/dv/sha1_top_test1/Makefile
@@ -0,0 +1,30 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+ 
+PWDD := $(shell pwd)
+BLOCKS := $(shell basename $(PWDD))
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+
+
+include $(MCW_ROOT)/verilog/dv/make/env.makefile
+include $(MCW_ROOT)/verilog/dv/make/var.makefile
+include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
+include $(MCW_ROOT)/verilog/dv/make/sim.makefile
diff --git a/verilog/dv/sha1_top_test1/sha1_top_test1.c b/verilog/dv/sha1_top_test1/sha1_top_test1.c
new file mode 100644
index 0000000..874aae9
--- /dev/null
+++ b/verilog/dv/sha1_top_test1/sha1_top_test1.c
@@ -0,0 +1,290 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include <defs.h>
+#include <stub.c>
+
+// constants
+#define ADDR_CTRL 0x08
+#define CTRL_INIT_BIT 0
+#define CTRL_NEXT_BIT 1
+
+#define ADDR_STATUS 0x09
+#define STATUS_READY_BIT 0
+#define STATUS_VALID_BIT 1
+
+#define ADDR_BLOCK0 0x10
+#define ADDR_BLOCK15 0x1f
+
+#define ADDR_DIGEST0 0x20
+#define ADDR_DIGEST4 0x24
+
+#define NUM_TRIALS_LIMIT 4
+
+
+/*
+	SHA1 test 1
+    - checks if automated state machine works as expected
+*/
+
+// void *memcpy(void *dest, const void *src, uint32_t n)
+// {
+//     for (uint32_t i = 0; i < n; i++)
+//     {
+//         ((char*)dest)[i] = ((char*)src)[i];
+//     }
+// }
+
+
+// void *memcpy (void *dest, const void *src, uint32_t len)
+// {
+//   char *d = dest;
+//   const char *s = src;
+//   while (len--)
+//     *d++ = *s++;
+//   return dest;
+// }
+
+
+void main()
+{
+    // boolean for validating all tests
+    uint32_t testsPassed = 1;
+    // number of trials for checking read back values
+    uint32_t num_trials = 0;
+    // temporary register value to be stored
+    uint32_t reg_val = 0;
+
+    // could put into array
+    uint32_t hash_out0 = 0;
+    uint32_t hash_out1 = 0;
+    uint32_t hash_out2 = 0;
+    uint32_t hash_out3 = 0;
+    uint32_t hash_out4 = 0;
+
+    // SHA info
+    // uint32_t index = 0;
+    // const uint32_t sha256_input[] = {
+    //     0x00000001, 0x00000002, 0x00000003, 0x00000004,
+    //     0x00000005, 0x00000006, 0x00000007, 0x00000008,
+    //     0x00000009, 0x0000000A, 0x0000000B, 0x0000000C,
+    //     0x0000000D, 0x0000000E, 0x0000000F, 0x00000010
+    // };
+
+
+	/* 
+	IO Control Registers
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
+	Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
+	
+	 
+	Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
+	*/
+
+	/* Set up the housekeeping SPI to be connected internally so	*/
+	/* that external pin changes don't affect it.			*/
+
+    reg_spi_enable = 1;
+    reg_wb_enable = 1;
+	// reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
+                                        // connect to housekeeping SPI
+
+	// Connect the housekeeping SPI to the SPI master
+	// so that the CSB line is not left floating.  This allows
+	// all of the GPIO pins to be used for user functions.
+
+    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+     /* Apply configuration */
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+
+    // LA probes [31:0] input to MGMT from USER
+    reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0]
+    // LA probes [63:32] input to MGMT from USER
+    reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32]
+    // LA probes [95:64]  input to MGMT from USER
+	reg_la2_oenb = reg_la2_iena = 0x00000000;    // [95:64]
+    // LA probes [127:96] output from MGMT into USER
+	reg_la3_oenb = reg_la3_iena = 0xFFFF3FFF;    // [127:96]
+
+    // Flag start of the test
+	reg_mprj_datal = 0xFEEDFEED;
+    // reg_mprj_datah = 0x00000000;
+
+    // set control information to SHA256: sha_init, auto_ctrl, and start_ctrl
+    // *init bit starts sha_core, but only write to control register after reading in 512-bit input!
+    reg_la3_data = 0x00010C00;
+    
+    // TODO could put in loop?
+// aa55aa55
+// deadbeef
+// 55aa55aa
+// f00ff00f
+    reg_mprj_slave = 0x0FAB0FAB;
+    // reg_mprj_slave = sha256_input[index];
+    // index++;
+    // sha_addr == ADDR_BLOCK0 && sha_we && sha_cs && sha_read_data == 0
+    // * removed because can not read register value
+    // reg_val = reg_la2_data;
+    // while ((reg_val & 0x00000FFF) != 0x310)
+    // {
+    //     num_trials++;
+    //     if (num_trials > NUM_TRIALS_LIMIT) {
+    //         // did not read input
+    //         testsPassed = testsPassed & 0;
+    //         reg_mprj_datal = 0xBAD0BAD0;
+    //         break;
+    //     }
+    //     reg_val = reg_la2_data;
+    // }
+    // num_trials = 0; // reset number of trials
+
+    // set control information to SHA256: disable start_ctrl
+    reg_la3_data = 0x00010800;
+
+    reg_mprj_slave = 0x0000F00D;
+    // reg_mprj_slave = sha256_input[index];
+    // index++;
+    // sha_addr == ADDR_BLOCK1 && sha_we && sha_cs && sha_read_data == 0
+    // * removed because can not read register value
+    // reg_val = reg_la2_data;
+    // while ((reg_val & 0x00000FFF) != 0x311)
+    // {
+    //     num_trials++;
+    //     if (num_trials > NUM_TRIALS_LIMIT) {
+    //         // did not read input
+    //         testsPassed = testsPassed & 0;
+    //         reg_mprj_datal = 0xBAD0BAD0;
+    //         break;
+    //     }
+    //     reg_val = reg_la2_data;
+    // }
+    // num_trials = 0; // reset number of trials
+
+    reg_mprj_slave = 0x0001F00D;
+    reg_mprj_slave = 0x0002F00D;
+    reg_mprj_slave = 0x0003F00D;
+    reg_mprj_slave = 0x0004F00D;
+    reg_mprj_slave = 0x0005F00D;
+    reg_mprj_slave = 0x0006F00D;
+    reg_mprj_slave = 0x0007F00D;
+    reg_mprj_slave = 0x0008F00D;
+    reg_mprj_slave = 0x0009F00D;
+    reg_mprj_slave = 0x000AF00D;
+    reg_mprj_slave = 0x000BF00D;
+    reg_mprj_slave = 0x000CF00D;
+    reg_mprj_slave = 0x000DF00D;
+    reg_mprj_slave = 0x000EF00D;
+
+    // read valid output hash (digest)
+    hash_out0 = reg_mprj_slave;
+    // reg_val = reg_la2_data;
+    // if ((reg_val & 0x00000FFF) == 0x120)
+    // {
+    //     testsPassed = testsPassed & 1;
+    // }
+    // else
+    // {
+    //     testsPassed = testsPassed & 0;
+    //     reg_mprj_datal = 0xBAD0BAD0;
+    // }
+
+    hash_out1 = reg_mprj_slave;
+    // reg_val = reg_la2_data;
+    // if ((reg_val & 0x00000FFF) == 0x121)
+    // {
+    //     testsPassed = testsPassed & 1;
+    // }
+    // else
+    // {
+    //     testsPassed = testsPassed & 0;
+    //     reg_mprj_datal = 0xBAD0BAD0;
+    // }
+
+    hash_out2 = reg_mprj_slave;
+    // reg_val = reg_la2_data;
+    // if ((reg_val & 0x00000FFF) == 0x122)
+    // {
+    //     testsPassed = testsPassed & 1;
+    // }
+    // else
+    // {
+    //     testsPassed = testsPassed & 0;
+    //     reg_mprj_datal = 0xBAD0BAD0;
+    // }
+
+    hash_out3 = reg_mprj_slave;
+    // reg_val = reg_la2_data;
+    // if ((reg_val & 0x00000FFF) == 0x123)
+    // {
+    //     testsPassed = testsPassed & 1;
+    // }
+    // else
+    // {
+    //     testsPassed = testsPassed & 0;
+    //     reg_mprj_datal = 0xBAD0BAD0;
+    // }
+
+    hash_out4 = reg_mprj_slave;
+    // reg_val = reg_la2_data;
+    // if ((reg_val & 0x00000FFF) == 0x124)
+    // {
+    //     testsPassed = testsPassed & 1;
+    // }
+    // else
+    // {
+    //     testsPassed = testsPassed & 0;
+    //     reg_mprj_datal = 0xBAD0BAD0;
+    // }
+
+    if (hash_out0 == 0x11111111) {
+        // TODO 
+    }
+
+
+    if (testsPassed)
+    {
+        // Successfully ended test
+        reg_mprj_datal = 0xDEADDEAD;
+    }
+    else
+    {
+        reg_mprj_datal = 0xBAD0BAD0;
+    }
+}
diff --git a/verilog/dv/sha1_top_test1/sha1_top_test1_tb.v b/verilog/dv/sha1_top_test1/sha1_top_test1_tb.v
new file mode 100644
index 0000000..537e048
--- /dev/null
+++ b/verilog/dv/sha1_top_test1/sha1_top_test1_tb.v
@@ -0,0 +1,244 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+module sha1_top_test1_tb;
+	reg clock;
+	reg RSTB;
+	reg CSB;
+	reg power1, power2;
+	reg power3, power4;
+
+	wire gpio;
+	wire [37:0] mprj_io;
+	wire [7:0] mprj_io_0;
+	wire [15:0] checkbits;
+
+	// TODO assign check bits
+	assign checkbits = mprj_io[31:16];
+
+	assign mprj_io[3] = 1'b1;
+
+	// External clock is used by default.  Make this artificially fast for the
+	// simulation.  Normally this would be a slow clock and the digital PLL
+	// would be the fast clock.
+
+	always #12.5 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	`ifdef ENABLE_SDF
+		initial begin
+			$sdf_annotate("../../../sdf/user_proj_example.sdf", uut.mprj) ;
+			$sdf_annotate("../../../sdf/user_project_wrapper.sdf", uut.mprj.mprj) ;
+			$sdf_annotate("../../../mgmt_core_wrapper/sdf/DFFRAM.sdf", uut.soc.DFFRAM_0) ;
+			$sdf_annotate("../../../mgmt_core_wrapper/sdf/mgmt_core.sdf", uut.soc.core) ;
+			$sdf_annotate("../../../caravel/sdf/housekeeping.sdf", uut.housekeeping) ;
+			$sdf_annotate("../../../caravel/sdf/chip_io.sdf", uut.padframe) ;
+			$sdf_annotate("../../../caravel/sdf/mprj_logic_high.sdf", uut.mgmt_buffers.mprj_logic_high_inst) ;
+			$sdf_annotate("../../../caravel/sdf/mprj2_logic_high.sdf", uut.mgmt_buffers.mprj2_logic_high_inst) ;
+			$sdf_annotate("../../../caravel/sdf/mgmt_protect_hv.sdf", uut.mgmt_buffers.powergood_check) ;
+			$sdf_annotate("../../../caravel/sdf/mgmt_protect.sdf", uut.mgmt_buffers) ;
+			$sdf_annotate("../../../caravel/sdf/caravel_clocking.sdf", uut.clocking) ;
+			$sdf_annotate("../../../caravel/sdf/digital_pll.sdf", uut.pll) ;
+			$sdf_annotate("../../../caravel/sdf/xres_buf.sdf", uut.rstb_level) ;
+			$sdf_annotate("../../../caravel/sdf/user_id_programming.sdf", uut.user_id_value) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[0] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[1] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[0] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[1] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[2] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[0] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[1] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[2] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[3] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[4] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[5] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[6] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[7] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[8] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[9] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[10] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[0] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[1] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[2] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[3] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[4] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[5] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[0] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[1] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[2] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[3] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[4] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[5] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[6] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[7] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[8] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[9] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[10] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[11] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[12] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[13] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[14] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[15] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_0[0] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_0[1] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[0] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[1] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[2] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_5) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_6) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_7) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_8) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_9) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_10) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_11) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_12) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_13) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_14) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_15) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_16) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_17) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_18) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_19) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_20) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_21) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_22) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_23) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_24) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_25) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_26) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_27) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_28) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_29) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_30) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_31) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_32) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_33) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_34) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_35) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_36) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_37) ;
+		end
+	`endif 
+
+	initial begin
+		$dumpfile("sha1_top_test1.vcd");
+		$dumpvars(0, sha1_top_test1_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (100) begin
+			repeat (1000) @(posedge clock);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, SHA1 Test 1 (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, SHA1 Test 1 (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+
+	// checking for: flag start of test bits
+	initial begin
+	  wait(checkbits == 16'hFEED);
+		$display("Monitor: SHA1 Test 1 Started");
+		wait(checkbits == 16'hDEAD);
+		`ifdef GL
+			$display("Monitor: SHA1 Test 1 (GL) Passed");
+		`else
+			$display("Monitor: SHA1 Test 1 (RTL) Passed");
+		`endif
+	    $finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		CSB  <= 1'b1;		// Force CSB high
+		#2000;
+		RSTB <= 1'b1;		// Release reset
+		#100000;
+		CSB = 1'b0;			// CSB can be released
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire VDD3V3 = power1;
+	wire VDD1V8 = power2;
+	wire USER_VDD3V3 = power3;
+	wire USER_VDD1V8 = power4;
+	wire VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vddio_2  (VDD3V3),
+		.vssio	  (VSS),
+		.vssio_2  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda1_2  (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa1_2  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock    (clock),
+		.gpio     (gpio),
+		.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("sha1_top_test1.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/sha1_top_test2/Makefile b/verilog/dv/sha1_top_test2/Makefile
new file mode 100644
index 0000000..2bff07e
--- /dev/null
+++ b/verilog/dv/sha1_top_test2/Makefile
@@ -0,0 +1,30 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+ 
+PWDD := $(shell pwd)
+BLOCKS := $(shell basename $(PWDD))
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+
+
+include $(MCW_ROOT)/verilog/dv/make/env.makefile
+include $(MCW_ROOT)/verilog/dv/make/var.makefile
+include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
+include $(MCW_ROOT)/verilog/dv/make/sim.makefile
diff --git a/verilog/dv/sha1_top_test2/sha1_top_test2.c b/verilog/dv/sha1_top_test2/sha1_top_test2.c
new file mode 100644
index 0000000..16edea8
--- /dev/null
+++ b/verilog/dv/sha1_top_test2/sha1_top_test2.c
@@ -0,0 +1,285 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include <defs.h>
+#include <stub.c>
+
+// constants
+#define ADDR_CTRL 0x08
+#define CTRL_INIT_BIT 0
+#define CTRL_NEXT_BIT 1
+
+#define ADDR_STATUS 0x09
+#define STATUS_READY_BIT 0
+#define STATUS_VALID_BIT 1
+
+#define ADDR_BLOCK0 0x10
+#define ADDR_BLOCK15 0x1f
+
+#define ADDR_DIGEST0 0x20
+#define ADDR_DIGEST4 0x24
+
+#define NUM_TRIALS_LIMIT 4
+
+/*
+    SHA1 test 2
+    - checks if automated state machine works as expected
+*/
+
+// void *memcpy(void *dest, const void *src, uint32_t n)
+// {
+//     for (uint32_t i = 0; i < n; i++)
+//     {
+//         ((char*)dest)[i] = ((char*)src)[i];
+//     }
+// }
+
+// void *memcpy (void *dest, const void *src, uint32_t len)
+// {
+//   char *d = dest;
+//   const char *s = src;
+//   while (len--)
+//     *d++ = *s++;
+//   return dest;
+// }
+
+void main()
+{
+    // boolean for validating all tests
+    uint32_t testsPassed = 1;
+    // number of trials for checking read back values
+    uint32_t num_trials = 0;
+    // temporary register value to be stored
+    uint32_t reg_val = 0;
+
+    // could put into array
+    uint32_t hash_out0 = 0;
+    uint32_t hash_out1 = 0;
+    uint32_t hash_out2 = 0;
+    uint32_t hash_out3 = 0;
+    uint32_t hash_out4 = 0;
+
+    // SHA info
+    // uint32_t index = 0;
+    // const uint32_t sha256_input[] = {
+    //     0x00000001, 0x00000002, 0x00000003, 0x00000004,
+    //     0x00000005, 0x00000006, 0x00000007, 0x00000008,
+    //     0x00000009, 0x0000000A, 0x0000000B, 0x0000000C,
+    //     0x0000000D, 0x0000000E, 0x0000000F, 0x00000010
+    // };
+
+    /*
+    IO Control Registers
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
+    Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
+
+
+    Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
+    */
+
+    /* Set up the housekeeping SPI to be connected internally so	*/
+    /* that external pin changes don't affect it.			*/
+
+    reg_spi_enable = 1;
+    reg_wb_enable = 1;
+    // reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
+    // connect to housekeeping SPI
+
+    // Connect the housekeeping SPI to the SPI master
+    // so that the CSB line is not left floating.  This allows
+    // all of the GPIO pins to be used for user functions.
+
+    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    /* Apply configuration */
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+
+    // LA probes [31:0] input to MGMT from USER
+    reg_la0_oenb = reg_la0_iena = 0x00000000; // [31:0]
+    // LA probes [63:32] input to MGMT from USER
+    reg_la1_oenb = reg_la1_iena = 0x00000000; // [63:32]
+                                              // LA probes [95:64]  input to MGMT from USER
+    reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64]
+                                              // LA probes [127:96] output from MGMT into USER
+    reg_la3_oenb = reg_la3_iena = 0xFFFF3FFF; // [127:96]
+
+    // Flag start of the test
+    reg_mprj_datal = 0xFEEDFEED;
+    // reg_mprj_datah = 0x00000000;
+
+    // set control information to SHA256: sha_init, auto_ctrl, and start_ctrl
+    // *init bit starts sha_core, but only write to control register after reading in 512-bit input!
+    reg_la3_data = 0x00010C00;
+
+    // TODO could put in loop?
+    // aa55aa55
+    // deadbeef
+    // 55aa55aa
+    // f00ff00f
+    reg_mprj_slave = 0xaa55aa55;
+    // reg_mprj_slave = sha256_input[index];
+    // index++;
+    // sha_addr == ADDR_BLOCK0 && sha_we && sha_cs && sha_read_data == 0
+    // * removed because can not read register value
+    // reg_val = reg_la2_data;
+    // while ((reg_val & 0x00000FFF) != 0x310)
+    // {
+    //     num_trials++;
+    //     if (num_trials > NUM_TRIALS_LIMIT) {
+    //         // did not read input
+    //         testsPassed = testsPassed & 0;
+    //         reg_mprj_datal = 0xBAD0BAD0;
+    //         break;
+    //     }
+    //     reg_val = reg_la2_data;
+    // }
+    // num_trials = 0; // reset number of trials
+
+    // set control information to SHA256: disable start_ctrl
+    reg_la3_data = 0x00010800;
+
+    reg_mprj_slave = 0xdeadbeef;
+    // reg_mprj_slave = sha256_input[index];
+    // index++;
+    // sha_addr == ADDR_BLOCK1 && sha_we && sha_cs && sha_read_data == 0
+    // * removed because can not read register value
+    // reg_val = reg_la2_data;
+    // while ((reg_val & 0x00000FFF) != 0x311)
+    // {
+    //     num_trials++;
+    //     if (num_trials > NUM_TRIALS_LIMIT) {
+    //         // did not read input
+    //         testsPassed = testsPassed & 0;
+    //         reg_mprj_datal = 0xBAD0BAD0;
+    //         break;
+    //     }
+    //     reg_val = reg_la2_data;
+    // }
+    // num_trials = 0; // reset number of trials
+
+    reg_mprj_slave = 0x55aa55aa;
+    reg_mprj_slave = 0xf00ff00f;
+
+    reg_mprj_slave = 0xaa55aa55;
+    reg_mprj_slave = 0xdeadbeef;
+    reg_mprj_slave = 0x55aa55aa;
+    reg_mprj_slave = 0xf00ff00f;
+
+    reg_mprj_slave = 0xaa55aa55;
+    reg_mprj_slave = 0xdeadbeef;
+    reg_mprj_slave = 0x55aa55aa;
+    reg_mprj_slave = 0xf00ff00f;
+
+    reg_mprj_slave = 0xaa55aa55;
+    reg_mprj_slave = 0xdeadbeef;
+    reg_mprj_slave = 0x55aa55aa;
+    reg_mprj_slave = 0xf00ff00f;
+
+    // read valid output hash (digest)
+    hash_out0 = reg_mprj_slave;
+    // reg_val = reg_la2_data;
+    // if ((reg_val & 0x00000FFF) == 0x120)
+    // {
+    //     testsPassed = testsPassed & 1;
+    // }
+    // else
+    // {
+    //     testsPassed = testsPassed & 0;
+    //     reg_mprj_datal = 0xBAD0BAD0;
+    // }
+
+    hash_out1 = reg_mprj_slave;
+    // reg_val = reg_la2_data;
+    // if ((reg_val & 0x00000FFF) == 0x121)
+    // {
+    //     testsPassed = testsPassed & 1;
+    // }
+    // else
+    // {
+    //     testsPassed = testsPassed & 0;
+    //     reg_mprj_datal = 0xBAD0BAD0;
+    // }
+
+    hash_out2 = reg_mprj_slave;
+    // reg_val = reg_la2_data;
+    // if ((reg_val & 0x00000FFF) == 0x122)
+    // {
+    //     testsPassed = testsPassed & 1;
+    // }
+    // else
+    // {
+    //     testsPassed = testsPassed & 0;
+    //     reg_mprj_datal = 0xBAD0BAD0;
+    // }
+
+    hash_out3 = reg_mprj_slave;
+    // reg_val = reg_la2_data;
+    // if ((reg_val & 0x00000FFF) == 0x123)
+    // {
+    //     testsPassed = testsPassed & 1;
+    // }
+    // else
+    // {
+    //     testsPassed = testsPassed & 0;
+    //     reg_mprj_datal = 0xBAD0BAD0;
+    // }
+
+    hash_out4 = reg_mprj_slave;
+    // reg_val = reg_la2_data;
+    // if ((reg_val & 0x00000FFF) == 0x124)
+    // {
+    //     testsPassed = testsPassed & 1;
+    // }
+    // else
+    // {
+    //     testsPassed = testsPassed & 0;
+    //     reg_mprj_datal = 0xBAD0BAD0;
+    // }
+
+    if ((hash_out4 == 0xea2ebc79) && (hash_out3 == 0x35516705) && (hash_out2 == 0xde1e1467) &&
+        (hash_out1 == 0x31e55587) && (hash_out0 == 0xa0038725))
+    {
+        // Successfully ended test
+        reg_mprj_datal = 0xDEADDEAD;
+    }
+    else
+    {
+        reg_mprj_datal = 0xBAD0BAD0;
+    }
+}
diff --git a/verilog/dv/sha1_top_test2/sha1_top_test2_tb.v b/verilog/dv/sha1_top_test2/sha1_top_test2_tb.v
new file mode 100644
index 0000000..aee51e5
--- /dev/null
+++ b/verilog/dv/sha1_top_test2/sha1_top_test2_tb.v
@@ -0,0 +1,244 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+module sha1_top_test2_tb;
+	reg clock;
+	reg RSTB;
+	reg CSB;
+	reg power1, power2;
+	reg power3, power4;
+
+	wire gpio;
+	wire [37:0] mprj_io;
+	wire [7:0] mprj_io_0;
+	wire [15:0] checkbits;
+
+	// TODO assign check bits
+	assign checkbits = mprj_io[31:16];
+
+	assign mprj_io[3] = 1'b1;
+
+	// External clock is used by default.  Make this artificially fast for the
+	// simulation.  Normally this would be a slow clock and the digital PLL
+	// would be the fast clock.
+
+	always #12.5 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	`ifdef ENABLE_SDF
+		initial begin
+			$sdf_annotate("../../../sdf/user_proj_example.sdf", uut.mprj) ;
+			$sdf_annotate("../../../sdf/user_project_wrapper.sdf", uut.mprj.mprj) ;
+			$sdf_annotate("../../../mgmt_core_wrapper/sdf/DFFRAM.sdf", uut.soc.DFFRAM_0) ;
+			$sdf_annotate("../../../mgmt_core_wrapper/sdf/mgmt_core.sdf", uut.soc.core) ;
+			$sdf_annotate("../../../caravel/sdf/housekeeping.sdf", uut.housekeeping) ;
+			$sdf_annotate("../../../caravel/sdf/chip_io.sdf", uut.padframe) ;
+			$sdf_annotate("../../../caravel/sdf/mprj_logic_high.sdf", uut.mgmt_buffers.mprj_logic_high_inst) ;
+			$sdf_annotate("../../../caravel/sdf/mprj2_logic_high.sdf", uut.mgmt_buffers.mprj2_logic_high_inst) ;
+			$sdf_annotate("../../../caravel/sdf/mgmt_protect_hv.sdf", uut.mgmt_buffers.powergood_check) ;
+			$sdf_annotate("../../../caravel/sdf/mgmt_protect.sdf", uut.mgmt_buffers) ;
+			$sdf_annotate("../../../caravel/sdf/caravel_clocking.sdf", uut.clocking) ;
+			$sdf_annotate("../../../caravel/sdf/digital_pll.sdf", uut.pll) ;
+			$sdf_annotate("../../../caravel/sdf/xres_buf.sdf", uut.rstb_level) ;
+			$sdf_annotate("../../../caravel/sdf/user_id_programming.sdf", uut.user_id_value) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[0] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[1] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[0] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[1] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[2] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[0] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[1] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[2] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[3] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[4] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[5] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[6] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[7] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[8] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[9] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[10] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[0] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[1] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[2] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[3] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[4] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[5] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[0] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[1] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[2] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[3] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[4] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[5] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[6] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[7] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[8] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[9] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[10] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[11] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[12] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[13] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[14] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[15] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_0[0] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_0[1] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[0] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[1] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[2] ) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_5) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_6) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_7) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_8) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_9) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_10) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_11) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_12) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_13) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_14) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_15) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_16) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_17) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_18) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_19) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_20) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_21) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_22) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_23) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_24) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_25) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_26) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_27) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_28) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_29) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_30) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_31) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_32) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_33) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_34) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_35) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_36) ;
+			$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_37) ;
+		end
+	`endif 
+
+	initial begin
+		$dumpfile("sha1_top_test2.vcd");
+		$dumpvars(0, sha1_top_test2_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (100) begin
+			repeat (1000) @(posedge clock);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, SHA1 Test 2 (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, SHA1 Test 2 (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+
+	// checking for: flag start of test bits
+	initial begin
+	  wait(checkbits == 16'hFEED);
+		$display("Monitor: SHA1 Test 2 Started");
+		wait(checkbits == 16'hDEAD);
+		`ifdef GL
+			$display("Monitor: SHA1 Test 2 (GL) Passed");
+		`else
+			$display("Monitor: SHA1 Test 2 (RTL) Passed");
+		`endif
+	    $finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		CSB  <= 1'b1;		// Force CSB high
+		#2000;
+		RSTB <= 1'b1;		// Release reset
+		#100000;
+		CSB = 1'b0;			// CSB can be released
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire VDD3V3 = power1;
+	wire VDD1V8 = power2;
+	wire USER_VDD3V3 = power3;
+	wire USER_VDD1V8 = power4;
+	wire VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vddio_2  (VDD3V3),
+		.vssio	  (VSS),
+		.vssio_2  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda1_2  (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa1_2  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock    (clock),
+		.gpio     (gpio),
+		.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("sha1_top_test2.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+endmodule
+`default_nettype wire
diff --git a/verilog/rtl/sha1.v b/verilog/rtl/sha1.v
index ac8e940..80a387b 100644
--- a/verilog/rtl/sha1.v
+++ b/verilog/rtl/sha1.v
@@ -206,12 +206,6 @@
             end // if (write_read)
           else
             begin
-              if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK15))
-                tmp_read_data = block_reg[address[3 : 0]];
-
-              if ((address >= ADDR_DIGEST0) && (address <= ADDR_DIGEST4))
-                tmp_read_data = digest_reg[(4 - (address - ADDR_DIGEST0)) * 32 +: 32];
-
               case (address)
                 // Read operations.
                 ADDR_NAME0:
@@ -231,7 +225,13 @@
 
                 default:
                   begin
-                    tmp_error = 1'h1;
+                    if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK15)) begin
+                      tmp_read_data = block_reg[address[3 : 0]];
+                    end else if ((address >= ADDR_DIGEST0) && (address <= ADDR_DIGEST4)) begin
+                      tmp_read_data = digest_reg[(4 - (address - ADDR_DIGEST0)) * 32 +: 32];
+                    end else begin
+                      tmp_error = 1'h1;
+                    end
                   end
               endcase // case (addr)
             end
diff --git a/verilog/rtl/sha1_top.v b/verilog/rtl/sha1_top.v
index 7c306cf..61dcb81 100644
--- a/verilog/rtl/sha1_top.v
+++ b/verilog/rtl/sha1_top.v
@@ -215,7 +215,7 @@
   wire sha_we;
   reg [7:0] reg_sha_address;
 
-  // sha_mode, sha_next, sha_init. Map to ADDR_CTRL register [2:0]
+  // sha_next, sha_init. Map to ADDR_CTRL register [1:0]
   wire [1:0] sha_ctrl_bits;
   wire read_status_flag;