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# Created by write_sdc
# Mon Dec  5 11:05:39 2022
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current_design trainable_nn
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# Timing Constraints
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create_clock -name wb_clk_i -period 200.0000 [get_ports {wb_clk_i}]
set_clock_transition 0.1500 [get_clocks {wb_clk_i}]
set_clock_uncertainty 0.2500 wb_clk_i
set_propagated_clock [get_clocks {wb_clk_i}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[0]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[10]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[11]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[12]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[13]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[14]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[15]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[16]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[17]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[18]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[19]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[1]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[20]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[21]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[22]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[23]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[24]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[25]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[26]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[27]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[28]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[29]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[2]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[30]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[31]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[32]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[33]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[34]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[35]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[36]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[37]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[3]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[4]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[5]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[6]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[7]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[8]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[9]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[0]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[100]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[101]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[102]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[103]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[104]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[105]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[106]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[107]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[108]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[109]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[10]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[110]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[111]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[112]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[113]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[114]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[115]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[116]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[117]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[118]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[119]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[11]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[120]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[121]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[122]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[123]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[124]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[125]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[126]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[127]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[12]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[13]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[14]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[15]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[16]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[17]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[18]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[19]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[1]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[20]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[21]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[22]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[23]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[24]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[25]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[26]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[27]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[28]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[29]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[2]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[30]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[31]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[32]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[33]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[34]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[35]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[36]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[37]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[38]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[39]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[3]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[40]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[41]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[42]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[43]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[44]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[45]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[46]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[47]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[48]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[49]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[4]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[50]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[51]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[52]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[53]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[54]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[55]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[56]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[57]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[58]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[59]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[5]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[60]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[61]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[62]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[63]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[64]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[65]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[66]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[67]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[68]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[69]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[6]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[70]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[71]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[72]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[73]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[74]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[75]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[76]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[77]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[78]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[79]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[7]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[80]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[81]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[82]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[83]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[84]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[85]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[86]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[87]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[88]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[89]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[8]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[90]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[91]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[92]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[93]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[94]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[95]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[96]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[97]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[98]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[99]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[9]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[0]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[100]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[101]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[102]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[103]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[104]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[105]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[106]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[107]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[108]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[109]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[10]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[110]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[111]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[112]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[113]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[114]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[115]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[116]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[117]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[118]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[119]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[11]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[120]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[121]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[122]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[123]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[124]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[125]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[126]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[127]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[12]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[13]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[14]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[15]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[16]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[17]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[18]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[19]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[1]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[20]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[21]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[22]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[23]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[24]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[25]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[26]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[27]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[28]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[29]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[2]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[30]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[31]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[32]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[33]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[34]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[35]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[36]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[37]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[38]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[39]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[3]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[40]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[41]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[42]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[43]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[44]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[45]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[46]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[47]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[48]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[49]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[4]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[50]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[51]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[52]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[53]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[54]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[55]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[56]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[57]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[58]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[59]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[5]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[60]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[61]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[62]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[63]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[64]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[65]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[66]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[67]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[68]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[69]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[6]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[70]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[71]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[72]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[73]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[74]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[75]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[76]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[77]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[78]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[79]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[7]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[80]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[81]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[82]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[83]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[84]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[85]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[86]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[87]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[88]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[89]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[8]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[90]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[91]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[92]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[93]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[94]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[95]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[96]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[97]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[98]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[99]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[9]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_rst_i}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[0]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[10]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[11]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[12]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[13]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[14]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[15]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[16]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[17]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[18]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[19]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[1]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[20]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[21]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[22]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[23]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[24]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[25]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[26]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[27]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[28]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[29]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[2]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[30]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[31]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[3]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[4]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[5]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[6]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[7]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[8]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[9]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_cyc_i}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[0]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[10]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[11]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[12]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[13]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[14]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[15]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[16]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[17]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[18]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[19]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[1]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[20]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[21]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[22]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[23]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[24]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[25]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[26]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[27]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[28]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[29]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[2]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[30]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[31]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[3]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[4]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[5]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[6]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[7]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[8]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[9]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_sel_i[0]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_sel_i[1]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_sel_i[2]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_sel_i[3]}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_stb_i}]
set_input_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_we_i}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[0]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[10]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[11]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[12]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[13]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[14]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[15]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[16]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[17]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[18]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[19]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[1]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[20]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[21]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[22]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[23]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[24]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[25]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[26]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[27]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[28]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[29]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[2]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[30]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[31]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[32]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[33]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[34]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[35]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[36]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[37]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[3]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[4]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[5]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[6]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[7]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[8]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[9]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[0]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[10]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[11]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[12]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[13]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[14]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[15]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[16]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[17]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[18]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[19]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[1]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[20]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[21]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[22]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[23]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[24]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[25]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[26]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[27]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[28]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[29]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[2]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[30]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[31]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[32]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[33]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[34]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[35]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[36]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[37]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[3]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[4]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[5]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[6]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[7]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[8]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[9]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[0]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[1]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[2]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[0]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[100]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[101]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[102]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[103]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[104]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[105]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[106]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[107]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[108]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[109]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[10]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[110]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[111]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[112]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[113]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[114]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[115]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[116]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[117]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[118]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[119]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[11]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[120]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[121]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[122]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[123]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[124]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[125]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[126]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[127]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[12]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[13]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[14]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[15]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[16]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[17]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[18]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[19]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[1]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[20]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[21]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[22]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[23]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[24]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[25]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[26]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[27]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[28]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[29]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[2]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[30]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[31]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[32]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[33]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[34]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[35]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[36]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[37]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[38]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[39]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[3]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[40]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[41]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[42]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[43]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[44]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[45]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[46]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[47]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[48]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[49]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[4]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[50]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[51]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[52]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[53]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[54]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[55]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[56]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[57]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[58]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[59]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[5]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[60]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[61]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[62]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[63]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[64]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[65]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[66]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[67]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[68]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[69]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[6]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[70]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[71]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[72]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[73]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[74]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[75]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[76]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[77]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[78]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[79]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[7]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[80]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[81]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[82]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[83]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[84]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[85]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[86]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[87]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[88]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[89]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[8]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[90]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[91]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[92]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[93]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[94]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[95]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[96]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[97]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[98]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[99]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[9]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_ack_o}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[0]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[10]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[11]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[12]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[13]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[14]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[15]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[16]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[17]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[18]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[19]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[1]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[20]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[21]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[22]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[23]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[24]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[25]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[26]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[27]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[28]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[29]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[2]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[30]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[31]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[3]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[4]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[5]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[6]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[7]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[8]}]
set_output_delay 40.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[9]}]
###############################################################################
# Environment
###############################################################################
set_load -pin_load 0.0334 [get_ports {wbs_ack_o}]
set_load -pin_load 0.0334 [get_ports {io_oeb[37]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[36]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[35]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[34]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[33]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[32]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[31]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[30]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[29]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[28]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[27]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[26]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[25]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[24]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[23]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[22]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[21]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[20]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[19]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[18]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[17]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[16]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[15]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[14]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[13]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[12]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[11]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[10]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[9]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[8]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[7]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[6]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[5]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[4]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[3]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[2]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[1]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[0]}]
set_load -pin_load 0.0334 [get_ports {io_out[37]}]
set_load -pin_load 0.0334 [get_ports {io_out[36]}]
set_load -pin_load 0.0334 [get_ports {io_out[35]}]
set_load -pin_load 0.0334 [get_ports {io_out[34]}]
set_load -pin_load 0.0334 [get_ports {io_out[33]}]
set_load -pin_load 0.0334 [get_ports {io_out[32]}]
set_load -pin_load 0.0334 [get_ports {io_out[31]}]
set_load -pin_load 0.0334 [get_ports {io_out[30]}]
set_load -pin_load 0.0334 [get_ports {io_out[29]}]
set_load -pin_load 0.0334 [get_ports {io_out[28]}]
set_load -pin_load 0.0334 [get_ports {io_out[27]}]
set_load -pin_load 0.0334 [get_ports {io_out[26]}]
set_load -pin_load 0.0334 [get_ports {io_out[25]}]
set_load -pin_load 0.0334 [get_ports {io_out[24]}]
set_load -pin_load 0.0334 [get_ports {io_out[23]}]
set_load -pin_load 0.0334 [get_ports {io_out[22]}]
set_load -pin_load 0.0334 [get_ports {io_out[21]}]
set_load -pin_load 0.0334 [get_ports {io_out[20]}]
set_load -pin_load 0.0334 [get_ports {io_out[19]}]
set_load -pin_load 0.0334 [get_ports {io_out[18]}]
set_load -pin_load 0.0334 [get_ports {io_out[17]}]
set_load -pin_load 0.0334 [get_ports {io_out[16]}]
set_load -pin_load 0.0334 [get_ports {io_out[15]}]
set_load -pin_load 0.0334 [get_ports {io_out[14]}]
set_load -pin_load 0.0334 [get_ports {io_out[13]}]
set_load -pin_load 0.0334 [get_ports {io_out[12]}]
set_load -pin_load 0.0334 [get_ports {io_out[11]}]
set_load -pin_load 0.0334 [get_ports {io_out[10]}]
set_load -pin_load 0.0334 [get_ports {io_out[9]}]
set_load -pin_load 0.0334 [get_ports {io_out[8]}]
set_load -pin_load 0.0334 [get_ports {io_out[7]}]
set_load -pin_load 0.0334 [get_ports {io_out[6]}]
set_load -pin_load 0.0334 [get_ports {io_out[5]}]
set_load -pin_load 0.0334 [get_ports {io_out[4]}]
set_load -pin_load 0.0334 [get_ports {io_out[3]}]
set_load -pin_load 0.0334 [get_ports {io_out[2]}]
set_load -pin_load 0.0334 [get_ports {io_out[1]}]
set_load -pin_load 0.0334 [get_ports {io_out[0]}]
set_load -pin_load 0.0334 [get_ports {irq[2]}]
set_load -pin_load 0.0334 [get_ports {irq[1]}]
set_load -pin_load 0.0334 [get_ports {irq[0]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[127]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[126]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[125]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[124]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[123]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[122]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[121]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[120]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[119]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[118]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[117]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[116]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[115]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[114]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[113]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[112]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[111]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[110]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[109]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[108]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[107]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[106]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[105]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[104]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[103]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[102]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[101]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[100]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[99]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[98]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[97]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[96]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[95]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[94]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[93]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[92]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[91]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[90]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[89]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[88]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[87]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[86]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[85]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[84]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[83]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[82]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[81]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[80]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[79]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[78]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[77]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[76]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[75]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[74]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[73]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[72]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[71]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[70]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[69]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[68]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[67]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[66]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[65]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[64]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[63]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[62]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[61]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[60]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[59]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[58]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[57]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[56]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[55]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[54]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[53]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[52]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[51]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[50]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[49]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[48]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[47]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[46]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[45]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[44]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[43]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[42]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[41]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[40]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[39]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[38]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[37]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[36]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[35]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[34]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[33]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[32]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[31]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[30]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[29]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[28]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[27]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[26]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[25]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[24]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[23]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[22]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[21]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[20]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[19]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[18]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[17]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[16]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[15]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[14]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[13]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[12]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[11]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[10]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[9]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[8]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[7]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[6]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[5]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[4]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[3]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[2]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[1]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[0]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[31]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[30]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[29]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[28]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[27]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[26]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[25]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[24]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[23]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[22]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[21]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[20]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[19]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[18]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[17]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[16]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[15]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[14]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[13]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[12]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[11]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[10]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[9]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[8]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[7]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[6]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[5]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[4]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[3]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[2]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[1]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_clk_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_rst_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_cyc_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_stb_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_we_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[37]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[36]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[35]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[34]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[33]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[32]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[127]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[126]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[125]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[124]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[123]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[122]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[121]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[120]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[119]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[118]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[117]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[116]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[115]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[114]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[113]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[112]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[111]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[110]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[109]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[108]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[107]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[106]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[105]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[104]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[103]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[102]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[101]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[100]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[99]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[98]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[97]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[96]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[95]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[94]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[93]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[92]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[91]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[90]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[89]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[88]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[87]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[86]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[85]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[84]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[83]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[82]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[81]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[80]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[79]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[78]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[77]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[76]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[75]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[74]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[73]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[72]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[71]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[70]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[69]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[68]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[67]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[66]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[65]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[64]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[63]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[62]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[61]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[60]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[59]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[58]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[57]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[56]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[55]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[54]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[53]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[52]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[51]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[50]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[49]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[48]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[47]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[46]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[45]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[44]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[43]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[42]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[41]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[40]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[39]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[38]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[37]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[36]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[35]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[34]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[33]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[32]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[127]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[126]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[125]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[124]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[123]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[122]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[121]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[120]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[119]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[118]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[117]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[116]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[115]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[114]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[113]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[112]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[111]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[110]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[109]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[108]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[107]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[106]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[105]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[104]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[103]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[102]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[101]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[100]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[99]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[98]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[97]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[96]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[95]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[94]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[93]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[92]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[91]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[90]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[89]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[88]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[87]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[86]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[85]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[84]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[83]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[82]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[81]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[80]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[79]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[78]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[77]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[76]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[75]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[74]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[73]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[72]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[71]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[70]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[69]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[68]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[67]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[66]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[65]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[64]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[63]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[62]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[61]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[60]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[59]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[58]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[57]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[56]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[55]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[54]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[53]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[52]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[51]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[50]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[49]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[48]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[47]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[46]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[45]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[44]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[43]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[42]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[41]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[40]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[39]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[38]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[37]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[36]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[35]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[34]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[33]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[32]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[0]}]
set_timing_derate -early 0.9500
set_timing_derate -late 1.0500
###############################################################################
# Design Rules
###############################################################################
set_max_fanout 10.0000 [current_design]