)]}'
{
  "commit": "2cdf3861d883c000d682da80d89aeabb3f79ada0",
  "tree": "8f976e0a2333288de05295db4d10c4860ec6634b",
  "parents": [
    "7116f5a89326fcf44e9b3c5bf552f5394694db17"
  ],
  "author": {
    "name": "Soumil Jain",
    "email": "soumil@capella.ucsd.edu",
    "time": "Fri Sep 09 17:59:24 2022 -0700"
  },
  "committer": {
    "name": "Soumil Jain",
    "email": "soumil@capella.ucsd.edu",
    "time": "Fri Sep 09 17:59:24 2022 -0700"
  },
  "message": "updated gds with 5x5um mimcaps\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "a62057ca195a15ea9db0abf9b35a1106bd3fc76e",
      "old_mode": 33188,
      "old_path": "gds/user_analog_project_wrapper.gds",
      "new_id": "b406aa34b6b15e9130cd178f67a43a4c5daf95af",
      "new_mode": 33188,
      "new_path": "gds/user_analog_project_wrapper.gds"
    },
    {
      "type": "delete",
      "old_id": "66697643a2be6605912255d39960fb9aafbeb23d",
      "old_mode": 33188,
      "old_path": "verilog/rtl/.reram_crossbar.v.swp",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    }
  ]
}