)]}'
{
  "commit": "a84af2086437a502f368bf115cb09525168e7f7f",
  "tree": "1c94f3c6d38137d07141c3565f85fd779df3e055",
  "parents": [
    "e9b52ee2057db66118c00f243dfb1a572da32dfc"
  ],
  "author": {
    "name": "Staf Verhaegen",
    "email": "staf@fibraservi.eu",
    "time": "Fri Jun 03 10:37:34 2022 +0200"
  },
  "committer": {
    "name": "Staf Verhaegen",
    "email": "staf@fibraservi.eu",
    "time": "Fri Jun 03 10:37:34 2022 +0200"
  },
  "message": "Update cell design using less wide transistors.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "b0ddb51658b19828df89a30574efaf4606c3485c",
      "old_mode": 33188,
      "old_path": "doitcode/sram.py",
      "new_id": "afcdc78780543925508dc9af4dc5918a3e4fcd98",
      "new_mode": 33188,
      "new_path": "doitcode/sram.py"
    },
    {
      "type": "modify",
      "old_id": "551aec6f7407fcb9ad9b85b494d37667c021186e",
      "old_mode": 33188,
      "old_path": "gds/user_analog_project_wrapper.gds.gz",
      "new_id": "e0c643fdec55aa0bfe7390f25dd74aeea0c7781e",
      "new_mode": 33188,
      "new_path": "gds/user_analog_project_wrapper.gds.gz"
    }
  ]
}