diff --git a/env/spef-mapping.tcl b/env/spef-mapping.tcl
index ce5a1ec..a5f39fd 100644
--- a/env/spef-mapping.tcl
+++ b/env/spef-mapping.tcl
@@ -8,5 +8,6 @@
 set spef_mapping(mprj/\u_riscv_top.i_core_top_0) "$::env(PROJECT_ROOT)/signoff/ycr_core_top/openlane-signoff/spef/ycr_core_top.$::env(RCX_CORNER).spef"
 set spef_mapping(mprj/\u_riscv_top.u_connect) "$::env(PROJECT_ROOT)/signoff/ycr_iconnect/openlane-signoff/spef/ycr_iconnect.$::env(RCX_CORNER).spef"
 set spef_mapping(mprj/\u_riscv_top.u_intf) "$::env(PROJECT_ROOT)/signoff/ycr_intf/openlane-signoff/spef/ycr_intf.$::env(RCX_CORNER).spef"
+set spef_mapping(mprj/u_rp_south) "$::env(PROJECT_ROOT)/signoff/bus_rep_south/openlane-signoff/spef/bus_rep_south.$::env(RCX_CORNER).spef"
 set spef_mapping(mprj/u_uart_i2c_usb_spi) "$::env(PROJECT_ROOT)/signoff/uart_i2c_usb_spi_top/openlane-signoff/spef/uart_i2c_usb_spi_top.$::env(RCX_CORNER).spef"
 set spef_mapping(mprj/u_wb_host) "$::env(PROJECT_ROOT)/signoff/wb_host/openlane-signoff/spef/wb_host.$::env(RCX_CORNER).spef"
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
index 1cb3c1d..9afeacf 100644
--- a/gds/user_project_wrapper.gds.gz
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/lef/user_project_wrapper.lef.gz b/lef/user_project_wrapper.lef.gz
index 1bdea93..f318870 100644
--- a/lef/user_project_wrapper.lef.gz
+++ b/lef/user_project_wrapper.lef.gz
Binary files differ
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 26d4cc6..25eab79 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -189,9 +189,9 @@
 	u_riscv_top.u_connect       vccd1 vssd1 VPWR  VGND, \
 	u_riscv_top.u_intf          vccd1 vssd1 vccd1 vssd1,\
 	u_4x8bit_dac                vdda1 vssa1 vccd1 vssd1,\
-	u_aes                       vdda1 vssa1 vccd1 vssd1,\
-	u_fpu                       vdda1 vssa1 vccd1 vssd1,\
-	u_rp_south                  vdda1 vssa1 vccd1 vssd1
+	u_aes                       vccd1 vssd1 vccd1 vssd1,\
+	u_fpu                       vccd1 vssd1 vccd1 vssd1,\
+	u_rp_south                  vccd1 vssd1 vccd1 vssd1
       	"
 
 
diff --git a/sdc/user_project_wrapper.sdc b/sdc/user_project_wrapper.sdc
index 16d5167..fddc749 100644
--- a/sdc/user_project_wrapper.sdc
+++ b/sdc/user_project_wrapper.sdc
@@ -1,6 +1,6 @@
 ###############################################################################
 # Created by write_sdc
-# Sun Nov 27 17:14:15 2022
+# Mon Nov 28 11:11:31 2022
 ###############################################################################
 current_design user_project_wrapper
 ###############################################################################
diff --git a/sdc/wb_host.sdc b/sdc/wb_host.sdc
index 76929a7..9c35c74 100644
--- a/sdc/wb_host.sdc
+++ b/sdc/wb_host.sdc
@@ -1,6 +1,6 @@
 ###############################################################################
 # Created by write_sdc
-# Sun Nov 27 11:39:42 2022
+# Mon Nov 28 06:54:23 2022
 ###############################################################################
 current_design wb_host
 ###############################################################################
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index 3a02890..3531d3e 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -19,19 +19,19 @@
 .SUFFIXES:
 .SILENT: clean all
 
-PATTERNS = user_basic user_uart user_uart1 user_risc_boot user_qspi user_sspi user_i2cm user_usb user_gpio user_aes user_spi_isp user_timer user_uart_master  user_sram_exec user_cache_bypass user_pwm user_sema risc_boot uart_master_test1 uart_master_test2 wb_port arduino_arrays arduino_digital_port_control arduino_i2c_scaner arduino_risc_boot arduino_timer_intr arduino_ascii_table arduino_gpio_intr arduino_i2c_wr_rd arduino_string arduino_ws281x arduino_character_analysis arduino_hello_world arduino_multi_serial arduino_switchCase2 user_aes_core user_fpu_core
+PATTERNS = user_uart user_uart1 user_risc_boot user_qspi user_sspi user_i2cm user_usb user_gpio user_basic user_aes user_spi_isp user_timer user_uart_master  user_sram_exec user_cache_bypass user_pwm user_sema risc_boot uart_master_test1 uart_master_test2 wb_port arduino_arrays arduino_digital_port_control arduino_i2c_scaner arduino_risc_boot arduino_timer_intr arduino_ascii_table arduino_gpio_intr arduino_i2c_wr_rd arduino_string arduino_ws281x arduino_character_analysis arduino_hello_world arduino_multi_serial arduino_switchCase2 user_aes_core user_fpu_core
 
 all:  ${PATTERNS}
 	echo "################# RTL Test case Summary #####################" > regression.rpt
 	xterm -e /usr/bin/watch -n 25 /bin/cat regression.rpt & 
-	for i in ${PATTERNS}; do \
-		( cd $$i && make | tee run.rtl.log && grep Monitor run.rtl.log | grep $$i >> ../regression.rpt) ; \
-	done
-	#echo "################# GL Test case Summary #####################" >> regression.rpt
-	#\rm -rf */*.vvp
 	#for i in ${PATTERNS}; do \
-	#	( cd $$i && make SIM=GL | tee run.gl.log && grep Monitor run.gl.log | grep $$i >> ../regression.rpt) ; \
+	#	( cd $$i && make | tee run.rtl.log && grep Monitor run.rtl.log | grep $$i >> ../regression.rpt) ; \
 	#done
+	echo "################# GL Test case Summary #####################" >> regression.rpt
+	\rm -rf */*.vvp
+	for i in ${PATTERNS}; do \
+		( cd $$i && make SIM=GL | tee run.gl.log && grep Monitor run.gl.log | grep $$i >> ../regression.rpt) ; \
+	done
 	echo "################# End of Test case Summary #####################" >> regression.rpt
 
 DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
diff --git a/verilog/dv/common/agents/user_tasks.sv b/verilog/dv/common/agents/user_tasks.sv
index 6bda236..84f98d1 100644
--- a/verilog/dv/common/agents/user_tasks.sv
+++ b/verilog/dv/common/agents/user_tasks.sv
@@ -90,7 +90,11 @@
 begin
    // Run in Fast Sim Mode
    `ifdef GL
-       force u_top.u_wb_host._10673_.Q= 1'b1; 
+       // Note During wb_host resynth this FF is changes,
+       // Keep cross-check during Gate Sim
+       force u_top.u_wb_host._09642_.Q= 1'b1; 
+       //force u_top.u_wb_host.u_reg.u_fastsim_buf.u_buf.X = 1'b1; 
+       //force u_top.u_wb_host.u_reg.cfg_fast_sim = 1'b1; 
    `else
        force u_top.u_wb_host.u_reg.u_fastsim_buf.X = 1'b1; 
     `endif
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
index 2865bda..401dc92 100644
--- a/verilog/dv/user_basic/user_basic_tb.v
+++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -196,11 +196,12 @@
 	   	$dumpfile("simx.vcd");
 	   	$dumpvars(1, `TB_TOP);
 	   	$dumpvars(1, `TB_TOP.u_top);
-	   	$dumpvars(0, `TB_TOP.u_top.u_pll);
+	   	//$dumpvars(0, `TB_TOP.u_top.u_pll);
 	   	$dumpvars(0, `TB_TOP.u_top.u_wb_host);
 	   	//$dumpvars(0, `TB_TOP.u_top.u_intercon);
 	   	//$dumpvars(1, `TB_TOP.u_top.u_intercon);
 	   	$dumpvars(0, `TB_TOP.u_top.u_pinmux);
+	   	$dumpvars(0, `TB_TOP.u_top.u_rp_south);
 	   end
        `endif
 
@@ -218,6 +219,7 @@
    test_fail=0;
    fork
    begin
+
        $display("##########################################################");
        $display("Step-1, Checking the Strap Loading");
        test_id = 1;
@@ -668,7 +670,7 @@
 input real exp_period;
 begin
    `ifdef GL
-   force clock_mon = u_top.u_wb_host._09635_.Q;
+   force clock_mon = u_top.u_wb_host._10399_.Q;
     `else
    force clock_mon = u_top.u_wb_host.u_uart2wb.u_core.line_clk_16x;
     `endif
diff --git a/verilog/gl/user_project_wrapper.v.gz b/verilog/gl/user_project_wrapper.v.gz
index 8b09148..9eae583 100644
--- a/verilog/gl/user_project_wrapper.v.gz
+++ b/verilog/gl/user_project_wrapper.v.gz
Binary files differ
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project
index bf5b965..f46170f 100644
--- a/verilog/includes/includes.gl.caravel_user_project
+++ b/verilog/includes/includes.gl.caravel_user_project
@@ -220,6 +220,7 @@
 
 $(USER_PROJECT_VERILOG)/gl/aes_top.v
 $(USER_PROJECT_VERILOG)/gl/fpu_wrapper.v
+$(USER_PROJECT_VERILOG)/gl/bus_rep_south.v
 
 -v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/dg_pll.v
 
diff --git a/verilog/rtl/bus_repeater.sv b/verilog/rtl/bus_repeater.sv
index aa11747..d50fa9f 100644
--- a/verilog/rtl/bus_repeater.sv
+++ b/verilog/rtl/bus_repeater.sv
@@ -274,8 +274,8 @@
 `endif
       ) u_rp_south(
 `ifdef USE_POWER_PINS
-    .vccd1                 (vdda1                  ),
-    .vssd1                 (vssa1                  ),
+    .vccd1                 (vccd1                  ),
+    .vssd1                 (vssd1                  ),
 `endif
     .ch_in (ch_in_south),
     .ch_out (ch_out_south)
diff --git a/verilog/rtl/user_params.svh b/verilog/rtl/user_params.svh
index ec2e9a5..58da5bf 100644
--- a/verilog/rtl/user_params.svh
+++ b/verilog/rtl/user_params.svh
@@ -4,9 +4,9 @@
 // ASCI Representation of RISC = 32'h8273_8343
 parameter CHIP_SIGNATURE = 32'h8273_8343;
 // Software Reg-1, Release date: <DAY><MONTH><YEAR>
-parameter CHIP_RELEASE_DATE = 32'h2711_2022;
+parameter CHIP_RELEASE_DATE = 32'h2811_2022;
 // Software Reg-2: Poject Revison 5.1 = 0005200
-parameter CHIP_REVISION   = 32'h0006_0000;
+parameter CHIP_REVISION   = 32'h0006_1000;
 
 parameter CLK_SKEW1_RESET_VAL = 32'b0000_0000_0100_1000_1000_1110_1000_0100;
 parameter CLK_SKEW2_RESET_VAL = 32'b1000_1000_1000_1000_1000_0100_0111_1110;
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 84b85d3..54a4b24 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -294,7 +294,10 @@
 ////         cpu_clk will be feed through wb_interconnect for     ////
 ////         buffering purpose                                    ////
 ////    6.0  Nov 27, 2022, Dinesh A                               ////
-////         MPW-7 Timing clean setup
+////         MPW-7 Timing clean setup                             ////
+////    6.1  Nov 28, 2022, Dinesh A                               ////
+////        Power Hook up connectivity issue for                  ////
+////        aes,fpu,bus repeater is fixed                         ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
 //// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
@@ -1243,8 +1246,8 @@
 *************************************************/
 aes_top u_aes (
 `ifdef USE_POWER_PINS
-    .vccd1                 (vdda1            ),
-    .vssd1                 (vssa1            ),
+    .vccd1                 (vccd1            ),
+    .vssd1                 (vssd1            ),
 `endif
 
     .mclk                  (cpu_clk_aes      ),
@@ -1269,8 +1272,8 @@
 *************************************************/
 fpu_wrapper u_fpu (
 `ifdef USE_POWER_PINS
-    .vccd1                 (vdda1            ),
-    .vssd1                 (vssa1            ),
+    .vccd1                 (vccd1            ),
+    .vssd1                 (vssd1            ),
 `endif
 
     .mclk                  (cpu_clk_fpu      ),
@@ -1611,7 +1614,7 @@
           .strap_sticky            (strap_sticky            ),
 	      .strap_uartm             (strap_uartm             ),
 
-          .user_clock1             (wb_clk_i                ),
+          .user_clock1             (wb_clk_int_i            ),
           .user_clock2             (user_clock2             ),
           .int_pll_clock           (int_pll_clock           ),
           .xtal_clk                (xtal_clk                ),